Using jit(/home/alahay01/dotnet/runtime_andchains/artifacts/bin/coreclr/Linux.arm64.Checked/./libclrjit.so) with input (/home/alahay01/dotnet/runtime_andchains/artifacts/spmi/repro.libraries.crossgen2.Linux.arm64.checked.1/repro-18888.mc) indexCount=-1 () Jit startup took 2.857761ms ****** START compiling System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) (MethodHash=1ee688ab) Generating code for Unix arm64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: No matching PGO data OPTIONS: Jit invoked for ngen IL to import: IL_0000 03 ldarg.1 IL_0001 28 31 18 00 06 call 0x6001831 IL_0006 16 ldc.i4.0 IL_0007 13 07 stloc.s 0x7 IL_0009 03 ldarg.1 IL_000a 28 32 18 00 06 call 0x6001832 IL_000f 13 0d stloc.s 0xD IL_0011 04 ldarg.2 IL_0012 11 0d ldloc.s 0xD IL_0014 47 ldind.u1 IL_0015 2c 0e brfalse.s 14 (IL_0025) IL_0017 03 ldarg.1 IL_0018 7b d3 04 00 04 ldfld 0x40004D3 IL_001d 2d 03 brtrue.s 3 (IL_0022) IL_001f 16 ldc.i4.0 IL_0020 2b 04 br.s 4 (IL_0026) IL_0022 17 ldc.i4.1 IL_0023 2b 01 br.s 1 (IL_0026) IL_0025 18 ldc.i4.2 IL_0026 28 98 17 00 06 call 0x6001798 IL_002b 13 0b stloc.s 0xB IL_002d 16 ldc.i4.0 IL_002e 0a stloc.0 IL_002f 15 ldc.i4.m1 IL_0030 0b stloc.1 IL_0031 20 ff ff ff 7f ldc.i4 0x7FFFFFFF IL_0036 0c stloc.2 IL_0037 16 ldc.i4.0 IL_0038 0d stloc.3 IL_0039 16 ldc.i4.0 IL_003a 13 05 stloc.s 0x5 IL_003c 15 ldc.i4.m1 IL_003d 13 06 stloc.s 0x6 IL_003f 16 ldc.i4.0 IL_0040 13 08 stloc.s 0x8 IL_0042 16 ldc.i4.0 IL_0043 13 09 stloc.s 0x9 IL_0045 11 0b ldloc.s 0xB IL_0047 13 0c stloc.s 0xC IL_0049 04 ldarg.2 IL_004a 28 fc 00 00 2b call 0x2B0000FC IL_004f 13 13 stloc.s 0x13 IL_0051 11 13 ldloc.s 0x13 IL_0053 e0 conv.u IL_0054 13 12 stloc.s 0x12 IL_0056 38 a9 01 00 00 br 425 (IL_0204) IL_005b 11 0e ldloc.s 0xE IL_005d 1f 45 ldc.i4.s 0x45 IL_005f 35 4e bgt.un.s 78 (IL_00af) IL_0061 11 0e ldloc.s 0xE IL_0063 1f 22 ldc.i4.s 0x22 IL_0065 59 sub IL_0066 45 06 00 00 00 bf 00 00 00 4c 00 00 00 81 01 00 00 a9 00 00 00 81 01 00 00 bf 00 00 00 switch IL_0083 11 0e ldloc.s 0xE IL_0085 1f 2c ldc.i4.s 0x2C IL_0087 59 sub IL_0088 45 05 00 00 00 5a 00 00 00 63 01 00 00 4c 00 00 00 63 01 00 00 37 00 00 00 switch IL_00a1 11 0e ldloc.s 0xE IL_00a3 1f 45 ldc.i4.s 0x45 IL_00a5 3b ec 00 00 00 beq 236 (IL_0196) IL_00aa 38 55 01 00 00 br 341 (IL_0204) IL_00af 11 0e ldloc.s 0xE IL_00b1 1f 5c ldc.i4.s 0x5C IL_00b3 3b bd 00 00 00 beq 189 (IL_0175) IL_00b8 11 0e ldloc.s 0xE IL_00ba 1f 65 ldc.i4.s 0x65 IL_00bc 3b d5 00 00 00 beq 213 (IL_0196) IL_00c1 11 0e ldloc.s 0xE IL_00c3 20 30 20 00 00 ldc.i4 0x2030 IL_00c8 2e 6d beq.s 109 (IL_0137) IL_00ca 38 35 01 00 00 br 309 (IL_0204) IL_00cf 06 ldloc.0 IL_00d0 17 ldc.i4.1 IL_00d1 58 add IL_00d2 0a stloc.0 IL_00d3 38 2c 01 00 00 br 300 (IL_0204) IL_00d8 08 ldloc.2 IL_00d9 20 ff ff ff 7f ldc.i4 0x7FFFFFFF IL_00de 33 02 bne.un.s 2 (IL_00e2) IL_00e0 06 ldloc.0 IL_00e1 0c stloc.2 IL_00e2 06 ldloc.0 IL_00e3 17 ldc.i4.1 IL_00e4 58 add IL_00e5 0a stloc.0 IL_00e6 06 ldloc.0 IL_00e7 0d stloc.3 IL_00e8 38 17 01 00 00 br 279 (IL_0204) IL_00ed 07 ldloc.1 IL_00ee 16 ldc.i4.0 IL_00ef 3c 10 01 00 00 bge 272 (IL_0204) IL_00f4 06 ldloc.0 IL_00f5 0b stloc.1 IL_00f6 38 09 01 00 00 br 265 (IL_0204) IL_00fb 06 ldloc.0 IL_00fc 16 ldc.i4.0 IL_00fd 3e 02 01 00 00 ble 258 (IL_0204) IL_0102 07 ldloc.1 IL_0103 16 ldc.i4.0 IL_0104 3c fb 00 00 00 bge 251 (IL_0204) IL_0109 11 06 ldloc.s 0x6 IL_010b 16 ldc.i4.0 IL_010c 32 13 blt.s 19 (IL_0121) IL_010e 11 06 ldloc.s 0x6 IL_0110 06 ldloc.0 IL_0111 33 0b bne.un.s 11 (IL_011e) IL_0113 11 07 ldloc.s 0x7 IL_0115 17 ldc.i4.1 IL_0116 58 add IL_0117 13 07 stloc.s 0x7 IL_0119 38 e6 00 00 00 br 230 (IL_0204) IL_011e 17 ldc.i4.1 IL_011f 13 08 stloc.s 0x8 IL_0121 06 ldloc.0 IL_0122 13 06 stloc.s 0x6 IL_0124 17 ldc.i4.1 IL_0125 13 07 stloc.s 0x7 IL_0127 38 d8 00 00 00 br 216 (IL_0204) IL_012c 11 09 ldloc.s 0x9 IL_012e 18 ldc.i4.2 IL_012f 58 add IL_0130 13 09 stloc.s 0x9 IL_0132 38 cd 00 00 00 br 205 (IL_0204) IL_0137 11 09 ldloc.s 0x9 IL_0139 19 ldc.i4.3 IL_013a 58 add IL_013b 13 09 stloc.s 0x9 IL_013d 38 c2 00 00 00 br 194 (IL_0204) IL_0142 11 0c ldloc.s 0xC IL_0144 0f 02 ldarga.s 0x2 IL_0146 28 07 00 00 0a call 0xA000007 IL_014b 3c b4 00 00 00 bge 180 (IL_0204) IL_0150 11 12 ldloc.s 0x12 IL_0152 11 0c ldloc.s 0xC IL_0154 d3 conv.i IL_0155 18 ldc.i4.2 IL_0156 5a mul IL_0157 58 add IL_0158 49 ldind.u2 IL_0159 39 a6 00 00 00 brfalse 166 (IL_0204) IL_015e 11 12 ldloc.s 0x12 IL_0160 11 0c ldloc.s 0xC IL_0162 25 dup IL_0163 17 ldc.i4.1 IL_0164 58 add IL_0165 13 0c stloc.s 0xC IL_0167 d3 conv.i IL_0168 18 ldc.i4.2 IL_0169 5a mul IL_016a 58 add IL_016b 49 ldind.u2 IL_016c 11 0e ldloc.s 0xE IL_016e 33 d2 bne.un.s -46 (IL_0142) IL_0170 38 8f 00 00 00 br 143 (IL_0204) IL_0175 11 0c ldloc.s 0xC IL_0177 0f 02 ldarga.s 0x2 IL_0179 28 07 00 00 0a call 0xA000007 IL_017e 3c 81 00 00 00 bge 129 (IL_0204) IL_0183 11 12 ldloc.s 0x12 IL_0185 11 0c ldloc.s 0xC IL_0187 d3 conv.i IL_0188 18 ldc.i4.2 IL_0189 5a mul IL_018a 58 add IL_018b 49 ldind.u2 IL_018c 2c 76 brfalse.s 118 (IL_0204) IL_018e 11 0c ldloc.s 0xC IL_0190 17 ldc.i4.1 IL_0191 58 add IL_0192 13 0c stloc.s 0xC IL_0194 2b 6e br.s 110 (IL_0204) IL_0196 11 0c ldloc.s 0xC IL_0198 0f 02 ldarga.s 0x2 IL_019a 28 07 00 00 0a call 0xA000007 IL_019f 2f 0d bge.s 13 (IL_01ae) IL_01a1 11 12 ldloc.s 0x12 IL_01a3 11 0c ldloc.s 0xC IL_01a5 d3 conv.i IL_01a6 18 ldc.i4.2 IL_01a7 5a mul IL_01a8 58 add IL_01a9 49 ldind.u2 IL_01aa 1f 30 ldc.i4.s 0x30 IL_01ac 2e 36 beq.s 54 (IL_01e4) IL_01ae 11 0c ldloc.s 0xC IL_01b0 17 ldc.i4.1 IL_01b1 58 add IL_01b2 0f 02 ldarga.s 0x2 IL_01b4 28 07 00 00 0a call 0xA000007 IL_01b9 2f 49 bge.s 73 (IL_0204) IL_01bb 11 12 ldloc.s 0x12 IL_01bd 11 0c ldloc.s 0xC IL_01bf d3 conv.i IL_01c0 18 ldc.i4.2 IL_01c1 5a mul IL_01c2 58 add IL_01c3 49 ldind.u2 IL_01c4 1f 2b ldc.i4.s 0x2B IL_01c6 2e 0d beq.s 13 (IL_01d5) IL_01c8 11 12 ldloc.s 0x12 IL_01ca 11 0c ldloc.s 0xC IL_01cc d3 conv.i IL_01cd 18 ldc.i4.2 IL_01ce 5a mul IL_01cf 58 add IL_01d0 49 ldind.u2 IL_01d1 1f 2d ldc.i4.s 0x2D IL_01d3 33 2f bne.un.s 47 (IL_0204) IL_01d5 11 12 ldloc.s 0x12 IL_01d7 11 0c ldloc.s 0xC IL_01d9 17 ldc.i4.1 IL_01da 58 add IL_01db d3 conv.i IL_01dc 18 ldc.i4.2 IL_01dd 5a mul IL_01de 58 add IL_01df 49 ldind.u2 IL_01e0 1f 30 ldc.i4.s 0x30 IL_01e2 33 20 bne.un.s 32 (IL_0204) IL_01e4 11 0c ldloc.s 0xC IL_01e6 17 ldc.i4.1 IL_01e7 58 add IL_01e8 25 dup IL_01e9 13 0c stloc.s 0xC IL_01eb 0f 02 ldarga.s 0x2 IL_01ed 28 07 00 00 0a call 0xA000007 IL_01f2 2f 0d bge.s 13 (IL_0201) IL_01f4 11 12 ldloc.s 0x12 IL_01f6 11 0c ldloc.s 0xC IL_01f8 d3 conv.i IL_01f9 18 ldc.i4.2 IL_01fa 5a mul IL_01fb 58 add IL_01fc 49 ldind.u2 IL_01fd 1f 30 ldc.i4.s 0x30 IL_01ff 2e e3 beq.s -29 (IL_01e4) IL_0201 17 ldc.i4.1 IL_0202 13 05 stloc.s 0x5 IL_0204 11 0c ldloc.s 0xC IL_0206 0f 02 ldarga.s 0x2 IL_0208 28 07 00 00 0a call 0xA000007 IL_020d 2f 1c bge.s 28 (IL_022b) IL_020f 11 12 ldloc.s 0x12 IL_0211 11 0c ldloc.s 0xC IL_0213 25 dup IL_0214 17 ldc.i4.1 IL_0215 58 add IL_0216 13 0c stloc.s 0xC IL_0218 d3 conv.i IL_0219 18 ldc.i4.2 IL_021a 5a mul IL_021b 58 add IL_021c 49 ldind.u2 IL_021d 25 dup IL_021e 13 0e stloc.s 0xE IL_0220 2c 09 brfalse.s 9 (IL_022b) IL_0222 11 0e ldloc.s 0xE IL_0224 1f 3b ldc.i4.s 0x3B IL_0226 40 30 fe ff ff bne.un -464 (IL_005b) IL_022b 16 ldc.i4.0 IL_022c e0 conv.u IL_022d 13 13 stloc.s 0x13 IL_022f 07 ldloc.1 IL_0230 16 ldc.i4.0 IL_0231 2f 02 bge.s 2 (IL_0235) IL_0233 06 ldloc.0 IL_0234 0b stloc.1 IL_0235 11 06 ldloc.s 0x6 IL_0237 16 ldc.i4.0 IL_0238 32 13 blt.s 19 (IL_024d) IL_023a 11 06 ldloc.s 0x6 IL_023c 07 ldloc.1 IL_023d 33 0b bne.un.s 11 (IL_024a) IL_023f 11 09 ldloc.s 0x9 IL_0241 11 07 ldloc.s 0x7 IL_0243 19 ldc.i4.3 IL_0244 5a mul IL_0245 59 sub IL_0246 13 09 stloc.s 0x9 IL_0248 2b 03 br.s 3 (IL_024d) IL_024a 17 ldc.i4.1 IL_024b 13 08 stloc.s 0x8 IL_024d 11 0d ldloc.s 0xD IL_024f 47 ldind.u1 IL_0250 2c 45 brfalse.s 69 (IL_0297) IL_0252 03 ldarg.1 IL_0253 7c d2 04 00 04 ldflda 0x40004D2 IL_0258 25 dup IL_0259 4a ldind.i4 IL_025a 11 09 ldloc.s 0x9 IL_025c 58 add IL_025d 54 stind.i4 IL_025e 11 05 ldloc.s 0x5 IL_0260 2d 0c brtrue.s 12 (IL_026e) IL_0262 03 ldarg.1 IL_0263 7b d2 04 00 04 ldfld 0x40004D2 IL_0268 06 ldloc.0 IL_0269 58 add IL_026a 07 ldloc.1 IL_026b 59 sub IL_026c 2b 01 br.s 1 (IL_026f) IL_026e 06 ldloc.0 IL_026f 13 14 stloc.s 0x14 IL_0271 03 ldarg.1 IL_0272 11 14 ldloc.s 0x14 IL_0274 16 ldc.i4.0 IL_0275 28 97 17 00 06 call 0x6001797 IL_027a 11 0d ldloc.s 0xD IL_027c 47 ldind.u1 IL_027d 2d 2f brtrue.s 47 (IL_02ae) IL_027f 04 ldarg.2 IL_0280 18 ldc.i4.2 IL_0281 28 98 17 00 06 call 0x6001798 IL_0286 13 0c stloc.s 0xC IL_0288 11 0c ldloc.s 0xC IL_028a 11 0b ldloc.s 0xB IL_028c 2e 20 beq.s 32 (IL_02ae) IL_028e 11 0c ldloc.s 0xC IL_0290 13 0b stloc.s 0xB IL_0292 38 96 fd ff ff br -618 (IL_002d) IL_0297 03 ldarg.1 IL_0298 7b d5 04 00 04 ldfld 0x40004D5 IL_029d 19 ldc.i4.3 IL_029e 2e 07 beq.s 7 (IL_02a7) IL_02a0 03 ldarg.1 IL_02a1 16 ldc.i4.0 IL_02a2 7d d3 04 00 04 stfld 0x40004D3 IL_02a7 03 ldarg.1 IL_02a8 16 ldc.i4.0 IL_02a9 7d d2 04 00 04 stfld 0x40004D2 IL_02ae 08 ldloc.2 IL_02af 07 ldloc.1 IL_02b0 32 03 blt.s 3 (IL_02b5) IL_02b2 16 ldc.i4.0 IL_02b3 2b 03 br.s 3 (IL_02b8) IL_02b5 07 ldloc.1 IL_02b6 08 ldloc.2 IL_02b7 59 sub IL_02b8 0c stloc.2 IL_02b9 09 ldloc.3 IL_02ba 07 ldloc.1 IL_02bb 30 03 bgt.s 3 (IL_02c0) IL_02bd 16 ldc.i4.0 IL_02be 2b 03 br.s 3 (IL_02c3) IL_02c0 07 ldloc.1 IL_02c1 09 ldloc.3 IL_02c2 59 sub IL_02c3 0d stloc.3 IL_02c4 11 05 ldloc.s 0x5 IL_02c6 2c 08 brfalse.s 8 (IL_02d0) IL_02c8 07 ldloc.1 IL_02c9 13 04 stloc.s 0x4 IL_02cb 16 ldc.i4.0 IL_02cc 13 0a stloc.s 0xA IL_02ce 2b 1e br.s 30 (IL_02ee) IL_02d0 03 ldarg.1 IL_02d1 7b d2 04 00 04 ldfld 0x40004D2 IL_02d6 07 ldloc.1 IL_02d7 30 03 bgt.s 3 (IL_02dc) IL_02d9 07 ldloc.1 IL_02da 2b 06 br.s 6 (IL_02e2) IL_02dc 03 ldarg.1 IL_02dd 7b d2 04 00 04 ldfld 0x40004D2 IL_02e2 13 04 stloc.s 0x4 IL_02e4 03 ldarg.1 IL_02e5 7b d2 04 00 04 ldfld 0x40004D2 IL_02ea 07 ldloc.1 IL_02eb 59 sub IL_02ec 13 0a stloc.s 0xA IL_02ee 11 0b ldloc.s 0xB IL_02f0 13 0c stloc.s 0xC IL_02f2 1f 10 ldc.i4.s 0x10 IL_02f4 e0 conv.u IL_02f5 fe 0f localloc IL_02f7 1a ldc.i4.4 IL_02f8 73 39 00 00 0a newobj 0xA000039 IL_02fd 13 15 stloc.s 0x15 IL_02ff 11 15 ldloc.s 0x15 IL_0301 13 0f stloc.s 0xF IL_0303 15 ldc.i4.m1 IL_0304 13 10 stloc.s 0x10 IL_0306 11 08 ldloc.s 0x8 IL_0308 39 bb 00 00 00 brfalse 187 (IL_03c8) IL_030d 05 ldarg.3 IL_030e 6f 0e 2e 00 06 callvirt 0x6002E0E IL_0313 6f 18 08 00 06 callvirt 0x6000818 IL_0318 16 ldc.i4.0 IL_0319 3e aa 00 00 00 ble 170 (IL_03c8) IL_031e 05 ldarg.3 IL_031f 7b 2d 09 00 04 ldfld 0x400092D IL_0324 13 16 stloc.s 0x16 IL_0326 16 ldc.i4.0 IL_0327 13 17 stloc.s 0x17 IL_0329 16 ldc.i4.0 IL_032a 13 18 stloc.s 0x18 IL_032c 11 16 ldloc.s 0x16 IL_032e 8e ldlen IL_032f 69 conv.i4 IL_0330 13 19 stloc.s 0x19 IL_0332 11 19 ldloc.s 0x19 IL_0334 2c 07 brfalse.s 7 (IL_033d) IL_0336 11 16 ldloc.s 0x16 IL_0338 11 17 ldloc.s 0x17 IL_033a 94 ldelem.i4 IL_033b 13 18 stloc.s 0x18 IL_033d 11 18 ldloc.s 0x18 IL_033f 13 1a stloc.s 0x1A IL_0341 11 04 ldloc.s 0x4 IL_0343 11 0a ldloc.s 0xA IL_0345 16 ldc.i4.0 IL_0346 32 03 blt.s 3 (IL_034b) IL_0348 16 ldc.i4.0 IL_0349 2b 02 br.s 2 (IL_034d) IL_034b 11 0a ldloc.s 0xA IL_034d 58 add IL_034e 13 1b stloc.s 0x1B IL_0350 08 ldloc.2 IL_0351 11 1b ldloc.s 0x1B IL_0353 30 04 bgt.s 4 (IL_0359) IL_0355 11 1b ldloc.s 0x1B IL_0357 2b 01 br.s 1 (IL_035a) IL_0359 08 ldloc.2 IL_035a 13 1c stloc.s 0x1C IL_035c 2b 64 br.s 100 (IL_03c2) IL_035e 11 1a ldloc.s 0x1A IL_0360 2c 66 brfalse.s 102 (IL_03c8) IL_0362 11 10 ldloc.s 0x10 IL_0364 17 ldc.i4.1 IL_0365 58 add IL_0366 13 10 stloc.s 0x10 IL_0368 11 10 ldloc.s 0x10 IL_036a 12 0f ldloca.s 0xF IL_036c 28 67 00 00 0a call 0xA000067 IL_0371 32 27 blt.s 39 (IL_039a) IL_0373 12 0f ldloca.s 0xF IL_0375 28 67 00 00 0a call 0xA000067 IL_037a 18 ldc.i4.2 IL_037b 5a mul IL_037c 8d 1b 01 00 02 newarr 0x200011B IL_0381 13 1d stloc.s 0x1D IL_0383 12 0f ldloca.s 0xF IL_0385 11 1d ldloc.s 0x1D IL_0387 28 16 06 00 0a call 0xA000616 IL_038c 28 17 06 00 0a call 0xA000617 IL_0391 11 1d ldloc.s 0x1D IL_0393 28 16 06 00 0a call 0xA000616 IL_0398 13 0f stloc.s 0xF IL_039a 12 0f ldloca.s 0xF IL_039c 11 10 ldloc.s 0x10 IL_039e 28 68 00 00 0a call 0xA000068 IL_03a3 11 18 ldloc.s 0x18 IL_03a5 54 stind.i4 IL_03a6 11 17 ldloc.s 0x17 IL_03a8 11 19 ldloc.s 0x19 IL_03aa 17 ldc.i4.1 IL_03ab 59 sub IL_03ac 2f 0d bge.s 13 (IL_03bb) IL_03ae 11 17 ldloc.s 0x17 IL_03b0 17 ldc.i4.1 IL_03b1 58 add IL_03b2 13 17 stloc.s 0x17 IL_03b4 11 16 ldloc.s 0x16 IL_03b6 11 17 ldloc.s 0x17 IL_03b8 94 ldelem.i4 IL_03b9 13 1a stloc.s 0x1A IL_03bb 11 18 ldloc.s 0x18 IL_03bd 11 1a ldloc.s 0x1A IL_03bf 58 add IL_03c0 13 18 stloc.s 0x18 IL_03c2 11 1c ldloc.s 0x1C IL_03c4 11 18 ldloc.s 0x18 IL_03c6 30 96 bgt.s -106 (IL_035e) IL_03c8 03 ldarg.1 IL_03c9 7b d3 04 00 04 ldfld 0x40004D3 IL_03ce 2c 18 brfalse.s 24 (IL_03e8) IL_03d0 11 0b ldloc.s 0xB IL_03d2 2d 14 brtrue.s 20 (IL_03e8) IL_03d4 03 ldarg.1 IL_03d5 7b d2 04 00 04 ldfld 0x40004D2 IL_03da 2c 0c brfalse.s 12 (IL_03e8) IL_03dc 02 ldarg.0 IL_03dd 05 ldarg.3 IL_03de 6f 08 2e 00 06 callvirt 0x6002E08 IL_03e3 28 5f 3e 00 06 call 0x6003E5F IL_03e8 16 ldc.i4.0 IL_03e9 13 11 stloc.s 0x11 IL_03eb 04 ldarg.2 IL_03ec 28 fc 00 00 2b call 0x2B0000FC IL_03f1 13 1f stloc.s 0x1F IL_03f3 11 1f ldloc.s 0x1F IL_03f5 e0 conv.u IL_03f6 13 1e stloc.s 0x1E IL_03f8 11 0d ldloc.s 0xD IL_03fa 13 20 stloc.s 0x20 IL_03fc 38 a9 03 00 00 br 937 (IL_07aa) IL_0401 11 0a ldloc.s 0xA IL_0403 16 ldc.i4.0 IL_0404 31 6c ble.s 108 (IL_0472) IL_0406 11 0e ldloc.s 0xE IL_0408 1f 23 ldc.i4.s 0x23 IL_040a 2e 61 beq.s 97 (IL_046d) IL_040c 11 0e ldloc.s 0xE IL_040e 1f 2e ldc.i4.s 0x2E IL_0410 2e 5b beq.s 91 (IL_046d) IL_0412 11 0e ldloc.s 0xE IL_0414 1f 30 ldc.i4.s 0x30 IL_0416 2e 55 beq.s 85 (IL_046d) IL_0418 2b 58 br.s 88 (IL_0472) IL_041a 02 ldarg.0 IL_041b 11 20 ldloc.s 0x20 IL_041d 47 ldind.u1 IL_041e 2d 04 brtrue.s 4 (IL_0424) IL_0420 1f 30 ldc.i4.s 0x30 IL_0422 2b 08 br.s 8 (IL_042c) IL_0424 11 20 ldloc.s 0x20 IL_0426 25 dup IL_0427 17 ldc.i4.1 IL_0428 58 add IL_0429 13 20 stloc.s 0x20 IL_042b 47 ldind.u1 IL_042c 28 5e 3e 00 06 call 0x6003E5E IL_0431 11 08 ldloc.s 0x8 IL_0433 2c 2c brfalse.s 44 (IL_0461) IL_0435 11 04 ldloc.s 0x4 IL_0437 17 ldc.i4.1 IL_0438 31 27 ble.s 39 (IL_0461) IL_043a 11 10 ldloc.s 0x10 IL_043c 16 ldc.i4.0 IL_043d 32 22 blt.s 34 (IL_0461) IL_043f 11 04 ldloc.s 0x4 IL_0441 12 0f ldloca.s 0xF IL_0443 11 10 ldloc.s 0x10 IL_0445 28 68 00 00 0a call 0xA000068 IL_044a 4a ldind.i4 IL_044b 17 ldc.i4.1 IL_044c 58 add IL_044d 33 12 bne.un.s 18 (IL_0461) IL_044f 02 ldarg.0 IL_0450 05 ldarg.3 IL_0451 6f 0e 2e 00 06 callvirt 0x6002E0E IL_0456 28 5f 3e 00 06 call 0x6003E5F IL_045b 11 10 ldloc.s 0x10 IL_045d 17 ldc.i4.1 IL_045e 59 sub IL_045f 13 10 stloc.s 0x10 IL_0461 11 04 ldloc.s 0x4 IL_0463 17 ldc.i4.1 IL_0464 59 sub IL_0465 13 04 stloc.s 0x4 IL_0467 11 0a ldloc.s 0xA IL_0469 17 ldc.i4.1 IL_046a 59 sub IL_046b 13 0a stloc.s 0xA IL_046d 11 0a ldloc.s 0xA IL_046f 16 ldc.i4.0 IL_0470 30 a8 bgt.s -88 (IL_041a) IL_0472 11 0e ldloc.s 0xE IL_0474 1f 45 ldc.i4.s 0x45 IL_0476 35 4e bgt.un.s 78 (IL_04c6) IL_0478 11 0e ldloc.s 0xE IL_047a 1f 22 ldc.i4.s 0x22 IL_047c 59 sub IL_047d 45 06 00 00 00 34 01 00 00 4f 00 00 00 08 03 00 00 0f 01 00 00 08 03 00 00 34 01 00 00 switch IL_049a 11 0e ldloc.s 0xE IL_049c 1f 2c ldc.i4.s 0x2C IL_049e 59 sub IL_049f 45 05 00 00 00 f2 02 00 00 ea 02 00 00 ac 00 00 00 ea 02 00 00 31 00 00 00 switch IL_04b8 11 0e ldloc.s 0xE IL_04ba 1f 45 ldc.i4.s 0x45 IL_04bc 3b 8c 01 00 00 beq 396 (IL_064d) IL_04c1 38 dc 02 00 00 br 732 (IL_07a2) IL_04c6 11 0e ldloc.s 0xE IL_04c8 1f 5c ldc.i4.s 0x5C IL_04ca 3b 49 01 00 00 beq 329 (IL_0618) IL_04cf 11 0e ldloc.s 0xE IL_04d1 1f 65 ldc.i4.s 0x65 IL_04d3 3b 75 01 00 00 beq 373 (IL_064d) IL_04d8 11 0e ldloc.s 0xE IL_04da 20 30 20 00 00 ldc.i4 0x2030 IL_04df 3b b4 00 00 00 beq 180 (IL_0598) IL_04e4 38 b9 02 00 00 br 697 (IL_07a2) IL_04e9 11 0a ldloc.s 0xA IL_04eb 16 ldc.i4.0 IL_04ec 2f 14 bge.s 20 (IL_0502) IL_04ee 11 0a ldloc.s 0xA IL_04f0 17 ldc.i4.1 IL_04f1 58 add IL_04f2 13 0a stloc.s 0xA IL_04f4 11 04 ldloc.s 0x4 IL_04f6 08 ldloc.2 IL_04f7 31 03 ble.s 3 (IL_04fc) IL_04f9 16 ldc.i4.0 IL_04fa 2b 02 br.s 2 (IL_04fe) IL_04fc 1f 30 ldc.i4.s 0x30 IL_04fe 13 0e stloc.s 0xE IL_0500 2b 1b br.s 27 (IL_051d) IL_0502 11 20 ldloc.s 0x20 IL_0504 47 ldind.u1 IL_0505 2d 0c brtrue.s 12 (IL_0513) IL_0507 11 04 ldloc.s 0x4 IL_0509 09 ldloc.3 IL_050a 30 03 bgt.s 3 (IL_050f) IL_050c 16 ldc.i4.0 IL_050d 2b 0c br.s 12 (IL_051b) IL_050f 1f 30 ldc.i4.s 0x30 IL_0511 2b 08 br.s 8 (IL_051b) IL_0513 11 20 ldloc.s 0x20 IL_0515 25 dup IL_0516 17 ldc.i4.1 IL_0517 58 add IL_0518 13 20 stloc.s 0x20 IL_051a 47 ldind.u1 IL_051b 13 0e stloc.s 0xE IL_051d 11 0e ldloc.s 0xE IL_051f 2c 38 brfalse.s 56 (IL_0559) IL_0521 02 ldarg.0 IL_0522 11 0e ldloc.s 0xE IL_0524 28 5e 3e 00 06 call 0x6003E5E IL_0529 11 08 ldloc.s 0x8 IL_052b 2c 2c brfalse.s 44 (IL_0559) IL_052d 11 04 ldloc.s 0x4 IL_052f 17 ldc.i4.1 IL_0530 31 27 ble.s 39 (IL_0559) IL_0532 11 10 ldloc.s 0x10 IL_0534 16 ldc.i4.0 IL_0535 32 22 blt.s 34 (IL_0559) IL_0537 11 04 ldloc.s 0x4 IL_0539 12 0f ldloca.s 0xF IL_053b 11 10 ldloc.s 0x10 IL_053d 28 68 00 00 0a call 0xA000068 IL_0542 4a ldind.i4 IL_0543 17 ldc.i4.1 IL_0544 58 add IL_0545 33 12 bne.un.s 18 (IL_0559) IL_0547 02 ldarg.0 IL_0548 05 ldarg.3 IL_0549 6f 0e 2e 00 06 callvirt 0x6002E0E IL_054e 28 5f 3e 00 06 call 0x6003E5F IL_0553 11 10 ldloc.s 0x10 IL_0555 17 ldc.i4.1 IL_0556 59 sub IL_0557 13 10 stloc.s 0x10 IL_0559 11 04 ldloc.s 0x4 IL_055b 17 ldc.i4.1 IL_055c 59 sub IL_055d 13 04 stloc.s 0x4 IL_055f 38 46 02 00 00 br 582 (IL_07aa) IL_0564 11 04 ldloc.s 0x4 IL_0566 16 ldc.i4.0 IL_0567 fe 03 cgt.un IL_0569 11 11 ldloc.s 0x11 IL_056b 60 or IL_056c 3a 39 02 00 00 brtrue 569 (IL_07aa) IL_0571 09 ldloc.3 IL_0572 16 ldc.i4.0 IL_0573 32 0f blt.s 15 (IL_0584) IL_0575 07 ldloc.1 IL_0576 06 ldloc.0 IL_0577 3c 2e 02 00 00 bge 558 (IL_07aa) IL_057c 11 20 ldloc.s 0x20 IL_057e 47 ldind.u1 IL_057f 39 26 02 00 00 brfalse 550 (IL_07aa) IL_0584 02 ldarg.0 IL_0585 05 ldarg.3 IL_0586 6f 0c 2e 00 06 callvirt 0x6002E0C IL_058b 28 5f 3e 00 06 call 0x6003E5F IL_0590 17 ldc.i4.1 IL_0591 13 11 stloc.s 0x11 IL_0593 38 12 02 00 00 br 530 (IL_07aa) IL_0598 02 ldarg.0 IL_0599 05 ldarg.3 IL_059a 6f 1e 2e 00 06 callvirt 0x6002E1E IL_059f 28 5f 3e 00 06 call 0x6003E5F IL_05a4 38 01 02 00 00 br 513 (IL_07aa) IL_05a9 02 ldarg.0 IL_05aa 05 ldarg.3 IL_05ab 6f 1c 2e 00 06 callvirt 0x6002E1C IL_05b0 28 5f 3e 00 06 call 0x6003E5F IL_05b5 38 f0 01 00 00 br 496 (IL_07aa) IL_05ba 02 ldarg.0 IL_05bb 11 1e ldloc.s 0x1E IL_05bd 11 0c ldloc.s 0xC IL_05bf 25 dup IL_05c0 17 ldc.i4.1 IL_05c1 58 add IL_05c2 13 0c stloc.s 0xC IL_05c4 d3 conv.i IL_05c5 18 ldc.i4.2 IL_05c6 5a mul IL_05c7 58 add IL_05c8 49 ldind.u2 IL_05c9 28 5e 3e 00 06 call 0x6003E5E IL_05ce 11 0c ldloc.s 0xC IL_05d0 0f 02 ldarga.s 0x2 IL_05d2 28 07 00 00 0a call 0xA000007 IL_05d7 2f 18 bge.s 24 (IL_05f1) IL_05d9 11 1e ldloc.s 0x1E IL_05db 11 0c ldloc.s 0xC IL_05dd d3 conv.i IL_05de 18 ldc.i4.2 IL_05df 5a mul IL_05e0 58 add IL_05e1 49 ldind.u2 IL_05e2 2c 0d brfalse.s 13 (IL_05f1) IL_05e4 11 1e ldloc.s 0x1E IL_05e6 11 0c ldloc.s 0xC IL_05e8 d3 conv.i IL_05e9 18 ldc.i4.2 IL_05ea 5a mul IL_05eb 58 add IL_05ec 49 ldind.u2 IL_05ed 11 0e ldloc.s 0xE IL_05ef 33 c9 bne.un.s -55 (IL_05ba) IL_05f1 11 0c ldloc.s 0xC IL_05f3 0f 02 ldarga.s 0x2 IL_05f5 28 07 00 00 0a call 0xA000007 IL_05fa 3c ab 01 00 00 bge 427 (IL_07aa) IL_05ff 11 1e ldloc.s 0x1E IL_0601 11 0c ldloc.s 0xC IL_0603 d3 conv.i IL_0604 18 ldc.i4.2 IL_0605 5a mul IL_0606 58 add IL_0607 49 ldind.u2 IL_0608 39 9d 01 00 00 brfalse 413 (IL_07aa) IL_060d 11 0c ldloc.s 0xC IL_060f 17 ldc.i4.1 IL_0610 58 add IL_0611 13 0c stloc.s 0xC IL_0613 38 92 01 00 00 br 402 (IL_07aa) IL_0618 11 0c ldloc.s 0xC IL_061a 0f 02 ldarga.s 0x2 IL_061c 28 07 00 00 0a call 0xA000007 IL_0621 3c 84 01 00 00 bge 388 (IL_07aa) IL_0626 11 1e ldloc.s 0x1E IL_0628 11 0c ldloc.s 0xC IL_062a d3 conv.i IL_062b 18 ldc.i4.2 IL_062c 5a mul IL_062d 58 add IL_062e 49 ldind.u2 IL_062f 39 76 01 00 00 brfalse 374 (IL_07aa) IL_0634 02 ldarg.0 IL_0635 11 1e ldloc.s 0x1E IL_0637 11 0c ldloc.s 0xC IL_0639 25 dup IL_063a 17 ldc.i4.1 IL_063b 58 add IL_063c 13 0c stloc.s 0xC IL_063e d3 conv.i IL_063f 18 ldc.i4.2 IL_0640 5a mul IL_0641 58 add IL_0642 49 ldind.u2 IL_0643 28 5e 3e 00 06 call 0x6003E5E IL_0648 38 5d 01 00 00 br 349 (IL_07aa) IL_064d 16 ldc.i4.0 IL_064e 13 21 stloc.s 0x21 IL_0650 16 ldc.i4.0 IL_0651 13 22 stloc.s 0x22 IL_0653 11 05 ldloc.s 0x5 IL_0655 39 d7 00 00 00 brfalse 215 (IL_0731) IL_065a 11 0c ldloc.s 0xC IL_065c 0f 02 ldarga.s 0x2 IL_065e 28 07 00 00 0a call 0xA000007 IL_0663 2f 15 bge.s 21 (IL_067a) IL_0665 11 1e ldloc.s 0x1E IL_0667 11 0c ldloc.s 0xC IL_0669 d3 conv.i IL_066a 18 ldc.i4.2 IL_066b 5a mul IL_066c 58 add IL_066d 49 ldind.u2 IL_066e 1f 30 ldc.i4.s 0x30 IL_0670 33 08 bne.un.s 8 (IL_067a) IL_0672 11 22 ldloc.s 0x22 IL_0674 17 ldc.i4.1 IL_0675 58 add IL_0676 13 22 stloc.s 0x22 IL_0678 2b 6a br.s 106 (IL_06e4) IL_067a 11 0c ldloc.s 0xC IL_067c 17 ldc.i4.1 IL_067d 58 add IL_067e 0f 02 ldarga.s 0x2 IL_0680 28 07 00 00 0a call 0xA000007 IL_0685 2f 21 bge.s 33 (IL_06a8) IL_0687 11 1e ldloc.s 0x1E IL_0689 11 0c ldloc.s 0xC IL_068b d3 conv.i IL_068c 18 ldc.i4.2 IL_068d 5a mul IL_068e 58 add IL_068f 49 ldind.u2 IL_0690 1f 2b ldc.i4.s 0x2B IL_0692 33 14 bne.un.s 20 (IL_06a8) IL_0694 11 1e ldloc.s 0x1E IL_0696 11 0c ldloc.s 0xC IL_0698 17 ldc.i4.1 IL_0699 58 add IL_069a d3 conv.i IL_069b 18 ldc.i4.2 IL_069c 5a mul IL_069d 58 add IL_069e 49 ldind.u2 IL_069f 1f 30 ldc.i4.s 0x30 IL_06a1 33 05 bne.un.s 5 (IL_06a8) IL_06a3 17 ldc.i4.1 IL_06a4 13 21 stloc.s 0x21 IL_06a6 2b 3c br.s 60 (IL_06e4) IL_06a8 11 0c ldloc.s 0xC IL_06aa 17 ldc.i4.1 IL_06ab 58 add IL_06ac 0f 02 ldarga.s 0x2 IL_06ae 28 07 00 00 0a call 0xA000007 IL_06b3 2f 1c bge.s 28 (IL_06d1) IL_06b5 11 1e ldloc.s 0x1E IL_06b7 11 0c ldloc.s 0xC IL_06b9 d3 conv.i IL_06ba 18 ldc.i4.2 IL_06bb 5a mul IL_06bc 58 add IL_06bd 49 ldind.u2 IL_06be 1f 2d ldc.i4.s 0x2D IL_06c0 33 0f bne.un.s 15 (IL_06d1) IL_06c2 11 1e ldloc.s 0x1E IL_06c4 11 0c ldloc.s 0xC IL_06c6 17 ldc.i4.1 IL_06c7 58 add IL_06c8 d3 conv.i IL_06c9 18 ldc.i4.2 IL_06ca 5a mul IL_06cb 58 add IL_06cc 49 ldind.u2 IL_06cd 1f 30 ldc.i4.s 0x30 IL_06cf 2e 13 beq.s 19 (IL_06e4) IL_06d1 02 ldarg.0 IL_06d2 11 0e ldloc.s 0xE IL_06d4 28 5e 3e 00 06 call 0x6003E5E IL_06d9 38 cc 00 00 00 br 204 (IL_07aa) IL_06de 11 22 ldloc.s 0x22 IL_06e0 17 ldc.i4.1 IL_06e1 58 add IL_06e2 13 22 stloc.s 0x22 IL_06e4 11 0c ldloc.s 0xC IL_06e6 17 ldc.i4.1 IL_06e7 58 add IL_06e8 25 dup IL_06e9 13 0c stloc.s 0xC IL_06eb 0f 02 ldarga.s 0x2 IL_06ed 28 07 00 00 0a call 0xA000007 IL_06f2 2f 0d bge.s 13 (IL_0701) IL_06f4 11 1e ldloc.s 0x1E IL_06f6 11 0c ldloc.s 0xC IL_06f8 d3 conv.i IL_06f9 18 ldc.i4.2 IL_06fa 5a mul IL_06fb 58 add IL_06fc 49 ldind.u2 IL_06fd 1f 30 ldc.i4.s 0x30 IL_06ff 2e dd beq.s -35 (IL_06de) IL_0701 11 22 ldloc.s 0x22 IL_0703 1f 0a ldc.i4.s 0xA IL_0705 31 04 ble.s 4 (IL_070b) IL_0707 1f 0a ldc.i4.s 0xA IL_0709 13 22 stloc.s 0x22 IL_070b 11 0d ldloc.s 0xD IL_070d 47 ldind.u1 IL_070e 2c 0a brfalse.s 10 (IL_071a) IL_0710 03 ldarg.1 IL_0711 7b d2 04 00 04 ldfld 0x40004D2 IL_0716 07 ldloc.1 IL_0717 59 sub IL_0718 2b 01 br.s 1 (IL_071b) IL_071a 16 ldc.i4.0 IL_071b 13 23 stloc.s 0x23 IL_071d 02 ldarg.0 IL_071e 05 ldarg.3 IL_071f 11 23 ldloc.s 0x23 IL_0721 11 0e ldloc.s 0xE IL_0723 11 22 ldloc.s 0x22 IL_0725 11 21 ldloc.s 0x21 IL_0727 28 94 17 00 06 call 0x6001794 IL_072c 16 ldc.i4.0 IL_072d 13 05 stloc.s 0x5 IL_072f 2b 79 br.s 121 (IL_07aa) IL_0731 02 ldarg.0 IL_0732 11 0e ldloc.s 0xE IL_0734 28 5e 3e 00 06 call 0x6003E5E IL_0739 11 0c ldloc.s 0xC IL_073b 0f 02 ldarga.s 0x2 IL_073d 28 07 00 00 0a call 0xA000007 IL_0742 2f 66 bge.s 102 (IL_07aa) IL_0744 11 1e ldloc.s 0x1E IL_0746 11 0c ldloc.s 0xC IL_0748 d3 conv.i IL_0749 18 ldc.i4.2 IL_074a 5a mul IL_074b 58 add IL_074c 49 ldind.u2 IL_074d 1f 2b ldc.i4.s 0x2B IL_074f 2e 0d beq.s 13 (IL_075e) IL_0751 11 1e ldloc.s 0x1E IL_0753 11 0c ldloc.s 0xC IL_0755 d3 conv.i IL_0756 18 ldc.i4.2 IL_0757 5a mul IL_0758 58 add IL_0759 49 ldind.u2 IL_075a 1f 2d ldc.i4.s 0x2D IL_075c 33 2a bne.un.s 42 (IL_0788) IL_075e 02 ldarg.0 IL_075f 11 1e ldloc.s 0x1E IL_0761 11 0c ldloc.s 0xC IL_0763 25 dup IL_0764 17 ldc.i4.1 IL_0765 58 add IL_0766 13 0c stloc.s 0xC IL_0768 d3 conv.i IL_0769 18 ldc.i4.2 IL_076a 5a mul IL_076b 58 add IL_076c 49 ldind.u2 IL_076d 28 5e 3e 00 06 call 0x6003E5E IL_0772 2b 14 br.s 20 (IL_0788) IL_0774 02 ldarg.0 IL_0775 11 1e ldloc.s 0x1E IL_0777 11 0c ldloc.s 0xC IL_0779 25 dup IL_077a 17 ldc.i4.1 IL_077b 58 add IL_077c 13 0c stloc.s 0xC IL_077e d3 conv.i IL_077f 18 ldc.i4.2 IL_0780 5a mul IL_0781 58 add IL_0782 49 ldind.u2 IL_0783 28 5e 3e 00 06 call 0x6003E5E IL_0788 11 0c ldloc.s 0xC IL_078a 0f 02 ldarga.s 0x2 IL_078c 28 07 00 00 0a call 0xA000007 IL_0791 2f 17 bge.s 23 (IL_07aa) IL_0793 11 1e ldloc.s 0x1E IL_0795 11 0c ldloc.s 0xC IL_0797 d3 conv.i IL_0798 18 ldc.i4.2 IL_0799 5a mul IL_079a 58 add IL_079b 49 ldind.u2 IL_079c 1f 30 ldc.i4.s 0x30 IL_079e 2e d4 beq.s -44 (IL_0774) IL_07a0 2b 08 br.s 8 (IL_07aa) IL_07a2 02 ldarg.0 IL_07a3 11 0e ldloc.s 0xE IL_07a5 28 5e 3e 00 06 call 0x6003E5E IL_07aa 11 0c ldloc.s 0xC IL_07ac 0f 02 ldarga.s 0x2 IL_07ae 28 07 00 00 0a call 0xA000007 IL_07b3 2f 1c bge.s 28 (IL_07d1) IL_07b5 11 1e ldloc.s 0x1E IL_07b7 11 0c ldloc.s 0xC IL_07b9 25 dup IL_07ba 17 ldc.i4.1 IL_07bb 58 add IL_07bc 13 0c stloc.s 0xC IL_07be d3 conv.i IL_07bf 18 ldc.i4.2 IL_07c0 5a mul IL_07c1 58 add IL_07c2 49 ldind.u2 IL_07c3 25 dup IL_07c4 13 0e stloc.s 0xE IL_07c6 2c 09 brfalse.s 9 (IL_07d1) IL_07c8 11 0e ldloc.s 0xE IL_07ca 1f 3b ldc.i4.s 0x3B IL_07cc 40 30 fc ff ff bne.un -976 (IL_0401) IL_07d1 16 ldc.i4.0 IL_07d2 e0 conv.u IL_07d3 13 1f stloc.s 0x1F IL_07d5 03 ldarg.1 IL_07d6 7b d3 04 00 04 ldfld 0x40004D3 IL_07db 2c 22 brfalse.s 34 (IL_07ff) IL_07dd 11 0b ldloc.s 0xB IL_07df 2d 1e brtrue.s 30 (IL_07ff) IL_07e1 03 ldarg.1 IL_07e2 7b d2 04 00 04 ldfld 0x40004D2 IL_07e7 2d 16 brtrue.s 22 (IL_07ff) IL_07e9 02 ldarg.0 IL_07ea 28 54 3e 00 06 call 0x6003E54 IL_07ef 16 ldc.i4.0 IL_07f0 31 0d ble.s 13 (IL_07ff) IL_07f2 02 ldarg.0 IL_07f3 16 ldc.i4.0 IL_07f4 05 ldarg.3 IL_07f5 6f 08 2e 00 06 callvirt 0x6002E08 IL_07fa 28 5d 3e 00 06 call 0x6003E5D IL_07ff 2a ret Arg #0 passed in register(s) x0 Arg #1 passed in register(s) x1 Arg #2 passed in register(s) x2,x3 lvaSetClass: setting class for V03 to (4000000000424640) System.Globalization.NumberFormatInfo Arg #3 passed in register(s) x4 Setting lvPinned for V23 lvaSetClass: setting class for V26 to (40000000004217B0) int[] lvaSetClass: setting class for V33 to (40000000004217B0) int[] Setting lvPinned for V35 lvaGrabTemp returning 40 (V40 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 arg0 byref ; V01 arg1 byref ; V02 arg2 struct multireg-arg ; V03 arg3 ref class-hnd ; V04 loc0 int ; V05 loc1 int ; V06 loc2 int ; V07 loc3 int ; V08 loc4 int ; V09 loc5 bool ; V10 loc6 int ; V11 loc7 int ; V12 loc8 bool ; V13 loc9 int ; V14 loc10 int ; V15 loc11 int ; V16 loc12 int ; V17 loc13 long ; V18 loc14 ushort ; V19 loc15 struct ; V20 loc16 int ; V21 loc17 bool ; V22 loc18 long ; V23 loc19 byref pinned ; V24 loc20 int ; V25 loc21 struct ; V26 loc22 ref class-hnd ; V27 loc23 int ; V28 loc24 int ; V29 loc25 int ; V30 loc26 int ; V31 loc27 int ; V32 loc28 int ; V33 loc29 ref class-hnd ; V34 loc30 long ; V35 loc31 byref pinned ; V36 loc32 long ; V37 loc33 bool ; V38 loc34 int ; V39 loc35 int ; V40 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 40 VarNum LVNum Name Beg End 0: 00h 00h V00 arg0 000h 800h 1: 01h 01h V01 arg1 000h 800h 2: 02h 02h V02 arg2 000h 800h 3: 03h 03h V03 arg3 000h 800h 4: 04h 04h V04 loc0 000h 800h 5: 05h 05h V05 loc1 000h 800h 6: 06h 06h V06 loc2 000h 800h 7: 07h 07h V07 loc3 000h 800h 8: 08h 08h V08 loc4 000h 800h 9: 09h 09h V09 loc5 000h 800h 10: 0Ah 0Ah V10 loc6 000h 800h 11: 0Bh 0Bh V11 loc7 000h 800h 12: 0Ch 0Ch V12 loc8 000h 800h 13: 0Dh 0Dh V13 loc9 000h 800h 14: 0Eh 0Eh V14 loc10 000h 800h 15: 0Fh 0Fh V15 loc11 000h 800h 16: 10h 10h V16 loc12 000h 800h 17: 11h 11h V17 loc13 000h 800h 18: 12h 12h V18 loc14 000h 800h 19: 13h 13h V19 loc15 000h 800h 20: 14h 14h V20 loc16 000h 800h 21: 15h 15h V21 loc17 000h 800h 22: 16h 16h V22 loc18 000h 800h 23: 17h 17h V23 loc19 000h 800h 24: 18h 18h V24 loc20 000h 800h 25: 19h 19h V25 loc21 000h 800h 26: 1Ah 1Ah V26 loc22 000h 800h 27: 1Bh 1Bh V27 loc23 000h 800h 28: 1Ch 1Ch V28 loc24 000h 800h 29: 1Dh 1Dh V29 loc25 000h 800h 30: 1Eh 1Eh V30 loc26 000h 800h 31: 1Fh 1Fh V31 loc27 000h 800h 32: 20h 20h V32 loc28 000h 800h 33: 21h 21h V33 loc29 000h 800h 34: 22h 22h V34 loc30 000h 800h 35: 23h 23h V35 loc31 000h 800h 36: 24h 24h V36 loc32 000h 800h 37: 25h 25h V37 loc33 000h 800h 38: 26h 26h V38 loc34 000h 800h 39: 27h 27h V39 loc35 000h 800h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) Named Intrinsic System.String.get_Length: Recognized Named Intrinsic System.Span`1.get_Item: Recognized Named Intrinsic System.Span`1.get_Item: Recognized Named Intrinsic System.Span`1.get_Item: Recognized Marked V17 as a single def local Marked V22 as a single def local Marked V24 as a single def local Marked V25 as a single def local Marked V26 as a single def local Marked V29 as a single def local Marked V31 as a single def local Marked V32 as a single def local Marked V33 as a single def local Marked V34 as a single def local Marked V39 as a single def local Jump targets: IL_0022 IL_0025 IL_0026 IL_002d IL_005b IL_0083 IL_00a1 IL_00af IL_00cf IL_00d8 IL_00e2 IL_00ed IL_00fb IL_011e IL_0121 IL_012c IL_0137 IL_0142 IL_0175 IL_0196 IL_01ae IL_01d5 IL_01e4 IL_0201 IL_0204 IL_022b IL_0235 IL_024a IL_024d IL_026e IL_026f IL_0297 IL_02a7 IL_02ae IL_02b5 IL_02b8 IL_02c0 IL_02c3 IL_02d0 IL_02dc IL_02e2 IL_02ee IL_033d IL_034b IL_034d IL_0359 IL_035a IL_035e IL_039a IL_03bb IL_03c2 IL_03c8 IL_03e8 IL_0401 IL_041a IL_0424 IL_042c IL_0461 IL_046d IL_0472 IL_049a IL_04b8 IL_04c6 IL_04e9 IL_04fc IL_04fe IL_0502 IL_050f IL_0513 IL_051b IL_051d IL_0559 IL_0564 IL_0584 IL_0598 IL_05a9 IL_05ba IL_05ce IL_05f1 IL_0618 IL_064d IL_067a IL_06a8 IL_06d1 IL_06de IL_06e4 IL_0701 IL_070b IL_071a IL_071b IL_0731 IL_075e IL_0774 IL_0788 IL_07a2 IL_07aa IL_07d1 IL_07ff New Basic Block BB01 [0000] created. BB01 [000..017) New Basic Block BB02 [0001] created. BB02 [017..01F) New Basic Block BB03 [0002] created. BB03 [01F..022) New Basic Block BB04 [0003] created. BB04 [022..025) New Basic Block BB05 [0004] created. BB05 [025..026) New Basic Block BB06 [0005] created. BB06 [026..02D) New Basic Block BB07 [0006] created. BB07 [02D..05B) New Basic Block BB08 [0007] created. BB08 [05B..061) New Basic Block BB09 [0008] created. BB09 [061..083) New Basic Block BB10 [0009] created. BB10 [083..0A1) New Basic Block BB11 [0010] created. BB11 [0A1..0AA) New Basic Block BB12 [0011] created. BB12 [0AA..0AF) New Basic Block BB13 [0012] created. BB13 [0AF..0B8) New Basic Block BB14 [0013] created. BB14 [0B8..0C1) New Basic Block BB15 [0014] created. BB15 [0C1..0CA) New Basic Block BB16 [0015] created. BB16 [0CA..0CF) New Basic Block BB17 [0016] created. BB17 [0CF..0D8) New Basic Block BB18 [0017] created. BB18 [0D8..0E0) New Basic Block BB19 [0018] created. BB19 [0E0..0E2) New Basic Block BB20 [0019] created. BB20 [0E2..0ED) New Basic Block BB21 [0020] created. BB21 [0ED..0F4) New Basic Block BB22 [0021] created. BB22 [0F4..0FB) New Basic Block BB23 [0022] created. BB23 [0FB..102) New Basic Block BB24 [0023] created. BB24 [102..109) New Basic Block BB25 [0024] created. BB25 [109..10E) New Basic Block BB26 [0025] created. BB26 [10E..113) New Basic Block BB27 [0026] created. BB27 [113..11E) New Basic Block BB28 [0027] created. BB28 [11E..121) New Basic Block BB29 [0028] created. BB29 [121..12C) New Basic Block BB30 [0029] created. BB30 [12C..137) New Basic Block BB31 [0030] created. BB31 [137..142) New Basic Block BB32 [0031] created. BB32 [142..150) New Basic Block BB33 [0032] created. BB33 [150..15E) New Basic Block BB34 [0033] created. BB34 [15E..170) New Basic Block BB35 [0034] created. BB35 [170..175) New Basic Block BB36 [0035] created. BB36 [175..183) New Basic Block BB37 [0036] created. BB37 [183..18E) New Basic Block BB38 [0037] created. BB38 [18E..196) New Basic Block BB39 [0038] created. BB39 [196..1A1) New Basic Block BB40 [0039] created. BB40 [1A1..1AE) New Basic Block BB41 [0040] created. BB41 [1AE..1BB) New Basic Block BB42 [0041] created. BB42 [1BB..1C8) New Basic Block BB43 [0042] created. BB43 [1C8..1D5) New Basic Block BB44 [0043] created. BB44 [1D5..1E4) New Basic Block BB45 [0044] created. BB45 [1E4..1F4) New Basic Block BB46 [0045] created. BB46 [1F4..201) New Basic Block BB47 [0046] created. BB47 [201..204) New Basic Block BB48 [0047] created. BB48 [204..20F) New Basic Block BB49 [0048] created. BB49 [20F..222) New Basic Block BB50 [0049] created. BB50 [222..22B) New Basic Block BB51 [0050] created. BB51 [22B..233) New Basic Block BB52 [0051] created. BB52 [233..235) New Basic Block BB53 [0052] created. BB53 [235..23A) New Basic Block BB54 [0053] created. BB54 [23A..23F) New Basic Block BB55 [0054] created. BB55 [23F..24A) New Basic Block BB56 [0055] created. BB56 [24A..24D) New Basic Block BB57 [0056] created. BB57 [24D..252) New Basic Block BB58 [0057] created. BB58 [252..262) New Basic Block BB59 [0058] created. BB59 [262..26E) New Basic Block BB60 [0059] created. BB60 [26E..26F) New Basic Block BB61 [0060] created. BB61 [26F..27F) New Basic Block BB62 [0061] created. BB62 [27F..28E) New Basic Block BB63 [0062] created. BB63 [28E..297) New Basic Block BB64 [0063] created. BB64 [297..2A0) New Basic Block BB65 [0064] created. BB65 [2A0..2A7) New Basic Block BB66 [0065] created. BB66 [2A7..2AE) New Basic Block BB67 [0066] created. BB67 [2AE..2B2) New Basic Block BB68 [0067] created. BB68 [2B2..2B5) New Basic Block BB69 [0068] created. BB69 [2B5..2B8) New Basic Block BB70 [0069] created. BB70 [2B8..2BD) New Basic Block BB71 [0070] created. BB71 [2BD..2C0) New Basic Block BB72 [0071] created. BB72 [2C0..2C3) New Basic Block BB73 [0072] created. BB73 [2C3..2C8) New Basic Block BB74 [0073] created. BB74 [2C8..2D0) New Basic Block BB75 [0074] created. BB75 [2D0..2D9) New Basic Block BB76 [0075] created. BB76 [2D9..2DC) New Basic Block BB77 [0076] created. BB77 [2DC..2E2) New Basic Block BB78 [0077] created. BB78 [2E2..2EE) New Basic Block BB79 [0078] created. BB79 [2EE..30D) New Basic Block BB80 [0079] created. BB80 [30D..31E) New Basic Block BB81 [0080] created. BB81 [31E..336) New Basic Block BB82 [0081] created. BB82 [336..33D) New Basic Block BB83 [0082] created. BB83 [33D..348) New Basic Block BB84 [0083] created. BB84 [348..34B) New Basic Block BB85 [0084] created. BB85 [34B..34D) New Basic Block BB86 [0085] created. BB86 [34D..355) New Basic Block BB87 [0086] created. BB87 [355..359) New Basic Block BB88 [0087] created. BB88 [359..35A) New Basic Block BB89 [0088] created. BB89 [35A..35E) New Basic Block BB90 [0089] created. BB90 [35E..362) New Basic Block BB91 [0090] created. BB91 [362..373) New Basic Block BB92 [0091] created. BB92 [373..39A) New Basic Block BB93 [0092] created. BB93 [39A..3AE) New Basic Block BB94 [0093] created. BB94 [3AE..3BB) New Basic Block BB95 [0094] created. BB95 [3BB..3C2) New Basic Block BB96 [0095] created. BB96 [3C2..3C8) New Basic Block BB97 [0096] created. BB97 [3C8..3D0) New Basic Block BB98 [0097] created. BB98 [3D0..3D4) New Basic Block BB99 [0098] created. BB99 [3D4..3DC) New Basic Block BB100 [0099] created. BB100 [3DC..3E8) New Basic Block BB101 [0100] created. BB101 [3E8..401) New Basic Block BB102 [0101] created. BB102 [401..406) New Basic Block BB103 [0102] created. BB103 [406..40C) New Basic Block BB104 [0103] created. BB104 [40C..412) New Basic Block BB105 [0104] created. BB105 [412..418) New Basic Block BB106 [0105] created. BB106 [418..41A) New Basic Block BB107 [0106] created. BB107 [41A..420) New Basic Block BB108 [0107] created. BB108 [420..424) New Basic Block BB109 [0108] created. BB109 [424..42C) New Basic Block BB110 [0109] created. BB110 [42C..435) New Basic Block BB111 [0110] created. BB111 [435..43A) New Basic Block BB112 [0111] created. BB112 [43A..43F) New Basic Block BB113 [0112] created. BB113 [43F..44F) New Basic Block BB114 [0113] created. BB114 [44F..461) New Basic Block BB115 [0114] created. BB115 [461..46D) New Basic Block BB116 [0115] created. BB116 [46D..472) New Basic Block BB117 [0116] created. BB117 [472..478) New Basic Block BB118 [0117] created. BB118 [478..49A) New Basic Block BB119 [0118] created. BB119 [49A..4B8) New Basic Block BB120 [0119] created. BB120 [4B8..4C1) New Basic Block BB121 [0120] created. BB121 [4C1..4C6) New Basic Block BB122 [0121] created. BB122 [4C6..4CF) New Basic Block BB123 [0122] created. BB123 [4CF..4D8) New Basic Block BB124 [0123] created. BB124 [4D8..4E4) New Basic Block BB125 [0124] created. BB125 [4E4..4E9) New Basic Block BB126 [0125] created. BB126 [4E9..4EE) New Basic Block BB127 [0126] created. BB127 [4EE..4F9) New Basic Block BB128 [0127] created. BB128 [4F9..4FC) New Basic Block BB129 [0128] created. BB129 [4FC..4FE) New Basic Block BB130 [0129] created. BB130 [4FE..502) New Basic Block BB131 [0130] created. BB131 [502..507) New Basic Block BB132 [0131] created. BB132 [507..50C) New Basic Block BB133 [0132] created. BB133 [50C..50F) New Basic Block BB134 [0133] created. BB134 [50F..513) New Basic Block BB135 [0134] created. BB135 [513..51B) New Basic Block BB136 [0135] created. BB136 [51B..51D) New Basic Block BB137 [0136] created. BB137 [51D..521) New Basic Block BB138 [0137] created. BB138 [521..52D) New Basic Block BB139 [0138] created. BB139 [52D..532) New Basic Block BB140 [0139] created. BB140 [532..537) New Basic Block BB141 [0140] created. BB141 [537..547) New Basic Block BB142 [0141] created. BB142 [547..559) New Basic Block BB143 [0142] created. BB143 [559..564) New Basic Block BB144 [0143] created. BB144 [564..571) New Basic Block BB145 [0144] created. BB145 [571..575) New Basic Block BB146 [0145] created. BB146 [575..57C) New Basic Block BB147 [0146] created. BB147 [57C..584) New Basic Block BB148 [0147] created. BB148 [584..598) New Basic Block BB149 [0148] created. BB149 [598..5A9) New Basic Block BB150 [0149] created. BB150 [5A9..5BA) New Basic Block BB151 [0150] created. BB151 [5BA..5CE) New Basic Block BB152 [0151] created. BB152 [5CE..5D9) New Basic Block BB153 [0152] created. BB153 [5D9..5E4) New Basic Block BB154 [0153] created. BB154 [5E4..5F1) New Basic Block BB155 [0154] created. BB155 [5F1..5FF) New Basic Block BB156 [0155] created. BB156 [5FF..60D) New Basic Block BB157 [0156] created. BB157 [60D..618) New Basic Block BB158 [0157] created. BB158 [618..626) New Basic Block BB159 [0158] created. BB159 [626..634) New Basic Block BB160 [0159] created. BB160 [634..64D) New Basic Block BB161 [0160] created. BB161 [64D..65A) New Basic Block BB162 [0161] created. BB162 [65A..665) New Basic Block BB163 [0162] created. BB163 [665..672) New Basic Block BB164 [0163] created. BB164 [672..67A) New Basic Block BB165 [0164] created. BB165 [67A..687) New Basic Block BB166 [0165] created. BB166 [687..694) New Basic Block BB167 [0166] created. BB167 [694..6A3) New Basic Block BB168 [0167] created. BB168 [6A3..6A8) New Basic Block BB169 [0168] created. BB169 [6A8..6B5) New Basic Block BB170 [0169] created. BB170 [6B5..6C2) New Basic Block BB171 [0170] created. BB171 [6C2..6D1) New Basic Block BB172 [0171] created. BB172 [6D1..6DE) New Basic Block BB173 [0172] created. BB173 [6DE..6E4) New Basic Block BB174 [0173] created. BB174 [6E4..6F4) New Basic Block BB175 [0174] created. BB175 [6F4..701) New Basic Block BB176 [0175] created. BB176 [701..707) New Basic Block BB177 [0176] created. BB177 [707..70B) New Basic Block BB178 [0177] created. BB178 [70B..710) New Basic Block BB179 [0178] created. BB179 [710..71A) New Basic Block BB180 [0179] created. BB180 [71A..71B) New Basic Block BB181 [0180] created. BB181 [71B..731) New Basic Block BB182 [0181] created. BB182 [731..744) New Basic Block BB183 [0182] created. BB183 [744..751) New Basic Block BB184 [0183] created. BB184 [751..75E) New Basic Block BB185 [0184] created. BB185 [75E..774) New Basic Block BB186 [0185] created. BB186 [774..788) New Basic Block BB187 [0186] created. BB187 [788..793) New Basic Block BB188 [0187] created. BB188 [793..7A0) New Basic Block BB189 [0188] created. BB189 [7A0..7A2) New Basic Block BB190 [0189] created. BB190 [7A2..7AA) New Basic Block BB191 [0190] created. BB191 [7AA..7B5) New Basic Block BB192 [0191] created. BB192 [7B5..7C8) New Basic Block BB193 [0192] created. BB193 [7C8..7D1) New Basic Block BB194 [0193] created. BB194 [7D1..7DD) New Basic Block BB195 [0194] created. BB195 [7DD..7E1) New Basic Block BB196 [0195] created. BB196 [7E1..7E9) New Basic Block BB197 [0196] created. BB197 [7E9..7F2) New Basic Block BB198 [0197] created. BB198 [7F2..7FF) New Basic Block BB199 [0198] created. BB199 [7FF..800) INLINER: during 'prejit' result 'failed this callee' reason 'too many locals' for 'n/a' calling 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' INLINER: Marking System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) as NOINLINE because of too many locals INLINER: during 'prejit' result 'failed this callee' reason 'too many locals' IL Code Size,Instr 2048, 996, Basic Block count 199, Local Variable Num,Ref count 41,391 for method System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) OPTIONS: opts.MinOpts() == false Basic block list for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) BB02 [0001] 1 1 [017..01F)-> BB04 ( cond ) BB03 [0002] 1 1 [01F..022)-> BB06 (always) BB04 [0003] 1 1 [022..025)-> BB06 (always) BB05 [0004] 1 1 [025..026) BB06 [0005] 3 1 [026..02D) BB07 [0006] 2 1 [02D..05B)-> BB48 (always) bwd bwd-target BB08 [0007] 1 1 [05B..061)-> BB13 ( cond ) bwd bwd-target BB09 [0008] 1 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) bwd BB10 [0009] 1 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) bwd BB11 [0010] 1 1 [0A1..0AA)-> BB39 ( cond ) bwd BB12 [0011] 1 1 [0AA..0AF)-> BB48 (always) bwd BB13 [0012] 1 1 [0AF..0B8)-> BB36 ( cond ) bwd BB14 [0013] 1 1 [0B8..0C1)-> BB39 ( cond ) bwd BB15 [0014] 1 1 [0C1..0CA)-> BB31 ( cond ) bwd BB16 [0015] 1 1 [0CA..0CF)-> BB48 (always) bwd BB17 [0016] 1 1 [0CF..0D8)-> BB48 (always) bwd BB18 [0017] 1 1 [0D8..0E0)-> BB20 ( cond ) bwd BB19 [0018] 1 1 [0E0..0E2) bwd BB20 [0019] 2 1 [0E2..0ED)-> BB48 (always) bwd BB21 [0020] 1 1 [0ED..0F4)-> BB48 ( cond ) bwd BB22 [0021] 1 1 [0F4..0FB)-> BB48 (always) bwd BB23 [0022] 1 1 [0FB..102)-> BB48 ( cond ) bwd BB24 [0023] 1 1 [102..109)-> BB48 ( cond ) bwd BB25 [0024] 1 1 [109..10E)-> BB29 ( cond ) bwd BB26 [0025] 1 1 [10E..113)-> BB28 ( cond ) bwd BB27 [0026] 1 1 [113..11E)-> BB48 (always) bwd BB28 [0027] 1 1 [11E..121) bwd BB29 [0028] 2 1 [121..12C)-> BB48 (always) bwd BB30 [0029] 1 1 [12C..137)-> BB48 (always) bwd BB31 [0030] 1 1 [137..142)-> BB48 (always) bwd BB32 [0031] 3 1 [142..150)-> BB48 ( cond ) bwd bwd-target BB33 [0032] 1 1 [150..15E)-> BB48 ( cond ) bwd BB34 [0033] 1 1 [15E..170)-> BB32 ( cond ) bwd bwd-src BB35 [0034] 1 1 [170..175)-> BB48 (always) bwd BB36 [0035] 1 1 [175..183)-> BB48 ( cond ) bwd BB37 [0036] 1 1 [183..18E)-> BB48 ( cond ) bwd BB38 [0037] 1 1 [18E..196)-> BB48 (always) bwd BB39 [0038] 2 1 [196..1A1)-> BB41 ( cond ) bwd BB40 [0039] 1 1 [1A1..1AE)-> BB45 ( cond ) bwd BB41 [0040] 2 1 [1AE..1BB)-> BB48 ( cond ) bwd BB42 [0041] 1 1 [1BB..1C8)-> BB44 ( cond ) bwd BB43 [0042] 1 1 [1C8..1D5)-> BB48 ( cond ) bwd BB44 [0043] 2 1 [1D5..1E4)-> BB48 ( cond ) bwd BB45 [0044] 3 1 [1E4..1F4)-> BB47 ( cond ) bwd bwd-target BB46 [0045] 1 1 [1F4..201)-> BB45 ( cond ) bwd bwd-src BB47 [0046] 2 1 [201..204) bwd BB48 [0047] 27 1 [204..20F)-> BB51 ( cond ) bwd BB49 [0048] 1 1 [20F..222)-> BB51 ( cond ) bwd BB50 [0049] 1 1 [222..22B)-> BB08 ( cond ) bwd bwd-src BB51 [0050] 3 1 [22B..233)-> BB53 ( cond ) bwd BB52 [0051] 1 1 [233..235) bwd BB53 [0052] 2 1 [235..23A)-> BB57 ( cond ) bwd BB54 [0053] 1 1 [23A..23F)-> BB56 ( cond ) bwd BB55 [0054] 1 1 [23F..24A)-> BB57 (always) bwd BB56 [0055] 1 1 [24A..24D) bwd BB57 [0056] 3 1 [24D..252)-> BB64 ( cond ) bwd BB58 [0057] 1 1 [252..262)-> BB60 ( cond ) bwd BB59 [0058] 1 1 [262..26E)-> BB61 (always) bwd BB60 [0059] 1 1 [26E..26F) bwd BB61 [0060] 2 1 [26F..27F)-> BB67 ( cond ) bwd BB62 [0061] 1 1 [27F..28E)-> BB67 ( cond ) bwd BB63 [0062] 1 1 [28E..297)-> BB07 (always) bwd bwd-src BB64 [0063] 1 1 [297..2A0)-> BB66 ( cond ) BB65 [0064] 1 1 [2A0..2A7) BB66 [0065] 2 1 [2A7..2AE) BB67 [0066] 3 1 [2AE..2B2)-> BB69 ( cond ) BB68 [0067] 1 1 [2B2..2B5)-> BB70 (always) BB69 [0068] 1 1 [2B5..2B8) BB70 [0069] 2 1 [2B8..2BD)-> BB72 ( cond ) BB71 [0070] 1 1 [2BD..2C0)-> BB73 (always) BB72 [0071] 1 1 [2C0..2C3) BB73 [0072] 2 1 [2C3..2C8)-> BB75 ( cond ) BB74 [0073] 1 1 [2C8..2D0)-> BB79 (always) BB75 [0074] 1 1 [2D0..2D9)-> BB77 ( cond ) BB76 [0075] 1 1 [2D9..2DC)-> BB78 (always) BB77 [0076] 1 1 [2DC..2E2) BB78 [0077] 2 1 [2E2..2EE) BB79 [0078] 2 1 [2EE..30D)-> BB97 ( cond ) BB80 [0079] 1 1 [30D..31E)-> BB97 ( cond ) BB81 [0080] 1 1 [31E..336)-> BB83 ( cond ) BB82 [0081] 1 1 [336..33D) BB83 [0082] 2 1 [33D..348)-> BB85 ( cond ) BB84 [0083] 1 1 [348..34B)-> BB86 (always) BB85 [0084] 1 1 [34B..34D) BB86 [0085] 2 1 [34D..355)-> BB88 ( cond ) BB87 [0086] 1 1 [355..359)-> BB89 (always) BB88 [0087] 1 1 [359..35A) BB89 [0088] 2 1 [35A..35E)-> BB96 (always) BB90 [0089] 1 1 [35E..362)-> BB97 ( cond ) bwd bwd-target BB91 [0090] 1 1 [362..373)-> BB93 ( cond ) bwd BB92 [0091] 1 1 [373..39A) bwd BB93 [0092] 2 1 [39A..3AE)-> BB95 ( cond ) bwd BB94 [0093] 1 1 [3AE..3BB) bwd BB95 [0094] 2 1 [3BB..3C2) bwd BB96 [0095] 2 1 [3C2..3C8)-> BB90 ( cond ) bwd bwd-src BB97 [0096] 4 1 [3C8..3D0)-> BB101 ( cond ) BB98 [0097] 1 1 [3D0..3D4)-> BB101 ( cond ) BB99 [0098] 1 1 [3D4..3DC)-> BB101 ( cond ) BB100 [0099] 1 1 [3DC..3E8) BB101 [0100] 4 1 [3E8..401)-> BB191 (always) BB102 [0101] 1 1 [401..406)-> BB117 ( cond ) bwd bwd-target BB103 [0102] 1 1 [406..40C)-> BB116 ( cond ) bwd BB104 [0103] 1 1 [40C..412)-> BB116 ( cond ) bwd BB105 [0104] 1 1 [412..418)-> BB116 ( cond ) bwd BB106 [0105] 1 1 [418..41A)-> BB117 (always) bwd BB107 [0106] 1 1 [41A..420)-> BB109 ( cond ) bwd bwd-target BB108 [0107] 1 1 [420..424)-> BB110 (always) bwd BB109 [0108] 1 1 [424..42C) bwd BB110 [0109] 2 1 [42C..435)-> BB115 ( cond ) bwd BB111 [0110] 1 1 [435..43A)-> BB115 ( cond ) bwd BB112 [0111] 1 1 [43A..43F)-> BB115 ( cond ) bwd BB113 [0112] 1 1 [43F..44F)-> BB115 ( cond ) bwd BB114 [0113] 1 1 [44F..461) bwd BB115 [0114] 5 1 [461..46D) bwd BB116 [0115] 4 1 [46D..472)-> BB107 ( cond ) bwd bwd-src BB117 [0116] 3 1 [472..478)-> BB122 ( cond ) bwd BB118 [0117] 1 1 [478..49A)-> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch) bwd BB119 [0118] 1 1 [49A..4B8)-> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch) bwd BB120 [0119] 1 1 [4B8..4C1)-> BB161 ( cond ) bwd BB121 [0120] 1 1 [4C1..4C6)-> BB190 (always) bwd BB122 [0121] 1 1 [4C6..4CF)-> BB158 ( cond ) bwd BB123 [0122] 1 1 [4CF..4D8)-> BB161 ( cond ) bwd BB124 [0123] 1 1 [4D8..4E4)-> BB149 ( cond ) bwd BB125 [0124] 1 1 [4E4..4E9)-> BB190 (always) bwd BB126 [0125] 2 1 [4E9..4EE)-> BB131 ( cond ) bwd BB127 [0126] 1 1 [4EE..4F9)-> BB129 ( cond ) bwd BB128 [0127] 1 1 [4F9..4FC)-> BB130 (always) bwd BB129 [0128] 1 1 [4FC..4FE) bwd BB130 [0129] 2 1 [4FE..502)-> BB137 (always) bwd BB131 [0130] 1 1 [502..507)-> BB135 ( cond ) bwd BB132 [0131] 1 1 [507..50C)-> BB134 ( cond ) bwd BB133 [0132] 1 1 [50C..50F)-> BB136 (always) bwd BB134 [0133] 1 1 [50F..513)-> BB136 (always) bwd BB135 [0134] 1 1 [513..51B) bwd BB136 [0135] 3 1 [51B..51D) bwd BB137 [0136] 2 1 [51D..521)-> BB143 ( cond ) bwd BB138 [0137] 1 1 [521..52D)-> BB143 ( cond ) bwd BB139 [0138] 1 1 [52D..532)-> BB143 ( cond ) bwd BB140 [0139] 1 1 [532..537)-> BB143 ( cond ) bwd BB141 [0140] 1 1 [537..547)-> BB143 ( cond ) bwd BB142 [0141] 1 1 [547..559) bwd BB143 [0142] 6 1 [559..564)-> BB191 (always) bwd BB144 [0143] 1 1 [564..571)-> BB191 ( cond ) bwd BB145 [0144] 1 1 [571..575)-> BB148 ( cond ) bwd BB146 [0145] 1 1 [575..57C)-> BB191 ( cond ) bwd BB147 [0146] 1 1 [57C..584)-> BB191 ( cond ) bwd BB148 [0147] 2 1 [584..598)-> BB191 (always) bwd BB149 [0148] 1 1 [598..5A9)-> BB191 (always) bwd BB150 [0149] 1 1 [5A9..5BA)-> BB191 (always) bwd BB151 [0150] 1 1 [5BA..5CE) bwd bwd-target BB152 [0151] 3 1 [5CE..5D9)-> BB155 ( cond ) bwd BB153 [0152] 1 1 [5D9..5E4)-> BB155 ( cond ) bwd BB154 [0153] 1 1 [5E4..5F1)-> BB151 ( cond ) bwd bwd-src BB155 [0154] 3 1 [5F1..5FF)-> BB191 ( cond ) bwd BB156 [0155] 1 1 [5FF..60D)-> BB191 ( cond ) bwd BB157 [0156] 1 1 [60D..618)-> BB191 (always) bwd BB158 [0157] 1 1 [618..626)-> BB191 ( cond ) bwd BB159 [0158] 1 1 [626..634)-> BB191 ( cond ) bwd BB160 [0159] 1 1 [634..64D)-> BB191 (always) bwd BB161 [0160] 2 1 [64D..65A)-> BB182 ( cond ) bwd BB162 [0161] 1 1 [65A..665)-> BB165 ( cond ) bwd BB163 [0162] 1 1 [665..672)-> BB165 ( cond ) bwd BB164 [0163] 1 1 [672..67A)-> BB174 (always) bwd BB165 [0164] 2 1 [67A..687)-> BB169 ( cond ) bwd BB166 [0165] 1 1 [687..694)-> BB169 ( cond ) bwd BB167 [0166] 1 1 [694..6A3)-> BB169 ( cond ) bwd BB168 [0167] 1 1 [6A3..6A8)-> BB174 (always) bwd BB169 [0168] 3 1 [6A8..6B5)-> BB172 ( cond ) bwd BB170 [0169] 1 1 [6B5..6C2)-> BB172 ( cond ) bwd BB171 [0170] 1 1 [6C2..6D1)-> BB174 ( cond ) bwd BB172 [0171] 3 1 [6D1..6DE)-> BB191 (always) bwd BB173 [0172] 1 1 [6DE..6E4) bwd bwd-target BB174 [0173] 4 1 [6E4..6F4)-> BB176 ( cond ) bwd BB175 [0174] 1 1 [6F4..701)-> BB173 ( cond ) bwd bwd-src BB176 [0175] 2 1 [701..707)-> BB178 ( cond ) bwd BB177 [0176] 1 1 [707..70B) bwd BB178 [0177] 2 1 [70B..710)-> BB180 ( cond ) bwd BB179 [0178] 1 1 [710..71A)-> BB181 (always) bwd BB180 [0179] 1 1 [71A..71B) bwd BB181 [0180] 2 1 [71B..731)-> BB191 (always) bwd BB182 [0181] 1 1 [731..744)-> BB191 ( cond ) bwd BB183 [0182] 1 1 [744..751)-> BB185 ( cond ) bwd BB184 [0183] 1 1 [751..75E)-> BB187 ( cond ) bwd BB185 [0184] 2 1 [75E..774)-> BB187 (always) bwd BB186 [0185] 1 1 [774..788) bwd bwd-target BB187 [0186] 3 1 [788..793)-> BB191 ( cond ) bwd BB188 [0187] 1 1 [793..7A0)-> BB186 ( cond ) bwd bwd-src BB189 [0188] 1 1 [7A0..7A2)-> BB191 (always) bwd BB190 [0189] 6 1 [7A2..7AA) bwd BB191 [0190] 21 1 [7AA..7B5)-> BB194 ( cond ) bwd BB192 [0191] 1 1 [7B5..7C8)-> BB194 ( cond ) bwd BB193 [0192] 1 1 [7C8..7D1)-> BB102 ( cond ) bwd bwd-src BB194 [0193] 3 1 [7D1..7DD)-> BB199 ( cond ) BB195 [0194] 1 1 [7DD..7E1)-> BB199 ( cond ) BB196 [0195] 1 1 [7E1..7E9)-> BB199 ( cond ) BB197 [0196] 1 1 [7E9..7F2)-> BB199 ( cond ) BB198 [0197] 1 1 [7F2..7FF) BB199 [0198] 5 1 [7FF..800) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) BB02 [0001] 1 1 [017..01F)-> BB04 ( cond ) BB03 [0002] 1 1 [01F..022)-> BB06 (always) BB04 [0003] 1 1 [022..025)-> BB06 (always) BB05 [0004] 1 1 [025..026) BB06 [0005] 3 1 [026..02D) BB07 [0006] 2 1 [02D..05B)-> BB48 (always) bwd bwd-target BB08 [0007] 1 1 [05B..061)-> BB13 ( cond ) bwd bwd-target BB09 [0008] 1 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) bwd BB10 [0009] 1 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) bwd BB11 [0010] 1 1 [0A1..0AA)-> BB39 ( cond ) bwd BB12 [0011] 1 1 [0AA..0AF)-> BB48 (always) bwd BB13 [0012] 1 1 [0AF..0B8)-> BB36 ( cond ) bwd BB14 [0013] 1 1 [0B8..0C1)-> BB39 ( cond ) bwd BB15 [0014] 1 1 [0C1..0CA)-> BB31 ( cond ) bwd BB16 [0015] 1 1 [0CA..0CF)-> BB48 (always) bwd BB17 [0016] 1 1 [0CF..0D8)-> BB48 (always) bwd BB18 [0017] 1 1 [0D8..0E0)-> BB20 ( cond ) bwd BB19 [0018] 1 1 [0E0..0E2) bwd BB20 [0019] 2 1 [0E2..0ED)-> BB48 (always) bwd BB21 [0020] 1 1 [0ED..0F4)-> BB48 ( cond ) bwd BB22 [0021] 1 1 [0F4..0FB)-> BB48 (always) bwd BB23 [0022] 1 1 [0FB..102)-> BB48 ( cond ) bwd BB24 [0023] 1 1 [102..109)-> BB48 ( cond ) bwd BB25 [0024] 1 1 [109..10E)-> BB29 ( cond ) bwd BB26 [0025] 1 1 [10E..113)-> BB28 ( cond ) bwd BB27 [0026] 1 1 [113..11E)-> BB48 (always) bwd BB28 [0027] 1 1 [11E..121) bwd BB29 [0028] 2 1 [121..12C)-> BB48 (always) bwd BB30 [0029] 1 1 [12C..137)-> BB48 (always) bwd BB31 [0030] 1 1 [137..142)-> BB48 (always) bwd BB32 [0031] 3 1 [142..150)-> BB48 ( cond ) bwd bwd-target BB33 [0032] 1 1 [150..15E)-> BB48 ( cond ) bwd BB34 [0033] 1 1 [15E..170)-> BB32 ( cond ) bwd bwd-src BB35 [0034] 1 1 [170..175)-> BB48 (always) bwd BB36 [0035] 1 1 [175..183)-> BB48 ( cond ) bwd BB37 [0036] 1 1 [183..18E)-> BB48 ( cond ) bwd BB38 [0037] 1 1 [18E..196)-> BB48 (always) bwd BB39 [0038] 2 1 [196..1A1)-> BB41 ( cond ) bwd BB40 [0039] 1 1 [1A1..1AE)-> BB45 ( cond ) bwd BB41 [0040] 2 1 [1AE..1BB)-> BB48 ( cond ) bwd BB42 [0041] 1 1 [1BB..1C8)-> BB44 ( cond ) bwd BB43 [0042] 1 1 [1C8..1D5)-> BB48 ( cond ) bwd BB44 [0043] 2 1 [1D5..1E4)-> BB48 ( cond ) bwd BB45 [0044] 3 1 [1E4..1F4)-> BB47 ( cond ) bwd bwd-target BB46 [0045] 1 1 [1F4..201)-> BB45 ( cond ) bwd bwd-src BB47 [0046] 2 1 [201..204) bwd BB48 [0047] 27 1 [204..20F)-> BB51 ( cond ) bwd BB49 [0048] 1 1 [20F..222)-> BB51 ( cond ) bwd BB50 [0049] 1 1 [222..22B)-> BB08 ( cond ) bwd bwd-src BB51 [0050] 3 1 [22B..233)-> BB53 ( cond ) bwd BB52 [0051] 1 1 [233..235) bwd BB53 [0052] 2 1 [235..23A)-> BB57 ( cond ) bwd BB54 [0053] 1 1 [23A..23F)-> BB56 ( cond ) bwd BB55 [0054] 1 1 [23F..24A)-> BB57 (always) bwd BB56 [0055] 1 1 [24A..24D) bwd BB57 [0056] 3 1 [24D..252)-> BB64 ( cond ) bwd BB58 [0057] 1 1 [252..262)-> BB60 ( cond ) bwd BB59 [0058] 1 1 [262..26E)-> BB61 (always) bwd BB60 [0059] 1 1 [26E..26F) bwd BB61 [0060] 2 1 [26F..27F)-> BB67 ( cond ) bwd BB62 [0061] 1 1 [27F..28E)-> BB67 ( cond ) bwd BB63 [0062] 1 1 [28E..297)-> BB07 (always) bwd bwd-src BB64 [0063] 1 1 [297..2A0)-> BB66 ( cond ) BB65 [0064] 1 1 [2A0..2A7) BB66 [0065] 2 1 [2A7..2AE) BB67 [0066] 3 1 [2AE..2B2)-> BB69 ( cond ) BB68 [0067] 1 1 [2B2..2B5)-> BB70 (always) BB69 [0068] 1 1 [2B5..2B8) BB70 [0069] 2 1 [2B8..2BD)-> BB72 ( cond ) BB71 [0070] 1 1 [2BD..2C0)-> BB73 (always) BB72 [0071] 1 1 [2C0..2C3) BB73 [0072] 2 1 [2C3..2C8)-> BB75 ( cond ) BB74 [0073] 1 1 [2C8..2D0)-> BB79 (always) BB75 [0074] 1 1 [2D0..2D9)-> BB77 ( cond ) BB76 [0075] 1 1 [2D9..2DC)-> BB78 (always) BB77 [0076] 1 1 [2DC..2E2) BB78 [0077] 2 1 [2E2..2EE) BB79 [0078] 2 1 [2EE..30D)-> BB97 ( cond ) BB80 [0079] 1 1 [30D..31E)-> BB97 ( cond ) BB81 [0080] 1 1 [31E..336)-> BB83 ( cond ) BB82 [0081] 1 1 [336..33D) BB83 [0082] 2 1 [33D..348)-> BB85 ( cond ) BB84 [0083] 1 1 [348..34B)-> BB86 (always) BB85 [0084] 1 1 [34B..34D) BB86 [0085] 2 1 [34D..355)-> BB88 ( cond ) BB87 [0086] 1 1 [355..359)-> BB89 (always) BB88 [0087] 1 1 [359..35A) BB89 [0088] 2 1 [35A..35E)-> BB96 (always) BB90 [0089] 1 1 [35E..362)-> BB97 ( cond ) bwd bwd-target BB91 [0090] 1 1 [362..373)-> BB93 ( cond ) bwd BB92 [0091] 1 1 [373..39A) bwd BB93 [0092] 2 1 [39A..3AE)-> BB95 ( cond ) bwd BB94 [0093] 1 1 [3AE..3BB) bwd BB95 [0094] 2 1 [3BB..3C2) bwd BB96 [0095] 2 1 [3C2..3C8)-> BB90 ( cond ) bwd bwd-src BB97 [0096] 4 1 [3C8..3D0)-> BB101 ( cond ) BB98 [0097] 1 1 [3D0..3D4)-> BB101 ( cond ) BB99 [0098] 1 1 [3D4..3DC)-> BB101 ( cond ) BB100 [0099] 1 1 [3DC..3E8) BB101 [0100] 4 1 [3E8..401)-> BB191 (always) BB102 [0101] 1 1 [401..406)-> BB117 ( cond ) bwd bwd-target BB103 [0102] 1 1 [406..40C)-> BB116 ( cond ) bwd BB104 [0103] 1 1 [40C..412)-> BB116 ( cond ) bwd BB105 [0104] 1 1 [412..418)-> BB116 ( cond ) bwd BB106 [0105] 1 1 [418..41A)-> BB117 (always) bwd BB107 [0106] 1 1 [41A..420)-> BB109 ( cond ) bwd bwd-target BB108 [0107] 1 1 [420..424)-> BB110 (always) bwd BB109 [0108] 1 1 [424..42C) bwd BB110 [0109] 2 1 [42C..435)-> BB115 ( cond ) bwd BB111 [0110] 1 1 [435..43A)-> BB115 ( cond ) bwd BB112 [0111] 1 1 [43A..43F)-> BB115 ( cond ) bwd BB113 [0112] 1 1 [43F..44F)-> BB115 ( cond ) bwd BB114 [0113] 1 1 [44F..461) bwd BB115 [0114] 5 1 [461..46D) bwd BB116 [0115] 4 1 [46D..472)-> BB107 ( cond ) bwd bwd-src BB117 [0116] 3 1 [472..478)-> BB122 ( cond ) bwd BB118 [0117] 1 1 [478..49A)-> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch) bwd BB119 [0118] 1 1 [49A..4B8)-> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch) bwd BB120 [0119] 1 1 [4B8..4C1)-> BB161 ( cond ) bwd BB121 [0120] 1 1 [4C1..4C6)-> BB190 (always) bwd BB122 [0121] 1 1 [4C6..4CF)-> BB158 ( cond ) bwd BB123 [0122] 1 1 [4CF..4D8)-> BB161 ( cond ) bwd BB124 [0123] 1 1 [4D8..4E4)-> BB149 ( cond ) bwd BB125 [0124] 1 1 [4E4..4E9)-> BB190 (always) bwd BB126 [0125] 2 1 [4E9..4EE)-> BB131 ( cond ) bwd BB127 [0126] 1 1 [4EE..4F9)-> BB129 ( cond ) bwd BB128 [0127] 1 1 [4F9..4FC)-> BB130 (always) bwd BB129 [0128] 1 1 [4FC..4FE) bwd BB130 [0129] 2 1 [4FE..502)-> BB137 (always) bwd BB131 [0130] 1 1 [502..507)-> BB135 ( cond ) bwd BB132 [0131] 1 1 [507..50C)-> BB134 ( cond ) bwd BB133 [0132] 1 1 [50C..50F)-> BB136 (always) bwd BB134 [0133] 1 1 [50F..513)-> BB136 (always) bwd BB135 [0134] 1 1 [513..51B) bwd BB136 [0135] 3 1 [51B..51D) bwd BB137 [0136] 2 1 [51D..521)-> BB143 ( cond ) bwd BB138 [0137] 1 1 [521..52D)-> BB143 ( cond ) bwd BB139 [0138] 1 1 [52D..532)-> BB143 ( cond ) bwd BB140 [0139] 1 1 [532..537)-> BB143 ( cond ) bwd BB141 [0140] 1 1 [537..547)-> BB143 ( cond ) bwd BB142 [0141] 1 1 [547..559) bwd BB143 [0142] 6 1 [559..564)-> BB191 (always) bwd BB144 [0143] 1 1 [564..571)-> BB191 ( cond ) bwd BB145 [0144] 1 1 [571..575)-> BB148 ( cond ) bwd BB146 [0145] 1 1 [575..57C)-> BB191 ( cond ) bwd BB147 [0146] 1 1 [57C..584)-> BB191 ( cond ) bwd BB148 [0147] 2 1 [584..598)-> BB191 (always) bwd BB149 [0148] 1 1 [598..5A9)-> BB191 (always) bwd BB150 [0149] 1 1 [5A9..5BA)-> BB191 (always) bwd BB151 [0150] 1 1 [5BA..5CE) bwd bwd-target BB152 [0151] 3 1 [5CE..5D9)-> BB155 ( cond ) bwd BB153 [0152] 1 1 [5D9..5E4)-> BB155 ( cond ) bwd BB154 [0153] 1 1 [5E4..5F1)-> BB151 ( cond ) bwd bwd-src BB155 [0154] 3 1 [5F1..5FF)-> BB191 ( cond ) bwd BB156 [0155] 1 1 [5FF..60D)-> BB191 ( cond ) bwd BB157 [0156] 1 1 [60D..618)-> BB191 (always) bwd BB158 [0157] 1 1 [618..626)-> BB191 ( cond ) bwd BB159 [0158] 1 1 [626..634)-> BB191 ( cond ) bwd BB160 [0159] 1 1 [634..64D)-> BB191 (always) bwd BB161 [0160] 2 1 [64D..65A)-> BB182 ( cond ) bwd BB162 [0161] 1 1 [65A..665)-> BB165 ( cond ) bwd BB163 [0162] 1 1 [665..672)-> BB165 ( cond ) bwd BB164 [0163] 1 1 [672..67A)-> BB174 (always) bwd BB165 [0164] 2 1 [67A..687)-> BB169 ( cond ) bwd BB166 [0165] 1 1 [687..694)-> BB169 ( cond ) bwd BB167 [0166] 1 1 [694..6A3)-> BB169 ( cond ) bwd BB168 [0167] 1 1 [6A3..6A8)-> BB174 (always) bwd BB169 [0168] 3 1 [6A8..6B5)-> BB172 ( cond ) bwd BB170 [0169] 1 1 [6B5..6C2)-> BB172 ( cond ) bwd BB171 [0170] 1 1 [6C2..6D1)-> BB174 ( cond ) bwd BB172 [0171] 3 1 [6D1..6DE)-> BB191 (always) bwd BB173 [0172] 1 1 [6DE..6E4) bwd bwd-target BB174 [0173] 4 1 [6E4..6F4)-> BB176 ( cond ) bwd BB175 [0174] 1 1 [6F4..701)-> BB173 ( cond ) bwd bwd-src BB176 [0175] 2 1 [701..707)-> BB178 ( cond ) bwd BB177 [0176] 1 1 [707..70B) bwd BB178 [0177] 2 1 [70B..710)-> BB180 ( cond ) bwd BB179 [0178] 1 1 [710..71A)-> BB181 (always) bwd BB180 [0179] 1 1 [71A..71B) bwd BB181 [0180] 2 1 [71B..731)-> BB191 (always) bwd BB182 [0181] 1 1 [731..744)-> BB191 ( cond ) bwd BB183 [0182] 1 1 [744..751)-> BB185 ( cond ) bwd BB184 [0183] 1 1 [751..75E)-> BB187 ( cond ) bwd BB185 [0184] 2 1 [75E..774)-> BB187 (always) bwd BB186 [0185] 1 1 [774..788) bwd bwd-target BB187 [0186] 3 1 [788..793)-> BB191 ( cond ) bwd BB188 [0187] 1 1 [793..7A0)-> BB186 ( cond ) bwd bwd-src BB189 [0188] 1 1 [7A0..7A2)-> BB191 (always) bwd BB190 [0189] 6 1 [7A2..7AA) bwd BB191 [0190] 21 1 [7AA..7B5)-> BB194 ( cond ) bwd BB192 [0191] 1 1 [7B5..7C8)-> BB194 ( cond ) bwd BB193 [0192] 1 1 [7C8..7D1)-> BB102 ( cond ) bwd bwd-src BB194 [0193] 3 1 [7D1..7DD)-> BB199 ( cond ) BB195 [0194] 1 1 [7DD..7E1)-> BB199 ( cond ) BB196 [0195] 1 1 [7E1..7E9)-> BB199 ( cond ) BB197 [0196] 1 1 [7E9..7F2)-> BB199 ( cond ) BB198 [0197] 1 1 [7F2..7FF) BB199 [0198] 5 1 [7FF..800) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ------------ BB02 [017..01F) -> BB04 (cond), preds={} succs={BB03,BB04} ------------ BB03 [01F..022) -> BB06 (always), preds={} succs={BB06} ------------ BB04 [022..025) -> BB06 (always), preds={} succs={BB06} ------------ BB05 [025..026), preds={} succs={BB06} ------------ BB06 [026..02D), preds={} succs={BB07} ------------ BB07 [02D..05B) -> BB48 (always), preds={} succs={BB48} ------------ BB08 [05B..061) -> BB13 (cond), preds={} succs={BB09,BB13} ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={} succs={BB10,BB17,BB30,BB32,BB48} ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={} succs={BB11,BB18,BB21,BB23,BB48} ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={} succs={BB12,BB39} ------------ BB12 [0AA..0AF) -> BB48 (always), preds={} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={} succs={BB14,BB36} ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={} succs={BB15,BB39} ------------ BB15 [0C1..0CA) -> BB31 (cond), preds={} succs={BB16,BB31} ------------ BB16 [0CA..0CF) -> BB48 (always), preds={} succs={BB48} ------------ BB17 [0CF..0D8) -> BB48 (always), preds={} succs={BB48} ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={} succs={BB19,BB20} ------------ BB19 [0E0..0E2), preds={} succs={BB20} ------------ BB20 [0E2..0ED) -> BB48 (always), preds={} succs={BB48} ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={} succs={BB22,BB48} ------------ BB22 [0F4..0FB) -> BB48 (always), preds={} succs={BB48} ------------ BB23 [0FB..102) -> BB48 (cond), preds={} succs={BB24,BB48} ------------ BB24 [102..109) -> BB48 (cond), preds={} succs={BB25,BB48} ------------ BB25 [109..10E) -> BB29 (cond), preds={} succs={BB26,BB29} ------------ BB26 [10E..113) -> BB28 (cond), preds={} succs={BB27,BB28} ------------ BB27 [113..11E) -> BB48 (always), preds={} succs={BB48} ------------ BB28 [11E..121), preds={} succs={BB29} ------------ BB29 [121..12C) -> BB48 (always), preds={} succs={BB48} ------------ BB30 [12C..137) -> BB48 (always), preds={} succs={BB48} ------------ BB31 [137..142) -> BB48 (always), preds={} succs={BB48} ------------ BB32 [142..150) -> BB48 (cond), preds={} succs={BB33,BB48} ------------ BB33 [150..15E) -> BB48 (cond), preds={} succs={BB34,BB48} ------------ BB34 [15E..170) -> BB32 (cond), preds={} succs={BB35,BB32} ------------ BB35 [170..175) -> BB48 (always), preds={} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={} succs={BB37,BB48} ------------ BB37 [183..18E) -> BB48 (cond), preds={} succs={BB38,BB48} ------------ BB38 [18E..196) -> BB48 (always), preds={} succs={BB48} ------------ BB39 [196..1A1) -> BB41 (cond), preds={} succs={BB40,BB41} ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={} succs={BB41,BB45} ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={} succs={BB42,BB48} ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={} succs={BB43,BB44} ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={} succs={BB44,BB48} ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={} succs={BB45,BB48} ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={} succs={BB46,BB47} ------------ BB46 [1F4..201) -> BB45 (cond), preds={} succs={BB47,BB45} ------------ BB47 [201..204), preds={} succs={BB48} ------------ BB48 [204..20F) -> BB51 (cond), preds={} succs={BB49,BB51} ------------ BB49 [20F..222) -> BB51 (cond), preds={} succs={BB50,BB51} ------------ BB50 [222..22B) -> BB08 (cond), preds={} succs={BB51,BB08} ------------ BB51 [22B..233) -> BB53 (cond), preds={} succs={BB52,BB53} ------------ BB52 [233..235), preds={} succs={BB53} ------------ BB53 [235..23A) -> BB57 (cond), preds={} succs={BB54,BB57} ------------ BB54 [23A..23F) -> BB56 (cond), preds={} succs={BB55,BB56} ------------ BB55 [23F..24A) -> BB57 (always), preds={} succs={BB57} ------------ BB56 [24A..24D), preds={} succs={BB57} ------------ BB57 [24D..252) -> BB64 (cond), preds={} succs={BB58,BB64} ------------ BB58 [252..262) -> BB60 (cond), preds={} succs={BB59,BB60} ------------ BB59 [262..26E) -> BB61 (always), preds={} succs={BB61} ------------ BB60 [26E..26F), preds={} succs={BB61} ------------ BB61 [26F..27F) -> BB67 (cond), preds={} succs={BB62,BB67} ------------ BB62 [27F..28E) -> BB67 (cond), preds={} succs={BB63,BB67} ------------ BB63 [28E..297) -> BB07 (always), preds={} succs={BB07} ------------ BB64 [297..2A0) -> BB66 (cond), preds={} succs={BB65,BB66} ------------ BB65 [2A0..2A7), preds={} succs={BB66} ------------ BB66 [2A7..2AE), preds={} succs={BB67} ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={} succs={BB68,BB69} ------------ BB68 [2B2..2B5) -> BB70 (always), preds={} succs={BB70} ------------ BB69 [2B5..2B8), preds={} succs={BB70} ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={} succs={BB71,BB72} ------------ BB71 [2BD..2C0) -> BB73 (always), preds={} succs={BB73} ------------ BB72 [2C0..2C3), preds={} succs={BB73} ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={} succs={BB74,BB75} ------------ BB74 [2C8..2D0) -> BB79 (always), preds={} succs={BB79} ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={} succs={BB76,BB77} ------------ BB76 [2D9..2DC) -> BB78 (always), preds={} succs={BB78} ------------ BB77 [2DC..2E2), preds={} succs={BB78} ------------ BB78 [2E2..2EE), preds={} succs={BB79} ------------ BB79 [2EE..30D) -> BB97 (cond), preds={} succs={BB80,BB97} ------------ BB80 [30D..31E) -> BB97 (cond), preds={} succs={BB81,BB97} ------------ BB81 [31E..336) -> BB83 (cond), preds={} succs={BB82,BB83} ------------ BB82 [336..33D), preds={} succs={BB83} ------------ BB83 [33D..348) -> BB85 (cond), preds={} succs={BB84,BB85} ------------ BB84 [348..34B) -> BB86 (always), preds={} succs={BB86} ------------ BB85 [34B..34D), preds={} succs={BB86} ------------ BB86 [34D..355) -> BB88 (cond), preds={} succs={BB87,BB88} ------------ BB87 [355..359) -> BB89 (always), preds={} succs={BB89} ------------ BB88 [359..35A), preds={} succs={BB89} ------------ BB89 [35A..35E) -> BB96 (always), preds={} succs={BB96} ------------ BB90 [35E..362) -> BB97 (cond), preds={} succs={BB91,BB97} ------------ BB91 [362..373) -> BB93 (cond), preds={} succs={BB92,BB93} ------------ BB92 [373..39A), preds={} succs={BB93} ------------ BB93 [39A..3AE) -> BB95 (cond), preds={} succs={BB94,BB95} ------------ BB94 [3AE..3BB), preds={} succs={BB95} ------------ BB95 [3BB..3C2), preds={} succs={BB96} ------------ BB96 [3C2..3C8) -> BB90 (cond), preds={} succs={BB97,BB90} ------------ BB97 [3C8..3D0) -> BB101 (cond), preds={} succs={BB98,BB101} ------------ BB98 [3D0..3D4) -> BB101 (cond), preds={} succs={BB99,BB101} ------------ BB99 [3D4..3DC) -> BB101 (cond), preds={} succs={BB100,BB101} ------------ BB100 [3DC..3E8), preds={} succs={BB101} ------------ BB101 [3E8..401) -> BB191 (always), preds={} succs={BB191} ------------ BB102 [401..406) -> BB117 (cond), preds={} succs={BB103,BB117} ------------ BB103 [406..40C) -> BB116 (cond), preds={} succs={BB104,BB116} ------------ BB104 [40C..412) -> BB116 (cond), preds={} succs={BB105,BB116} ------------ BB105 [412..418) -> BB116 (cond), preds={} succs={BB106,BB116} ------------ BB106 [418..41A) -> BB117 (always), preds={} succs={BB117} ------------ BB107 [41A..420) -> BB109 (cond), preds={} succs={BB108,BB109} ------------ BB108 [420..424) -> BB110 (always), preds={} succs={BB110} ------------ BB109 [424..42C), preds={} succs={BB110} ------------ BB110 [42C..435) -> BB115 (cond), preds={} succs={BB111,BB115} ------------ BB111 [435..43A) -> BB115 (cond), preds={} succs={BB112,BB115} ------------ BB112 [43A..43F) -> BB115 (cond), preds={} succs={BB113,BB115} ------------ BB113 [43F..44F) -> BB115 (cond), preds={} succs={BB114,BB115} ------------ BB114 [44F..461), preds={} succs={BB115} ------------ BB115 [461..46D), preds={} succs={BB116} ------------ BB116 [46D..472) -> BB107 (cond), preds={} succs={BB117,BB107} ------------ BB117 [472..478) -> BB122 (cond), preds={} succs={BB118,BB122} ------------ BB118 [478..49A) -> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch), preds={} succs={BB119,BB126,BB150,BB152,BB190} ------------ BB119 [49A..4B8) -> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch), preds={} succs={BB120,BB126,BB144,BB190,BB191} ------------ BB120 [4B8..4C1) -> BB161 (cond), preds={} succs={BB121,BB161} ------------ BB121 [4C1..4C6) -> BB190 (always), preds={} succs={BB190} ------------ BB122 [4C6..4CF) -> BB158 (cond), preds={} succs={BB123,BB158} ------------ BB123 [4CF..4D8) -> BB161 (cond), preds={} succs={BB124,BB161} ------------ BB124 [4D8..4E4) -> BB149 (cond), preds={} succs={BB125,BB149} ------------ BB125 [4E4..4E9) -> BB190 (always), preds={} succs={BB190} ------------ BB126 [4E9..4EE) -> BB131 (cond), preds={} succs={BB127,BB131} ------------ BB127 [4EE..4F9) -> BB129 (cond), preds={} succs={BB128,BB129} ------------ BB128 [4F9..4FC) -> BB130 (always), preds={} succs={BB130} ------------ BB129 [4FC..4FE), preds={} succs={BB130} ------------ BB130 [4FE..502) -> BB137 (always), preds={} succs={BB137} ------------ BB131 [502..507) -> BB135 (cond), preds={} succs={BB132,BB135} ------------ BB132 [507..50C) -> BB134 (cond), preds={} succs={BB133,BB134} ------------ BB133 [50C..50F) -> BB136 (always), preds={} succs={BB136} ------------ BB134 [50F..513) -> BB136 (always), preds={} succs={BB136} ------------ BB135 [513..51B), preds={} succs={BB136} ------------ BB136 [51B..51D), preds={} succs={BB137} ------------ BB137 [51D..521) -> BB143 (cond), preds={} succs={BB138,BB143} ------------ BB138 [521..52D) -> BB143 (cond), preds={} succs={BB139,BB143} ------------ BB139 [52D..532) -> BB143 (cond), preds={} succs={BB140,BB143} ------------ BB140 [532..537) -> BB143 (cond), preds={} succs={BB141,BB143} ------------ BB141 [537..547) -> BB143 (cond), preds={} succs={BB142,BB143} ------------ BB142 [547..559), preds={} succs={BB143} ------------ BB143 [559..564) -> BB191 (always), preds={} succs={BB191} ------------ BB144 [564..571) -> BB191 (cond), preds={} succs={BB145,BB191} ------------ BB145 [571..575) -> BB148 (cond), preds={} succs={BB146,BB148} ------------ BB146 [575..57C) -> BB191 (cond), preds={} succs={BB147,BB191} ------------ BB147 [57C..584) -> BB191 (cond), preds={} succs={BB148,BB191} ------------ BB148 [584..598) -> BB191 (always), preds={} succs={BB191} ------------ BB149 [598..5A9) -> BB191 (always), preds={} succs={BB191} ------------ BB150 [5A9..5BA) -> BB191 (always), preds={} succs={BB191} ------------ BB151 [5BA..5CE), preds={} succs={BB152} ------------ BB152 [5CE..5D9) -> BB155 (cond), preds={} succs={BB153,BB155} ------------ BB153 [5D9..5E4) -> BB155 (cond), preds={} succs={BB154,BB155} ------------ BB154 [5E4..5F1) -> BB151 (cond), preds={} succs={BB155,BB151} ------------ BB155 [5F1..5FF) -> BB191 (cond), preds={} succs={BB156,BB191} ------------ BB156 [5FF..60D) -> BB191 (cond), preds={} succs={BB157,BB191} ------------ BB157 [60D..618) -> BB191 (always), preds={} succs={BB191} ------------ BB158 [618..626) -> BB191 (cond), preds={} succs={BB159,BB191} ------------ BB159 [626..634) -> BB191 (cond), preds={} succs={BB160,BB191} ------------ BB160 [634..64D) -> BB191 (always), preds={} succs={BB191} ------------ BB161 [64D..65A) -> BB182 (cond), preds={} succs={BB162,BB182} ------------ BB162 [65A..665) -> BB165 (cond), preds={} succs={BB163,BB165} ------------ BB163 [665..672) -> BB165 (cond), preds={} succs={BB164,BB165} ------------ BB164 [672..67A) -> BB174 (always), preds={} succs={BB174} ------------ BB165 [67A..687) -> BB169 (cond), preds={} succs={BB166,BB169} ------------ BB166 [687..694) -> BB169 (cond), preds={} succs={BB167,BB169} ------------ BB167 [694..6A3) -> BB169 (cond), preds={} succs={BB168,BB169} ------------ BB168 [6A3..6A8) -> BB174 (always), preds={} succs={BB174} ------------ BB169 [6A8..6B5) -> BB172 (cond), preds={} succs={BB170,BB172} ------------ BB170 [6B5..6C2) -> BB172 (cond), preds={} succs={BB171,BB172} ------------ BB171 [6C2..6D1) -> BB174 (cond), preds={} succs={BB172,BB174} ------------ BB172 [6D1..6DE) -> BB191 (always), preds={} succs={BB191} ------------ BB173 [6DE..6E4), preds={} succs={BB174} ------------ BB174 [6E4..6F4) -> BB176 (cond), preds={} succs={BB175,BB176} ------------ BB175 [6F4..701) -> BB173 (cond), preds={} succs={BB176,BB173} ------------ BB176 [701..707) -> BB178 (cond), preds={} succs={BB177,BB178} ------------ BB177 [707..70B), preds={} succs={BB178} ------------ BB178 [70B..710) -> BB180 (cond), preds={} succs={BB179,BB180} ------------ BB179 [710..71A) -> BB181 (always), preds={} succs={BB181} ------------ BB180 [71A..71B), preds={} succs={BB181} ------------ BB181 [71B..731) -> BB191 (always), preds={} succs={BB191} ------------ BB182 [731..744) -> BB191 (cond), preds={} succs={BB183,BB191} ------------ BB183 [744..751) -> BB185 (cond), preds={} succs={BB184,BB185} ------------ BB184 [751..75E) -> BB187 (cond), preds={} succs={BB185,BB187} ------------ BB185 [75E..774) -> BB187 (always), preds={} succs={BB187} ------------ BB186 [774..788), preds={} succs={BB187} ------------ BB187 [788..793) -> BB191 (cond), preds={} succs={BB188,BB191} ------------ BB188 [793..7A0) -> BB186 (cond), preds={} succs={BB189,BB186} ------------ BB189 [7A0..7A2) -> BB191 (always), preds={} succs={BB191} ------------ BB190 [7A2..7AA), preds={} succs={BB191} ------------ BB191 [7AA..7B5) -> BB194 (cond), preds={} succs={BB192,BB194} ------------ BB192 [7B5..7C8) -> BB194 (cond), preds={} succs={BB193,BB194} ------------ BB193 [7C8..7D1) -> BB102 (cond), preds={} succs={BB194,BB102} ------------ BB194 [7D1..7DD) -> BB199 (cond), preds={} succs={BB195,BB199} ------------ BB195 [7DD..7E1) -> BB199 (cond), preds={} succs={BB196,BB199} ------------ BB196 [7E1..7E9) -> BB199 (cond), preds={} succs={BB197,BB199} ------------ BB197 [7E9..7F2) -> BB199 (cond), preds={} succs={BB198,BB199} ------------ BB198 [7F2..7FF), preds={} succs={BB199} ------------ BB199 [7FF..800) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) *************** Finishing PHASE Profile incorporation [no changes] *************** Starting PHASE Importation *************** In impImport() for System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo) impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 0 (0x000) ldarg.1 [ 1] 1 (0x001) call 06001831 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' STMT00000 ( 0x000[E-] ... ??? ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 [ 0] 6 (0x006) ldc.i4.0 0 [ 1] 7 (0x007) stloc.s 7 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 [ 0] 9 (0x009) ldarg.1 [ 1] 10 (0x00a) call 06001832 In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Number+NumberBuffer:GetDigitsPointer():ulong:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00002 ( 0x009[E-] ... ??? ) [000006] I-C-G------ * CALL r2r_ind long System.Number+NumberBuffer:GetDigitsPointer():ulong:this (exactContextHnd=0x40000000004246E9) [000005] ----------- this \--* LCL_VAR byref V01 arg1 [ 1] 15 (0x00f) stloc.s 13 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [000007] --C-------- \--* RET_EXPR long (for [000006]) [ 0] 17 (0x011) ldarg.2 [ 1] 18 (0x012) ldloc.s 13 [ 2] 20 (0x014) ldind.u1 [ 2] 21 (0x015) brfalse.s STMT00004 ( 0x011[E-] ... ??? ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 *************** In impGetSpillTmpBase(BB01) lvaGrabTemps(1) returning 41..41 (long lifetime temps) called for IL Stack Entries *************** In fgComputeCheapPreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) BB02 [0001] 1 1 [017..01F)-> BB04 ( cond ) BB03 [0002] 1 1 [01F..022)-> BB06 (always) BB04 [0003] 1 1 [022..025)-> BB06 (always) BB05 [0004] 1 1 [025..026) BB06 [0005] 3 1 [026..02D) BB07 [0006] 2 1 [02D..05B)-> BB48 (always) bwd bwd-target BB08 [0007] 1 1 [05B..061)-> BB13 ( cond ) bwd bwd-target BB09 [0008] 1 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) bwd BB10 [0009] 1 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) bwd BB11 [0010] 1 1 [0A1..0AA)-> BB39 ( cond ) bwd BB12 [0011] 1 1 [0AA..0AF)-> BB48 (always) bwd BB13 [0012] 1 1 [0AF..0B8)-> BB36 ( cond ) bwd BB14 [0013] 1 1 [0B8..0C1)-> BB39 ( cond ) bwd BB15 [0014] 1 1 [0C1..0CA)-> BB31 ( cond ) bwd BB16 [0015] 1 1 [0CA..0CF)-> BB48 (always) bwd BB17 [0016] 1 1 [0CF..0D8)-> BB48 (always) bwd BB18 [0017] 1 1 [0D8..0E0)-> BB20 ( cond ) bwd BB19 [0018] 1 1 [0E0..0E2) bwd BB20 [0019] 2 1 [0E2..0ED)-> BB48 (always) bwd BB21 [0020] 1 1 [0ED..0F4)-> BB48 ( cond ) bwd BB22 [0021] 1 1 [0F4..0FB)-> BB48 (always) bwd BB23 [0022] 1 1 [0FB..102)-> BB48 ( cond ) bwd BB24 [0023] 1 1 [102..109)-> BB48 ( cond ) bwd BB25 [0024] 1 1 [109..10E)-> BB29 ( cond ) bwd BB26 [0025] 1 1 [10E..113)-> BB28 ( cond ) bwd BB27 [0026] 1 1 [113..11E)-> BB48 (always) bwd BB28 [0027] 1 1 [11E..121) bwd BB29 [0028] 2 1 [121..12C)-> BB48 (always) bwd BB30 [0029] 1 1 [12C..137)-> BB48 (always) bwd BB31 [0030] 1 1 [137..142)-> BB48 (always) bwd BB32 [0031] 3 1 [142..150)-> BB48 ( cond ) bwd bwd-target BB33 [0032] 1 1 [150..15E)-> BB48 ( cond ) bwd BB34 [0033] 1 1 [15E..170)-> BB32 ( cond ) bwd bwd-src BB35 [0034] 1 1 [170..175)-> BB48 (always) bwd BB36 [0035] 1 1 [175..183)-> BB48 ( cond ) bwd BB37 [0036] 1 1 [183..18E)-> BB48 ( cond ) bwd BB38 [0037] 1 1 [18E..196)-> BB48 (always) bwd BB39 [0038] 2 1 [196..1A1)-> BB41 ( cond ) bwd BB40 [0039] 1 1 [1A1..1AE)-> BB45 ( cond ) bwd BB41 [0040] 2 1 [1AE..1BB)-> BB48 ( cond ) bwd BB42 [0041] 1 1 [1BB..1C8)-> BB44 ( cond ) bwd BB43 [0042] 1 1 [1C8..1D5)-> BB48 ( cond ) bwd BB44 [0043] 2 1 [1D5..1E4)-> BB48 ( cond ) bwd BB45 [0044] 3 1 [1E4..1F4)-> BB47 ( cond ) bwd bwd-target BB46 [0045] 1 1 [1F4..201)-> BB45 ( cond ) bwd bwd-src BB47 [0046] 2 1 [201..204) bwd BB48 [0047] 27 1 [204..20F)-> BB51 ( cond ) bwd BB49 [0048] 1 1 [20F..222)-> BB51 ( cond ) bwd BB50 [0049] 1 1 [222..22B)-> BB08 ( cond ) bwd bwd-src BB51 [0050] 3 1 [22B..233)-> BB53 ( cond ) bwd BB52 [0051] 1 1 [233..235) bwd BB53 [0052] 2 1 [235..23A)-> BB57 ( cond ) bwd BB54 [0053] 1 1 [23A..23F)-> BB56 ( cond ) bwd BB55 [0054] 1 1 [23F..24A)-> BB57 (always) bwd BB56 [0055] 1 1 [24A..24D) bwd BB57 [0056] 3 1 [24D..252)-> BB64 ( cond ) bwd BB58 [0057] 1 1 [252..262)-> BB60 ( cond ) bwd BB59 [0058] 1 1 [262..26E)-> BB61 (always) bwd BB60 [0059] 1 1 [26E..26F) bwd BB61 [0060] 2 1 [26F..27F)-> BB67 ( cond ) bwd BB62 [0061] 1 1 [27F..28E)-> BB67 ( cond ) bwd BB63 [0062] 1 1 [28E..297)-> BB07 (always) bwd bwd-src BB64 [0063] 1 1 [297..2A0)-> BB66 ( cond ) BB65 [0064] 1 1 [2A0..2A7) BB66 [0065] 2 1 [2A7..2AE) BB67 [0066] 3 1 [2AE..2B2)-> BB69 ( cond ) BB68 [0067] 1 1 [2B2..2B5)-> BB70 (always) BB69 [0068] 1 1 [2B5..2B8) BB70 [0069] 2 1 [2B8..2BD)-> BB72 ( cond ) BB71 [0070] 1 1 [2BD..2C0)-> BB73 (always) BB72 [0071] 1 1 [2C0..2C3) BB73 [0072] 2 1 [2C3..2C8)-> BB75 ( cond ) BB74 [0073] 1 1 [2C8..2D0)-> BB79 (always) BB75 [0074] 1 1 [2D0..2D9)-> BB77 ( cond ) BB76 [0075] 1 1 [2D9..2DC)-> BB78 (always) BB77 [0076] 1 1 [2DC..2E2) BB78 [0077] 2 1 [2E2..2EE) BB79 [0078] 2 1 [2EE..30D)-> BB97 ( cond ) BB80 [0079] 1 1 [30D..31E)-> BB97 ( cond ) BB81 [0080] 1 1 [31E..336)-> BB83 ( cond ) BB82 [0081] 1 1 [336..33D) BB83 [0082] 2 1 [33D..348)-> BB85 ( cond ) BB84 [0083] 1 1 [348..34B)-> BB86 (always) BB85 [0084] 1 1 [34B..34D) BB86 [0085] 2 1 [34D..355)-> BB88 ( cond ) BB87 [0086] 1 1 [355..359)-> BB89 (always) BB88 [0087] 1 1 [359..35A) BB89 [0088] 2 1 [35A..35E)-> BB96 (always) BB90 [0089] 1 1 [35E..362)-> BB97 ( cond ) bwd bwd-target BB91 [0090] 1 1 [362..373)-> BB93 ( cond ) bwd BB92 [0091] 1 1 [373..39A) bwd BB93 [0092] 2 1 [39A..3AE)-> BB95 ( cond ) bwd BB94 [0093] 1 1 [3AE..3BB) bwd BB95 [0094] 2 1 [3BB..3C2) bwd BB96 [0095] 2 1 [3C2..3C8)-> BB90 ( cond ) bwd bwd-src BB97 [0096] 4 1 [3C8..3D0)-> BB101 ( cond ) BB98 [0097] 1 1 [3D0..3D4)-> BB101 ( cond ) BB99 [0098] 1 1 [3D4..3DC)-> BB101 ( cond ) BB100 [0099] 1 1 [3DC..3E8) BB101 [0100] 4 1 [3E8..401)-> BB191 (always) BB102 [0101] 1 1 [401..406)-> BB117 ( cond ) bwd bwd-target BB103 [0102] 1 1 [406..40C)-> BB116 ( cond ) bwd BB104 [0103] 1 1 [40C..412)-> BB116 ( cond ) bwd BB105 [0104] 1 1 [412..418)-> BB116 ( cond ) bwd BB106 [0105] 1 1 [418..41A)-> BB117 (always) bwd BB107 [0106] 1 1 [41A..420)-> BB109 ( cond ) bwd bwd-target BB108 [0107] 1 1 [420..424)-> BB110 (always) bwd BB109 [0108] 1 1 [424..42C) bwd BB110 [0109] 2 1 [42C..435)-> BB115 ( cond ) bwd BB111 [0110] 1 1 [435..43A)-> BB115 ( cond ) bwd BB112 [0111] 1 1 [43A..43F)-> BB115 ( cond ) bwd BB113 [0112] 1 1 [43F..44F)-> BB115 ( cond ) bwd BB114 [0113] 1 1 [44F..461) bwd BB115 [0114] 5 1 [461..46D) bwd BB116 [0115] 4 1 [46D..472)-> BB107 ( cond ) bwd bwd-src BB117 [0116] 3 1 [472..478)-> BB122 ( cond ) bwd BB118 [0117] 1 1 [478..49A)-> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch) bwd BB119 [0118] 1 1 [49A..4B8)-> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch) bwd BB120 [0119] 1 1 [4B8..4C1)-> BB161 ( cond ) bwd BB121 [0120] 1 1 [4C1..4C6)-> BB190 (always) bwd BB122 [0121] 1 1 [4C6..4CF)-> BB158 ( cond ) bwd BB123 [0122] 1 1 [4CF..4D8)-> BB161 ( cond ) bwd BB124 [0123] 1 1 [4D8..4E4)-> BB149 ( cond ) bwd BB125 [0124] 1 1 [4E4..4E9)-> BB190 (always) bwd BB126 [0125] 2 1 [4E9..4EE)-> BB131 ( cond ) bwd BB127 [0126] 1 1 [4EE..4F9)-> BB129 ( cond ) bwd BB128 [0127] 1 1 [4F9..4FC)-> BB130 (always) bwd BB129 [0128] 1 1 [4FC..4FE) bwd BB130 [0129] 2 1 [4FE..502)-> BB137 (always) bwd BB131 [0130] 1 1 [502..507)-> BB135 ( cond ) bwd BB132 [0131] 1 1 [507..50C)-> BB134 ( cond ) bwd BB133 [0132] 1 1 [50C..50F)-> BB136 (always) bwd BB134 [0133] 1 1 [50F..513)-> BB136 (always) bwd BB135 [0134] 1 1 [513..51B) bwd BB136 [0135] 3 1 [51B..51D) bwd BB137 [0136] 2 1 [51D..521)-> BB143 ( cond ) bwd BB138 [0137] 1 1 [521..52D)-> BB143 ( cond ) bwd BB139 [0138] 1 1 [52D..532)-> BB143 ( cond ) bwd BB140 [0139] 1 1 [532..537)-> BB143 ( cond ) bwd BB141 [0140] 1 1 [537..547)-> BB143 ( cond ) bwd BB142 [0141] 1 1 [547..559) bwd BB143 [0142] 6 1 [559..564)-> BB191 (always) bwd BB144 [0143] 1 1 [564..571)-> BB191 ( cond ) bwd BB145 [0144] 1 1 [571..575)-> BB148 ( cond ) bwd BB146 [0145] 1 1 [575..57C)-> BB191 ( cond ) bwd BB147 [0146] 1 1 [57C..584)-> BB191 ( cond ) bwd BB148 [0147] 2 1 [584..598)-> BB191 (always) bwd BB149 [0148] 1 1 [598..5A9)-> BB191 (always) bwd BB150 [0149] 1 1 [5A9..5BA)-> BB191 (always) bwd BB151 [0150] 1 1 [5BA..5CE) bwd bwd-target BB152 [0151] 3 1 [5CE..5D9)-> BB155 ( cond ) bwd BB153 [0152] 1 1 [5D9..5E4)-> BB155 ( cond ) bwd BB154 [0153] 1 1 [5E4..5F1)-> BB151 ( cond ) bwd bwd-src BB155 [0154] 3 1 [5F1..5FF)-> BB191 ( cond ) bwd BB156 [0155] 1 1 [5FF..60D)-> BB191 ( cond ) bwd BB157 [0156] 1 1 [60D..618)-> BB191 (always) bwd BB158 [0157] 1 1 [618..626)-> BB191 ( cond ) bwd BB159 [0158] 1 1 [626..634)-> BB191 ( cond ) bwd BB160 [0159] 1 1 [634..64D)-> BB191 (always) bwd BB161 [0160] 2 1 [64D..65A)-> BB182 ( cond ) bwd BB162 [0161] 1 1 [65A..665)-> BB165 ( cond ) bwd BB163 [0162] 1 1 [665..672)-> BB165 ( cond ) bwd BB164 [0163] 1 1 [672..67A)-> BB174 (always) bwd BB165 [0164] 2 1 [67A..687)-> BB169 ( cond ) bwd BB166 [0165] 1 1 [687..694)-> BB169 ( cond ) bwd BB167 [0166] 1 1 [694..6A3)-> BB169 ( cond ) bwd BB168 [0167] 1 1 [6A3..6A8)-> BB174 (always) bwd BB169 [0168] 3 1 [6A8..6B5)-> BB172 ( cond ) bwd BB170 [0169] 1 1 [6B5..6C2)-> BB172 ( cond ) bwd BB171 [0170] 1 1 [6C2..6D1)-> BB174 ( cond ) bwd BB172 [0171] 3 1 [6D1..6DE)-> BB191 (always) bwd BB173 [0172] 1 1 [6DE..6E4) bwd bwd-target BB174 [0173] 4 1 [6E4..6F4)-> BB176 ( cond ) bwd BB175 [0174] 1 1 [6F4..701)-> BB173 ( cond ) bwd bwd-src BB176 [0175] 2 1 [701..707)-> BB178 ( cond ) bwd BB177 [0176] 1 1 [707..70B) bwd BB178 [0177] 2 1 [70B..710)-> BB180 ( cond ) bwd BB179 [0178] 1 1 [710..71A)-> BB181 (always) bwd BB180 [0179] 1 1 [71A..71B) bwd BB181 [0180] 2 1 [71B..731)-> BB191 (always) bwd BB182 [0181] 1 1 [731..744)-> BB191 ( cond ) bwd BB183 [0182] 1 1 [744..751)-> BB185 ( cond ) bwd BB184 [0183] 1 1 [751..75E)-> BB187 ( cond ) bwd BB185 [0184] 2 1 [75E..774)-> BB187 (always) bwd BB186 [0185] 1 1 [774..788) bwd bwd-target BB187 [0186] 3 1 [788..793)-> BB191 ( cond ) bwd BB188 [0187] 1 1 [793..7A0)-> BB186 ( cond ) bwd bwd-src BB189 [0188] 1 1 [7A0..7A2)-> BB191 (always) bwd BB190 [0189] 6 1 [7A2..7AA) bwd BB191 [0190] 21 1 [7AA..7B5)-> BB194 ( cond ) bwd BB192 [0191] 1 1 [7B5..7C8)-> BB194 ( cond ) bwd BB193 [0192] 1 1 [7C8..7D1)-> BB102 ( cond ) bwd bwd-src BB194 [0193] 3 1 [7D1..7DD)-> BB199 ( cond ) BB195 [0194] 1 1 [7DD..7E1)-> BB199 ( cond ) BB196 [0195] 1 1 [7E1..7E9)-> BB199 ( cond ) BB197 [0196] 1 1 [7E9..7F2)-> BB199 ( cond ) BB198 [0197] 1 1 [7F2..7FF) BB199 [0198] 5 1 [7FF..800) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputeCheapPreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd cheap preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) BB05 [0004] 1 BB01 1 [025..026) BB06 [0005] 3 BB05,BB04,BB03 1 [026..02D) BB07 [0006] 2 BB63,BB06 1 [02D..05B)-> BB48 (always) bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB31 ( cond ) bwd BB16 [0015] 1 BB15 1 [0CA..0CF)-> BB48 (always) bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) bwd BB19 [0018] 1 BB18 1 [0E0..0E2) bwd BB20 [0019] 2 BB19,BB18 1 [0E2..0ED)-> BB48 (always) bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) bwd BB28 [0027] 1 BB26 1 [11E..121) bwd BB29 [0028] 2 BB28,BB25 1 [121..12C)-> BB48 (always) bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) bwd BB32 [0031] 3 BB34,BB09,BB09 1 [142..150)-> BB48 ( cond ) bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) bwd BB39 [0038] 2 BB14,BB11 1 [196..1A1)-> BB41 ( cond ) bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) bwd BB41 [0040] 2 BB40,BB39 1 [1AE..1BB)-> BB48 ( cond ) bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) bwd BB44 [0043] 2 BB43,BB42 1 [1D5..1E4)-> BB48 ( cond ) bwd BB45 [0044] 3 BB46,BB44,BB40 1 [1E4..1F4)-> BB47 ( cond ) bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) bwd bwd-src BB47 [0046] 2 BB46,BB45 1 [201..204) bwd BB48 [0047] 27 BB47,BB44,BB43,BB41,BB38,BB37,BB36,BB35,BB33,BB32,BB31,BB30,BB29,BB27,BB24,BB23,BB22,BB21,BB20,BB17,BB16,BB12,BB10,BB10,BB09,BB09,BB07 1 [204..20F)-> BB51 ( cond ) bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) bwd bwd-src BB51 [0050] 3 BB50,BB49,BB48 1 [22B..233)-> BB53 ( cond ) bwd BB52 [0051] 1 BB51 1 [233..235) bwd BB53 [0052] 2 BB52,BB51 1 [235..23A)-> BB57 ( cond ) bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) bwd BB56 [0055] 1 BB54 1 [24A..24D) bwd BB57 [0056] 3 BB56,BB55,BB53 1 [24D..252)-> BB64 ( cond ) bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) bwd BB60 [0059] 1 BB58 1 [26E..26F) bwd BB61 [0060] 2 BB60,BB59 1 [26F..27F)-> BB67 ( cond ) bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) BB65 [0064] 1 BB64 1 [2A0..2A7) BB66 [0065] 2 BB65,BB64 1 [2A7..2AE) BB67 [0066] 3 BB66,BB62,BB61 1 [2AE..2B2)-> BB69 ( cond ) BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) BB69 [0068] 1 BB67 1 [2B5..2B8) BB70 [0069] 2 BB69,BB68 1 [2B8..2BD)-> BB72 ( cond ) BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) BB72 [0071] 1 BB70 1 [2C0..2C3) BB73 [0072] 2 BB72,BB71 1 [2C3..2C8)-> BB75 ( cond ) BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) BB77 [0076] 1 BB75 1 [2DC..2E2) BB78 [0077] 2 BB77,BB76 1 [2E2..2EE) BB79 [0078] 2 BB78,BB74 1 [2EE..30D)-> BB97 ( cond ) BB80 [0079] 1 BB79 1 [30D..31E)-> BB97 ( cond ) BB81 [0080] 1 BB80 1 [31E..336)-> BB83 ( cond ) BB82 [0081] 1 BB81 1 [336..33D) BB83 [0082] 2 BB82,BB81 1 [33D..348)-> BB85 ( cond ) BB84 [0083] 1 BB83 1 [348..34B)-> BB86 (always) BB85 [0084] 1 BB83 1 [34B..34D) BB86 [0085] 2 BB85,BB84 1 [34D..355)-> BB88 ( cond ) BB87 [0086] 1 BB86 1 [355..359)-> BB89 (always) BB88 [0087] 1 BB86 1 [359..35A) BB89 [0088] 2 BB88,BB87 1 [35A..35E)-> BB96 (always) BB90 [0089] 1 BB96 1 [35E..362)-> BB97 ( cond ) bwd bwd-target BB91 [0090] 1 BB90 1 [362..373)-> BB93 ( cond ) bwd BB92 [0091] 1 BB91 1 [373..39A) bwd BB93 [0092] 2 BB92,BB91 1 [39A..3AE)-> BB95 ( cond ) bwd BB94 [0093] 1 BB93 1 [3AE..3BB) bwd BB95 [0094] 2 BB94,BB93 1 [3BB..3C2) bwd BB96 [0095] 2 BB95,BB89 1 [3C2..3C8)-> BB90 ( cond ) bwd bwd-src BB97 [0096] 4 BB96,BB90,BB80,BB79 1 [3C8..3D0)-> BB101 ( cond ) BB98 [0097] 1 BB97 1 [3D0..3D4)-> BB101 ( cond ) BB99 [0098] 1 BB98 1 [3D4..3DC)-> BB101 ( cond ) BB100 [0099] 1 BB99 1 [3DC..3E8) BB101 [0100] 4 BB100,BB99,BB98,BB97 1 [3E8..401)-> BB191 (always) BB102 [0101] 1 BB193 1 [401..406)-> BB117 ( cond ) bwd bwd-target BB103 [0102] 1 BB102 1 [406..40C)-> BB116 ( cond ) bwd BB104 [0103] 1 BB103 1 [40C..412)-> BB116 ( cond ) bwd BB105 [0104] 1 BB104 1 [412..418)-> BB116 ( cond ) bwd BB106 [0105] 1 BB105 1 [418..41A)-> BB117 (always) bwd BB107 [0106] 1 BB116 1 [41A..420)-> BB109 ( cond ) bwd bwd-target BB108 [0107] 1 BB107 1 [420..424)-> BB110 (always) bwd BB109 [0108] 1 BB107 1 [424..42C) bwd BB110 [0109] 2 BB109,BB108 1 [42C..435)-> BB115 ( cond ) bwd BB111 [0110] 1 BB110 1 [435..43A)-> BB115 ( cond ) bwd BB112 [0111] 1 BB111 1 [43A..43F)-> BB115 ( cond ) bwd BB113 [0112] 1 BB112 1 [43F..44F)-> BB115 ( cond ) bwd BB114 [0113] 1 BB113 1 [44F..461) bwd BB115 [0114] 5 BB114,BB113,BB112,BB111,BB110 1 [461..46D) bwd BB116 [0115] 4 BB115,BB105,BB104,BB103 1 [46D..472)-> BB107 ( cond ) bwd bwd-src BB117 [0116] 3 BB116,BB106,BB102 1 [472..478)-> BB122 ( cond ) bwd BB118 [0117] 1 BB117 1 [478..49A)-> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch) bwd BB119 [0118] 1 BB118 1 [49A..4B8)-> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch) bwd BB120 [0119] 1 BB119 1 [4B8..4C1)-> BB161 ( cond ) bwd BB121 [0120] 1 BB120 1 [4C1..4C6)-> BB190 (always) bwd BB122 [0121] 1 BB117 1 [4C6..4CF)-> BB158 ( cond ) bwd BB123 [0122] 1 BB122 1 [4CF..4D8)-> BB161 ( cond ) bwd BB124 [0123] 1 BB123 1 [4D8..4E4)-> BB149 ( cond ) bwd BB125 [0124] 1 BB124 1 [4E4..4E9)-> BB190 (always) bwd BB126 [0125] 2 BB119,BB118 1 [4E9..4EE)-> BB131 ( cond ) bwd BB127 [0126] 1 BB126 1 [4EE..4F9)-> BB129 ( cond ) bwd BB128 [0127] 1 BB127 1 [4F9..4FC)-> BB130 (always) bwd BB129 [0128] 1 BB127 1 [4FC..4FE) bwd BB130 [0129] 2 BB129,BB128 1 [4FE..502)-> BB137 (always) bwd BB131 [0130] 1 BB126 1 [502..507)-> BB135 ( cond ) bwd BB132 [0131] 1 BB131 1 [507..50C)-> BB134 ( cond ) bwd BB133 [0132] 1 BB132 1 [50C..50F)-> BB136 (always) bwd BB134 [0133] 1 BB132 1 [50F..513)-> BB136 (always) bwd BB135 [0134] 1 BB131 1 [513..51B) bwd BB136 [0135] 3 BB135,BB134,BB133 1 [51B..51D) bwd BB137 [0136] 2 BB136,BB130 1 [51D..521)-> BB143 ( cond ) bwd BB138 [0137] 1 BB137 1 [521..52D)-> BB143 ( cond ) bwd BB139 [0138] 1 BB138 1 [52D..532)-> BB143 ( cond ) bwd BB140 [0139] 1 BB139 1 [532..537)-> BB143 ( cond ) bwd BB141 [0140] 1 BB140 1 [537..547)-> BB143 ( cond ) bwd BB142 [0141] 1 BB141 1 [547..559) bwd BB143 [0142] 6 BB142,BB141,BB140,BB139,BB138,BB137 1 [559..564)-> BB191 (always) bwd BB144 [0143] 1 BB119 1 [564..571)-> BB191 ( cond ) bwd BB145 [0144] 1 BB144 1 [571..575)-> BB148 ( cond ) bwd BB146 [0145] 1 BB145 1 [575..57C)-> BB191 ( cond ) bwd BB147 [0146] 1 BB146 1 [57C..584)-> BB191 ( cond ) bwd BB148 [0147] 2 BB147,BB145 1 [584..598)-> BB191 (always) bwd BB149 [0148] 1 BB124 1 [598..5A9)-> BB191 (always) bwd BB150 [0149] 1 BB118 1 [5A9..5BA)-> BB191 (always) bwd BB151 [0150] 1 BB154 1 [5BA..5CE) bwd bwd-target BB152 [0151] 3 BB151,BB118,BB118 1 [5CE..5D9)-> BB155 ( cond ) bwd BB153 [0152] 1 BB152 1 [5D9..5E4)-> BB155 ( cond ) bwd BB154 [0153] 1 BB153 1 [5E4..5F1)-> BB151 ( cond ) bwd bwd-src BB155 [0154] 3 BB154,BB153,BB152 1 [5F1..5FF)-> BB191 ( cond ) bwd BB156 [0155] 1 BB155 1 [5FF..60D)-> BB191 ( cond ) bwd BB157 [0156] 1 BB156 1 [60D..618)-> BB191 (always) bwd BB158 [0157] 1 BB122 1 [618..626)-> BB191 ( cond ) bwd BB159 [0158] 1 BB158 1 [626..634)-> BB191 ( cond ) bwd BB160 [0159] 1 BB159 1 [634..64D)-> BB191 (always) bwd BB161 [0160] 2 BB123,BB120 1 [64D..65A)-> BB182 ( cond ) bwd BB162 [0161] 1 BB161 1 [65A..665)-> BB165 ( cond ) bwd BB163 [0162] 1 BB162 1 [665..672)-> BB165 ( cond ) bwd BB164 [0163] 1 BB163 1 [672..67A)-> BB174 (always) bwd BB165 [0164] 2 BB163,BB162 1 [67A..687)-> BB169 ( cond ) bwd BB166 [0165] 1 BB165 1 [687..694)-> BB169 ( cond ) bwd BB167 [0166] 1 BB166 1 [694..6A3)-> BB169 ( cond ) bwd BB168 [0167] 1 BB167 1 [6A3..6A8)-> BB174 (always) bwd BB169 [0168] 3 BB167,BB166,BB165 1 [6A8..6B5)-> BB172 ( cond ) bwd BB170 [0169] 1 BB169 1 [6B5..6C2)-> BB172 ( cond ) bwd BB171 [0170] 1 BB170 1 [6C2..6D1)-> BB174 ( cond ) bwd BB172 [0171] 3 BB171,BB170,BB169 1 [6D1..6DE)-> BB191 (always) bwd BB173 [0172] 1 BB175 1 [6DE..6E4) bwd bwd-target BB174 [0173] 4 BB173,BB171,BB168,BB164 1 [6E4..6F4)-> BB176 ( cond ) bwd BB175 [0174] 1 BB174 1 [6F4..701)-> BB173 ( cond ) bwd bwd-src BB176 [0175] 2 BB175,BB174 1 [701..707)-> BB178 ( cond ) bwd BB177 [0176] 1 BB176 1 [707..70B) bwd BB178 [0177] 2 BB177,BB176 1 [70B..710)-> BB180 ( cond ) bwd BB179 [0178] 1 BB178 1 [710..71A)-> BB181 (always) bwd BB180 [0179] 1 BB178 1 [71A..71B) bwd BB181 [0180] 2 BB180,BB179 1 [71B..731)-> BB191 (always) bwd BB182 [0181] 1 BB161 1 [731..744)-> BB191 ( cond ) bwd BB183 [0182] 1 BB182 1 [744..751)-> BB185 ( cond ) bwd BB184 [0183] 1 BB183 1 [751..75E)-> BB187 ( cond ) bwd BB185 [0184] 2 BB184,BB183 1 [75E..774)-> BB187 (always) bwd BB186 [0185] 1 BB188 1 [774..788) bwd bwd-target BB187 [0186] 3 BB186,BB185,BB184 1 [788..793)-> BB191 ( cond ) bwd BB188 [0187] 1 BB187 1 [793..7A0)-> BB186 ( cond ) bwd bwd-src BB189 [0188] 1 BB188 1 [7A0..7A2)-> BB191 (always) bwd BB190 [0189] 6 BB125,BB121,BB119,BB119,BB118,BB118 1 [7A2..7AA) bwd BB191 [0190] 21 BB190,BB189,BB187,BB182,BB181,BB172,BB160,BB159,BB158,BB157,BB156,BB155,BB150,BB149,BB148,BB147,BB146,BB144,BB143,BB119,BB101 1 [7AA..7B5)-> BB194 ( cond ) bwd BB192 [0191] 1 BB191 1 [7B5..7C8)-> BB194 ( cond ) bwd BB193 [0192] 1 BB192 1 [7C8..7D1)-> BB102 ( cond ) bwd bwd-src BB194 [0193] 3 BB193,BB192,BB191 1 [7D1..7DD)-> BB199 ( cond ) BB195 [0194] 1 BB194 1 [7DD..7E1)-> BB199 ( cond ) BB196 [0195] 1 BB195 1 [7E1..7E9)-> BB199 ( cond ) BB197 [0196] 1 BB196 1 [7E9..7F2)-> BB199 ( cond ) BB198 [0197] 1 BB197 1 [7F2..7FF) BB199 [0198] 5 BB198,BB197,BB196,BB195,BB194 1 [7FF..800) (return) ----------------------------------------------------------------------------------------------------------------------------------------- Spilling stack entries into temps STMT00005 ( ??? ... ??? ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct V41 tmp1 [000010] ----------- \--* LCL_VAR struct V02 arg2 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 impImportBlockPending for BB02 impImportBlockPending for BB05 Importing BB05 (PC=037) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 37 (0x025) ldc.i4.2 2 *************** In impGetSpillTmpBase(BB05) lvaGrabTemps(2) returning 42..43 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00006 ( ??? ... ??? ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct V42 tmp2 [000020] ----------- \--* LCL_VAR struct V41 tmp1 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 impImportBlockPending for BB06 Importing BB06 (PC=038) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 2] 38 (0x026) call 06001798 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [000028] ----------- * LCL_VAR struct V42 tmp2 resulting tree: [000032] n---------- * OBJ struct [000031] ----------- \--* ADDR byref [000028] -------N--- \--* LCL_VAR struct V42 tmp2 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 43 (0x02b) stloc.s 11 STMT00008 ( ??? ... ??? ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] n---------- arg0 +--* OBJ struct [000031] ----------- | \--* ADDR byref [000028] -------N--- | \--* LCL_VAR struct V42 tmp2 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 impImportBlockPending for BB07 Importing BB07 (PC=045) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 45 (0x02d) ldc.i4.0 0 [ 1] 46 (0x02e) stloc.0 STMT00009 ( 0x02D[E-] ... ??? ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 [ 0] 47 (0x02f) ldc.i4.m1 -1 [ 1] 48 (0x030) stloc.1 STMT00010 ( 0x02F[E-] ... ??? ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 [ 0] 49 (0x031) ldc.i4 2147483647 [ 1] 54 (0x036) stloc.2 STMT00011 ( 0x031[E-] ... ??? ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF [ 0] 55 (0x037) ldc.i4.0 0 [ 1] 56 (0x038) stloc.3 STMT00012 ( 0x037[E-] ... ??? ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 [ 0] 57 (0x039) ldc.i4.0 0 [ 1] 58 (0x03a) stloc.s 5 STMT00013 ( 0x039[E-] ... ??? ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 [ 0] 60 (0x03c) ldc.i4.m1 -1 [ 1] 61 (0x03d) stloc.s 6 STMT00014 ( 0x03C[E-] ... ??? ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 [ 0] 63 (0x03f) ldc.i4.0 0 [ 1] 64 (0x040) stloc.s 8 STMT00015 ( 0x03F[E-] ... ??? ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 [ 0] 66 (0x042) ldc.i4.0 0 [ 1] 67 (0x043) stloc.s 9 STMT00016 ( 0x042[E-] ... ??? ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 [ 0] 69 (0x045) ldloc.s 11 [ 1] 71 (0x047) stloc.s 12 STMT00017 ( 0x045[E-] ... ??? ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 [ 0] 73 (0x049) ldarg.2 [ 1] 74 (0x04a) call 2B0000FC In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Calling impNormStructVal on: [000062] ----------- * LCL_VAR struct V02 arg2 resulting tree: [000065] n---------- * OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00018 ( 0x049[E-] ... ??? ) [000063] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref (exactContextHnd=0x4000000000428710) [000065] n---------- arg0 \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 [ 1] 79 (0x04f) stloc.s 19 STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [000066] --C-------- \--* RET_EXPR byref (for [000063]) [ 0] 81 (0x051) ldloc.s 19 [ 1] 83 (0x053) conv.u [ 1] 84 (0x054) stloc.s 18 STMT00020 ( 0x051[E-] ... ??? ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 [ 0] 86 (0x056) br impImportBlockPending for BB48 Importing BB48 (PC=516) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 516 (0x204) ldloc.s 12 [ 1] 518 (0x206) ldarga.s 2 [ 2] 520 (0x208) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00021 ( 0x204[E-] ... ??? ) [000076] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000075] ----------- this \--* ADDR byref [000074] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 525 (0x20d) bge.s STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [000077] --C-------- \--* RET_EXPR int (for [000076]) impImportBlockPending for BB49 impImportBlockPending for BB51 Importing BB51 (PC=555) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 555 (0x22b) ldc.i4.0 0 [ 1] 556 (0x22c) conv.u Folding long operator with constant nodes into a constant: [000081] ---------U- * CAST long <- ulong <- uint [000080] ----------- \--* CNS_INT int 0 Bashed to long constant: [000081] ----------- * CNS_INT long 0 [ 1] 557 (0x22d) stloc.s 19 STMT00023 ( 0x22B[E-] ... ??? ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 [ 0] 559 (0x22f) ldloc.1 [ 1] 560 (0x230) ldc.i4.0 0 [ 2] 561 (0x231) bge.s STMT00024 ( 0x22F[E-] ... ??? ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 impImportBlockPending for BB52 impImportBlockPending for BB53 Importing BB53 (PC=565) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 565 (0x235) ldloc.s 6 [ 1] 567 (0x237) ldc.i4.0 0 [ 2] 568 (0x238) blt.s STMT00025 ( 0x235[E-] ... ??? ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 impImportBlockPending for BB54 impImportBlockPending for BB57 Importing BB57 (PC=589) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 589 (0x24d) ldloc.s 13 [ 1] 591 (0x24f) ldind.u1 [ 1] 592 (0x250) brfalse.s STMT00026 ( 0x24D[E-] ... ??? ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 impImportBlockPending for BB58 impImportBlockPending for BB64 Importing BB64 (PC=663) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 663 (0x297) ldarg.1 [ 1] 664 (0x298) ldfld 040004D5 [ 1] 669 (0x29d) ldc.i4.3 3 [ 2] 670 (0x29e) beq.s STMT00027 ( 0x297[E-] ... ??? ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 impImportBlockPending for BB65 impImportBlockPending for BB66 Importing BB66 (PC=679) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 679 (0x2a7) ldarg.1 [ 1] 680 (0x2a8) ldc.i4.0 0 [ 2] 681 (0x2a9) stfld 040004D2 STMT00028 ( 0x2A7[E-] ... ??? ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 impImportBlockPending for BB67 Importing BB67 (PC=686) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 686 (0x2ae) ldloc.2 [ 1] 687 (0x2af) ldloc.1 [ 2] 688 (0x2b0) blt.s STMT00029 ( 0x2AE[E-] ... ??? ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 impImportBlockPending for BB68 impImportBlockPending for BB69 Importing BB69 (PC=693) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 693 (0x2b5) ldloc.1 [ 1] 694 (0x2b6) ldloc.2 [ 2] 695 (0x2b7) sub *************** In impGetSpillTmpBase(BB69) lvaGrabTemps(1) returning 44..44 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00030 ( 0x2B5[E-] ... ??? ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 impImportBlockPending for BB70 Importing BB70 (PC=696) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 696 (0x2b8) stloc.2 STMT00031 ( ??? ... ??? ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 [ 0] 697 (0x2b9) ldloc.3 [ 1] 698 (0x2ba) ldloc.1 [ 2] 699 (0x2bb) bgt.s STMT00032 ( 0x2B9[E-] ... ??? ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 impImportBlockPending for BB71 impImportBlockPending for BB72 Importing BB72 (PC=704) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 704 (0x2c0) ldloc.1 [ 1] 705 (0x2c1) ldloc.3 [ 2] 706 (0x2c2) sub *************** In impGetSpillTmpBase(BB72) lvaGrabTemps(1) returning 45..45 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00033 ( 0x2C0[E-] ... ??? ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 impImportBlockPending for BB73 Importing BB73 (PC=707) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 707 (0x2c3) stloc.3 STMT00034 ( ??? ... ??? ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 [ 0] 708 (0x2c4) ldloc.s 5 [ 1] 710 (0x2c6) brfalse.s STMT00035 ( 0x2C4[E-] ... ??? ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 impImportBlockPending for BB74 impImportBlockPending for BB75 Importing BB75 (PC=720) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 720 (0x2d0) ldarg.1 [ 1] 721 (0x2d1) ldfld 040004D2 [ 1] 726 (0x2d6) ldloc.1 [ 2] 727 (0x2d7) bgt.s STMT00036 ( 0x2D0[E-] ... ??? ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 impImportBlockPending for BB76 impImportBlockPending for BB77 Importing BB77 (PC=732) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 732 (0x2dc) ldarg.1 [ 1] 733 (0x2dd) ldfld 040004D2 *************** In impGetSpillTmpBase(BB77) lvaGrabTemps(1) returning 46..46 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00037 ( 0x2DC[E-] ... ??? ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 impImportBlockPending for BB78 Importing BB78 (PC=738) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 738 (0x2e2) stloc.s 4 STMT00038 ( ??? ... ??? ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 [ 0] 740 (0x2e4) ldarg.1 [ 1] 741 (0x2e5) ldfld 040004D2 [ 1] 746 (0x2ea) ldloc.1 [ 2] 747 (0x2eb) sub [ 1] 748 (0x2ec) stloc.s 10 STMT00039 ( 0x2E4[E-] ... ??? ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 impImportBlockPending for BB79 Importing BB79 (PC=750) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 750 (0x2ee) ldloc.s 11 [ 1] 752 (0x2f0) stloc.s 12 STMT00040 ( 0x2EE[E-] ... ??? ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 [ 0] 754 (0x2f2) ldc.i4.s 16 [ 1] 756 (0x2f4) conv.u Folding long operator with constant nodes into a constant: [000159] ---------U- * CAST long <- ulong <- uint [000158] ----------- \--* CNS_INT int 16 Bashed to long constant: [000159] ----------- * CNS_INT long 16 [ 1] 757 (0x2f5) localloc lvaGrabTemp returning 47 (V47 tmp7) (a long lifetime temp) called for stackallocLocal. Converting stackalloc of 16 bytes to new local V47 [ 1] 759 (0x2f7) ldc.i4.4 4 [ 2] 760 (0x2f8) newobj lvaGrabTemp returning 48 (V48 tmp8) called for NewObj constructor temp. STMT00041 ( 0x2F2[E-] ... ??? ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct V48 tmp8 [000164] ----------- \--* CNS_INT int 0 0A000039 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:.ctor(ulong,int):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00042 ( ??? ... ??? ) [000168] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(ulong,int):this (exactContextHnd=0x40000000004219E1) [000167] ----------- this +--* ADDR byref [000166] -------N--- | \--* LCL_VAR struct V48 tmp8 [000161] ----------- arg1 +--* ADDR long [000160] -------N--- | \--* LCL_VAR blk V47 tmp7 [000162] ----------- arg2 \--* CNS_INT int 4 [ 1] 765 (0x2fd) stloc.s 21 STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct V25 loc21 [000169] ----------- \--* LCL_VAR struct V48 tmp8 [ 0] 767 (0x2ff) ldloc.s 21 [ 1] 769 (0x301) stloc.s 15 STMT00044 ( 0x2FF[E-] ... ??? ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct V19 loc15 [000172] ----------- \--* LCL_VAR struct V25 loc21 [ 0] 771 (0x303) ldc.i4.m1 -1 [ 1] 772 (0x304) stloc.s 16 STMT00045 ( 0x303[E-] ... ??? ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 [ 0] 774 (0x306) ldloc.s 8 [ 1] 776 (0x308) brfalse STMT00046 ( 0x306[E-] ... ??? ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 impImportBlockPending for BB80 impImportBlockPending for BB97 Importing BB97 (PC=968) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 968 (0x3c8) ldarg.1 [ 1] 969 (0x3c9) ldfld 040004D3 [ 1] 974 (0x3ce) brfalse.s STMT00047 ( 0x3C8[E-] ... ??? ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 impImportBlockPending for BB98 impImportBlockPending for BB101 Importing BB101 (PC=1000) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1000 (0x3e8) ldc.i4.0 0 [ 1] 1001 (0x3e9) stloc.s 17 STMT00048 ( 0x3E8[E-] ... ??? ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 [ 0] 1003 (0x3eb) ldarg.2 [ 1] 1004 (0x3ec) call 2B0000FC In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Calling impNormStructVal on: [000190] ----------- * LCL_VAR struct V02 arg2 resulting tree: [000193] n---------- * OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00049 ( 0x3EB[E-] ... ??? ) [000191] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref (exactContextHnd=0x4000000000428710) [000193] n---------- arg0 \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 [ 1] 1009 (0x3f1) stloc.s 31 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [000194] --C-------- \--* RET_EXPR byref (for [000191]) [ 0] 1011 (0x3f3) ldloc.s 31 [ 1] 1013 (0x3f5) conv.u [ 1] 1014 (0x3f6) stloc.s 30 STMT00051 ( 0x3F3[E-] ... ??? ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 [ 0] 1016 (0x3f8) ldloc.s 13 [ 1] 1018 (0x3fa) stloc.s 32 STMT00052 ( 0x3F8[E-] ... ??? ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 [ 0] 1020 (0x3fc) br impImportBlockPending for BB191 Importing BB191 (PC=1962) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1962 (0x7aa) ldloc.s 12 [ 1] 1964 (0x7ac) ldarga.s 2 [ 2] 1966 (0x7ae) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00053 ( 0x7AA[E-] ... ??? ) [000207] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000206] ----------- this \--* ADDR byref [000205] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1971 (0x7b3) bge.s STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [000208] --C-------- \--* RET_EXPR int (for [000207]) impImportBlockPending for BB192 impImportBlockPending for BB194 Importing BB194 (PC=2001) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 2001 (0x7d1) ldc.i4.0 0 [ 1] 2002 (0x7d2) conv.u Folding long operator with constant nodes into a constant: [000212] ---------U- * CAST long <- ulong <- uint [000211] ----------- \--* CNS_INT int 0 Bashed to long constant: [000212] ----------- * CNS_INT long 0 [ 1] 2003 (0x7d3) stloc.s 31 STMT00055 ( 0x7D1[E-] ... ??? ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 [ 0] 2005 (0x7d5) ldarg.1 [ 1] 2006 (0x7d6) ldfld 040004D3 [ 1] 2011 (0x7db) brfalse.s STMT00056 ( 0x7D5[E-] ... ??? ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 impImportBlockPending for BB195 impImportBlockPending for BB199 Importing BB199 (PC=2047) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 2047 (0x7ff) ret STMT00057 ( 0x7FF[E-] ... ??? ) [000220] ----------- * RETURN void Importing BB195 (PC=2013) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 2013 (0x7dd) ldloc.s 11 [ 1] 2015 (0x7df) brtrue.s STMT00058 ( 0x7DD[E-] ... ??? ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 impImportBlockPending for BB196 impImportBlockPending for BB199 Importing BB196 (PC=2017) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 2017 (0x7e1) ldarg.1 [ 1] 2018 (0x7e2) ldfld 040004D2 [ 1] 2023 (0x7e7) brtrue.s STMT00059 ( 0x7E1[E-] ... ??? ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 impImportBlockPending for BB197 impImportBlockPending for BB199 Importing BB197 (PC=2025) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 2025 (0x7e9) ldarg.0 [ 1] 2026 (0x7ea) call 06003E54 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00060 ( 0x7E9[E-] ... ??? ) [000231] I-C-G------ * CALL r2r_ind int System.Text.ValueStringBuilder:get_Length():int:this (exactContextHnd=0x40000000004246F9) [000230] ----------- this \--* LCL_VAR byref V00 arg0 [ 1] 2031 (0x7ef) ldc.i4.0 0 [ 2] 2032 (0x7f0) ble.s STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [000232] --C-------- +--* RET_EXPR int (for [000231]) [000233] ----------- \--* CNS_INT int 0 impImportBlockPending for BB198 impImportBlockPending for BB199 Importing BB198 (PC=2034) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 2034 (0x7f2) ldarg.0 [ 1] 2035 (0x7f3) ldc.i4.0 0 [ 2] 2036 (0x7f4) ldarg.3 [ 3] 2037 (0x7f5) callvirt 06002E08 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00062 ( 0x7F2[E-] ... ??? ) [000239] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this (exactContextHnd=0x4000000000424641) [000238] ----------- this \--* LCL_VAR ref V03 arg3 [ 3] 2042 (0x7fa) call 06003E5D (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 GTF_CALL_M_IMPLICIT_TAILCALL set for call [000241] INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [000240] --C-------- arg2 \--* RET_EXPR ref (for [000239]) impImportBlockPending for BB199 Importing BB192 (PC=1973) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1973 (0x7b5) ldloc.s 30 [ 1] 1975 (0x7b7) ldloc.s 12 [ 2] 1977 (0x7b9) dup [ 3] 1978 (0x7ba) ldc.i4.1 1 [ 4] 1979 (0x7bb) add [ 3] 1980 (0x7bc) stloc.s 12 lvaGrabTemp returning 49 (V49 tmp9) called for impSpillLclRefs. STMT00065 ( 0x7B5[E-] ... ??? ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 [ 2] 1982 (0x7be) conv.i [ 2] 1983 (0x7bf) ldc.i4.2 2 [ 3] 1984 (0x7c0) mul [ 2] 1985 (0x7c1) add [ 1] 1986 (0x7c2) ldind.u2 [ 1] 1987 (0x7c3) dup lvaGrabTemp returning 50 (V50 tmp10) called for dup spill. STMT00066 ( ??? ... ??? ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 [ 2] 1988 (0x7c4) stloc.s 14 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 [ 1] 1990 (0x7c6) brfalse.s STMT00068 ( ??? ... ??? ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 impImportBlockPending for BB193 impImportBlockPending for BB194 Importing BB193 (PC=1992) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1992 (0x7c8) ldloc.s 14 [ 1] 1994 (0x7ca) ldc.i4.s 59 [ 2] 1996 (0x7cc) bne.un STMT00069 ( 0x7C8[E-] ... ??? ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 impImportBlockPending for BB194 impImportBlockPending for BB102 Importing BB102 (PC=1025) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1025 (0x401) ldloc.s 10 [ 1] 1027 (0x403) ldc.i4.0 0 [ 2] 1028 (0x404) ble.s STMT00070 ( 0x401[E-] ... ??? ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 impImportBlockPending for BB103 impImportBlockPending for BB117 Importing BB117 (PC=1138) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1138 (0x472) ldloc.s 14 [ 1] 1140 (0x474) ldc.i4.s 69 [ 2] 1142 (0x476) bgt.un.s STMT00071 ( 0x472[E-] ... ??? ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 impImportBlockPending for BB118 impImportBlockPending for BB122 Importing BB122 (PC=1222) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1222 (0x4c6) ldloc.s 14 [ 1] 1224 (0x4c8) ldc.i4.s 92 [ 2] 1226 (0x4ca) beq STMT00072 ( 0x4C6[E-] ... ??? ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 impImportBlockPending for BB123 impImportBlockPending for BB158 Importing BB158 (PC=1560) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1560 (0x618) ldloc.s 12 [ 1] 1562 (0x61a) ldarga.s 2 [ 2] 1564 (0x61c) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00073 ( 0x618[E-] ... ??? ) [000286] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000285] ----------- this \--* ADDR byref [000284] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1569 (0x621) bge STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [000287] --C-------- \--* RET_EXPR int (for [000286]) impImportBlockPending for BB159 impImportBlockPending for BB191 Importing BB159 (PC=1574) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1574 (0x626) ldloc.s 30 [ 1] 1576 (0x628) ldloc.s 12 [ 2] 1578 (0x62a) conv.i [ 2] 1579 (0x62b) ldc.i4.2 2 [ 3] 1580 (0x62c) mul [ 2] 1581 (0x62d) add [ 1] 1582 (0x62e) ldind.u2 [ 1] 1583 (0x62f) brfalse STMT00075 ( 0x626[E-] ... ??? ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 impImportBlockPending for BB160 impImportBlockPending for BB191 Importing BB160 (PC=1588) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1588 (0x634) ldarg.0 [ 1] 1589 (0x635) ldloc.s 30 [ 2] 1591 (0x637) ldloc.s 12 [ 3] 1593 (0x639) dup [ 4] 1594 (0x63a) ldc.i4.1 1 [ 5] 1595 (0x63b) add [ 4] 1596 (0x63c) stloc.s 12 lvaGrabTemp returning 51 (V51 tmp11) called for impSpillLclRefs. STMT00077 ( 0x634[E-] ... ??? ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 [ 3] 1598 (0x63e) conv.i [ 3] 1599 (0x63f) ldc.i4.2 2 [ 4] 1600 (0x640) mul [ 3] 1601 (0x641) add [ 2] 1602 (0x642) ldind.u2 [ 2] 1603 (0x643) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00078 ( ??? ... ??? ) [000318] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000301] ----------- this +--* LCL_VAR byref V00 arg0 [000317] ---XG------ arg1 \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 [ 0] 1608 (0x648) br impImportBlockPending for BB191 Importing BB123 (PC=1231) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1231 (0x4cf) ldloc.s 14 [ 1] 1233 (0x4d1) ldc.i4.s 101 [ 2] 1235 (0x4d3) beq STMT00079 ( 0x4CF[E-] ... ??? ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 impImportBlockPending for BB124 impImportBlockPending for BB161 Importing BB161 (PC=1613) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1613 (0x64d) ldc.i4.0 0 [ 1] 1614 (0x64e) stloc.s 33 STMT00080 ( 0x64D[E-] ... ??? ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 [ 0] 1616 (0x650) ldc.i4.0 0 [ 1] 1617 (0x651) stloc.s 34 STMT00081 ( 0x650[E-] ... ??? ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 [ 0] 1619 (0x653) ldloc.s 5 [ 1] 1621 (0x655) brfalse STMT00082 ( 0x653[E-] ... ??? ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 impImportBlockPending for BB162 impImportBlockPending for BB182 Importing BB182 (PC=1841) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1841 (0x731) ldarg.0 [ 1] 1842 (0x732) ldloc.s 14 [ 2] 1844 (0x734) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00083 ( 0x731[E-] ... ??? ) [000335] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000333] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 [ 0] 1849 (0x739) ldloc.s 12 [ 1] 1851 (0x73b) ldarga.s 2 [ 2] 1853 (0x73d) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00084 ( 0x739[E-] ... ??? ) [000339] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000338] ----------- this \--* ADDR byref [000337] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1858 (0x742) bge.s STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [000340] --C-------- \--* RET_EXPR int (for [000339]) impImportBlockPending for BB183 impImportBlockPending for BB191 Importing BB183 (PC=1860) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1860 (0x744) ldloc.s 30 [ 1] 1862 (0x746) ldloc.s 12 [ 2] 1864 (0x748) conv.i [ 2] 1865 (0x749) ldc.i4.2 2 [ 3] 1866 (0x74a) mul [ 2] 1867 (0x74b) add [ 1] 1868 (0x74c) ldind.u2 [ 1] 1869 (0x74d) ldc.i4.s 43 [ 2] 1871 (0x74f) beq.s STMT00086 ( 0x744[E-] ... ??? ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 impImportBlockPending for BB184 impImportBlockPending for BB185 Importing BB185 (PC=1886) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1886 (0x75e) ldarg.0 [ 1] 1887 (0x75f) ldloc.s 30 [ 2] 1889 (0x761) ldloc.s 12 [ 3] 1891 (0x763) dup [ 4] 1892 (0x764) ldc.i4.1 1 [ 5] 1893 (0x765) add [ 4] 1894 (0x766) stloc.s 12 lvaGrabTemp returning 52 (V52 tmp12) called for impSpillLclRefs. STMT00088 ( 0x75E[E-] ... ??? ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 [ 3] 1896 (0x768) conv.i [ 3] 1897 (0x769) ldc.i4.2 2 [ 4] 1898 (0x76a) mul [ 3] 1899 (0x76b) add [ 2] 1900 (0x76c) ldind.u2 [ 2] 1901 (0x76d) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00089 ( ??? ... ??? ) [000371] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000354] ----------- this +--* LCL_VAR byref V00 arg0 [000370] ---XG------ arg1 \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 [ 0] 1906 (0x772) br.s impImportBlockPending for BB187 Importing BB187 (PC=1928) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1928 (0x788) ldloc.s 12 [ 1] 1930 (0x78a) ldarga.s 2 [ 2] 1932 (0x78c) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00090 ( 0x788[E-] ... ??? ) [000375] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000374] ----------- this \--* ADDR byref [000373] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1937 (0x791) bge.s STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [000376] --C-------- \--* RET_EXPR int (for [000375]) impImportBlockPending for BB188 impImportBlockPending for BB191 Importing BB188 (PC=1939) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1939 (0x793) ldloc.s 30 [ 1] 1941 (0x795) ldloc.s 12 [ 2] 1943 (0x797) conv.i [ 2] 1944 (0x798) ldc.i4.2 2 [ 3] 1945 (0x799) mul [ 2] 1946 (0x79a) add [ 1] 1947 (0x79b) ldind.u2 [ 1] 1948 (0x79c) ldc.i4.s 48 [ 2] 1950 (0x79e) beq.s STMT00092 ( 0x793[E-] ... ??? ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 impImportBlockPending for BB189 impImportBlockPending for BB186 Importing BB186 (PC=1908) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1908 (0x774) ldarg.0 [ 1] 1909 (0x775) ldloc.s 30 [ 2] 1911 (0x777) ldloc.s 12 [ 3] 1913 (0x779) dup [ 4] 1914 (0x77a) ldc.i4.1 1 [ 5] 1915 (0x77b) add [ 4] 1916 (0x77c) stloc.s 12 lvaGrabTemp returning 53 (V53 tmp13) called for impSpillLclRefs. STMT00094 ( 0x774[E-] ... ??? ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 [ 3] 1918 (0x77e) conv.i [ 3] 1919 (0x77f) ldc.i4.2 2 [ 4] 1920 (0x780) mul [ 3] 1921 (0x781) add [ 2] 1922 (0x782) ldind.u2 [ 2] 1923 (0x783) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00095 ( ??? ... ??? ) [000407] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000390] ----------- this +--* LCL_VAR byref V00 arg0 [000406] ---XG------ arg1 \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 impImportBlockPending for BB187 Importing BB189 (PC=1952) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1952 (0x7a0) br.s impImportBlockPending for BB191 Importing BB184 (PC=1873) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1873 (0x751) ldloc.s 30 [ 1] 1875 (0x753) ldloc.s 12 [ 2] 1877 (0x755) conv.i [ 2] 1878 (0x756) ldc.i4.2 2 [ 3] 1879 (0x757) mul [ 2] 1880 (0x758) add [ 1] 1881 (0x759) ldind.u2 [ 1] 1882 (0x75a) ldc.i4.s 45 [ 2] 1884 (0x75c) bne.un.s STMT00096 ( 0x751[E-] ... ??? ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 impImportBlockPending for BB185 impImportBlockPending for BB187 Importing BB162 (PC=1626) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1626 (0x65a) ldloc.s 12 [ 1] 1628 (0x65c) ldarga.s 2 [ 2] 1630 (0x65e) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00097 ( 0x65A[E-] ... ??? ) [000422] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000421] ----------- this \--* ADDR byref [000420] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1635 (0x663) bge.s STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [000423] --C-------- \--* RET_EXPR int (for [000422]) impImportBlockPending for BB163 impImportBlockPending for BB165 Importing BB165 (PC=1658) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1658 (0x67a) ldloc.s 12 [ 1] 1660 (0x67c) ldc.i4.1 1 [ 2] 1661 (0x67d) add [ 1] 1662 (0x67e) ldarga.s 2 [ 2] 1664 (0x680) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00099 ( 0x67A[E-] ... ??? ) [000431] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000430] ----------- this \--* ADDR byref [000429] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1669 (0x685) bge.s STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [000432] --C-------- \--* RET_EXPR int (for [000431]) impImportBlockPending for BB166 impImportBlockPending for BB169 Importing BB169 (PC=1704) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1704 (0x6a8) ldloc.s 12 [ 1] 1706 (0x6aa) ldc.i4.1 1 [ 2] 1707 (0x6ab) add [ 1] 1708 (0x6ac) ldarga.s 2 [ 2] 1710 (0x6ae) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00101 ( 0x6A8[E-] ... ??? ) [000440] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000439] ----------- this \--* ADDR byref [000438] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1715 (0x6b3) bge.s STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [000441] --C-------- \--* RET_EXPR int (for [000440]) impImportBlockPending for BB170 impImportBlockPending for BB172 Importing BB172 (PC=1745) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1745 (0x6d1) ldarg.0 [ 1] 1746 (0x6d2) ldloc.s 14 [ 2] 1748 (0x6d4) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00103 ( 0x6D1[E-] ... ??? ) [000446] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000444] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 [ 0] 1753 (0x6d9) br impImportBlockPending for BB191 Importing BB170 (PC=1717) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1717 (0x6b5) ldloc.s 30 [ 1] 1719 (0x6b7) ldloc.s 12 [ 2] 1721 (0x6b9) conv.i [ 2] 1722 (0x6ba) ldc.i4.2 2 [ 3] 1723 (0x6bb) mul [ 2] 1724 (0x6bc) add [ 1] 1725 (0x6bd) ldind.u2 [ 1] 1726 (0x6be) ldc.i4.s 45 [ 2] 1728 (0x6c0) bne.un.s STMT00104 ( 0x6B5[E-] ... ??? ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 impImportBlockPending for BB171 impImportBlockPending for BB172 Importing BB171 (PC=1730) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1730 (0x6c2) ldloc.s 30 [ 1] 1732 (0x6c4) ldloc.s 12 [ 2] 1734 (0x6c6) ldc.i4.1 1 [ 3] 1735 (0x6c7) add [ 2] 1736 (0x6c8) conv.i [ 2] 1737 (0x6c9) ldc.i4.2 2 [ 3] 1738 (0x6ca) mul [ 2] 1739 (0x6cb) add [ 1] 1740 (0x6cc) ldind.u2 [ 1] 1741 (0x6cd) ldc.i4.s 48 [ 2] 1743 (0x6cf) beq.s STMT00105 ( 0x6C2[E-] ... ??? ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 impImportBlockPending for BB172 impImportBlockPending for BB174 Importing BB174 (PC=1764) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1764 (0x6e4) ldloc.s 12 [ 1] 1766 (0x6e6) ldc.i4.1 1 [ 2] 1767 (0x6e7) add [ 1] 1768 (0x6e8) dup lvaGrabTemp returning 54 (V54 tmp14) called for dup spill. STMT00106 ( 0x6E4[E-] ... ??? ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 [ 2] 1769 (0x6e9) stloc.s 12 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 [ 1] 1771 (0x6eb) ldarga.s 2 [ 2] 1773 (0x6ed) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00108 ( ??? ... ??? ) [000482] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000481] ----------- this \--* ADDR byref [000480] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1778 (0x6f2) bge.s STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [000483] --C-------- \--* RET_EXPR int (for [000482]) impImportBlockPending for BB175 impImportBlockPending for BB176 Importing BB176 (PC=1793) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1793 (0x701) ldloc.s 34 [ 1] 1795 (0x703) ldc.i4.s 10 [ 2] 1797 (0x705) ble.s STMT00110 ( 0x701[E-] ... ??? ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 impImportBlockPending for BB177 impImportBlockPending for BB178 Importing BB178 (PC=1803) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1803 (0x70b) ldloc.s 13 [ 1] 1805 (0x70d) ldind.u1 [ 1] 1806 (0x70e) brfalse.s STMT00111 ( 0x70B[E-] ... ??? ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 impImportBlockPending for BB179 impImportBlockPending for BB180 Importing BB180 (PC=1818) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1818 (0x71a) ldc.i4.0 0 *************** In impGetSpillTmpBase(BB180) lvaGrabTemps(1) returning 55..55 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00112 ( 0x71A[E-] ... ??? ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 impImportBlockPending for BB181 Importing BB181 (PC=1819) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 1819 (0x71b) stloc.s 35 STMT00113 ( ??? ... ??? ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 [ 0] 1821 (0x71d) ldarg.0 [ 1] 1822 (0x71e) ldarg.3 [ 2] 1823 (0x71f) ldloc.s 35 [ 3] 1825 (0x721) ldloc.s 14 [ 4] 1827 (0x723) ldloc.s 34 [ 5] 1829 (0x725) ldloc.s 33 [ 6] 1831 (0x727) call 06001794 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool)' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00114 ( 0x71D[E-] ... ??? ) [000508] I-C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) (exactContextHnd=0x4000000000424651) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 [ 0] 1836 (0x72c) ldc.i4.0 0 [ 1] 1837 (0x72d) stloc.s 5 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 [ 0] 1839 (0x72f) br.s impImportBlockPending for BB191 Importing BB179 (PC=1808) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1808 (0x710) ldarg.1 [ 1] 1809 (0x711) ldfld 040004D2 [ 1] 1814 (0x716) ldloc.1 [ 2] 1815 (0x717) sub [ 1] 1816 (0x718) br.s Spilling stack entries into temps STMT00116 ( 0x710[E-] ... ??? ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 impImportBlockPending for BB181 Importing BB177 (PC=1799) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1799 (0x707) ldc.i4.s 10 [ 1] 1801 (0x709) stloc.s 34 STMT00117 ( 0x707[E-] ... ??? ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 impImportBlockPending for BB178 Importing BB175 (PC=1780) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1780 (0x6f4) ldloc.s 30 [ 1] 1782 (0x6f6) ldloc.s 12 [ 2] 1784 (0x6f8) conv.i [ 2] 1785 (0x6f9) ldc.i4.2 2 [ 3] 1786 (0x6fa) mul [ 2] 1787 (0x6fb) add [ 1] 1788 (0x6fc) ldind.u2 [ 1] 1789 (0x6fd) ldc.i4.s 48 [ 2] 1791 (0x6ff) beq.s STMT00118 ( 0x6F4[E-] ... ??? ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 impImportBlockPending for BB176 impImportBlockPending for BB173 Importing BB173 (PC=1758) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1758 (0x6de) ldloc.s 34 [ 1] 1760 (0x6e0) ldc.i4.1 1 [ 2] 1761 (0x6e1) add [ 1] 1762 (0x6e2) stloc.s 34 STMT00119 ( 0x6DE[E-] ... ??? ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 impImportBlockPending for BB174 Importing BB166 (PC=1671) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1671 (0x687) ldloc.s 30 [ 1] 1673 (0x689) ldloc.s 12 [ 2] 1675 (0x68b) conv.i [ 2] 1676 (0x68c) ldc.i4.2 2 [ 3] 1677 (0x68d) mul [ 2] 1678 (0x68e) add [ 1] 1679 (0x68f) ldind.u2 [ 1] 1680 (0x690) ldc.i4.s 43 [ 2] 1682 (0x692) bne.un.s STMT00120 ( 0x687[E-] ... ??? ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 impImportBlockPending for BB167 impImportBlockPending for BB169 Importing BB167 (PC=1684) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1684 (0x694) ldloc.s 30 [ 1] 1686 (0x696) ldloc.s 12 [ 2] 1688 (0x698) ldc.i4.1 1 [ 3] 1689 (0x699) add [ 2] 1690 (0x69a) conv.i [ 2] 1691 (0x69b) ldc.i4.2 2 [ 3] 1692 (0x69c) mul [ 2] 1693 (0x69d) add [ 1] 1694 (0x69e) ldind.u2 [ 1] 1695 (0x69f) ldc.i4.s 48 [ 2] 1697 (0x6a1) bne.un.s STMT00121 ( 0x694[E-] ... ??? ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 impImportBlockPending for BB168 impImportBlockPending for BB169 Importing BB168 (PC=1699) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1699 (0x6a3) ldc.i4.1 1 [ 1] 1700 (0x6a4) stloc.s 33 STMT00122 ( 0x6A3[E-] ... ??? ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 [ 0] 1702 (0x6a6) br.s impImportBlockPending for BB174 Importing BB163 (PC=1637) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1637 (0x665) ldloc.s 30 [ 1] 1639 (0x667) ldloc.s 12 [ 2] 1641 (0x669) conv.i [ 2] 1642 (0x66a) ldc.i4.2 2 [ 3] 1643 (0x66b) mul [ 2] 1644 (0x66c) add [ 1] 1645 (0x66d) ldind.u2 [ 1] 1646 (0x66e) ldc.i4.s 48 [ 2] 1648 (0x670) bne.un.s STMT00123 ( 0x665[E-] ... ??? ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* NE int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 impImportBlockPending for BB164 impImportBlockPending for BB165 Importing BB164 (PC=1650) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1650 (0x672) ldloc.s 34 [ 1] 1652 (0x674) ldc.i4.1 1 [ 2] 1653 (0x675) add [ 1] 1654 (0x676) stloc.s 34 STMT00124 ( 0x672[E-] ... ??? ) [000580] -A--------- * ASG int [000579] D------N--- +--* LCL_VAR int V38 loc34 [000578] ----------- \--* ADD int [000576] ----------- +--* LCL_VAR int V38 loc34 [000577] ----------- \--* CNS_INT int 1 [ 0] 1656 (0x678) br.s impImportBlockPending for BB174 Importing BB124 (PC=1240) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1240 (0x4d8) ldloc.s 14 [ 1] 1242 (0x4da) ldc.i4 8240 [ 2] 1247 (0x4df) beq STMT00125 ( 0x4D8[E-] ... ??? ) [000584] ----------- * JTRUE void [000583] ----------- \--* EQ int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 impImportBlockPending for BB125 impImportBlockPending for BB149 Importing BB149 (PC=1432) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1432 (0x598) ldarg.0 [ 1] 1433 (0x599) ldarg.3 [ 2] 1434 (0x59a) callvirt 06002E1E In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00126 ( 0x598[E-] ... ??? ) [000587] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this (exactContextHnd=0x4000000000424641) [000586] ----------- this \--* LCL_VAR ref V03 arg3 [ 2] 1439 (0x59f) call 06003E5F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00127 ( 0x598[E-] ... ??? ) [000589] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000585] ----------- this +--* LCL_VAR byref V00 arg0 [000588] --C-------- arg1 \--* RET_EXPR ref (for [000587]) [ 0] 1444 (0x5a4) br impImportBlockPending for BB191 Importing BB125 (PC=1252) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1252 (0x4e4) br impImportBlockPending for BB190 Importing BB190 (PC=1954) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1954 (0x7a2) ldarg.0 [ 1] 1955 (0x7a3) ldloc.s 14 [ 2] 1957 (0x7a5) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00128 ( 0x7A2[E-] ... ??? ) [000592] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000590] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 impImportBlockPending for BB191 Importing BB118 (PC=1144) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1144 (0x478) ldloc.s 14 [ 1] 1146 (0x47a) ldc.i4.s 34 [ 2] 1148 (0x47c) sub [ 1] 1149 (0x47d) switch STMT00129 ( 0x478[E-] ... ??? ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 impImportBlockPending for BB152 impImportBlockPending for BB126 impImportBlockPending for BB190 impImportBlockPending for BB150 impImportBlockPending for BB190 impImportBlockPending for BB152 impImportBlockPending for BB119 Importing BB119 (PC=1178) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1178 (0x49a) ldloc.s 14 [ 1] 1180 (0x49c) ldc.i4.s 44 [ 2] 1182 (0x49e) sub [ 1] 1183 (0x49f) switch STMT00130 ( 0x49A[E-] ... ??? ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 impImportBlockPending for BB191 impImportBlockPending for BB190 impImportBlockPending for BB144 impImportBlockPending for BB190 impImportBlockPending for BB126 impImportBlockPending for BB120 Importing BB120 (PC=1208) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1208 (0x4b8) ldloc.s 14 [ 1] 1210 (0x4ba) ldc.i4.s 69 [ 2] 1212 (0x4bc) beq STMT00131 ( 0x4B8[E-] ... ??? ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 impImportBlockPending for BB121 impImportBlockPending for BB161 Importing BB121 (PC=1217) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1217 (0x4c1) br impImportBlockPending for BB190 Importing BB144 (PC=1380) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1380 (0x564) ldloc.s 4 [ 1] 1382 (0x566) ldc.i4.0 0 [ 2] 1383 (0x567) cgt.un [ 1] 1385 (0x569) ldloc.s 17 [ 2] 1387 (0x56b) or [ 1] 1388 (0x56c) brtrue STMT00132 ( 0x564[E-] ... ??? ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 impImportBlockPending for BB145 impImportBlockPending for BB191 Importing BB145 (PC=1393) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1393 (0x571) ldloc.3 [ 1] 1394 (0x572) ldc.i4.0 0 [ 2] 1395 (0x573) blt.s STMT00133 ( 0x571[E-] ... ??? ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 impImportBlockPending for BB146 impImportBlockPending for BB148 Importing BB148 (PC=1412) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1412 (0x584) ldarg.0 [ 1] 1413 (0x585) ldarg.3 [ 2] 1414 (0x586) callvirt 06002E0C In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00134 ( 0x584[E-] ... ??? ) [000619] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000618] ----------- this \--* LCL_VAR ref V03 arg3 [ 2] 1419 (0x58b) call 06003E5F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00135 ( 0x584[E-] ... ??? ) [000621] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000617] ----------- this +--* LCL_VAR byref V00 arg0 [000620] --C-------- arg1 \--* RET_EXPR ref (for [000619]) [ 0] 1424 (0x590) ldc.i4.1 1 [ 1] 1425 (0x591) stloc.s 17 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 [ 0] 1427 (0x593) br impImportBlockPending for BB191 Importing BB146 (PC=1397) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1397 (0x575) ldloc.1 [ 1] 1398 (0x576) ldloc.0 [ 2] 1399 (0x577) bge STMT00137 ( 0x575[E-] ... ??? ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 impImportBlockPending for BB147 impImportBlockPending for BB191 Importing BB147 (PC=1404) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1404 (0x57c) ldloc.s 32 [ 1] 1406 (0x57e) ldind.u1 [ 1] 1407 (0x57f) brfalse STMT00138 ( 0x57C[E-] ... ??? ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 impImportBlockPending for BB148 impImportBlockPending for BB191 Importing BB150 (PC=1449) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1449 (0x5a9) ldarg.0 [ 1] 1450 (0x5aa) ldarg.3 [ 2] 1451 (0x5ab) callvirt 06002E1C In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00139 ( 0x5A9[E-] ... ??? ) [000636] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this (exactContextHnd=0x4000000000424641) [000635] ----------- this \--* LCL_VAR ref V03 arg3 [ 2] 1456 (0x5b0) call 06003E5F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00140 ( 0x5A9[E-] ... ??? ) [000638] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000634] ----------- this +--* LCL_VAR byref V00 arg0 [000637] --C-------- arg1 \--* RET_EXPR ref (for [000636]) [ 0] 1461 (0x5b5) br impImportBlockPending for BB191 Importing BB126 (PC=1257) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1257 (0x4e9) ldloc.s 10 [ 1] 1259 (0x4eb) ldc.i4.0 0 [ 2] 1260 (0x4ec) bge.s STMT00141 ( 0x4E9[E-] ... ??? ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 impImportBlockPending for BB127 impImportBlockPending for BB131 Importing BB131 (PC=1282) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1282 (0x502) ldloc.s 32 [ 1] 1284 (0x504) ldind.u1 [ 1] 1285 (0x505) brtrue.s STMT00142 ( 0x502[E-] ... ??? ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 impImportBlockPending for BB132 impImportBlockPending for BB135 Importing BB135 (PC=1299) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1299 (0x513) ldloc.s 32 [ 1] 1301 (0x515) dup [ 2] 1302 (0x516) ldc.i4.1 1 [ 3] 1303 (0x517) add [ 2] 1304 (0x518) stloc.s 32 lvaGrabTemp returning 56 (V56 tmp16) called for impSpillLclRefs. STMT00144 ( 0x513[E-] ... ??? ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 [ 1] 1306 (0x51a) ldind.u1 *************** In impGetSpillTmpBase(BB135) lvaGrabTemps(1) returning 57..57 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00145 ( ??? ... ??? ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 impImportBlockPending for BB136 Importing BB136 (PC=1307) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 1307 (0x51b) stloc.s 14 STMT00146 ( ??? ... ??? ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 impImportBlockPending for BB137 Importing BB137 (PC=1309) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1309 (0x51d) ldloc.s 14 [ 1] 1311 (0x51f) brfalse.s STMT00147 ( 0x51D[E-] ... ??? ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 impImportBlockPending for BB138 impImportBlockPending for BB143 Importing BB143 (PC=1369) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1369 (0x559) ldloc.s 4 [ 1] 1371 (0x55b) ldc.i4.1 1 [ 2] 1372 (0x55c) sub [ 1] 1373 (0x55d) stloc.s 4 STMT00148 ( 0x559[E-] ... ??? ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 [ 0] 1375 (0x55f) br impImportBlockPending for BB191 Importing BB138 (PC=1313) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1313 (0x521) ldarg.0 [ 1] 1314 (0x522) ldloc.s 14 [ 2] 1316 (0x524) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00149 ( 0x521[E-] ... ??? ) [000676] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000674] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 [ 0] 1321 (0x529) ldloc.s 8 [ 1] 1323 (0x52b) brfalse.s STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 impImportBlockPending for BB139 impImportBlockPending for BB143 Importing BB139 (PC=1325) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1325 (0x52d) ldloc.s 4 [ 1] 1327 (0x52f) ldc.i4.1 1 [ 2] 1328 (0x530) ble.s STMT00151 ( 0x52D[E-] ... ??? ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 impImportBlockPending for BB140 impImportBlockPending for BB143 Importing BB140 (PC=1330) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1330 (0x532) ldloc.s 16 [ 1] 1332 (0x534) ldc.i4.0 0 [ 2] 1333 (0x535) blt.s STMT00152 ( 0x532[E-] ... ??? ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 impImportBlockPending for BB141 impImportBlockPending for BB143 Importing BB141 (PC=1335) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1335 (0x537) ldloc.s 4 [ 1] 1337 (0x539) ldloca.s 15 [ 2] 1339 (0x53b) ldloc.s 16 [ 3] 1341 (0x53d) call 0A000068 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=4 with ptr-to-span [000691] ----------- * ADDR byref [000690] -------N--- \--* LCL_VAR struct V19 loc15 and index [000692] ----------- * LCL_VAR int V20 loc16 [ 2] 1346 (0x542) ldind.i4 [ 2] 1347 (0x543) ldc.i4.1 1 [ 3] 1348 (0x544) add [ 2] 1349 (0x545) bne.un.s STMT00153 ( 0x537[E-] ... ??? ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* FIELD int :_length [000691] ----------- | | \--* ADDR byref [000690] -------N--- | | \--* LCL_VAR struct V19 loc15 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* FIELD byref :_reference [000695] ----------- | | \--* ADDR byref [000694] -------N--- | | \--* LCL_VAR struct V19 loc15 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 impImportBlockPending for BB142 impImportBlockPending for BB143 Importing BB142 (PC=1351) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1351 (0x547) ldarg.0 [ 1] 1352 (0x548) ldarg.3 [ 2] 1353 (0x549) callvirt 06002E0E In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00154 ( 0x547[E-] ... ??? ) [000711] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000710] ----------- this \--* LCL_VAR ref V03 arg3 [ 2] 1358 (0x54e) call 06003E5F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00155 ( 0x547[E-] ... ??? ) [000713] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000709] ----------- this +--* LCL_VAR byref V00 arg0 [000712] --C-------- arg1 \--* RET_EXPR ref (for [000711]) [ 0] 1363 (0x553) ldloc.s 16 [ 1] 1365 (0x555) ldc.i4.1 1 [ 2] 1366 (0x556) sub [ 1] 1367 (0x557) stloc.s 16 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 impImportBlockPending for BB143 Importing BB132 (PC=1287) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1287 (0x507) ldloc.s 4 [ 1] 1289 (0x509) ldloc.3 [ 2] 1290 (0x50a) bgt.s STMT00157 ( 0x507[E-] ... ??? ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 impImportBlockPending for BB133 impImportBlockPending for BB134 Importing BB134 (PC=1295) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1295 (0x50f) ldc.i4.s 48 [ 1] 1297 (0x511) br.s Spilling stack entries into temps STMT00158 ( 0x50F[E-] ... ??? ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 impImportBlockPending for BB136 Importing BB133 (PC=1292) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1292 (0x50c) ldc.i4.0 0 [ 1] 1293 (0x50d) br.s Spilling stack entries into temps STMT00159 ( 0x50C[E-] ... ??? ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 impImportBlockPending for BB136 Importing BB127 (PC=1262) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1262 (0x4ee) ldloc.s 10 [ 1] 1264 (0x4f0) ldc.i4.1 1 [ 2] 1265 (0x4f1) add [ 1] 1266 (0x4f2) stloc.s 10 STMT00160 ( 0x4EE[E-] ... ??? ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 [ 0] 1268 (0x4f4) ldloc.s 4 [ 1] 1270 (0x4f6) ldloc.2 [ 2] 1271 (0x4f7) ble.s STMT00161 ( 0x4F4[E-] ... ??? ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 impImportBlockPending for BB128 impImportBlockPending for BB129 Importing BB129 (PC=1276) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1276 (0x4fc) ldc.i4.s 48 *************** In impGetSpillTmpBase(BB129) lvaGrabTemps(1) returning 58..58 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00162 ( 0x4FC[E-] ... ??? ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 impImportBlockPending for BB130 Importing BB130 (PC=1278) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 1278 (0x4fe) stloc.s 14 STMT00163 ( ??? ... ??? ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 [ 0] 1280 (0x500) br.s impImportBlockPending for BB137 Importing BB128 (PC=1273) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1273 (0x4f9) ldc.i4.0 0 [ 1] 1274 (0x4fa) br.s Spilling stack entries into temps STMT00164 ( 0x4F9[E-] ... ??? ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 impImportBlockPending for BB130 Importing BB152 (PC=1486) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1486 (0x5ce) ldloc.s 12 [ 1] 1488 (0x5d0) ldarga.s 2 [ 2] 1490 (0x5d2) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00165 ( 0x5CE[E-] ... ??? ) [000754] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000753] ----------- this \--* ADDR byref [000752] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1495 (0x5d7) bge.s STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [000755] --C-------- \--* RET_EXPR int (for [000754]) impImportBlockPending for BB153 impImportBlockPending for BB155 Importing BB155 (PC=1521) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1521 (0x5f1) ldloc.s 12 [ 1] 1523 (0x5f3) ldarga.s 2 [ 2] 1525 (0x5f5) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00167 ( 0x5F1[E-] ... ??? ) [000761] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000760] ----------- this \--* ADDR byref [000759] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 1530 (0x5fa) bge STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [000762] --C-------- \--* RET_EXPR int (for [000761]) impImportBlockPending for BB156 impImportBlockPending for BB191 Importing BB156 (PC=1535) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1535 (0x5ff) ldloc.s 30 [ 1] 1537 (0x601) ldloc.s 12 [ 2] 1539 (0x603) conv.i [ 2] 1540 (0x604) ldc.i4.2 2 [ 3] 1541 (0x605) mul [ 2] 1542 (0x606) add [ 1] 1543 (0x607) ldind.u2 [ 1] 1544 (0x608) brfalse STMT00169 ( 0x5FF[E-] ... ??? ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 impImportBlockPending for BB157 impImportBlockPending for BB191 Importing BB157 (PC=1549) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1549 (0x60d) ldloc.s 12 [ 1] 1551 (0x60f) ldc.i4.1 1 [ 2] 1552 (0x610) add [ 1] 1553 (0x611) stloc.s 12 STMT00170 ( 0x60D[E-] ... ??? ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 [ 0] 1555 (0x613) br impImportBlockPending for BB191 Importing BB153 (PC=1497) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1497 (0x5d9) ldloc.s 30 [ 1] 1499 (0x5db) ldloc.s 12 [ 2] 1501 (0x5dd) conv.i [ 2] 1502 (0x5de) ldc.i4.2 2 [ 3] 1503 (0x5df) mul [ 2] 1504 (0x5e0) add [ 1] 1505 (0x5e1) ldind.u2 [ 1] 1506 (0x5e2) brfalse.s STMT00171 ( 0x5D9[E-] ... ??? ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 impImportBlockPending for BB154 impImportBlockPending for BB155 Importing BB154 (PC=1508) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1508 (0x5e4) ldloc.s 30 [ 1] 1510 (0x5e6) ldloc.s 12 [ 2] 1512 (0x5e8) conv.i [ 2] 1513 (0x5e9) ldc.i4.2 2 [ 3] 1514 (0x5ea) mul [ 2] 1515 (0x5eb) add [ 1] 1516 (0x5ec) ldind.u2 [ 1] 1517 (0x5ed) ldloc.s 14 [ 2] 1519 (0x5ef) bne.un.s STMT00172 ( 0x5E4[E-] ... ??? ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 impImportBlockPending for BB155 impImportBlockPending for BB151 Importing BB151 (PC=1466) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1466 (0x5ba) ldarg.0 [ 1] 1467 (0x5bb) ldloc.s 30 [ 2] 1469 (0x5bd) ldloc.s 12 [ 3] 1471 (0x5bf) dup [ 4] 1472 (0x5c0) ldc.i4.1 1 [ 5] 1473 (0x5c1) add [ 4] 1474 (0x5c2) stloc.s 12 lvaGrabTemp returning 59 (V59 tmp19) called for impSpillLclRefs. STMT00174 ( 0x5BA[E-] ... ??? ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 [ 3] 1476 (0x5c4) conv.i [ 3] 1477 (0x5c5) ldc.i4.2 2 [ 4] 1478 (0x5c6) mul [ 3] 1479 (0x5c7) add [ 2] 1480 (0x5c8) ldind.u2 [ 2] 1481 (0x5c9) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00175 ( ??? ... ??? ) [000820] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000803] ----------- this +--* LCL_VAR byref V00 arg0 [000819] ---XG------ arg1 \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 impImportBlockPending for BB152 Importing BB103 (PC=1030) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1030 (0x406) ldloc.s 14 [ 1] 1032 (0x408) ldc.i4.s 35 [ 2] 1034 (0x40a) beq.s STMT00176 ( 0x406[E-] ... ??? ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 impImportBlockPending for BB104 impImportBlockPending for BB116 Importing BB116 (PC=1133) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1133 (0x46d) ldloc.s 10 [ 1] 1135 (0x46f) ldc.i4.0 0 [ 2] 1136 (0x470) bgt.s STMT00177 ( 0x46D[E-] ... ??? ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 impImportBlockPending for BB117 impImportBlockPending for BB107 Importing BB107 (PC=1050) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1050 (0x41a) ldarg.0 [ 1] 1051 (0x41b) ldloc.s 32 [ 2] 1053 (0x41d) ldind.u1 [ 2] 1054 (0x41e) brtrue.s STMT00178 ( 0x41A[E-] ... ??? ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 *************** In impGetSpillTmpBase(BB107) lvaGrabTemps(1) returning 60..60 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00179 ( ??? ... ??? ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 impImportBlockPending for BB108 impImportBlockPending for BB109 Importing BB109 (PC=1060) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 1060 (0x424) ldloc.s 32 [ 2] 1062 (0x426) dup [ 3] 1063 (0x427) ldc.i4.1 1 [ 4] 1064 (0x428) add [ 3] 1065 (0x429) stloc.s 32 lvaGrabTemp returning 61 (V61 tmp21) called for impSpillLclRefs. STMT00181 ( ??? ... ??? ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 [ 2] 1067 (0x42b) ldind.u1 *************** In impGetSpillTmpBase(BB109) lvaGrabTemps(2) returning 62..63 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00182 ( ??? ... ??? ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 impImportBlockPending for BB110 Importing BB110 (PC=1068) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 2] 1068 (0x42c) call 06003E5E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00184 ( ??? ... ??? ) [000859] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000857] ----------- this +--* LCL_VAR byref V62 tmp22 [000858] ----------- arg1 \--* LCL_VAR int V63 tmp23 [ 0] 1073 (0x431) ldloc.s 8 [ 1] 1075 (0x433) brfalse.s STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 impImportBlockPending for BB111 impImportBlockPending for BB115 Importing BB115 (PC=1121) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1121 (0x461) ldloc.s 4 [ 1] 1123 (0x463) ldc.i4.1 1 [ 2] 1124 (0x464) sub [ 1] 1125 (0x465) stloc.s 4 STMT00186 ( 0x461[E-] ... ??? ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 [ 0] 1127 (0x467) ldloc.s 10 [ 1] 1129 (0x469) ldc.i4.1 1 [ 2] 1130 (0x46a) sub [ 1] 1131 (0x46b) stloc.s 10 STMT00187 ( 0x467[E-] ... ??? ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 impImportBlockPending for BB116 Importing BB111 (PC=1077) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1077 (0x435) ldloc.s 4 [ 1] 1079 (0x437) ldc.i4.1 1 [ 2] 1080 (0x438) ble.s STMT00188 ( 0x435[E-] ... ??? ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 impImportBlockPending for BB112 impImportBlockPending for BB115 Importing BB112 (PC=1082) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1082 (0x43a) ldloc.s 16 [ 1] 1084 (0x43c) ldc.i4.0 0 [ 2] 1085 (0x43d) blt.s STMT00189 ( 0x43A[E-] ... ??? ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 impImportBlockPending for BB113 impImportBlockPending for BB115 Importing BB113 (PC=1087) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1087 (0x43f) ldloc.s 4 [ 1] 1089 (0x441) ldloca.s 15 [ 2] 1091 (0x443) ldloc.s 16 [ 3] 1093 (0x445) call 0A000068 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=4 with ptr-to-span [000884] ----------- * ADDR byref [000883] -------N--- \--* LCL_VAR struct V19 loc15 and index [000885] ----------- * LCL_VAR int V20 loc16 [ 2] 1098 (0x44a) ldind.i4 [ 2] 1099 (0x44b) ldc.i4.1 1 [ 3] 1100 (0x44c) add [ 2] 1101 (0x44d) bne.un.s STMT00190 ( 0x43F[E-] ... ??? ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* FIELD int :_length [000884] ----------- | | \--* ADDR byref [000883] -------N--- | | \--* LCL_VAR struct V19 loc15 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* FIELD byref :_reference [000888] ----------- | | \--* ADDR byref [000887] -------N--- | | \--* LCL_VAR struct V19 loc15 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 impImportBlockPending for BB114 impImportBlockPending for BB115 Importing BB114 (PC=1103) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1103 (0x44f) ldarg.0 [ 1] 1104 (0x450) ldarg.3 [ 2] 1105 (0x451) callvirt 06002E0E In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00191 ( 0x44F[E-] ... ??? ) [000904] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000903] ----------- this \--* LCL_VAR ref V03 arg3 [ 2] 1110 (0x456) call 06003E5F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00192 ( 0x44F[E-] ... ??? ) [000906] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000902] ----------- this +--* LCL_VAR byref V00 arg0 [000905] --C-------- arg1 \--* RET_EXPR ref (for [000904]) [ 0] 1115 (0x45b) ldloc.s 16 [ 1] 1117 (0x45d) ldc.i4.1 1 [ 2] 1118 (0x45e) sub [ 1] 1119 (0x45f) stloc.s 16 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 impImportBlockPending for BB115 Importing BB108 (PC=1056) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 1056 (0x420) ldc.i4.s 48 [ 2] 1058 (0x422) br.s Spilling stack entries into temps STMT00194 ( ??? ... ??? ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 impImportBlockPending for BB110 Importing BB104 (PC=1036) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1036 (0x40c) ldloc.s 14 [ 1] 1038 (0x40e) ldc.i4.s 46 [ 2] 1040 (0x410) beq.s STMT00196 ( 0x40C[E-] ... ??? ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 impImportBlockPending for BB105 impImportBlockPending for BB116 Importing BB105 (PC=1042) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1042 (0x412) ldloc.s 14 [ 1] 1044 (0x414) ldc.i4.s 48 [ 2] 1046 (0x416) beq.s STMT00197 ( 0x412[E-] ... ??? ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 impImportBlockPending for BB106 impImportBlockPending for BB116 Importing BB106 (PC=1048) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 1048 (0x418) br.s impImportBlockPending for BB117 Importing BB98 (PC=976) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 976 (0x3d0) ldloc.s 11 [ 1] 978 (0x3d2) brtrue.s STMT00198 ( 0x3D0[E-] ... ??? ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 impImportBlockPending for BB99 impImportBlockPending for BB101 Importing BB99 (PC=980) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 980 (0x3d4) ldarg.1 [ 1] 981 (0x3d5) ldfld 040004D2 [ 1] 986 (0x3da) brfalse.s STMT00199 ( 0x3D4[E-] ... ??? ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 impImportBlockPending for BB100 impImportBlockPending for BB101 Importing BB100 (PC=988) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 988 (0x3dc) ldarg.0 [ 1] 989 (0x3dd) ldarg.3 [ 2] 990 (0x3de) callvirt 06002E08 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00200 ( 0x3DC[E-] ... ??? ) [000938] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this (exactContextHnd=0x4000000000424641) [000937] ----------- this \--* LCL_VAR ref V03 arg3 [ 2] 995 (0x3e3) call 06003E5F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00201 ( 0x3DC[E-] ... ??? ) [000940] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000936] ----------- this +--* LCL_VAR byref V00 arg0 [000939] --C-------- arg1 \--* RET_EXPR ref (for [000938]) impImportBlockPending for BB101 Importing BB80 (PC=781) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 781 (0x30d) ldarg.3 [ 1] 782 (0x30e) callvirt 06002E0E In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00202 ( 0x30D[E-] ... ??? ) [000942] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000941] ----------- this \--* LCL_VAR ref V03 arg3 [ 1] 787 (0x313) callvirt 06000818 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.String.get_Length: Recognized [ 1] 792 (0x318) ldc.i4.0 0 [ 2] 793 (0x319) ble STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [000943] --C-------- | \--* RET_EXPR ref (for [000942]) [000945] ----------- \--* CNS_INT int 0 impImportBlockPending for BB81 impImportBlockPending for BB97 Importing BB81 (PC=798) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 798 (0x31e) ldarg.3 [ 1] 799 (0x31f) ldfld 0400092D [ 1] 804 (0x324) stloc.s 22Querying runtime about current class of field : (declared as int[]) Field's current class not available STMT00204 ( 0x31E[E-] ... ??? ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 [ 0] 806 (0x326) ldc.i4.0 0 [ 1] 807 (0x327) stloc.s 23 STMT00205 ( 0x326[E-] ... ??? ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 [ 0] 809 (0x329) ldc.i4.0 0 [ 1] 810 (0x32a) stloc.s 24 STMT00206 ( 0x329[E-] ... ??? ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 [ 0] 812 (0x32c) ldloc.s 22 [ 1] 814 (0x32e) ldlen [ 1] 815 (0x32f) conv.i4 [ 1] 816 (0x330) stloc.s 25 STMT00207 ( 0x32C[E-] ... ??? ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 [ 0] 818 (0x332) ldloc.s 25 [ 1] 820 (0x334) brfalse.s STMT00208 ( 0x332[E-] ... ??? ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 impImportBlockPending for BB82 impImportBlockPending for BB83 Importing BB83 (PC=829) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 829 (0x33d) ldloc.s 24 [ 1] 831 (0x33f) stloc.s 26 STMT00209 ( 0x33D[E-] ... ??? ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 [ 0] 833 (0x341) ldloc.s 4 [ 1] 835 (0x343) ldloc.s 10 [ 2] 837 (0x345) ldc.i4.0 0 [ 3] 838 (0x346) blt.s STMT00210 ( 0x341[E-] ... ??? ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 *************** In impGetSpillTmpBase(BB83) lvaGrabTemps(1) returning 64..64 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00211 ( ??? ... ??? ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 impImportBlockPending for BB84 impImportBlockPending for BB85 Importing BB85 (PC=843) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 843 (0x34b) ldloc.s 10 *************** In impGetSpillTmpBase(BB85) lvaGrabTemps(2) returning 65..66 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00212 ( ??? ... ??? ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 impImportBlockPending for BB86 Importing BB86 (PC=845) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 2] 845 (0x34d) add [ 1] 846 (0x34e) stloc.s 27 STMT00214 ( ??? ... ??? ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 [ 0] 848 (0x350) ldloc.2 [ 1] 849 (0x351) ldloc.s 27 [ 2] 851 (0x353) bgt.s STMT00215 ( 0x350[E-] ... ??? ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 impImportBlockPending for BB87 impImportBlockPending for BB88 Importing BB88 (PC=857) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 857 (0x359) ldloc.2 *************** In impGetSpillTmpBase(BB88) lvaGrabTemps(1) returning 67..67 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00216 ( 0x359[E-] ... ??? ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 impImportBlockPending for BB89 Importing BB89 (PC=858) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 858 (0x35a) stloc.s 28 STMT00217 ( ??? ... ??? ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 [ 0] 860 (0x35c) br.s impImportBlockPending for BB96 Importing BB96 (PC=962) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 962 (0x3c2) ldloc.s 28 [ 1] 964 (0x3c4) ldloc.s 24 [ 2] 966 (0x3c6) bgt.s STMT00218 ( 0x3C2[E-] ... ??? ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 impImportBlockPending for BB97 impImportBlockPending for BB90 Importing BB90 (PC=862) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 862 (0x35e) ldloc.s 26 [ 1] 864 (0x360) brfalse.s STMT00219 ( 0x35E[E-] ... ??? ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 impImportBlockPending for BB91 impImportBlockPending for BB97 Importing BB91 (PC=866) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 866 (0x362) ldloc.s 16 [ 1] 868 (0x364) ldc.i4.1 1 [ 2] 869 (0x365) add [ 1] 870 (0x366) stloc.s 16 STMT00220 ( 0x362[E-] ... ??? ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 [ 0] 872 (0x368) ldloc.s 16 [ 1] 874 (0x36a) ldloca.s 15 [ 2] 876 (0x36c) call 0A000067 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00221 ( 0x368[E-] ... ??? ) [001018] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001017] ----------- this \--* ADDR byref [001016] -------N--- \--* LCL_VAR struct V19 loc15 [ 2] 881 (0x371) blt.s STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001019] --C-------- \--* RET_EXPR int (for [001018]) impImportBlockPending for BB92 impImportBlockPending for BB93 Importing BB93 (PC=922) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 922 (0x39a) ldloca.s 15 [ 1] 924 (0x39c) ldloc.s 16 [ 2] 926 (0x39e) call 0A000068 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=4 with ptr-to-span [001023] ----------- * ADDR byref [001022] -------N--- \--* LCL_VAR struct V19 loc15 and index [001024] ----------- * LCL_VAR int V20 loc16 [ 1] 931 (0x3a3) ldloc.s 24 [ 2] 933 (0x3a5) stind.i4 STMT00223 ( 0x39A[E-] ... ??? ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* FIELD int :_length [001023] ----------- | | \--* ADDR byref [001022] -------N--- | | \--* LCL_VAR struct V19 loc15 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* FIELD byref :_reference [001027] ----------- | | \--* ADDR byref [001026] -------N--- | | \--* LCL_VAR struct V19 loc15 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 [ 0] 934 (0x3a6) ldloc.s 23 [ 1] 936 (0x3a8) ldloc.s 25 [ 2] 938 (0x3aa) ldc.i4.1 1 [ 3] 939 (0x3ab) sub [ 2] 940 (0x3ac) bge.s STMT00224 ( 0x3A6[E-] ... ??? ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 impImportBlockPending for BB94 impImportBlockPending for BB95 Importing BB95 (PC=955) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 955 (0x3bb) ldloc.s 24 [ 1] 957 (0x3bd) ldloc.s 26 [ 2] 959 (0x3bf) add [ 1] 960 (0x3c0) stloc.s 24 STMT00225 ( 0x3BB[E-] ... ??? ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 impImportBlockPending for BB96 Importing BB94 (PC=942) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 942 (0x3ae) ldloc.s 23 [ 1] 944 (0x3b0) ldc.i4.1 1 [ 2] 945 (0x3b1) add [ 1] 946 (0x3b2) stloc.s 23 STMT00226 ( 0x3AE[E-] ... ??? ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 [ 0] 948 (0x3b4) ldloc.s 22 [ 1] 950 (0x3b6) ldloc.s 23 [ 2] 952 (0x3b8) ldelem.i4 [ 1] 953 (0x3b9) stloc.s 26 STMT00227 ( 0x3B4[E-] ... ??? ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 impImportBlockPending for BB95 Importing BB92 (PC=883) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 883 (0x373) ldloca.s 15 [ 1] 885 (0x375) call 0A000067 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00228 ( 0x373[E-] ... ??? ) [001063] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001062] ----------- this \--* ADDR byref [001061] -------N--- \--* LCL_VAR struct V19 loc15 [ 1] 890 (0x37a) ldc.i4.2 2 [ 2] 891 (0x37b) mul [ 1] 892 (0x37c) newarr 0200011B [ 1] 897 (0x381) stloc.s 29 lvaUpdateClass: Updating class for V33 from (40000000004217B0) int[] to (40000000004217B0) int[] [exact] STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001064] --C-------- +--* RET_EXPR int (for [001063]) [001065] ----------- \--* CNS_INT int 2 [ 0] 899 (0x383) ldloca.s 15 [ 1] 901 (0x385) ldloc.s 29 [ 2] 903 (0x387) call 0A000616 In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00230 ( 0x383[E-] ... ??? ) [001074] I-C-G------ * CALL r2r_ind struct System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] (exactContextHnd=0x40000000004219E1) [001073] ----------- arg0 \--* LCL_VAR ref V33 loc29 [ 2] 908 (0x38c) call 0A000617 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 Calling impNormStructVal on: [001075] --C-------- * RET_EXPR struct(for [001074]) lvaGrabTemp returning 68 (V68 tmp28) called for struct address for call/obj. STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct V68 tmp28 [001075] --C-------- \--* RET_EXPR struct(for [001074]) resulting tree: [001081] n---------- * OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00232 ( ??? ... ??? ) [001076] I-C-G------ * CALL r2r_ind void System.Span`1[int]:CopyTo(System.Span`1[int]):this (exactContextHnd=0x40000000004219E1) [001072] ----------- this +--* ADDR byref [001071] -------N--- | \--* LCL_VAR struct V19 loc15 [001081] n---------- arg1 \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 [ 0] 913 (0x391) ldloc.s 29 [ 1] 915 (0x393) call 0A000616 In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00233 ( 0x391[E-] ... ??? ) [001083] I-C-G------ * CALL r2r_ind struct System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] (exactContextHnd=0x40000000004219E1) [001082] ----------- arg0 \--* LCL_VAR ref V33 loc29 [ 1] 920 (0x398) stloc.s 15 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct V19 loc15 [001084] --C-------- \--* RET_EXPR struct(for [001083]) impImportBlockPending for BB93 Importing BB87 (PC=853) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 853 (0x355) ldloc.s 27 [ 1] 855 (0x357) br.s Spilling stack entries into temps STMT00235 ( 0x355[E-] ... ??? ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 impImportBlockPending for BB89 Importing BB84 (PC=840) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 840 (0x348) ldc.i4.0 0 [ 2] 841 (0x349) br.s Spilling stack entries into temps STMT00236 ( ??? ... ??? ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 impImportBlockPending for BB86 Importing BB82 (PC=822) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 822 (0x336) ldloc.s 22 [ 1] 824 (0x338) ldloc.s 23 [ 2] 826 (0x33a) ldelem.i4 [ 1] 827 (0x33b) stloc.s 24 STMT00238 ( 0x336[E-] ... ??? ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 impImportBlockPending for BB83 Importing BB76 (PC=729) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 729 (0x2d9) ldloc.1 [ 1] 730 (0x2da) br.s Spilling stack entries into temps STMT00239 ( 0x2D9[E-] ... ??? ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 impImportBlockPending for BB78 Importing BB74 (PC=712) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 712 (0x2c8) ldloc.1 [ 1] 713 (0x2c9) stloc.s 4 STMT00240 ( 0x2C8[E-] ... ??? ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 [ 0] 715 (0x2cb) ldc.i4.0 0 [ 1] 716 (0x2cc) stloc.s 10 STMT00241 ( 0x2CB[E-] ... ??? ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 [ 0] 718 (0x2ce) br.s impImportBlockPending for BB79 Importing BB71 (PC=701) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 701 (0x2bd) ldc.i4.0 0 [ 1] 702 (0x2be) br.s Spilling stack entries into temps STMT00242 ( 0x2BD[E-] ... ??? ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 impImportBlockPending for BB73 Importing BB68 (PC=690) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 690 (0x2b2) ldc.i4.0 0 [ 1] 691 (0x2b3) br.s Spilling stack entries into temps STMT00243 ( 0x2B2[E-] ... ??? ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 impImportBlockPending for BB70 Importing BB65 (PC=672) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 672 (0x2a0) ldarg.1 [ 1] 673 (0x2a1) ldc.i4.0 0 [ 2] 674 (0x2a2) stfld 040004D3 STMT00244 ( 0x2A0[E-] ... ??? ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 impImportBlockPending for BB66 Importing BB58 (PC=594) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 594 (0x252) ldarg.1 [ 1] 595 (0x253) ldflda 040004D2 [ 1] 600 (0x258) dup lvaGrabTemp returning 69 (V69 tmp29) called for dup spill. STMT00245 ( 0x252[E-] ... ??? ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 [ 2] 601 (0x259) ldind.i4 [ 2] 602 (0x25a) ldloc.s 9 [ 3] 604 (0x25c) add [ 2] 605 (0x25d) stind.i4 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 [ 0] 606 (0x25e) ldloc.s 5 [ 1] 608 (0x260) brtrue.s STMT00247 ( 0x25E[E-] ... ??? ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 impImportBlockPending for BB59 impImportBlockPending for BB60 Importing BB60 (PC=622) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 622 (0x26e) ldloc.0 *************** In impGetSpillTmpBase(BB60) lvaGrabTemps(1) returning 70..70 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00248 ( 0x26E[E-] ... ??? ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 impImportBlockPending for BB61 Importing BB61 (PC=623) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 623 (0x26f) stloc.s 20 STMT00249 ( ??? ... ??? ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 [ 0] 625 (0x271) ldarg.1 [ 1] 626 (0x272) ldloc.s 20 [ 2] 628 (0x274) ldc.i4.0 0 [ 3] 629 (0x275) call 06001797 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' STMT00250 ( 0x271[E-] ... ??? ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 [ 0] 634 (0x27a) ldloc.s 13 [ 1] 636 (0x27c) ldind.u1 [ 1] 637 (0x27d) brtrue.s STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 impImportBlockPending for BB62 impImportBlockPending for BB67 Importing BB62 (PC=639) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 639 (0x27f) ldarg.2 [ 1] 640 (0x280) ldc.i4.2 2 [ 2] 641 (0x281) call 06001798 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 Calling impNormStructVal on: [001157] ----------- * LCL_VAR struct V02 arg2 resulting tree: [001161] n---------- * OBJ struct [001160] ----------- \--* ADDR byref [001157] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 646 (0x286) stloc.s 12 STMT00252 ( 0x27F[E-] ... ??? ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] n---------- arg0 +--* OBJ struct [001160] ----------- | \--* ADDR byref [001157] -------N--- | \--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 [ 0] 648 (0x288) ldloc.s 12 [ 1] 650 (0x28a) ldloc.s 11 [ 2] 652 (0x28c) beq.s STMT00253 ( 0x288[E-] ... ??? ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 impImportBlockPending for BB63 impImportBlockPending for BB67 Importing BB63 (PC=654) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 654 (0x28e) ldloc.s 12 [ 1] 656 (0x290) stloc.s 11 STMT00254 ( 0x28E[E-] ... ??? ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 [ 0] 658 (0x292) br impImportBlockPending for BB07 Importing BB59 (PC=610) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 610 (0x262) ldarg.1 [ 1] 611 (0x263) ldfld 040004D2 [ 1] 616 (0x268) ldloc.0 [ 2] 617 (0x269) add [ 1] 618 (0x26a) ldloc.1 [ 2] 619 (0x26b) sub [ 1] 620 (0x26c) br.s Spilling stack entries into temps STMT00255 ( 0x262[E-] ... ??? ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 impImportBlockPending for BB61 Importing BB54 (PC=570) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 570 (0x23a) ldloc.s 6 [ 1] 572 (0x23c) ldloc.1 [ 2] 573 (0x23d) bne.un.s STMT00256 ( 0x23A[E-] ... ??? ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 impImportBlockPending for BB55 impImportBlockPending for BB56 Importing BB56 (PC=586) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 586 (0x24a) ldc.i4.1 1 [ 1] 587 (0x24b) stloc.s 8 STMT00257 ( 0x24A[E-] ... ??? ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 impImportBlockPending for BB57 Importing BB55 (PC=575) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 575 (0x23f) ldloc.s 9 [ 1] 577 (0x241) ldloc.s 7 [ 2] 579 (0x243) ldc.i4.3 3 [ 3] 580 (0x244) mul [ 2] 581 (0x245) sub [ 1] 582 (0x246) stloc.s 9 STMT00258 ( 0x23F[E-] ... ??? ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 [ 0] 584 (0x248) br.s impImportBlockPending for BB57 Importing BB52 (PC=563) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 563 (0x233) ldloc.0 [ 1] 564 (0x234) stloc.1 STMT00259 ( 0x233[E-] ... ??? ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 impImportBlockPending for BB53 Importing BB49 (PC=527) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 527 (0x20f) ldloc.s 18 [ 1] 529 (0x211) ldloc.s 12 [ 2] 531 (0x213) dup [ 3] 532 (0x214) ldc.i4.1 1 [ 4] 533 (0x215) add [ 3] 534 (0x216) stloc.s 12 lvaGrabTemp returning 71 (V71 tmp31) called for impSpillLclRefs. STMT00261 ( 0x20F[E-] ... ??? ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 [ 2] 536 (0x218) conv.i [ 2] 537 (0x219) ldc.i4.2 2 [ 3] 538 (0x21a) mul [ 2] 539 (0x21b) add [ 1] 540 (0x21c) ldind.u2 [ 1] 541 (0x21d) dup lvaGrabTemp returning 72 (V72 tmp32) called for dup spill. STMT00262 ( ??? ... ??? ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 [ 2] 542 (0x21e) stloc.s 14 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 [ 1] 544 (0x220) brfalse.s STMT00264 ( ??? ... ??? ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 impImportBlockPending for BB50 impImportBlockPending for BB51 Importing BB50 (PC=546) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 546 (0x222) ldloc.s 14 [ 1] 548 (0x224) ldc.i4.s 59 [ 2] 550 (0x226) bne.un STMT00265 ( 0x222[E-] ... ??? ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 impImportBlockPending for BB51 impImportBlockPending for BB08 Importing BB08 (PC=091) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 91 (0x05b) ldloc.s 14 [ 1] 93 (0x05d) ldc.i4.s 69 [ 2] 95 (0x05f) bgt.un.s STMT00266 ( 0x05B[E-] ... ??? ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 impImportBlockPending for BB09 impImportBlockPending for BB13 Importing BB13 (PC=175) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 175 (0x0af) ldloc.s 14 [ 1] 177 (0x0b1) ldc.i4.s 92 [ 2] 179 (0x0b3) beq STMT00267 ( 0x0AF[E-] ... ??? ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 impImportBlockPending for BB14 impImportBlockPending for BB36 Importing BB36 (PC=373) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 373 (0x175) ldloc.s 12 [ 1] 375 (0x177) ldarga.s 2 [ 2] 377 (0x179) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00268 ( 0x175[E-] ... ??? ) [001237] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001236] ----------- this \--* ADDR byref [001235] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 382 (0x17e) bge STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001238] --C-------- \--* RET_EXPR int (for [001237]) impImportBlockPending for BB37 impImportBlockPending for BB48 Importing BB37 (PC=387) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 387 (0x183) ldloc.s 18 [ 1] 389 (0x185) ldloc.s 12 [ 2] 391 (0x187) conv.i [ 2] 392 (0x188) ldc.i4.2 2 [ 3] 393 (0x189) mul [ 2] 394 (0x18a) add [ 1] 395 (0x18b) ldind.u2 [ 1] 396 (0x18c) brfalse.s STMT00270 ( 0x183[E-] ... ??? ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 impImportBlockPending for BB38 impImportBlockPending for BB48 Importing BB38 (PC=398) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 398 (0x18e) ldloc.s 12 [ 1] 400 (0x190) ldc.i4.1 1 [ 2] 401 (0x191) add [ 1] 402 (0x192) stloc.s 12 STMT00271 ( 0x18E[E-] ... ??? ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 [ 0] 404 (0x194) br.s impImportBlockPending for BB48 Importing BB14 (PC=184) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 184 (0x0b8) ldloc.s 14 [ 1] 186 (0x0ba) ldc.i4.s 101 [ 2] 188 (0x0bc) beq STMT00272 ( 0x0B8[E-] ... ??? ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 impImportBlockPending for BB15 impImportBlockPending for BB39 Importing BB39 (PC=406) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 406 (0x196) ldloc.s 12 [ 1] 408 (0x198) ldarga.s 2 [ 2] 410 (0x19a) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00273 ( 0x196[E-] ... ??? ) [001264] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001263] ----------- this \--* ADDR byref [001262] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 415 (0x19f) bge.s STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001265] --C-------- \--* RET_EXPR int (for [001264]) impImportBlockPending for BB40 impImportBlockPending for BB41 Importing BB41 (PC=430) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 430 (0x1ae) ldloc.s 12 [ 1] 432 (0x1b0) ldc.i4.1 1 [ 2] 433 (0x1b1) add [ 1] 434 (0x1b2) ldarga.s 2 [ 2] 436 (0x1b4) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00275 ( 0x1AE[E-] ... ??? ) [001273] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001272] ----------- this \--* ADDR byref [001271] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 441 (0x1b9) bge.s STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001274] --C-------- \--* RET_EXPR int (for [001273]) impImportBlockPending for BB42 impImportBlockPending for BB48 Importing BB42 (PC=443) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 443 (0x1bb) ldloc.s 18 [ 1] 445 (0x1bd) ldloc.s 12 [ 2] 447 (0x1bf) conv.i [ 2] 448 (0x1c0) ldc.i4.2 2 [ 3] 449 (0x1c1) mul [ 2] 450 (0x1c2) add [ 1] 451 (0x1c3) ldind.u2 [ 1] 452 (0x1c4) ldc.i4.s 43 [ 2] 454 (0x1c6) beq.s STMT00277 ( 0x1BB[E-] ... ??? ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 impImportBlockPending for BB43 impImportBlockPending for BB44 Importing BB44 (PC=469) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 469 (0x1d5) ldloc.s 18 [ 1] 471 (0x1d7) ldloc.s 12 [ 2] 473 (0x1d9) ldc.i4.1 1 [ 3] 474 (0x1da) add [ 2] 475 (0x1db) conv.i [ 2] 476 (0x1dc) ldc.i4.2 2 [ 3] 477 (0x1dd) mul [ 2] 478 (0x1de) add [ 1] 479 (0x1df) ldind.u2 [ 1] 480 (0x1e0) ldc.i4.s 48 [ 2] 482 (0x1e2) bne.un.s STMT00278 ( 0x1D5[E-] ... ??? ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 impImportBlockPending for BB45 impImportBlockPending for BB48 Importing BB45 (PC=484) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 484 (0x1e4) ldloc.s 12 [ 1] 486 (0x1e6) ldc.i4.1 1 [ 2] 487 (0x1e7) add [ 1] 488 (0x1e8) dup lvaGrabTemp returning 73 (V73 tmp33) called for dup spill. STMT00279 ( 0x1E4[E-] ... ??? ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 [ 2] 489 (0x1e9) stloc.s 12 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 [ 1] 491 (0x1eb) ldarga.s 2 [ 2] 493 (0x1ed) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00281 ( ??? ... ??? ) [001312] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001311] ----------- this \--* ADDR byref [001310] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 498 (0x1f2) bge.s STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001313] --C-------- \--* RET_EXPR int (for [001312]) impImportBlockPending for BB46 impImportBlockPending for BB47 Importing BB47 (PC=513) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 513 (0x201) ldc.i4.1 1 [ 1] 514 (0x202) stloc.s 5 STMT00283 ( 0x201[E-] ... ??? ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 impImportBlockPending for BB48 Importing BB46 (PC=500) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 500 (0x1f4) ldloc.s 18 [ 1] 502 (0x1f6) ldloc.s 12 [ 2] 504 (0x1f8) conv.i [ 2] 505 (0x1f9) ldc.i4.2 2 [ 3] 506 (0x1fa) mul [ 2] 507 (0x1fb) add [ 1] 508 (0x1fc) ldind.u2 [ 1] 509 (0x1fd) ldc.i4.s 48 [ 2] 511 (0x1ff) beq.s STMT00284 ( 0x1F4[E-] ... ??? ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 impImportBlockPending for BB47 impImportBlockPending for BB45 Importing BB43 (PC=456) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 456 (0x1c8) ldloc.s 18 [ 1] 458 (0x1ca) ldloc.s 12 [ 2] 460 (0x1cc) conv.i [ 2] 461 (0x1cd) ldc.i4.2 2 [ 3] 462 (0x1ce) mul [ 2] 463 (0x1cf) add [ 1] 464 (0x1d0) ldind.u2 [ 1] 465 (0x1d1) ldc.i4.s 45 [ 2] 467 (0x1d3) bne.un.s STMT00285 ( 0x1C8[E-] ... ??? ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 impImportBlockPending for BB44 impImportBlockPending for BB48 Importing BB40 (PC=417) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 417 (0x1a1) ldloc.s 18 [ 1] 419 (0x1a3) ldloc.s 12 [ 2] 421 (0x1a5) conv.i [ 2] 422 (0x1a6) ldc.i4.2 2 [ 3] 423 (0x1a7) mul [ 2] 424 (0x1a8) add [ 1] 425 (0x1a9) ldind.u2 [ 1] 426 (0x1aa) ldc.i4.s 48 [ 2] 428 (0x1ac) beq.s STMT00286 ( 0x1A1[E-] ... ??? ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 impImportBlockPending for BB41 impImportBlockPending for BB45 Importing BB15 (PC=193) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 193 (0x0c1) ldloc.s 14 [ 1] 195 (0x0c3) ldc.i4 8240 [ 2] 200 (0x0c8) beq.s STMT00287 ( 0x0C1[E-] ... ??? ) [001355] ----------- * JTRUE void [001354] ----------- \--* EQ int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 impImportBlockPending for BB16 impImportBlockPending for BB31 Importing BB31 (PC=311) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 311 (0x137) ldloc.s 9 [ 1] 313 (0x139) ldc.i4.3 3 [ 2] 314 (0x13a) add [ 1] 315 (0x13b) stloc.s 9 STMT00288 ( 0x137[E-] ... ??? ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 [ 0] 317 (0x13d) br impImportBlockPending for BB48 Importing BB16 (PC=202) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 202 (0x0ca) br impImportBlockPending for BB48 Importing BB09 (PC=097) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 97 (0x061) ldloc.s 14 [ 1] 99 (0x063) ldc.i4.s 34 [ 2] 101 (0x065) sub [ 1] 102 (0x066) switch STMT00289 ( 0x061[E-] ... ??? ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 impImportBlockPending for BB32 impImportBlockPending for BB17 impImportBlockPending for BB48 impImportBlockPending for BB30 impImportBlockPending for BB48 impImportBlockPending for BB32 impImportBlockPending for BB10 Importing BB10 (PC=131) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 131 (0x083) ldloc.s 14 [ 1] 133 (0x085) ldc.i4.s 44 [ 2] 135 (0x087) sub [ 1] 136 (0x088) switch STMT00290 ( 0x083[E-] ... ??? ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 impImportBlockPending for BB23 impImportBlockPending for BB48 impImportBlockPending for BB21 impImportBlockPending for BB48 impImportBlockPending for BB18 impImportBlockPending for BB11 Importing BB11 (PC=161) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 161 (0x0a1) ldloc.s 14 [ 1] 163 (0x0a3) ldc.i4.s 69 [ 2] 165 (0x0a5) beq STMT00291 ( 0x0A1[E-] ... ??? ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 impImportBlockPending for BB12 impImportBlockPending for BB39 Importing BB12 (PC=170) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 170 (0x0aa) br impImportBlockPending for BB48 Importing BB18 (PC=216) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 216 (0x0d8) ldloc.2 [ 1] 217 (0x0d9) ldc.i4 2147483647 [ 2] 222 (0x0de) bne.un.s STMT00292 ( 0x0D8[E-] ... ??? ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF impImportBlockPending for BB19 impImportBlockPending for BB20 Importing BB20 (PC=226) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 226 (0x0e2) ldloc.0 [ 1] 227 (0x0e3) ldc.i4.1 1 [ 2] 228 (0x0e4) add [ 1] 229 (0x0e5) stloc.0 STMT00293 ( 0x0E2[E-] ... ??? ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 [ 0] 230 (0x0e6) ldloc.0 [ 1] 231 (0x0e7) stloc.3 STMT00294 ( 0x0E6[E-] ... ??? ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 [ 0] 232 (0x0e8) br impImportBlockPending for BB48 Importing BB19 (PC=224) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 224 (0x0e0) ldloc.0 [ 1] 225 (0x0e1) stloc.2 STMT00295 ( 0x0E0[E-] ... ??? ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 impImportBlockPending for BB20 Importing BB21 (PC=237) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 237 (0x0ed) ldloc.1 [ 1] 238 (0x0ee) ldc.i4.0 0 [ 2] 239 (0x0ef) bge STMT00296 ( 0x0ED[E-] ... ??? ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 impImportBlockPending for BB22 impImportBlockPending for BB48 Importing BB22 (PC=244) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 244 (0x0f4) ldloc.0 [ 1] 245 (0x0f5) stloc.1 STMT00297 ( 0x0F4[E-] ... ??? ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 [ 0] 246 (0x0f6) br impImportBlockPending for BB48 Importing BB23 (PC=251) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 251 (0x0fb) ldloc.0 [ 1] 252 (0x0fc) ldc.i4.0 0 [ 2] 253 (0x0fd) ble STMT00298 ( 0x0FB[E-] ... ??? ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 impImportBlockPending for BB24 impImportBlockPending for BB48 Importing BB24 (PC=258) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 258 (0x102) ldloc.1 [ 1] 259 (0x103) ldc.i4.0 0 [ 2] 260 (0x104) bge STMT00299 ( 0x102[E-] ... ??? ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 impImportBlockPending for BB25 impImportBlockPending for BB48 Importing BB25 (PC=265) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 265 (0x109) ldloc.s 6 [ 1] 267 (0x10b) ldc.i4.0 0 [ 2] 268 (0x10c) blt.s STMT00300 ( 0x109[E-] ... ??? ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 impImportBlockPending for BB26 impImportBlockPending for BB29 Importing BB29 (PC=289) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 289 (0x121) ldloc.0 [ 1] 290 (0x122) stloc.s 6 STMT00301 ( 0x121[E-] ... ??? ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 [ 0] 292 (0x124) ldc.i4.1 1 [ 1] 293 (0x125) stloc.s 7 STMT00302 ( 0x124[E-] ... ??? ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 [ 0] 295 (0x127) br impImportBlockPending for BB48 Importing BB26 (PC=270) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 270 (0x10e) ldloc.s 6 [ 1] 272 (0x110) ldloc.0 [ 2] 273 (0x111) bne.un.s STMT00303 ( 0x10E[E-] ... ??? ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 impImportBlockPending for BB27 impImportBlockPending for BB28 Importing BB28 (PC=286) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 286 (0x11e) ldc.i4.1 1 [ 1] 287 (0x11f) stloc.s 8 STMT00304 ( 0x11E[E-] ... ??? ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 impImportBlockPending for BB29 Importing BB27 (PC=275) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 275 (0x113) ldloc.s 7 [ 1] 277 (0x115) ldc.i4.1 1 [ 2] 278 (0x116) add [ 1] 279 (0x117) stloc.s 7 STMT00305 ( 0x113[E-] ... ??? ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 [ 0] 281 (0x119) br impImportBlockPending for BB48 Importing BB30 (PC=300) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 300 (0x12c) ldloc.s 9 [ 1] 302 (0x12e) ldc.i4.2 2 [ 2] 303 (0x12f) add [ 1] 304 (0x130) stloc.s 9 STMT00306 ( 0x12C[E-] ... ??? ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 [ 0] 306 (0x132) br impImportBlockPending for BB48 Importing BB17 (PC=207) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 207 (0x0cf) ldloc.0 [ 1] 208 (0x0d0) ldc.i4.1 1 [ 2] 209 (0x0d1) add [ 1] 210 (0x0d2) stloc.0 STMT00307 ( 0x0CF[E-] ... ??? ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 [ 0] 211 (0x0d3) br impImportBlockPending for BB48 Importing BB32 (PC=322) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 322 (0x142) ldloc.s 12 [ 1] 324 (0x144) ldarga.s 2 [ 2] 326 (0x146) call 0A000007 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00308 ( 0x142[E-] ... ??? ) [001438] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001437] ----------- this \--* ADDR byref [001436] -------N--- \--* LCL_VAR struct V02 arg2 [ 2] 331 (0x14b) bge STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001439] --C-------- \--* RET_EXPR int (for [001438]) impImportBlockPending for BB33 impImportBlockPending for BB48 Importing BB33 (PC=336) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 336 (0x150) ldloc.s 18 [ 1] 338 (0x152) ldloc.s 12 [ 2] 340 (0x154) conv.i [ 2] 341 (0x155) ldc.i4.2 2 [ 3] 342 (0x156) mul [ 2] 343 (0x157) add [ 1] 344 (0x158) ldind.u2 [ 1] 345 (0x159) brfalse STMT00310 ( 0x150[E-] ... ??? ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 impImportBlockPending for BB34 impImportBlockPending for BB48 Importing BB34 (PC=350) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 350 (0x15e) ldloc.s 18 [ 1] 352 (0x160) ldloc.s 12 [ 2] 354 (0x162) dup [ 3] 355 (0x163) ldc.i4.1 1 [ 4] 356 (0x164) add [ 3] 357 (0x165) stloc.s 12 lvaGrabTemp returning 74 (V74 tmp34) called for impSpillLclRefs. STMT00312 ( 0x15E[E-] ... ??? ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 [ 2] 359 (0x167) conv.i [ 2] 360 (0x168) ldc.i4.2 2 [ 3] 361 (0x169) mul [ 2] 362 (0x16a) add [ 1] 363 (0x16b) ldind.u2 [ 1] 364 (0x16c) ldloc.s 14 [ 2] 366 (0x16e) bne.un.s STMT00313 ( ??? ... ??? ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 impImportBlockPending for BB35 impImportBlockPending for BB32 Importing BB35 (PC=368) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 0] 368 (0x170) br impImportBlockPending for BB48 Importing BB02 (PC=023) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 23 (0x017) ldarg.1 [ 2] 24 (0x018) ldfld 040004D3 [ 2] 29 (0x01d) brtrue.s STMT00314 ( ??? ... ??? ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 *************** In impGetSpillTmpBase(BB02) lvaGrabTemps(1) returning 75..75 (long lifetime temps) called for IL Stack Entries Spilling stack entries into temps STMT00315 ( ??? ... ??? ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct V75 tmp35 [000019] ----------- \--* LCL_VAR struct V41 tmp1 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 impImportBlockPending for BB03 impImportBlockPending for BB04 Importing BB04 (PC=034) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 34 (0x022) ldc.i4.1 1 [ 2] 35 (0x023) br.s Spilling stack entries into temps STMT00316 ( ??? ... ??? ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct V42 tmp2 [001481] ----------- \--* LCL_VAR struct V75 tmp35 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 impImportBlockPending for BB06 Importing BB03 (PC=031) of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' [ 1] 31 (0x01f) ldc.i4.0 0 [ 2] 32 (0x020) br.s Spilling stack entries into temps STMT00318 ( ??? ... ??? ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct V42 tmp2 [001480] ----------- \--* LCL_VAR struct V75 tmp35 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 impImportBlockPending for BB06 ** Note: root method IL was partially imported -- imported 2019 of 2048 bytes of method IL *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 1 [022..025)-> BB06 (always) i BB05 [0004] 1 1 [025..026) i BB06 [0005] 3 1 [026..02D) i BB07 [0006] 2 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 1 [0C1..0CA)-> BB31 ( cond ) i bwd BB16 [0015] 1 1 [0CA..0CF)-> BB48 (always) i bwd BB17 [0016] 1 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 1 [0E0..0E2) i bwd BB20 [0019] 2 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 1 [11E..121) i bwd BB29 [0028] 2 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 1 [12C..137)-> BB48 (always) i bwd BB31 [0030] 1 1 [137..142)-> BB48 (always) i bwd BB32 [0031] 3 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 1 [201..204) i bwd BB48 [0047] 27 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 1 [233..235) i bwd BB53 [0052] 2 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 1 [24A..24D) i bwd BB57 [0056] 3 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 1 [26E..26F) i bwd BB61 [0060] 2 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 1 [2A0..2A7) i BB66 [0065] 2 1 [2A7..2AE) i BB67 [0066] 3 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 1 [2B5..2B8) i BB70 [0069] 2 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 1 [2C0..2C3) i BB73 [0072] 2 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 1 [2DC..2E2) i BB78 [0077] 2 1 [2E2..2EE) i BB79 [0078] 2 1 [2EE..30D)-> BB97 ( cond ) i BB80 [0079] 1 1 [30D..31E)-> BB97 ( cond ) i idxlen BB81 [0080] 1 1 [31E..336)-> BB83 ( cond ) i idxlen BB82 [0081] 1 1 [336..33D) i idxlen BB83 [0082] 2 1 [33D..348)-> BB85 ( cond ) i BB84 [0083] 1 1 [348..34B)-> BB86 (always) i BB85 [0084] 1 1 [34B..34D) i BB86 [0085] 2 1 [34D..355)-> BB88 ( cond ) i BB87 [0086] 1 1 [355..359)-> BB89 (always) i BB88 [0087] 1 1 [359..35A) i BB89 [0088] 2 1 [35A..35E)-> BB96 (always) i BB90 [0089] 1 1 [35E..362)-> BB97 ( cond ) i bwd bwd-target BB91 [0090] 1 1 [362..373)-> BB93 ( cond ) i bwd BB92 [0091] 1 1 [373..39A) i bwd BB93 [0092] 2 1 [39A..3AE)-> BB95 ( cond ) i bwd BB94 [0093] 1 1 [3AE..3BB) i idxlen bwd BB95 [0094] 2 1 [3BB..3C2) i bwd BB96 [0095] 2 1 [3C2..3C8)-> BB90 ( cond ) i bwd bwd-src BB97 [0096] 4 1 [3C8..3D0)-> BB101 ( cond ) i BB98 [0097] 1 1 [3D0..3D4)-> BB101 ( cond ) i BB99 [0098] 1 1 [3D4..3DC)-> BB101 ( cond ) i BB100 [0099] 1 1 [3DC..3E8) i BB101 [0100] 4 1 [3E8..401)-> BB191 (always) i BB102 [0101] 1 1 [401..406)-> BB117 ( cond ) i bwd bwd-target BB103 [0102] 1 1 [406..40C)-> BB116 ( cond ) i bwd BB104 [0103] 1 1 [40C..412)-> BB116 ( cond ) i bwd BB105 [0104] 1 1 [412..418)-> BB116 ( cond ) i bwd BB106 [0105] 1 1 [418..41A)-> BB117 (always) i bwd BB107 [0106] 1 1 [41A..420)-> BB109 ( cond ) i bwd bwd-target BB108 [0107] 1 1 [420..424)-> BB110 (always) i bwd BB109 [0108] 1 1 [424..42C) i bwd BB110 [0109] 2 1 [42C..435)-> BB115 ( cond ) i bwd BB111 [0110] 1 1 [435..43A)-> BB115 ( cond ) i bwd BB112 [0111] 1 1 [43A..43F)-> BB115 ( cond ) i bwd BB113 [0112] 1 1 [43F..44F)-> BB115 ( cond ) i bwd BB114 [0113] 1 1 [44F..461) i bwd BB115 [0114] 5 1 [461..46D) i bwd BB116 [0115] 4 1 [46D..472)-> BB107 ( cond ) i bwd bwd-src BB117 [0116] 3 1 [472..478)-> BB122 ( cond ) i bwd BB118 [0117] 1 1 [478..49A)-> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch) i bwd BB119 [0118] 1 1 [49A..4B8)-> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch) i bwd BB120 [0119] 1 1 [4B8..4C1)-> BB161 ( cond ) i bwd BB121 [0120] 1 1 [4C1..4C6)-> BB190 (always) i bwd BB122 [0121] 1 1 [4C6..4CF)-> BB158 ( cond ) i bwd BB123 [0122] 1 1 [4CF..4D8)-> BB161 ( cond ) i bwd BB124 [0123] 1 1 [4D8..4E4)-> BB149 ( cond ) i bwd BB125 [0124] 1 1 [4E4..4E9)-> BB190 (always) i bwd BB126 [0125] 2 1 [4E9..4EE)-> BB131 ( cond ) i bwd BB127 [0126] 1 1 [4EE..4F9)-> BB129 ( cond ) i bwd BB128 [0127] 1 1 [4F9..4FC)-> BB130 (always) i bwd BB129 [0128] 1 1 [4FC..4FE) i bwd BB130 [0129] 2 1 [4FE..502)-> BB137 (always) i bwd BB131 [0130] 1 1 [502..507)-> BB135 ( cond ) i bwd BB132 [0131] 1 1 [507..50C)-> BB134 ( cond ) i bwd BB133 [0132] 1 1 [50C..50F)-> BB136 (always) i bwd BB134 [0133] 1 1 [50F..513)-> BB136 (always) i bwd BB135 [0134] 1 1 [513..51B) i bwd BB136 [0135] 3 1 [51B..51D) i bwd BB137 [0136] 2 1 [51D..521)-> BB143 ( cond ) i bwd BB138 [0137] 1 1 [521..52D)-> BB143 ( cond ) i bwd BB139 [0138] 1 1 [52D..532)-> BB143 ( cond ) i bwd BB140 [0139] 1 1 [532..537)-> BB143 ( cond ) i bwd BB141 [0140] 1 1 [537..547)-> BB143 ( cond ) i bwd BB142 [0141] 1 1 [547..559) i bwd BB143 [0142] 6 1 [559..564)-> BB191 (always) i bwd BB144 [0143] 1 1 [564..571)-> BB191 ( cond ) i bwd BB145 [0144] 1 1 [571..575)-> BB148 ( cond ) i bwd BB146 [0145] 1 1 [575..57C)-> BB191 ( cond ) i bwd BB147 [0146] 1 1 [57C..584)-> BB191 ( cond ) i bwd BB148 [0147] 2 1 [584..598)-> BB191 (always) i bwd BB149 [0148] 1 1 [598..5A9)-> BB191 (always) i bwd BB150 [0149] 1 1 [5A9..5BA)-> BB191 (always) i bwd BB151 [0150] 1 1 [5BA..5CE) i bwd bwd-target BB152 [0151] 3 1 [5CE..5D9)-> BB155 ( cond ) i bwd BB153 [0152] 1 1 [5D9..5E4)-> BB155 ( cond ) i bwd BB154 [0153] 1 1 [5E4..5F1)-> BB151 ( cond ) i bwd bwd-src BB155 [0154] 3 1 [5F1..5FF)-> BB191 ( cond ) i bwd BB156 [0155] 1 1 [5FF..60D)-> BB191 ( cond ) i bwd BB157 [0156] 1 1 [60D..618)-> BB191 (always) i bwd BB158 [0157] 1 1 [618..626)-> BB191 ( cond ) i bwd BB159 [0158] 1 1 [626..634)-> BB191 ( cond ) i bwd BB160 [0159] 1 1 [634..64D)-> BB191 (always) i bwd BB161 [0160] 2 1 [64D..65A)-> BB182 ( cond ) i bwd BB162 [0161] 1 1 [65A..665)-> BB165 ( cond ) i bwd BB163 [0162] 1 1 [665..672)-> BB165 ( cond ) i bwd BB164 [0163] 1 1 [672..67A)-> BB174 (always) i bwd BB165 [0164] 2 1 [67A..687)-> BB169 ( cond ) i bwd BB166 [0165] 1 1 [687..694)-> BB169 ( cond ) i bwd BB167 [0166] 1 1 [694..6A3)-> BB169 ( cond ) i bwd BB168 [0167] 1 1 [6A3..6A8)-> BB174 (always) i bwd BB169 [0168] 3 1 [6A8..6B5)-> BB172 ( cond ) i bwd BB170 [0169] 1 1 [6B5..6C2)-> BB172 ( cond ) i bwd BB171 [0170] 1 1 [6C2..6D1)-> BB174 ( cond ) i bwd BB172 [0171] 3 1 [6D1..6DE)-> BB191 (always) i bwd BB173 [0172] 1 1 [6DE..6E4) i bwd bwd-target BB174 [0173] 4 1 [6E4..6F4)-> BB176 ( cond ) i bwd BB175 [0174] 1 1 [6F4..701)-> BB173 ( cond ) i bwd bwd-src BB176 [0175] 2 1 [701..707)-> BB178 ( cond ) i bwd BB177 [0176] 1 1 [707..70B) i bwd BB178 [0177] 2 1 [70B..710)-> BB180 ( cond ) i bwd BB179 [0178] 1 1 [710..71A)-> BB181 (always) i bwd BB180 [0179] 1 1 [71A..71B) i bwd BB181 [0180] 2 1 [71B..731)-> BB191 (always) i bwd BB182 [0181] 1 1 [731..744)-> BB191 ( cond ) i bwd BB183 [0182] 1 1 [744..751)-> BB185 ( cond ) i bwd BB184 [0183] 1 1 [751..75E)-> BB187 ( cond ) i bwd BB185 [0184] 2 1 [75E..774)-> BB187 (always) i bwd BB186 [0185] 1 1 [774..788) i bwd bwd-target BB187 [0186] 3 1 [788..793)-> BB191 ( cond ) i bwd BB188 [0187] 1 1 [793..7A0)-> BB186 ( cond ) i bwd bwd-src BB189 [0188] 1 1 [7A0..7A2)-> BB191 (always) i bwd BB190 [0189] 6 1 [7A2..7AA) i bwd BB191 [0190] 21 1 [7AA..7B5)-> BB194 ( cond ) i bwd BB192 [0191] 1 1 [7B5..7C8)-> BB194 ( cond ) i bwd BB193 [0192] 1 1 [7C8..7D1)-> BB102 ( cond ) i bwd bwd-src BB194 [0193] 3 1 [7D1..7DD)-> BB199 ( cond ) i BB195 [0194] 1 1 [7DD..7E1)-> BB199 ( cond ) i BB196 [0195] 1 1 [7E1..7E9)-> BB199 ( cond ) i BB197 [0196] 1 1 [7E9..7F2)-> BB199 ( cond ) i BB198 [0197] 1 1 [7F2..7FF) i BB199 [0198] 5 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00002 ( 0x009[E-] ... 0x00F ) [000006] I-C-G------ * CALL r2r_ind long System.Number+NumberBuffer:GetDigitsPointer():ulong:this (exactContextHnd=0x40000000004246E9) [000005] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [000007] --C-------- \--* RET_EXPR long (for [000006]) ***** BB01 STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct V41 tmp1 [000010] ----------- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct V75 tmp35 [000019] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct V42 tmp2 [001480] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct V42 tmp2 [001481] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct V42 tmp2 [000020] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] n---------- arg0 +--* OBJ struct [000031] ----------- | \--* ADDR byref [000028] -------N--- | \--* LCL_VAR struct V42 tmp2 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 ------------ BB07 [02D..05B) -> BB48 (always), preds={} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00018 ( 0x049[E-] ... 0x04F ) [000063] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref (exactContextHnd=0x4000000000428710) [000065] n---------- arg0 \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [000066] --C-------- \--* RET_EXPR byref (for [000063]) ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 ------------ BB08 [05B..061) -> BB13 (cond), preds={} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB31 (cond), preds={} succs={BB16,BB31} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* EQ int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB16 [0CA..0CF) -> BB48 (always), preds={} succs={BB48} ------------ BB17 [0CF..0D8) -> BB48 (always), preds={} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 ------------ BB31 [137..142) -> BB48 (always), preds={} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 ------------ BB32 [142..150) -> BB48 (cond), preds={} succs={BB33,BB48} ***** BB32 STMT00308 ( 0x142[E-] ... 0x14B ) [001438] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001437] ----------- this \--* ADDR byref [001436] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001439] --C-------- \--* RET_EXPR int (for [001438]) ------------ BB33 [150..15E) -> BB48 (cond), preds={} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={} succs={BB37,BB48} ***** BB36 STMT00268 ( 0x175[E-] ... 0x17E ) [001237] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001236] ----------- this \--* ADDR byref [001235] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001238] --C-------- \--* RET_EXPR int (for [001237]) ------------ BB37 [183..18E) -> BB48 (cond), preds={} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={} succs={BB40,BB41} ***** BB39 STMT00273 ( 0x196[E-] ... 0x19F ) [001264] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001263] ----------- this \--* ADDR byref [001262] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001265] --C-------- \--* RET_EXPR int (for [001264]) ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={} succs={BB42,BB48} ***** BB41 STMT00275 ( 0x1AE[E-] ... 0x1B9 ) [001273] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001272] ----------- this \--* ADDR byref [001271] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001274] --C-------- \--* RET_EXPR int (for [001273]) ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00281 ( ??? ... 0x1F2 ) [001312] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001311] ----------- this \--* ADDR byref [001310] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001313] --C-------- \--* RET_EXPR int (for [001312]) ------------ BB46 [1F4..201) -> BB45 (cond), preds={} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={} succs={BB49,BB51} ***** BB48 STMT00021 ( 0x204[E-] ... 0x20D ) [000076] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000075] ----------- this \--* ADDR byref [000074] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [000077] --C-------- \--* RET_EXPR int (for [000076]) ------------ BB49 [20F..222) -> BB51 (cond), preds={} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={} succs={BB62,BB67} ***** BB61 STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] n---------- arg0 +--* OBJ struct [001160] ----------- | \--* ADDR byref [001157] -------N--- | \--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 ------------ BB78 [2E2..2EE), preds={} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB79 [2EE..30D) -> BB97 (cond), preds={} succs={BB80,BB97} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct V48 tmp8 [000164] ----------- \--* CNS_INT int 0 ***** BB79 STMT00042 ( ??? ... ??? ) [000168] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(ulong,int):this (exactContextHnd=0x40000000004219E1) [000167] ----------- this +--* ADDR byref [000166] -------N--- | \--* LCL_VAR struct V48 tmp8 [000161] ----------- arg1 +--* ADDR long [000160] -------N--- | \--* LCL_VAR blk V47 tmp7 [000162] ----------- arg2 \--* CNS_INT int 4 ***** BB79 STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct V25 loc21 [000169] ----------- \--* LCL_VAR struct V48 tmp8 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct V19 loc15 [000172] ----------- \--* LCL_VAR struct V25 loc21 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 ------------ BB80 [30D..31E) -> BB97 (cond), preds={} succs={BB81,BB97} ***** BB80 STMT00202 ( 0x30D[E-] ... 0x319 ) [000942] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000941] ----------- this \--* LCL_VAR ref V03 arg3 ***** BB80 STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [000943] --C-------- | \--* RET_EXPR ref (for [000942]) [000945] ----------- \--* CNS_INT int 0 ------------ BB81 [31E..336) -> BB83 (cond), preds={} succs={BB82,BB83} ***** BB81 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 ***** BB81 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 ***** BB81 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 ***** BB81 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB81 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 ------------ BB82 [336..33D), preds={} succs={BB83} ***** BB82 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 ------------ BB83 [33D..348) -> BB85 (cond), preds={} succs={BB84,BB85} ***** BB83 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB83 STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB83 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 ------------ BB84 [348..34B) -> BB86 (always), preds={} succs={BB86} ***** BB84 STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 ------------ BB85 [34B..34D), preds={} succs={BB86} ***** BB85 STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB85 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB86 [34D..355) -> BB88 (cond), preds={} succs={BB87,BB88} ***** BB86 STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB86 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB87 [355..359) -> BB89 (always), preds={} succs={BB89} ***** BB87 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB88 [359..35A), preds={} succs={BB89} ***** BB88 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB89 [35A..35E) -> BB96 (always), preds={} succs={BB96} ***** BB89 STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 ------------ BB90 [35E..362) -> BB97 (cond), preds={} succs={BB91,BB97} ***** BB90 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 ------------ BB91 [362..373) -> BB93 (cond), preds={} succs={BB92,BB93} ***** BB91 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 ***** BB91 STMT00221 ( 0x368[E-] ... 0x371 ) [001018] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001017] ----------- this \--* ADDR byref [001016] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB91 STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001019] --C-------- \--* RET_EXPR int (for [001018]) ------------ BB92 [373..39A), preds={} succs={BB93} ***** BB92 STMT00228 ( 0x373[E-] ... 0x381 ) [001063] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001062] ----------- this \--* ADDR byref [001061] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB92 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001064] --C-------- +--* RET_EXPR int (for [001063]) [001065] ----------- \--* CNS_INT int 2 ***** BB92 STMT00230 ( 0x383[E-] ... 0x398 ) [001074] I-C-G------ * CALL r2r_ind struct System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] (exactContextHnd=0x40000000004219E1) [001073] ----------- arg0 \--* LCL_VAR ref V33 loc29 ***** BB92 STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct V68 tmp28 [001075] --C-------- \--* RET_EXPR struct(for [001074]) ***** BB92 STMT00232 ( ??? ... ??? ) [001076] I-C-G------ * CALL r2r_ind void System.Span`1[int]:CopyTo(System.Span`1[int]):this (exactContextHnd=0x40000000004219E1) [001072] ----------- this +--* ADDR byref [001071] -------N--- | \--* LCL_VAR struct V19 loc15 [001081] n---------- arg1 \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 ***** BB92 STMT00233 ( 0x391[E-] ... ??? ) [001083] I-C-G------ * CALL r2r_ind struct System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] (exactContextHnd=0x40000000004219E1) [001082] ----------- arg0 \--* LCL_VAR ref V33 loc29 ***** BB92 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct V19 loc15 [001084] --C-------- \--* RET_EXPR struct(for [001083]) ------------ BB93 [39A..3AE) -> BB95 (cond), preds={} succs={BB94,BB95} ***** BB93 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* FIELD int :_length [001023] ----------- | | \--* ADDR byref [001022] -------N--- | | \--* LCL_VAR struct V19 loc15 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* FIELD byref :_reference [001027] ----------- | | \--* ADDR byref [001026] -------N--- | | \--* LCL_VAR struct V19 loc15 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB93 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 ------------ BB94 [3AE..3BB), preds={} succs={BB95} ***** BB94 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 ***** BB94 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 ------------ BB95 [3BB..3C2), preds={} succs={BB96} ***** BB95 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 ------------ BB96 [3C2..3C8) -> BB90 (cond), preds={} succs={BB97,BB90} ***** BB96 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB97 [3C8..3D0) -> BB101 (cond), preds={} succs={BB98,BB101} ***** BB97 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 ------------ BB98 [3D0..3D4) -> BB101 (cond), preds={} succs={BB99,BB101} ***** BB98 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 ------------ BB99 [3D4..3DC) -> BB101 (cond), preds={} succs={BB100,BB101} ***** BB99 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 ------------ BB100 [3DC..3E8), preds={} succs={BB101} ***** BB100 STMT00200 ( 0x3DC[E-] ... 0x3E3 ) [000938] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this (exactContextHnd=0x4000000000424641) [000937] ----------- this \--* LCL_VAR ref V03 arg3 ***** BB100 STMT00201 ( 0x3DC[E-] ... ??? ) [000940] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000936] ----------- this +--* LCL_VAR byref V00 arg0 [000939] --C-------- arg1 \--* RET_EXPR ref (for [000938]) ------------ BB101 [3E8..401) -> BB191 (always), preds={} succs={BB191} ***** BB101 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 ***** BB101 STMT00049 ( 0x3EB[E-] ... 0x3F1 ) [000191] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref (exactContextHnd=0x4000000000428710) [000193] n---------- arg0 \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB101 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [000194] --C-------- \--* RET_EXPR byref (for [000191]) ***** BB101 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 ***** BB101 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB102 [401..406) -> BB117 (cond), preds={} succs={BB103,BB117} ***** BB102 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 ------------ BB103 [406..40C) -> BB116 (cond), preds={} succs={BB104,BB116} ***** BB103 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 ------------ BB104 [40C..412) -> BB116 (cond), preds={} succs={BB105,BB116} ***** BB104 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 ------------ BB105 [412..418) -> BB116 (cond), preds={} succs={BB106,BB116} ***** BB105 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 ------------ BB106 [418..41A) -> BB117 (always), preds={} succs={BB117} ------------ BB107 [41A..420) -> BB109 (cond), preds={} succs={BB108,BB109} ***** BB107 STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB107 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 ------------ BB108 [420..424) -> BB110 (always), preds={} succs={BB110} ***** BB108 STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB108 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 ------------ BB109 [424..42C), preds={} succs={BB110} ***** BB109 STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB109 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 ***** BB109 STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB109 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB110 [42C..435) -> BB115 (cond), preds={} succs={BB111,BB115} ***** BB110 STMT00184 ( ??? ... 0x433 ) [000859] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000857] ----------- this +--* LCL_VAR byref V62 tmp22 [000858] ----------- arg1 \--* LCL_VAR int V63 tmp23 ***** BB110 STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 ------------ BB111 [435..43A) -> BB115 (cond), preds={} succs={BB112,BB115} ***** BB111 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 ------------ BB112 [43A..43F) -> BB115 (cond), preds={} succs={BB113,BB115} ***** BB112 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 ------------ BB113 [43F..44F) -> BB115 (cond), preds={} succs={BB114,BB115} ***** BB113 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* FIELD int :_length [000884] ----------- | | \--* ADDR byref [000883] -------N--- | | \--* LCL_VAR struct V19 loc15 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* FIELD byref :_reference [000888] ----------- | | \--* ADDR byref [000887] -------N--- | | \--* LCL_VAR struct V19 loc15 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 ------------ BB114 [44F..461), preds={} succs={BB115} ***** BB114 STMT00191 ( 0x44F[E-] ... 0x45F ) [000904] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000903] ----------- this \--* LCL_VAR ref V03 arg3 ***** BB114 STMT00192 ( 0x44F[E-] ... ??? ) [000906] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000902] ----------- this +--* LCL_VAR byref V00 arg0 [000905] --C-------- arg1 \--* RET_EXPR ref (for [000904]) ***** BB114 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 ------------ BB115 [461..46D), preds={} succs={BB116} ***** BB115 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 ***** BB115 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 ------------ BB116 [46D..472) -> BB107 (cond), preds={} succs={BB117,BB107} ***** BB116 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 ------------ BB117 [472..478) -> BB122 (cond), preds={} succs={BB118,BB122} ***** BB117 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 ------------ BB118 [478..49A) -> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch), preds={} succs={BB119,BB126,BB150,BB152,BB190} ***** BB118 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 ------------ BB119 [49A..4B8) -> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch), preds={} succs={BB120,BB126,BB144,BB190,BB191} ***** BB119 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 ------------ BB120 [4B8..4C1) -> BB161 (cond), preds={} succs={BB121,BB161} ***** BB120 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 ------------ BB121 [4C1..4C6) -> BB190 (always), preds={} succs={BB190} ------------ BB122 [4C6..4CF) -> BB158 (cond), preds={} succs={BB123,BB158} ***** BB122 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 ------------ BB123 [4CF..4D8) -> BB161 (cond), preds={} succs={BB124,BB161} ***** BB123 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 ------------ BB124 [4D8..4E4) -> BB149 (cond), preds={} succs={BB125,BB149} ***** BB124 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* EQ int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB125 [4E4..4E9) -> BB190 (always), preds={} succs={BB190} ------------ BB126 [4E9..4EE) -> BB131 (cond), preds={} succs={BB127,BB131} ***** BB126 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 ------------ BB127 [4EE..4F9) -> BB129 (cond), preds={} succs={BB128,BB129} ***** BB127 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 ***** BB127 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB128 [4F9..4FC) -> BB130 (always), preds={} succs={BB130} ***** BB128 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 ------------ BB129 [4FC..4FE), preds={} succs={BB130} ***** BB129 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 ------------ BB130 [4FE..502) -> BB137 (always), preds={} succs={BB137} ***** BB130 STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB131 [502..507) -> BB135 (cond), preds={} succs={BB132,BB135} ***** BB131 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 ------------ BB132 [507..50C) -> BB134 (cond), preds={} succs={BB133,BB134} ***** BB132 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB133 [50C..50F) -> BB136 (always), preds={} succs={BB136} ***** BB133 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 ------------ BB134 [50F..513) -> BB136 (always), preds={} succs={BB136} ***** BB134 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 ------------ BB135 [513..51B), preds={} succs={BB136} ***** BB135 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB135 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 ***** BB135 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB136 [51B..51D), preds={} succs={BB137} ***** BB136 STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB137 [51D..521) -> BB143 (cond), preds={} succs={BB138,BB143} ***** BB137 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 ------------ BB138 [521..52D) -> BB143 (cond), preds={} succs={BB139,BB143} ***** BB138 STMT00149 ( 0x521[E-] ... 0x52B ) [000676] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000674] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ***** BB138 STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 ------------ BB139 [52D..532) -> BB143 (cond), preds={} succs={BB140,BB143} ***** BB139 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 ------------ BB140 [532..537) -> BB143 (cond), preds={} succs={BB141,BB143} ***** BB140 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 ------------ BB141 [537..547) -> BB143 (cond), preds={} succs={BB142,BB143} ***** BB141 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* FIELD int :_length [000691] ----------- | | \--* ADDR byref [000690] -------N--- | | \--* LCL_VAR struct V19 loc15 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* FIELD byref :_reference [000695] ----------- | | \--* ADDR byref [000694] -------N--- | | \--* LCL_VAR struct V19 loc15 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 ------------ BB142 [547..559), preds={} succs={BB143} ***** BB142 STMT00154 ( 0x547[E-] ... 0x557 ) [000711] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000710] ----------- this \--* LCL_VAR ref V03 arg3 ***** BB142 STMT00155 ( 0x547[E-] ... ??? ) [000713] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000709] ----------- this +--* LCL_VAR byref V00 arg0 [000712] --C-------- arg1 \--* RET_EXPR ref (for [000711]) ***** BB142 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 ------------ BB143 [559..564) -> BB191 (always), preds={} succs={BB191} ***** BB143 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 ------------ BB144 [564..571) -> BB191 (cond), preds={} succs={BB145,BB191} ***** BB144 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 ------------ BB145 [571..575) -> BB148 (cond), preds={} succs={BB146,BB148} ***** BB145 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 ------------ BB146 [575..57C) -> BB191 (cond), preds={} succs={BB147,BB191} ***** BB146 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB147 [57C..584) -> BB191 (cond), preds={} succs={BB148,BB191} ***** BB147 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 ------------ BB148 [584..598) -> BB191 (always), preds={} succs={BB191} ***** BB148 STMT00134 ( 0x584[E-] ... 0x591 ) [000619] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000618] ----------- this \--* LCL_VAR ref V03 arg3 ***** BB148 STMT00135 ( 0x584[E-] ... ??? ) [000621] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000617] ----------- this +--* LCL_VAR byref V00 arg0 [000620] --C-------- arg1 \--* RET_EXPR ref (for [000619]) ***** BB148 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 ------------ BB149 [598..5A9) -> BB191 (always), preds={} succs={BB191} ***** BB149 STMT00126 ( 0x598[E-] ... 0x5A4 ) [000587] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this (exactContextHnd=0x4000000000424641) [000586] ----------- this \--* LCL_VAR ref V03 arg3 ***** BB149 STMT00127 ( 0x598[E-] ... ??? ) [000589] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000585] ----------- this +--* LCL_VAR byref V00 arg0 [000588] --C-------- arg1 \--* RET_EXPR ref (for [000587]) ------------ BB150 [5A9..5BA) -> BB191 (always), preds={} succs={BB191} ***** BB150 STMT00139 ( 0x5A9[E-] ... 0x5B5 ) [000636] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this (exactContextHnd=0x4000000000424641) [000635] ----------- this \--* LCL_VAR ref V03 arg3 ***** BB150 STMT00140 ( 0x5A9[E-] ... ??? ) [000638] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000634] ----------- this +--* LCL_VAR byref V00 arg0 [000637] --C-------- arg1 \--* RET_EXPR ref (for [000636]) ------------ BB151 [5BA..5CE), preds={} succs={BB152} ***** BB151 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB151 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 ***** BB151 STMT00175 ( ??? ... 0x5C9 ) [000820] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000803] ----------- this +--* LCL_VAR byref V00 arg0 [000819] ---XG------ arg1 \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 ------------ BB152 [5CE..5D9) -> BB155 (cond), preds={} succs={BB153,BB155} ***** BB152 STMT00165 ( 0x5CE[E-] ... 0x5D7 ) [000754] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000753] ----------- this \--* ADDR byref [000752] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB152 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [000755] --C-------- \--* RET_EXPR int (for [000754]) ------------ BB153 [5D9..5E4) -> BB155 (cond), preds={} succs={BB154,BB155} ***** BB153 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 ------------ BB154 [5E4..5F1) -> BB151 (cond), preds={} succs={BB155,BB151} ***** BB154 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB155 [5F1..5FF) -> BB191 (cond), preds={} succs={BB156,BB191} ***** BB155 STMT00167 ( 0x5F1[E-] ... 0x5FA ) [000761] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000760] ----------- this \--* ADDR byref [000759] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB155 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [000762] --C-------- \--* RET_EXPR int (for [000761]) ------------ BB156 [5FF..60D) -> BB191 (cond), preds={} succs={BB157,BB191} ***** BB156 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 ------------ BB157 [60D..618) -> BB191 (always), preds={} succs={BB191} ***** BB157 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 ------------ BB158 [618..626) -> BB191 (cond), preds={} succs={BB159,BB191} ***** BB158 STMT00073 ( 0x618[E-] ... 0x621 ) [000286] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000285] ----------- this \--* ADDR byref [000284] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB158 STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [000287] --C-------- \--* RET_EXPR int (for [000286]) ------------ BB159 [626..634) -> BB191 (cond), preds={} succs={BB160,BB191} ***** BB159 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 ------------ BB160 [634..64D) -> BB191 (always), preds={} succs={BB191} ***** BB160 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB160 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 ***** BB160 STMT00078 ( ??? ... 0x648 ) [000318] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000301] ----------- this +--* LCL_VAR byref V00 arg0 [000317] ---XG------ arg1 \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 ------------ BB161 [64D..65A) -> BB182 (cond), preds={} succs={BB162,BB182} ***** BB161 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 ***** BB161 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 ***** BB161 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 ------------ BB162 [65A..665) -> BB165 (cond), preds={} succs={BB163,BB165} ***** BB162 STMT00097 ( 0x65A[E-] ... 0x663 ) [000422] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000421] ----------- this \--* ADDR byref [000420] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB162 STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [000423] --C-------- \--* RET_EXPR int (for [000422]) ------------ BB163 [665..672) -> BB165 (cond), preds={} succs={BB164,BB165} ***** BB163 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* NE int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 ------------ BB164 [672..67A) -> BB174 (always), preds={} succs={BB174} ***** BB164 STMT00124 ( 0x672[E-] ... 0x676 ) [000580] -A--------- * ASG int [000579] D------N--- +--* LCL_VAR int V38 loc34 [000578] ----------- \--* ADD int [000576] ----------- +--* LCL_VAR int V38 loc34 [000577] ----------- \--* CNS_INT int 1 ------------ BB165 [67A..687) -> BB169 (cond), preds={} succs={BB166,BB169} ***** BB165 STMT00099 ( 0x67A[E-] ... 0x685 ) [000431] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000430] ----------- this \--* ADDR byref [000429] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB165 STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [000432] --C-------- \--* RET_EXPR int (for [000431]) ------------ BB166 [687..694) -> BB169 (cond), preds={} succs={BB167,BB169} ***** BB166 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 ------------ BB167 [694..6A3) -> BB169 (cond), preds={} succs={BB168,BB169} ***** BB167 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 ------------ BB168 [6A3..6A8) -> BB174 (always), preds={} succs={BB174} ***** BB168 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 ------------ BB169 [6A8..6B5) -> BB172 (cond), preds={} succs={BB170,BB172} ***** BB169 STMT00101 ( 0x6A8[E-] ... 0x6B3 ) [000440] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000439] ----------- this \--* ADDR byref [000438] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB169 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [000441] --C-------- \--* RET_EXPR int (for [000440]) ------------ BB170 [6B5..6C2) -> BB172 (cond), preds={} succs={BB171,BB172} ***** BB170 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 ------------ BB171 [6C2..6D1) -> BB174 (cond), preds={} succs={BB172,BB174} ***** BB171 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 ------------ BB172 [6D1..6DE) -> BB191 (always), preds={} succs={BB191} ***** BB172 STMT00103 ( 0x6D1[E-] ... 0x6D9 ) [000446] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000444] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB173 [6DE..6E4), preds={} succs={BB174} ***** BB173 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 ------------ BB174 [6E4..6F4) -> BB176 (cond), preds={} succs={BB175,BB176} ***** BB174 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 ***** BB174 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB174 STMT00108 ( ??? ... 0x6F2 ) [000482] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000481] ----------- this \--* ADDR byref [000480] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB174 STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [000483] --C-------- \--* RET_EXPR int (for [000482]) ------------ BB175 [6F4..701) -> BB173 (cond), preds={} succs={BB176,BB173} ***** BB175 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 ------------ BB176 [701..707) -> BB178 (cond), preds={} succs={BB177,BB178} ***** BB176 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 ------------ BB177 [707..70B), preds={} succs={BB178} ***** BB177 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 ------------ BB178 [70B..710) -> BB180 (cond), preds={} succs={BB179,BB180} ***** BB178 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 ------------ BB179 [710..71A) -> BB181 (always), preds={} succs={BB181} ***** BB179 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB180 [71A..71B), preds={} succs={BB181} ***** BB180 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 ------------ BB181 [71B..731) -> BB191 (always), preds={} succs={BB191} ***** BB181 STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 ***** BB181 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] I-C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) (exactContextHnd=0x4000000000424651) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 ***** BB181 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 ------------ BB182 [731..744) -> BB191 (cond), preds={} succs={BB183,BB191} ***** BB182 STMT00083 ( 0x731[E-] ... 0x742 ) [000335] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000333] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ***** BB182 STMT00084 ( 0x739[E-] ... ??? ) [000339] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000338] ----------- this \--* ADDR byref [000337] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB182 STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [000340] --C-------- \--* RET_EXPR int (for [000339]) ------------ BB183 [744..751) -> BB185 (cond), preds={} succs={BB184,BB185} ***** BB183 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 ------------ BB184 [751..75E) -> BB187 (cond), preds={} succs={BB185,BB187} ***** BB184 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 ------------ BB185 [75E..774) -> BB187 (always), preds={} succs={BB187} ***** BB185 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB185 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 ***** BB185 STMT00089 ( ??? ... 0x772 ) [000371] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000354] ----------- this +--* LCL_VAR byref V00 arg0 [000370] ---XG------ arg1 \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 ------------ BB186 [774..788), preds={} succs={BB187} ***** BB186 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB186 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 ***** BB186 STMT00095 ( ??? ... 0x783 ) [000407] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000390] ----------- this +--* LCL_VAR byref V00 arg0 [000406] ---XG------ arg1 \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 ------------ BB187 [788..793) -> BB191 (cond), preds={} succs={BB188,BB191} ***** BB187 STMT00090 ( 0x788[E-] ... 0x791 ) [000375] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000374] ----------- this \--* ADDR byref [000373] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB187 STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [000376] --C-------- \--* RET_EXPR int (for [000375]) ------------ BB188 [793..7A0) -> BB186 (cond), preds={} succs={BB189,BB186} ***** BB188 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 ------------ BB189 [7A0..7A2) -> BB191 (always), preds={} succs={BB191} ------------ BB190 [7A2..7AA), preds={} succs={BB191} ***** BB190 STMT00128 ( 0x7A2[E-] ... 0x7A5 ) [000592] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000590] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB191 [7AA..7B5) -> BB194 (cond), preds={} succs={BB192,BB194} ***** BB191 STMT00053 ( 0x7AA[E-] ... 0x7B3 ) [000207] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000206] ----------- this \--* ADDR byref [000205] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB191 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [000208] --C-------- \--* RET_EXPR int (for [000207]) ------------ BB192 [7B5..7C8) -> BB194 (cond), preds={} succs={BB193,BB194} ***** BB192 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB192 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 ***** BB192 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 ***** BB192 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB192 STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 ------------ BB193 [7C8..7D1) -> BB102 (cond), preds={} succs={BB194,BB102} ***** BB193 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 ------------ BB194 [7D1..7DD) -> BB199 (cond), preds={} succs={BB195,BB199} ***** BB194 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 ***** BB194 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 ------------ BB195 [7DD..7E1) -> BB199 (cond), preds={} succs={BB196,BB199} ***** BB195 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 ------------ BB196 [7E1..7E9) -> BB199 (cond), preds={} succs={BB197,BB199} ***** BB196 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 ------------ BB197 [7E9..7F2) -> BB199 (cond), preds={} succs={BB198,BB199} ***** BB197 STMT00060 ( 0x7E9[E-] ... 0x7F0 ) [000231] I-C-G------ * CALL r2r_ind int System.Text.ValueStringBuilder:get_Length():int:this (exactContextHnd=0x40000000004246F9) [000230] ----------- this \--* LCL_VAR byref V00 arg0 ***** BB197 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [000232] --C-------- +--* RET_EXPR int (for [000231]) [000233] ----------- \--* CNS_INT int 0 ------------ BB198 [7F2..7FF), preds={} succs={BB199} ***** BB198 STMT00062 ( 0x7F2[E-] ... 0x7FA ) [000239] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this (exactContextHnd=0x4000000000424641) [000238] ----------- this \--* LCL_VAR ref V03 arg3 ***** BB198 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [000240] --C-------- arg2 \--* RET_EXPR ref (for [000239]) ------------ BB199 [7FF..800) (return), preds={} succs={} ***** BB199 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import [no changes] *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 200, bitset array size: 4 (long) *************** Finishing PHASE Morph - Init [no changes] *************** Starting PHASE Morph - Inlining *************** In fgDebugCheckBBlist INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' Expanding INLINE_CANDIDATE in statement STMT00002 in BB01: STMT00002 ( 0x009[E-] ... 0x00F ) [000006] I-C-G------ * CALL r2r_ind long System.Number+NumberBuffer:GetDigitsPointer():ulong:this (exactContextHnd=0x40000000004246E9) [000005] ----------- this \--* LCL_VAR byref V01 arg1 thisArg: is a local var [000005] ----------- * LCL_VAR byref V01 arg1 INLINER: inlineInfo.tokenLookupContextHandle for System.Number+NumberBuffer:GetDigitsPointer():ulong:this set to 0x40000000004246E9: Invoking compiler for the inlinee method System.Number+NumberBuffer:GetDigitsPointer():ulong:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7c d6 04 00 04 ldflda 0x40004D6 IL_0006 16 ldc.i4.0 IL_0007 28 be 00 00 0a call 0xA0000BE IL_000c 28 5a 02 00 2b call 0x2B00025A IL_0011 2a ret INLINER impTokenLookupContextHandle for System.Number+NumberBuffer:GetDigitsPointer():ulong:this is 0x40000000004246E9. *************** In compInitDebuggingInfo() for System.Number+NumberBuffer:GetDigitsPointer():ulong:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Number+NumberBuffer:GetDigitsPointer():ulong:this weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 79 : state 40 [ call ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate is mostly loads and stores. Multiplier increased to 4. Inline candidate callsite is boring. Multiplier increased to 5.3. calleeNativeSizeEstimate=219 callsiteNativeSizeEstimate=85 benefit multiplier=5.3 threshold=450 Native estimate for function size is within threshold for inlining 21.9 <= 45 (multiplier = 5.3) Jump targets: none New Basic Block BB200 [0199] created. BB200 [000..012) Basic block list for 'System.Number+NumberBuffer:GetDigitsPointer():ulong:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB200 [0199] 1 1 [000..012) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000006] Starting PHASE Pre-import *************** Inline @[000006] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB200 [0199] 1 1 [000..012) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB200 [000..012) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000006] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000006] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB200 [0199] 1 1 [000..012) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB200 [000..012) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000006] Starting PHASE Importation *************** In impImport() for System.Number+NumberBuffer:GetDigitsPointer():ulong:this impImportBlockPending for BB200 Importing BB200 (PC=000) of 'System.Number+NumberBuffer:GetDigitsPointer():ulong:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldflda 040004D6 [ 1] 6 (0x006) ldc.i4.0 0 [ 2] 7 (0x007) call 0A0000BE In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=1 with ptr-to-span [001496] ---XG------ * FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 and index [001497] ----------- * CNS_INT int 0 lvaGrabTemp returning 76 (V76 tmp36) called for Span.get_Item ptrToSpan. STMT00320 ( 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 [ 1] 12 (0x00c) call 2B00025A In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.Unsafe.AsPointer: Recognized [ 1] 17 (0x011) ret Inlinee Return expression (before normalization) => [001508] ---XGO----- * CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 Inlinee Return expression (after normalization) => [001508] ---XGO----- * CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 *************** Inline @[000006] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB200 [0199] 1 1 [000..012) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB200 [000..012) (return), preds={} succs={} ***** BB200 STMT00320 ( 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000006] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000006] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000006] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000006] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000006] Starting PHASE Post-import *************** Inline @[000006] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000006] ----------- Arguments setup: Inlinee method body: STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Number+NumberBuffer:GetDigitsPointer():ulong:this (18 IL bytes) (depth 1) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Number+NumberBuffer:GetDigitsPointer():ulong:this' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Replacing the return expression placeholder [000007] with [001508] [000007] --C-------- * RET_EXPR long (for [000006]) -> [001508] Inserting the inline return expression [001508] ---XGO----- * CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' Expanding INLINE_CANDIDATE in statement STMT00018 in BB07: STMT00018 ( 0x049[E-] ... 0x04F ) [000063] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref (exactContextHnd=0x4000000000428710) [000065] n---------- arg0 \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 Argument #0: has caller local ref [000065] n---------- * OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref set to 0x4000000000428710: Invoking compiler for the inlinee method System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref : IL to import: IL_0000 0f 00 ldarga.s 0x0 IL_0002 7b 90 11 00 0a ldfld 0xA001190 IL_0007 2a ret INLINER impTokenLookupContextHandle for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref is 0x4000000000428710. *************** In compInitDebuggingInfo() for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref Jump targets: none New Basic Block BB201 [0200] created. BB201 [000..008) Basic block list for 'System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB201 [0200] 1 1 [000..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000063] Starting PHASE Pre-import *************** Inline @[000063] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB201 [0200] 1 1 [000..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB201 [000..008) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000063] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000063] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB201 [0200] 1 1 [000..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB201 [000..008) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000063] Starting PHASE Importation *************** In impImport() for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref impImportBlockPending for BB201 Importing BB201 (PC=000) of 'System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref' [ 0] 0 (0x000) ldarga.s 0 lvaGrabTemp returning 77 (V77 tmp37) called for Inlining Arg. [ 1] 2 (0x002) ldfld 0A001190 [ 1] 7 (0x007) ret Inlinee Return expression (before normalization) => [001512] ----------- * FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct V77 tmp37 Inlinee Return expression (after normalization) => [001512] ----------- * FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct V77 tmp37 ** Note: inlinee IL was partially imported -- imported 0 of 8 bytes of method IL *************** Inline @[000063] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB201 [0200] 1 1 [000..008) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB201 [000..008) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000063] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000063] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000063] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000063] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000063] Starting PHASE Post-import *************** Inline @[000063] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000063] ----------- Arguments setup: STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct V77 tmp37 [000065] n---------- \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref (8 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000066] with [001512] [000066] --C-------- * RET_EXPR byref (for [000063]) -> [001512] Inserting the inline return expression [001512] ----------- * FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct V77 tmp37 Expanding INLINE_CANDIDATE in statement STMT00308 in BB32: STMT00308 ( 0x142[E-] ... 0x14B ) [001438] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001437] ----------- this \--* ADDR byref [001436] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [001437] ----------- * ADDR byref [001436] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB202 [0201] created. BB202 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB202 [0201] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001438] Starting PHASE Pre-import *************** Inline @[001438] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB202 [0201] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB202 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001438] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001438] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB202 [0201] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB202 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001438] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB202 Importing BB202 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001518] ----------- * FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [001518] ----------- * FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001438] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB202 [0201] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB202 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001438] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001438] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001438] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001438] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001438] Starting PHASE Post-import *************** Inline @[001438] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001438] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001439] with [001518] [001439] --C-------- * RET_EXPR int (for [001438]) -> [001518] Inserting the inline return expression [001518] ----------- * FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00268 in BB36: STMT00268 ( 0x175[E-] ... 0x17E ) [001237] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001236] ----------- this \--* ADDR byref [001235] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [001236] ----------- * ADDR byref [001235] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB203 [0202] created. BB203 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB203 [0202] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001237] Starting PHASE Pre-import *************** Inline @[001237] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB203 [0202] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB203 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001237] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001237] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB203 [0202] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB203 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001237] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB203 Importing BB203 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001522] ----------- * FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [001522] ----------- * FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001237] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB203 [0202] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB203 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001237] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001237] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001237] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001237] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001237] Starting PHASE Post-import *************** Inline @[001237] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001237] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001238] with [001522] [001238] --C-------- * RET_EXPR int (for [001237]) -> [001522] Inserting the inline return expression [001522] ----------- * FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00273 in BB39: STMT00273 ( 0x196[E-] ... 0x19F ) [001264] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001263] ----------- this \--* ADDR byref [001262] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [001263] ----------- * ADDR byref [001262] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB204 [0203] created. BB204 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB204 [0203] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001264] Starting PHASE Pre-import *************** Inline @[001264] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB204 [0203] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB204 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001264] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001264] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB204 [0203] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB204 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001264] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB204 Importing BB204 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001526] ----------- * FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [001526] ----------- * FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001264] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB204 [0203] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB204 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001264] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001264] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001264] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001264] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001264] Starting PHASE Post-import *************** Inline @[001264] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001264] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001265] with [001526] [001265] --C-------- * RET_EXPR int (for [001264]) -> [001526] Inserting the inline return expression [001526] ----------- * FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00275 in BB41: STMT00275 ( 0x1AE[E-] ... 0x1B9 ) [001273] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001272] ----------- this \--* ADDR byref [001271] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [001272] ----------- * ADDR byref [001271] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB205 [0204] created. BB205 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB205 [0204] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001273] Starting PHASE Pre-import *************** Inline @[001273] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB205 [0204] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB205 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001273] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001273] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB205 [0204] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB205 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001273] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB205 Importing BB205 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001530] ----------- * FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [001530] ----------- * FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001273] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB205 [0204] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB205 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001273] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001273] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001273] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001273] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001273] Starting PHASE Post-import *************** Inline @[001273] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001273] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001274] with [001530] [001274] --C-------- * RET_EXPR int (for [001273]) -> [001530] Inserting the inline return expression [001530] ----------- * FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00281 in BB45: STMT00281 ( ??? ... 0x1F2 ) [001312] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [001311] ----------- this \--* ADDR byref [001310] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [001311] ----------- * ADDR byref [001310] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB206 [0205] created. BB206 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB206 [0205] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001312] Starting PHASE Pre-import *************** Inline @[001312] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB206 [0205] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB206 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001312] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001312] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB206 [0205] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB206 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001312] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB206 Importing BB206 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001534] ----------- * FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [001534] ----------- * FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001312] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB206 [0205] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB206 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001312] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001312] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001312] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001312] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001312] Starting PHASE Post-import *************** Inline @[001312] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001312] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001313] with [001534] [001313] --C-------- * RET_EXPR int (for [001312]) -> [001534] Inserting the inline return expression [001534] ----------- * FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00021 in BB48: STMT00021 ( 0x204[E-] ... 0x20D ) [000076] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000075] ----------- this \--* ADDR byref [000074] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000075] ----------- * ADDR byref [000074] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB207 [0206] created. BB207 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB207 [0206] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000076] Starting PHASE Pre-import *************** Inline @[000076] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB207 [0206] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB207 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000076] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000076] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB207 [0206] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB207 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000076] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB207 Importing BB207 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001538] ----------- * FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [001538] ----------- * FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000076] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB207 [0206] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB207 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000076] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000076] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000076] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000076] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000076] Starting PHASE Post-import *************** Inline @[000076] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000076] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000077] with [001538] [000077] --C-------- * RET_EXPR int (for [000076]) -> [001538] Inserting the inline return expression [001538] ----------- * FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' Expanding INLINE_CANDIDATE in statement STMT00042 in BB79: STMT00042 ( ??? ... ??? ) [000168] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(ulong,int):this (exactContextHnd=0x40000000004219E1) [000167] ----------- this +--* ADDR byref [000166] -------N--- | \--* LCL_VAR struct V48 tmp8 [000161] ----------- arg1 +--* ADDR long [000160] -------N--- | \--* LCL_VAR blk V47 tmp7 [000162] ----------- arg2 \--* CNS_INT int 4 thisArg: is a constant or invariant is byref to a struct local [000167] ----------- * ADDR byref [000166] -------N--- \--* LCL_VAR struct V48 tmp8 Argument #1: is a constant or invariant [000161] ----------- * ADDR long [000160] -------N--- \--* LCL_VAR blk V47 tmp7 Argument #2: is a constant or invariant [000162] ----------- * CNS_INT int 4 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:.ctor(ulong,int):this set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:.ctor(ulong,int):this : IL to import: IL_0000 28 62 02 00 2b call 0x2B000262 IL_0005 2c 0f brfalse.s 15 (IL_0016) IL_0007 d0 2b 00 00 1b ldtoken 0x1B00002B IL_000c 28 a1 08 00 06 call 0x60008A1 IL_0011 28 9f 1f 00 06 call 0x6001F9F IL_0016 04 ldarg.2 IL_0017 16 ldc.i4.0 IL_0018 2f 05 bge.s 5 (IL_001f) IL_001a 28 a1 1f 00 06 call 0x6001FA1 IL_001f 02 ldarg.0 IL_0020 03 ldarg.1 IL_0021 7d 38 06 00 0a stfld 0xA000638 IL_0026 02 ldarg.0 IL_0027 04 ldarg.2 IL_0028 7d 31 07 00 0a stfld 0xA000731 IL_002d 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:.ctor(ulong,int):this is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:.ctor(ulong,int):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:.ctor(ulong,int):this Jump targets: IL_0016 IL_001f New Basic Block BB208 [0207] created. BB208 [000..007) New Basic Block BB209 [0208] created. BB209 [007..016) New Basic Block BB210 [0209] created. BB210 [016..01A) New Basic Block BB211 [0210] created. BB211 [01A..01F) New Basic Block BB212 [0211] created. BB212 [01F..02E) Basic block list for 'System.Span`1[int]:.ctor(ulong,int):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB208 [0207] 1 1 [000..007)-> BB210 ( cond ) BB209 [0208] 1 1 [007..016) BB210 [0209] 2 1 [016..01A)-> BB212 ( cond ) BB211 [0210] 1 1 [01A..01F) BB212 [0211] 2 1 [01F..02E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000168] Starting PHASE Pre-import *************** Inline @[000168] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB208 [0207] 1 1 [000..007)-> BB210 ( cond ) BB209 [0208] 1 1 [007..016) BB210 [0209] 2 1 [016..01A)-> BB212 ( cond ) BB211 [0210] 1 1 [01A..01F) BB212 [0211] 2 1 [01F..02E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB208 [000..007) -> BB210 (cond), preds={} succs={BB209,BB210} ------------ BB209 [007..016), preds={} succs={BB210} ------------ BB210 [016..01A) -> BB212 (cond), preds={} succs={BB211,BB212} ------------ BB211 [01A..01F), preds={} succs={BB212} ------------ BB212 [01F..02E) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000168] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000168] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB208 [0207] 1 1 [000..007)-> BB210 ( cond ) BB209 [0208] 1 1 [007..016) BB210 [0209] 2 1 [016..01A)-> BB212 ( cond ) BB211 [0210] 1 1 [01A..01F) BB212 [0211] 2 1 [01F..02E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB208 [000..007) -> BB210 (cond), preds={} succs={BB209,BB210} ------------ BB209 [007..016), preds={} succs={BB210} ------------ BB210 [016..01A) -> BB212 (cond), preds={} succs={BB211,BB212} ------------ BB211 [01A..01F), preds={} succs={BB212} ------------ BB212 [01F..02E) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000168] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:.ctor(ulong,int):this impImportBlockPending for BB208 Importing BB208 (PC=000) of 'System.Span`1[int]:.ctor(ulong,int):this' [ 0] 0 (0x000) call 2B000262 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.RuntimeHelpers.IsReferenceOrContainsReferences: Not recognized INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:.ctor(ulong,int):this' calling 'System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00322 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001540] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) [ 1] 5 (0x005) brfalse.s STMT00323 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] --C-------- * JTRUE void [001543] --C-------- \--* EQ int [001541] --C-------- +--* RET_EXPR int (for [001540]) [001542] ----------- \--* CNS_INT int 0 impImportBlockPending for BB209 impImportBlockPending for BB210 Importing BB210 (PC=022) of 'System.Span`1[int]:.ctor(ulong,int):this' [ 0] 22 (0x016) ldarg.2 [ 1] 23 (0x017) ldc.i4.0 0 [ 2] 24 (0x018) bge.s Folding operator with constant nodes into a constant: [001547] ----------- * GE int [001545] ----------- +--* CNS_INT int 4 [001546] ----------- \--* CNS_INT int 0 Bashed to int constant: [001547] ----------- * CNS_INT int 1 The conditional jump becomes an unconditional jump to BB212 impImportBlockPending for BB212 Importing BB212 (PC=031) of 'System.Span`1[int]:.ctor(ulong,int):this' [ 0] 31 (0x01f) ldarg.0 [ 1] 32 (0x020) ldarg.1 [ 2] 33 (0x021) stfld 0A000638 STMT00324 ( 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct V48 tmp8 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 [ 0] 38 (0x026) ldarg.0 [ 1] 39 (0x027) ldarg.2 [ 2] 40 (0x028) stfld 0A000731 STMT00325 ( 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct V48 tmp8 [001556] ----------- \--* CNS_INT int 4 [ 0] 45 (0x02d) ret Importing BB209 (PC=007) of 'System.Span`1[int]:.ctor(ulong,int):this' [ 0] 7 (0x007) ldtoken [ 1] 12 (0x00c) call 060008A1 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 Named Intrinsic System.Type.GetTypeFromHandle: Recognized [ 1] 17 (0x011) call 06001F9F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:.ctor(ulong,int):this' calling 'System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type)' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00326 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) (exactContextHnd=0x4000000000420331) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class impImportBlockPending for BB210 ** Note: inlinee IL was partially imported -- imported 37 of 46 bytes of method IL *************** Inline @[000168] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB208 [0207] 1 1 [000..007)-> BB210 ( cond ) i BB209 [0208] 1 1 [007..016) i BB210 [0209] 2 1 [016..01A)-> BB212 (always) i BB211 [0210] 1 1 [01A..01F) BB212 [0211] 2 1 [01F..02E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB208 [000..007) -> BB210 (cond), preds={} succs={BB209,BB210} ***** BB208 STMT00322 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001540] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) ***** BB208 STMT00323 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] --C-------- * JTRUE void [001543] --C-------- \--* EQ int [001541] --C-------- +--* RET_EXPR int (for [001540]) [001542] ----------- \--* CNS_INT int 0 ------------ BB209 [007..016), preds={} succs={BB210} ***** BB209 STMT00326 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) (exactContextHnd=0x4000000000420331) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class ------------ BB210 [016..01A) -> BB212 (always), preds={} succs={BB212} ------------ BB211 [01A..01F), preds={} succs={BB212} ------------ BB212 [01F..02E) (return), preds={} succs={} ***** BB212 STMT00324 ( 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct V48 tmp8 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 ***** BB212 STMT00325 ( 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct V48 tmp8 [001556] ----------- \--* CNS_INT int 4 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000168] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000168] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000168] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000168] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000168] Starting PHASE Post-import BB211 was not imported, marking as removed (0) Renumbering the basic blocks for fgPostImportationCleanup *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB208 [0207] 1 1 [000..007)-> BB210 ( cond ) i BB209 [0208] 1 1 [007..016) i BB210 [0209] 2 1 [016..01A)-> BB212 (always) i BB212 [0211] 2 1 [01F..02E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB208 to BB213 Renumber BB209 to BB214 Renumber BB210 to BB215 Renumber BB212 to BB216 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB213 [0207] 1 1 [000..007)-> BB215 ( cond ) i BB214 [0208] 1 1 [007..016) i BB215 [0209] 2 1 [016..01A)-> BB216 (always) i BB216 [0211] 2 1 [01F..02E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 1, # of blocks (including unused BB00): 6, bitset array size: 1 (short) *************** Inline @[000168] Finishing PHASE Post-import Trees after Post-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB213 [0207] 1 1 [000..007)-> BB215 ( cond ) i BB214 [0208] 1 1 [007..016) i BB215 [0209] 2 1 [016..01A)-> BB216 (always) i BB216 [0211] 2 1 [01F..02E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB213 [000..007) -> BB215 (cond), preds={} succs={BB214,BB215} ***** BB213 STMT00322 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001540] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) ***** BB213 STMT00323 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] --C-------- * JTRUE void [001543] --C-------- \--* EQ int [001541] --C-------- +--* RET_EXPR int (for [001540]) [001542] ----------- \--* CNS_INT int 0 ------------ BB214 [007..016), preds={} succs={BB215} ***** BB214 STMT00326 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) (exactContextHnd=0x4000000000420331) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class ------------ BB215 [016..01A) -> BB216 (always), preds={} succs={BB216} ------------ BB216 [01F..02E) (return), preds={} succs={} ***** BB216 STMT00324 ( 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct V48 tmp8 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 ***** BB216 STMT00325 ( 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct V48 tmp8 [001556] ----------- \--* CNS_INT int 4 ------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000168] ----------- Arguments setup: Inlinee method body:New Basic Block BB217 [0212] created. Convert bbJumpKind of BB216 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB213 [0207] 1 1 [000..000)-> BB215 ( cond ) i internal BB214 [0208] 1 1 [000..000) i internal BB215 [0209] 2 1 [000..000)-> BB216 (always) i internal BB216 [0211] 2 1 [000..000) i internal ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB213 [000..000) -> BB215 (cond), preds={} succs={BB214,BB215} ***** BB213 STMT00322 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001540] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) ***** BB213 STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] --C-------- * JTRUE void [001543] --C-------- \--* EQ int [001541] --C-------- +--* RET_EXPR int (for [001540]) [001542] ----------- \--* CNS_INT int 0 ------------ BB214 [000..000), preds={} succs={BB215} ***** BB214 STMT00326 ( INL09 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) (exactContextHnd=0x4000000000420331) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class ------------ BB215 [000..000) -> BB216 (always), preds={} succs={BB216} ------------ BB216 [000..000), preds={} succs={BB217} ***** BB216 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct V48 tmp8 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 ***** BB216 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct V48 tmp8 [001556] ----------- \--* CNS_INT int 4 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Span`1[int]:.ctor(ulong,int):this (46 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:.ctor(ulong,int):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00322 in BB213: STMT00322 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001540] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool set to 0x4000000000421A38: Invoking compiler for the inlinee method System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool : IL to import: IL_0000 16 ldc.i4.0 IL_0001 2a ret INLINER impTokenLookupContextHandle for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool is 0x4000000000421A38. *************** In compInitDebuggingInfo() for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool Jump targets: none New Basic Block BB218 [0213] created. BB218 [000..002) Basic block list for 'System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB218 [0213] 1 1 [000..002) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001540] Starting PHASE Pre-import *************** Inline @[001540] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB218 [0213] 1 1 [000..002) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB218 [000..002) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001540] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001540] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB218 [0213] 1 1 [000..002) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB218 [000..002) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001540] Starting PHASE Importation *************** In impImport() for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool impImportBlockPending for BB218 Importing BB218 (PC=000) of 'System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool' [ 0] 0 (0x000) ldc.i4.0 0 [ 1] 1 (0x001) ret Inlinee Return expression (before normalization) => [001565] ----------- * CNS_INT int 0 Inlinee Return expression (after normalization) => [001566] ----------- * CAST int <- bool <- int [001565] ----------- \--* CNS_INT int 0 ** Note: inlinee IL was partially imported -- imported 0 of 2 bytes of method IL *************** Inline @[001540] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB218 [0213] 1 1 [000..002) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB218 [000..002) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001540] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001540] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001540] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001540] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001540] Starting PHASE Post-import *************** Inline @[001540] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001540] ----------- Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (2 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Folding operator with constant nodes into a constant: [001566] ----------- * CAST int <- bool <- int [001565] ----------- \--* CNS_INT int 0 Bashed to int constant: [001566] ----------- * CNS_INT int 0 Replacing the return expression placeholder [001541] with [001566] [001541] --C-------- * RET_EXPR int (for [001540]) -> [001566] Inserting the inline return expression [001566] ----------- * CNS_INT int 0 Folding operator with constant nodes into a constant: [001543] --C-------- * EQ int [001566] ----------- +--* CNS_INT int 0 [001542] ----------- \--* CNS_INT int 0 Bashed to int constant: [001543] ----------- * CNS_INT int 1 ... found foldable jtrue at [001544] in BB213 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'n/a' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' Expanding INLINE_CANDIDATE in statement STMT00326 in BB214: STMT00326 ( INL09 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) (exactContextHnd=0x4000000000420331) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class Argument #0: is a constant or invariant has global refs [001562] --C-G------ * CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) set to 0x4000000000420331: Invoking compiler for the inlinee method System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) : IL to import: IL_0000 28 91 1c 00 06 call 0x6001C91 IL_0005 02 ldarg.0 IL_0006 28 27 1b 00 06 call 0x6001B27 IL_000b 73 8e 0a 00 06 newobj 0x6000A8E IL_0010 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) is 0x4000000000420331. *************** In compInitDebuggingInfo() for System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) weight= 79 : state 40 [ call ] weight= 10 : state 3 [ ldarg.0 ] weight= 79 : state 40 [ call ] weight=227 : state 103 [ newobj ] weight=210 : state 108 [ throw ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=605 callsiteNativeSizeEstimate=85 benefit multiplier=1.3 threshold=110 Native estimate for function size exceeds threshold for inlining 60.5 > 11 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00202 in BB80: STMT00202 ( 0x30D[E-] ... 0x319 ) [000942] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000941] ----------- this \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000941] ----------- * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this set to 0x4000000000424641: Invoking compiler for the inlinee method System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 09 00 04 ldfld 0x4000933 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this is 0x4000000000424641. *************** In compInitDebuggingInfo() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this Jump targets: none New Basic Block BB219 [0214] created. BB219 [000..007) Basic block list for 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB219 [0214] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000942] Starting PHASE Pre-import *************** Inline @[000942] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB219 [0214] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB219 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000942] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000942] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB219 [0214] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB219 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000942] Starting PHASE Importation *************** In impImport() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this impImportBlockPending for BB219 Importing BB219 (PC=000) of 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000933 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001570] ---XG------ * FIELD ref : [000941] ----------- \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [001570] ---XG------ * FIELD ref : [000941] ----------- \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000942] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB219 [0214] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB219 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000942] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000942] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000942] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000942] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000942] Starting PHASE Post-import *************** Inline @[000942] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000942] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000943] with [001570] [000943] --C-------- * RET_EXPR ref (for [000942]) -> [001570] Inserting the inline return expression [001570] ---XG------ * FIELD ref : [000941] ----------- \--* LCL_VAR ref V03 arg3 Querying runtime about current class of field : (declared as int[]) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00221 in BB91: STMT00221 ( 0x368[E-] ... 0x371 ) [001018] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001017] ----------- this \--* ADDR byref [001016] -------N--- \--* LCL_VAR struct V19 loc15 thisArg: is a constant or invariant is byref to a struct local [001017] ----------- * ADDR byref [001016] -------N--- \--* LCL_VAR struct V19 loc15 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:get_Length():int:this set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:get_Length():int:this is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:get_Length():int:this Jump targets: none New Basic Block BB220 [0215] created. BB220 [000..007) Basic block list for 'System.Span`1[int]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB220 [0215] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001018] Starting PHASE Pre-import *************** Inline @[001018] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB220 [0215] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB220 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001018] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001018] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB220 [0215] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB220 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001018] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:get_Length():int:this impImportBlockPending for BB220 Importing BB220 (PC=000) of 'System.Span`1[int]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001574] ----------- * FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct V19 loc15 Inlinee Return expression (after normalization) => [001574] ----------- * FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct V19 loc15 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001018] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB220 [0215] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB220 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001018] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001018] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001018] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001018] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001018] Starting PHASE Post-import *************** Inline @[001018] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001018] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[int]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001019] with [001574] [001019] --C-------- * RET_EXPR int (for [001018]) -> [001574] Inserting the inline return expression [001574] ----------- * FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct V19 loc15 Expanding INLINE_CANDIDATE in statement STMT00228 in BB92: STMT00228 ( 0x373[E-] ... 0x381 ) [001063] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001062] ----------- this \--* ADDR byref [001061] -------N--- \--* LCL_VAR struct V19 loc15 thisArg: is a constant or invariant is byref to a struct local [001062] ----------- * ADDR byref [001061] -------N--- \--* LCL_VAR struct V19 loc15 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:get_Length():int:this set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:get_Length():int:this is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:get_Length():int:this Jump targets: none New Basic Block BB221 [0216] created. BB221 [000..007) Basic block list for 'System.Span`1[int]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB221 [0216] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001063] Starting PHASE Pre-import *************** Inline @[001063] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB221 [0216] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB221 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001063] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001063] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB221 [0216] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB221 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001063] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:get_Length():int:this impImportBlockPending for BB221 Importing BB221 (PC=000) of 'System.Span`1[int]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001578] ----------- * FIELD int :_length [001576] ----------- \--* ADDR byref [001577] -------N--- \--* LCL_VAR struct V19 loc15 Inlinee Return expression (after normalization) => [001578] ----------- * FIELD int :_length [001576] ----------- \--* ADDR byref [001577] -------N--- \--* LCL_VAR struct V19 loc15 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001063] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB221 [0216] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB221 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001063] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001063] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001063] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001063] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001063] Starting PHASE Post-import *************** Inline @[001063] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001063] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[int]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'n/a' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target is helper' Replacing the return expression placeholder [001064] with [001578] [001064] --C-------- * RET_EXPR int (for [001063]) -> [001578] Inserting the inline return expression [001578] ----------- * FIELD int :_length [001576] ----------- \--* ADDR byref [001577] -------N--- \--* LCL_VAR struct V19 loc15 Expanding INLINE_CANDIDATE in statement STMT00230 in BB92: STMT00230 ( 0x383[E-] ... 0x398 ) [001074] I-C-G------ * CALL r2r_ind struct System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] (exactContextHnd=0x40000000004219E1) [001073] ----------- arg0 \--* LCL_VAR ref V33 loc29 Argument #0: is a local var [001073] ----------- * LCL_VAR ref V33 loc29 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] : IL to import: IL_0000 02 ldarg.0 IL_0001 73 33 07 00 0a newobj 0xA000733 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] Jump targets: none New Basic Block BB222 [0217] created. BB222 [000..007) Basic block list for 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB222 [0217] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001074] Starting PHASE Pre-import *************** Inline @[001074] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB222 [0217] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB222 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001074] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001074] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB222 [0217] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB222 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001074] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] impImportBlockPending for BB222 Importing BB222 (PC=000) of 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) newobj lvaGrabTemp returning 78 (V78 tmp38) called for NewObj constructor temp. STMT00327 ( 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct V78 tmp38 [001581] ----------- \--* CNS_INT int 0 0A000733 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' calling 'System.Span`1[int]:.ctor(int[]):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00328 ( ??? ... ??? ) <- INLRT @ 0x383[E-] [001585] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(int[]):this (exactContextHnd=0x40000000004219E1) [001584] ----------- this +--* ADDR byref [001583] -------N--- | \--* LCL_VAR struct V78 tmp38 [001073] ----------- arg1 \--* LCL_VAR ref V33 loc29 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001586] ----------- * LCL_VAR struct V78 tmp38 *************** Inline @[001074] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB222 [0217] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB222 [000..007) (return), preds={} succs={} ***** BB222 STMT00327 ( 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct V78 tmp38 [001581] ----------- \--* CNS_INT int 0 ***** BB222 STMT00328 ( ??? ... ??? ) <- INLRT @ 0x383[E-] [001585] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(int[]):this (exactContextHnd=0x40000000004219E1) [001584] ----------- this +--* ADDR byref [001583] -------N--- | \--* LCL_VAR struct V78 tmp38 [001073] ----------- arg1 \--* LCL_VAR ref V33 loc29 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001074] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001074] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001074] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001074] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001074] Starting PHASE Post-import *************** Inline @[001074] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001074] ----------- Arguments setup: Inlinee method body: STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct V78 tmp38 [001581] ----------- \--* CNS_INT int 0 STMT00328 ( INL14 @ ??? ... ??? ) <- INLRT @ 0x383[E-] [001585] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(int[]):this (exactContextHnd=0x40000000004219E1) [001584] ----------- this +--* ADDR byref [001583] -------N--- | \--* LCL_VAR struct V78 tmp38 [001073] ----------- arg1 \--* LCL_VAR ref V33 loc29 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00328 in BB92: STMT00328 ( INL14 @ ??? ... ??? ) <- INLRT @ 0x383[E-] [001585] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(int[]):this (exactContextHnd=0x40000000004219E1) [001584] ----------- this +--* ADDR byref [001583] -------N--- | \--* LCL_VAR struct V78 tmp38 [001073] ----------- arg1 \--* LCL_VAR ref V33 loc29 thisArg: is a constant or invariant is byref to a struct local [001584] ----------- * ADDR byref [001583] -------N--- \--* LCL_VAR struct V78 tmp38 Argument #1: is a local var [001073] ----------- * LCL_VAR ref V33 loc29 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:.ctor(int[]):this set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:.ctor(int[]):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 08 brtrue.s 8 (IL_000b) IL_0003 02 ldarg.0 IL_0004 fe 15 d6 01 00 1b initobj 0x1B0001D6 IL_000a 2a ret IL_000b d0 2b 00 00 1b ldtoken 0x1B00002B IL_0010 28 a1 08 00 06 call 0x60008A1 IL_0015 28 e7 08 00 06 call 0x60008E7 IL_001a 2d 1c brtrue.s 28 (IL_0038) IL_001c 03 ldarg.1 IL_001d 6f 90 05 00 06 callvirt 0x6000590 IL_0022 d0 7d 00 00 1b ldtoken 0x1B00007D IL_0027 28 a1 08 00 06 call 0x60008A1 IL_002c 28 4d 09 00 06 call 0x600094D IL_0031 2c 05 brfalse.s 5 (IL_0038) IL_0033 28 9e 1f 00 06 call 0x6001F9E IL_0038 02 ldarg.0 IL_0039 03 ldarg.1 IL_003a 28 af 01 00 2b call 0x2B0001AF IL_003f 7d 38 06 00 0a stfld 0xA000638 IL_0044 02 ldarg.0 IL_0045 03 ldarg.1 IL_0046 8e ldlen IL_0047 69 conv.i4 IL_0048 7d 31 07 00 0a stfld 0xA000731 IL_004d 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:.ctor(int[]):this is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:.ctor(int[]):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:.ctor(int[]):this Jump targets: IL_000b IL_0038 New Basic Block BB223 [0218] created. BB223 [000..003) New Basic Block BB224 [0219] created. BB224 [003..00B) New Basic Block BB225 [0220] created. BB225 [00B..01C) New Basic Block BB226 [0221] created. BB226 [01C..033) New Basic Block BB227 [0222] created. BB227 [033..038) New Basic Block BB228 [0223] created. BB228 [038..04E) Basic block list for 'System.Span`1[int]:.ctor(int[]):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB223 [0218] 1 1 [000..003)-> BB225 ( cond ) BB224 [0219] 1 1 [003..00B) (return) BB225 [0220] 1 1 [00B..01C)-> BB228 ( cond ) BB226 [0221] 1 1 [01C..033)-> BB228 ( cond ) BB227 [0222] 1 1 [033..038) BB228 [0223] 3 1 [038..04E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001585] Starting PHASE Pre-import *************** Inline @[001585] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB223 [0218] 1 1 [000..003)-> BB225 ( cond ) BB224 [0219] 1 1 [003..00B) (return) BB225 [0220] 1 1 [00B..01C)-> BB228 ( cond ) BB226 [0221] 1 1 [01C..033)-> BB228 ( cond ) BB227 [0222] 1 1 [033..038) BB228 [0223] 3 1 [038..04E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB223 [000..003) -> BB225 (cond), preds={} succs={BB224,BB225} ------------ BB224 [003..00B) (return), preds={} succs={} ------------ BB225 [00B..01C) -> BB228 (cond), preds={} succs={BB226,BB228} ------------ BB226 [01C..033) -> BB228 (cond), preds={} succs={BB227,BB228} ------------ BB227 [033..038), preds={} succs={BB228} ------------ BB228 [038..04E) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001585] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001585] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB223 [0218] 1 1 [000..003)-> BB225 ( cond ) BB224 [0219] 1 1 [003..00B) (return) BB225 [0220] 1 1 [00B..01C)-> BB228 ( cond ) BB226 [0221] 1 1 [01C..033)-> BB228 ( cond ) BB227 [0222] 1 1 [033..038) BB228 [0223] 3 1 [038..04E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB223 [000..003) -> BB225 (cond), preds={} succs={BB224,BB225} ------------ BB224 [003..00B) (return), preds={} succs={} ------------ BB225 [00B..01C) -> BB228 (cond), preds={} succs={BB226,BB228} ------------ BB226 [01C..033) -> BB228 (cond), preds={} succs={BB227,BB228} ------------ BB227 [033..038), preds={} succs={BB228} ------------ BB228 [038..04E) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001585] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:.ctor(int[]):this impImportBlockPending for BB223 Importing BB223 (PC=000) of 'System.Span`1[int]:.ctor(int[]):this' [ 0] 0 (0x000) ldarg.1 [ 1] 1 (0x001) brtrue.s STMT00329 ( 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null impImportBlockPending for BB224 impImportBlockPending for BB225 Importing BB225 (PC=011) of 'System.Span`1[int]:.ctor(int[]):this' [ 0] 11 (0x00b) ldtoken [ 1] 16 (0x010) call 060008A1 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 Named Intrinsic System.Type.GetTypeFromHandle: Recognized [ 1] 21 (0x015) call 060008E7 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Named Intrinsic System.Type.get_IsValueType: Recognized [ 1] 26 (0x01a) brtrue.s Folding operator with constant nodes into a constant: [001597] ----------- * NE int [001595] ----------- +--* CNS_INT int 1 [001596] ----------- \--* CNS_INT int 0 Bashed to int constant: [001597] ----------- * CNS_INT int 1 The conditional jump becomes an unconditional jump to BB228 impImportBlockPending for BB228 Importing BB228 (PC=056) of 'System.Span`1[int]:.ctor(int[]):this' [ 0] 56 (0x038) ldarg.0 [ 1] 57 (0x039) ldarg.1 [ 2] 58 (0x03a) call 2B0001AF In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.InteropServices.MemoryMarshal.GetArrayDataReference: Not recognized INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:.ctor(int[]):this' calling 'System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00330 ( 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001601] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001600] ----------- arg0 \--* LCL_VAR ref V33 loc29 [ 2] 63 (0x03f) stfld 0A000638 STMT00331 ( 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct V78 tmp38 [001602] --C-------- \--* RET_EXPR byref (for [001601]) [ 0] 68 (0x044) ldarg.0 [ 1] 69 (0x045) ldarg.1 [ 2] 70 (0x046) ldlen [ 2] 71 (0x047) conv.i4 [ 2] 72 (0x048) stfld 0A000731 STMT00332 ( 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct V78 tmp38 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 [ 0] 77 (0x04d) ret Importing BB224 (PC=003) of 'System.Span`1[int]:.ctor(int[]):this' [ 0] 3 (0x003) ldarg.0 [ 1] 4 (0x004) initobj 1B0001D6 STMT00333 ( 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct V78 tmp38 [001613] ----------- \--* CNS_INT int 0 [ 0] 10 (0x00a) ret ** Note: inlinee IL was partially imported -- imported 33 of 78 bytes of method IL *************** Inline @[001585] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB223 [0218] 1 1 [000..003)-> BB225 ( cond ) i BB224 [0219] 1 1 [003..00B) (return) i BB225 [0220] 1 1 [00B..01C)-> BB228 (always) i BB226 [0221] 1 1 [01C..033)-> BB228 ( cond ) BB227 [0222] 1 1 [033..038) BB228 [0223] 3 1 [038..04E) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB223 [000..003) -> BB225 (cond), preds={} succs={BB224,BB225} ***** BB223 STMT00329 ( 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB224 [003..00B) (return), preds={} succs={} ***** BB224 STMT00333 ( 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct V78 tmp38 [001613] ----------- \--* CNS_INT int 0 ------------ BB225 [00B..01C) -> BB228 (always), preds={} succs={BB228} ------------ BB226 [01C..033) -> BB228 (cond), preds={} succs={BB227,BB228} ------------ BB227 [033..038), preds={} succs={BB228} ------------ BB228 [038..04E) (return), preds={} succs={} ***** BB228 STMT00330 ( 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001601] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001600] ----------- arg0 \--* LCL_VAR ref V33 loc29 ***** BB228 STMT00331 ( 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct V78 tmp38 [001602] --C-------- \--* RET_EXPR byref (for [001601]) ***** BB228 STMT00332 ( 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct V78 tmp38 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001585] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001585] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001585] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001585] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001585] Starting PHASE Post-import BB226 was not imported, marking as removed (0) BB227 was not imported, marking as removed (1) Renumbering the basic blocks for fgPostImportationCleanup *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB223 [0218] 1 1 [000..003)-> BB225 ( cond ) i BB224 [0219] 1 1 [003..00B) (return) i BB225 [0220] 1 1 [00B..01C)-> BB228 (always) i BB228 [0223] 3 1 [038..04E) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB223 to BB229 Renumber BB224 to BB230 Renumber BB225 to BB231 Renumber BB228 to BB232 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB229 [0218] 1 1 [000..003)-> BB231 ( cond ) i BB230 [0219] 1 1 [003..00B) (return) i BB231 [0220] 1 1 [00B..01C)-> BB232 (always) i BB232 [0223] 3 1 [038..04E) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 1, # of blocks (including unused BB00): 7, bitset array size: 1 (short) *************** Inline @[001585] Finishing PHASE Post-import Trees after Post-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB229 [0218] 1 1 [000..003)-> BB231 ( cond ) i BB230 [0219] 1 1 [003..00B) (return) i BB231 [0220] 1 1 [00B..01C)-> BB232 (always) i BB232 [0223] 3 1 [038..04E) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB229 [000..003) -> BB231 (cond), preds={} succs={BB230,BB231} ***** BB229 STMT00329 ( 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB230 [003..00B) (return), preds={} succs={} ***** BB230 STMT00333 ( 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct V78 tmp38 [001613] ----------- \--* CNS_INT int 0 ------------ BB231 [00B..01C) -> BB232 (always), preds={} succs={BB232} ------------ BB232 [038..04E) (return), preds={} succs={} ***** BB232 STMT00330 ( 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001601] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001600] ----------- arg0 \--* LCL_VAR ref V33 loc29 ***** BB232 STMT00331 ( 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct V78 tmp38 [001602] --C-------- \--* RET_EXPR byref (for [001601]) ***** BB232 STMT00332 ( 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct V78 tmp38 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [001585] ----------- Arguments setup: Inlinee method body:New Basic Block BB233 [0224] created. Convert bbJumpKind of BB230 to BBJ_ALWAYS to bottomBlock BB233 Convert bbJumpKind of BB232 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB229 [0218] 1 1 [383..384)-> BB231 ( cond ) i bwd BB230 [0219] 1 1 [383..384)-> BB233 (always) i bwd BB231 [0220] 1 1 [383..384)-> BB232 (always) i bwd BB232 [0223] 3 1 [383..384) i idxlen bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB229 [383..384) -> BB231 (cond), preds={} succs={BB230,BB231} ***** BB229 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB230 [383..384) -> BB233 (always), preds={} succs={BB233} ***** BB230 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct V78 tmp38 [001613] ----------- \--* CNS_INT int 0 ------------ BB231 [383..384) -> BB232 (always), preds={} succs={BB232} ------------ BB232 [383..384), preds={} succs={BB233} ***** BB232 STMT00330 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001601] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001600] ----------- arg0 \--* LCL_VAR ref V33 loc29 ***** BB232 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct V78 tmp38 [001602] --C-------- \--* RET_EXPR byref (for [001601]) ***** BB232 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct V78 tmp38 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Span`1[int]:.ctor(int[]):this (78 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:.ctor(int[]):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00330 in BB232: STMT00330 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001601] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001600] ----------- arg0 \--* LCL_VAR ref V33 loc29 Argument #0: is a local var [001600] ----------- * LCL_VAR ref V33 loc29 INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref set to 0x4000000000421960: Invoking compiler for the inlinee method System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref : IL to import: IL_0000 02 ldarg.0 IL_0001 7c 01 00 00 0a ldflda 0xA000001 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref is 0x4000000000421960. *************** In compInitDebuggingInfo() for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref Jump targets: none New Basic Block BB234 [0225] created. BB234 [000..007) Basic block list for 'System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB234 [0225] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001601] Starting PHASE Pre-import *************** Inline @[001601] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB234 [0225] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB234 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001601] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001601] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB234 [0225] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB234 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001601] Starting PHASE Importation *************** In impImport() for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref impImportBlockPending for BB234 Importing BB234 (PC=000) of 'System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldflda 0A000001 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001616] ---XG------ * FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 Inlinee Return expression (after normalization) => [001616] ---XG------ * FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001601] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB234 [0225] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB234 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001601] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001601] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001601] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001601] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001601] Starting PHASE Post-import *************** Inline @[001601] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001601] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (7 IL bytes) (depth 3) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [001602] with [001616] [001602] --C-------- * RET_EXPR byref (for [001601]) -> [001616] Inserting the inline return expression [001616] ---XG------ * FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 Replacing the return expression placeholder [001075] with [001586] [001075] --C-------- * RET_EXPR struct(for [001074]) -> [001586] Inserting the inline return expression [001586] ----------- * LCL_VAR struct V78 tmp38 Expanding INLINE_CANDIDATE in statement STMT00232 in BB233: STMT00232 ( ??? ... ??? ) [001076] I-C-G------ * CALL r2r_ind void System.Span`1[int]:CopyTo(System.Span`1[int]):this (exactContextHnd=0x40000000004219E1) [001072] ----------- this +--* ADDR byref [001071] -------N--- | \--* LCL_VAR struct V19 loc15 [001081] n---------- arg1 \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 thisArg: is a constant or invariant is byref to a struct local [001072] ----------- * ADDR byref [001071] -------N--- \--* LCL_VAR struct V19 loc15 Argument #1: [001081] n---------- * OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:CopyTo(System.Span`1[int]):this set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:CopyTo(System.Span`1[int]):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 0f 01 ldarga.s 0x1 IL_0008 28 d3 05 00 0a call 0xA0005D3 IL_000d 35 1a bgt.un.s 26 (IL_0029) IL_000f 0f 01 ldarga.s 0x1 IL_0011 7b 38 06 00 0a ldfld 0xA000638 IL_0016 02 ldarg.0 IL_0017 7b 38 06 00 0a ldfld 0xA000638 IL_001c 02 ldarg.0 IL_001d 7b 31 07 00 0a ldfld 0xA000731 IL_0022 e0 conv.u IL_0023 28 65 02 00 2b call 0x2B000265 IL_0028 2a ret IL_0029 28 a2 1f 00 06 call 0x6001FA2 IL_002e 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:CopyTo(System.Span`1[int]):this is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:CopyTo(System.Span`1[int]):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:CopyTo(System.Span`1[int]):this Jump targets: IL_0029 New Basic Block BB235 [0226] created. BB235 [000..00F) New Basic Block BB236 [0227] created. BB236 [00F..029) New Basic Block BB237 [0228] created. BB237 [029..02F) Basic block list for 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB235 [0226] 1 1 [000..00F)-> BB237 ( cond ) BB236 [0227] 1 1 [00F..029) (return) BB237 [0228] 1 1 [029..02F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001076] Starting PHASE Pre-import *************** Inline @[001076] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB235 [0226] 1 1 [000..00F)-> BB237 ( cond ) BB236 [0227] 1 1 [00F..029) (return) BB237 [0228] 1 1 [029..02F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB235 [000..00F) -> BB237 (cond), preds={} succs={BB236,BB237} ------------ BB236 [00F..029) (return), preds={} succs={} ------------ BB237 [029..02F) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001076] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001076] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB235 [0226] 1 1 [000..00F)-> BB237 ( cond ) BB236 [0227] 1 1 [00F..029) (return) BB237 [0228] 1 1 [029..02F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB235 [000..00F) -> BB237 (cond), preds={} succs={BB236,BB237} ------------ BB236 [00F..029) (return), preds={} succs={} ------------ BB237 [029..02F) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001076] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:CopyTo(System.Span`1[int]):this impImportBlockPending for BB235 Importing BB235 (PC=000) of 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ldarga.s 1 lvaGrabTemp returning 79 (V79 tmp39) called for Inlining Arg. [ 2] 8 (0x008) call 0A0005D3 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' calling 'System.Span`1[int]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' lvaGrabTemp returning 80 (V80 tmp40) called for impAppendStmt. STMT00335 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct V19 loc15 STMT00334 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001623] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001622] ----------- this \--* ADDR byref [001621] -------N--- \--* LCL_VAR struct V79 tmp39 [ 2] 13 (0x00d) bgt.un.s STMT00336 ( ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001627] --C-------- \--* RET_EXPR int (for [001623]) impImportBlockPending for BB236 impImportBlockPending for BB237 Importing BB237 (PC=041) of 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' [ 0] 41 (0x029) call 06001FA2 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' calling 'System.ThrowHelper:ThrowArgumentException_DestinationTooShort()' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00337 ( 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() (exactContextHnd=0x4000000000420331) [ 0] 46 (0x02e) ret Importing BB236 (PC=015) of 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' [ 0] 15 (0x00f) ldarga.s 1 [ 1] 17 (0x011) ldfld 0A000638 [ 1] 22 (0x016) ldarg.0 [ 2] 23 (0x017) ldfld 0A000638 [ 2] 28 (0x01c) ldarg.0 [ 3] 29 (0x01d) ldfld 0A000731 [ 3] 34 (0x022) conv.u [ 3] 35 (0x023) call 2B000265 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' calling 'System.Buffer:Memmove[int](byref,byref,ulong)' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00338 ( 0x00F[E-] ... ??? ) <- INLRT @ ??? [001641] I-C-G------ * CALL r2r_ind void System.Buffer:Memmove[int](byref,byref,ulong) (exactContextHnd=0x4000000000465B08) [001633] ----------- arg0 +--* FIELD byref :_reference [001632] ----------- | \--* ADDR byref [001631] -------N--- | \--* LCL_VAR struct V79 tmp39 [001636] ----------- arg1 +--* FIELD byref :_reference [001634] ----------- | \--* ADDR byref [001635] -------N--- | \--* LCL_VAR struct V19 loc15 [001640] ---------U- arg2 \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 [ 0] 40 (0x028) ret *************** Inline @[001076] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB235 [0226] 1 1 [000..00F)-> BB237 ( cond ) i BB236 [0227] 1 1 [00F..029) (return) i BB237 [0228] 1 1 [029..02F) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB235 [000..00F) -> BB237 (cond), preds={} succs={BB236,BB237} ***** BB235 STMT00335 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB235 STMT00334 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001623] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001622] ----------- this \--* ADDR byref [001621] -------N--- \--* LCL_VAR struct V79 tmp39 ***** BB235 STMT00336 ( ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001627] --C-------- \--* RET_EXPR int (for [001623]) ------------ BB236 [00F..029) (return), preds={} succs={} ***** BB236 STMT00338 ( 0x00F[E-] ... ??? ) <- INLRT @ ??? [001641] I-C-G------ * CALL r2r_ind void System.Buffer:Memmove[int](byref,byref,ulong) (exactContextHnd=0x4000000000465B08) [001633] ----------- arg0 +--* FIELD byref :_reference [001632] ----------- | \--* ADDR byref [001631] -------N--- | \--* LCL_VAR struct V79 tmp39 [001636] ----------- arg1 +--* FIELD byref :_reference [001634] ----------- | \--* ADDR byref [001635] -------N--- | \--* LCL_VAR struct V19 loc15 [001640] ---------U- arg2 \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB237 [029..02F) (return), preds={} succs={} ***** BB237 STMT00337 ( 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() (exactContextHnd=0x4000000000420331) ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001076] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001076] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001076] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001076] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001076] Starting PHASE Post-import *************** Inline @[001076] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001076] ----------- Arguments setup: STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct V79 tmp39 [001081] n---------- \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 Inlinee method body:New Basic Block BB238 [0229] created. Convert bbJumpKind of BB236 to BBJ_ALWAYS to bottomBlock BB238 Convert bbJumpKind of BB237 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB235 [0226] 1 1 [000..000)-> BB237 ( cond ) i internal bwd BB236 [0227] 1 1 [000..000)-> BB238 (always) i internal bwd BB237 [0228] 1 1 [000..000) i internal bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB235 [000..000) -> BB237 (cond), preds={} succs={BB236,BB237} ***** BB235 STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB235 STMT00334 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001623] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001622] ----------- this \--* ADDR byref [001621] -------N--- \--* LCL_VAR struct V79 tmp39 ***** BB235 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001627] --C-------- \--* RET_EXPR int (for [001623]) ------------ BB236 [000..000) -> BB238 (always), preds={} succs={BB238} ***** BB236 STMT00338 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001641] I-C-G------ * CALL r2r_ind void System.Buffer:Memmove[int](byref,byref,ulong) (exactContextHnd=0x4000000000465B08) [001633] ----------- arg0 +--* FIELD byref :_reference [001632] ----------- | \--* ADDR byref [001631] -------N--- | \--* LCL_VAR struct V79 tmp39 [001636] ----------- arg1 +--* FIELD byref :_reference [001634] ----------- | \--* ADDR byref [001635] -------N--- | \--* LCL_VAR struct V19 loc15 [001640] ---------U- arg2 \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB237 [000..000), preds={} succs={BB238} ***** BB237 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() (exactContextHnd=0x4000000000420331) ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Span`1[int]:CopyTo(System.Span`1[int]):this (47 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:CopyTo(System.Span`1[int]):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00334 in BB235: STMT00334 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001623] I-C-G------ * CALL r2r_ind int System.Span`1[int]:get_Length():int:this (exactContextHnd=0x40000000004219E1) [001622] ----------- this \--* ADDR byref [001621] -------N--- \--* LCL_VAR struct V79 tmp39 thisArg: is a constant or invariant is byref to a struct local [001622] ----------- * ADDR byref [001621] -------N--- \--* LCL_VAR struct V79 tmp39 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:get_Length():int:this set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:get_Length():int:this is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:get_Length():int:this Jump targets: none New Basic Block BB239 [0230] created. BB239 [000..007) Basic block list for 'System.Span`1[int]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB239 [0230] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001623] Starting PHASE Pre-import *************** Inline @[001623] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB239 [0230] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB239 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001623] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001623] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB239 [0230] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB239 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001623] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:get_Length():int:this impImportBlockPending for BB239 Importing BB239 (PC=000) of 'System.Span`1[int]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001647] ----------- * FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct V79 tmp39 Inlinee Return expression (after normalization) => [001647] ----------- * FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct V79 tmp39 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001623] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB239 [0230] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB239 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001623] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001623] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001623] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001623] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001623] Starting PHASE Post-import *************** Inline @[001623] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001623] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[int]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001627] with [001647] [001627] --C-------- * RET_EXPR int (for [001623]) -> [001647] Inserting the inline return expression [001647] ----------- * FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct V79 tmp39 Expanding INLINE_CANDIDATE in statement STMT00338 in BB236: STMT00338 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001641] I-C-G------ * CALL r2r_ind void System.Buffer:Memmove[int](byref,byref,ulong) (exactContextHnd=0x4000000000465B08) [001633] ----------- arg0 +--* FIELD byref :_reference [001632] ----------- | \--* ADDR byref [001631] -------N--- | \--* LCL_VAR struct V79 tmp39 [001636] ----------- arg1 +--* FIELD byref :_reference [001634] ----------- | \--* ADDR byref [001635] -------N--- | \--* LCL_VAR struct V19 loc15 [001640] ---------U- arg2 \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 Argument #0: has caller local ref [001633] ----------- * FIELD byref :_reference [001632] ----------- \--* ADDR byref [001631] -------N--- \--* LCL_VAR struct V79 tmp39 Argument #1: has caller local ref [001636] ----------- * FIELD byref :_reference [001634] ----------- \--* ADDR byref [001635] -------N--- \--* LCL_VAR struct V19 loc15 Argument #2: has caller local ref [001640] ---------U- * CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 INLINER: inlineInfo.tokenLookupContextHandle for System.Buffer:Memmove[int](byref,byref,ulong) set to 0x4000000000465B08: Invoking compiler for the inlinee method System.Buffer:Memmove[int](byref,byref,ulong) : IL to import: IL_0000 28 83 00 00 2b call 0x2B000083 IL_0005 2d 1b brtrue.s 27 (IL_0022) IL_0007 02 ldarg.0 IL_0008 28 3f 00 00 2b call 0x2B00003F IL_000d 03 ldarg.1 IL_000e 28 3f 00 00 2b call 0x2B00003F IL_0013 04 ldarg.2 IL_0014 fe 1c 1a 00 00 1b sizeof 0x1B00001A IL_001a d3 conv.i IL_001b 5a mul IL_001c 28 67 02 00 06 call 0x6000267 IL_0021 2a ret IL_0022 02 ldarg.0 IL_0023 28 3f 00 00 2b call 0x2B00003F IL_0028 03 ldarg.1 IL_0029 28 3f 00 00 2b call 0x2B00003F IL_002e 04 ldarg.2 IL_002f fe 1c 1a 00 00 1b sizeof 0x1B00001A IL_0035 d3 conv.i IL_0036 5a mul IL_0037 28 6b 02 00 06 call 0x600026B IL_003c 2a ret INLINER impTokenLookupContextHandle for System.Buffer:Memmove[int](byref,byref,ulong) is 0x4000000000465B08. *************** In compInitDebuggingInfo() for System.Buffer:Memmove[int](byref,byref,ulong) info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Buffer:Memmove[int](byref,byref,ulong) Jump targets: IL_0022 New Basic Block BB240 [0231] created. BB240 [000..007) New Basic Block BB241 [0232] created. BB241 [007..022) New Basic Block BB242 [0233] created. BB242 [022..03D) Basic block list for 'System.Buffer:Memmove[int](byref,byref,ulong)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB240 [0231] 1 1 [000..007)-> BB242 ( cond ) BB241 [0232] 1 1 [007..022) (return) BB242 [0233] 1 1 [022..03D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001641] Starting PHASE Pre-import *************** Inline @[001641] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB240 [0231] 1 1 [000..007)-> BB242 ( cond ) BB241 [0232] 1 1 [007..022) (return) BB242 [0233] 1 1 [022..03D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB240 [000..007) -> BB242 (cond), preds={} succs={BB241,BB242} ------------ BB241 [007..022) (return), preds={} succs={} ------------ BB242 [022..03D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001641] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001641] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB240 [0231] 1 1 [000..007)-> BB242 ( cond ) BB241 [0232] 1 1 [007..022) (return) BB242 [0233] 1 1 [022..03D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB240 [000..007) -> BB242 (cond), preds={} succs={BB241,BB242} ------------ BB241 [007..022) (return), preds={} succs={} ------------ BB242 [022..03D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001641] Starting PHASE Importation *************** In impImport() for System.Buffer:Memmove[int](byref,byref,ulong) impImportBlockPending for BB240 Importing BB240 (PC=000) of 'System.Buffer:Memmove[int](byref,byref,ulong)' [ 0] 0 (0x000) call 2B000083 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.RuntimeHelpers.IsReferenceOrContainsReferences: Not recognized INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Buffer:Memmove[int](byref,byref,ulong)' calling 'System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00340 ( 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001649] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) [ 1] 5 (0x005) brtrue.s STMT00341 ( 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] --C-------- * JTRUE void [001652] --C-------- \--* NE int [001650] --C-------- +--* RET_EXPR int (for [001649]) [001651] ----------- \--* CNS_INT int 0 impImportBlockPending for BB241 impImportBlockPending for BB242 Importing BB242 (PC=034) of 'System.Buffer:Memmove[int](byref,byref,ulong)' [ 0] 34 (0x022) ldarg.0 lvaGrabTemp returning 81 (V81 tmp41) called for Inlining Arg. [ 1] 35 (0x023) call 2B00003F In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.Unsafe.As: Recognized [ 1] 40 (0x028) ldarg.1 lvaGrabTemp returning 82 (V82 tmp42) called for Inlining Arg. [ 2] 41 (0x029) call 2B00003F In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.Unsafe.As: Recognized [ 2] 46 (0x02e) ldarg.2 lvaGrabTemp returning 83 (V83 tmp43) called for Inlining Arg. [ 3] 47 (0x02f) sizeof 1B00001A [ 4] 53 (0x035) conv.i Folding long operator with constant nodes into a constant: [001658] ----------- * CAST long <- int [001657] ----------- \--* CNS_INT int 4 Bashed to long constant: [001658] ----------- * CNS_INT long 4 [ 4] 54 (0x036) mul [ 3] 55 (0x037) call 0600026B In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Buffer:Memmove[int](byref,byref,ulong)' calling 'System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong)' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00342 ( 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001660] I-C-G------ * CALL r2r_ind void System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) (exactContextHnd=0x40000000004203E9) [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001659] ----------- arg2 \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 [ 0] 60 (0x03c) ret Importing BB241 (PC=007) of 'System.Buffer:Memmove[int](byref,byref,ulong)' [ 0] 7 (0x007) ldarg.0 [ 1] 8 (0x008) call 2B00003F In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.Unsafe.As: Recognized [ 1] 13 (0x00d) ldarg.1 [ 2] 14 (0x00e) call 2B00003F In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.CompilerServices.Unsafe.As: Recognized [ 2] 19 (0x013) ldarg.2 [ 3] 20 (0x014) sizeof 1B00001A [ 4] 26 (0x01a) conv.i Folding long operator with constant nodes into a constant: [001665] ----------- * CAST long <- int [001664] ----------- \--* CNS_INT int 4 Bashed to long constant: [001665] ----------- * CNS_INT long 4 [ 4] 27 (0x01b) mul [ 3] 28 (0x01c) call 06000267 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Buffer:Memmove[int](byref,byref,ulong)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' STMT00343 ( 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 [ 0] 33 (0x021) ret *************** Inline @[001641] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB240 [0231] 1 1 [000..007)-> BB242 ( cond ) i BB241 [0232] 1 1 [007..022) (return) i BB242 [0233] 1 1 [022..03D) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB240 [000..007) -> BB242 (cond), preds={} succs={BB241,BB242} ***** BB240 STMT00340 ( 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001649] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) ***** BB240 STMT00341 ( 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] --C-------- * JTRUE void [001652] --C-------- \--* NE int [001650] --C-------- +--* RET_EXPR int (for [001649]) [001651] ----------- \--* CNS_INT int 0 ------------ BB241 [007..022) (return), preds={} succs={} ***** BB241 STMT00343 ( 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB242 [022..03D) (return), preds={} succs={} ***** BB242 STMT00342 ( 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001660] I-C-G------ * CALL r2r_ind void System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) (exactContextHnd=0x40000000004203E9) [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001659] ----------- arg2 \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001641] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001641] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001641] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001641] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001641] Starting PHASE Post-import *************** Inline @[001641] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001641] ----------- Arguments setup: STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* FIELD byref :_reference [001632] ----------- \--* ADDR byref [001631] -------N--- \--* LCL_VAR struct V79 tmp39 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* FIELD byref :_reference [001634] ----------- \--* ADDR byref [001635] -------N--- \--* LCL_VAR struct V19 loc15 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 Inlinee method body:New Basic Block BB243 [0234] created. Convert bbJumpKind of BB241 to BBJ_ALWAYS to bottomBlock BB243 Convert bbJumpKind of BB242 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB240 [0231] 1 1 [000..000)-> BB242 ( cond ) i internal bwd BB241 [0232] 1 1 [000..000)-> BB243 (always) i internal bwd BB242 [0233] 1 1 [000..000) i internal bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB240 [000..000) -> BB242 (cond), preds={} succs={BB241,BB242} ***** BB240 STMT00340 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001649] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) ***** BB240 STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] --C-------- * JTRUE void [001652] --C-------- \--* NE int [001650] --C-------- +--* RET_EXPR int (for [001649]) [001651] ----------- \--* CNS_INT int 0 ------------ BB241 [000..000) -> BB243 (always), preds={} succs={BB243} ***** BB241 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB242 [000..000), preds={} succs={BB243} ***** BB242 STMT00342 ( INL19 @ 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001660] I-C-G------ * CALL r2r_ind void System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) (exactContextHnd=0x40000000004203E9) [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001659] ----------- arg2 \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Buffer:Memmove[int](byref,byref,ulong) (61 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Buffer:Memmove[int](byref,byref,ulong)' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00340 in BB240: STMT00340 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001649] I-C-G------ * CALL r2r_ind int System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (exactContextHnd=0x4000000000421A38) INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool set to 0x4000000000421A38: Invoking compiler for the inlinee method System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool : IL to import: IL_0000 16 ldc.i4.0 IL_0001 2a ret INLINER impTokenLookupContextHandle for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool is 0x4000000000421A38. *************** In compInitDebuggingInfo() for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool Jump targets: none New Basic Block BB244 [0235] created. BB244 [000..002) Basic block list for 'System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB244 [0235] 1 1 [000..002) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001649] Starting PHASE Pre-import *************** Inline @[001649] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB244 [0235] 1 1 [000..002) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB244 [000..002) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001649] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001649] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB244 [0235] 1 1 [000..002) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB244 [000..002) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001649] Starting PHASE Importation *************** In impImport() for System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool impImportBlockPending for BB244 Importing BB244 (PC=000) of 'System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool' [ 0] 0 (0x000) ldc.i4.0 0 [ 1] 1 (0x001) ret Inlinee Return expression (before normalization) => [001675] ----------- * CNS_INT int 0 Inlinee Return expression (after normalization) => [001676] ----------- * CAST int <- bool <- int [001675] ----------- \--* CNS_INT int 0 ** Note: inlinee IL was partially imported -- imported 0 of 2 bytes of method IL *************** Inline @[001649] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB244 [0235] 1 1 [000..002) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB244 [000..002) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001649] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001649] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001649] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001649] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001649] Starting PHASE Post-import *************** Inline @[001649] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001649] ----------- Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool (2 IL bytes) (depth 3) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Folding operator with constant nodes into a constant: [001676] ----------- * CAST int <- bool <- int [001675] ----------- \--* CNS_INT int 0 Bashed to int constant: [001676] ----------- * CNS_INT int 0 Replacing the return expression placeholder [001650] with [001676] [001650] --C-------- * RET_EXPR int (for [001649]) -> [001676] Inserting the inline return expression [001676] ----------- * CNS_INT int 0 Folding operator with constant nodes into a constant: [001652] --C-------- * NE int [001676] ----------- +--* CNS_INT int 0 [001651] ----------- \--* CNS_INT int 0 Bashed to int constant: [001652] ----------- * CNS_INT int 0 ... found foldable jtrue at [001653] in BB240 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' Expanding INLINE_CANDIDATE in statement STMT00342 in BB242: STMT00342 ( INL19 @ 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001660] I-C-G------ * CALL r2r_ind void System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) (exactContextHnd=0x40000000004203E9) [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001659] ----------- arg2 \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 Argument #0: is a local var [001654] ----------- * LCL_VAR byref V81 tmp41 Argument #1: is a local var [001655] ----------- * LCL_VAR byref V82 tmp42 Argument #2: [001659] ----------- * MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 INLINER: inlineInfo.tokenLookupContextHandle for System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) set to 0x40000000004203E9: Invoking compiler for the inlinee method System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) : IL to import: IL_0000 04 ldarg.2 IL_0001 20 00 04 00 00 ldc.i4 0x400 IL_0006 d3 conv.i IL_0007 35 09 bgt.un.s 9 (IL_0012) IL_0009 02 ldarg.0 IL_000a 03 ldarg.1 IL_000b 04 ldarg.2 IL_000c 28 5e 02 00 06 call 0x600025E IL_0011 2a ret IL_0012 02 ldarg.0 IL_0013 03 ldarg.1 IL_0014 04 ldarg.2 IL_0015 28 6c 02 00 06 call 0x600026C IL_001a 2a ret INLINER impTokenLookupContextHandle for System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) is 0x40000000004203E9. *************** In compInitDebuggingInfo() for System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) weight= 35 : state 5 [ ldarg.2 ] weight= 38 : state 33 [ ldc.i4 ] weight= 0 : state 157 [ conv.i ] weight=-52 : state 53 [ bgt.un.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate has an arg that feeds a constant test. Multiplier increased to 2. Inline candidate callsite is in a loop. Multiplier increased to 5. calleeNativeSizeEstimate=339 callsiteNativeSizeEstimate=145 benefit multiplier=5 threshold=725 Native estimate for function size is within threshold for inlining 33.9 <= 72.5 (multiplier = 5) Jump targets: IL_0012 New Basic Block BB245 [0236] created. BB245 [000..009) New Basic Block BB246 [0237] created. BB246 [009..012) New Basic Block BB247 [0238] created. BB247 [012..01B) Basic block list for 'System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB245 [0236] 1 1 [000..009)-> BB247 ( cond ) BB246 [0237] 1 1 [009..012) (return) BB247 [0238] 1 1 [012..01B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001660] Starting PHASE Pre-import *************** Inline @[001660] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB245 [0236] 1 1 [000..009)-> BB247 ( cond ) BB246 [0237] 1 1 [009..012) (return) BB247 [0238] 1 1 [012..01B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB245 [000..009) -> BB247 (cond), preds={} succs={BB246,BB247} ------------ BB246 [009..012) (return), preds={} succs={} ------------ BB247 [012..01B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001660] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001660] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB245 [0236] 1 1 [000..009)-> BB247 ( cond ) BB246 [0237] 1 1 [009..012) (return) BB247 [0238] 1 1 [012..01B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB245 [000..009) -> BB247 (cond), preds={} succs={BB246,BB247} ------------ BB246 [009..012) (return), preds={} succs={} ------------ BB247 [012..01B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001660] Starting PHASE Importation *************** In impImport() for System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) impImportBlockPending for BB245 Importing BB245 (PC=000) of 'System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong)' [ 0] 0 (0x000) ldarg.2 lvaGrabTemp returning 84 (V84 tmp44) called for Inlining Arg. [ 1] 1 (0x001) ldc.i4 1024 [ 2] 6 (0x006) conv.i Folding long operator with constant nodes into a constant: [001680] ----------- * CAST long <- int [001679] ----------- \--* CNS_INT int 0x400 Bashed to long constant: [001680] ----------- * CNS_INT long 0x400 [ 2] 7 (0x007) bgt.un.s STMT00347 ( 0x000[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001682] ----------- * JTRUE void [001681] N--------U- \--* GT int [001678] ----------- +--* LCL_VAR long V84 tmp44 [001680] ----------- \--* CNS_INT long 0x400 impImportBlockPending for BB246 impImportBlockPending for BB247 Importing BB247 (PC=018) of 'System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong)' [ 0] 18 (0x012) ldarg.0 [ 1] 19 (0x013) ldarg.1 [ 2] 20 (0x014) ldarg.2 [ 3] 21 (0x015) call 0600026C In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong)' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00348 ( 0x012[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001684] --C-G------ * CALL r2r_ind void [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001683] ----------- arg2 \--* LCL_VAR long V84 tmp44 [ 0] 26 (0x01a) ret Importing BB246 (PC=009) of 'System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong)' [ 0] 9 (0x009) ldarg.0 [ 1] 10 (0x00a) ldarg.1 [ 2] 11 (0x00b) ldarg.2 [ 3] 12 (0x00c) call 0600025E In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'cannot get method info' for 'System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong)' calling '' INLINER: Marking as NOINLINE because of cannot get method info INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'cannot get method info' STMT00349 ( 0x009[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001688] --C-G------ * CALL r2r_ind void [001685] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001686] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001687] ----------- arg2 \--* LCL_VAR long V84 tmp44 [ 0] 17 (0x011) ret *************** Inline @[001660] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB245 [0236] 1 1 [000..009)-> BB247 ( cond ) i BB246 [0237] 1 1 [009..012) (return) i BB247 [0238] 1 1 [012..01B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB245 [000..009) -> BB247 (cond), preds={} succs={BB246,BB247} ***** BB245 STMT00347 ( 0x000[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001682] ----------- * JTRUE void [001681] N--------U- \--* GT int [001678] ----------- +--* LCL_VAR long V84 tmp44 [001680] ----------- \--* CNS_INT long 0x400 ------------ BB246 [009..012) (return), preds={} succs={} ***** BB246 STMT00349 ( 0x009[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001688] --C-G------ * CALL r2r_ind void [001685] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001686] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001687] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------ BB247 [012..01B) (return), preds={} succs={} ***** BB247 STMT00348 ( 0x012[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001684] --C-G------ * CALL r2r_ind void [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001683] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001660] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001660] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001660] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001660] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001660] Starting PHASE Post-import *************** Inline @[001660] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001660] ----------- Arguments setup: STMT00350 ( INL19 @ 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001690] -A--------- * ASG long [001689] D------N--- +--* LCL_VAR long V84 tmp44 [001659] ----------- \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 Inlinee method body:New Basic Block BB248 [0239] created. Convert bbJumpKind of BB246 to BBJ_ALWAYS to bottomBlock BB248 Convert bbJumpKind of BB247 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB245 [0236] 1 1 [000..000)-> BB247 ( cond ) i internal bwd BB246 [0237] 1 1 [000..000)-> BB248 (always) i internal bwd BB247 [0238] 1 1 [000..000) i internal bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB245 [000..000) -> BB247 (cond), preds={} succs={BB246,BB247} ***** BB245 STMT00347 ( INL21 @ 0x000[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001682] ----------- * JTRUE void [001681] N--------U- \--* GT int [001678] ----------- +--* LCL_VAR long V84 tmp44 [001680] ----------- \--* CNS_INT long 0x400 ------------ BB246 [000..000) -> BB248 (always), preds={} succs={BB248} ***** BB246 STMT00349 ( INL21 @ 0x009[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001688] --C-G------ * CALL r2r_ind void [001685] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001686] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001687] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------ BB247 [000..000), preds={} succs={BB248} ***** BB247 STMT00348 ( INL21 @ 0x012[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001684] --C-G------ * CALL r2r_ind void [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001683] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) (27 IL bytes) (depth 3) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong)' INLINER: during 'fgInline' result 'success' reason 'profitable inline' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'cannot get method info' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of cannot get method info INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'cannot get method info' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00337 in BB237: STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] I-C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() (exactContextHnd=0x4000000000420331) INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowArgumentException_DestinationTooShort() set to 0x4000000000420331: Invoking compiler for the inlinee method System.ThrowHelper:ThrowArgumentException_DestinationTooShort() : IL to import: IL_0000 28 3a 1c 00 06 call 0x6001C3A IL_0005 72 0c 1a 00 70 ldstr 0x70001A0C IL_000a 73 91 0a 00 06 newobj 0x6000A91 IL_000f 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowArgumentException_DestinationTooShort() is 0x4000000000420331. *************** In compInitDebuggingInfo() for System.ThrowHelper:ThrowArgumentException_DestinationTooShort() info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowArgumentException_DestinationTooShort() Jump targets: none New Basic Block BB249 [0240] created. BB249 [000..010) Basic block list for 'System.ThrowHelper:ThrowArgumentException_DestinationTooShort()' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB249 [0240] 1 0 [000..010) (throw ) rare ----------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ThrowHelper:ThrowArgumentException_DestinationTooShort()' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement STMT00233 in BB238: STMT00233 ( 0x391[E-] ... ??? ) [001083] I-C-G------ * CALL r2r_ind struct System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] (exactContextHnd=0x40000000004219E1) [001082] ----------- arg0 \--* LCL_VAR ref V33 loc29 Argument #0: is a local var [001082] ----------- * LCL_VAR ref V33 loc29 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] : IL to import: IL_0000 02 ldarg.0 IL_0001 73 33 07 00 0a newobj 0xA000733 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] Jump targets: none New Basic Block BB250 [0240] created. BB250 [000..007) Basic block list for 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB250 [0240] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001083] Starting PHASE Pre-import *************** Inline @[001083] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB250 [0240] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB250 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001083] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001083] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB250 [0240] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB250 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001083] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] impImportBlockPending for BB250 Importing BB250 (PC=000) of 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) newobj lvaGrabTemp returning 85 (V85 tmp45) called for NewObj constructor temp. STMT00351 ( 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct V85 tmp45 [001693] ----------- \--* CNS_INT int 0 0A000733 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' calling 'System.Span`1[int]:.ctor(int[]):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00352 ( ??? ... ??? ) <- INLRT @ 0x391[E-] [001697] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(int[]):this (exactContextHnd=0x40000000004219E1) [001696] ----------- this +--* ADDR byref [001695] -------N--- | \--* LCL_VAR struct V85 tmp45 [001082] ----------- arg1 \--* LCL_VAR ref V33 loc29 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001698] ----------- * LCL_VAR struct V85 tmp45 *************** Inline @[001083] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB250 [0240] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB250 [000..007) (return), preds={} succs={} ***** BB250 STMT00351 ( 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct V85 tmp45 [001693] ----------- \--* CNS_INT int 0 ***** BB250 STMT00352 ( ??? ... ??? ) <- INLRT @ 0x391[E-] [001697] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(int[]):this (exactContextHnd=0x40000000004219E1) [001696] ----------- this +--* ADDR byref [001695] -------N--- | \--* LCL_VAR struct V85 tmp45 [001082] ----------- arg1 \--* LCL_VAR ref V33 loc29 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001083] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001083] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001083] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001083] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001083] Starting PHASE Post-import *************** Inline @[001083] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001083] ----------- Arguments setup: Inlinee method body: STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct V85 tmp45 [001693] ----------- \--* CNS_INT int 0 STMT00352 ( INL22 @ ??? ... ??? ) <- INLRT @ 0x391[E-] [001697] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(int[]):this (exactContextHnd=0x40000000004219E1) [001696] ----------- this +--* ADDR byref [001695] -------N--- | \--* LCL_VAR struct V85 tmp45 [001082] ----------- arg1 \--* LCL_VAR ref V33 loc29 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:op_Implicit(int[]):System.Span`1[int]' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00352 in BB238: STMT00352 ( INL22 @ ??? ... ??? ) <- INLRT @ 0x391[E-] [001697] I-C-G------ * CALL r2r_ind void System.Span`1[int]:.ctor(int[]):this (exactContextHnd=0x40000000004219E1) [001696] ----------- this +--* ADDR byref [001695] -------N--- | \--* LCL_VAR struct V85 tmp45 [001082] ----------- arg1 \--* LCL_VAR ref V33 loc29 thisArg: is a constant or invariant is byref to a struct local [001696] ----------- * ADDR byref [001695] -------N--- \--* LCL_VAR struct V85 tmp45 Argument #1: is a local var [001082] ----------- * LCL_VAR ref V33 loc29 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[int]:.ctor(int[]):this set to 0x40000000004219E1: Invoking compiler for the inlinee method System.Span`1[int]:.ctor(int[]):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 08 brtrue.s 8 (IL_000b) IL_0003 02 ldarg.0 IL_0004 fe 15 d6 01 00 1b initobj 0x1B0001D6 IL_000a 2a ret IL_000b d0 2b 00 00 1b ldtoken 0x1B00002B IL_0010 28 a1 08 00 06 call 0x60008A1 IL_0015 28 e7 08 00 06 call 0x60008E7 IL_001a 2d 1c brtrue.s 28 (IL_0038) IL_001c 03 ldarg.1 IL_001d 6f 90 05 00 06 callvirt 0x6000590 IL_0022 d0 7d 00 00 1b ldtoken 0x1B00007D IL_0027 28 a1 08 00 06 call 0x60008A1 IL_002c 28 4d 09 00 06 call 0x600094D IL_0031 2c 05 brfalse.s 5 (IL_0038) IL_0033 28 9e 1f 00 06 call 0x6001F9E IL_0038 02 ldarg.0 IL_0039 03 ldarg.1 IL_003a 28 af 01 00 2b call 0x2B0001AF IL_003f 7d 38 06 00 0a stfld 0xA000638 IL_0044 02 ldarg.0 IL_0045 03 ldarg.1 IL_0046 8e ldlen IL_0047 69 conv.i4 IL_0048 7d 31 07 00 0a stfld 0xA000731 IL_004d 2a ret INLINER impTokenLookupContextHandle for System.Span`1[int]:.ctor(int[]):this is 0x40000000004219E1. *************** In compInitDebuggingInfo() for System.Span`1[int]:.ctor(int[]):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[int]:.ctor(int[]):this Jump targets: IL_000b IL_0038 New Basic Block BB251 [0241] created. BB251 [000..003) New Basic Block BB252 [0242] created. BB252 [003..00B) New Basic Block BB253 [0243] created. BB253 [00B..01C) New Basic Block BB254 [0244] created. BB254 [01C..033) New Basic Block BB255 [0245] created. BB255 [033..038) New Basic Block BB256 [0246] created. BB256 [038..04E) Basic block list for 'System.Span`1[int]:.ctor(int[]):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB251 [0241] 1 1 [000..003)-> BB253 ( cond ) BB252 [0242] 1 1 [003..00B) (return) BB253 [0243] 1 1 [00B..01C)-> BB256 ( cond ) BB254 [0244] 1 1 [01C..033)-> BB256 ( cond ) BB255 [0245] 1 1 [033..038) BB256 [0246] 3 1 [038..04E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001697] Starting PHASE Pre-import *************** Inline @[001697] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB251 [0241] 1 1 [000..003)-> BB253 ( cond ) BB252 [0242] 1 1 [003..00B) (return) BB253 [0243] 1 1 [00B..01C)-> BB256 ( cond ) BB254 [0244] 1 1 [01C..033)-> BB256 ( cond ) BB255 [0245] 1 1 [033..038) BB256 [0246] 3 1 [038..04E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB251 [000..003) -> BB253 (cond), preds={} succs={BB252,BB253} ------------ BB252 [003..00B) (return), preds={} succs={} ------------ BB253 [00B..01C) -> BB256 (cond), preds={} succs={BB254,BB256} ------------ BB254 [01C..033) -> BB256 (cond), preds={} succs={BB255,BB256} ------------ BB255 [033..038), preds={} succs={BB256} ------------ BB256 [038..04E) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001697] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001697] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB251 [0241] 1 1 [000..003)-> BB253 ( cond ) BB252 [0242] 1 1 [003..00B) (return) BB253 [0243] 1 1 [00B..01C)-> BB256 ( cond ) BB254 [0244] 1 1 [01C..033)-> BB256 ( cond ) BB255 [0245] 1 1 [033..038) BB256 [0246] 3 1 [038..04E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB251 [000..003) -> BB253 (cond), preds={} succs={BB252,BB253} ------------ BB252 [003..00B) (return), preds={} succs={} ------------ BB253 [00B..01C) -> BB256 (cond), preds={} succs={BB254,BB256} ------------ BB254 [01C..033) -> BB256 (cond), preds={} succs={BB255,BB256} ------------ BB255 [033..038), preds={} succs={BB256} ------------ BB256 [038..04E) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001697] Starting PHASE Importation *************** In impImport() for System.Span`1[int]:.ctor(int[]):this impImportBlockPending for BB251 Importing BB251 (PC=000) of 'System.Span`1[int]:.ctor(int[]):this' [ 0] 0 (0x000) ldarg.1 [ 1] 1 (0x001) brtrue.s STMT00353 ( 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null impImportBlockPending for BB252 impImportBlockPending for BB253 Importing BB253 (PC=011) of 'System.Span`1[int]:.ctor(int[]):this' [ 0] 11 (0x00b) ldtoken [ 1] 16 (0x010) call 060008A1 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 Named Intrinsic System.Type.GetTypeFromHandle: Recognized [ 1] 21 (0x015) call 060008E7 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Named Intrinsic System.Type.get_IsValueType: Recognized [ 1] 26 (0x01a) brtrue.s Folding operator with constant nodes into a constant: [001709] ----------- * NE int [001707] ----------- +--* CNS_INT int 1 [001708] ----------- \--* CNS_INT int 0 Bashed to int constant: [001709] ----------- * CNS_INT int 1 The conditional jump becomes an unconditional jump to BB256 impImportBlockPending for BB256 Importing BB256 (PC=056) of 'System.Span`1[int]:.ctor(int[]):this' [ 0] 56 (0x038) ldarg.0 [ 1] 57 (0x039) ldarg.1 [ 2] 58 (0x03a) call 2B0001AF In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Runtime.InteropServices.MemoryMarshal.GetArrayDataReference: Not recognized INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Span`1[int]:.ctor(int[]):this' calling 'System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00354 ( 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001713] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001712] ----------- arg0 \--* LCL_VAR ref V33 loc29 [ 2] 63 (0x03f) stfld 0A000638 STMT00355 ( 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct V85 tmp45 [001714] --C-------- \--* RET_EXPR byref (for [001713]) [ 0] 68 (0x044) ldarg.0 [ 1] 69 (0x045) ldarg.1 [ 2] 70 (0x046) ldlen [ 2] 71 (0x047) conv.i4 [ 2] 72 (0x048) stfld 0A000731 STMT00356 ( 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct V85 tmp45 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 [ 0] 77 (0x04d) ret Importing BB252 (PC=003) of 'System.Span`1[int]:.ctor(int[]):this' [ 0] 3 (0x003) ldarg.0 [ 1] 4 (0x004) initobj 1B0001D6 STMT00357 ( 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct V85 tmp45 [001725] ----------- \--* CNS_INT int 0 [ 0] 10 (0x00a) ret ** Note: inlinee IL was partially imported -- imported 33 of 78 bytes of method IL *************** Inline @[001697] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB251 [0241] 1 1 [000..003)-> BB253 ( cond ) i BB252 [0242] 1 1 [003..00B) (return) i BB253 [0243] 1 1 [00B..01C)-> BB256 (always) i BB254 [0244] 1 1 [01C..033)-> BB256 ( cond ) BB255 [0245] 1 1 [033..038) BB256 [0246] 3 1 [038..04E) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB251 [000..003) -> BB253 (cond), preds={} succs={BB252,BB253} ***** BB251 STMT00353 ( 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB252 [003..00B) (return), preds={} succs={} ***** BB252 STMT00357 ( 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct V85 tmp45 [001725] ----------- \--* CNS_INT int 0 ------------ BB253 [00B..01C) -> BB256 (always), preds={} succs={BB256} ------------ BB254 [01C..033) -> BB256 (cond), preds={} succs={BB255,BB256} ------------ BB255 [033..038), preds={} succs={BB256} ------------ BB256 [038..04E) (return), preds={} succs={} ***** BB256 STMT00354 ( 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001713] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001712] ----------- arg0 \--* LCL_VAR ref V33 loc29 ***** BB256 STMT00355 ( 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct V85 tmp45 [001714] --C-------- \--* RET_EXPR byref (for [001713]) ***** BB256 STMT00356 ( 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct V85 tmp45 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001697] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001697] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001697] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001697] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001697] Starting PHASE Post-import BB254 was not imported, marking as removed (0) BB255 was not imported, marking as removed (1) Renumbering the basic blocks for fgPostImportationCleanup *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB251 [0241] 1 1 [000..003)-> BB253 ( cond ) i BB252 [0242] 1 1 [003..00B) (return) i BB253 [0243] 1 1 [00B..01C)-> BB256 (always) i BB256 [0246] 3 1 [038..04E) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB251 to BB257 Renumber BB252 to BB258 Renumber BB253 to BB259 Renumber BB256 to BB260 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB257 [0241] 1 1 [000..003)-> BB259 ( cond ) i BB258 [0242] 1 1 [003..00B) (return) i BB259 [0243] 1 1 [00B..01C)-> BB260 (always) i BB260 [0246] 3 1 [038..04E) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 1, # of blocks (including unused BB00): 7, bitset array size: 1 (short) *************** Inline @[001697] Finishing PHASE Post-import Trees after Post-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB257 [0241] 1 1 [000..003)-> BB259 ( cond ) i BB258 [0242] 1 1 [003..00B) (return) i BB259 [0243] 1 1 [00B..01C)-> BB260 (always) i BB260 [0246] 3 1 [038..04E) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB257 [000..003) -> BB259 (cond), preds={} succs={BB258,BB259} ***** BB257 STMT00353 ( 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB258 [003..00B) (return), preds={} succs={} ***** BB258 STMT00357 ( 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct V85 tmp45 [001725] ----------- \--* CNS_INT int 0 ------------ BB259 [00B..01C) -> BB260 (always), preds={} succs={BB260} ------------ BB260 [038..04E) (return), preds={} succs={} ***** BB260 STMT00354 ( 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001713] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001712] ----------- arg0 \--* LCL_VAR ref V33 loc29 ***** BB260 STMT00355 ( 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct V85 tmp45 [001714] --C-------- \--* RET_EXPR byref (for [001713]) ***** BB260 STMT00356 ( 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct V85 tmp45 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [001697] ----------- Arguments setup: Inlinee method body:New Basic Block BB261 [0247] created. Convert bbJumpKind of BB258 to BBJ_ALWAYS to bottomBlock BB261 Convert bbJumpKind of BB260 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB257 [0241] 1 1 [391..392)-> BB259 ( cond ) i bwd BB258 [0242] 1 1 [391..392)-> BB261 (always) i bwd BB259 [0243] 1 1 [391..392)-> BB260 (always) i bwd BB260 [0246] 3 1 [391..392) i idxlen bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB257 [391..392) -> BB259 (cond), preds={} succs={BB258,BB259} ***** BB257 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB258 [391..392) -> BB261 (always), preds={} succs={BB261} ***** BB258 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct V85 tmp45 [001725] ----------- \--* CNS_INT int 0 ------------ BB259 [391..392) -> BB260 (always), preds={} succs={BB260} ------------ BB260 [391..392), preds={} succs={BB261} ***** BB260 STMT00354 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001713] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001712] ----------- arg0 \--* LCL_VAR ref V33 loc29 ***** BB260 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct V85 tmp45 [001714] --C-------- \--* RET_EXPR byref (for [001713]) ***** BB260 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct V85 tmp45 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Span`1[int]:.ctor(int[]):this (78 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[int]:.ctor(int[]):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00354 in BB260: STMT00354 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001713] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (exactContextHnd=0x4000000000421960) [001712] ----------- arg0 \--* LCL_VAR ref V33 loc29 Argument #0: is a local var [001712] ----------- * LCL_VAR ref V33 loc29 INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref set to 0x4000000000421960: Invoking compiler for the inlinee method System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref : IL to import: IL_0000 02 ldarg.0 IL_0001 7c 01 00 00 0a ldflda 0xA000001 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref is 0x4000000000421960. *************** In compInitDebuggingInfo() for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref Jump targets: none New Basic Block BB262 [0248] created. BB262 [000..007) Basic block list for 'System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB262 [0248] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001713] Starting PHASE Pre-import *************** Inline @[001713] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB262 [0248] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB262 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001713] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001713] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB262 [0248] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB262 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001713] Starting PHASE Importation *************** In impImport() for System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref impImportBlockPending for BB262 Importing BB262 (PC=000) of 'System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldflda 0A000001 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001728] ---XG------ * FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 Inlinee Return expression (after normalization) => [001728] ---XG------ * FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001713] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB262 [0248] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB262 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001713] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001713] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001713] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001713] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001713] Starting PHASE Post-import *************** Inline @[001713] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001713] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref (7 IL bytes) (depth 3) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [001714] with [001728] [001714] --C-------- * RET_EXPR byref (for [001713]) -> [001728] Inserting the inline return expression [001728] ---XG------ * FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 Replacing the return expression placeholder [001084] with [001698] [001084] --C-------- * RET_EXPR struct(for [001083]) -> [001698] Inserting the inline return expression [001698] ----------- * LCL_VAR struct V85 tmp45 Expanding INLINE_CANDIDATE in statement STMT00200 in BB100: STMT00200 ( 0x3DC[E-] ... 0x3E3 ) [000938] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this (exactContextHnd=0x4000000000424641) [000937] ----------- this \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000937] ----------- * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this set to 0x4000000000424641: Invoking compiler for the inlinee method System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 09 00 04 ldfld 0x4000931 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this is 0x4000000000424641. *************** In compInitDebuggingInfo() for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this Jump targets: none New Basic Block BB263 [0249] created. BB263 [000..007) Basic block list for 'System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB263 [0249] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000938] Starting PHASE Pre-import *************** Inline @[000938] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB263 [0249] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB263 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000938] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000938] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB263 [0249] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB263 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000938] Starting PHASE Importation *************** In impImport() for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this impImportBlockPending for BB263 Importing BB263 (PC=000) of 'System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000931 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001730] ---XG------ * FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [001730] ---XG------ * FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000938] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB263 [0249] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB263 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000938] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000938] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000938] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000938] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000938] Starting PHASE Post-import *************** Inline @[000938] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000938] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000939] with [001730] [000939] --C-------- * RET_EXPR ref (for [000938]) -> [001730] Inserting the inline return expression [001730] ---XG------ * FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 Expanding INLINE_CANDIDATE in statement STMT00201 in BB100: STMT00201 ( 0x3DC[E-] ... ??? ) [000940] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000936] ----------- this +--* LCL_VAR byref V00 arg0 [001730] ---XG------ arg1 \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000936] ----------- * LCL_VAR byref V00 arg0 Querying runtime about current class of field : (declared as System.String) Field's current class not available Argument #1: has global refs has side effects [001730] ---XG------ * FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(System.String):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 01 brtrue.s 1 (IL_0004) IL_0003 2a ret IL_0004 02 ldarg.0 IL_0005 7b 27 0f 00 04 ldfld 0x4000F27 IL_000a 0a stloc.0 IL_000b 03 ldarg.1 IL_000c 6f 18 08 00 06 callvirt 0x6000818 IL_0011 17 ldc.i4.1 IL_0012 33 2c bne.un.s 44 (IL_0040) IL_0014 06 ldloc.0 IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 28 0a 00 00 0a call 0xA00000A IL_0020 34 1e bge.un.s 30 (IL_0040) IL_0022 02 ldarg.0 IL_0023 7c 26 0f 00 04 ldflda 0x4000F26 IL_0028 06 ldloc.0 IL_0029 28 0b 00 00 0a call 0xA00000B IL_002e 03 ldarg.1 IL_002f 16 ldc.i4.0 IL_0030 6f 17 08 00 06 callvirt 0x6000817 IL_0035 53 stind.i2 IL_0036 02 ldarg.0 IL_0037 06 ldloc.0 IL_0038 17 ldc.i4.1 IL_0039 58 add IL_003a 7d 27 0f 00 04 stfld 0x4000F27 IL_003f 2a ret IL_0040 02 ldarg.0 IL_0041 03 ldarg.1 IL_0042 28 60 3e 00 06 call 0x6003E60 IL_0047 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(System.String):this Jump targets: IL_0004 IL_0040 New Basic Block BB264 [0250] created. BB264 [000..003) New Basic Block BB265 [0251] created. BB265 [003..004) New Basic Block BB266 [0252] created. BB266 [004..014) New Basic Block BB267 [0253] created. BB267 [014..022) New Basic Block BB268 [0254] created. BB268 [022..040) New Basic Block BB269 [0255] created. BB269 [040..048) Basic block list for 'System.Text.ValueStringBuilder:Append(System.String):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB264 [0250] 1 1 [000..003)-> BB266 ( cond ) BB265 [0251] 1 1 [003..004) (return) BB266 [0252] 1 1 [004..014)-> BB269 ( cond ) BB267 [0253] 1 1 [014..022)-> BB269 ( cond ) BB268 [0254] 1 1 [022..040) (return) BB269 [0255] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000940] Starting PHASE Pre-import *************** Inline @[000940] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB264 [0250] 1 1 [000..003)-> BB266 ( cond ) BB265 [0251] 1 1 [003..004) (return) BB266 [0252] 1 1 [004..014)-> BB269 ( cond ) BB267 [0253] 1 1 [014..022)-> BB269 ( cond ) BB268 [0254] 1 1 [022..040) (return) BB269 [0255] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB264 [000..003) -> BB266 (cond), preds={} succs={BB265,BB266} ------------ BB265 [003..004) (return), preds={} succs={} ------------ BB266 [004..014) -> BB269 (cond), preds={} succs={BB267,BB269} ------------ BB267 [014..022) -> BB269 (cond), preds={} succs={BB268,BB269} ------------ BB268 [022..040) (return), preds={} succs={} ------------ BB269 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000940] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000940] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB264 [0250] 1 1 [000..003)-> BB266 ( cond ) BB265 [0251] 1 1 [003..004) (return) BB266 [0252] 1 1 [004..014)-> BB269 ( cond ) BB267 [0253] 1 1 [014..022)-> BB269 ( cond ) BB268 [0254] 1 1 [022..040) (return) BB269 [0255] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB264 [000..003) -> BB266 (cond), preds={} succs={BB265,BB266} ------------ BB265 [003..004) (return), preds={} succs={} ------------ BB266 [004..014) -> BB269 (cond), preds={} succs={BB267,BB269} ------------ BB267 [014..022) -> BB269 (cond), preds={} succs={BB268,BB269} ------------ BB268 [022..040) (return), preds={} succs={} ------------ BB269 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000940] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(System.String):this impImportBlockPending for BB264 Importing BB264 (PC=000) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 86 (V86 tmp46) called for Inlining Arg. Marked V86 as a single def temp Querying runtime about current class of field : (declared as System.String) Field's current class not available lvaSetClass: setting class for V86 to (4000000000420010) System.String [ 1] 1 (0x001) brtrue.s STMT00358 ( 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* NE int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null impImportBlockPending for BB265 impImportBlockPending for BB266 Importing BB266 (PC=004) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 4 (0x004) ldarg.0 [ 1] 5 (0x005) ldfld 04000F27 [ 1] 10 (0x00a) stloc.0 lvaGrabTemp returning 87 (V87 tmp47) (a long lifetime temp) called for Inline stloc first use temp. STMT00359 ( 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 this [ 0] 11 (0x00b) ldarg.1 [ 1] 12 (0x00c) callvirt 06000818 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.String.get_Length: Recognized [ 1] 17 (0x011) ldc.i4.1 1 [ 2] 18 (0x012) bne.un.s STMT00360 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 impImportBlockPending for BB267 impImportBlockPending for BB269 Importing BB269 (PC=064) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 64 (0x040) ldarg.0 [ 1] 65 (0x041) ldarg.1 [ 2] 66 (0x042) call 06003E60 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00361 ( 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001744] ----------- this +--* LCL_VAR byref V00 this [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 [ 0] 71 (0x047) ret Importing BB267 (PC=020) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 20 (0x014) ldloc.0 [ 1] 21 (0x015) ldarg.0 [ 2] 22 (0x016) ldflda 04000F26 [ 2] 27 (0x01b) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00362 ( 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001750] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001749] ---XG------ this \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 this [ 2] 32 (0x020) bge.un.s STMT00363 ( 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001751] --C-------- \--* RET_EXPR int (for [001750]) impImportBlockPending for BB268 impImportBlockPending for BB269 Importing BB268 (PC=034) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 34 (0x022) ldarg.0 [ 1] 35 (0x023) ldflda 04000F26 [ 1] 40 (0x028) ldloc.0 [ 2] 41 (0x029) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [001755] ---XG------ * FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 this and index [001756] ----------- * LCL_VAR int V87 tmp47 lvaGrabTemp returning 88 (V88 tmp48) called for Span.get_Item ptrToSpan. STMT00364 ( 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 this [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) ldc.i4.0 0 [ 3] 48 (0x030) callvirt 06000817 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ushort, structSize is 0 Named Intrinsic System.String.get_Chars: Recognized [ 2] 53 (0x035) stind.i2 STMT00365 ( ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 [ 0] 54 (0x036) ldarg.0 [ 1] 55 (0x037) ldloc.0 [ 2] 56 (0x038) ldc.i4.1 1 [ 3] 57 (0x039) add [ 2] 58 (0x03a) stfld 04000F27 STMT00366 ( 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 this [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 [ 0] 63 (0x03f) ret Importing BB265 (PC=003) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 3 (0x003) ret ** Note: inlinee IL was partially imported -- imported 71 of 72 bytes of method IL *************** Inline @[000940] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB264 [0250] 1 1 [000..003)-> BB266 ( cond ) i BB265 [0251] 1 1 [003..004) (return) i BB266 [0252] 1 1 [004..014)-> BB269 ( cond ) i idxlen BB267 [0253] 1 1 [014..022)-> BB269 ( cond ) i BB268 [0254] 1 1 [022..040) (return) i BB269 [0255] 2 1 [040..048) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB264 [000..003) -> BB266 (cond), preds={} succs={BB265,BB266} ***** BB264 STMT00358 ( 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* NE int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB265 [003..004) (return), preds={} succs={} ------------ BB266 [004..014) -> BB269 (cond), preds={} succs={BB267,BB269} ***** BB266 STMT00359 ( 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 this ***** BB266 STMT00360 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB267 [014..022) -> BB269 (cond), preds={} succs={BB268,BB269} ***** BB267 STMT00362 ( 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001750] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001749] ---XG------ this \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 this ***** BB267 STMT00363 ( 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001751] --C-------- \--* RET_EXPR int (for [001750]) ------------ BB268 [022..040) (return), preds={} succs={} ***** BB268 STMT00364 ( 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 this ***** BB268 STMT00365 ( ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB268 STMT00366 ( 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 this [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB269 [040..048) (return), preds={} succs={} ***** BB269 STMT00361 ( 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001744] ----------- this +--* LCL_VAR byref V00 this [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000940] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000940] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000940] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000940] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000940] Starting PHASE Post-import *************** Inline @[000940] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000940] ----------- Arguments setup: STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 Inlinee method body:New Basic Block BB270 [0256] created. Convert bbJumpKind of BB265 to BBJ_ALWAYS to bottomBlock BB270 Convert bbJumpKind of BB268 to BBJ_ALWAYS to bottomBlock BB270 Convert bbJumpKind of BB269 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB264 [0250] 1 1 [3DC..3DD)-> BB266 ( cond ) i BB265 [0251] 1 1 [3DC..3DD)-> BB270 (always) i BB266 [0252] 1 1 [3DC..3DD)-> BB269 ( cond ) i idxlen BB267 [0253] 1 1 [3DC..3DD)-> BB269 ( cond ) i BB268 [0254] 1 1 [3DC..3DD)-> BB270 (always) i BB269 [0255] 2 1 [3DC..3DD) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB264 [3DC..3DD) -> BB266 (cond), preds={} succs={BB265,BB266} ***** BB264 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* NE int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB265 [3DC..3DD) -> BB270 (always), preds={} succs={BB270} ------------ BB266 [3DC..3DD) -> BB269 (cond), preds={} succs={BB267,BB269} ***** BB266 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 ***** BB266 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB267 [3DC..3DD) -> BB269 (cond), preds={} succs={BB268,BB269} ***** BB267 STMT00362 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001750] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001749] ---XG------ this \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 ***** BB267 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001751] --C-------- \--* RET_EXPR int (for [001750]) ------------ BB268 [3DC..3DD) -> BB270 (always), preds={} succs={BB270} ***** BB268 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 ***** BB268 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB268 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB269 [3DC..3DD), preds={} succs={BB270} ***** BB269 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(System.String):this (72 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Querying runtime about current class of field : (declared as System.String) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00362 in BB267: STMT00362 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001750] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001749] ---XG------ this \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [001749] ---XG------ * FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB271 [0257] created. BB271 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB271 [0257] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001750] Starting PHASE Pre-import *************** Inline @[001750] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB271 [0257] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB271 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001750] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001750] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB271 [0257] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB271 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001750] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB271 Importing BB271 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 89 (V89 tmp49) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001786] ---XG------ * FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 Inlinee Return expression (after normalization) => [001786] ---XG------ * FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001750] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB271 [0257] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB271 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001750] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001750] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001750] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001750] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001750] Starting PHASE Post-import *************** Inline @[001750] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001750] ----------- Arguments setup: STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001751] with [001786] [001751] --C-------- * RET_EXPR int (for [001750]) -> [001786] Inserting the inline return expression [001786] ---XG------ * FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 Expanding INLINE_CANDIDATE in statement STMT00361 in BB269: STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 thisArg: is a local var [001744] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [001745] ----------- * LCL_VAR ref V86 tmp46 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:AppendSlow(System.String):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 03 ldarg.1 IL_0014 6f 18 08 00 06 callvirt 0x6000818 IL_0019 59 sub IL_001a 31 0c ble.s 12 (IL_0028) IL_001c 02 ldarg.0 IL_001d 03 ldarg.1 IL_001e 6f 18 08 00 06 callvirt 0x6000818 IL_0023 28 66 3e 00 06 call 0x6003E66 IL_0028 03 ldarg.1 IL_0029 02 ldarg.0 IL_002a 7c 26 0f 00 04 ldflda 0x4000F26 IL_002f 06 ldloc.0 IL_0030 28 c0 00 00 0a call 0xA0000C0 IL_0035 6f ee 07 00 06 callvirt 0x60007EE IL_003a 02 ldarg.0 IL_003b 02 ldarg.0 IL_003c 7b 27 0f 00 04 ldfld 0x4000F27 IL_0041 03 ldarg.1 IL_0042 6f 18 08 00 06 callvirt 0x6000818 IL_0047 58 add IL_0048 7d 27 0f 00 04 stfld 0x4000F27 IL_004d 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:AppendSlow(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:AppendSlow(System.String):this weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-15 : state 77 [ sub ] weight= 53 : state 49 [ ble.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 83 : state 99 [ callvirt ] weight= 10 : state 3 [ ldarg.0 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-12 : state 76 [ add ] weight= 31 : state 111 [ stfld ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=877 callsiteNativeSizeEstimate=115 benefit multiplier=1.3 threshold=149 Native estimate for function size exceeds threshold for inlining 87.7 > 14.9 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00049 in BB101: STMT00049 ( 0x3EB[E-] ... 0x3F1 ) [000191] I-C-G------ * CALL r2r_ind byref System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref (exactContextHnd=0x4000000000428710) [000193] n---------- arg0 \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 Argument #0: has caller local ref [000193] n---------- * OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref set to 0x4000000000428710: Invoking compiler for the inlinee method System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref : IL to import: IL_0000 0f 00 ldarga.s 0x0 IL_0002 7b 90 11 00 0a ldfld 0xA001190 IL_0007 2a ret INLINER impTokenLookupContextHandle for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref is 0x4000000000428710. *************** In compInitDebuggingInfo() for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref Jump targets: none New Basic Block BB272 [0258] created. BB272 [000..008) Basic block list for 'System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB272 [0258] 1 1 [000..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000191] Starting PHASE Pre-import *************** Inline @[000191] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB272 [0258] 1 1 [000..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB272 [000..008) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000191] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000191] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB272 [0258] 1 1 [000..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB272 [000..008) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000191] Starting PHASE Importation *************** In impImport() for System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref impImportBlockPending for BB272 Importing BB272 (PC=000) of 'System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref' [ 0] 0 (0x000) ldarga.s 0 lvaGrabTemp returning 90 (V90 tmp50) called for Inlining Arg. [ 1] 2 (0x002) ldfld 0A001190 [ 1] 7 (0x007) ret Inlinee Return expression (before normalization) => [001792] ----------- * FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct V90 tmp50 Inlinee Return expression (after normalization) => [001792] ----------- * FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct V90 tmp50 ** Note: inlinee IL was partially imported -- imported 0 of 8 bytes of method IL *************** Inline @[000191] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB272 [0258] 1 1 [000..008) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB272 [000..008) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000191] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000191] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000191] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000191] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000191] Starting PHASE Post-import *************** Inline @[000191] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000191] ----------- Arguments setup: STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct V90 tmp50 [000193] n---------- \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref (8 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000194] with [001792] [000194] --C-------- * RET_EXPR byref (for [000191]) -> [001792] Inserting the inline return expression [001792] ----------- * FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct V90 tmp50 Expanding INLINE_CANDIDATE in statement STMT00184 in BB110: STMT00184 ( ??? ... 0x433 ) [000859] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000857] ----------- this +--* LCL_VAR byref V62 tmp22 [000858] ----------- arg1 \--* LCL_VAR int V63 tmp23 thisArg: is a local var [000857] ----------- * LCL_VAR byref V62 tmp22 Argument #1: is a local var [000858] ----------- * LCL_VAR int V63 tmp23 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB273 [0259] created. BB273 [000..015) New Basic Block BB274 [0260] created. BB274 [015..02D) New Basic Block BB275 [0261] created. BB275 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB273 [0259] 1 1 [000..015)-> BB275 ( cond ) BB274 [0260] 1 1 [015..02D) (return) BB275 [0261] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000859] Starting PHASE Pre-import *************** Inline @[000859] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB273 [0259] 1 1 [000..015)-> BB275 ( cond ) BB274 [0260] 1 1 [015..02D) (return) BB275 [0261] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB273 [000..015) -> BB275 (cond), preds={} succs={BB274,BB275} ------------ BB274 [015..02D) (return), preds={} succs={} ------------ BB275 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000859] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000859] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB273 [0259] 1 1 [000..015)-> BB275 ( cond ) BB274 [0260] 1 1 [015..02D) (return) BB275 [0261] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB273 [000..015) -> BB275 (cond), preds={} succs={BB274,BB275} ------------ BB274 [015..02D) (return), preds={} succs={} ------------ BB275 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000859] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB273 Importing BB273 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 91 (V91 tmp51) (a long lifetime temp) called for Inline stloc first use temp. STMT00370 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00371 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [001803] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001802] ---XG------ this \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 [ 2] 19 (0x013) bge.un.s STMT00372 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001804] --C-------- \--* RET_EXPR int (for [001803]) impImportBlockPending for BB274 impImportBlockPending for BB275 Importing BB275 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 lvaGrabTemp returning 92 (V92 tmp52) called for Inlining Arg. [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00373 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 [ 0] 52 (0x034) ret Importing BB274 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [001811] ---XG------ * FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 and index [001812] ----------- * LCL_VAR int V91 tmp51 lvaGrabTemp returning 93 (V93 tmp53) called for Span.get_Item ptrToSpan. STMT00374 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00375 ( ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00376 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000859] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB273 [0259] 1 1 [000..015)-> BB275 ( cond ) i BB274 [0260] 1 1 [015..02D) (return) i BB275 [0261] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB273 [000..015) -> BB275 (cond), preds={} succs={BB274,BB275} ***** BB273 STMT00370 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB273 STMT00371 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [001803] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001802] ---XG------ this \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB273 STMT00372 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001804] --C-------- \--* RET_EXPR int (for [001803]) ------------ BB274 [015..02D) (return), preds={} succs={} ***** BB274 STMT00374 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB274 STMT00375 ( ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB274 STMT00376 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB275 [02D..035) (return), preds={} succs={} ***** BB275 STMT00373 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000859] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000859] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000859] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000859] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000859] Starting PHASE Post-import *************** Inline @[000859] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000859] ----------- Arguments setup: STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 Inlinee method body:New Basic Block BB276 [0262] created. Convert bbJumpKind of BB274 to BBJ_ALWAYS to bottomBlock BB276 Convert bbJumpKind of BB275 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB273 [0259] 1 1 [000..000)-> BB275 ( cond ) i internal bwd BB274 [0260] 1 1 [000..000)-> BB276 (always) i internal bwd BB275 [0261] 1 1 [000..000) i internal bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB273 [000..000) -> BB275 (cond), preds={} succs={BB274,BB275} ***** BB273 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB273 STMT00371 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001803] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001802] ---XG------ this \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB273 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001804] --C-------- \--* RET_EXPR int (for [001803]) ------------ BB274 [000..000) -> BB276 (always), preds={} succs={BB276} ***** BB274 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB274 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB274 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB275 [000..000), preds={} succs={BB276} ***** BB275 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00371 in BB273: STMT00371 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001803] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001802] ---XG------ this \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 thisArg: has global refs has side effects [001802] ---XG------ * FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB277 [0263] created. BB277 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB277 [0263] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001803] Starting PHASE Pre-import *************** Inline @[001803] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB277 [0263] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB277 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001803] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001803] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB277 [0263] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB277 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001803] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB277 Importing BB277 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 94 (V94 tmp54) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001839] ---XG------ * FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 Inlinee Return expression (after normalization) => [001839] ---XG------ * FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001803] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB277 [0263] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB277 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001803] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001803] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001803] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001803] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001803] Starting PHASE Post-import *************** Inline @[001803] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001803] ----------- Arguments setup: STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001804] with [001839] [001804] --C-------- * RET_EXPR int (for [001803]) -> [001839] Inserting the inline return expression [001839] ---XG------ * FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00191 in BB114: STMT00191 ( 0x44F[E-] ... 0x45F ) [000904] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000903] ----------- this \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000903] ----------- * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this set to 0x4000000000424641: Invoking compiler for the inlinee method System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 09 00 04 ldfld 0x4000933 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this is 0x4000000000424641. *************** In compInitDebuggingInfo() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this Jump targets: none New Basic Block BB278 [0264] created. BB278 [000..007) Basic block list for 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB278 [0264] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000904] Starting PHASE Pre-import *************** Inline @[000904] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB278 [0264] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB278 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000904] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000904] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB278 [0264] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB278 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000904] Starting PHASE Importation *************** In impImport() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this impImportBlockPending for BB278 Importing BB278 (PC=000) of 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000933 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001843] ---XG------ * FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [001843] ---XG------ * FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000904] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB278 [0264] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB278 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000904] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000904] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000904] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000904] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000904] Starting PHASE Post-import *************** Inline @[000904] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000904] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000905] with [001843] [000905] --C-------- * RET_EXPR ref (for [000904]) -> [001843] Inserting the inline return expression [001843] ---XG------ * FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 Expanding INLINE_CANDIDATE in statement STMT00192 in BB114: STMT00192 ( 0x44F[E-] ... ??? ) [000906] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000902] ----------- this +--* LCL_VAR byref V00 arg0 [001843] ---XG------ arg1 \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000902] ----------- * LCL_VAR byref V00 arg0 Querying runtime about current class of field : (declared as System.String) Field's current class not available Argument #1: has global refs has side effects [001843] ---XG------ * FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(System.String):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 01 brtrue.s 1 (IL_0004) IL_0003 2a ret IL_0004 02 ldarg.0 IL_0005 7b 27 0f 00 04 ldfld 0x4000F27 IL_000a 0a stloc.0 IL_000b 03 ldarg.1 IL_000c 6f 18 08 00 06 callvirt 0x6000818 IL_0011 17 ldc.i4.1 IL_0012 33 2c bne.un.s 44 (IL_0040) IL_0014 06 ldloc.0 IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 28 0a 00 00 0a call 0xA00000A IL_0020 34 1e bge.un.s 30 (IL_0040) IL_0022 02 ldarg.0 IL_0023 7c 26 0f 00 04 ldflda 0x4000F26 IL_0028 06 ldloc.0 IL_0029 28 0b 00 00 0a call 0xA00000B IL_002e 03 ldarg.1 IL_002f 16 ldc.i4.0 IL_0030 6f 17 08 00 06 callvirt 0x6000817 IL_0035 53 stind.i2 IL_0036 02 ldarg.0 IL_0037 06 ldloc.0 IL_0038 17 ldc.i4.1 IL_0039 58 add IL_003a 7d 27 0f 00 04 stfld 0x4000F27 IL_003f 2a ret IL_0040 02 ldarg.0 IL_0041 03 ldarg.1 IL_0042 28 60 3e 00 06 call 0x6003E60 IL_0047 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(System.String):this Jump targets: IL_0004 IL_0040 New Basic Block BB279 [0265] created. BB279 [000..003) New Basic Block BB280 [0266] created. BB280 [003..004) New Basic Block BB281 [0267] created. BB281 [004..014) New Basic Block BB282 [0268] created. BB282 [014..022) New Basic Block BB283 [0269] created. BB283 [022..040) New Basic Block BB284 [0270] created. BB284 [040..048) Basic block list for 'System.Text.ValueStringBuilder:Append(System.String):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB279 [0265] 1 1 [000..003)-> BB281 ( cond ) BB280 [0266] 1 1 [003..004) (return) BB281 [0267] 1 1 [004..014)-> BB284 ( cond ) BB282 [0268] 1 1 [014..022)-> BB284 ( cond ) BB283 [0269] 1 1 [022..040) (return) BB284 [0270] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000906] Starting PHASE Pre-import *************** Inline @[000906] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB279 [0265] 1 1 [000..003)-> BB281 ( cond ) BB280 [0266] 1 1 [003..004) (return) BB281 [0267] 1 1 [004..014)-> BB284 ( cond ) BB282 [0268] 1 1 [014..022)-> BB284 ( cond ) BB283 [0269] 1 1 [022..040) (return) BB284 [0270] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB279 [000..003) -> BB281 (cond), preds={} succs={BB280,BB281} ------------ BB280 [003..004) (return), preds={} succs={} ------------ BB281 [004..014) -> BB284 (cond), preds={} succs={BB282,BB284} ------------ BB282 [014..022) -> BB284 (cond), preds={} succs={BB283,BB284} ------------ BB283 [022..040) (return), preds={} succs={} ------------ BB284 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000906] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000906] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB279 [0265] 1 1 [000..003)-> BB281 ( cond ) BB280 [0266] 1 1 [003..004) (return) BB281 [0267] 1 1 [004..014)-> BB284 ( cond ) BB282 [0268] 1 1 [014..022)-> BB284 ( cond ) BB283 [0269] 1 1 [022..040) (return) BB284 [0270] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB279 [000..003) -> BB281 (cond), preds={} succs={BB280,BB281} ------------ BB280 [003..004) (return), preds={} succs={} ------------ BB281 [004..014) -> BB284 (cond), preds={} succs={BB282,BB284} ------------ BB282 [014..022) -> BB284 (cond), preds={} succs={BB283,BB284} ------------ BB283 [022..040) (return), preds={} succs={} ------------ BB284 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000906] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(System.String):this impImportBlockPending for BB279 Importing BB279 (PC=000) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 95 (V95 tmp55) called for Inlining Arg. Marked V95 as a single def temp Querying runtime about current class of field : (declared as System.String) Field's current class not available lvaSetClass: setting class for V95 to (4000000000420010) System.String [ 1] 1 (0x001) brtrue.s STMT00379 ( 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* NE int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null impImportBlockPending for BB280 impImportBlockPending for BB281 Importing BB281 (PC=004) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 4 (0x004) ldarg.0 [ 1] 5 (0x005) ldfld 04000F27 [ 1] 10 (0x00a) stloc.0 lvaGrabTemp returning 96 (V96 tmp56) (a long lifetime temp) called for Inline stloc first use temp. STMT00380 ( 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 this [ 0] 11 (0x00b) ldarg.1 [ 1] 12 (0x00c) callvirt 06000818 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.String.get_Length: Recognized [ 1] 17 (0x011) ldc.i4.1 1 [ 2] 18 (0x012) bne.un.s STMT00381 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 impImportBlockPending for BB282 impImportBlockPending for BB284 Importing BB284 (PC=064) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 64 (0x040) ldarg.0 [ 1] 65 (0x041) ldarg.1 [ 2] 66 (0x042) call 06003E60 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00382 ( 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001857] ----------- this +--* LCL_VAR byref V00 this [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 [ 0] 71 (0x047) ret Importing BB282 (PC=020) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 20 (0x014) ldloc.0 [ 1] 21 (0x015) ldarg.0 [ 2] 22 (0x016) ldflda 04000F26 [ 2] 27 (0x01b) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00383 ( 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001863] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001862] ---XG------ this \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 this [ 2] 32 (0x020) bge.un.s STMT00384 ( 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001864] --C-------- \--* RET_EXPR int (for [001863]) impImportBlockPending for BB283 impImportBlockPending for BB284 Importing BB283 (PC=034) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 34 (0x022) ldarg.0 [ 1] 35 (0x023) ldflda 04000F26 [ 1] 40 (0x028) ldloc.0 [ 2] 41 (0x029) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [001868] ---XG------ * FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 this and index [001869] ----------- * LCL_VAR int V96 tmp56 lvaGrabTemp returning 97 (V97 tmp57) called for Span.get_Item ptrToSpan. STMT00385 ( 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 this [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) ldc.i4.0 0 [ 3] 48 (0x030) callvirt 06000817 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ushort, structSize is 0 Named Intrinsic System.String.get_Chars: Recognized [ 2] 53 (0x035) stind.i2 STMT00386 ( ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 [ 0] 54 (0x036) ldarg.0 [ 1] 55 (0x037) ldloc.0 [ 2] 56 (0x038) ldc.i4.1 1 [ 3] 57 (0x039) add [ 2] 58 (0x03a) stfld 04000F27 STMT00387 ( 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 this [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 [ 0] 63 (0x03f) ret Importing BB280 (PC=003) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 3 (0x003) ret ** Note: inlinee IL was partially imported -- imported 71 of 72 bytes of method IL *************** Inline @[000906] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB279 [0265] 1 1 [000..003)-> BB281 ( cond ) i BB280 [0266] 1 1 [003..004) (return) i BB281 [0267] 1 1 [004..014)-> BB284 ( cond ) i idxlen BB282 [0268] 1 1 [014..022)-> BB284 ( cond ) i BB283 [0269] 1 1 [022..040) (return) i BB284 [0270] 2 1 [040..048) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB279 [000..003) -> BB281 (cond), preds={} succs={BB280,BB281} ***** BB279 STMT00379 ( 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* NE int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB280 [003..004) (return), preds={} succs={} ------------ BB281 [004..014) -> BB284 (cond), preds={} succs={BB282,BB284} ***** BB281 STMT00380 ( 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 this ***** BB281 STMT00381 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB282 [014..022) -> BB284 (cond), preds={} succs={BB283,BB284} ***** BB282 STMT00383 ( 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001863] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001862] ---XG------ this \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 this ***** BB282 STMT00384 ( 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001864] --C-------- \--* RET_EXPR int (for [001863]) ------------ BB283 [022..040) (return), preds={} succs={} ***** BB283 STMT00385 ( 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 this ***** BB283 STMT00386 ( ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB283 STMT00387 ( 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 this [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB284 [040..048) (return), preds={} succs={} ***** BB284 STMT00382 ( 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001857] ----------- this +--* LCL_VAR byref V00 this [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000906] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000906] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000906] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000906] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000906] Starting PHASE Post-import *************** Inline @[000906] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000906] ----------- Arguments setup: STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 Inlinee method body:New Basic Block BB285 [0271] created. Convert bbJumpKind of BB280 to BBJ_ALWAYS to bottomBlock BB285 Convert bbJumpKind of BB283 to BBJ_ALWAYS to bottomBlock BB285 Convert bbJumpKind of BB284 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB279 [0265] 1 1 [44F..450)-> BB281 ( cond ) i bwd BB280 [0266] 1 1 [44F..450)-> BB285 (always) i bwd BB281 [0267] 1 1 [44F..450)-> BB284 ( cond ) i idxlen bwd BB282 [0268] 1 1 [44F..450)-> BB284 ( cond ) i bwd BB283 [0269] 1 1 [44F..450)-> BB285 (always) i bwd BB284 [0270] 2 1 [44F..450) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB279 [44F..450) -> BB281 (cond), preds={} succs={BB280,BB281} ***** BB279 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* NE int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB280 [44F..450) -> BB285 (always), preds={} succs={BB285} ------------ BB281 [44F..450) -> BB284 (cond), preds={} succs={BB282,BB284} ***** BB281 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 ***** BB281 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB282 [44F..450) -> BB284 (cond), preds={} succs={BB283,BB284} ***** BB282 STMT00383 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001863] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001862] ---XG------ this \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 ***** BB282 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001864] --C-------- \--* RET_EXPR int (for [001863]) ------------ BB283 [44F..450) -> BB285 (always), preds={} succs={BB285} ***** BB283 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB283 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB284 [44F..450), preds={} succs={BB285} ***** BB284 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(System.String):this (72 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Querying runtime about current class of field : (declared as System.String) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00383 in BB282: STMT00383 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001863] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001862] ---XG------ this \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [001862] ---XG------ * FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB286 [0272] created. BB286 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB286 [0272] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001863] Starting PHASE Pre-import *************** Inline @[001863] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB286 [0272] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB286 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001863] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001863] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB286 [0272] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB286 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001863] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB286 Importing BB286 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 98 (V98 tmp58) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001899] ---XG------ * FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 Inlinee Return expression (after normalization) => [001899] ---XG------ * FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001863] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB286 [0272] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB286 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001863] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001863] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001863] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001863] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001863] Starting PHASE Post-import *************** Inline @[001863] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001863] ----------- Arguments setup: STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001864] with [001899] [001864] --C-------- * RET_EXPR int (for [001863]) -> [001899] Inserting the inline return expression [001899] ---XG------ * FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 Expanding INLINE_CANDIDATE in statement STMT00382 in BB284: STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 thisArg: is a local var [001857] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [001858] ----------- * LCL_VAR ref V95 tmp55 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:AppendSlow(System.String):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 03 ldarg.1 IL_0014 6f 18 08 00 06 callvirt 0x6000818 IL_0019 59 sub IL_001a 31 0c ble.s 12 (IL_0028) IL_001c 02 ldarg.0 IL_001d 03 ldarg.1 IL_001e 6f 18 08 00 06 callvirt 0x6000818 IL_0023 28 66 3e 00 06 call 0x6003E66 IL_0028 03 ldarg.1 IL_0029 02 ldarg.0 IL_002a 7c 26 0f 00 04 ldflda 0x4000F26 IL_002f 06 ldloc.0 IL_0030 28 c0 00 00 0a call 0xA0000C0 IL_0035 6f ee 07 00 06 callvirt 0x60007EE IL_003a 02 ldarg.0 IL_003b 02 ldarg.0 IL_003c 7b 27 0f 00 04 ldfld 0x4000F27 IL_0041 03 ldarg.1 IL_0042 6f 18 08 00 06 callvirt 0x6000818 IL_0047 58 add IL_0048 7d 27 0f 00 04 stfld 0x4000F27 IL_004d 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:AppendSlow(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:AppendSlow(System.String):this weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-15 : state 77 [ sub ] weight= 53 : state 49 [ ble.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 83 : state 99 [ callvirt ] weight= 10 : state 3 [ ldarg.0 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-12 : state 76 [ add ] weight= 31 : state 111 [ stfld ] weight= 19 : state 42 [ ret ] Inline candidate callsite is in a loop. Multiplier increased to 3. calleeNativeSizeEstimate=877 callsiteNativeSizeEstimate=115 benefit multiplier=3 threshold=345 Native estimate for function size exceeds threshold for inlining 87.7 > 34.5 (multiplier = 3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00149 in BB138: STMT00149 ( 0x521[E-] ... 0x52B ) [000676] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000674] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 thisArg: is a local var [000674] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [000675] ----------- * LCL_VAR int V18 loc14 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB287 [0273] created. BB287 [000..015) New Basic Block BB288 [0274] created. BB288 [015..02D) New Basic Block BB289 [0275] created. BB289 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB287 [0273] 1 1 [000..015)-> BB289 ( cond ) BB288 [0274] 1 1 [015..02D) (return) BB289 [0275] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000676] Starting PHASE Pre-import *************** Inline @[000676] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB287 [0273] 1 1 [000..015)-> BB289 ( cond ) BB288 [0274] 1 1 [015..02D) (return) BB289 [0275] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB287 [000..015) -> BB289 (cond), preds={} succs={BB288,BB289} ------------ BB288 [015..02D) (return), preds={} succs={} ------------ BB289 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000676] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000676] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB287 [0273] 1 1 [000..015)-> BB289 ( cond ) BB288 [0274] 1 1 [015..02D) (return) BB289 [0275] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB287 [000..015) -> BB289 (cond), preds={} succs={BB288,BB289} ------------ BB288 [015..02D) (return), preds={} succs={} ------------ BB289 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000676] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB287 Importing BB287 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 99 (V99 tmp59) (a long lifetime temp) called for Inline stloc first use temp. STMT00390 ( 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00391 ( 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001909] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001908] ---XG------ this \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 this [ 2] 19 (0x013) bge.un.s STMT00392 ( 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001910] --C-------- \--* RET_EXPR int (for [001909]) impImportBlockPending for BB288 impImportBlockPending for BB289 Importing BB289 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00393 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 this [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 [ 0] 52 (0x034) ret Importing BB288 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [001916] ---XG------ * FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 this and index [001917] ----------- * LCL_VAR int V99 tmp59 lvaGrabTemp returning 100 (V100 tmp60) called for Span.get_Item ptrToSpan. STMT00394 ( 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 this [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00395 ( ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00396 ( 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 this [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000676] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB287 [0273] 1 1 [000..015)-> BB289 ( cond ) i BB288 [0274] 1 1 [015..02D) (return) i BB289 [0275] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB287 [000..015) -> BB289 (cond), preds={} succs={BB288,BB289} ***** BB287 STMT00390 ( 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 this ***** BB287 STMT00391 ( 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001909] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001908] ---XG------ this \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 this ***** BB287 STMT00392 ( 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001910] --C-------- \--* RET_EXPR int (for [001909]) ------------ BB288 [015..02D) (return), preds={} succs={} ***** BB288 STMT00394 ( 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 this ***** BB288 STMT00395 ( ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB288 STMT00396 ( 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 this [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB289 [02D..035) (return), preds={} succs={} ***** BB289 STMT00393 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 this [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000676] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000676] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000676] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000676] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000676] Starting PHASE Post-import *************** Inline @[000676] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000676] ----------- Arguments setup: Inlinee method body:New Basic Block BB290 [0276] created. Convert bbJumpKind of BB288 to BBJ_ALWAYS to bottomBlock BB290 Convert bbJumpKind of BB289 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB287 [0273] 1 1 [521..522)-> BB289 ( cond ) i bwd BB288 [0274] 1 1 [521..522)-> BB290 (always) i bwd BB289 [0275] 1 1 [521..522) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB287 [521..522) -> BB289 (cond), preds={} succs={BB288,BB289} ***** BB287 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 ***** BB287 STMT00391 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001909] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001908] ---XG------ this \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 ***** BB287 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001910] --C-------- \--* RET_EXPR int (for [001909]) ------------ BB288 [521..522) -> BB290 (always), preds={} succs={BB290} ***** BB288 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 ***** BB288 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB288 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB289 [521..522), preds={} succs={BB290} ***** BB289 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- BB138 becomes empty INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00391 in BB287: STMT00391 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001909] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001908] ---XG------ this \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [001908] ---XG------ * FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB291 [0277] created. BB291 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB291 [0277] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001909] Starting PHASE Pre-import *************** Inline @[001909] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB291 [0277] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB291 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001909] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001909] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB291 [0277] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB291 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001909] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB291 Importing BB291 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 101 (V101 tmp61) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001942] ---XG------ * FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 Inlinee Return expression (after normalization) => [001942] ---XG------ * FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001909] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB291 [0277] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB291 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001909] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001909] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001909] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001909] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001909] Starting PHASE Post-import *************** Inline @[001909] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001909] ----------- Arguments setup: STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001910] with [001942] [001910] --C-------- * RET_EXPR int (for [001909]) -> [001942] Inserting the inline return expression [001942] ---XG------ * FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00154 in BB142: STMT00154 ( 0x547[E-] ... 0x557 ) [000711] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000710] ----------- this \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000710] ----------- * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this set to 0x4000000000424641: Invoking compiler for the inlinee method System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 09 00 04 ldfld 0x4000933 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this is 0x4000000000424641. *************** In compInitDebuggingInfo() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this Jump targets: none New Basic Block BB292 [0278] created. BB292 [000..007) Basic block list for 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB292 [0278] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000711] Starting PHASE Pre-import *************** Inline @[000711] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB292 [0278] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB292 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000711] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000711] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB292 [0278] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB292 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000711] Starting PHASE Importation *************** In impImport() for System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this impImportBlockPending for BB292 Importing BB292 (PC=000) of 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000933 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [001946] ---XG------ * FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [001946] ---XG------ * FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000711] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB292 [0278] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB292 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000711] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000711] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000711] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000711] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000711] Starting PHASE Post-import *************** Inline @[000711] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000711] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000712] with [001946] [000712] --C-------- * RET_EXPR ref (for [000711]) -> [001946] Inserting the inline return expression [001946] ---XG------ * FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 Expanding INLINE_CANDIDATE in statement STMT00155 in BB142: STMT00155 ( 0x547[E-] ... ??? ) [000713] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000709] ----------- this +--* LCL_VAR byref V00 arg0 [001946] ---XG------ arg1 \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000709] ----------- * LCL_VAR byref V00 arg0 Querying runtime about current class of field : (declared as System.String) Field's current class not available Argument #1: has global refs has side effects [001946] ---XG------ * FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(System.String):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 01 brtrue.s 1 (IL_0004) IL_0003 2a ret IL_0004 02 ldarg.0 IL_0005 7b 27 0f 00 04 ldfld 0x4000F27 IL_000a 0a stloc.0 IL_000b 03 ldarg.1 IL_000c 6f 18 08 00 06 callvirt 0x6000818 IL_0011 17 ldc.i4.1 IL_0012 33 2c bne.un.s 44 (IL_0040) IL_0014 06 ldloc.0 IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 28 0a 00 00 0a call 0xA00000A IL_0020 34 1e bge.un.s 30 (IL_0040) IL_0022 02 ldarg.0 IL_0023 7c 26 0f 00 04 ldflda 0x4000F26 IL_0028 06 ldloc.0 IL_0029 28 0b 00 00 0a call 0xA00000B IL_002e 03 ldarg.1 IL_002f 16 ldc.i4.0 IL_0030 6f 17 08 00 06 callvirt 0x6000817 IL_0035 53 stind.i2 IL_0036 02 ldarg.0 IL_0037 06 ldloc.0 IL_0038 17 ldc.i4.1 IL_0039 58 add IL_003a 7d 27 0f 00 04 stfld 0x4000F27 IL_003f 2a ret IL_0040 02 ldarg.0 IL_0041 03 ldarg.1 IL_0042 28 60 3e 00 06 call 0x6003E60 IL_0047 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(System.String):this Jump targets: IL_0004 IL_0040 New Basic Block BB293 [0279] created. BB293 [000..003) New Basic Block BB294 [0280] created. BB294 [003..004) New Basic Block BB295 [0281] created. BB295 [004..014) New Basic Block BB296 [0282] created. BB296 [014..022) New Basic Block BB297 [0283] created. BB297 [022..040) New Basic Block BB298 [0284] created. BB298 [040..048) Basic block list for 'System.Text.ValueStringBuilder:Append(System.String):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB293 [0279] 1 1 [000..003)-> BB295 ( cond ) BB294 [0280] 1 1 [003..004) (return) BB295 [0281] 1 1 [004..014)-> BB298 ( cond ) BB296 [0282] 1 1 [014..022)-> BB298 ( cond ) BB297 [0283] 1 1 [022..040) (return) BB298 [0284] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000713] Starting PHASE Pre-import *************** Inline @[000713] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB293 [0279] 1 1 [000..003)-> BB295 ( cond ) BB294 [0280] 1 1 [003..004) (return) BB295 [0281] 1 1 [004..014)-> BB298 ( cond ) BB296 [0282] 1 1 [014..022)-> BB298 ( cond ) BB297 [0283] 1 1 [022..040) (return) BB298 [0284] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB293 [000..003) -> BB295 (cond), preds={} succs={BB294,BB295} ------------ BB294 [003..004) (return), preds={} succs={} ------------ BB295 [004..014) -> BB298 (cond), preds={} succs={BB296,BB298} ------------ BB296 [014..022) -> BB298 (cond), preds={} succs={BB297,BB298} ------------ BB297 [022..040) (return), preds={} succs={} ------------ BB298 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000713] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000713] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB293 [0279] 1 1 [000..003)-> BB295 ( cond ) BB294 [0280] 1 1 [003..004) (return) BB295 [0281] 1 1 [004..014)-> BB298 ( cond ) BB296 [0282] 1 1 [014..022)-> BB298 ( cond ) BB297 [0283] 1 1 [022..040) (return) BB298 [0284] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB293 [000..003) -> BB295 (cond), preds={} succs={BB294,BB295} ------------ BB294 [003..004) (return), preds={} succs={} ------------ BB295 [004..014) -> BB298 (cond), preds={} succs={BB296,BB298} ------------ BB296 [014..022) -> BB298 (cond), preds={} succs={BB297,BB298} ------------ BB297 [022..040) (return), preds={} succs={} ------------ BB298 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000713] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(System.String):this impImportBlockPending for BB293 Importing BB293 (PC=000) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 102 (V102 tmp62) called for Inlining Arg. Marked V102 as a single def temp Querying runtime about current class of field : (declared as System.String) Field's current class not available lvaSetClass: setting class for V102 to (4000000000420010) System.String [ 1] 1 (0x001) brtrue.s STMT00398 ( 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* NE int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null impImportBlockPending for BB294 impImportBlockPending for BB295 Importing BB295 (PC=004) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 4 (0x004) ldarg.0 [ 1] 5 (0x005) ldfld 04000F27 [ 1] 10 (0x00a) stloc.0 lvaGrabTemp returning 103 (V103 tmp63) (a long lifetime temp) called for Inline stloc first use temp. STMT00399 ( 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 this [ 0] 11 (0x00b) ldarg.1 [ 1] 12 (0x00c) callvirt 06000818 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.String.get_Length: Recognized [ 1] 17 (0x011) ldc.i4.1 1 [ 2] 18 (0x012) bne.un.s STMT00400 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 impImportBlockPending for BB296 impImportBlockPending for BB298 Importing BB298 (PC=064) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 64 (0x040) ldarg.0 [ 1] 65 (0x041) ldarg.1 [ 2] 66 (0x042) call 06003E60 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00401 ( 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001960] ----------- this +--* LCL_VAR byref V00 this [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 [ 0] 71 (0x047) ret Importing BB296 (PC=020) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 20 (0x014) ldloc.0 [ 1] 21 (0x015) ldarg.0 [ 2] 22 (0x016) ldflda 04000F26 [ 2] 27 (0x01b) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00402 ( 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001966] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001965] ---XG------ this \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 this [ 2] 32 (0x020) bge.un.s STMT00403 ( 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [001967] --C-------- \--* RET_EXPR int (for [001966]) impImportBlockPending for BB297 impImportBlockPending for BB298 Importing BB297 (PC=034) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 34 (0x022) ldarg.0 [ 1] 35 (0x023) ldflda 04000F26 [ 1] 40 (0x028) ldloc.0 [ 2] 41 (0x029) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [001971] ---XG------ * FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 this and index [001972] ----------- * LCL_VAR int V103 tmp63 lvaGrabTemp returning 104 (V104 tmp64) called for Span.get_Item ptrToSpan. STMT00404 ( 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 this [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) ldc.i4.0 0 [ 3] 48 (0x030) callvirt 06000817 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ushort, structSize is 0 Named Intrinsic System.String.get_Chars: Recognized [ 2] 53 (0x035) stind.i2 STMT00405 ( ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 [ 0] 54 (0x036) ldarg.0 [ 1] 55 (0x037) ldloc.0 [ 2] 56 (0x038) ldc.i4.1 1 [ 3] 57 (0x039) add [ 2] 58 (0x03a) stfld 04000F27 STMT00406 ( 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 this [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 [ 0] 63 (0x03f) ret Importing BB294 (PC=003) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 3 (0x003) ret ** Note: inlinee IL was partially imported -- imported 71 of 72 bytes of method IL *************** Inline @[000713] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB293 [0279] 1 1 [000..003)-> BB295 ( cond ) i BB294 [0280] 1 1 [003..004) (return) i BB295 [0281] 1 1 [004..014)-> BB298 ( cond ) i idxlen BB296 [0282] 1 1 [014..022)-> BB298 ( cond ) i BB297 [0283] 1 1 [022..040) (return) i BB298 [0284] 2 1 [040..048) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB293 [000..003) -> BB295 (cond), preds={} succs={BB294,BB295} ***** BB293 STMT00398 ( 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* NE int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB294 [003..004) (return), preds={} succs={} ------------ BB295 [004..014) -> BB298 (cond), preds={} succs={BB296,BB298} ***** BB295 STMT00399 ( 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 this ***** BB295 STMT00400 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB296 [014..022) -> BB298 (cond), preds={} succs={BB297,BB298} ***** BB296 STMT00402 ( 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001966] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001965] ---XG------ this \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 this ***** BB296 STMT00403 ( 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [001967] --C-------- \--* RET_EXPR int (for [001966]) ------------ BB297 [022..040) (return), preds={} succs={} ***** BB297 STMT00404 ( 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 this ***** BB297 STMT00405 ( ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB297 STMT00406 ( 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 this [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB298 [040..048) (return), preds={} succs={} ***** BB298 STMT00401 ( 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001960] ----------- this +--* LCL_VAR byref V00 this [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000713] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000713] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000713] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000713] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000713] Starting PHASE Post-import *************** Inline @[000713] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000713] ----------- Arguments setup: STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 Inlinee method body:New Basic Block BB299 [0285] created. Convert bbJumpKind of BB294 to BBJ_ALWAYS to bottomBlock BB299 Convert bbJumpKind of BB297 to BBJ_ALWAYS to bottomBlock BB299 Convert bbJumpKind of BB298 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB293 [0279] 1 1 [547..548)-> BB295 ( cond ) i bwd BB294 [0280] 1 1 [547..548)-> BB299 (always) i bwd BB295 [0281] 1 1 [547..548)-> BB298 ( cond ) i idxlen bwd BB296 [0282] 1 1 [547..548)-> BB298 ( cond ) i bwd BB297 [0283] 1 1 [547..548)-> BB299 (always) i bwd BB298 [0284] 2 1 [547..548) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB293 [547..548) -> BB295 (cond), preds={} succs={BB294,BB295} ***** BB293 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* NE int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB294 [547..548) -> BB299 (always), preds={} succs={BB299} ------------ BB295 [547..548) -> BB298 (cond), preds={} succs={BB296,BB298} ***** BB295 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 ***** BB295 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB296 [547..548) -> BB298 (cond), preds={} succs={BB297,BB298} ***** BB296 STMT00402 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001966] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001965] ---XG------ this \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 ***** BB296 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [001967] --C-------- \--* RET_EXPR int (for [001966]) ------------ BB297 [547..548) -> BB299 (always), preds={} succs={BB299} ***** BB297 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 ***** BB297 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB297 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB298 [547..548), preds={} succs={BB299} ***** BB298 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(System.String):this (72 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Querying runtime about current class of field : (declared as System.String) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00402 in BB296: STMT00402 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001966] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [001965] ---XG------ this \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [001965] ---XG------ * FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB300 [0286] created. BB300 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB300 [0286] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[001966] Starting PHASE Pre-import *************** Inline @[001966] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB300 [0286] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB300 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001966] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[001966] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB300 [0286] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB300 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001966] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB300 Importing BB300 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 105 (V105 tmp65) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002002] ---XG------ * FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 Inlinee Return expression (after normalization) => [002002] ---XG------ * FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[001966] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB300 [0286] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB300 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[001966] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[001966] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[001966] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[001966] Finishing PHASE Indirect call transform [no changes] *************** Inline @[001966] Starting PHASE Post-import *************** Inline @[001966] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [001966] ----------- Arguments setup: STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [001967] with [002002] [001967] --C-------- * RET_EXPR int (for [001966]) -> [002002] Inserting the inline return expression [002002] ---XG------ * FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 Expanding INLINE_CANDIDATE in statement STMT00401 in BB298: STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 thisArg: is a local var [001960] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [001961] ----------- * LCL_VAR ref V102 tmp62 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:AppendSlow(System.String):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 03 ldarg.1 IL_0014 6f 18 08 00 06 callvirt 0x6000818 IL_0019 59 sub IL_001a 31 0c ble.s 12 (IL_0028) IL_001c 02 ldarg.0 IL_001d 03 ldarg.1 IL_001e 6f 18 08 00 06 callvirt 0x6000818 IL_0023 28 66 3e 00 06 call 0x6003E66 IL_0028 03 ldarg.1 IL_0029 02 ldarg.0 IL_002a 7c 26 0f 00 04 ldflda 0x4000F26 IL_002f 06 ldloc.0 IL_0030 28 c0 00 00 0a call 0xA0000C0 IL_0035 6f ee 07 00 06 callvirt 0x60007EE IL_003a 02 ldarg.0 IL_003b 02 ldarg.0 IL_003c 7b 27 0f 00 04 ldfld 0x4000F27 IL_0041 03 ldarg.1 IL_0042 6f 18 08 00 06 callvirt 0x6000818 IL_0047 58 add IL_0048 7d 27 0f 00 04 stfld 0x4000F27 IL_004d 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:AppendSlow(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:AppendSlow(System.String):this weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-15 : state 77 [ sub ] weight= 53 : state 49 [ ble.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 83 : state 99 [ callvirt ] weight= 10 : state 3 [ ldarg.0 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-12 : state 76 [ add ] weight= 31 : state 111 [ stfld ] weight= 19 : state 42 [ ret ] Inline candidate callsite is in a loop. Multiplier increased to 3. calleeNativeSizeEstimate=877 callsiteNativeSizeEstimate=115 benefit multiplier=3 threshold=345 Native estimate for function size exceeds threshold for inlining 87.7 > 34.5 (multiplier = 3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00134 in BB148: STMT00134 ( 0x584[E-] ... 0x591 ) [000619] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this (exactContextHnd=0x4000000000424641) [000618] ----------- this \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000618] ----------- * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this set to 0x4000000000424641: Invoking compiler for the inlinee method System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 32 09 00 04 ldfld 0x4000932 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this is 0x4000000000424641. *************** In compInitDebuggingInfo() for System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this Jump targets: none New Basic Block BB301 [0287] created. BB301 [000..007) Basic block list for 'System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB301 [0287] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000619] Starting PHASE Pre-import *************** Inline @[000619] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB301 [0287] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB301 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000619] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000619] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB301 [0287] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB301 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000619] Starting PHASE Importation *************** In impImport() for System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this impImportBlockPending for BB301 Importing BB301 (PC=000) of 'System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000932 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002006] ---XG------ * FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [002006] ---XG------ * FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000619] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB301 [0287] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB301 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000619] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000619] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000619] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000619] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000619] Starting PHASE Post-import *************** Inline @[000619] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000619] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000620] with [002006] [000620] --C-------- * RET_EXPR ref (for [000619]) -> [002006] Inserting the inline return expression [002006] ---XG------ * FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 Expanding INLINE_CANDIDATE in statement STMT00135 in BB148: STMT00135 ( 0x584[E-] ... ??? ) [000621] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000617] ----------- this +--* LCL_VAR byref V00 arg0 [002006] ---XG------ arg1 \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000617] ----------- * LCL_VAR byref V00 arg0 Querying runtime about current class of field : (declared as System.String) Field's current class not available Argument #1: has global refs has side effects [002006] ---XG------ * FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(System.String):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 01 brtrue.s 1 (IL_0004) IL_0003 2a ret IL_0004 02 ldarg.0 IL_0005 7b 27 0f 00 04 ldfld 0x4000F27 IL_000a 0a stloc.0 IL_000b 03 ldarg.1 IL_000c 6f 18 08 00 06 callvirt 0x6000818 IL_0011 17 ldc.i4.1 IL_0012 33 2c bne.un.s 44 (IL_0040) IL_0014 06 ldloc.0 IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 28 0a 00 00 0a call 0xA00000A IL_0020 34 1e bge.un.s 30 (IL_0040) IL_0022 02 ldarg.0 IL_0023 7c 26 0f 00 04 ldflda 0x4000F26 IL_0028 06 ldloc.0 IL_0029 28 0b 00 00 0a call 0xA00000B IL_002e 03 ldarg.1 IL_002f 16 ldc.i4.0 IL_0030 6f 17 08 00 06 callvirt 0x6000817 IL_0035 53 stind.i2 IL_0036 02 ldarg.0 IL_0037 06 ldloc.0 IL_0038 17 ldc.i4.1 IL_0039 58 add IL_003a 7d 27 0f 00 04 stfld 0x4000F27 IL_003f 2a ret IL_0040 02 ldarg.0 IL_0041 03 ldarg.1 IL_0042 28 60 3e 00 06 call 0x6003E60 IL_0047 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(System.String):this Jump targets: IL_0004 IL_0040 New Basic Block BB302 [0288] created. BB302 [000..003) New Basic Block BB303 [0289] created. BB303 [003..004) New Basic Block BB304 [0290] created. BB304 [004..014) New Basic Block BB305 [0291] created. BB305 [014..022) New Basic Block BB306 [0292] created. BB306 [022..040) New Basic Block BB307 [0293] created. BB307 [040..048) Basic block list for 'System.Text.ValueStringBuilder:Append(System.String):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB302 [0288] 1 1 [000..003)-> BB304 ( cond ) BB303 [0289] 1 1 [003..004) (return) BB304 [0290] 1 1 [004..014)-> BB307 ( cond ) BB305 [0291] 1 1 [014..022)-> BB307 ( cond ) BB306 [0292] 1 1 [022..040) (return) BB307 [0293] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000621] Starting PHASE Pre-import *************** Inline @[000621] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB302 [0288] 1 1 [000..003)-> BB304 ( cond ) BB303 [0289] 1 1 [003..004) (return) BB304 [0290] 1 1 [004..014)-> BB307 ( cond ) BB305 [0291] 1 1 [014..022)-> BB307 ( cond ) BB306 [0292] 1 1 [022..040) (return) BB307 [0293] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB302 [000..003) -> BB304 (cond), preds={} succs={BB303,BB304} ------------ BB303 [003..004) (return), preds={} succs={} ------------ BB304 [004..014) -> BB307 (cond), preds={} succs={BB305,BB307} ------------ BB305 [014..022) -> BB307 (cond), preds={} succs={BB306,BB307} ------------ BB306 [022..040) (return), preds={} succs={} ------------ BB307 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000621] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000621] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB302 [0288] 1 1 [000..003)-> BB304 ( cond ) BB303 [0289] 1 1 [003..004) (return) BB304 [0290] 1 1 [004..014)-> BB307 ( cond ) BB305 [0291] 1 1 [014..022)-> BB307 ( cond ) BB306 [0292] 1 1 [022..040) (return) BB307 [0293] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB302 [000..003) -> BB304 (cond), preds={} succs={BB303,BB304} ------------ BB303 [003..004) (return), preds={} succs={} ------------ BB304 [004..014) -> BB307 (cond), preds={} succs={BB305,BB307} ------------ BB305 [014..022) -> BB307 (cond), preds={} succs={BB306,BB307} ------------ BB306 [022..040) (return), preds={} succs={} ------------ BB307 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000621] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(System.String):this impImportBlockPending for BB302 Importing BB302 (PC=000) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 106 (V106 tmp66) called for Inlining Arg. Marked V106 as a single def temp Querying runtime about current class of field : (declared as System.String) Field's current class not available lvaSetClass: setting class for V106 to (4000000000420010) System.String [ 1] 1 (0x001) brtrue.s STMT00409 ( 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* NE int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null impImportBlockPending for BB303 impImportBlockPending for BB304 Importing BB304 (PC=004) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 4 (0x004) ldarg.0 [ 1] 5 (0x005) ldfld 04000F27 [ 1] 10 (0x00a) stloc.0 lvaGrabTemp returning 107 (V107 tmp67) (a long lifetime temp) called for Inline stloc first use temp. STMT00410 ( 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 this [ 0] 11 (0x00b) ldarg.1 [ 1] 12 (0x00c) callvirt 06000818 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.String.get_Length: Recognized [ 1] 17 (0x011) ldc.i4.1 1 [ 2] 18 (0x012) bne.un.s STMT00411 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 impImportBlockPending for BB305 impImportBlockPending for BB307 Importing BB307 (PC=064) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 64 (0x040) ldarg.0 [ 1] 65 (0x041) ldarg.1 [ 2] 66 (0x042) call 06003E60 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00412 ( 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002020] ----------- this +--* LCL_VAR byref V00 this [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 [ 0] 71 (0x047) ret Importing BB305 (PC=020) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 20 (0x014) ldloc.0 [ 1] 21 (0x015) ldarg.0 [ 2] 22 (0x016) ldflda 04000F26 [ 2] 27 (0x01b) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00413 ( 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002026] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002025] ---XG------ this \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 this [ 2] 32 (0x020) bge.un.s STMT00414 ( 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002027] --C-------- \--* RET_EXPR int (for [002026]) impImportBlockPending for BB306 impImportBlockPending for BB307 Importing BB306 (PC=034) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 34 (0x022) ldarg.0 [ 1] 35 (0x023) ldflda 04000F26 [ 1] 40 (0x028) ldloc.0 [ 2] 41 (0x029) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002031] ---XG------ * FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 this and index [002032] ----------- * LCL_VAR int V107 tmp67 lvaGrabTemp returning 108 (V108 tmp68) called for Span.get_Item ptrToSpan. STMT00415 ( 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 this [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) ldc.i4.0 0 [ 3] 48 (0x030) callvirt 06000817 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ushort, structSize is 0 Named Intrinsic System.String.get_Chars: Recognized [ 2] 53 (0x035) stind.i2 STMT00416 ( ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 [ 0] 54 (0x036) ldarg.0 [ 1] 55 (0x037) ldloc.0 [ 2] 56 (0x038) ldc.i4.1 1 [ 3] 57 (0x039) add [ 2] 58 (0x03a) stfld 04000F27 STMT00417 ( 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 this [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 [ 0] 63 (0x03f) ret Importing BB303 (PC=003) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 3 (0x003) ret ** Note: inlinee IL was partially imported -- imported 71 of 72 bytes of method IL *************** Inline @[000621] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB302 [0288] 1 1 [000..003)-> BB304 ( cond ) i BB303 [0289] 1 1 [003..004) (return) i BB304 [0290] 1 1 [004..014)-> BB307 ( cond ) i idxlen BB305 [0291] 1 1 [014..022)-> BB307 ( cond ) i BB306 [0292] 1 1 [022..040) (return) i BB307 [0293] 2 1 [040..048) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB302 [000..003) -> BB304 (cond), preds={} succs={BB303,BB304} ***** BB302 STMT00409 ( 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* NE int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB303 [003..004) (return), preds={} succs={} ------------ BB304 [004..014) -> BB307 (cond), preds={} succs={BB305,BB307} ***** BB304 STMT00410 ( 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 this ***** BB304 STMT00411 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB305 [014..022) -> BB307 (cond), preds={} succs={BB306,BB307} ***** BB305 STMT00413 ( 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002026] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002025] ---XG------ this \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 this ***** BB305 STMT00414 ( 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002027] --C-------- \--* RET_EXPR int (for [002026]) ------------ BB306 [022..040) (return), preds={} succs={} ***** BB306 STMT00415 ( 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 this ***** BB306 STMT00416 ( ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB306 STMT00417 ( 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 this [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB307 [040..048) (return), preds={} succs={} ***** BB307 STMT00412 ( 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002020] ----------- this +--* LCL_VAR byref V00 this [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000621] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000621] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000621] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000621] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000621] Starting PHASE Post-import *************** Inline @[000621] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000621] ----------- Arguments setup: STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 Inlinee method body:New Basic Block BB308 [0294] created. Convert bbJumpKind of BB303 to BBJ_ALWAYS to bottomBlock BB308 Convert bbJumpKind of BB306 to BBJ_ALWAYS to bottomBlock BB308 Convert bbJumpKind of BB307 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB302 [0288] 1 1 [584..585)-> BB304 ( cond ) i bwd BB303 [0289] 1 1 [584..585)-> BB308 (always) i bwd BB304 [0290] 1 1 [584..585)-> BB307 ( cond ) i idxlen bwd BB305 [0291] 1 1 [584..585)-> BB307 ( cond ) i bwd BB306 [0292] 1 1 [584..585)-> BB308 (always) i bwd BB307 [0293] 2 1 [584..585) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB302 [584..585) -> BB304 (cond), preds={} succs={BB303,BB304} ***** BB302 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* NE int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB303 [584..585) -> BB308 (always), preds={} succs={BB308} ------------ BB304 [584..585) -> BB307 (cond), preds={} succs={BB305,BB307} ***** BB304 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 ***** BB304 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB305 [584..585) -> BB307 (cond), preds={} succs={BB306,BB307} ***** BB305 STMT00413 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002026] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002025] ---XG------ this \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 ***** BB305 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002027] --C-------- \--* RET_EXPR int (for [002026]) ------------ BB306 [584..585) -> BB308 (always), preds={} succs={BB308} ***** BB306 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 ***** BB306 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB306 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB307 [584..585), preds={} succs={BB308} ***** BB307 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(System.String):this (72 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Querying runtime about current class of field : (declared as System.String) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00413 in BB305: STMT00413 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002026] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002025] ---XG------ this \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002025] ---XG------ * FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB309 [0295] created. BB309 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB309 [0295] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002026] Starting PHASE Pre-import *************** Inline @[002026] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB309 [0295] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB309 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002026] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002026] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB309 [0295] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB309 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002026] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB309 Importing BB309 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 109 (V109 tmp69) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002062] ---XG------ * FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 Inlinee Return expression (after normalization) => [002062] ---XG------ * FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002026] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB309 [0295] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB309 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002026] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002026] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002026] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002026] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002026] Starting PHASE Post-import *************** Inline @[002026] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002026] ----------- Arguments setup: STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002027] with [002062] [002027] --C-------- * RET_EXPR int (for [002026]) -> [002062] Inserting the inline return expression [002062] ---XG------ * FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 Expanding INLINE_CANDIDATE in statement STMT00412 in BB307: STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 thisArg: is a local var [002020] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [002021] ----------- * LCL_VAR ref V106 tmp66 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:AppendSlow(System.String):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 03 ldarg.1 IL_0014 6f 18 08 00 06 callvirt 0x6000818 IL_0019 59 sub IL_001a 31 0c ble.s 12 (IL_0028) IL_001c 02 ldarg.0 IL_001d 03 ldarg.1 IL_001e 6f 18 08 00 06 callvirt 0x6000818 IL_0023 28 66 3e 00 06 call 0x6003E66 IL_0028 03 ldarg.1 IL_0029 02 ldarg.0 IL_002a 7c 26 0f 00 04 ldflda 0x4000F26 IL_002f 06 ldloc.0 IL_0030 28 c0 00 00 0a call 0xA0000C0 IL_0035 6f ee 07 00 06 callvirt 0x60007EE IL_003a 02 ldarg.0 IL_003b 02 ldarg.0 IL_003c 7b 27 0f 00 04 ldfld 0x4000F27 IL_0041 03 ldarg.1 IL_0042 6f 18 08 00 06 callvirt 0x6000818 IL_0047 58 add IL_0048 7d 27 0f 00 04 stfld 0x4000F27 IL_004d 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:AppendSlow(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:AppendSlow(System.String):this weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-15 : state 77 [ sub ] weight= 53 : state 49 [ ble.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 83 : state 99 [ callvirt ] weight= 10 : state 3 [ ldarg.0 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-12 : state 76 [ add ] weight= 31 : state 111 [ stfld ] weight= 19 : state 42 [ ret ] Inline candidate callsite is in a loop. Multiplier increased to 3. calleeNativeSizeEstimate=877 callsiteNativeSizeEstimate=115 benefit multiplier=3 threshold=345 Native estimate for function size exceeds threshold for inlining 87.7 > 34.5 (multiplier = 3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00126 in BB149: STMT00126 ( 0x598[E-] ... 0x5A4 ) [000587] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this (exactContextHnd=0x4000000000424641) [000586] ----------- this \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000586] ----------- * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this set to 0x4000000000424641: Invoking compiler for the inlinee method System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 3d 09 00 04 ldfld 0x400093D IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this is 0x4000000000424641. *************** In compInitDebuggingInfo() for System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this Jump targets: none New Basic Block BB310 [0296] created. BB310 [000..007) Basic block list for 'System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB310 [0296] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000587] Starting PHASE Pre-import *************** Inline @[000587] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB310 [0296] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB310 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000587] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000587] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB310 [0296] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB310 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000587] Starting PHASE Importation *************** In impImport() for System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this impImportBlockPending for BB310 Importing BB310 (PC=000) of 'System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0400093D [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002066] ---XG------ * FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [002066] ---XG------ * FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000587] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB310 [0296] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB310 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000587] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000587] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000587] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000587] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000587] Starting PHASE Post-import *************** Inline @[000587] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000587] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000588] with [002066] [000588] --C-------- * RET_EXPR ref (for [000587]) -> [002066] Inserting the inline return expression [002066] ---XG------ * FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 Expanding INLINE_CANDIDATE in statement STMT00127 in BB149: STMT00127 ( 0x598[E-] ... ??? ) [000589] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000585] ----------- this +--* LCL_VAR byref V00 arg0 [002066] ---XG------ arg1 \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000585] ----------- * LCL_VAR byref V00 arg0 Querying runtime about current class of field : (declared as System.String) Field's current class not available Argument #1: has global refs has side effects [002066] ---XG------ * FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(System.String):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 01 brtrue.s 1 (IL_0004) IL_0003 2a ret IL_0004 02 ldarg.0 IL_0005 7b 27 0f 00 04 ldfld 0x4000F27 IL_000a 0a stloc.0 IL_000b 03 ldarg.1 IL_000c 6f 18 08 00 06 callvirt 0x6000818 IL_0011 17 ldc.i4.1 IL_0012 33 2c bne.un.s 44 (IL_0040) IL_0014 06 ldloc.0 IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 28 0a 00 00 0a call 0xA00000A IL_0020 34 1e bge.un.s 30 (IL_0040) IL_0022 02 ldarg.0 IL_0023 7c 26 0f 00 04 ldflda 0x4000F26 IL_0028 06 ldloc.0 IL_0029 28 0b 00 00 0a call 0xA00000B IL_002e 03 ldarg.1 IL_002f 16 ldc.i4.0 IL_0030 6f 17 08 00 06 callvirt 0x6000817 IL_0035 53 stind.i2 IL_0036 02 ldarg.0 IL_0037 06 ldloc.0 IL_0038 17 ldc.i4.1 IL_0039 58 add IL_003a 7d 27 0f 00 04 stfld 0x4000F27 IL_003f 2a ret IL_0040 02 ldarg.0 IL_0041 03 ldarg.1 IL_0042 28 60 3e 00 06 call 0x6003E60 IL_0047 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(System.String):this Jump targets: IL_0004 IL_0040 New Basic Block BB311 [0297] created. BB311 [000..003) New Basic Block BB312 [0298] created. BB312 [003..004) New Basic Block BB313 [0299] created. BB313 [004..014) New Basic Block BB314 [0300] created. BB314 [014..022) New Basic Block BB315 [0301] created. BB315 [022..040) New Basic Block BB316 [0302] created. BB316 [040..048) Basic block list for 'System.Text.ValueStringBuilder:Append(System.String):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB311 [0297] 1 1 [000..003)-> BB313 ( cond ) BB312 [0298] 1 1 [003..004) (return) BB313 [0299] 1 1 [004..014)-> BB316 ( cond ) BB314 [0300] 1 1 [014..022)-> BB316 ( cond ) BB315 [0301] 1 1 [022..040) (return) BB316 [0302] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000589] Starting PHASE Pre-import *************** Inline @[000589] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB311 [0297] 1 1 [000..003)-> BB313 ( cond ) BB312 [0298] 1 1 [003..004) (return) BB313 [0299] 1 1 [004..014)-> BB316 ( cond ) BB314 [0300] 1 1 [014..022)-> BB316 ( cond ) BB315 [0301] 1 1 [022..040) (return) BB316 [0302] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB311 [000..003) -> BB313 (cond), preds={} succs={BB312,BB313} ------------ BB312 [003..004) (return), preds={} succs={} ------------ BB313 [004..014) -> BB316 (cond), preds={} succs={BB314,BB316} ------------ BB314 [014..022) -> BB316 (cond), preds={} succs={BB315,BB316} ------------ BB315 [022..040) (return), preds={} succs={} ------------ BB316 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000589] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000589] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB311 [0297] 1 1 [000..003)-> BB313 ( cond ) BB312 [0298] 1 1 [003..004) (return) BB313 [0299] 1 1 [004..014)-> BB316 ( cond ) BB314 [0300] 1 1 [014..022)-> BB316 ( cond ) BB315 [0301] 1 1 [022..040) (return) BB316 [0302] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB311 [000..003) -> BB313 (cond), preds={} succs={BB312,BB313} ------------ BB312 [003..004) (return), preds={} succs={} ------------ BB313 [004..014) -> BB316 (cond), preds={} succs={BB314,BB316} ------------ BB314 [014..022) -> BB316 (cond), preds={} succs={BB315,BB316} ------------ BB315 [022..040) (return), preds={} succs={} ------------ BB316 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000589] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(System.String):this impImportBlockPending for BB311 Importing BB311 (PC=000) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 110 (V110 tmp70) called for Inlining Arg. Marked V110 as a single def temp Querying runtime about current class of field : (declared as System.String) Field's current class not available lvaSetClass: setting class for V110 to (4000000000420010) System.String [ 1] 1 (0x001) brtrue.s STMT00420 ( 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* NE int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null impImportBlockPending for BB312 impImportBlockPending for BB313 Importing BB313 (PC=004) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 4 (0x004) ldarg.0 [ 1] 5 (0x005) ldfld 04000F27 [ 1] 10 (0x00a) stloc.0 lvaGrabTemp returning 111 (V111 tmp71) (a long lifetime temp) called for Inline stloc first use temp. STMT00421 ( 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 this [ 0] 11 (0x00b) ldarg.1 [ 1] 12 (0x00c) callvirt 06000818 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.String.get_Length: Recognized [ 1] 17 (0x011) ldc.i4.1 1 [ 2] 18 (0x012) bne.un.s STMT00422 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 impImportBlockPending for BB314 impImportBlockPending for BB316 Importing BB316 (PC=064) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 64 (0x040) ldarg.0 [ 1] 65 (0x041) ldarg.1 [ 2] 66 (0x042) call 06003E60 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00423 ( 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002080] ----------- this +--* LCL_VAR byref V00 this [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 [ 0] 71 (0x047) ret Importing BB314 (PC=020) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 20 (0x014) ldloc.0 [ 1] 21 (0x015) ldarg.0 [ 2] 22 (0x016) ldflda 04000F26 [ 2] 27 (0x01b) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00424 ( 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002086] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002085] ---XG------ this \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 this [ 2] 32 (0x020) bge.un.s STMT00425 ( 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002087] --C-------- \--* RET_EXPR int (for [002086]) impImportBlockPending for BB315 impImportBlockPending for BB316 Importing BB315 (PC=034) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 34 (0x022) ldarg.0 [ 1] 35 (0x023) ldflda 04000F26 [ 1] 40 (0x028) ldloc.0 [ 2] 41 (0x029) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002091] ---XG------ * FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 this and index [002092] ----------- * LCL_VAR int V111 tmp71 lvaGrabTemp returning 112 (V112 tmp72) called for Span.get_Item ptrToSpan. STMT00426 ( 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 this [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) ldc.i4.0 0 [ 3] 48 (0x030) callvirt 06000817 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ushort, structSize is 0 Named Intrinsic System.String.get_Chars: Recognized [ 2] 53 (0x035) stind.i2 STMT00427 ( ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 [ 0] 54 (0x036) ldarg.0 [ 1] 55 (0x037) ldloc.0 [ 2] 56 (0x038) ldc.i4.1 1 [ 3] 57 (0x039) add [ 2] 58 (0x03a) stfld 04000F27 STMT00428 ( 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 this [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 [ 0] 63 (0x03f) ret Importing BB312 (PC=003) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 3 (0x003) ret ** Note: inlinee IL was partially imported -- imported 71 of 72 bytes of method IL *************** Inline @[000589] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB311 [0297] 1 1 [000..003)-> BB313 ( cond ) i BB312 [0298] 1 1 [003..004) (return) i BB313 [0299] 1 1 [004..014)-> BB316 ( cond ) i idxlen BB314 [0300] 1 1 [014..022)-> BB316 ( cond ) i BB315 [0301] 1 1 [022..040) (return) i BB316 [0302] 2 1 [040..048) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB311 [000..003) -> BB313 (cond), preds={} succs={BB312,BB313} ***** BB311 STMT00420 ( 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* NE int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB312 [003..004) (return), preds={} succs={} ------------ BB313 [004..014) -> BB316 (cond), preds={} succs={BB314,BB316} ***** BB313 STMT00421 ( 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 this ***** BB313 STMT00422 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB314 [014..022) -> BB316 (cond), preds={} succs={BB315,BB316} ***** BB314 STMT00424 ( 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002086] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002085] ---XG------ this \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 this ***** BB314 STMT00425 ( 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002087] --C-------- \--* RET_EXPR int (for [002086]) ------------ BB315 [022..040) (return), preds={} succs={} ***** BB315 STMT00426 ( 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 this ***** BB315 STMT00427 ( ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB315 STMT00428 ( 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 this [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB316 [040..048) (return), preds={} succs={} ***** BB316 STMT00423 ( 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002080] ----------- this +--* LCL_VAR byref V00 this [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000589] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000589] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000589] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000589] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000589] Starting PHASE Post-import *************** Inline @[000589] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000589] ----------- Arguments setup: STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 Inlinee method body:New Basic Block BB317 [0303] created. Convert bbJumpKind of BB312 to BBJ_ALWAYS to bottomBlock BB317 Convert bbJumpKind of BB315 to BBJ_ALWAYS to bottomBlock BB317 Convert bbJumpKind of BB316 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB311 [0297] 1 1 [598..599)-> BB313 ( cond ) i bwd BB312 [0298] 1 1 [598..599)-> BB317 (always) i bwd BB313 [0299] 1 1 [598..599)-> BB316 ( cond ) i idxlen bwd BB314 [0300] 1 1 [598..599)-> BB316 ( cond ) i bwd BB315 [0301] 1 1 [598..599)-> BB317 (always) i bwd BB316 [0302] 2 1 [598..599) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB311 [598..599) -> BB313 (cond), preds={} succs={BB312,BB313} ***** BB311 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* NE int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB312 [598..599) -> BB317 (always), preds={} succs={BB317} ------------ BB313 [598..599) -> BB316 (cond), preds={} succs={BB314,BB316} ***** BB313 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 ***** BB313 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB314 [598..599) -> BB316 (cond), preds={} succs={BB315,BB316} ***** BB314 STMT00424 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002086] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002085] ---XG------ this \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 ***** BB314 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002087] --C-------- \--* RET_EXPR int (for [002086]) ------------ BB315 [598..599) -> BB317 (always), preds={} succs={BB317} ***** BB315 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 ***** BB315 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB315 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB316 [598..599), preds={} succs={BB317} ***** BB316 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(System.String):this (72 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Querying runtime about current class of field : (declared as System.String) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00424 in BB314: STMT00424 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002086] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002085] ---XG------ this \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002085] ---XG------ * FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB318 [0304] created. BB318 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB318 [0304] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002086] Starting PHASE Pre-import *************** Inline @[002086] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB318 [0304] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB318 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002086] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002086] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB318 [0304] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB318 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002086] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB318 Importing BB318 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 113 (V113 tmp73) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002122] ---XG------ * FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 Inlinee Return expression (after normalization) => [002122] ---XG------ * FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002086] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB318 [0304] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB318 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002086] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002086] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002086] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002086] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002086] Starting PHASE Post-import *************** Inline @[002086] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002086] ----------- Arguments setup: STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002087] with [002122] [002087] --C-------- * RET_EXPR int (for [002086]) -> [002122] Inserting the inline return expression [002122] ---XG------ * FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 Expanding INLINE_CANDIDATE in statement STMT00423 in BB316: STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 thisArg: is a local var [002080] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [002081] ----------- * LCL_VAR ref V110 tmp70 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:AppendSlow(System.String):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 03 ldarg.1 IL_0014 6f 18 08 00 06 callvirt 0x6000818 IL_0019 59 sub IL_001a 31 0c ble.s 12 (IL_0028) IL_001c 02 ldarg.0 IL_001d 03 ldarg.1 IL_001e 6f 18 08 00 06 callvirt 0x6000818 IL_0023 28 66 3e 00 06 call 0x6003E66 IL_0028 03 ldarg.1 IL_0029 02 ldarg.0 IL_002a 7c 26 0f 00 04 ldflda 0x4000F26 IL_002f 06 ldloc.0 IL_0030 28 c0 00 00 0a call 0xA0000C0 IL_0035 6f ee 07 00 06 callvirt 0x60007EE IL_003a 02 ldarg.0 IL_003b 02 ldarg.0 IL_003c 7b 27 0f 00 04 ldfld 0x4000F27 IL_0041 03 ldarg.1 IL_0042 6f 18 08 00 06 callvirt 0x6000818 IL_0047 58 add IL_0048 7d 27 0f 00 04 stfld 0x4000F27 IL_004d 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:AppendSlow(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:AppendSlow(System.String):this weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-15 : state 77 [ sub ] weight= 53 : state 49 [ ble.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 83 : state 99 [ callvirt ] weight= 10 : state 3 [ ldarg.0 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-12 : state 76 [ add ] weight= 31 : state 111 [ stfld ] weight= 19 : state 42 [ ret ] Inline candidate callsite is in a loop. Multiplier increased to 3. calleeNativeSizeEstimate=877 callsiteNativeSizeEstimate=115 benefit multiplier=3 threshold=345 Native estimate for function size exceeds threshold for inlining 87.7 > 34.5 (multiplier = 3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00139 in BB150: STMT00139 ( 0x5A9[E-] ... 0x5B5 ) [000636] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this (exactContextHnd=0x4000000000424641) [000635] ----------- this \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000635] ----------- * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this set to 0x4000000000424641: Invoking compiler for the inlinee method System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 3c 09 00 04 ldfld 0x400093C IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this is 0x4000000000424641. *************** In compInitDebuggingInfo() for System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this Jump targets: none New Basic Block BB319 [0305] created. BB319 [000..007) Basic block list for 'System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB319 [0305] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000636] Starting PHASE Pre-import *************** Inline @[000636] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB319 [0305] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB319 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000636] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000636] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB319 [0305] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB319 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000636] Starting PHASE Importation *************** In impImport() for System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this impImportBlockPending for BB319 Importing BB319 (PC=000) of 'System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0400093C [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002126] ---XG------ * FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [002126] ---XG------ * FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000636] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB319 [0305] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB319 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000636] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000636] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000636] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000636] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000636] Starting PHASE Post-import *************** Inline @[000636] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000636] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000637] with [002126] [000637] --C-------- * RET_EXPR ref (for [000636]) -> [002126] Inserting the inline return expression [002126] ---XG------ * FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 Expanding INLINE_CANDIDATE in statement STMT00140 in BB150: STMT00140 ( 0x5A9[E-] ... ??? ) [000638] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(System.String):this (exactContextHnd=0x40000000004246F9) [000634] ----------- this +--* LCL_VAR byref V00 arg0 [002126] ---XG------ arg1 \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000634] ----------- * LCL_VAR byref V00 arg0 Querying runtime about current class of field : (declared as System.String) Field's current class not available Argument #1: has global refs has side effects [002126] ---XG------ * FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(System.String):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 01 brtrue.s 1 (IL_0004) IL_0003 2a ret IL_0004 02 ldarg.0 IL_0005 7b 27 0f 00 04 ldfld 0x4000F27 IL_000a 0a stloc.0 IL_000b 03 ldarg.1 IL_000c 6f 18 08 00 06 callvirt 0x6000818 IL_0011 17 ldc.i4.1 IL_0012 33 2c bne.un.s 44 (IL_0040) IL_0014 06 ldloc.0 IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 28 0a 00 00 0a call 0xA00000A IL_0020 34 1e bge.un.s 30 (IL_0040) IL_0022 02 ldarg.0 IL_0023 7c 26 0f 00 04 ldflda 0x4000F26 IL_0028 06 ldloc.0 IL_0029 28 0b 00 00 0a call 0xA00000B IL_002e 03 ldarg.1 IL_002f 16 ldc.i4.0 IL_0030 6f 17 08 00 06 callvirt 0x6000817 IL_0035 53 stind.i2 IL_0036 02 ldarg.0 IL_0037 06 ldloc.0 IL_0038 17 ldc.i4.1 IL_0039 58 add IL_003a 7d 27 0f 00 04 stfld 0x4000F27 IL_003f 2a ret IL_0040 02 ldarg.0 IL_0041 03 ldarg.1 IL_0042 28 60 3e 00 06 call 0x6003E60 IL_0047 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(System.String):this Jump targets: IL_0004 IL_0040 New Basic Block BB320 [0306] created. BB320 [000..003) New Basic Block BB321 [0307] created. BB321 [003..004) New Basic Block BB322 [0308] created. BB322 [004..014) New Basic Block BB323 [0309] created. BB323 [014..022) New Basic Block BB324 [0310] created. BB324 [022..040) New Basic Block BB325 [0311] created. BB325 [040..048) Basic block list for 'System.Text.ValueStringBuilder:Append(System.String):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB320 [0306] 1 1 [000..003)-> BB322 ( cond ) BB321 [0307] 1 1 [003..004) (return) BB322 [0308] 1 1 [004..014)-> BB325 ( cond ) BB323 [0309] 1 1 [014..022)-> BB325 ( cond ) BB324 [0310] 1 1 [022..040) (return) BB325 [0311] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000638] Starting PHASE Pre-import *************** Inline @[000638] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB320 [0306] 1 1 [000..003)-> BB322 ( cond ) BB321 [0307] 1 1 [003..004) (return) BB322 [0308] 1 1 [004..014)-> BB325 ( cond ) BB323 [0309] 1 1 [014..022)-> BB325 ( cond ) BB324 [0310] 1 1 [022..040) (return) BB325 [0311] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB320 [000..003) -> BB322 (cond), preds={} succs={BB321,BB322} ------------ BB321 [003..004) (return), preds={} succs={} ------------ BB322 [004..014) -> BB325 (cond), preds={} succs={BB323,BB325} ------------ BB323 [014..022) -> BB325 (cond), preds={} succs={BB324,BB325} ------------ BB324 [022..040) (return), preds={} succs={} ------------ BB325 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000638] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000638] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB320 [0306] 1 1 [000..003)-> BB322 ( cond ) BB321 [0307] 1 1 [003..004) (return) BB322 [0308] 1 1 [004..014)-> BB325 ( cond ) BB323 [0309] 1 1 [014..022)-> BB325 ( cond ) BB324 [0310] 1 1 [022..040) (return) BB325 [0311] 2 1 [040..048) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB320 [000..003) -> BB322 (cond), preds={} succs={BB321,BB322} ------------ BB321 [003..004) (return), preds={} succs={} ------------ BB322 [004..014) -> BB325 (cond), preds={} succs={BB323,BB325} ------------ BB323 [014..022) -> BB325 (cond), preds={} succs={BB324,BB325} ------------ BB324 [022..040) (return), preds={} succs={} ------------ BB325 [040..048) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000638] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(System.String):this impImportBlockPending for BB320 Importing BB320 (PC=000) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 114 (V114 tmp74) called for Inlining Arg. Marked V114 as a single def temp Querying runtime about current class of field : (declared as System.String) Field's current class not available lvaSetClass: setting class for V114 to (4000000000420010) System.String [ 1] 1 (0x001) brtrue.s STMT00431 ( 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* NE int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null impImportBlockPending for BB321 impImportBlockPending for BB322 Importing BB322 (PC=004) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 4 (0x004) ldarg.0 [ 1] 5 (0x005) ldfld 04000F27 [ 1] 10 (0x00a) stloc.0 lvaGrabTemp returning 115 (V115 tmp75) (a long lifetime temp) called for Inline stloc first use temp. STMT00432 ( 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 this [ 0] 11 (0x00b) ldarg.1 [ 1] 12 (0x00c) callvirt 06000818 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is int, structSize is 0 Named Intrinsic System.String.get_Length: Recognized [ 1] 17 (0x011) ldc.i4.1 1 [ 2] 18 (0x012) bne.un.s STMT00433 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 impImportBlockPending for BB323 impImportBlockPending for BB325 Importing BB325 (PC=064) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 64 (0x040) ldarg.0 [ 1] 65 (0x041) ldarg.1 [ 2] 66 (0x042) call 06003E60 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00434 ( 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002140] ----------- this +--* LCL_VAR byref V00 this [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 [ 0] 71 (0x047) ret Importing BB323 (PC=020) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 20 (0x014) ldloc.0 [ 1] 21 (0x015) ldarg.0 [ 2] 22 (0x016) ldflda 04000F26 [ 2] 27 (0x01b) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(System.String):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00435 ( 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002146] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002145] ---XG------ this \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 this [ 2] 32 (0x020) bge.un.s STMT00436 ( 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002147] --C-------- \--* RET_EXPR int (for [002146]) impImportBlockPending for BB324 impImportBlockPending for BB325 Importing BB324 (PC=034) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 34 (0x022) ldarg.0 [ 1] 35 (0x023) ldflda 04000F26 [ 1] 40 (0x028) ldloc.0 [ 2] 41 (0x029) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002151] ---XG------ * FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 this and index [002152] ----------- * LCL_VAR int V115 tmp75 lvaGrabTemp returning 116 (V116 tmp76) called for Span.get_Item ptrToSpan. STMT00437 ( 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 this [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) ldc.i4.0 0 [ 3] 48 (0x030) callvirt 06000817 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ushort, structSize is 0 Named Intrinsic System.String.get_Chars: Recognized [ 2] 53 (0x035) stind.i2 STMT00438 ( ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 [ 0] 54 (0x036) ldarg.0 [ 1] 55 (0x037) ldloc.0 [ 2] 56 (0x038) ldc.i4.1 1 [ 3] 57 (0x039) add [ 2] 58 (0x03a) stfld 04000F27 STMT00439 ( 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 this [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 [ 0] 63 (0x03f) ret Importing BB321 (PC=003) of 'System.Text.ValueStringBuilder:Append(System.String):this' [ 0] 3 (0x003) ret ** Note: inlinee IL was partially imported -- imported 71 of 72 bytes of method IL *************** Inline @[000638] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB320 [0306] 1 1 [000..003)-> BB322 ( cond ) i BB321 [0307] 1 1 [003..004) (return) i BB322 [0308] 1 1 [004..014)-> BB325 ( cond ) i idxlen BB323 [0309] 1 1 [014..022)-> BB325 ( cond ) i BB324 [0310] 1 1 [022..040) (return) i BB325 [0311] 2 1 [040..048) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB320 [000..003) -> BB322 (cond), preds={} succs={BB321,BB322} ***** BB320 STMT00431 ( 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* NE int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB321 [003..004) (return), preds={} succs={} ------------ BB322 [004..014) -> BB325 (cond), preds={} succs={BB323,BB325} ***** BB322 STMT00432 ( 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 this ***** BB322 STMT00433 ( 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB323 [014..022) -> BB325 (cond), preds={} succs={BB324,BB325} ***** BB323 STMT00435 ( 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002146] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002145] ---XG------ this \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 this ***** BB323 STMT00436 ( 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002147] --C-------- \--* RET_EXPR int (for [002146]) ------------ BB324 [022..040) (return), preds={} succs={} ***** BB324 STMT00437 ( 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 this ***** BB324 STMT00438 ( ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB324 STMT00439 ( 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 this [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB325 [040..048) (return), preds={} succs={} ***** BB325 STMT00434 ( 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002140] ----------- this +--* LCL_VAR byref V00 this [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000638] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000638] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000638] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000638] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000638] Starting PHASE Post-import *************** Inline @[000638] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000638] ----------- Arguments setup: STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 Inlinee method body:New Basic Block BB326 [0312] created. Convert bbJumpKind of BB321 to BBJ_ALWAYS to bottomBlock BB326 Convert bbJumpKind of BB324 to BBJ_ALWAYS to bottomBlock BB326 Convert bbJumpKind of BB325 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB320 [0306] 1 1 [5A9..5AA)-> BB322 ( cond ) i bwd BB321 [0307] 1 1 [5A9..5AA)-> BB326 (always) i bwd BB322 [0308] 1 1 [5A9..5AA)-> BB325 ( cond ) i idxlen bwd BB323 [0309] 1 1 [5A9..5AA)-> BB325 ( cond ) i bwd BB324 [0310] 1 1 [5A9..5AA)-> BB326 (always) i bwd BB325 [0311] 2 1 [5A9..5AA) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB320 [5A9..5AA) -> BB322 (cond), preds={} succs={BB321,BB322} ***** BB320 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* NE int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB321 [5A9..5AA) -> BB326 (always), preds={} succs={BB326} ------------ BB322 [5A9..5AA) -> BB325 (cond), preds={} succs={BB323,BB325} ***** BB322 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 ***** BB322 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB323 [5A9..5AA) -> BB325 (cond), preds={} succs={BB324,BB325} ***** BB323 STMT00435 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002146] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002145] ---XG------ this \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 ***** BB323 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002147] --C-------- \--* RET_EXPR int (for [002146]) ------------ BB324 [5A9..5AA) -> BB326 (always), preds={} succs={BB326} ***** BB324 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 ***** BB324 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB324 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB325 [5A9..5AA), preds={} succs={BB326} ***** BB325 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(System.String):this (72 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(System.String):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Querying runtime about current class of field : (declared as System.String) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00435 in BB323: STMT00435 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002146] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002145] ---XG------ this \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002145] ---XG------ * FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB327 [0313] created. BB327 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB327 [0313] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002146] Starting PHASE Pre-import *************** Inline @[002146] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB327 [0313] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB327 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002146] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002146] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB327 [0313] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB327 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002146] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB327 Importing BB327 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 117 (V117 tmp77) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002182] ---XG------ * FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 Inlinee Return expression (after normalization) => [002182] ---XG------ * FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002146] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB327 [0313] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB327 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002146] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002146] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002146] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002146] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002146] Starting PHASE Post-import *************** Inline @[002146] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002146] ----------- Arguments setup: STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002147] with [002182] [002147] --C-------- * RET_EXPR int (for [002146]) -> [002182] Inserting the inline return expression [002182] ---XG------ * FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 Expanding INLINE_CANDIDATE in statement STMT00434 in BB325: STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this (exactContextHnd=0x40000000004246F9) [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 thisArg: is a local var [002140] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [002141] ----------- * LCL_VAR ref V114 tmp74 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:AppendSlow(System.String):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 03 ldarg.1 IL_0014 6f 18 08 00 06 callvirt 0x6000818 IL_0019 59 sub IL_001a 31 0c ble.s 12 (IL_0028) IL_001c 02 ldarg.0 IL_001d 03 ldarg.1 IL_001e 6f 18 08 00 06 callvirt 0x6000818 IL_0023 28 66 3e 00 06 call 0x6003E66 IL_0028 03 ldarg.1 IL_0029 02 ldarg.0 IL_002a 7c 26 0f 00 04 ldflda 0x4000F26 IL_002f 06 ldloc.0 IL_0030 28 c0 00 00 0a call 0xA0000C0 IL_0035 6f ee 07 00 06 callvirt 0x60007EE IL_003a 02 ldarg.0 IL_003b 02 ldarg.0 IL_003c 7b 27 0f 00 04 ldfld 0x4000F27 IL_0041 03 ldarg.1 IL_0042 6f 18 08 00 06 callvirt 0x6000818 IL_0047 58 add IL_0048 7d 27 0f 00 04 stfld 0x4000F27 IL_004d 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:AppendSlow(System.String):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:AppendSlow(System.String):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:AppendSlow(System.String):this weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-15 : state 77 [ sub ] weight= 53 : state 49 [ ble.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 16 : state 4 [ ldarg.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 17 : state 110 [ ldflda ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 83 : state 99 [ callvirt ] weight= 10 : state 3 [ ldarg.0 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight=-12 : state 76 [ add ] weight= 31 : state 111 [ stfld ] weight= 19 : state 42 [ ret ] Inline candidate callsite is in a loop. Multiplier increased to 3. calleeNativeSizeEstimate=877 callsiteNativeSizeEstimate=115 benefit multiplier=3 threshold=345 Native estimate for function size exceeds threshold for inlining 87.7 > 34.5 (multiplier = 3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:AppendSlow(System.String):this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00175 in BB151: STMT00175 ( ??? ... 0x5C9 ) [000820] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000803] ----------- this +--* LCL_VAR byref V00 arg0 [000819] ---XG------ arg1 \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 thisArg: is a local var [000803] ----------- * LCL_VAR byref V00 arg0 Argument #1: has global refs has side effects [000819] ---XG------ * IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB328 [0314] created. BB328 [000..015) New Basic Block BB329 [0315] created. BB329 [015..02D) New Basic Block BB330 [0316] created. BB330 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB328 [0314] 1 1 [000..015)-> BB330 ( cond ) BB329 [0315] 1 1 [015..02D) (return) BB330 [0316] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000820] Starting PHASE Pre-import *************** Inline @[000820] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB328 [0314] 1 1 [000..015)-> BB330 ( cond ) BB329 [0315] 1 1 [015..02D) (return) BB330 [0316] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB328 [000..015) -> BB330 (cond), preds={} succs={BB329,BB330} ------------ BB329 [015..02D) (return), preds={} succs={} ------------ BB330 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000820] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000820] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB328 [0314] 1 1 [000..015)-> BB330 ( cond ) BB329 [0315] 1 1 [015..02D) (return) BB330 [0316] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB328 [000..015) -> BB330 (cond), preds={} succs={BB329,BB330} ------------ BB329 [015..02D) (return), preds={} succs={} ------------ BB330 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000820] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB328 Importing BB328 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 118 (V118 tmp78) (a long lifetime temp) called for Inline stloc first use temp. STMT00442 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00443 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002192] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002191] ---XG------ this \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 this [ 2] 19 (0x013) bge.un.s STMT00444 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002193] --C-------- \--* RET_EXPR int (for [002192]) impImportBlockPending for BB329 impImportBlockPending for BB330 Importing BB330 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 lvaGrabTemp returning 119 (V119 tmp79) called for Inlining Arg. [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00445 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 this [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 [ 0] 52 (0x034) ret Importing BB329 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002200] ---XG------ * FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 this and index [002201] ----------- * LCL_VAR int V118 tmp78 lvaGrabTemp returning 120 (V120 tmp80) called for Span.get_Item ptrToSpan. STMT00446 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 this [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00447 ( ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00448 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 this [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000820] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB328 [0314] 1 1 [000..015)-> BB330 ( cond ) i BB329 [0315] 1 1 [015..02D) (return) i BB330 [0316] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB328 [000..015) -> BB330 (cond), preds={} succs={BB329,BB330} ***** BB328 STMT00442 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 this ***** BB328 STMT00443 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002192] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002191] ---XG------ this \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 this ***** BB328 STMT00444 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002193] --C-------- \--* RET_EXPR int (for [002192]) ------------ BB329 [015..02D) (return), preds={} succs={} ***** BB329 STMT00446 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 this ***** BB329 STMT00447 ( ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB329 STMT00448 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 this [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB330 [02D..035) (return), preds={} succs={} ***** BB330 STMT00445 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 this [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000820] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000820] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000820] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000820] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000820] Starting PHASE Post-import *************** Inline @[000820] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000820] ----------- Arguments setup: STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 Inlinee method body:New Basic Block BB331 [0317] created. Convert bbJumpKind of BB329 to BBJ_ALWAYS to bottomBlock BB331 Convert bbJumpKind of BB330 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB328 [0314] 1 1 [000..000)-> BB330 ( cond ) i internal bwd BB329 [0315] 1 1 [000..000)-> BB331 (always) i internal bwd BB330 [0316] 1 1 [000..000) i internal bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB328 [000..000) -> BB330 (cond), preds={} succs={BB329,BB330} ***** BB328 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 ***** BB328 STMT00443 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002192] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002191] ---XG------ this \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 ***** BB328 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002193] --C-------- \--* RET_EXPR int (for [002192]) ------------ BB329 [000..000) -> BB331 (always), preds={} succs={BB331} ***** BB329 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 ***** BB329 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB329 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB330 [000..000), preds={} succs={BB331} ***** BB330 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00443 in BB328: STMT00443 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002192] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002191] ---XG------ this \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002191] ---XG------ * FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB332 [0318] created. BB332 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB332 [0318] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002192] Starting PHASE Pre-import *************** Inline @[002192] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB332 [0318] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB332 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002192] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002192] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB332 [0318] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB332 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002192] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB332 Importing BB332 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 121 (V121 tmp81) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002228] ---XG------ * FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 Inlinee Return expression (after normalization) => [002228] ---XG------ * FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002192] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB332 [0318] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB332 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002192] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002192] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002192] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002192] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002192] Starting PHASE Post-import *************** Inline @[002192] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002192] ----------- Arguments setup: STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002193] with [002228] [002193] --C-------- * RET_EXPR int (for [002192]) -> [002228] Inserting the inline return expression [002228] ---XG------ * FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00165 in BB152: STMT00165 ( 0x5CE[E-] ... 0x5D7 ) [000754] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000753] ----------- this \--* ADDR byref [000752] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000753] ----------- * ADDR byref [000752] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB333 [0319] created. BB333 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB333 [0319] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000754] Starting PHASE Pre-import *************** Inline @[000754] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB333 [0319] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB333 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000754] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000754] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB333 [0319] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB333 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000754] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB333 Importing BB333 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002234] ----------- * FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002234] ----------- * FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000754] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB333 [0319] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB333 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000754] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000754] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000754] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000754] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000754] Starting PHASE Post-import *************** Inline @[000754] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000754] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000755] with [002234] [000755] --C-------- * RET_EXPR int (for [000754]) -> [002234] Inserting the inline return expression [002234] ----------- * FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00167 in BB155: STMT00167 ( 0x5F1[E-] ... 0x5FA ) [000761] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000760] ----------- this \--* ADDR byref [000759] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000760] ----------- * ADDR byref [000759] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB334 [0320] created. BB334 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB334 [0320] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000761] Starting PHASE Pre-import *************** Inline @[000761] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB334 [0320] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB334 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000761] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000761] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB334 [0320] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB334 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000761] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB334 Importing BB334 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002238] ----------- * FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002238] ----------- * FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000761] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB334 [0320] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB334 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000761] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000761] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000761] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000761] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000761] Starting PHASE Post-import *************** Inline @[000761] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000761] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000762] with [002238] [000762] --C-------- * RET_EXPR int (for [000761]) -> [002238] Inserting the inline return expression [002238] ----------- * FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00073 in BB158: STMT00073 ( 0x618[E-] ... 0x621 ) [000286] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000285] ----------- this \--* ADDR byref [000284] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000285] ----------- * ADDR byref [000284] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB335 [0321] created. BB335 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB335 [0321] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000286] Starting PHASE Pre-import *************** Inline @[000286] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB335 [0321] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB335 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000286] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000286] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB335 [0321] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB335 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000286] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB335 Importing BB335 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002242] ----------- * FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002242] ----------- * FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000286] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB335 [0321] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB335 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000286] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000286] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000286] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000286] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000286] Starting PHASE Post-import *************** Inline @[000286] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000286] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000287] with [002242] [000287] --C-------- * RET_EXPR int (for [000286]) -> [002242] Inserting the inline return expression [002242] ----------- * FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00078 in BB160: STMT00078 ( ??? ... 0x648 ) [000318] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000301] ----------- this +--* LCL_VAR byref V00 arg0 [000317] ---XG------ arg1 \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 thisArg: is a local var [000301] ----------- * LCL_VAR byref V00 arg0 Argument #1: has global refs has side effects [000317] ---XG------ * IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB336 [0322] created. BB336 [000..015) New Basic Block BB337 [0323] created. BB337 [015..02D) New Basic Block BB338 [0324] created. BB338 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB336 [0322] 1 1 [000..015)-> BB338 ( cond ) BB337 [0323] 1 1 [015..02D) (return) BB338 [0324] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000318] Starting PHASE Pre-import *************** Inline @[000318] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB336 [0322] 1 1 [000..015)-> BB338 ( cond ) BB337 [0323] 1 1 [015..02D) (return) BB338 [0324] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB336 [000..015) -> BB338 (cond), preds={} succs={BB337,BB338} ------------ BB337 [015..02D) (return), preds={} succs={} ------------ BB338 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000318] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000318] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB336 [0322] 1 1 [000..015)-> BB338 ( cond ) BB337 [0323] 1 1 [015..02D) (return) BB338 [0324] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB336 [000..015) -> BB338 (cond), preds={} succs={BB337,BB338} ------------ BB337 [015..02D) (return), preds={} succs={} ------------ BB338 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000318] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB336 Importing BB336 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 122 (V122 tmp82) (a long lifetime temp) called for Inline stloc first use temp. STMT00451 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00452 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002250] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002249] ---XG------ this \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 this [ 2] 19 (0x013) bge.un.s STMT00453 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002251] --C-------- \--* RET_EXPR int (for [002250]) impImportBlockPending for BB337 impImportBlockPending for BB338 Importing BB338 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 lvaGrabTemp returning 123 (V123 tmp83) called for Inlining Arg. [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00454 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 this [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 [ 0] 52 (0x034) ret Importing BB337 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002258] ---XG------ * FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 this and index [002259] ----------- * LCL_VAR int V122 tmp82 lvaGrabTemp returning 124 (V124 tmp84) called for Span.get_Item ptrToSpan. STMT00455 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 this [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00456 ( ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00457 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 this [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000318] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB336 [0322] 1 1 [000..015)-> BB338 ( cond ) i BB337 [0323] 1 1 [015..02D) (return) i BB338 [0324] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB336 [000..015) -> BB338 (cond), preds={} succs={BB337,BB338} ***** BB336 STMT00451 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 this ***** BB336 STMT00452 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002250] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002249] ---XG------ this \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 this ***** BB336 STMT00453 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002251] --C-------- \--* RET_EXPR int (for [002250]) ------------ BB337 [015..02D) (return), preds={} succs={} ***** BB337 STMT00455 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 this ***** BB337 STMT00456 ( ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB337 STMT00457 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 this [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB338 [02D..035) (return), preds={} succs={} ***** BB338 STMT00454 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 this [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000318] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000318] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000318] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000318] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000318] Starting PHASE Post-import *************** Inline @[000318] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000318] ----------- Arguments setup: STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 Inlinee method body:New Basic Block BB339 [0325] created. Convert bbJumpKind of BB337 to BBJ_ALWAYS to bottomBlock BB339 Convert bbJumpKind of BB338 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB336 [0322] 1 1 [000..000)-> BB338 ( cond ) i internal bwd BB337 [0323] 1 1 [000..000)-> BB339 (always) i internal bwd BB338 [0324] 1 1 [000..000) i internal bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB336 [000..000) -> BB338 (cond), preds={} succs={BB337,BB338} ***** BB336 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 ***** BB336 STMT00452 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002250] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002249] ---XG------ this \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 ***** BB336 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002251] --C-------- \--* RET_EXPR int (for [002250]) ------------ BB337 [000..000) -> BB339 (always), preds={} succs={BB339} ***** BB337 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 ***** BB337 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB337 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB338 [000..000), preds={} succs={BB339} ***** BB338 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00452 in BB336: STMT00452 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002250] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002249] ---XG------ this \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002249] ---XG------ * FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB340 [0326] created. BB340 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB340 [0326] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002250] Starting PHASE Pre-import *************** Inline @[002250] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB340 [0326] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB340 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002250] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002250] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB340 [0326] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB340 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002250] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB340 Importing BB340 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 125 (V125 tmp85) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002286] ---XG------ * FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 Inlinee Return expression (after normalization) => [002286] ---XG------ * FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002250] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB340 [0326] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB340 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002250] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002250] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002250] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002250] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002250] Starting PHASE Post-import *************** Inline @[002250] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002250] ----------- Arguments setup: STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002251] with [002286] [002251] --C-------- * RET_EXPR int (for [002250]) -> [002286] Inserting the inline return expression [002286] ---XG------ * FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00097 in BB162: STMT00097 ( 0x65A[E-] ... 0x663 ) [000422] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000421] ----------- this \--* ADDR byref [000420] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000421] ----------- * ADDR byref [000420] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB341 [0327] created. BB341 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB341 [0327] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000422] Starting PHASE Pre-import *************** Inline @[000422] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB341 [0327] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB341 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000422] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000422] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB341 [0327] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB341 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000422] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB341 Importing BB341 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002292] ----------- * FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002292] ----------- * FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000422] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB341 [0327] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB341 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000422] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000422] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000422] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000422] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000422] Starting PHASE Post-import *************** Inline @[000422] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000422] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000423] with [002292] [000423] --C-------- * RET_EXPR int (for [000422]) -> [002292] Inserting the inline return expression [002292] ----------- * FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00099 in BB165: STMT00099 ( 0x67A[E-] ... 0x685 ) [000431] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000430] ----------- this \--* ADDR byref [000429] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000430] ----------- * ADDR byref [000429] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB342 [0328] created. BB342 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB342 [0328] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000431] Starting PHASE Pre-import *************** Inline @[000431] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB342 [0328] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB342 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000431] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000431] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB342 [0328] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB342 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000431] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB342 Importing BB342 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002296] ----------- * FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002296] ----------- * FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000431] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB342 [0328] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB342 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000431] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000431] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000431] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000431] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000431] Starting PHASE Post-import *************** Inline @[000431] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000431] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000432] with [002296] [000432] --C-------- * RET_EXPR int (for [000431]) -> [002296] Inserting the inline return expression [002296] ----------- * FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00101 in BB169: STMT00101 ( 0x6A8[E-] ... 0x6B3 ) [000440] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000439] ----------- this \--* ADDR byref [000438] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000439] ----------- * ADDR byref [000438] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB343 [0329] created. BB343 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB343 [0329] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000440] Starting PHASE Pre-import *************** Inline @[000440] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB343 [0329] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB343 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000440] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000440] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB343 [0329] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB343 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000440] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB343 Importing BB343 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002300] ----------- * FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002300] ----------- * FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000440] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB343 [0329] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB343 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000440] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000440] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000440] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000440] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000440] Starting PHASE Post-import *************** Inline @[000440] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000440] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000441] with [002300] [000441] --C-------- * RET_EXPR int (for [000440]) -> [002300] Inserting the inline return expression [002300] ----------- * FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00103 in BB172: STMT00103 ( 0x6D1[E-] ... 0x6D9 ) [000446] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000444] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 thisArg: is a local var [000444] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [000445] ----------- * LCL_VAR int V18 loc14 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB344 [0330] created. BB344 [000..015) New Basic Block BB345 [0331] created. BB345 [015..02D) New Basic Block BB346 [0332] created. BB346 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB344 [0330] 1 1 [000..015)-> BB346 ( cond ) BB345 [0331] 1 1 [015..02D) (return) BB346 [0332] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000446] Starting PHASE Pre-import *************** Inline @[000446] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB344 [0330] 1 1 [000..015)-> BB346 ( cond ) BB345 [0331] 1 1 [015..02D) (return) BB346 [0332] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB344 [000..015) -> BB346 (cond), preds={} succs={BB345,BB346} ------------ BB345 [015..02D) (return), preds={} succs={} ------------ BB346 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000446] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000446] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB344 [0330] 1 1 [000..015)-> BB346 ( cond ) BB345 [0331] 1 1 [015..02D) (return) BB346 [0332] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB344 [000..015) -> BB346 (cond), preds={} succs={BB345,BB346} ------------ BB345 [015..02D) (return), preds={} succs={} ------------ BB346 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000446] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB344 Importing BB344 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 126 (V126 tmp86) (a long lifetime temp) called for Inline stloc first use temp. STMT00460 ( 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00461 ( 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002308] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002307] ---XG------ this \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 this [ 2] 19 (0x013) bge.un.s STMT00462 ( 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002309] --C-------- \--* RET_EXPR int (for [002308]) impImportBlockPending for BB345 impImportBlockPending for BB346 Importing BB346 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00463 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 this [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 [ 0] 52 (0x034) ret Importing BB345 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002315] ---XG------ * FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 this and index [002316] ----------- * LCL_VAR int V126 tmp86 lvaGrabTemp returning 127 (V127 tmp87) called for Span.get_Item ptrToSpan. STMT00464 ( 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 this [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00465 ( ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00466 ( 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 this [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000446] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB344 [0330] 1 1 [000..015)-> BB346 ( cond ) i BB345 [0331] 1 1 [015..02D) (return) i BB346 [0332] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB344 [000..015) -> BB346 (cond), preds={} succs={BB345,BB346} ***** BB344 STMT00460 ( 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 this ***** BB344 STMT00461 ( 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002308] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002307] ---XG------ this \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 this ***** BB344 STMT00462 ( 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002309] --C-------- \--* RET_EXPR int (for [002308]) ------------ BB345 [015..02D) (return), preds={} succs={} ***** BB345 STMT00464 ( 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 this ***** BB345 STMT00465 ( ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB345 STMT00466 ( 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 this [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB346 [02D..035) (return), preds={} succs={} ***** BB346 STMT00463 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 this [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000446] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000446] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000446] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000446] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000446] Starting PHASE Post-import *************** Inline @[000446] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000446] ----------- Arguments setup: Inlinee method body:New Basic Block BB347 [0333] created. Convert bbJumpKind of BB345 to BBJ_ALWAYS to bottomBlock BB347 Convert bbJumpKind of BB346 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB344 [0330] 1 1 [6D1..6D2)-> BB346 ( cond ) i bwd BB345 [0331] 1 1 [6D1..6D2)-> BB347 (always) i bwd BB346 [0332] 1 1 [6D1..6D2) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB344 [6D1..6D2) -> BB346 (cond), preds={} succs={BB345,BB346} ***** BB344 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 ***** BB344 STMT00461 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002308] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002307] ---XG------ this \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 ***** BB344 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002309] --C-------- \--* RET_EXPR int (for [002308]) ------------ BB345 [6D1..6D2) -> BB347 (always), preds={} succs={BB347} ***** BB345 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 ***** BB345 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB345 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB346 [6D1..6D2), preds={} succs={BB347} ***** BB346 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- BB172 becomes empty INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00461 in BB344: STMT00461 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002308] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002307] ---XG------ this \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002307] ---XG------ * FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB348 [0334] created. BB348 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB348 [0334] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002308] Starting PHASE Pre-import *************** Inline @[002308] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB348 [0334] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB348 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002308] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002308] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB348 [0334] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB348 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002308] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB348 Importing BB348 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 128 (V128 tmp88) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002341] ---XG------ * FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 Inlinee Return expression (after normalization) => [002341] ---XG------ * FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002308] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB348 [0334] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB348 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002308] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002308] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002308] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002308] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002308] Starting PHASE Post-import *************** Inline @[002308] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002308] ----------- Arguments setup: STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002309] with [002341] [002309] --C-------- * RET_EXPR int (for [002308]) -> [002341] Inserting the inline return expression [002341] ---XG------ * FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00108 in BB174: STMT00108 ( ??? ... 0x6F2 ) [000482] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000481] ----------- this \--* ADDR byref [000480] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000481] ----------- * ADDR byref [000480] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB349 [0335] created. BB349 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB349 [0335] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000482] Starting PHASE Pre-import *************** Inline @[000482] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB349 [0335] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB349 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000482] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000482] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB349 [0335] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB349 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000482] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB349 Importing BB349 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002347] ----------- * FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002347] ----------- * FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000482] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB349 [0335] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB349 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000482] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000482] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000482] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000482] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000482] Starting PHASE Post-import *************** Inline @[000482] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000482] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000483] with [002347] [000483] --C-------- * RET_EXPR int (for [000482]) -> [002347] Inserting the inline return expression [002347] ----------- * FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00114 in BB181: STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] I-C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) (exactContextHnd=0x4000000000424651) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 Argument #0: is a local var [000502] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [000503] ----------- * LCL_VAR ref V03 arg3 Argument #2: is a local var [000504] ----------- * LCL_VAR int V39 loc35 Argument #3: is a local var [000505] ----------- * LCL_VAR int V18 loc14 Argument #4: is a local var [000506] ----------- * LCL_VAR int V38 loc34 Argument #5: is a local var [000507] ----------- * LCL_VAR int V37 loc33 INLINER: inlineInfo.tokenLookupContextHandle for System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) set to 0x4000000000424651: Invoking compiler for the inlinee method System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) : IL to import: IL_0000 02 ldarg.0 IL_0001 05 ldarg.3 IL_0002 28 5e 3e 00 06 call 0x6003E5E IL_0007 04 ldarg.2 IL_0008 16 ldc.i4.0 IL_0009 2f 12 bge.s 18 (IL_001d) IL_000b 02 ldarg.0 IL_000c 03 ldarg.1 IL_000d 6f 08 2e 00 06 callvirt 0x6002E08 IL_0012 28 5f 3e 00 06 call 0x6003E5F IL_0017 04 ldarg.2 IL_0018 65 neg IL_0019 10 02 starg.s 0x2 IL_001b 2b 10 br.s 16 (IL_002d) IL_001d 0e 05 ldarg.s 0x5 IL_001f 2c 0c brfalse.s 12 (IL_002d) IL_0021 02 ldarg.0 IL_0022 03 ldarg.1 IL_0023 6f 14 2e 00 06 callvirt 0x6002E14 IL_0028 28 5f 3e 00 06 call 0x6003E5F IL_002d 1f 14 ldc.i4.s 0x14 IL_002f e0 conv.u IL_0030 fe 0f localloc IL_0032 0a stloc.0 IL_0033 06 ldloc.0 IL_0034 1f 0a ldc.i4.s 0xA IL_0036 d3 conv.i IL_0037 18 ldc.i4.2 IL_0038 5a mul IL_0039 58 add IL_003a 04 ldarg.2 IL_003b 0e 04 ldarg.s 0x4 IL_003d 28 68 17 00 06 call 0x6001768 IL_0042 0b stloc.1 IL_0043 02 ldarg.0 IL_0044 07 ldloc.1 IL_0045 06 ldloc.0 IL_0046 1f 0a ldc.i4.s 0xA IL_0048 d3 conv.i IL_0049 18 ldc.i4.2 IL_004a 5a mul IL_004b 58 add IL_004c 07 ldloc.1 IL_004d 59 sub IL_004e 18 ldc.i4.2 IL_004f 5b div IL_0050 6a conv.i8 IL_0051 69 conv.i4 IL_0052 28 62 3e 00 06 call 0x6003E62 IL_0057 2a ret INLINER impTokenLookupContextHandle for System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) is 0x4000000000424651. *************** In compInitDebuggingInfo() for System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) weight= 10 : state 3 [ ldarg.0 ] weight= 28 : state 6 [ ldarg.3 ] weight= 79 : state 40 [ call ] weight= 35 : state 5 [ ldarg.2 ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 20 : state 47 [ bge.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 35 : state 5 [ ldarg.2 ] weight= 58 : state 89 [ neg ] weight= 21 : state 17 [ starg.s ] weight= 44 : state 43 [ br.s ] weight= 32 : state 15 [ ldarg.s ] weight= 27 : state 44 [ brfalse.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 79 : state 40 [ call ] weight= 41 : state 32 [ ldc.i4.s ] weight=-36 : state 165 [ conv.u ] weight=347 : state 176 [ localloc ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 41 : state 32 [ ldc.i4.s ] weight= 0 : state 157 [ conv.i ] weight= 34 : state 25 [ ldc.i4.2 ] weight= -9 : state 78 [ mul ] weight=-12 : state 76 [ add ] weight= 35 : state 5 [ ldarg.2 ] weight= 32 : state 15 [ ldarg.s ] weight= 79 : state 40 [ call ] weight= 34 : state 12 [ stloc.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 9 : state 8 [ ldloc.1 ] weight= 12 : state 7 [ ldloc.0 ] weight= 41 : state 32 [ ldc.i4.s ] weight= 0 : state 157 [ conv.i ] weight= 34 : state 25 [ ldc.i4.2 ] weight= -9 : state 78 [ mul ] weight=-12 : state 76 [ add ] weight= 9 : state 8 [ ldloc.1 ] weight=-15 : state 77 [ sub ] weight= 34 : state 25 [ ldc.i4.2 ] weight= 35 : state 79 [ div ] weight= 99 : state 94 [ conv.i8 ] weight= 2 : state 93 [ conv.i4 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate has an arg that feeds a constant test. Multiplier increased to 2. Inline candidate callsite is in a loop. Multiplier increased to 5. calleeNativeSizeEstimate=1733 callsiteNativeSizeEstimate=235 benefit multiplier=5 threshold=1175 Native estimate for function size exceeds threshold for inlining 173.3 > 117.5 (multiplier = 5) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00083 in BB182: STMT00083 ( 0x731[E-] ... 0x742 ) [000335] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000333] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 thisArg: is a local var [000333] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [000334] ----------- * LCL_VAR int V18 loc14 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB350 [0336] created. BB350 [000..015) New Basic Block BB351 [0337] created. BB351 [015..02D) New Basic Block BB352 [0338] created. BB352 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB350 [0336] 1 1 [000..015)-> BB352 ( cond ) BB351 [0337] 1 1 [015..02D) (return) BB352 [0338] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000335] Starting PHASE Pre-import *************** Inline @[000335] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB350 [0336] 1 1 [000..015)-> BB352 ( cond ) BB351 [0337] 1 1 [015..02D) (return) BB352 [0338] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB350 [000..015) -> BB352 (cond), preds={} succs={BB351,BB352} ------------ BB351 [015..02D) (return), preds={} succs={} ------------ BB352 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000335] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000335] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB350 [0336] 1 1 [000..015)-> BB352 ( cond ) BB351 [0337] 1 1 [015..02D) (return) BB352 [0338] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB350 [000..015) -> BB352 (cond), preds={} succs={BB351,BB352} ------------ BB351 [015..02D) (return), preds={} succs={} ------------ BB352 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000335] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB350 Importing BB350 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 129 (V129 tmp89) (a long lifetime temp) called for Inline stloc first use temp. STMT00468 ( 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00469 ( 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002355] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002354] ---XG------ this \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 this [ 2] 19 (0x013) bge.un.s STMT00470 ( 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002356] --C-------- \--* RET_EXPR int (for [002355]) impImportBlockPending for BB351 impImportBlockPending for BB352 Importing BB352 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00471 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 this [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 [ 0] 52 (0x034) ret Importing BB351 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002362] ---XG------ * FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 this and index [002363] ----------- * LCL_VAR int V129 tmp89 lvaGrabTemp returning 130 (V130 tmp90) called for Span.get_Item ptrToSpan. STMT00472 ( 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 this [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00473 ( ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00474 ( 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 this [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000335] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB350 [0336] 1 1 [000..015)-> BB352 ( cond ) i BB351 [0337] 1 1 [015..02D) (return) i BB352 [0338] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB350 [000..015) -> BB352 (cond), preds={} succs={BB351,BB352} ***** BB350 STMT00468 ( 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 this ***** BB350 STMT00469 ( 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002355] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002354] ---XG------ this \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 this ***** BB350 STMT00470 ( 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002356] --C-------- \--* RET_EXPR int (for [002355]) ------------ BB351 [015..02D) (return), preds={} succs={} ***** BB351 STMT00472 ( 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 this ***** BB351 STMT00473 ( ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB351 STMT00474 ( 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 this [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB352 [02D..035) (return), preds={} succs={} ***** BB352 STMT00471 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 this [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000335] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000335] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000335] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000335] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000335] Starting PHASE Post-import *************** Inline @[000335] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000335] ----------- Arguments setup: Inlinee method body:New Basic Block BB353 [0339] created. Convert bbJumpKind of BB351 to BBJ_ALWAYS to bottomBlock BB353 Convert bbJumpKind of BB352 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB350 [0336] 1 1 [731..732)-> BB352 ( cond ) i bwd BB351 [0337] 1 1 [731..732)-> BB353 (always) i bwd BB352 [0338] 1 1 [731..732) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB350 [731..732) -> BB352 (cond), preds={} succs={BB351,BB352} ***** BB350 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 ***** BB350 STMT00469 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002355] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002354] ---XG------ this \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 ***** BB350 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002356] --C-------- \--* RET_EXPR int (for [002355]) ------------ BB351 [731..732) -> BB353 (always), preds={} succs={BB353} ***** BB351 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 ***** BB351 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB351 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB352 [731..732), preds={} succs={BB353} ***** BB352 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- BB182 becomes empty INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00469 in BB350: STMT00469 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002355] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002354] ---XG------ this \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002354] ---XG------ * FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB354 [0340] created. BB354 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB354 [0340] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002355] Starting PHASE Pre-import *************** Inline @[002355] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB354 [0340] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB354 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002355] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002355] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB354 [0340] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB354 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002355] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB354 Importing BB354 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 131 (V131 tmp91) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002388] ---XG------ * FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 Inlinee Return expression (after normalization) => [002388] ---XG------ * FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002355] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB354 [0340] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB354 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002355] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002355] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002355] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002355] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002355] Starting PHASE Post-import *************** Inline @[002355] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002355] ----------- Arguments setup: STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002356] with [002388] [002356] --C-------- * RET_EXPR int (for [002355]) -> [002388] Inserting the inline return expression [002388] ---XG------ * FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00084 in BB353: STMT00084 ( 0x739[E-] ... ??? ) [000339] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000338] ----------- this \--* ADDR byref [000337] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000338] ----------- * ADDR byref [000337] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB355 [0341] created. BB355 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB355 [0341] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000339] Starting PHASE Pre-import *************** Inline @[000339] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB355 [0341] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB355 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000339] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000339] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB355 [0341] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB355 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000339] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB355 Importing BB355 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002394] ----------- * FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002394] ----------- * FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000339] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB355 [0341] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB355 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000339] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000339] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000339] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000339] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000339] Starting PHASE Post-import *************** Inline @[000339] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000339] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000340] with [002394] [000340] --C-------- * RET_EXPR int (for [000339]) -> [002394] Inserting the inline return expression [002394] ----------- * FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00089 in BB185: STMT00089 ( ??? ... 0x772 ) [000371] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000354] ----------- this +--* LCL_VAR byref V00 arg0 [000370] ---XG------ arg1 \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 thisArg: is a local var [000354] ----------- * LCL_VAR byref V00 arg0 Argument #1: has global refs has side effects [000370] ---XG------ * IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB356 [0342] created. BB356 [000..015) New Basic Block BB357 [0343] created. BB357 [015..02D) New Basic Block BB358 [0344] created. BB358 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB356 [0342] 1 1 [000..015)-> BB358 ( cond ) BB357 [0343] 1 1 [015..02D) (return) BB358 [0344] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000371] Starting PHASE Pre-import *************** Inline @[000371] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB356 [0342] 1 1 [000..015)-> BB358 ( cond ) BB357 [0343] 1 1 [015..02D) (return) BB358 [0344] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB356 [000..015) -> BB358 (cond), preds={} succs={BB357,BB358} ------------ BB357 [015..02D) (return), preds={} succs={} ------------ BB358 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000371] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000371] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB356 [0342] 1 1 [000..015)-> BB358 ( cond ) BB357 [0343] 1 1 [015..02D) (return) BB358 [0344] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB356 [000..015) -> BB358 (cond), preds={} succs={BB357,BB358} ------------ BB357 [015..02D) (return), preds={} succs={} ------------ BB358 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000371] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB356 Importing BB356 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 132 (V132 tmp92) (a long lifetime temp) called for Inline stloc first use temp. STMT00476 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00477 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002402] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002401] ---XG------ this \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 this [ 2] 19 (0x013) bge.un.s STMT00478 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002403] --C-------- \--* RET_EXPR int (for [002402]) impImportBlockPending for BB357 impImportBlockPending for BB358 Importing BB358 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 lvaGrabTemp returning 133 (V133 tmp93) called for Inlining Arg. [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00479 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 this [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 [ 0] 52 (0x034) ret Importing BB357 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002410] ---XG------ * FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 this and index [002411] ----------- * LCL_VAR int V132 tmp92 lvaGrabTemp returning 134 (V134 tmp94) called for Span.get_Item ptrToSpan. STMT00480 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 this [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00481 ( ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00482 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 this [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000371] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB356 [0342] 1 1 [000..015)-> BB358 ( cond ) i BB357 [0343] 1 1 [015..02D) (return) i BB358 [0344] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB356 [000..015) -> BB358 (cond), preds={} succs={BB357,BB358} ***** BB356 STMT00476 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 this ***** BB356 STMT00477 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002402] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002401] ---XG------ this \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 this ***** BB356 STMT00478 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002403] --C-------- \--* RET_EXPR int (for [002402]) ------------ BB357 [015..02D) (return), preds={} succs={} ***** BB357 STMT00480 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 this ***** BB357 STMT00481 ( ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB357 STMT00482 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 this [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB358 [02D..035) (return), preds={} succs={} ***** BB358 STMT00479 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 this [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000371] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000371] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000371] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000371] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000371] Starting PHASE Post-import *************** Inline @[000371] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000371] ----------- Arguments setup: STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 Inlinee method body:New Basic Block BB359 [0345] created. Convert bbJumpKind of BB357 to BBJ_ALWAYS to bottomBlock BB359 Convert bbJumpKind of BB358 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB356 [0342] 1 1 [000..000)-> BB358 ( cond ) i internal bwd BB357 [0343] 1 1 [000..000)-> BB359 (always) i internal bwd BB358 [0344] 1 1 [000..000) i internal bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB356 [000..000) -> BB358 (cond), preds={} succs={BB357,BB358} ***** BB356 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 ***** BB356 STMT00477 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002402] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002401] ---XG------ this \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 ***** BB356 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002403] --C-------- \--* RET_EXPR int (for [002402]) ------------ BB357 [000..000) -> BB359 (always), preds={} succs={BB359} ***** BB357 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 ***** BB357 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB357 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB358 [000..000), preds={} succs={BB359} ***** BB358 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00477 in BB356: STMT00477 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002402] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002401] ---XG------ this \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002401] ---XG------ * FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB360 [0346] created. BB360 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB360 [0346] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002402] Starting PHASE Pre-import *************** Inline @[002402] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB360 [0346] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB360 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002402] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002402] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB360 [0346] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB360 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002402] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB360 Importing BB360 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 135 (V135 tmp95) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002438] ---XG------ * FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 Inlinee Return expression (after normalization) => [002438] ---XG------ * FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002402] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB360 [0346] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB360 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002402] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002402] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002402] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002402] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002402] Starting PHASE Post-import *************** Inline @[002402] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002402] ----------- Arguments setup: STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002403] with [002438] [002403] --C-------- * RET_EXPR int (for [002402]) -> [002438] Inserting the inline return expression [002438] ---XG------ * FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00095 in BB186: STMT00095 ( ??? ... 0x783 ) [000407] I-CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000390] ----------- this +--* LCL_VAR byref V00 arg0 [000406] ---XG------ arg1 \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 thisArg: is a local var [000390] ----------- * LCL_VAR byref V00 arg0 Argument #1: has global refs has side effects [000406] ---XG------ * IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB361 [0347] created. BB361 [000..015) New Basic Block BB362 [0348] created. BB362 [015..02D) New Basic Block BB363 [0349] created. BB363 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB361 [0347] 1 1 [000..015)-> BB363 ( cond ) BB362 [0348] 1 1 [015..02D) (return) BB363 [0349] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000407] Starting PHASE Pre-import *************** Inline @[000407] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB361 [0347] 1 1 [000..015)-> BB363 ( cond ) BB362 [0348] 1 1 [015..02D) (return) BB363 [0349] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB361 [000..015) -> BB363 (cond), preds={} succs={BB362,BB363} ------------ BB362 [015..02D) (return), preds={} succs={} ------------ BB363 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000407] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000407] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB361 [0347] 1 1 [000..015)-> BB363 ( cond ) BB362 [0348] 1 1 [015..02D) (return) BB363 [0349] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB361 [000..015) -> BB363 (cond), preds={} succs={BB362,BB363} ------------ BB362 [015..02D) (return), preds={} succs={} ------------ BB363 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000407] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB361 Importing BB361 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 136 (V136 tmp96) (a long lifetime temp) called for Inline stloc first use temp. STMT00485 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00486 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002448] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002447] ---XG------ this \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 this [ 2] 19 (0x013) bge.un.s STMT00487 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002449] --C-------- \--* RET_EXPR int (for [002448]) impImportBlockPending for BB362 impImportBlockPending for BB363 Importing BB363 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 lvaGrabTemp returning 137 (V137 tmp97) called for Inlining Arg. [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00488 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 this [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 [ 0] 52 (0x034) ret Importing BB362 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002456] ---XG------ * FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 this and index [002457] ----------- * LCL_VAR int V136 tmp96 lvaGrabTemp returning 138 (V138 tmp98) called for Span.get_Item ptrToSpan. STMT00489 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 this [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00490 ( ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00491 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 this [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000407] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB361 [0347] 1 1 [000..015)-> BB363 ( cond ) i BB362 [0348] 1 1 [015..02D) (return) i BB363 [0349] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB361 [000..015) -> BB363 (cond), preds={} succs={BB362,BB363} ***** BB361 STMT00485 ( 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 this ***** BB361 STMT00486 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002448] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002447] ---XG------ this \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 this ***** BB361 STMT00487 ( 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002449] --C-------- \--* RET_EXPR int (for [002448]) ------------ BB362 [015..02D) (return), preds={} succs={} ***** BB362 STMT00489 ( 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 this ***** BB362 STMT00490 ( ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB362 STMT00491 ( 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 this [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB363 [02D..035) (return), preds={} succs={} ***** BB363 STMT00488 ( 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 this [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000407] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000407] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000407] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000407] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000407] Starting PHASE Post-import *************** Inline @[000407] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000407] ----------- Arguments setup: STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 Inlinee method body:New Basic Block BB364 [0350] created. Convert bbJumpKind of BB362 to BBJ_ALWAYS to bottomBlock BB364 Convert bbJumpKind of BB363 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB361 [0347] 1 1 [000..000)-> BB363 ( cond ) i internal bwd BB362 [0348] 1 1 [000..000)-> BB364 (always) i internal bwd BB363 [0349] 1 1 [000..000) i internal bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB361 [000..000) -> BB363 (cond), preds={} succs={BB362,BB363} ***** BB361 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 ***** BB361 STMT00486 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002448] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002447] ---XG------ this \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 ***** BB361 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002449] --C-------- \--* RET_EXPR int (for [002448]) ------------ BB362 [000..000) -> BB364 (always), preds={} succs={BB364} ***** BB362 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 ***** BB362 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB362 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB363 [000..000), preds={} succs={BB364} ***** BB363 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00486 in BB361: STMT00486 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002448] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002447] ---XG------ this \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002447] ---XG------ * FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB365 [0351] created. BB365 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB365 [0351] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002448] Starting PHASE Pre-import *************** Inline @[002448] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB365 [0351] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB365 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002448] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002448] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB365 [0351] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB365 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002448] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB365 Importing BB365 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 139 (V139 tmp99) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002484] ---XG------ * FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 Inlinee Return expression (after normalization) => [002484] ---XG------ * FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002448] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB365 [0351] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB365 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002448] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002448] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002448] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002448] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002448] Starting PHASE Post-import *************** Inline @[002448] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002448] ----------- Arguments setup: STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002449] with [002484] [002449] --C-------- * RET_EXPR int (for [002448]) -> [002484] Inserting the inline return expression [002484] ---XG------ * FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00090 in BB187: STMT00090 ( 0x788[E-] ... 0x791 ) [000375] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000374] ----------- this \--* ADDR byref [000373] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000374] ----------- * ADDR byref [000373] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB366 [0352] created. BB366 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB366 [0352] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000375] Starting PHASE Pre-import *************** Inline @[000375] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB366 [0352] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB366 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000375] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000375] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB366 [0352] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB366 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000375] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB366 Importing BB366 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002490] ----------- * FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002490] ----------- * FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000375] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB366 [0352] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB366 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000375] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000375] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000375] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000375] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000375] Starting PHASE Post-import *************** Inline @[000375] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000375] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000376] with [002490] [000376] --C-------- * RET_EXPR int (for [000375]) -> [002490] Inserting the inline return expression [002490] ----------- * FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00128 in BB190: STMT00128 ( 0x7A2[E-] ... 0x7A5 ) [000592] I-C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:Append(ushort):this (exactContextHnd=0x40000000004246F9) [000590] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 thisArg: is a local var [000590] ----------- * LCL_VAR byref V00 arg0 Argument #1: is a local var [000591] ----------- * LCL_VAR int V18 loc14 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:Append(ushort):this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 02 ldarg.0 IL_0009 7c 26 0f 00 04 ldflda 0x4000F26 IL_000e 28 0a 00 00 0a call 0xA00000A IL_0013 34 18 bge.un.s 24 (IL_002d) IL_0015 02 ldarg.0 IL_0016 7c 26 0f 00 04 ldflda 0x4000F26 IL_001b 06 ldloc.0 IL_001c 28 0b 00 00 0a call 0xA00000B IL_0021 03 ldarg.1 IL_0022 53 stind.i2 IL_0023 02 ldarg.0 IL_0024 06 ldloc.0 IL_0025 17 ldc.i4.1 IL_0026 58 add IL_0027 7d 27 0f 00 04 stfld 0x4000F27 IL_002c 2a ret IL_002d 02 ldarg.0 IL_002e 03 ldarg.1 IL_002f 28 65 3e 00 06 call 0x6003E65 IL_0034 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:Append(ushort):this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:Append(ushort):this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:Append(ushort):this Jump targets: IL_002d New Basic Block BB367 [0353] created. BB367 [000..015) New Basic Block BB368 [0354] created. BB368 [015..02D) New Basic Block BB369 [0355] created. BB369 [02D..035) Basic block list for 'System.Text.ValueStringBuilder:Append(ushort):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB367 [0353] 1 1 [000..015)-> BB369 ( cond ) BB368 [0354] 1 1 [015..02D) (return) BB369 [0355] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000592] Starting PHASE Pre-import *************** Inline @[000592] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB367 [0353] 1 1 [000..015)-> BB369 ( cond ) BB368 [0354] 1 1 [015..02D) (return) BB369 [0355] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB367 [000..015) -> BB369 (cond), preds={} succs={BB368,BB369} ------------ BB368 [015..02D) (return), preds={} succs={} ------------ BB369 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000592] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000592] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB367 [0353] 1 1 [000..015)-> BB369 ( cond ) BB368 [0354] 1 1 [015..02D) (return) BB369 [0355] 1 1 [02D..035) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB367 [000..015) -> BB369 (cond), preds={} succs={BB368,BB369} ------------ BB368 [015..02D) (return), preds={} succs={} ------------ BB369 [02D..035) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000592] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:Append(ushort):this impImportBlockPending for BB367 Importing BB367 (PC=000) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 140 (V140 tmp100) (a long lifetime temp) called for Inline stloc first use temp. STMT00494 ( 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.0 [ 2] 9 (0x009) ldflda 04000F26 [ 2] 14 (0x00e) call 0A00000A In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'impMarkInlineCandidate' result 'CheckCanInline Success' reason 'CheckCanInline Success' STMT00495 ( 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002498] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002497] ---XG------ this \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 this [ 2] 19 (0x013) bge.un.s STMT00496 ( 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002499] --C-------- \--* RET_EXPR int (for [002498]) impImportBlockPending for BB368 impImportBlockPending for BB369 Importing BB369 (PC=045) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 45 (0x02d) ldarg.0 [ 1] 46 (0x02e) ldarg.1 [ 2] 47 (0x02f) call 06003E65 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Text.ValueStringBuilder:Append(ushort):this' calling '' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00497 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 this [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 [ 0] 52 (0x034) ret Importing BB368 (PC=021) of 'System.Text.ValueStringBuilder:Append(ushort):this' [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldflda 04000F26 [ 1] 27 (0x01b) ldloc.0 [ 2] 28 (0x01c) call 0A00000B In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 Named Intrinsic System.Span`1.get_Item: Recognized impIntrinsic: Expanding Span.get_Item, T=, sizeof(T)=2 with ptr-to-span [002505] ---XG------ * FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 this and index [002506] ----------- * LCL_VAR int V140 tmp100 lvaGrabTemp returning 141 (V141 tmp101) called for Span.get_Item ptrToSpan. STMT00498 ( 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 this [ 1] 33 (0x021) ldarg.1 [ 2] 34 (0x022) stind.i2 STMT00499 ( ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 [ 0] 35 (0x023) ldarg.0 [ 1] 36 (0x024) ldloc.0 [ 2] 37 (0x025) ldc.i4.1 1 [ 3] 38 (0x026) add [ 2] 39 (0x027) stfld 04000F27 STMT00500 ( 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 this [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 [ 0] 44 (0x02c) ret *************** Inline @[000592] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB367 [0353] 1 1 [000..015)-> BB369 ( cond ) i BB368 [0354] 1 1 [015..02D) (return) i BB369 [0355] 1 1 [02D..035) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB367 [000..015) -> BB369 (cond), preds={} succs={BB368,BB369} ***** BB367 STMT00494 ( 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 this ***** BB367 STMT00495 ( 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002498] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002497] ---XG------ this \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 this ***** BB367 STMT00496 ( 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002499] --C-------- \--* RET_EXPR int (for [002498]) ------------ BB368 [015..02D) (return), preds={} succs={} ***** BB368 STMT00498 ( 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 this ***** BB368 STMT00499 ( ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB368 STMT00500 ( 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 this [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB369 [02D..035) (return), preds={} succs={} ***** BB369 STMT00497 ( 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 this [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000592] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000592] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000592] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000592] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000592] Starting PHASE Post-import *************** Inline @[000592] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000592] ----------- Arguments setup: Inlinee method body:New Basic Block BB370 [0356] created. Convert bbJumpKind of BB368 to BBJ_ALWAYS to bottomBlock BB370 Convert bbJumpKind of BB369 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB367 [0353] 1 1 [7A2..7A3)-> BB369 ( cond ) i bwd BB368 [0354] 1 1 [7A2..7A3)-> BB370 (always) i bwd BB369 [0355] 1 1 [7A2..7A3) i bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB367 [7A2..7A3) -> BB369 (cond), preds={} succs={BB368,BB369} ***** BB367 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 ***** BB367 STMT00495 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002498] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002497] ---XG------ this \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 ***** BB367 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002499] --C-------- \--* RET_EXPR int (for [002498]) ------------ BB368 [7A2..7A3) -> BB370 (always), preds={} succs={BB370} ***** BB368 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 ***** BB368 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB368 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB369 [7A2..7A3), preds={} succs={BB370} ***** BB369 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Text.ValueStringBuilder:Append(ushort):this (53 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- BB190 becomes empty INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:Append(ushort):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00495 in BB367: STMT00495 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002498] I-CXG------ * CALL r2r_ind int System.Span`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000420091) [002497] ---XG------ this \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 thisArg: has global refs has side effects [002497] ---XG------ * FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this set to 0x4000000000420091: Invoking compiler for the inlinee method System.Span`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 07 00 0a ldfld 0xA000731 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Span`1[ushort]:get_Length():int:this is 0x4000000000420091. *************** In compInitDebuggingInfo() for System.Span`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Span`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB371 [0357] created. BB371 [000..007) Basic block list for 'System.Span`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB371 [0357] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[002498] Starting PHASE Pre-import *************** Inline @[002498] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB371 [0357] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB371 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002498] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[002498] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB371 [0357] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB371 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002498] Starting PHASE Importation *************** In impImport() for System.Span`1[ushort]:get_Length():int:this impImportBlockPending for BB371 Importing BB371 (PC=000) of 'System.Span`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 142 (V142 tmp102) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0A000731 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002531] ---XG------ * FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 Inlinee Return expression (after normalization) => [002531] ---XG------ * FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[002498] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB371 [0357] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB371 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[002498] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[002498] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[002498] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[002498] Finishing PHASE Indirect call transform [no changes] *************** Inline @[002498] Starting PHASE Post-import *************** Inline @[002498] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [002498] ----------- Arguments setup: STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Span`1[ushort]:get_Length():int:this (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Span`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [002499] with [002531] [002499] --C-------- * RET_EXPR int (for [002498]) -> [002531] Inserting the inline return expression [002531] ---XG------ * FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' Expanding INLINE_CANDIDATE in statement STMT00053 in BB191: STMT00053 ( 0x7AA[E-] ... 0x7B3 ) [000207] I-C-G------ * CALL r2r_ind int System.ReadOnlySpan`1[ushort]:get_Length():int:this (exactContextHnd=0x4000000000424631) [000206] ----------- this \--* ADDR byref [000205] -------N--- \--* LCL_VAR struct V02 arg2 thisArg: is a constant or invariant is byref to a struct local [000206] ----------- * ADDR byref [000205] -------N--- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this set to 0x4000000000424631: Invoking compiler for the inlinee method System.ReadOnlySpan`1[ushort]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 33 06 00 0a ldfld 0xA000633 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.ReadOnlySpan`1[ushort]:get_Length():int:this is 0x4000000000424631. *************** In compInitDebuggingInfo() for System.ReadOnlySpan`1[ushort]:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.ReadOnlySpan`1[ushort]:get_Length():int:this Jump targets: none New Basic Block BB372 [0358] created. BB372 [000..007) Basic block list for 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB372 [0358] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000207] Starting PHASE Pre-import *************** Inline @[000207] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB372 [0358] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB372 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000207] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000207] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB372 [0358] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB372 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000207] Starting PHASE Importation *************** In impImport() for System.ReadOnlySpan`1[ushort]:get_Length():int:this impImportBlockPending for BB372 Importing BB372 (PC=000) of 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000633 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002537] ----------- * FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [002537] ----------- * FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000207] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB372 [0358] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB372 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000207] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000207] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000207] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000207] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000207] Starting PHASE Post-import *************** Inline @[000207] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000207] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ReadOnlySpan`1[ushort]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.ReadOnlySpan`1[ushort]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000208] with [002537] [000208] --C-------- * RET_EXPR int (for [000207]) -> [002537] Inserting the inline return expression [002537] ----------- * FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00060 in BB197: STMT00060 ( 0x7E9[E-] ... 0x7F0 ) [000231] I-C-G------ * CALL r2r_ind int System.Text.ValueStringBuilder:get_Length():int:this (exactContextHnd=0x40000000004246F9) [000230] ----------- this \--* LCL_VAR byref V00 arg0 thisArg: is a local var [000230] ----------- * LCL_VAR byref V00 arg0 INLINER: inlineInfo.tokenLookupContextHandle for System.Text.ValueStringBuilder:get_Length():int:this set to 0x40000000004246F9: Invoking compiler for the inlinee method System.Text.ValueStringBuilder:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 27 0f 00 04 ldfld 0x4000F27 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Text.ValueStringBuilder:get_Length():int:this is 0x40000000004246F9. *************** In compInitDebuggingInfo() for System.Text.ValueStringBuilder:get_Length():int:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Text.ValueStringBuilder:get_Length():int:this Jump targets: none New Basic Block BB373 [0359] created. BB373 [000..007) Basic block list for 'System.Text.ValueStringBuilder:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB373 [0359] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000231] Starting PHASE Pre-import *************** Inline @[000231] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB373 [0359] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB373 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000231] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000231] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB373 [0359] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB373 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000231] Starting PHASE Importation *************** In impImport() for System.Text.ValueStringBuilder:get_Length():int:this impImportBlockPending for BB373 Importing BB373 (PC=000) of 'System.Text.ValueStringBuilder:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000F27 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002539] ---XG------ * FIELD int : [000230] ----------- \--* LCL_VAR byref V00 this Inlinee Return expression (after normalization) => [002539] ---XG------ * FIELD int : [000230] ----------- \--* LCL_VAR byref V00 this ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000231] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB373 [0359] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB373 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000231] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000231] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000231] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000231] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000231] Starting PHASE Post-import *************** Inline @[000231] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000231] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Text.ValueStringBuilder:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Text.ValueStringBuilder:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000232] with [002539] [000232] --C-------- * RET_EXPR int (for [000231]) -> [002539] Inserting the inline return expression [002539] ---XG------ * FIELD int : [000230] ----------- \--* LCL_VAR byref V00 arg0 Expanding INLINE_CANDIDATE in statement STMT00062 in BB198: STMT00062 ( 0x7F2[E-] ... 0x7FA ) [000239] I-C-G------ * CALL r2r_ind ref System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this (exactContextHnd=0x4000000000424641) [000238] ----------- this \--* LCL_VAR ref V03 arg3 thisArg: is a local var [000238] ----------- * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this set to 0x4000000000424641: Invoking compiler for the inlinee method System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 31 09 00 04 ldfld 0x4000931 IL_0006 2a ret INLINER impTokenLookupContextHandle for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this is 0x4000000000424641. *************** In compInitDebuggingInfo() for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this Jump targets: none New Basic Block BB374 [0360] created. BB374 [000..007) Basic block list for 'System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB374 [0360] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000239] Starting PHASE Pre-import *************** Inline @[000239] Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB374 [0360] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB374 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000239] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000239] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB374 [0360] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB374 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000239] Starting PHASE Importation *************** In impImport() for System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this impImportBlockPending for BB374 Importing BB374 (PC=000) of 'System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000931 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [002541] ---XG------ * FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [002541] ---XG------ * FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** Inline @[000239] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB374 [0360] 1 1 [000..007) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB374 [000..007) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000239] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000239] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000239] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000239] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000239] Starting PHASE Post-import *************** Inline @[000239] Finishing PHASE Post-import [no changes] ----------- Statements (and blocks) added due to the inlining of call [000239] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling 'System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' calling '' INLINER: Marking as NOINLINE because of too many il bytes INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'too many il bytes' Replacing the return expression placeholder [000240] with [002541] [000240] --C-------- * RET_EXPR ref (for [000239]) -> [002541] Inserting the inline return expression [002541] ---XG------ * FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 **************** Inline Tree Inlines into 06000000 [via ExtendedDefaultPolicy] System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo): [INL00 IL=0001 TR=000001 06000000] [FAILED: callee: too many il bytes] [INL01 IL=0010 TR=000006 06000000] [INLINED: call site: profitable inline] System.Number+NumberBuffer:GetDigitsPointer():ulong:this [INL00 IL=0038 TR=000030 06000000] [FAILED: callee: too many il bytes] [INL02 IL=0074 TR=000063 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref [INL03 IL=0326 TR=001438 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL04 IL=0377 TR=001237 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL05 IL=0410 TR=001264 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL06 IL=0436 TR=001273 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL07 IL=0493 TR=001312 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL08 IL=0520 TR=000076 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL00 IL=0629 TR=001151 06000000] [FAILED: callee: too many il bytes] [INL00 IL=0641 TR=001159 06000000] [FAILED: callee: too many il bytes] [INL09 IL=0760 TR=000168 06000000] [INLINED: callee: aggressive inline attribute] System.Span`1[int]:.ctor(ulong,int):this [INL10 IL=0000 TR=001540 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool [INL00 IL=0017 TR=001563 06000000] [FAILED: call site: unprofitable inline] System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) [INL11 IL=0782 TR=000942 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this [INL12 IL=0876 TR=001018 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[int]:get_Length():int:this [INL13 IL=0885 TR=001063 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[int]:get_Length():int:this [INL14 IL=0903 TR=001074 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] [INL15 IL=0001 TR=001585 06000000] [INLINED: callee: aggressive inline attribute] System.Span`1[int]:.ctor(int[]):this [INL16 IL=0058 TR=001601 06000000] [INLINED: callee: aggressive inline attribute] System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref [INL17 IL=0908 TR=001076 06000000] [INLINED: callee: aggressive inline attribute] System.Span`1[int]:CopyTo(System.Span`1[int]):this [INL18 IL=0008 TR=001623 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[int]:get_Length():int:this [INL19 IL=0035 TR=001641 06000000] [INLINED: callee: aggressive inline attribute] System.Buffer:Memmove[int](byref,byref,ulong) [INL20 IL=0000 TR=001649 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Runtime.CompilerServices.RuntimeHelpers:IsReferenceOrContainsReferences[int]():bool [INL00 IL=0028 TR=001667 06000000] [FAILED: callee: too many il bytes] [INL21 IL=0055 TR=001660 06000000] [INLINED: call site: profitable inline] System.Buffer:BulkMoveWithWriteBarrier(byref,byref,ulong) [INL00 IL=0012 TR=001688 06000000] [FAILED: callee: cannot get method info] [INL00 IL=0021 TR=001684 06000000] [FAILED: callee: noinline per IL/cached result] [INL00 IL=0041 TR=001630 06000000] [FAILED: callee: does not return] System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [INL22 IL=0915 TR=001083 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[int]:op_Implicit(int[]):System.Span`1[int] [INL23 IL=0001 TR=001697 06000000] [INLINED: callee: aggressive inline attribute] System.Span`1[int]:.ctor(int[]):this [INL24 IL=0058 TR=001713 06000000] [INLINED: callee: aggressive inline attribute] System.Runtime.InteropServices.MemoryMarshal:GetArrayDataReference[int](int[]):byref [INL25 IL=0990 TR=000938 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this [INL26 IL=0995 TR=000940 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(System.String):this [INL27 IL=0027 TR=001750 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0066 TR=001746 06000000] [FAILED: call site: unprofitable inline] System.Text.ValueStringBuilder:AppendSlow(System.String):this [INL28 IL=1004 TR=000191 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Runtime.InteropServices.MemoryMarshal:GetReference[ushort](System.ReadOnlySpan`1[ushort]):byref [INL29 IL=1068 TR=000859 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL30 IL=0014 TR=001803 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=001809 06000000] [FAILED: callee: noinline per IL/cached result] [INL31 IL=1105 TR=000904 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this [INL32 IL=1110 TR=000906 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(System.String):this [INL33 IL=0027 TR=001863 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0066 TR=001859 06000000] [FAILED: call site: unprofitable inline] System.Text.ValueStringBuilder:AppendSlow(System.String):this [INL34 IL=1316 TR=000676 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL35 IL=0014 TR=001909 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=001914 06000000] [FAILED: callee: noinline per IL/cached result] [INL36 IL=1353 TR=000711 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Globalization.NumberFormatInfo:get_NumberGroupSeparator():System.String:this [INL37 IL=1358 TR=000713 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(System.String):this [INL38 IL=0027 TR=001966 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0066 TR=001962 06000000] [FAILED: call site: unprofitable inline] System.Text.ValueStringBuilder:AppendSlow(System.String):this [INL39 IL=1414 TR=000619 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Globalization.NumberFormatInfo:get_NumberDecimalSeparator():System.String:this [INL40 IL=1419 TR=000621 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(System.String):this [INL41 IL=0027 TR=002026 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0066 TR=002022 06000000] [FAILED: call site: unprofitable inline] System.Text.ValueStringBuilder:AppendSlow(System.String):this [INL42 IL=1434 TR=000587 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Globalization.NumberFormatInfo:get_PerMilleSymbol():System.String:this [INL43 IL=1439 TR=000589 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(System.String):this [INL44 IL=0027 TR=002086 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0066 TR=002082 06000000] [FAILED: call site: unprofitable inline] System.Text.ValueStringBuilder:AppendSlow(System.String):this [INL45 IL=1451 TR=000636 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Globalization.NumberFormatInfo:get_PercentSymbol():System.String:this [INL46 IL=1456 TR=000638 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(System.String):this [INL47 IL=0027 TR=002146 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0066 TR=002142 06000000] [FAILED: call site: unprofitable inline] System.Text.ValueStringBuilder:AppendSlow(System.String):this [INL48 IL=1481 TR=000820 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL49 IL=0014 TR=002192 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=002198 06000000] [FAILED: callee: noinline per IL/cached result] [INL50 IL=1490 TR=000754 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL51 IL=1525 TR=000761 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL52 IL=1564 TR=000286 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL53 IL=1603 TR=000318 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL54 IL=0014 TR=002250 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=002256 06000000] [FAILED: callee: noinline per IL/cached result] [INL55 IL=1630 TR=000422 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL56 IL=1664 TR=000431 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL57 IL=1710 TR=000440 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL58 IL=1748 TR=000446 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL59 IL=0014 TR=002308 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=002313 06000000] [FAILED: callee: noinline per IL/cached result] [INL60 IL=1773 TR=000482 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL00 IL=1831 TR=000508 06000000] [FAILED: call site: unprofitable inline] System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [INL61 IL=1844 TR=000335 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL62 IL=0014 TR=002355 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=002360 06000000] [FAILED: callee: noinline per IL/cached result] [INL63 IL=1853 TR=000339 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL64 IL=1901 TR=000371 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL65 IL=0014 TR=002402 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=002408 06000000] [FAILED: callee: noinline per IL/cached result] [INL66 IL=1923 TR=000407 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL67 IL=0014 TR=002448 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=002454 06000000] [FAILED: callee: noinline per IL/cached result] [INL68 IL=1932 TR=000375 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL69 IL=1957 TR=000592 06000000] [INLINED: callee: aggressive inline attribute] System.Text.ValueStringBuilder:Append(ushort):this [INL70 IL=0014 TR=002498 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Span`1[ushort]:get_Length():int:this [INL00 IL=0047 TR=002503 06000000] [FAILED: callee: noinline per IL/cached result] [INL71 IL=1966 TR=000207 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.ReadOnlySpan`1[ushort]:get_Length():int:this [INL72 IL=2026 TR=000231 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Text.ValueStringBuilder:get_Length():int:this [INL73 IL=2037 TR=000239 06000000] [INLINED: callee: below ALWAYS_INLINE size] System.Globalization.NumberFormatInfo:get_NegativeSign():System.String:this [INL00 IL=2042 TR=000241 06000000] [FAILED: callee: too many il bytes] Budget: initialTime=6204, finalTime=7528, initialBudget=62040, currentBudget=63884 Budget: increased by 1844 because of force inlines Budget: discretionary inline caused a force inline Budget: initialSize=46825, finalSize=47153 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 1 [022..025)-> BB06 (always) i BB05 [0004] 1 1 [025..026) i BB06 [0005] 3 1 [026..02D) i BB07 [0006] 2 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 1 [0C1..0CA)-> BB31 ( cond ) i bwd BB16 [0015] 1 1 [0CA..0CF)-> BB48 (always) i bwd BB17 [0016] 1 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 1 [0E0..0E2) i bwd BB20 [0019] 2 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 1 [11E..121) i bwd BB29 [0028] 2 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 1 [12C..137)-> BB48 (always) i bwd BB31 [0030] 1 1 [137..142)-> BB48 (always) i bwd BB32 [0031] 3 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 1 [201..204) i bwd BB48 [0047] 27 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 1 [233..235) i bwd BB53 [0052] 2 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 1 [24A..24D) i bwd BB57 [0056] 3 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 1 [26E..26F) i bwd BB61 [0060] 2 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 1 [2A0..2A7) i BB66 [0065] 2 1 [2A7..2AE) i BB67 [0066] 3 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 1 [2B5..2B8) i BB70 [0069] 2 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 1 [2C0..2C3) i BB73 [0072] 2 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 1 [2DC..2E2) i BB78 [0077] 2 1 [2E2..2EE) i BB79 [0078] 2 1 [2EE..30D) i BB213 [0207] 1 1 [000..000)-> BB215 (always) i internal BB214 [0208] 1 1 [000..000) i internal BB215 [0209] 2 1 [000..000)-> BB216 (always) i internal BB216 [0211] 2 1 [000..000) i internal BB217 [0212] 1 1 [???..???)-> BB97 ( cond ) internal BB80 [0079] 1 1 [30D..31E)-> BB97 ( cond ) i idxlen BB81 [0080] 1 1 [31E..336)-> BB83 ( cond ) i idxlen BB82 [0081] 1 1 [336..33D) i idxlen BB83 [0082] 2 1 [33D..348)-> BB85 ( cond ) i BB84 [0083] 1 1 [348..34B)-> BB86 (always) i BB85 [0084] 1 1 [34B..34D) i BB86 [0085] 2 1 [34D..355)-> BB88 ( cond ) i BB87 [0086] 1 1 [355..359)-> BB89 (always) i BB88 [0087] 1 1 [359..35A) i BB89 [0088] 2 1 [35A..35E)-> BB96 (always) i BB90 [0089] 1 1 [35E..362)-> BB97 ( cond ) i bwd bwd-target BB91 [0090] 1 1 [362..373)-> BB93 ( cond ) i bwd BB92 [0091] 1 1 [373..39A) i bwd BB229 [0218] 1 1 [383..384)-> BB231 ( cond ) i bwd BB230 [0219] 1 1 [383..384)-> BB233 (always) i bwd BB231 [0220] 1 1 [383..384)-> BB232 (always) i bwd BB232 [0223] 3 1 [383..384) i idxlen bwd BB233 [0224] 1 1 [???..???) internal bwd BB235 [0226] 1 1 [000..000)-> BB237 ( cond ) i internal bwd BB236 [0227] 1 1 [000..000) i internal bwd BB240 [0231] 1 1 [000..000) i internal bwd BB241 [0232] 1 1 [000..000)-> BB243 (always) i internal bwd BB242 [0233] 1 1 [000..000) i internal bwd BB245 [0236] 1 1 [000..000)-> BB247 ( cond ) i internal bwd BB246 [0237] 1 1 [000..000)-> BB248 (always) i internal bwd BB247 [0238] 1 1 [000..000) i internal bwd BB248 [0239] 1 1 [???..???) internal bwd BB243 [0234] 1 1 [???..???)-> BB238 (always) internal bwd BB237 [0228] 1 1 [000..000) i internal bwd BB238 [0229] 1 1 [???..???) i internal bwd BB257 [0241] 1 1 [391..392)-> BB259 ( cond ) i bwd BB258 [0242] 1 1 [391..392)-> BB261 (always) i bwd BB259 [0243] 1 1 [391..392)-> BB260 (always) i bwd BB260 [0246] 3 1 [391..392) i idxlen bwd BB261 [0247] 1 1 [???..???) internal bwd BB93 [0092] 2 1 [39A..3AE)-> BB95 ( cond ) i bwd BB94 [0093] 1 1 [3AE..3BB) i idxlen bwd BB95 [0094] 2 1 [3BB..3C2) i bwd BB96 [0095] 2 1 [3C2..3C8)-> BB90 ( cond ) i bwd bwd-src BB97 [0096] 4 1 [3C8..3D0)-> BB101 ( cond ) i BB98 [0097] 1 1 [3D0..3D4)-> BB101 ( cond ) i BB99 [0098] 1 1 [3D4..3DC)-> BB101 ( cond ) i BB100 [0099] 1 1 [3DC..3E8) i BB264 [0250] 1 1 [3DC..3DD)-> BB266 ( cond ) i BB265 [0251] 1 1 [3DC..3DD)-> BB270 (always) i BB266 [0252] 1 1 [3DC..3DD)-> BB269 ( cond ) i idxlen BB267 [0253] 1 1 [3DC..3DD)-> BB269 ( cond ) i BB268 [0254] 1 1 [3DC..3DD)-> BB270 (always) i BB269 [0255] 2 1 [3DC..3DD) i BB270 [0256] 1 1 [???..???) internal BB101 [0100] 4 1 [3E8..401)-> BB191 (always) i BB102 [0101] 1 1 [401..406)-> BB117 ( cond ) i bwd bwd-target BB103 [0102] 1 1 [406..40C)-> BB116 ( cond ) i bwd BB104 [0103] 1 1 [40C..412)-> BB116 ( cond ) i bwd BB105 [0104] 1 1 [412..418)-> BB116 ( cond ) i bwd BB106 [0105] 1 1 [418..41A)-> BB117 (always) i bwd BB107 [0106] 1 1 [41A..420)-> BB109 ( cond ) i bwd bwd-target BB108 [0107] 1 1 [420..424)-> BB110 (always) i bwd BB109 [0108] 1 1 [424..42C) i bwd BB110 [0109] 2 1 [42C..435) i bwd BB273 [0259] 1 1 [000..000)-> BB275 ( cond ) i internal bwd BB274 [0260] 1 1 [000..000)-> BB276 (always) i internal bwd BB275 [0261] 1 1 [000..000) i internal bwd BB276 [0262] 1 1 [???..???)-> BB115 ( cond ) internal bwd BB111 [0110] 1 1 [435..43A)-> BB115 ( cond ) i bwd BB112 [0111] 1 1 [43A..43F)-> BB115 ( cond ) i bwd BB113 [0112] 1 1 [43F..44F)-> BB115 ( cond ) i bwd BB114 [0113] 1 1 [44F..461) i bwd BB279 [0265] 1 1 [44F..450)-> BB281 ( cond ) i bwd BB280 [0266] 1 1 [44F..450)-> BB285 (always) i bwd BB281 [0267] 1 1 [44F..450)-> BB284 ( cond ) i idxlen bwd BB282 [0268] 1 1 [44F..450)-> BB284 ( cond ) i bwd BB283 [0269] 1 1 [44F..450)-> BB285 (always) i bwd BB284 [0270] 2 1 [44F..450) i bwd BB285 [0271] 1 1 [???..???) internal bwd BB115 [0114] 5 1 [461..46D) i bwd BB116 [0115] 4 1 [46D..472)-> BB107 ( cond ) i bwd bwd-src BB117 [0116] 3 1 [472..478)-> BB122 ( cond ) i bwd BB118 [0117] 1 1 [478..49A)-> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch) i bwd BB119 [0118] 1 1 [49A..4B8)-> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch) i bwd BB120 [0119] 1 1 [4B8..4C1)-> BB161 ( cond ) i bwd BB121 [0120] 1 1 [4C1..4C6)-> BB190 (always) i bwd BB122 [0121] 1 1 [4C6..4CF)-> BB158 ( cond ) i bwd BB123 [0122] 1 1 [4CF..4D8)-> BB161 ( cond ) i bwd BB124 [0123] 1 1 [4D8..4E4)-> BB149 ( cond ) i bwd BB125 [0124] 1 1 [4E4..4E9)-> BB190 (always) i bwd BB126 [0125] 2 1 [4E9..4EE)-> BB131 ( cond ) i bwd BB127 [0126] 1 1 [4EE..4F9)-> BB129 ( cond ) i bwd BB128 [0127] 1 1 [4F9..4FC)-> BB130 (always) i bwd BB129 [0128] 1 1 [4FC..4FE) i bwd BB130 [0129] 2 1 [4FE..502)-> BB137 (always) i bwd BB131 [0130] 1 1 [502..507)-> BB135 ( cond ) i bwd BB132 [0131] 1 1 [507..50C)-> BB134 ( cond ) i bwd BB133 [0132] 1 1 [50C..50F)-> BB136 (always) i bwd BB134 [0133] 1 1 [50F..513)-> BB136 (always) i bwd BB135 [0134] 1 1 [513..51B) i bwd BB136 [0135] 3 1 [51B..51D) i bwd BB137 [0136] 2 1 [51D..521)-> BB143 ( cond ) i bwd BB138 [0137] 1 1 [521..52D) i bwd BB287 [0273] 1 1 [521..522)-> BB289 ( cond ) i bwd BB288 [0274] 1 1 [521..522)-> BB290 (always) i bwd BB289 [0275] 1 1 [521..522) i bwd BB290 [0276] 1 1 [???..???)-> BB143 ( cond ) internal bwd BB139 [0138] 1 1 [52D..532)-> BB143 ( cond ) i bwd BB140 [0139] 1 1 [532..537)-> BB143 ( cond ) i bwd BB141 [0140] 1 1 [537..547)-> BB143 ( cond ) i bwd BB142 [0141] 1 1 [547..559) i bwd BB293 [0279] 1 1 [547..548)-> BB295 ( cond ) i bwd BB294 [0280] 1 1 [547..548)-> BB299 (always) i bwd BB295 [0281] 1 1 [547..548)-> BB298 ( cond ) i idxlen bwd BB296 [0282] 1 1 [547..548)-> BB298 ( cond ) i bwd BB297 [0283] 1 1 [547..548)-> BB299 (always) i bwd BB298 [0284] 2 1 [547..548) i bwd BB299 [0285] 1 1 [???..???) internal bwd BB143 [0142] 6 1 [559..564)-> BB191 (always) i bwd BB144 [0143] 1 1 [564..571)-> BB191 ( cond ) i bwd BB145 [0144] 1 1 [571..575)-> BB148 ( cond ) i bwd BB146 [0145] 1 1 [575..57C)-> BB191 ( cond ) i bwd BB147 [0146] 1 1 [57C..584)-> BB191 ( cond ) i bwd BB148 [0147] 2 1 [584..598) i bwd BB302 [0288] 1 1 [584..585)-> BB304 ( cond ) i bwd BB303 [0289] 1 1 [584..585)-> BB308 (always) i bwd BB304 [0290] 1 1 [584..585)-> BB307 ( cond ) i idxlen bwd BB305 [0291] 1 1 [584..585)-> BB307 ( cond ) i bwd BB306 [0292] 1 1 [584..585)-> BB308 (always) i bwd BB307 [0293] 2 1 [584..585) i bwd BB308 [0294] 1 1 [???..???)-> BB191 (always) internal bwd BB149 [0148] 1 1 [598..5A9) i bwd BB311 [0297] 1 1 [598..599)-> BB313 ( cond ) i bwd BB312 [0298] 1 1 [598..599)-> BB317 (always) i bwd BB313 [0299] 1 1 [598..599)-> BB316 ( cond ) i idxlen bwd BB314 [0300] 1 1 [598..599)-> BB316 ( cond ) i bwd BB315 [0301] 1 1 [598..599)-> BB317 (always) i bwd BB316 [0302] 2 1 [598..599) i bwd BB317 [0303] 1 1 [???..???)-> BB191 (always) internal bwd BB150 [0149] 1 1 [5A9..5BA) i bwd BB320 [0306] 1 1 [5A9..5AA)-> BB322 ( cond ) i bwd BB321 [0307] 1 1 [5A9..5AA)-> BB326 (always) i bwd BB322 [0308] 1 1 [5A9..5AA)-> BB325 ( cond ) i idxlen bwd BB323 [0309] 1 1 [5A9..5AA)-> BB325 ( cond ) i bwd BB324 [0310] 1 1 [5A9..5AA)-> BB326 (always) i bwd BB325 [0311] 2 1 [5A9..5AA) i bwd BB326 [0312] 1 1 [???..???)-> BB191 (always) internal bwd BB151 [0150] 1 1 [5BA..5CE) i bwd bwd-target BB328 [0314] 1 1 [000..000)-> BB330 ( cond ) i internal bwd BB329 [0315] 1 1 [000..000)-> BB331 (always) i internal bwd BB330 [0316] 1 1 [000..000) i internal bwd BB331 [0317] 1 1 [???..???) internal bwd BB152 [0151] 3 1 [5CE..5D9)-> BB155 ( cond ) i bwd BB153 [0152] 1 1 [5D9..5E4)-> BB155 ( cond ) i bwd BB154 [0153] 1 1 [5E4..5F1)-> BB151 ( cond ) i bwd bwd-src BB155 [0154] 3 1 [5F1..5FF)-> BB191 ( cond ) i bwd BB156 [0155] 1 1 [5FF..60D)-> BB191 ( cond ) i bwd BB157 [0156] 1 1 [60D..618)-> BB191 (always) i bwd BB158 [0157] 1 1 [618..626)-> BB191 ( cond ) i bwd BB159 [0158] 1 1 [626..634)-> BB191 ( cond ) i bwd BB160 [0159] 1 1 [634..64D) i bwd BB336 [0322] 1 1 [000..000)-> BB338 ( cond ) i internal bwd BB337 [0323] 1 1 [000..000)-> BB339 (always) i internal bwd BB338 [0324] 1 1 [000..000) i internal bwd BB339 [0325] 1 1 [???..???)-> BB191 (always) internal bwd BB161 [0160] 2 1 [64D..65A)-> BB182 ( cond ) i bwd BB162 [0161] 1 1 [65A..665)-> BB165 ( cond ) i bwd BB163 [0162] 1 1 [665..672)-> BB165 ( cond ) i bwd BB164 [0163] 1 1 [672..67A)-> BB174 (always) i bwd BB165 [0164] 2 1 [67A..687)-> BB169 ( cond ) i bwd BB166 [0165] 1 1 [687..694)-> BB169 ( cond ) i bwd BB167 [0166] 1 1 [694..6A3)-> BB169 ( cond ) i bwd BB168 [0167] 1 1 [6A3..6A8)-> BB174 (always) i bwd BB169 [0168] 3 1 [6A8..6B5)-> BB172 ( cond ) i bwd BB170 [0169] 1 1 [6B5..6C2)-> BB172 ( cond ) i bwd BB171 [0170] 1 1 [6C2..6D1)-> BB174 ( cond ) i bwd BB172 [0171] 3 1 [6D1..6DE) i bwd BB344 [0330] 1 1 [6D1..6D2)-> BB346 ( cond ) i bwd BB345 [0331] 1 1 [6D1..6D2)-> BB347 (always) i bwd BB346 [0332] 1 1 [6D1..6D2) i bwd BB347 [0333] 1 1 [???..???)-> BB191 (always) internal bwd BB173 [0172] 1 1 [6DE..6E4) i bwd bwd-target BB174 [0173] 4 1 [6E4..6F4)-> BB176 ( cond ) i bwd BB175 [0174] 1 1 [6F4..701)-> BB173 ( cond ) i bwd bwd-src BB176 [0175] 2 1 [701..707)-> BB178 ( cond ) i bwd BB177 [0176] 1 1 [707..70B) i bwd BB178 [0177] 2 1 [70B..710)-> BB180 ( cond ) i bwd BB179 [0178] 1 1 [710..71A)-> BB181 (always) i bwd BB180 [0179] 1 1 [71A..71B) i bwd BB181 [0180] 2 1 [71B..731)-> BB191 (always) i bwd BB182 [0181] 1 1 [731..744) i bwd BB350 [0336] 1 1 [731..732)-> BB352 ( cond ) i bwd BB351 [0337] 1 1 [731..732)-> BB353 (always) i bwd BB352 [0338] 1 1 [731..732) i bwd BB353 [0339] 1 1 [???..???)-> BB191 ( cond ) i internal bwd BB183 [0182] 1 1 [744..751)-> BB185 ( cond ) i bwd BB184 [0183] 1 1 [751..75E)-> BB187 ( cond ) i bwd BB185 [0184] 2 1 [75E..774) i bwd BB356 [0342] 1 1 [000..000)-> BB358 ( cond ) i internal bwd BB357 [0343] 1 1 [000..000)-> BB359 (always) i internal bwd BB358 [0344] 1 1 [000..000) i internal bwd BB359 [0345] 1 1 [???..???)-> BB187 (always) internal bwd BB186 [0185] 1 1 [774..788) i bwd bwd-target BB361 [0347] 1 1 [000..000)-> BB363 ( cond ) i internal bwd BB362 [0348] 1 1 [000..000)-> BB364 (always) i internal bwd BB363 [0349] 1 1 [000..000) i internal bwd BB364 [0350] 1 1 [???..???) internal bwd BB187 [0186] 3 1 [788..793)-> BB191 ( cond ) i bwd BB188 [0187] 1 1 [793..7A0)-> BB186 ( cond ) i bwd bwd-src BB189 [0188] 1 1 [7A0..7A2)-> BB191 (always) i bwd BB190 [0189] 6 1 [7A2..7AA) i bwd BB367 [0353] 1 1 [7A2..7A3)-> BB369 ( cond ) i bwd BB368 [0354] 1 1 [7A2..7A3)-> BB370 (always) i bwd BB369 [0355] 1 1 [7A2..7A3) i bwd BB370 [0356] 1 1 [???..???) internal bwd BB191 [0190] 21 1 [7AA..7B5)-> BB194 ( cond ) i bwd BB192 [0191] 1 1 [7B5..7C8)-> BB194 ( cond ) i bwd BB193 [0192] 1 1 [7C8..7D1)-> BB102 ( cond ) i bwd bwd-src BB194 [0193] 3 1 [7D1..7DD)-> BB199 ( cond ) i BB195 [0194] 1 1 [7DD..7E1)-> BB199 ( cond ) i BB196 [0195] 1 1 [7E1..7E9)-> BB199 ( cond ) i BB197 [0196] 1 1 [7E9..7F2)-> BB199 ( cond ) i BB198 [0197] 1 1 [7F2..7FF) i BB199 [0198] 5 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 ***** BB01 STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct V41 tmp1 [000010] ----------- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct V75 tmp35 [000019] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct V42 tmp2 [001480] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct V42 tmp2 [001481] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct V42 tmp2 [000020] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] n---------- arg0 +--* OBJ struct [000031] ----------- | \--* ADDR byref [000028] -------N--- | \--* LCL_VAR struct V42 tmp2 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 ------------ BB07 [02D..05B) -> BB48 (always), preds={} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct V77 tmp37 [000065] n---------- \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct V77 tmp37 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 ------------ BB08 [05B..061) -> BB13 (cond), preds={} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB31 (cond), preds={} succs={BB16,BB31} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* EQ int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB16 [0CA..0CF) -> BB48 (always), preds={} succs={BB48} ------------ BB17 [0CF..0D8) -> BB48 (always), preds={} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 ------------ BB31 [137..142) -> BB48 (always), preds={} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 ------------ BB32 [142..150) -> BB48 (cond), preds={} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB33 [150..15E) -> BB48 (cond), preds={} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB37 [183..18E) -> BB48 (cond), preds={} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB46 [1F4..201) -> BB45 (cond), preds={} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB49 [20F..222) -> BB51 (cond), preds={} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={} succs={BB62,BB67} ***** BB61 STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] n---------- arg0 +--* OBJ struct [001160] ----------- | \--* ADDR byref [001157] -------N--- | \--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 ------------ BB78 [2E2..2EE), preds={} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB79 [2EE..30D), preds={} succs={BB213} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct V48 tmp8 [000164] ----------- \--* CNS_INT int 0 ------------ BB213 [000..000) -> BB215 (always), preds={} succs={BB215} ***** BB213 STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] ----------- * NOP void ------------ BB214 [000..000), preds={} succs={BB215} ***** BB214 STMT00326 ( INL09 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class ------------ BB215 [000..000) -> BB216 (always), preds={} succs={BB216} ------------ BB216 [000..000), preds={} succs={BB217} ***** BB216 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct V48 tmp8 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 ***** BB216 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct V48 tmp8 [001556] ----------- \--* CNS_INT int 4 ------------ BB217 [???..???) -> BB97 (cond), preds={} succs={BB80,BB97} ***** BB217 STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct V25 loc21 [000169] ----------- \--* LCL_VAR struct V48 tmp8 ***** BB217 STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct V19 loc15 [000172] ----------- \--* LCL_VAR struct V25 loc21 ***** BB217 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 ***** BB217 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 ------------ BB80 [30D..31E) -> BB97 (cond), preds={} succs={BB81,BB97} ***** BB80 STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 ------------ BB81 [31E..336) -> BB83 (cond), preds={} succs={BB82,BB83} ***** BB81 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 ***** BB81 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 ***** BB81 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 ***** BB81 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB81 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 ------------ BB82 [336..33D), preds={} succs={BB83} ***** BB82 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 ------------ BB83 [33D..348) -> BB85 (cond), preds={} succs={BB84,BB85} ***** BB83 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB83 STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB83 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 ------------ BB84 [348..34B) -> BB86 (always), preds={} succs={BB86} ***** BB84 STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 ------------ BB85 [34B..34D), preds={} succs={BB86} ***** BB85 STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB85 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB86 [34D..355) -> BB88 (cond), preds={} succs={BB87,BB88} ***** BB86 STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB86 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB87 [355..359) -> BB89 (always), preds={} succs={BB89} ***** BB87 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB88 [359..35A), preds={} succs={BB89} ***** BB88 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB89 [35A..35E) -> BB96 (always), preds={} succs={BB96} ***** BB89 STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 ------------ BB90 [35E..362) -> BB97 (cond), preds={} succs={BB91,BB97} ***** BB90 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 ------------ BB91 [362..373) -> BB93 (cond), preds={} succs={BB92,BB93} ***** BB91 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 ***** BB91 STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB92 [373..39A), preds={} succs={BB229} ***** BB92 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* FIELD int :_length [001576] ----------- | \--* ADDR byref [001577] -------N--- | \--* LCL_VAR struct V19 loc15 [001065] ----------- \--* CNS_INT int 2 ***** BB92 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct V78 tmp38 [001581] ----------- \--* CNS_INT int 0 ------------ BB229 [383..384) -> BB231 (cond), preds={} succs={BB230,BB231} ***** BB229 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB230 [383..384) -> BB233 (always), preds={} succs={BB233} ***** BB230 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct V78 tmp38 [001613] ----------- \--* CNS_INT int 0 ------------ BB231 [383..384) -> BB232 (always), preds={} succs={BB232} ------------ BB232 [383..384), preds={} succs={BB233} ***** BB232 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct V78 tmp38 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 ***** BB232 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct V78 tmp38 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB233 [???..???), preds={} succs={BB235} ***** BB233 STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct V68 tmp28 [001586] ----------- \--* LCL_VAR struct V78 tmp38 ***** BB233 STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct V79 tmp39 [001081] n---------- \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 ------------ BB235 [000..000) -> BB237 (cond), preds={} succs={BB236,BB237} ***** BB235 STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB235 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001647] ----------- \--* FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct V79 tmp39 ------------ BB236 [000..000), preds={} succs={BB240} ***** BB236 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* FIELD byref :_reference [001632] ----------- \--* ADDR byref [001631] -------N--- \--* LCL_VAR struct V79 tmp39 ***** BB236 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* FIELD byref :_reference [001634] ----------- \--* ADDR byref [001635] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB236 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB240 [000..000), preds={} succs={BB241} ***** BB240 STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] ----------- * NOP void ------------ BB241 [000..000) -> BB243 (always), preds={} succs={BB243} ***** BB241 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB242 [000..000), preds={} succs={BB245} ***** BB242 STMT00350 ( INL19 @ 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001690] -A--------- * ASG long [001689] D------N--- +--* LCL_VAR long V84 tmp44 [001659] ----------- \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 ------------ BB245 [000..000) -> BB247 (cond), preds={} succs={BB246,BB247} ***** BB245 STMT00347 ( INL21 @ 0x000[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001682] ----------- * JTRUE void [001681] N--------U- \--* GT int [001678] ----------- +--* LCL_VAR long V84 tmp44 [001680] ----------- \--* CNS_INT long 0x400 ------------ BB246 [000..000) -> BB248 (always), preds={} succs={BB248} ***** BB246 STMT00349 ( INL21 @ 0x009[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001688] --C-G------ * CALL r2r_ind void [001685] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001686] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001687] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------ BB247 [000..000), preds={} succs={BB248} ***** BB247 STMT00348 ( INL21 @ 0x012[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001684] --C-G------ * CALL r2r_ind void [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001683] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------ BB248 [???..???), preds={} succs={BB243} ------------ BB243 [???..???) -> BB238 (always), preds={} succs={BB238} ------------ BB237 [000..000), preds={} succs={BB238} ***** BB237 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() ------------ BB238 [???..???), preds={} succs={BB257} ***** BB238 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct V85 tmp45 [001693] ----------- \--* CNS_INT int 0 ------------ BB257 [391..392) -> BB259 (cond), preds={} succs={BB258,BB259} ***** BB257 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB258 [391..392) -> BB261 (always), preds={} succs={BB261} ***** BB258 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct V85 tmp45 [001725] ----------- \--* CNS_INT int 0 ------------ BB259 [391..392) -> BB260 (always), preds={} succs={BB260} ------------ BB260 [391..392), preds={} succs={BB261} ***** BB260 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct V85 tmp45 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 ***** BB260 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct V85 tmp45 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB261 [???..???), preds={} succs={BB93} ***** BB261 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct V19 loc15 [001698] ----------- \--* LCL_VAR struct V85 tmp45 ------------ BB93 [39A..3AE) -> BB95 (cond), preds={} succs={BB94,BB95} ***** BB93 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* FIELD int :_length [001023] ----------- | | \--* ADDR byref [001022] -------N--- | | \--* LCL_VAR struct V19 loc15 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* FIELD byref :_reference [001027] ----------- | | \--* ADDR byref [001026] -------N--- | | \--* LCL_VAR struct V19 loc15 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB93 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 ------------ BB94 [3AE..3BB), preds={} succs={BB95} ***** BB94 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 ***** BB94 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 ------------ BB95 [3BB..3C2), preds={} succs={BB96} ***** BB95 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 ------------ BB96 [3C2..3C8) -> BB90 (cond), preds={} succs={BB97,BB90} ***** BB96 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB97 [3C8..3D0) -> BB101 (cond), preds={} succs={BB98,BB101} ***** BB97 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 ------------ BB98 [3D0..3D4) -> BB101 (cond), preds={} succs={BB99,BB101} ***** BB98 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 ------------ BB99 [3D4..3DC) -> BB101 (cond), preds={} succs={BB100,BB101} ***** BB99 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 ------------ BB100 [3DC..3E8), preds={} succs={BB264} ***** BB100 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB264 [3DC..3DD) -> BB266 (cond), preds={} succs={BB265,BB266} ***** BB264 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* NE int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB265 [3DC..3DD) -> BB270 (always), preds={} succs={BB270} ------------ BB266 [3DC..3DD) -> BB269 (cond), preds={} succs={BB267,BB269} ***** BB266 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 ***** BB266 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB267 [3DC..3DD) -> BB269 (cond), preds={} succs={BB268,BB269} ***** BB267 STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 ***** BB267 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 ------------ BB268 [3DC..3DD) -> BB270 (always), preds={} succs={BB270} ***** BB268 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 ***** BB268 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB268 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB269 [3DC..3DD), preds={} succs={BB270} ***** BB269 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------ BB270 [???..???), preds={} succs={BB101} ------------ BB101 [3E8..401) -> BB191 (always), preds={} succs={BB191} ***** BB101 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 ***** BB101 STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct V90 tmp50 [000193] n---------- \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB101 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct V90 tmp50 ***** BB101 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 ***** BB101 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB102 [401..406) -> BB117 (cond), preds={} succs={BB103,BB117} ***** BB102 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 ------------ BB103 [406..40C) -> BB116 (cond), preds={} succs={BB104,BB116} ***** BB103 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 ------------ BB104 [40C..412) -> BB116 (cond), preds={} succs={BB105,BB116} ***** BB104 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 ------------ BB105 [412..418) -> BB116 (cond), preds={} succs={BB106,BB116} ***** BB105 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 ------------ BB106 [418..41A) -> BB117 (always), preds={} succs={BB117} ------------ BB107 [41A..420) -> BB109 (cond), preds={} succs={BB108,BB109} ***** BB107 STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB107 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 ------------ BB108 [420..424) -> BB110 (always), preds={} succs={BB110} ***** BB108 STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB108 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 ------------ BB109 [424..42C), preds={} succs={BB110} ***** BB109 STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB109 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 ***** BB109 STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB109 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB110 [42C..435), preds={} succs={BB273} ***** BB110 STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 ------------ BB273 [000..000) -> BB275 (cond), preds={} succs={BB274,BB275} ***** BB273 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB273 STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB273 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 ------------ BB274 [000..000) -> BB276 (always), preds={} succs={BB276} ***** BB274 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB274 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB274 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB275 [000..000), preds={} succs={BB276} ***** BB275 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------ BB276 [???..???) -> BB115 (cond), preds={} succs={BB111,BB115} ***** BB276 STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 ------------ BB111 [435..43A) -> BB115 (cond), preds={} succs={BB112,BB115} ***** BB111 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 ------------ BB112 [43A..43F) -> BB115 (cond), preds={} succs={BB113,BB115} ***** BB112 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 ------------ BB113 [43F..44F) -> BB115 (cond), preds={} succs={BB114,BB115} ***** BB113 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* FIELD int :_length [000884] ----------- | | \--* ADDR byref [000883] -------N--- | | \--* LCL_VAR struct V19 loc15 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* FIELD byref :_reference [000888] ----------- | | \--* ADDR byref [000887] -------N--- | | \--* LCL_VAR struct V19 loc15 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 ------------ BB114 [44F..461), preds={} succs={BB279} ***** BB114 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB279 [44F..450) -> BB281 (cond), preds={} succs={BB280,BB281} ***** BB279 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* NE int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB280 [44F..450) -> BB285 (always), preds={} succs={BB285} ------------ BB281 [44F..450) -> BB284 (cond), preds={} succs={BB282,BB284} ***** BB281 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 ***** BB281 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB282 [44F..450) -> BB284 (cond), preds={} succs={BB283,BB284} ***** BB282 STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 ***** BB282 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 ------------ BB283 [44F..450) -> BB285 (always), preds={} succs={BB285} ***** BB283 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB283 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB284 [44F..450), preds={} succs={BB285} ***** BB284 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------ BB285 [???..???), preds={} succs={BB115} ***** BB285 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 ------------ BB115 [461..46D), preds={} succs={BB116} ***** BB115 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 ***** BB115 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 ------------ BB116 [46D..472) -> BB107 (cond), preds={} succs={BB117,BB107} ***** BB116 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 ------------ BB117 [472..478) -> BB122 (cond), preds={} succs={BB118,BB122} ***** BB117 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 ------------ BB118 [478..49A) -> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch), preds={} succs={BB119,BB126,BB150,BB152,BB190} ***** BB118 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 ------------ BB119 [49A..4B8) -> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch), preds={} succs={BB120,BB126,BB144,BB190,BB191} ***** BB119 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 ------------ BB120 [4B8..4C1) -> BB161 (cond), preds={} succs={BB121,BB161} ***** BB120 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 ------------ BB121 [4C1..4C6) -> BB190 (always), preds={} succs={BB190} ------------ BB122 [4C6..4CF) -> BB158 (cond), preds={} succs={BB123,BB158} ***** BB122 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 ------------ BB123 [4CF..4D8) -> BB161 (cond), preds={} succs={BB124,BB161} ***** BB123 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 ------------ BB124 [4D8..4E4) -> BB149 (cond), preds={} succs={BB125,BB149} ***** BB124 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* EQ int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB125 [4E4..4E9) -> BB190 (always), preds={} succs={BB190} ------------ BB126 [4E9..4EE) -> BB131 (cond), preds={} succs={BB127,BB131} ***** BB126 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 ------------ BB127 [4EE..4F9) -> BB129 (cond), preds={} succs={BB128,BB129} ***** BB127 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 ***** BB127 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB128 [4F9..4FC) -> BB130 (always), preds={} succs={BB130} ***** BB128 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 ------------ BB129 [4FC..4FE), preds={} succs={BB130} ***** BB129 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 ------------ BB130 [4FE..502) -> BB137 (always), preds={} succs={BB137} ***** BB130 STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB131 [502..507) -> BB135 (cond), preds={} succs={BB132,BB135} ***** BB131 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 ------------ BB132 [507..50C) -> BB134 (cond), preds={} succs={BB133,BB134} ***** BB132 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB133 [50C..50F) -> BB136 (always), preds={} succs={BB136} ***** BB133 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 ------------ BB134 [50F..513) -> BB136 (always), preds={} succs={BB136} ***** BB134 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 ------------ BB135 [513..51B), preds={} succs={BB136} ***** BB135 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB135 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 ***** BB135 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB136 [51B..51D), preds={} succs={BB137} ***** BB136 STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB137 [51D..521) -> BB143 (cond), preds={} succs={BB138,BB143} ***** BB137 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 ------------ BB138 [521..52D), preds={} succs={BB287} ------------ BB287 [521..522) -> BB289 (cond), preds={} succs={BB288,BB289} ***** BB287 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 ***** BB287 STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 ***** BB287 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 ------------ BB288 [521..522) -> BB290 (always), preds={} succs={BB290} ***** BB288 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 ***** BB288 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB288 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB289 [521..522), preds={} succs={BB290} ***** BB289 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB290 [???..???) -> BB143 (cond), preds={} succs={BB139,BB143} ***** BB290 STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 ------------ BB139 [52D..532) -> BB143 (cond), preds={} succs={BB140,BB143} ***** BB139 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 ------------ BB140 [532..537) -> BB143 (cond), preds={} succs={BB141,BB143} ***** BB140 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 ------------ BB141 [537..547) -> BB143 (cond), preds={} succs={BB142,BB143} ***** BB141 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* FIELD int :_length [000691] ----------- | | \--* ADDR byref [000690] -------N--- | | \--* LCL_VAR struct V19 loc15 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* FIELD byref :_reference [000695] ----------- | | \--* ADDR byref [000694] -------N--- | | \--* LCL_VAR struct V19 loc15 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 ------------ BB142 [547..559), preds={} succs={BB293} ***** BB142 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB293 [547..548) -> BB295 (cond), preds={} succs={BB294,BB295} ***** BB293 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* NE int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB294 [547..548) -> BB299 (always), preds={} succs={BB299} ------------ BB295 [547..548) -> BB298 (cond), preds={} succs={BB296,BB298} ***** BB295 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 ***** BB295 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB296 [547..548) -> BB298 (cond), preds={} succs={BB297,BB298} ***** BB296 STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 ***** BB296 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 ------------ BB297 [547..548) -> BB299 (always), preds={} succs={BB299} ***** BB297 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 ***** BB297 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB297 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB298 [547..548), preds={} succs={BB299} ***** BB298 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------ BB299 [???..???), preds={} succs={BB143} ***** BB299 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 ------------ BB143 [559..564) -> BB191 (always), preds={} succs={BB191} ***** BB143 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 ------------ BB144 [564..571) -> BB191 (cond), preds={} succs={BB145,BB191} ***** BB144 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 ------------ BB145 [571..575) -> BB148 (cond), preds={} succs={BB146,BB148} ***** BB145 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 ------------ BB146 [575..57C) -> BB191 (cond), preds={} succs={BB147,BB191} ***** BB146 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB147 [57C..584) -> BB191 (cond), preds={} succs={BB148,BB191} ***** BB147 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 ------------ BB148 [584..598), preds={} succs={BB302} ***** BB148 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB302 [584..585) -> BB304 (cond), preds={} succs={BB303,BB304} ***** BB302 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* NE int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB303 [584..585) -> BB308 (always), preds={} succs={BB308} ------------ BB304 [584..585) -> BB307 (cond), preds={} succs={BB305,BB307} ***** BB304 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 ***** BB304 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB305 [584..585) -> BB307 (cond), preds={} succs={BB306,BB307} ***** BB305 STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 ***** BB305 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 ------------ BB306 [584..585) -> BB308 (always), preds={} succs={BB308} ***** BB306 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 ***** BB306 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB306 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB307 [584..585), preds={} succs={BB308} ***** BB307 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------ BB308 [???..???) -> BB191 (always), preds={} succs={BB191} ***** BB308 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 ------------ BB149 [598..5A9), preds={} succs={BB311} ***** BB149 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB311 [598..599) -> BB313 (cond), preds={} succs={BB312,BB313} ***** BB311 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* NE int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB312 [598..599) -> BB317 (always), preds={} succs={BB317} ------------ BB313 [598..599) -> BB316 (cond), preds={} succs={BB314,BB316} ***** BB313 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 ***** BB313 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB314 [598..599) -> BB316 (cond), preds={} succs={BB315,BB316} ***** BB314 STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 ***** BB314 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 ------------ BB315 [598..599) -> BB317 (always), preds={} succs={BB317} ***** BB315 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 ***** BB315 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB315 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB316 [598..599), preds={} succs={BB317} ***** BB316 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------ BB317 [???..???) -> BB191 (always), preds={} succs={BB191} ------------ BB150 [5A9..5BA), preds={} succs={BB320} ***** BB150 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB320 [5A9..5AA) -> BB322 (cond), preds={} succs={BB321,BB322} ***** BB320 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* NE int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB321 [5A9..5AA) -> BB326 (always), preds={} succs={BB326} ------------ BB322 [5A9..5AA) -> BB325 (cond), preds={} succs={BB323,BB325} ***** BB322 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 ***** BB322 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB323 [5A9..5AA) -> BB325 (cond), preds={} succs={BB324,BB325} ***** BB323 STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 ***** BB323 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 ------------ BB324 [5A9..5AA) -> BB326 (always), preds={} succs={BB326} ***** BB324 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 ***** BB324 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB324 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB325 [5A9..5AA), preds={} succs={BB326} ***** BB325 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------ BB326 [???..???) -> BB191 (always), preds={} succs={BB191} ------------ BB151 [5BA..5CE), preds={} succs={BB328} ***** BB151 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB151 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 ***** BB151 STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 ------------ BB328 [000..000) -> BB330 (cond), preds={} succs={BB329,BB330} ***** BB328 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 ***** BB328 STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 ***** BB328 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 ------------ BB329 [000..000) -> BB331 (always), preds={} succs={BB331} ***** BB329 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 ***** BB329 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB329 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB330 [000..000), preds={} succs={BB331} ***** BB330 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------ BB331 [???..???), preds={} succs={BB152} ------------ BB152 [5CE..5D9) -> BB155 (cond), preds={} succs={BB153,BB155} ***** BB152 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB153 [5D9..5E4) -> BB155 (cond), preds={} succs={BB154,BB155} ***** BB153 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 ------------ BB154 [5E4..5F1) -> BB151 (cond), preds={} succs={BB155,BB151} ***** BB154 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB155 [5F1..5FF) -> BB191 (cond), preds={} succs={BB156,BB191} ***** BB155 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB156 [5FF..60D) -> BB191 (cond), preds={} succs={BB157,BB191} ***** BB156 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 ------------ BB157 [60D..618) -> BB191 (always), preds={} succs={BB191} ***** BB157 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 ------------ BB158 [618..626) -> BB191 (cond), preds={} succs={BB159,BB191} ***** BB158 STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB159 [626..634) -> BB191 (cond), preds={} succs={BB160,BB191} ***** BB159 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 ------------ BB160 [634..64D), preds={} succs={BB336} ***** BB160 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB160 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 ***** BB160 STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 ------------ BB336 [000..000) -> BB338 (cond), preds={} succs={BB337,BB338} ***** BB336 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 ***** BB336 STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 ***** BB336 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 ------------ BB337 [000..000) -> BB339 (always), preds={} succs={BB339} ***** BB337 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 ***** BB337 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB337 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB338 [000..000), preds={} succs={BB339} ***** BB338 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------ BB339 [???..???) -> BB191 (always), preds={} succs={BB191} ------------ BB161 [64D..65A) -> BB182 (cond), preds={} succs={BB162,BB182} ***** BB161 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 ***** BB161 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 ***** BB161 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 ------------ BB162 [65A..665) -> BB165 (cond), preds={} succs={BB163,BB165} ***** BB162 STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB163 [665..672) -> BB165 (cond), preds={} succs={BB164,BB165} ***** BB163 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* NE int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 ------------ BB164 [672..67A) -> BB174 (always), preds={} succs={BB174} ***** BB164 STMT00124 ( 0x672[E-] ... 0x676 ) [000580] -A--------- * ASG int [000579] D------N--- +--* LCL_VAR int V38 loc34 [000578] ----------- \--* ADD int [000576] ----------- +--* LCL_VAR int V38 loc34 [000577] ----------- \--* CNS_INT int 1 ------------ BB165 [67A..687) -> BB169 (cond), preds={} succs={BB166,BB169} ***** BB165 STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB166 [687..694) -> BB169 (cond), preds={} succs={BB167,BB169} ***** BB166 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 ------------ BB167 [694..6A3) -> BB169 (cond), preds={} succs={BB168,BB169} ***** BB167 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 ------------ BB168 [6A3..6A8) -> BB174 (always), preds={} succs={BB174} ***** BB168 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 ------------ BB169 [6A8..6B5) -> BB172 (cond), preds={} succs={BB170,BB172} ***** BB169 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB170 [6B5..6C2) -> BB172 (cond), preds={} succs={BB171,BB172} ***** BB170 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 ------------ BB171 [6C2..6D1) -> BB174 (cond), preds={} succs={BB172,BB174} ***** BB171 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 ------------ BB172 [6D1..6DE), preds={} succs={BB344} ------------ BB344 [6D1..6D2) -> BB346 (cond), preds={} succs={BB345,BB346} ***** BB344 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 ***** BB344 STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 ***** BB344 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 ------------ BB345 [6D1..6D2) -> BB347 (always), preds={} succs={BB347} ***** BB345 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 ***** BB345 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB345 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB346 [6D1..6D2), preds={} succs={BB347} ***** BB346 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB347 [???..???) -> BB191 (always), preds={} succs={BB191} ------------ BB173 [6DE..6E4), preds={} succs={BB174} ***** BB173 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 ------------ BB174 [6E4..6F4) -> BB176 (cond), preds={} succs={BB175,BB176} ***** BB174 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 ***** BB174 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB174 STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB175 [6F4..701) -> BB173 (cond), preds={} succs={BB176,BB173} ***** BB175 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 ------------ BB176 [701..707) -> BB178 (cond), preds={} succs={BB177,BB178} ***** BB176 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 ------------ BB177 [707..70B), preds={} succs={BB178} ***** BB177 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 ------------ BB178 [70B..710) -> BB180 (cond), preds={} succs={BB179,BB180} ***** BB178 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 ------------ BB179 [710..71A) -> BB181 (always), preds={} succs={BB181} ***** BB179 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB180 [71A..71B), preds={} succs={BB181} ***** BB180 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 ------------ BB181 [71B..731) -> BB191 (always), preds={} succs={BB191} ***** BB181 STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 ***** BB181 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 ***** BB181 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 ------------ BB182 [731..744), preds={} succs={BB350} ------------ BB350 [731..732) -> BB352 (cond), preds={} succs={BB351,BB352} ***** BB350 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 ***** BB350 STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 ***** BB350 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 ------------ BB351 [731..732) -> BB353 (always), preds={} succs={BB353} ***** BB351 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 ***** BB351 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB351 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB352 [731..732), preds={} succs={BB353} ***** BB352 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB353 [???..???) -> BB191 (cond), preds={} succs={BB183,BB191} ***** BB353 STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB183 [744..751) -> BB185 (cond), preds={} succs={BB184,BB185} ***** BB183 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 ------------ BB184 [751..75E) -> BB187 (cond), preds={} succs={BB185,BB187} ***** BB184 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 ------------ BB185 [75E..774), preds={} succs={BB356} ***** BB185 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB185 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 ***** BB185 STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 ------------ BB356 [000..000) -> BB358 (cond), preds={} succs={BB357,BB358} ***** BB356 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 ***** BB356 STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 ***** BB356 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 ------------ BB357 [000..000) -> BB359 (always), preds={} succs={BB359} ***** BB357 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 ***** BB357 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB357 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB358 [000..000), preds={} succs={BB359} ***** BB358 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------ BB359 [???..???) -> BB187 (always), preds={} succs={BB187} ------------ BB186 [774..788), preds={} succs={BB361} ***** BB186 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB186 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 ***** BB186 STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 ------------ BB361 [000..000) -> BB363 (cond), preds={} succs={BB362,BB363} ***** BB361 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 ***** BB361 STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 ***** BB361 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 ------------ BB362 [000..000) -> BB364 (always), preds={} succs={BB364} ***** BB362 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 ***** BB362 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB362 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB363 [000..000), preds={} succs={BB364} ***** BB363 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------ BB364 [???..???), preds={} succs={BB187} ------------ BB187 [788..793) -> BB191 (cond), preds={} succs={BB188,BB191} ***** BB187 STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB188 [793..7A0) -> BB186 (cond), preds={} succs={BB189,BB186} ***** BB188 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 ------------ BB189 [7A0..7A2) -> BB191 (always), preds={} succs={BB191} ------------ BB190 [7A2..7AA), preds={} succs={BB367} ------------ BB367 [7A2..7A3) -> BB369 (cond), preds={} succs={BB368,BB369} ***** BB367 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 ***** BB367 STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 ***** BB367 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 ------------ BB368 [7A2..7A3) -> BB370 (always), preds={} succs={BB370} ***** BB368 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 ***** BB368 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB368 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB369 [7A2..7A3), preds={} succs={BB370} ***** BB369 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB370 [???..???), preds={} succs={BB191} ------------ BB191 [7AA..7B5) -> BB194 (cond), preds={} succs={BB192,BB194} ***** BB191 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB192 [7B5..7C8) -> BB194 (cond), preds={} succs={BB193,BB194} ***** BB192 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB192 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 ***** BB192 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 ***** BB192 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB192 STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 ------------ BB193 [7C8..7D1) -> BB102 (cond), preds={} succs={BB194,BB102} ***** BB193 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 ------------ BB194 [7D1..7DD) -> BB199 (cond), preds={} succs={BB195,BB199} ***** BB194 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 ***** BB194 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 ------------ BB195 [7DD..7E1) -> BB199 (cond), preds={} succs={BB196,BB199} ***** BB195 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 ------------ BB196 [7E1..7E9) -> BB199 (cond), preds={} succs={BB197,BB199} ***** BB196 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 ------------ BB197 [7E9..7F2) -> BB199 (cond), preds={} succs={BB198,BB199} ***** BB197 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 ------------ BB198 [7F2..7FF), preds={} succs={BB199} ***** BB198 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB199 [7FF..800) (return), preds={} succs={} ***** BB199 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Allocate Objects no newobjs in this method; punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 1 [022..025)-> BB06 (always) i BB05 [0004] 1 1 [025..026) i BB06 [0005] 3 1 [026..02D) i BB07 [0006] 2 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 1 [0C1..0CA)-> BB31 ( cond ) i bwd BB16 [0015] 1 1 [0CA..0CF)-> BB48 (always) i bwd BB17 [0016] 1 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 1 [0E0..0E2) i bwd BB20 [0019] 2 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 1 [11E..121) i bwd BB29 [0028] 2 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 1 [12C..137)-> BB48 (always) i bwd BB31 [0030] 1 1 [137..142)-> BB48 (always) i bwd BB32 [0031] 3 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 1 [201..204) i bwd BB48 [0047] 27 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 1 [233..235) i bwd BB53 [0052] 2 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 1 [24A..24D) i bwd BB57 [0056] 3 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 1 [26E..26F) i bwd BB61 [0060] 2 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 1 [2A0..2A7) i BB66 [0065] 2 1 [2A7..2AE) i BB67 [0066] 3 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 1 [2B5..2B8) i BB70 [0069] 2 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 1 [2C0..2C3) i BB73 [0072] 2 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 1 [2DC..2E2) i BB78 [0077] 2 1 [2E2..2EE) i BB79 [0078] 2 1 [2EE..30D) i BB213 [0207] 1 1 [000..000)-> BB215 (always) i internal BB214 [0208] 1 1 [000..000) i internal BB215 [0209] 2 1 [000..000)-> BB216 (always) i internal BB216 [0211] 2 1 [000..000) i internal BB217 [0212] 1 1 [???..???)-> BB97 ( cond ) internal BB80 [0079] 1 1 [30D..31E)-> BB97 ( cond ) i idxlen BB81 [0080] 1 1 [31E..336)-> BB83 ( cond ) i idxlen BB82 [0081] 1 1 [336..33D) i idxlen BB83 [0082] 2 1 [33D..348)-> BB85 ( cond ) i BB84 [0083] 1 1 [348..34B)-> BB86 (always) i BB85 [0084] 1 1 [34B..34D) i BB86 [0085] 2 1 [34D..355)-> BB88 ( cond ) i BB87 [0086] 1 1 [355..359)-> BB89 (always) i BB88 [0087] 1 1 [359..35A) i BB89 [0088] 2 1 [35A..35E)-> BB96 (always) i BB90 [0089] 1 1 [35E..362)-> BB97 ( cond ) i bwd bwd-target BB91 [0090] 1 1 [362..373)-> BB93 ( cond ) i bwd BB92 [0091] 1 1 [373..39A) i bwd BB229 [0218] 1 1 [383..384)-> BB231 ( cond ) i bwd BB230 [0219] 1 1 [383..384)-> BB233 (always) i bwd BB231 [0220] 1 1 [383..384)-> BB232 (always) i bwd BB232 [0223] 3 1 [383..384) i idxlen bwd BB233 [0224] 1 1 [???..???) internal bwd BB235 [0226] 1 1 [000..000)-> BB237 ( cond ) i internal bwd BB236 [0227] 1 1 [000..000) i internal bwd BB240 [0231] 1 1 [000..000) i internal bwd BB241 [0232] 1 1 [000..000)-> BB243 (always) i internal bwd BB242 [0233] 1 1 [000..000) i internal bwd BB245 [0236] 1 1 [000..000)-> BB247 ( cond ) i internal bwd BB246 [0237] 1 1 [000..000)-> BB248 (always) i internal bwd BB247 [0238] 1 1 [000..000) i internal bwd BB248 [0239] 1 1 [???..???) internal bwd BB243 [0234] 1 1 [???..???)-> BB238 (always) internal bwd BB237 [0228] 1 1 [000..000) i internal bwd BB238 [0229] 1 1 [???..???) i internal bwd BB257 [0241] 1 1 [391..392)-> BB259 ( cond ) i bwd BB258 [0242] 1 1 [391..392)-> BB261 (always) i bwd BB259 [0243] 1 1 [391..392)-> BB260 (always) i bwd BB260 [0246] 3 1 [391..392) i idxlen bwd BB261 [0247] 1 1 [???..???) internal bwd BB93 [0092] 2 1 [39A..3AE)-> BB95 ( cond ) i bwd BB94 [0093] 1 1 [3AE..3BB) i idxlen bwd BB95 [0094] 2 1 [3BB..3C2) i bwd BB96 [0095] 2 1 [3C2..3C8)-> BB90 ( cond ) i bwd bwd-src BB97 [0096] 4 1 [3C8..3D0)-> BB101 ( cond ) i BB98 [0097] 1 1 [3D0..3D4)-> BB101 ( cond ) i BB99 [0098] 1 1 [3D4..3DC)-> BB101 ( cond ) i BB100 [0099] 1 1 [3DC..3E8) i BB264 [0250] 1 1 [3DC..3DD)-> BB266 ( cond ) i BB265 [0251] 1 1 [3DC..3DD)-> BB270 (always) i BB266 [0252] 1 1 [3DC..3DD)-> BB269 ( cond ) i idxlen BB267 [0253] 1 1 [3DC..3DD)-> BB269 ( cond ) i BB268 [0254] 1 1 [3DC..3DD)-> BB270 (always) i BB269 [0255] 2 1 [3DC..3DD) i BB270 [0256] 1 1 [???..???) internal BB101 [0100] 4 1 [3E8..401)-> BB191 (always) i BB102 [0101] 1 1 [401..406)-> BB117 ( cond ) i bwd bwd-target BB103 [0102] 1 1 [406..40C)-> BB116 ( cond ) i bwd BB104 [0103] 1 1 [40C..412)-> BB116 ( cond ) i bwd BB105 [0104] 1 1 [412..418)-> BB116 ( cond ) i bwd BB106 [0105] 1 1 [418..41A)-> BB117 (always) i bwd BB107 [0106] 1 1 [41A..420)-> BB109 ( cond ) i bwd bwd-target BB108 [0107] 1 1 [420..424)-> BB110 (always) i bwd BB109 [0108] 1 1 [424..42C) i bwd BB110 [0109] 2 1 [42C..435) i bwd BB273 [0259] 1 1 [000..000)-> BB275 ( cond ) i internal bwd BB274 [0260] 1 1 [000..000)-> BB276 (always) i internal bwd BB275 [0261] 1 1 [000..000) i internal bwd BB276 [0262] 1 1 [???..???)-> BB115 ( cond ) internal bwd BB111 [0110] 1 1 [435..43A)-> BB115 ( cond ) i bwd BB112 [0111] 1 1 [43A..43F)-> BB115 ( cond ) i bwd BB113 [0112] 1 1 [43F..44F)-> BB115 ( cond ) i bwd BB114 [0113] 1 1 [44F..461) i bwd BB279 [0265] 1 1 [44F..450)-> BB281 ( cond ) i bwd BB280 [0266] 1 1 [44F..450)-> BB285 (always) i bwd BB281 [0267] 1 1 [44F..450)-> BB284 ( cond ) i idxlen bwd BB282 [0268] 1 1 [44F..450)-> BB284 ( cond ) i bwd BB283 [0269] 1 1 [44F..450)-> BB285 (always) i bwd BB284 [0270] 2 1 [44F..450) i bwd BB285 [0271] 1 1 [???..???) internal bwd BB115 [0114] 5 1 [461..46D) i bwd BB116 [0115] 4 1 [46D..472)-> BB107 ( cond ) i bwd bwd-src BB117 [0116] 3 1 [472..478)-> BB122 ( cond ) i bwd BB118 [0117] 1 1 [478..49A)-> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch) i bwd BB119 [0118] 1 1 [49A..4B8)-> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch) i bwd BB120 [0119] 1 1 [4B8..4C1)-> BB161 ( cond ) i bwd BB121 [0120] 1 1 [4C1..4C6)-> BB190 (always) i bwd BB122 [0121] 1 1 [4C6..4CF)-> BB158 ( cond ) i bwd BB123 [0122] 1 1 [4CF..4D8)-> BB161 ( cond ) i bwd BB124 [0123] 1 1 [4D8..4E4)-> BB149 ( cond ) i bwd BB125 [0124] 1 1 [4E4..4E9)-> BB190 (always) i bwd BB126 [0125] 2 1 [4E9..4EE)-> BB131 ( cond ) i bwd BB127 [0126] 1 1 [4EE..4F9)-> BB129 ( cond ) i bwd BB128 [0127] 1 1 [4F9..4FC)-> BB130 (always) i bwd BB129 [0128] 1 1 [4FC..4FE) i bwd BB130 [0129] 2 1 [4FE..502)-> BB137 (always) i bwd BB131 [0130] 1 1 [502..507)-> BB135 ( cond ) i bwd BB132 [0131] 1 1 [507..50C)-> BB134 ( cond ) i bwd BB133 [0132] 1 1 [50C..50F)-> BB136 (always) i bwd BB134 [0133] 1 1 [50F..513)-> BB136 (always) i bwd BB135 [0134] 1 1 [513..51B) i bwd BB136 [0135] 3 1 [51B..51D) i bwd BB137 [0136] 2 1 [51D..521)-> BB143 ( cond ) i bwd BB138 [0137] 1 1 [521..52D) i bwd BB287 [0273] 1 1 [521..522)-> BB289 ( cond ) i bwd BB288 [0274] 1 1 [521..522)-> BB290 (always) i bwd BB289 [0275] 1 1 [521..522) i bwd BB290 [0276] 1 1 [???..???)-> BB143 ( cond ) internal bwd BB139 [0138] 1 1 [52D..532)-> BB143 ( cond ) i bwd BB140 [0139] 1 1 [532..537)-> BB143 ( cond ) i bwd BB141 [0140] 1 1 [537..547)-> BB143 ( cond ) i bwd BB142 [0141] 1 1 [547..559) i bwd BB293 [0279] 1 1 [547..548)-> BB295 ( cond ) i bwd BB294 [0280] 1 1 [547..548)-> BB299 (always) i bwd BB295 [0281] 1 1 [547..548)-> BB298 ( cond ) i idxlen bwd BB296 [0282] 1 1 [547..548)-> BB298 ( cond ) i bwd BB297 [0283] 1 1 [547..548)-> BB299 (always) i bwd BB298 [0284] 2 1 [547..548) i bwd BB299 [0285] 1 1 [???..???) internal bwd BB143 [0142] 6 1 [559..564)-> BB191 (always) i bwd BB144 [0143] 1 1 [564..571)-> BB191 ( cond ) i bwd BB145 [0144] 1 1 [571..575)-> BB148 ( cond ) i bwd BB146 [0145] 1 1 [575..57C)-> BB191 ( cond ) i bwd BB147 [0146] 1 1 [57C..584)-> BB191 ( cond ) i bwd BB148 [0147] 2 1 [584..598) i bwd BB302 [0288] 1 1 [584..585)-> BB304 ( cond ) i bwd BB303 [0289] 1 1 [584..585)-> BB308 (always) i bwd BB304 [0290] 1 1 [584..585)-> BB307 ( cond ) i idxlen bwd BB305 [0291] 1 1 [584..585)-> BB307 ( cond ) i bwd BB306 [0292] 1 1 [584..585)-> BB308 (always) i bwd BB307 [0293] 2 1 [584..585) i bwd BB308 [0294] 1 1 [???..???)-> BB191 (always) internal bwd BB149 [0148] 1 1 [598..5A9) i bwd BB311 [0297] 1 1 [598..599)-> BB313 ( cond ) i bwd BB312 [0298] 1 1 [598..599)-> BB317 (always) i bwd BB313 [0299] 1 1 [598..599)-> BB316 ( cond ) i idxlen bwd BB314 [0300] 1 1 [598..599)-> BB316 ( cond ) i bwd BB315 [0301] 1 1 [598..599)-> BB317 (always) i bwd BB316 [0302] 2 1 [598..599) i bwd BB317 [0303] 1 1 [???..???)-> BB191 (always) internal bwd BB150 [0149] 1 1 [5A9..5BA) i bwd BB320 [0306] 1 1 [5A9..5AA)-> BB322 ( cond ) i bwd BB321 [0307] 1 1 [5A9..5AA)-> BB326 (always) i bwd BB322 [0308] 1 1 [5A9..5AA)-> BB325 ( cond ) i idxlen bwd BB323 [0309] 1 1 [5A9..5AA)-> BB325 ( cond ) i bwd BB324 [0310] 1 1 [5A9..5AA)-> BB326 (always) i bwd BB325 [0311] 2 1 [5A9..5AA) i bwd BB326 [0312] 1 1 [???..???)-> BB191 (always) internal bwd BB151 [0150] 1 1 [5BA..5CE) i bwd bwd-target BB328 [0314] 1 1 [000..000)-> BB330 ( cond ) i internal bwd BB329 [0315] 1 1 [000..000)-> BB331 (always) i internal bwd BB330 [0316] 1 1 [000..000) i internal bwd BB331 [0317] 1 1 [???..???) internal bwd BB152 [0151] 3 1 [5CE..5D9)-> BB155 ( cond ) i bwd BB153 [0152] 1 1 [5D9..5E4)-> BB155 ( cond ) i bwd BB154 [0153] 1 1 [5E4..5F1)-> BB151 ( cond ) i bwd bwd-src BB155 [0154] 3 1 [5F1..5FF)-> BB191 ( cond ) i bwd BB156 [0155] 1 1 [5FF..60D)-> BB191 ( cond ) i bwd BB157 [0156] 1 1 [60D..618)-> BB191 (always) i bwd BB158 [0157] 1 1 [618..626)-> BB191 ( cond ) i bwd BB159 [0158] 1 1 [626..634)-> BB191 ( cond ) i bwd BB160 [0159] 1 1 [634..64D) i bwd BB336 [0322] 1 1 [000..000)-> BB338 ( cond ) i internal bwd BB337 [0323] 1 1 [000..000)-> BB339 (always) i internal bwd BB338 [0324] 1 1 [000..000) i internal bwd BB339 [0325] 1 1 [???..???)-> BB191 (always) internal bwd BB161 [0160] 2 1 [64D..65A)-> BB182 ( cond ) i bwd BB162 [0161] 1 1 [65A..665)-> BB165 ( cond ) i bwd BB163 [0162] 1 1 [665..672)-> BB165 ( cond ) i bwd BB164 [0163] 1 1 [672..67A)-> BB174 (always) i bwd BB165 [0164] 2 1 [67A..687)-> BB169 ( cond ) i bwd BB166 [0165] 1 1 [687..694)-> BB169 ( cond ) i bwd BB167 [0166] 1 1 [694..6A3)-> BB169 ( cond ) i bwd BB168 [0167] 1 1 [6A3..6A8)-> BB174 (always) i bwd BB169 [0168] 3 1 [6A8..6B5)-> BB172 ( cond ) i bwd BB170 [0169] 1 1 [6B5..6C2)-> BB172 ( cond ) i bwd BB171 [0170] 1 1 [6C2..6D1)-> BB174 ( cond ) i bwd BB172 [0171] 3 1 [6D1..6DE) i bwd BB344 [0330] 1 1 [6D1..6D2)-> BB346 ( cond ) i bwd BB345 [0331] 1 1 [6D1..6D2)-> BB347 (always) i bwd BB346 [0332] 1 1 [6D1..6D2) i bwd BB347 [0333] 1 1 [???..???)-> BB191 (always) internal bwd BB173 [0172] 1 1 [6DE..6E4) i bwd bwd-target BB174 [0173] 4 1 [6E4..6F4)-> BB176 ( cond ) i bwd BB175 [0174] 1 1 [6F4..701)-> BB173 ( cond ) i bwd bwd-src BB176 [0175] 2 1 [701..707)-> BB178 ( cond ) i bwd BB177 [0176] 1 1 [707..70B) i bwd BB178 [0177] 2 1 [70B..710)-> BB180 ( cond ) i bwd BB179 [0178] 1 1 [710..71A)-> BB181 (always) i bwd BB180 [0179] 1 1 [71A..71B) i bwd BB181 [0180] 2 1 [71B..731)-> BB191 (always) i bwd BB182 [0181] 1 1 [731..744) i bwd BB350 [0336] 1 1 [731..732)-> BB352 ( cond ) i bwd BB351 [0337] 1 1 [731..732)-> BB353 (always) i bwd BB352 [0338] 1 1 [731..732) i bwd BB353 [0339] 1 1 [???..???)-> BB191 ( cond ) i internal bwd BB183 [0182] 1 1 [744..751)-> BB185 ( cond ) i bwd BB184 [0183] 1 1 [751..75E)-> BB187 ( cond ) i bwd BB185 [0184] 2 1 [75E..774) i bwd BB356 [0342] 1 1 [000..000)-> BB358 ( cond ) i internal bwd BB357 [0343] 1 1 [000..000)-> BB359 (always) i internal bwd BB358 [0344] 1 1 [000..000) i internal bwd BB359 [0345] 1 1 [???..???)-> BB187 (always) internal bwd BB186 [0185] 1 1 [774..788) i bwd bwd-target BB361 [0347] 1 1 [000..000)-> BB363 ( cond ) i internal bwd BB362 [0348] 1 1 [000..000)-> BB364 (always) i internal bwd BB363 [0349] 1 1 [000..000) i internal bwd BB364 [0350] 1 1 [???..???) internal bwd BB187 [0186] 3 1 [788..793)-> BB191 ( cond ) i bwd BB188 [0187] 1 1 [793..7A0)-> BB186 ( cond ) i bwd bwd-src BB189 [0188] 1 1 [7A0..7A2)-> BB191 (always) i bwd BB190 [0189] 6 1 [7A2..7AA) i bwd BB367 [0353] 1 1 [7A2..7A3)-> BB369 ( cond ) i bwd BB368 [0354] 1 1 [7A2..7A3)-> BB370 (always) i bwd BB369 [0355] 1 1 [7A2..7A3) i bwd BB370 [0356] 1 1 [???..???) internal bwd BB191 [0190] 21 1 [7AA..7B5)-> BB194 ( cond ) i bwd BB192 [0191] 1 1 [7B5..7C8)-> BB194 ( cond ) i bwd BB193 [0192] 1 1 [7C8..7D1)-> BB102 ( cond ) i bwd bwd-src BB194 [0193] 3 1 [7D1..7DD)-> BB199 ( cond ) i BB195 [0194] 1 1 [7DD..7E1)-> BB199 ( cond ) i BB196 [0195] 1 1 [7E1..7E9)-> BB199 ( cond ) i BB197 [0196] 1 1 [7E9..7F2)-> BB199 ( cond ) i BB198 [0197] 1 1 [7F2..7FF) i BB199 [0198] 5 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks [no changes] *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 1 [022..025)-> BB06 (always) i BB05 [0004] 1 1 [025..026) i BB06 [0005] 3 1 [026..02D) i BB07 [0006] 2 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 1 [0C1..0CA)-> BB31 ( cond ) i bwd BB16 [0015] 1 1 [0CA..0CF)-> BB48 (always) i bwd BB17 [0016] 1 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 1 [0E0..0E2) i bwd BB20 [0019] 2 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 1 [11E..121) i bwd BB29 [0028] 2 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 1 [12C..137)-> BB48 (always) i bwd BB31 [0030] 1 1 [137..142)-> BB48 (always) i bwd BB32 [0031] 3 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 1 [201..204) i bwd BB48 [0047] 27 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 1 [233..235) i bwd BB53 [0052] 2 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 1 [24A..24D) i bwd BB57 [0056] 3 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 1 [26E..26F) i bwd BB61 [0060] 2 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 1 [2A0..2A7) i BB66 [0065] 2 1 [2A7..2AE) i BB67 [0066] 3 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 1 [2B5..2B8) i BB70 [0069] 2 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 1 [2C0..2C3) i BB73 [0072] 2 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 1 [2DC..2E2) i BB78 [0077] 2 1 [2E2..2EE) i BB79 [0078] 2 1 [2EE..30D) i BB213 [0207] 1 1 [000..000)-> BB215 (always) i internal BB214 [0208] 1 1 [000..000) i internal BB215 [0209] 2 1 [000..000)-> BB216 (always) i internal BB216 [0211] 2 1 [000..000) i internal BB217 [0212] 1 1 [???..???)-> BB97 ( cond ) internal BB80 [0079] 1 1 [30D..31E)-> BB97 ( cond ) i idxlen BB81 [0080] 1 1 [31E..336)-> BB83 ( cond ) i idxlen BB82 [0081] 1 1 [336..33D) i idxlen BB83 [0082] 2 1 [33D..348)-> BB85 ( cond ) i BB84 [0083] 1 1 [348..34B)-> BB86 (always) i BB85 [0084] 1 1 [34B..34D) i BB86 [0085] 2 1 [34D..355)-> BB88 ( cond ) i BB87 [0086] 1 1 [355..359)-> BB89 (always) i BB88 [0087] 1 1 [359..35A) i BB89 [0088] 2 1 [35A..35E)-> BB96 (always) i BB90 [0089] 1 1 [35E..362)-> BB97 ( cond ) i bwd bwd-target BB91 [0090] 1 1 [362..373)-> BB93 ( cond ) i bwd BB92 [0091] 1 1 [373..39A) i bwd BB229 [0218] 1 1 [383..384)-> BB231 ( cond ) i bwd BB230 [0219] 1 1 [383..384)-> BB233 (always) i bwd BB231 [0220] 1 1 [383..384)-> BB232 (always) i bwd BB232 [0223] 3 1 [383..384) i idxlen bwd BB233 [0224] 1 1 [???..???) internal bwd BB235 [0226] 1 1 [000..000)-> BB237 ( cond ) i internal bwd BB236 [0227] 1 1 [000..000) i internal bwd BB240 [0231] 1 1 [000..000) i internal bwd BB241 [0232] 1 1 [000..000)-> BB243 (always) i internal bwd BB242 [0233] 1 1 [000..000) i internal bwd BB245 [0236] 1 1 [000..000)-> BB247 ( cond ) i internal bwd BB246 [0237] 1 1 [000..000)-> BB248 (always) i internal bwd BB247 [0238] 1 1 [000..000) i internal bwd BB248 [0239] 1 1 [???..???) internal bwd BB243 [0234] 1 1 [???..???)-> BB238 (always) internal bwd BB237 [0228] 1 1 [000..000) i internal bwd BB238 [0229] 1 1 [???..???) i internal bwd BB257 [0241] 1 1 [391..392)-> BB259 ( cond ) i bwd BB258 [0242] 1 1 [391..392)-> BB261 (always) i bwd BB259 [0243] 1 1 [391..392)-> BB260 (always) i bwd BB260 [0246] 3 1 [391..392) i idxlen bwd BB261 [0247] 1 1 [???..???) internal bwd BB93 [0092] 2 1 [39A..3AE)-> BB95 ( cond ) i bwd BB94 [0093] 1 1 [3AE..3BB) i idxlen bwd BB95 [0094] 2 1 [3BB..3C2) i bwd BB96 [0095] 2 1 [3C2..3C8)-> BB90 ( cond ) i bwd bwd-src BB97 [0096] 4 1 [3C8..3D0)-> BB101 ( cond ) i BB98 [0097] 1 1 [3D0..3D4)-> BB101 ( cond ) i BB99 [0098] 1 1 [3D4..3DC)-> BB101 ( cond ) i BB100 [0099] 1 1 [3DC..3E8) i BB264 [0250] 1 1 [3DC..3DD)-> BB266 ( cond ) i BB265 [0251] 1 1 [3DC..3DD)-> BB270 (always) i BB266 [0252] 1 1 [3DC..3DD)-> BB269 ( cond ) i idxlen BB267 [0253] 1 1 [3DC..3DD)-> BB269 ( cond ) i BB268 [0254] 1 1 [3DC..3DD)-> BB270 (always) i BB269 [0255] 2 1 [3DC..3DD) i BB270 [0256] 1 1 [???..???) internal BB101 [0100] 4 1 [3E8..401)-> BB191 (always) i BB102 [0101] 1 1 [401..406)-> BB117 ( cond ) i bwd bwd-target BB103 [0102] 1 1 [406..40C)-> BB116 ( cond ) i bwd BB104 [0103] 1 1 [40C..412)-> BB116 ( cond ) i bwd BB105 [0104] 1 1 [412..418)-> BB116 ( cond ) i bwd BB106 [0105] 1 1 [418..41A)-> BB117 (always) i bwd BB107 [0106] 1 1 [41A..420)-> BB109 ( cond ) i bwd bwd-target BB108 [0107] 1 1 [420..424)-> BB110 (always) i bwd BB109 [0108] 1 1 [424..42C) i bwd BB110 [0109] 2 1 [42C..435) i bwd BB273 [0259] 1 1 [000..000)-> BB275 ( cond ) i internal bwd BB274 [0260] 1 1 [000..000)-> BB276 (always) i internal bwd BB275 [0261] 1 1 [000..000) i internal bwd BB276 [0262] 1 1 [???..???)-> BB115 ( cond ) internal bwd BB111 [0110] 1 1 [435..43A)-> BB115 ( cond ) i bwd BB112 [0111] 1 1 [43A..43F)-> BB115 ( cond ) i bwd BB113 [0112] 1 1 [43F..44F)-> BB115 ( cond ) i bwd BB114 [0113] 1 1 [44F..461) i bwd BB279 [0265] 1 1 [44F..450)-> BB281 ( cond ) i bwd BB280 [0266] 1 1 [44F..450)-> BB285 (always) i bwd BB281 [0267] 1 1 [44F..450)-> BB284 ( cond ) i idxlen bwd BB282 [0268] 1 1 [44F..450)-> BB284 ( cond ) i bwd BB283 [0269] 1 1 [44F..450)-> BB285 (always) i bwd BB284 [0270] 2 1 [44F..450) i bwd BB285 [0271] 1 1 [???..???) internal bwd BB115 [0114] 5 1 [461..46D) i bwd BB116 [0115] 4 1 [46D..472)-> BB107 ( cond ) i bwd bwd-src BB117 [0116] 3 1 [472..478)-> BB122 ( cond ) i bwd BB118 [0117] 1 1 [478..49A)-> BB152,BB126,BB190,BB150,BB190,BB152,BB119[def] (switch) i bwd BB119 [0118] 1 1 [49A..4B8)-> BB191,BB190,BB144,BB190,BB126,BB120[def] (switch) i bwd BB120 [0119] 1 1 [4B8..4C1)-> BB161 ( cond ) i bwd BB121 [0120] 1 1 [4C1..4C6)-> BB190 (always) i bwd BB122 [0121] 1 1 [4C6..4CF)-> BB158 ( cond ) i bwd BB123 [0122] 1 1 [4CF..4D8)-> BB161 ( cond ) i bwd BB124 [0123] 1 1 [4D8..4E4)-> BB149 ( cond ) i bwd BB125 [0124] 1 1 [4E4..4E9)-> BB190 (always) i bwd BB126 [0125] 2 1 [4E9..4EE)-> BB131 ( cond ) i bwd BB127 [0126] 1 1 [4EE..4F9)-> BB129 ( cond ) i bwd BB128 [0127] 1 1 [4F9..4FC)-> BB130 (always) i bwd BB129 [0128] 1 1 [4FC..4FE) i bwd BB130 [0129] 2 1 [4FE..502)-> BB137 (always) i bwd BB131 [0130] 1 1 [502..507)-> BB135 ( cond ) i bwd BB132 [0131] 1 1 [507..50C)-> BB134 ( cond ) i bwd BB133 [0132] 1 1 [50C..50F)-> BB136 (always) i bwd BB134 [0133] 1 1 [50F..513)-> BB136 (always) i bwd BB135 [0134] 1 1 [513..51B) i bwd BB136 [0135] 3 1 [51B..51D) i bwd BB137 [0136] 2 1 [51D..521)-> BB143 ( cond ) i bwd BB138 [0137] 1 1 [521..52D) i bwd BB287 [0273] 1 1 [521..522)-> BB289 ( cond ) i bwd BB288 [0274] 1 1 [521..522)-> BB290 (always) i bwd BB289 [0275] 1 1 [521..522) i bwd BB290 [0276] 1 1 [???..???)-> BB143 ( cond ) internal bwd BB139 [0138] 1 1 [52D..532)-> BB143 ( cond ) i bwd BB140 [0139] 1 1 [532..537)-> BB143 ( cond ) i bwd BB141 [0140] 1 1 [537..547)-> BB143 ( cond ) i bwd BB142 [0141] 1 1 [547..559) i bwd BB293 [0279] 1 1 [547..548)-> BB295 ( cond ) i bwd BB294 [0280] 1 1 [547..548)-> BB299 (always) i bwd BB295 [0281] 1 1 [547..548)-> BB298 ( cond ) i idxlen bwd BB296 [0282] 1 1 [547..548)-> BB298 ( cond ) i bwd BB297 [0283] 1 1 [547..548)-> BB299 (always) i bwd BB298 [0284] 2 1 [547..548) i bwd BB299 [0285] 1 1 [???..???) internal bwd BB143 [0142] 6 1 [559..564)-> BB191 (always) i bwd BB144 [0143] 1 1 [564..571)-> BB191 ( cond ) i bwd BB145 [0144] 1 1 [571..575)-> BB148 ( cond ) i bwd BB146 [0145] 1 1 [575..57C)-> BB191 ( cond ) i bwd BB147 [0146] 1 1 [57C..584)-> BB191 ( cond ) i bwd BB148 [0147] 2 1 [584..598) i bwd BB302 [0288] 1 1 [584..585)-> BB304 ( cond ) i bwd BB303 [0289] 1 1 [584..585)-> BB308 (always) i bwd BB304 [0290] 1 1 [584..585)-> BB307 ( cond ) i idxlen bwd BB305 [0291] 1 1 [584..585)-> BB307 ( cond ) i bwd BB306 [0292] 1 1 [584..585)-> BB308 (always) i bwd BB307 [0293] 2 1 [584..585) i bwd BB308 [0294] 1 1 [???..???)-> BB191 (always) internal bwd BB149 [0148] 1 1 [598..5A9) i bwd BB311 [0297] 1 1 [598..599)-> BB313 ( cond ) i bwd BB312 [0298] 1 1 [598..599)-> BB317 (always) i bwd BB313 [0299] 1 1 [598..599)-> BB316 ( cond ) i idxlen bwd BB314 [0300] 1 1 [598..599)-> BB316 ( cond ) i bwd BB315 [0301] 1 1 [598..599)-> BB317 (always) i bwd BB316 [0302] 2 1 [598..599) i bwd BB317 [0303] 1 1 [???..???)-> BB191 (always) internal bwd BB150 [0149] 1 1 [5A9..5BA) i bwd BB320 [0306] 1 1 [5A9..5AA)-> BB322 ( cond ) i bwd BB321 [0307] 1 1 [5A9..5AA)-> BB326 (always) i bwd BB322 [0308] 1 1 [5A9..5AA)-> BB325 ( cond ) i idxlen bwd BB323 [0309] 1 1 [5A9..5AA)-> BB325 ( cond ) i bwd BB324 [0310] 1 1 [5A9..5AA)-> BB326 (always) i bwd BB325 [0311] 2 1 [5A9..5AA) i bwd BB326 [0312] 1 1 [???..???)-> BB191 (always) internal bwd BB151 [0150] 1 1 [5BA..5CE) i bwd bwd-target BB328 [0314] 1 1 [000..000)-> BB330 ( cond ) i internal bwd BB329 [0315] 1 1 [000..000)-> BB331 (always) i internal bwd BB330 [0316] 1 1 [000..000) i internal bwd BB331 [0317] 1 1 [???..???) internal bwd BB152 [0151] 3 1 [5CE..5D9)-> BB155 ( cond ) i bwd BB153 [0152] 1 1 [5D9..5E4)-> BB155 ( cond ) i bwd BB154 [0153] 1 1 [5E4..5F1)-> BB151 ( cond ) i bwd bwd-src BB155 [0154] 3 1 [5F1..5FF)-> BB191 ( cond ) i bwd BB156 [0155] 1 1 [5FF..60D)-> BB191 ( cond ) i bwd BB157 [0156] 1 1 [60D..618)-> BB191 (always) i bwd BB158 [0157] 1 1 [618..626)-> BB191 ( cond ) i bwd BB159 [0158] 1 1 [626..634)-> BB191 ( cond ) i bwd BB160 [0159] 1 1 [634..64D) i bwd BB336 [0322] 1 1 [000..000)-> BB338 ( cond ) i internal bwd BB337 [0323] 1 1 [000..000)-> BB339 (always) i internal bwd BB338 [0324] 1 1 [000..000) i internal bwd BB339 [0325] 1 1 [???..???)-> BB191 (always) internal bwd BB161 [0160] 2 1 [64D..65A)-> BB182 ( cond ) i bwd BB162 [0161] 1 1 [65A..665)-> BB165 ( cond ) i bwd BB163 [0162] 1 1 [665..672)-> BB165 ( cond ) i bwd BB164 [0163] 1 1 [672..67A)-> BB174 (always) i bwd BB165 [0164] 2 1 [67A..687)-> BB169 ( cond ) i bwd BB166 [0165] 1 1 [687..694)-> BB169 ( cond ) i bwd BB167 [0166] 1 1 [694..6A3)-> BB169 ( cond ) i bwd BB168 [0167] 1 1 [6A3..6A8)-> BB174 (always) i bwd BB169 [0168] 3 1 [6A8..6B5)-> BB172 ( cond ) i bwd BB170 [0169] 1 1 [6B5..6C2)-> BB172 ( cond ) i bwd BB171 [0170] 1 1 [6C2..6D1)-> BB174 ( cond ) i bwd BB172 [0171] 3 1 [6D1..6DE) i bwd BB344 [0330] 1 1 [6D1..6D2)-> BB346 ( cond ) i bwd BB345 [0331] 1 1 [6D1..6D2)-> BB347 (always) i bwd BB346 [0332] 1 1 [6D1..6D2) i bwd BB347 [0333] 1 1 [???..???)-> BB191 (always) internal bwd BB173 [0172] 1 1 [6DE..6E4) i bwd bwd-target BB174 [0173] 4 1 [6E4..6F4)-> BB176 ( cond ) i bwd BB175 [0174] 1 1 [6F4..701)-> BB173 ( cond ) i bwd bwd-src BB176 [0175] 2 1 [701..707)-> BB178 ( cond ) i bwd BB177 [0176] 1 1 [707..70B) i bwd BB178 [0177] 2 1 [70B..710)-> BB180 ( cond ) i bwd BB179 [0178] 1 1 [710..71A)-> BB181 (always) i bwd BB180 [0179] 1 1 [71A..71B) i bwd BB181 [0180] 2 1 [71B..731)-> BB191 (always) i bwd BB182 [0181] 1 1 [731..744) i bwd BB350 [0336] 1 1 [731..732)-> BB352 ( cond ) i bwd BB351 [0337] 1 1 [731..732)-> BB353 (always) i bwd BB352 [0338] 1 1 [731..732) i bwd BB353 [0339] 1 1 [???..???)-> BB191 ( cond ) i internal bwd BB183 [0182] 1 1 [744..751)-> BB185 ( cond ) i bwd BB184 [0183] 1 1 [751..75E)-> BB187 ( cond ) i bwd BB185 [0184] 2 1 [75E..774) i bwd BB356 [0342] 1 1 [000..000)-> BB358 ( cond ) i internal bwd BB357 [0343] 1 1 [000..000)-> BB359 (always) i internal bwd BB358 [0344] 1 1 [000..000) i internal bwd BB359 [0345] 1 1 [???..???)-> BB187 (always) internal bwd BB186 [0185] 1 1 [774..788) i bwd bwd-target BB361 [0347] 1 1 [000..000)-> BB363 ( cond ) i internal bwd BB362 [0348] 1 1 [000..000)-> BB364 (always) i internal bwd BB363 [0349] 1 1 [000..000) i internal bwd BB364 [0350] 1 1 [???..???) internal bwd BB187 [0186] 3 1 [788..793)-> BB191 ( cond ) i bwd BB188 [0187] 1 1 [793..7A0)-> BB186 ( cond ) i bwd bwd-src BB189 [0188] 1 1 [7A0..7A2)-> BB191 (always) i bwd BB190 [0189] 6 1 [7A2..7AA) i bwd BB367 [0353] 1 1 [7A2..7A3)-> BB369 ( cond ) i bwd BB368 [0354] 1 1 [7A2..7A3)-> BB370 (always) i bwd BB369 [0355] 1 1 [7A2..7A3) i bwd BB370 [0356] 1 1 [???..???) internal bwd BB191 [0190] 21 1 [7AA..7B5)-> BB194 ( cond ) i bwd BB192 [0191] 1 1 [7B5..7C8)-> BB194 ( cond ) i bwd BB193 [0192] 1 1 [7C8..7D1)-> BB102 ( cond ) i bwd bwd-src BB194 [0193] 3 1 [7D1..7DD)-> BB199 ( cond ) i BB195 [0194] 1 1 [7DD..7E1)-> BB199 ( cond ) i BB196 [0195] 1 1 [7E1..7E9)-> BB199 ( cond ) i BB197 [0196] 1 1 [7E9..7F2)-> BB199 ( cond ) i BB198 [0197] 1 1 [7F2..7FF) i BB199 [0198] 5 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB213 to BB80 Renumber BB214 to BB81 Renumber BB215 to BB82 Renumber BB216 to BB83 Renumber BB217 to BB84 Renumber BB80 to BB85 Renumber BB81 to BB86 Renumber BB82 to BB87 Renumber BB83 to BB88 Renumber BB84 to BB89 Renumber BB85 to BB90 Renumber BB86 to BB91 Renumber BB87 to BB92 Renumber BB88 to BB93 Renumber BB89 to BB94 Renumber BB90 to BB95 Renumber BB91 to BB96 Renumber BB92 to BB97 Renumber BB229 to BB98 Renumber BB230 to BB99 Renumber BB231 to BB100 Renumber BB232 to BB101 Renumber BB233 to BB102 Renumber BB235 to BB103 Renumber BB236 to BB104 Renumber BB240 to BB105 Renumber BB241 to BB106 Renumber BB242 to BB107 Renumber BB245 to BB108 Renumber BB246 to BB109 Renumber BB247 to BB110 Renumber BB248 to BB111 Renumber BB243 to BB112 Renumber BB237 to BB113 Renumber BB238 to BB114 Renumber BB257 to BB115 Renumber BB258 to BB116 Renumber BB259 to BB117 Renumber BB260 to BB118 Renumber BB261 to BB119 Renumber BB93 to BB120 Renumber BB94 to BB121 Renumber BB95 to BB122 Renumber BB96 to BB123 Renumber BB97 to BB124 Renumber BB98 to BB125 Renumber BB99 to BB126 Renumber BB100 to BB127 Renumber BB264 to BB128 Renumber BB265 to BB129 Renumber BB266 to BB130 Renumber BB267 to BB131 Renumber BB268 to BB132 Renumber BB269 to BB133 Renumber BB270 to BB134 Renumber BB101 to BB135 Renumber BB102 to BB136 Renumber BB103 to BB137 Renumber BB104 to BB138 Renumber BB105 to BB139 Renumber BB106 to BB140 Renumber BB107 to BB141 Renumber BB108 to BB142 Renumber BB109 to BB143 Renumber BB110 to BB144 Renumber BB273 to BB145 Renumber BB274 to BB146 Renumber BB275 to BB147 Renumber BB276 to BB148 Renumber BB111 to BB149 Renumber BB112 to BB150 Renumber BB113 to BB151 Renumber BB114 to BB152 Renumber BB279 to BB153 Renumber BB280 to BB154 Renumber BB281 to BB155 Renumber BB282 to BB156 Renumber BB283 to BB157 Renumber BB284 to BB158 Renumber BB285 to BB159 Renumber BB115 to BB160 Renumber BB116 to BB161 Renumber BB117 to BB162 Renumber BB118 to BB163 Renumber BB119 to BB164 Renumber BB120 to BB165 Renumber BB121 to BB166 Renumber BB122 to BB167 Renumber BB123 to BB168 Renumber BB124 to BB169 Renumber BB125 to BB170 Renumber BB126 to BB171 Renumber BB127 to BB172 Renumber BB128 to BB173 Renumber BB129 to BB174 Renumber BB130 to BB175 Renumber BB131 to BB176 Renumber BB132 to BB177 Renumber BB133 to BB178 Renumber BB134 to BB179 Renumber BB135 to BB180 Renumber BB136 to BB181 Renumber BB137 to BB182 Renumber BB138 to BB183 Renumber BB287 to BB184 Renumber BB288 to BB185 Renumber BB289 to BB186 Renumber BB290 to BB187 Renumber BB139 to BB188 Renumber BB140 to BB189 Renumber BB141 to BB190 Renumber BB142 to BB191 Renumber BB293 to BB192 Renumber BB294 to BB193 Renumber BB295 to BB194 Renumber BB296 to BB195 Renumber BB297 to BB196 Renumber BB298 to BB197 Renumber BB299 to BB198 Renumber BB143 to BB199 Renumber BB144 to BB200 Renumber BB145 to BB201 Renumber BB146 to BB202 Renumber BB147 to BB203 Renumber BB148 to BB204 Renumber BB302 to BB205 Renumber BB303 to BB206 Renumber BB304 to BB207 Renumber BB305 to BB208 Renumber BB306 to BB209 Renumber BB307 to BB210 Renumber BB308 to BB211 Renumber BB149 to BB212 Renumber BB311 to BB213 Renumber BB312 to BB214 Renumber BB313 to BB215 Renumber BB314 to BB216 Renumber BB315 to BB217 Renumber BB316 to BB218 Renumber BB317 to BB219 Renumber BB150 to BB220 Renumber BB320 to BB221 Renumber BB321 to BB222 Renumber BB322 to BB223 Renumber BB323 to BB224 Renumber BB324 to BB225 Renumber BB325 to BB226 Renumber BB326 to BB227 Renumber BB151 to BB228 Renumber BB328 to BB229 Renumber BB329 to BB230 Renumber BB330 to BB231 Renumber BB331 to BB232 Renumber BB152 to BB233 Renumber BB153 to BB234 Renumber BB154 to BB235 Renumber BB155 to BB236 Renumber BB156 to BB237 Renumber BB157 to BB238 Renumber BB158 to BB239 Renumber BB159 to BB240 Renumber BB160 to BB241 Renumber BB336 to BB242 Renumber BB337 to BB243 Renumber BB338 to BB244 Renumber BB339 to BB245 Renumber BB161 to BB246 Renumber BB162 to BB247 Renumber BB163 to BB248 Renumber BB164 to BB249 Renumber BB165 to BB250 Renumber BB166 to BB251 Renumber BB167 to BB252 Renumber BB168 to BB253 Renumber BB169 to BB254 Renumber BB170 to BB255 Renumber BB171 to BB256 Renumber BB172 to BB257 Renumber BB344 to BB258 Renumber BB345 to BB259 Renumber BB346 to BB260 Renumber BB347 to BB261 Renumber BB173 to BB262 Renumber BB174 to BB263 Renumber BB175 to BB264 Renumber BB176 to BB265 Renumber BB177 to BB266 Renumber BB178 to BB267 Renumber BB179 to BB268 Renumber BB180 to BB269 Renumber BB181 to BB270 Renumber BB182 to BB271 Renumber BB350 to BB272 Renumber BB351 to BB273 Renumber BB352 to BB274 Renumber BB353 to BB275 Renumber BB183 to BB276 Renumber BB184 to BB277 Renumber BB185 to BB278 Renumber BB356 to BB279 Renumber BB357 to BB280 Renumber BB358 to BB281 Renumber BB359 to BB282 Renumber BB186 to BB283 Renumber BB361 to BB284 Renumber BB362 to BB285 Renumber BB363 to BB286 Renumber BB364 to BB287 Renumber BB187 to BB288 Renumber BB188 to BB289 Renumber BB189 to BB290 Renumber BB190 to BB291 Renumber BB367 to BB292 Renumber BB368 to BB293 Renumber BB369 to BB294 Renumber BB370 to BB295 Renumber BB191 to BB296 Renumber BB192 to BB297 Renumber BB193 to BB298 Renumber BB194 to BB299 Renumber BB195 to BB300 Renumber BB196 to BB301 Renumber BB197 to BB302 Renumber BB198 to BB303 Renumber BB199 to BB304 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 1 [022..025)-> BB06 (always) i BB05 [0004] 1 1 [025..026) i BB06 [0005] 3 1 [026..02D) i BB07 [0006] 2 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 1 [0C1..0CA)-> BB31 ( cond ) i bwd BB16 [0015] 1 1 [0CA..0CF)-> BB48 (always) i bwd BB17 [0016] 1 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 1 [0E0..0E2) i bwd BB20 [0019] 2 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 1 [11E..121) i bwd BB29 [0028] 2 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 1 [12C..137)-> BB48 (always) i bwd BB31 [0030] 1 1 [137..142)-> BB48 (always) i bwd BB32 [0031] 3 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 1 [201..204) i bwd BB48 [0047] 27 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 1 [233..235) i bwd BB53 [0052] 2 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 1 [24A..24D) i bwd BB57 [0056] 3 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 1 [26E..26F) i bwd BB61 [0060] 2 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 1 [2A0..2A7) i BB66 [0065] 2 1 [2A7..2AE) i BB67 [0066] 3 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 1 [2B5..2B8) i BB70 [0069] 2 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 1 [2C0..2C3) i BB73 [0072] 2 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 1 [2DC..2E2) i BB78 [0077] 2 1 [2E2..2EE) i BB79 [0078] 2 1 [2EE..30D) i BB80 [0207] 1 1 [000..000)-> BB82 (always) i internal BB81 [0208] 1 1 [000..000) i internal BB82 [0209] 2 1 [000..000)-> BB83 (always) i internal BB83 [0211] 2 1 [000..000) i internal BB84 [0212] 1 1 [???..???)-> BB124 ( cond ) internal BB85 [0079] 1 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 1 [336..33D) i idxlen BB88 [0082] 2 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 1 [34B..34D) i BB91 [0085] 2 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 1 [355..359)-> BB94 (always) i BB93 [0087] 1 1 [359..35A) i BB94 [0088] 2 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 1 [373..39A) i bwd BB98 [0218] 1 1 [383..384)-> BB100 ( cond ) i bwd BB99 [0219] 1 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 1 [383..384)-> BB101 (always) i bwd BB101 [0223] 3 1 [383..384) i idxlen bwd BB102 [0224] 1 1 [???..???) internal bwd BB103 [0226] 1 1 [000..000)-> BB113 ( cond ) i internal bwd BB104 [0227] 1 1 [000..000) i internal bwd BB105 [0231] 1 1 [000..000) i internal bwd BB106 [0232] 1 1 [000..000)-> BB112 (always) i internal bwd BB107 [0233] 1 1 [000..000) i internal bwd BB108 [0236] 1 1 [000..000)-> BB110 ( cond ) i internal bwd BB109 [0237] 1 1 [000..000)-> BB111 (always) i internal bwd BB110 [0238] 1 1 [000..000) i internal bwd BB111 [0239] 1 1 [???..???) internal bwd BB112 [0234] 1 1 [???..???)-> BB114 (always) internal bwd BB113 [0228] 1 1 [000..000) i internal bwd BB114 [0229] 1 1 [???..???) i internal bwd BB115 [0241] 1 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 1 [391..392)-> BB118 (always) i bwd BB118 [0246] 3 1 [391..392) i idxlen bwd BB119 [0247] 1 1 [???..???) internal bwd BB120 [0092] 2 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 1 [3BB..3C2) i bwd BB123 [0095] 2 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 1 [3C8..3D0)-> BB135 ( cond ) i BB125 [0097] 1 1 [3D0..3D4)-> BB135 ( cond ) i BB126 [0098] 1 1 [3D4..3DC)-> BB135 ( cond ) i BB127 [0099] 1 1 [3DC..3E8) i BB128 [0250] 1 1 [3DC..3DD)-> BB130 ( cond ) i BB129 [0251] 1 1 [3DC..3DD)-> BB134 (always) i BB130 [0252] 1 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 1 [3DC..3DD) i BB134 [0256] 1 1 [???..???) internal BB135 [0100] 4 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 1 [424..42C) i bwd BB144 [0109] 2 1 [42C..435) i bwd BB145 [0259] 1 1 [000..000)-> BB147 ( cond ) i internal bwd BB146 [0260] 1 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 1 [000..000) i internal bwd BB148 [0262] 1 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 1 [44F..461) i bwd BB153 [0265] 1 1 [44F..450)-> BB155 ( cond ) i bwd BB154 [0266] 1 1 [44F..450)-> BB159 (always) i bwd BB155 [0267] 1 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 1 [44F..450) i bwd BB159 [0271] 1 1 [???..???) internal bwd BB160 [0114] 5 1 [461..46D) i bwd BB161 [0115] 4 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 1 [4D8..4E4)-> BB212 ( cond ) i bwd BB170 [0124] 1 1 [4E4..4E9)-> BB291 (always) i bwd BB171 [0125] 2 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 1 [4FC..4FE) i bwd BB175 [0129] 2 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 1 [513..51B) i bwd BB181 [0135] 3 1 [51B..51D) i bwd BB182 [0136] 2 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 1 [521..52D) i bwd BB184 [0273] 1 1 [521..522)-> BB186 ( cond ) i bwd BB185 [0274] 1 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 1 [521..522) i bwd BB187 [0276] 1 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 1 [547..559) i bwd BB192 [0279] 1 1 [547..548)-> BB194 ( cond ) i bwd BB193 [0280] 1 1 [547..548)-> BB198 (always) i bwd BB194 [0281] 1 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 1 [547..548) i bwd BB198 [0285] 1 1 [???..???) internal bwd BB199 [0142] 6 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 1 [584..598) i bwd BB205 [0288] 1 1 [584..585)-> BB207 ( cond ) i bwd BB206 [0289] 1 1 [584..585)-> BB211 (always) i bwd BB207 [0290] 1 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 1 [584..585) i bwd BB211 [0294] 1 1 [???..???)-> BB296 (always) internal bwd BB212 [0148] 1 1 [598..5A9) i bwd BB213 [0297] 1 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 1 [598..599) i bwd BB219 [0303] 1 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 1 [5A9..5BA) i bwd BB221 [0306] 1 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 1 [5A9..5AA) i bwd BB227 [0312] 1 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 1 [000..000) i internal bwd BB232 [0317] 1 1 [???..???) internal bwd BB233 [0151] 3 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 1 [634..64D) i bwd BB242 [0322] 1 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 1 [000..000) i internal bwd BB245 [0325] 1 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 1 [672..67A)-> BB263 (always) i bwd BB250 [0164] 2 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 1 [6D1..6DE) i bwd BB258 [0330] 1 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 1 [6D1..6D2) i bwd BB261 [0333] 1 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 1 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 4 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 1 [707..70B) i bwd BB267 [0177] 2 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 1 [71A..71B) i bwd BB270 [0180] 2 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 1 [731..744) i bwd BB272 [0336] 1 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 1 [731..732) i bwd BB275 [0339] 1 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 1 [75E..774) i bwd BB279 [0342] 1 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 1 [000..000) i internal bwd BB282 [0345] 1 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 1 [774..788) i bwd bwd-target BB284 [0347] 1 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 1 [000..000) i internal bwd BB287 [0350] 1 1 [???..???) internal bwd BB288 [0186] 3 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 1 [7A2..7AA) i bwd BB292 [0353] 1 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 1 [7A2..7A3) i bwd BB295 [0356] 1 1 [???..???) internal bwd BB296 [0190] 21 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 1 [7F2..7FF) i BB304 [0198] 5 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 305, bitset array size: 5 (long) Setting edge weights for BB01 -> BB05 to [0 .. 3.402823e+38] Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38] Setting edge weights for BB02 -> BB04 to [0 .. 3.402823e+38] Setting edge weights for BB02 -> BB03 to [0 .. 3.402823e+38] Setting edge weights for BB03 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB04 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB05 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB06 -> BB07 to [0 .. 3.402823e+38] Setting edge weights for BB07 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB08 -> BB13 to [0 .. 3.402823e+38] Setting edge weights for BB08 -> BB09 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB32 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB17 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB30 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB10 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB23 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB21 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB18 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB11 to [0 .. 3.402823e+38] Setting edge weights for BB11 -> BB39 to [0 .. 3.402823e+38] Setting edge weights for BB11 -> BB12 to [0 .. 3.402823e+38] Setting edge weights for BB12 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB13 -> BB36 to [0 .. 3.402823e+38] Setting edge weights for BB13 -> BB14 to [0 .. 3.402823e+38] Setting edge weights for BB14 -> BB39 to [0 .. 3.402823e+38] Setting edge weights for BB14 -> BB15 to [0 .. 3.402823e+38] Setting edge weights for BB15 -> BB31 to [0 .. 3.402823e+38] Setting edge weights for BB15 -> BB16 to [0 .. 3.402823e+38] Setting edge weights for BB16 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB17 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB18 -> BB20 to [0 .. 3.402823e+38] Setting edge weights for BB18 -> BB19 to [0 .. 3.402823e+38] Setting edge weights for BB19 -> BB20 to [0 .. 3.402823e+38] Setting edge weights for BB20 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB21 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB21 -> BB22 to [0 .. 3.402823e+38] Setting edge weights for BB22 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB23 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB23 -> BB24 to [0 .. 3.402823e+38] Setting edge weights for BB24 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB24 -> BB25 to [0 .. 3.402823e+38] Setting edge weights for BB25 -> BB29 to [0 .. 3.402823e+38] Setting edge weights for BB25 -> BB26 to [0 .. 3.402823e+38] Setting edge weights for BB26 -> BB28 to [0 .. 3.402823e+38] Setting edge weights for BB26 -> BB27 to [0 .. 3.402823e+38] Setting edge weights for BB27 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB28 -> BB29 to [0 .. 3.402823e+38] Setting edge weights for BB29 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB30 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB31 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB32 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB32 -> BB33 to [0 .. 3.402823e+38] Setting edge weights for BB33 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB33 -> BB34 to [0 .. 3.402823e+38] Setting edge weights for BB34 -> BB32 to [0 .. 3.402823e+38] Setting edge weights for BB34 -> BB35 to [0 .. 3.402823e+38] Setting edge weights for BB35 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB36 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB36 -> BB37 to [0 .. 3.402823e+38] Setting edge weights for BB37 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB37 -> BB38 to [0 .. 3.402823e+38] Setting edge weights for BB38 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB39 -> BB41 to [0 .. 3.402823e+38] Setting edge weights for BB39 -> BB40 to [0 .. 3.402823e+38] Setting edge weights for BB40 -> BB45 to [0 .. 3.402823e+38] Setting edge weights for BB40 -> BB41 to [0 .. 3.402823e+38] Setting edge weights for BB41 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB41 -> BB42 to [0 .. 3.402823e+38] Setting edge weights for BB42 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB42 -> BB43 to [0 .. 3.402823e+38] Setting edge weights for BB43 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB43 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB44 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB44 -> BB45 to [0 .. 3.402823e+38] Setting edge weights for BB45 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB45 -> BB46 to [0 .. 3.402823e+38] Setting edge weights for BB46 -> BB45 to [0 .. 3.402823e+38] Setting edge weights for BB46 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB47 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB48 -> BB51 to [0 .. 3.402823e+38] Setting edge weights for BB48 -> BB49 to [0 .. 3.402823e+38] Setting edge weights for BB49 -> BB51 to [0 .. 3.402823e+38] Setting edge weights for BB49 -> BB50 to [0 .. 3.402823e+38] Setting edge weights for BB50 -> BB08 to [0 .. 3.402823e+38] Setting edge weights for BB50 -> BB51 to [0 .. 3.402823e+38] Setting edge weights for BB51 -> BB53 to [0 .. 3.402823e+38] Setting edge weights for BB51 -> BB52 to [0 .. 3.402823e+38] Setting edge weights for BB52 -> BB53 to [0 .. 3.402823e+38] Setting edge weights for BB53 -> BB57 to [0 .. 3.402823e+38] Setting edge weights for BB53 -> BB54 to [0 .. 3.402823e+38] Setting edge weights for BB54 -> BB56 to [0 .. 3.402823e+38] Setting edge weights for BB54 -> BB55 to [0 .. 3.402823e+38] Setting edge weights for BB55 -> BB57 to [0 .. 3.402823e+38] Setting edge weights for BB56 -> BB57 to [0 .. 3.402823e+38] Setting edge weights for BB57 -> BB64 to [0 .. 3.402823e+38] Setting edge weights for BB57 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB58 -> BB60 to [0 .. 3.402823e+38] Setting edge weights for BB58 -> BB59 to [0 .. 3.402823e+38] Setting edge weights for BB59 -> BB61 to [0 .. 3.402823e+38] Setting edge weights for BB60 -> BB61 to [0 .. 3.402823e+38] Setting edge weights for BB61 -> BB67 to [0 .. 3.402823e+38] Setting edge weights for BB61 -> BB62 to [0 .. 3.402823e+38] Setting edge weights for BB62 -> BB67 to [0 .. 3.402823e+38] Setting edge weights for BB62 -> BB63 to [0 .. 3.402823e+38] Setting edge weights for BB63 -> BB07 to [0 .. 3.402823e+38] Setting edge weights for BB64 -> BB66 to [0 .. 3.402823e+38] Setting edge weights for BB64 -> BB65 to [0 .. 3.402823e+38] Setting edge weights for BB65 -> BB66 to [0 .. 3.402823e+38] Setting edge weights for BB66 -> BB67 to [0 .. 3.402823e+38] Setting edge weights for BB67 -> BB69 to [0 .. 3.402823e+38] Setting edge weights for BB67 -> BB68 to [0 .. 3.402823e+38] Setting edge weights for BB68 -> BB70 to [0 .. 3.402823e+38] Setting edge weights for BB69 -> BB70 to [0 .. 3.402823e+38] Setting edge weights for BB70 -> BB72 to [0 .. 3.402823e+38] Setting edge weights for BB70 -> BB71 to [0 .. 3.402823e+38] Setting edge weights for BB71 -> BB73 to [0 .. 3.402823e+38] Setting edge weights for BB72 -> BB73 to [0 .. 3.402823e+38] Setting edge weights for BB73 -> BB75 to [0 .. 3.402823e+38] Setting edge weights for BB73 -> BB74 to [0 .. 3.402823e+38] Setting edge weights for BB74 -> BB79 to [0 .. 3.402823e+38] Setting edge weights for BB75 -> BB77 to [0 .. 3.402823e+38] Setting edge weights for BB75 -> BB76 to [0 .. 3.402823e+38] Setting edge weights for BB76 -> BB78 to [0 .. 3.402823e+38] Setting edge weights for BB77 -> BB78 to [0 .. 3.402823e+38] Setting edge weights for BB78 -> BB79 to [0 .. 3.402823e+38] Setting edge weights for BB79 -> BB80 to [0 .. 3.402823e+38] Setting edge weights for BB80 -> BB82 to [0 .. 3.402823e+38] Setting edge weights for BB81 -> BB82 to [0 .. 3.402823e+38] Setting edge weights for BB82 -> BB83 to [0 .. 3.402823e+38] Setting edge weights for BB83 -> BB84 to [0 .. 3.402823e+38] Setting edge weights for BB84 -> BB124 to [0 .. 3.402823e+38] Setting edge weights for BB84 -> BB85 to [0 .. 3.402823e+38] Setting edge weights for BB85 -> BB124 to [0 .. 3.402823e+38] Setting edge weights for BB85 -> BB86 to [0 .. 3.402823e+38] Setting edge weights for BB86 -> BB88 to [0 .. 3.402823e+38] Setting edge weights for BB86 -> BB87 to [0 .. 3.402823e+38] Setting edge weights for BB87 -> BB88 to [0 .. 3.402823e+38] Setting edge weights for BB88 -> BB90 to [0 .. 3.402823e+38] Setting edge weights for BB88 -> BB89 to [0 .. 3.402823e+38] Setting edge weights for BB89 -> BB91 to [0 .. 3.402823e+38] Setting edge weights for BB90 -> BB91 to [0 .. 3.402823e+38] Setting edge weights for BB91 -> BB93 to [0 .. 3.402823e+38] Setting edge weights for BB91 -> BB92 to [0 .. 3.402823e+38] Setting edge weights for BB92 -> BB94 to [0 .. 3.402823e+38] Setting edge weights for BB93 -> BB94 to [0 .. 3.402823e+38] Setting edge weights for BB94 -> BB123 to [0 .. 3.402823e+38] Setting edge weights for BB95 -> BB124 to [0 .. 3.402823e+38] Setting edge weights for BB95 -> BB96 to [0 .. 3.402823e+38] Setting edge weights for BB96 -> BB120 to [0 .. 3.402823e+38] Setting edge weights for BB96 -> BB97 to [0 .. 3.402823e+38] Setting edge weights for BB97 -> BB98 to [0 .. 3.402823e+38] Setting edge weights for BB98 -> BB100 to [0 .. 3.402823e+38] Setting edge weights for BB98 -> BB99 to [0 .. 3.402823e+38] Setting edge weights for BB99 -> BB102 to [0 .. 3.402823e+38] Setting edge weights for BB100 -> BB101 to [0 .. 3.402823e+38] Setting edge weights for BB101 -> BB102 to [0 .. 3.402823e+38] Setting edge weights for BB102 -> BB103 to [0 .. 3.402823e+38] Setting edge weights for BB103 -> BB113 to [0 .. 3.402823e+38] Setting edge weights for BB103 -> BB104 to [0 .. 3.402823e+38] Setting edge weights for BB104 -> BB105 to [0 .. 3.402823e+38] Setting edge weights for BB105 -> BB106 to [0 .. 3.402823e+38] Setting edge weights for BB106 -> BB112 to [0 .. 3.402823e+38] Setting edge weights for BB107 -> BB108 to [0 .. 3.402823e+38] Setting edge weights for BB108 -> BB110 to [0 .. 3.402823e+38] Setting edge weights for BB108 -> BB109 to [0 .. 3.402823e+38] Setting edge weights for BB109 -> BB111 to [0 .. 3.402823e+38] Setting edge weights for BB110 -> BB111 to [0 .. 3.402823e+38] Setting edge weights for BB111 -> BB112 to [0 .. 3.402823e+38] Setting edge weights for BB112 -> BB114 to [0 .. 3.402823e+38] Setting edge weights for BB113 -> BB114 to [0 .. 3.402823e+38] Setting edge weights for BB114 -> BB115 to [0 .. 3.402823e+38] Setting edge weights for BB115 -> BB117 to [0 .. 3.402823e+38] Setting edge weights for BB115 -> BB116 to [0 .. 3.402823e+38] Setting edge weights for BB116 -> BB119 to [0 .. 3.402823e+38] Setting edge weights for BB117 -> BB118 to [0 .. 3.402823e+38] Setting edge weights for BB118 -> BB119 to [0 .. 3.402823e+38] Setting edge weights for BB119 -> BB120 to [0 .. 3.402823e+38] Setting edge weights for BB120 -> BB122 to [0 .. 3.402823e+38] Setting edge weights for BB120 -> BB121 to [0 .. 3.402823e+38] Setting edge weights for BB121 -> BB122 to [0 .. 3.402823e+38] Setting edge weights for BB122 -> BB123 to [0 .. 3.402823e+38] Setting edge weights for BB123 -> BB95 to [0 .. 3.402823e+38] Setting edge weights for BB123 -> BB124 to [0 .. 3.402823e+38] Setting edge weights for BB124 -> BB135 to [0 .. 3.402823e+38] Setting edge weights for BB124 -> BB125 to [0 .. 3.402823e+38] Setting edge weights for BB125 -> BB135 to [0 .. 3.402823e+38] Setting edge weights for BB125 -> BB126 to [0 .. 3.402823e+38] Setting edge weights for BB126 -> BB135 to [0 .. 3.402823e+38] Setting edge weights for BB126 -> BB127 to [0 .. 3.402823e+38] Setting edge weights for BB127 -> BB128 to [0 .. 3.402823e+38] Setting edge weights for BB128 -> BB130 to [0 .. 3.402823e+38] Setting edge weights for BB128 -> BB129 to [0 .. 3.402823e+38] Setting edge weights for BB129 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB130 -> BB133 to [0 .. 3.402823e+38] Setting edge weights for BB130 -> BB131 to [0 .. 3.402823e+38] Setting edge weights for BB131 -> BB133 to [0 .. 3.402823e+38] Setting edge weights for BB131 -> BB132 to [0 .. 3.402823e+38] Setting edge weights for BB132 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB133 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB134 -> BB135 to [0 .. 3.402823e+38] Setting edge weights for BB135 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB136 -> BB162 to [0 .. 3.402823e+38] Setting edge weights for BB136 -> BB137 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB161 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB138 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB161 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB139 to [0 .. 3.402823e+38] Setting edge weights for BB139 -> BB161 to [0 .. 3.402823e+38] Setting edge weights for BB139 -> BB140 to [0 .. 3.402823e+38] Setting edge weights for BB140 -> BB162 to [0 .. 3.402823e+38] Setting edge weights for BB141 -> BB143 to [0 .. 3.402823e+38] Setting edge weights for BB141 -> BB142 to [0 .. 3.402823e+38] Setting edge weights for BB142 -> BB144 to [0 .. 3.402823e+38] Setting edge weights for BB143 -> BB144 to [0 .. 3.402823e+38] Setting edge weights for BB144 -> BB145 to [0 .. 3.402823e+38] Setting edge weights for BB145 -> BB147 to [0 .. 3.402823e+38] Setting edge weights for BB145 -> BB146 to [0 .. 3.402823e+38] Setting edge weights for BB146 -> BB148 to [0 .. 3.402823e+38] Setting edge weights for BB147 -> BB148 to [0 .. 3.402823e+38] Setting edge weights for BB148 -> BB160 to [0 .. 3.402823e+38] Setting edge weights for BB148 -> BB149 to [0 .. 3.402823e+38] Setting edge weights for BB149 -> BB160 to [0 .. 3.402823e+38] Setting edge weights for BB149 -> BB150 to [0 .. 3.402823e+38] Setting edge weights for BB150 -> BB160 to [0 .. 3.402823e+38] Setting edge weights for BB150 -> BB151 to [0 .. 3.402823e+38] Setting edge weights for BB151 -> BB160 to [0 .. 3.402823e+38] Setting edge weights for BB151 -> BB152 to [0 .. 3.402823e+38] Setting edge weights for BB152 -> BB153 to [0 .. 3.402823e+38] Setting edge weights for BB153 -> BB155 to [0 .. 3.402823e+38] Setting edge weights for BB153 -> BB154 to [0 .. 3.402823e+38] Setting edge weights for BB154 -> BB159 to [0 .. 3.402823e+38] Setting edge weights for BB155 -> BB158 to [0 .. 3.402823e+38] Setting edge weights for BB155 -> BB156 to [0 .. 3.402823e+38] Setting edge weights for BB156 -> BB158 to [0 .. 3.402823e+38] Setting edge weights for BB156 -> BB157 to [0 .. 3.402823e+38] Setting edge weights for BB157 -> BB159 to [0 .. 3.402823e+38] Setting edge weights for BB158 -> BB159 to [0 .. 3.402823e+38] Setting edge weights for BB159 -> BB160 to [0 .. 3.402823e+38] Setting edge weights for BB160 -> BB161 to [0 .. 3.402823e+38] Setting edge weights for BB161 -> BB141 to [0 .. 3.402823e+38] Setting edge weights for BB161 -> BB162 to [0 .. 3.402823e+38] Setting edge weights for BB162 -> BB167 to [0 .. 3.402823e+38] Setting edge weights for BB162 -> BB163 to [0 .. 3.402823e+38] Setting edge weights for BB163 -> BB233 to [0 .. 3.402823e+38] Setting edge weights for BB163 -> BB171 to [0 .. 3.402823e+38] Setting edge weights for BB163 -> BB291 to [0 .. 3.402823e+38] Setting edge weights for BB163 -> BB220 to [0 .. 3.402823e+38] Setting edge weights for BB163 -> BB164 to [0 .. 3.402823e+38] Setting edge weights for BB164 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB164 -> BB291 to [0 .. 3.402823e+38] Setting edge weights for BB164 -> BB200 to [0 .. 3.402823e+38] Setting edge weights for BB164 -> BB171 to [0 .. 3.402823e+38] Setting edge weights for BB164 -> BB165 to [0 .. 3.402823e+38] Setting edge weights for BB165 -> BB246 to [0 .. 3.402823e+38] Setting edge weights for BB165 -> BB166 to [0 .. 3.402823e+38] Setting edge weights for BB166 -> BB291 to [0 .. 3.402823e+38] Setting edge weights for BB167 -> BB239 to [0 .. 3.402823e+38] Setting edge weights for BB167 -> BB168 to [0 .. 3.402823e+38] Setting edge weights for BB168 -> BB246 to [0 .. 3.402823e+38] Setting edge weights for BB168 -> BB169 to [0 .. 3.402823e+38] Setting edge weights for BB169 -> BB212 to [0 .. 3.402823e+38] Setting edge weights for BB169 -> BB170 to [0 .. 3.402823e+38] Setting edge weights for BB170 -> BB291 to [0 .. 3.402823e+38] Setting edge weights for BB171 -> BB176 to [0 .. 3.402823e+38] Setting edge weights for BB171 -> BB172 to [0 .. 3.402823e+38] Setting edge weights for BB172 -> BB174 to [0 .. 3.402823e+38] Setting edge weights for BB172 -> BB173 to [0 .. 3.402823e+38] Setting edge weights for BB173 -> BB175 to [0 .. 3.402823e+38] Setting edge weights for BB174 -> BB175 to [0 .. 3.402823e+38] Setting edge weights for BB175 -> BB182 to [0 .. 3.402823e+38] Setting edge weights for BB176 -> BB180 to [0 .. 3.402823e+38] Setting edge weights for BB176 -> BB177 to [0 .. 3.402823e+38] Setting edge weights for BB177 -> BB179 to [0 .. 3.402823e+38] Setting edge weights for BB177 -> BB178 to [0 .. 3.402823e+38] Setting edge weights for BB178 -> BB181 to [0 .. 3.402823e+38] Setting edge weights for BB179 -> BB181 to [0 .. 3.402823e+38] Setting edge weights for BB180 -> BB181 to [0 .. 3.402823e+38] Setting edge weights for BB181 -> BB182 to [0 .. 3.402823e+38] Setting edge weights for BB182 -> BB199 to [0 .. 3.402823e+38] Setting edge weights for BB182 -> BB183 to [0 .. 3.402823e+38] Setting edge weights for BB183 -> BB184 to [0 .. 3.402823e+38] Setting edge weights for BB184 -> BB186 to [0 .. 3.402823e+38] Setting edge weights for BB184 -> BB185 to [0 .. 3.402823e+38] Setting edge weights for BB185 -> BB187 to [0 .. 3.402823e+38] Setting edge weights for BB186 -> BB187 to [0 .. 3.402823e+38] Setting edge weights for BB187 -> BB199 to [0 .. 3.402823e+38] Setting edge weights for BB187 -> BB188 to [0 .. 3.402823e+38] Setting edge weights for BB188 -> BB199 to [0 .. 3.402823e+38] Setting edge weights for BB188 -> BB189 to [0 .. 3.402823e+38] Setting edge weights for BB189 -> BB199 to [0 .. 3.402823e+38] Setting edge weights for BB189 -> BB190 to [0 .. 3.402823e+38] Setting edge weights for BB190 -> BB199 to [0 .. 3.402823e+38] Setting edge weights for BB190 -> BB191 to [0 .. 3.402823e+38] Setting edge weights for BB191 -> BB192 to [0 .. 3.402823e+38] Setting edge weights for BB192 -> BB194 to [0 .. 3.402823e+38] Setting edge weights for BB192 -> BB193 to [0 .. 3.402823e+38] Setting edge weights for BB193 -> BB198 to [0 .. 3.402823e+38] Setting edge weights for BB194 -> BB197 to [0 .. 3.402823e+38] Setting edge weights for BB194 -> BB195 to [0 .. 3.402823e+38] Setting edge weights for BB195 -> BB197 to [0 .. 3.402823e+38] Setting edge weights for BB195 -> BB196 to [0 .. 3.402823e+38] Setting edge weights for BB196 -> BB198 to [0 .. 3.402823e+38] Setting edge weights for BB197 -> BB198 to [0 .. 3.402823e+38] Setting edge weights for BB198 -> BB199 to [0 .. 3.402823e+38] Setting edge weights for BB199 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB200 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB200 -> BB201 to [0 .. 3.402823e+38] Setting edge weights for BB201 -> BB204 to [0 .. 3.402823e+38] Setting edge weights for BB201 -> BB202 to [0 .. 3.402823e+38] Setting edge weights for BB202 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB202 -> BB203 to [0 .. 3.402823e+38] Setting edge weights for BB203 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB203 -> BB204 to [0 .. 3.402823e+38] Setting edge weights for BB204 -> BB205 to [0 .. 3.402823e+38] Setting edge weights for BB205 -> BB207 to [0 .. 3.402823e+38] Setting edge weights for BB205 -> BB206 to [0 .. 3.402823e+38] Setting edge weights for BB206 -> BB211 to [0 .. 3.402823e+38] Setting edge weights for BB207 -> BB210 to [0 .. 3.402823e+38] Setting edge weights for BB207 -> BB208 to [0 .. 3.402823e+38] Setting edge weights for BB208 -> BB210 to [0 .. 3.402823e+38] Setting edge weights for BB208 -> BB209 to [0 .. 3.402823e+38] Setting edge weights for BB209 -> BB211 to [0 .. 3.402823e+38] Setting edge weights for BB210 -> BB211 to [0 .. 3.402823e+38] Setting edge weights for BB211 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB212 -> BB213 to [0 .. 3.402823e+38] Setting edge weights for BB213 -> BB215 to [0 .. 3.402823e+38] Setting edge weights for BB213 -> BB214 to [0 .. 3.402823e+38] Setting edge weights for BB214 -> BB219 to [0 .. 3.402823e+38] Setting edge weights for BB215 -> BB218 to [0 .. 3.402823e+38] Setting edge weights for BB215 -> BB216 to [0 .. 3.402823e+38] Setting edge weights for BB216 -> BB218 to [0 .. 3.402823e+38] Setting edge weights for BB216 -> BB217 to [0 .. 3.402823e+38] Setting edge weights for BB217 -> BB219 to [0 .. 3.402823e+38] Setting edge weights for BB218 -> BB219 to [0 .. 3.402823e+38] Setting edge weights for BB219 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB220 -> BB221 to [0 .. 3.402823e+38] Setting edge weights for BB221 -> BB223 to [0 .. 3.402823e+38] Setting edge weights for BB221 -> BB222 to [0 .. 3.402823e+38] Setting edge weights for BB222 -> BB227 to [0 .. 3.402823e+38] Setting edge weights for BB223 -> BB226 to [0 .. 3.402823e+38] Setting edge weights for BB223 -> BB224 to [0 .. 3.402823e+38] Setting edge weights for BB224 -> BB226 to [0 .. 3.402823e+38] Setting edge weights for BB224 -> BB225 to [0 .. 3.402823e+38] Setting edge weights for BB225 -> BB227 to [0 .. 3.402823e+38] Setting edge weights for BB226 -> BB227 to [0 .. 3.402823e+38] Setting edge weights for BB227 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB228 -> BB229 to [0 .. 3.402823e+38] Setting edge weights for BB229 -> BB231 to [0 .. 3.402823e+38] Setting edge weights for BB229 -> BB230 to [0 .. 3.402823e+38] Setting edge weights for BB230 -> BB232 to [0 .. 3.402823e+38] Setting edge weights for BB231 -> BB232 to [0 .. 3.402823e+38] Setting edge weights for BB232 -> BB233 to [0 .. 3.402823e+38] Setting edge weights for BB233 -> BB236 to [0 .. 3.402823e+38] Setting edge weights for BB233 -> BB234 to [0 .. 3.402823e+38] Setting edge weights for BB234 -> BB236 to [0 .. 3.402823e+38] Setting edge weights for BB234 -> BB235 to [0 .. 3.402823e+38] Setting edge weights for BB235 -> BB228 to [0 .. 3.402823e+38] Setting edge weights for BB235 -> BB236 to [0 .. 3.402823e+38] Setting edge weights for BB236 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB236 -> BB237 to [0 .. 3.402823e+38] Setting edge weights for BB237 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB237 -> BB238 to [0 .. 3.402823e+38] Setting edge weights for BB238 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB239 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB239 -> BB240 to [0 .. 3.402823e+38] Setting edge weights for BB240 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB240 -> BB241 to [0 .. 3.402823e+38] Setting edge weights for BB241 -> BB242 to [0 .. 3.402823e+38] Setting edge weights for BB242 -> BB244 to [0 .. 3.402823e+38] Setting edge weights for BB242 -> BB243 to [0 .. 3.402823e+38] Setting edge weights for BB243 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB244 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB245 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB246 -> BB271 to [0 .. 3.402823e+38] Setting edge weights for BB246 -> BB247 to [0 .. 3.402823e+38] Setting edge weights for BB247 -> BB250 to [0 .. 3.402823e+38] Setting edge weights for BB247 -> BB248 to [0 .. 3.402823e+38] Setting edge weights for BB248 -> BB250 to [0 .. 3.402823e+38] Setting edge weights for BB248 -> BB249 to [0 .. 3.402823e+38] Setting edge weights for BB249 -> BB263 to [0 .. 3.402823e+38] Setting edge weights for BB250 -> BB254 to [0 .. 3.402823e+38] Setting edge weights for BB250 -> BB251 to [0 .. 3.402823e+38] Setting edge weights for BB251 -> BB254 to [0 .. 3.402823e+38] Setting edge weights for BB251 -> BB252 to [0 .. 3.402823e+38] Setting edge weights for BB252 -> BB254 to [0 .. 3.402823e+38] Setting edge weights for BB252 -> BB253 to [0 .. 3.402823e+38] Setting edge weights for BB253 -> BB263 to [0 .. 3.402823e+38] Setting edge weights for BB254 -> BB257 to [0 .. 3.402823e+38] Setting edge weights for BB254 -> BB255 to [0 .. 3.402823e+38] Setting edge weights for BB255 -> BB257 to [0 .. 3.402823e+38] Setting edge weights for BB255 -> BB256 to [0 .. 3.402823e+38] Setting edge weights for BB256 -> BB263 to [0 .. 3.402823e+38] Setting edge weights for BB256 -> BB257 to [0 .. 3.402823e+38] Setting edge weights for BB257 -> BB258 to [0 .. 3.402823e+38] Setting edge weights for BB258 -> BB260 to [0 .. 3.402823e+38] Setting edge weights for BB258 -> BB259 to [0 .. 3.402823e+38] Setting edge weights for BB259 -> BB261 to [0 .. 3.402823e+38] Setting edge weights for BB260 -> BB261 to [0 .. 3.402823e+38] Setting edge weights for BB261 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB262 -> BB263 to [0 .. 3.402823e+38] Setting edge weights for BB263 -> BB265 to [0 .. 3.402823e+38] Setting edge weights for BB263 -> BB264 to [0 .. 3.402823e+38] Setting edge weights for BB264 -> BB262 to [0 .. 3.402823e+38] Setting edge weights for BB264 -> BB265 to [0 .. 3.402823e+38] Setting edge weights for BB265 -> BB267 to [0 .. 3.402823e+38] Setting edge weights for BB265 -> BB266 to [0 .. 3.402823e+38] Setting edge weights for BB266 -> BB267 to [0 .. 3.402823e+38] Setting edge weights for BB267 -> BB269 to [0 .. 3.402823e+38] Setting edge weights for BB267 -> BB268 to [0 .. 3.402823e+38] Setting edge weights for BB268 -> BB270 to [0 .. 3.402823e+38] Setting edge weights for BB269 -> BB270 to [0 .. 3.402823e+38] Setting edge weights for BB270 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB271 -> BB272 to [0 .. 3.402823e+38] Setting edge weights for BB272 -> BB274 to [0 .. 3.402823e+38] Setting edge weights for BB272 -> BB273 to [0 .. 3.402823e+38] Setting edge weights for BB273 -> BB275 to [0 .. 3.402823e+38] Setting edge weights for BB274 -> BB275 to [0 .. 3.402823e+38] Setting edge weights for BB275 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB275 -> BB276 to [0 .. 3.402823e+38] Setting edge weights for BB276 -> BB278 to [0 .. 3.402823e+38] Setting edge weights for BB276 -> BB277 to [0 .. 3.402823e+38] Setting edge weights for BB277 -> BB288 to [0 .. 3.402823e+38] Setting edge weights for BB277 -> BB278 to [0 .. 3.402823e+38] Setting edge weights for BB278 -> BB279 to [0 .. 3.402823e+38] Setting edge weights for BB279 -> BB281 to [0 .. 3.402823e+38] Setting edge weights for BB279 -> BB280 to [0 .. 3.402823e+38] Setting edge weights for BB280 -> BB282 to [0 .. 3.402823e+38] Setting edge weights for BB281 -> BB282 to [0 .. 3.402823e+38] Setting edge weights for BB282 -> BB288 to [0 .. 3.402823e+38] Setting edge weights for BB283 -> BB284 to [0 .. 3.402823e+38] Setting edge weights for BB284 -> BB286 to [0 .. 3.402823e+38] Setting edge weights for BB284 -> BB285 to [0 .. 3.402823e+38] Setting edge weights for BB285 -> BB287 to [0 .. 3.402823e+38] Setting edge weights for BB286 -> BB287 to [0 .. 3.402823e+38] Setting edge weights for BB287 -> BB288 to [0 .. 3.402823e+38] Setting edge weights for BB288 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB288 -> BB289 to [0 .. 3.402823e+38] Setting edge weights for BB289 -> BB283 to [0 .. 3.402823e+38] Setting edge weights for BB289 -> BB290 to [0 .. 3.402823e+38] Setting edge weights for BB290 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB291 -> BB292 to [0 .. 3.402823e+38] Setting edge weights for BB292 -> BB294 to [0 .. 3.402823e+38] Setting edge weights for BB292 -> BB293 to [0 .. 3.402823e+38] Setting edge weights for BB293 -> BB295 to [0 .. 3.402823e+38] Setting edge weights for BB294 -> BB295 to [0 .. 3.402823e+38] Setting edge weights for BB295 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB296 -> BB299 to [0 .. 3.402823e+38] Setting edge weights for BB296 -> BB297 to [0 .. 3.402823e+38] Setting edge weights for BB297 -> BB299 to [0 .. 3.402823e+38] Setting edge weights for BB297 -> BB298 to [0 .. 3.402823e+38] Setting edge weights for BB298 -> BB136 to [0 .. 3.402823e+38] Setting edge weights for BB298 -> BB299 to [0 .. 3.402823e+38] Setting edge weights for BB299 -> BB304 to [0 .. 3.402823e+38] Setting edge weights for BB299 -> BB300 to [0 .. 3.402823e+38] Setting edge weights for BB300 -> BB304 to [0 .. 3.402823e+38] Setting edge weights for BB300 -> BB301 to [0 .. 3.402823e+38] Setting edge weights for BB301 -> BB304 to [0 .. 3.402823e+38] Setting edge weights for BB301 -> BB302 to [0 .. 3.402823e+38] Setting edge weights for BB302 -> BB304 to [0 .. 3.402823e+38] Setting edge weights for BB302 -> BB303 to [0 .. 3.402823e+38] Setting edge weights for BB303 -> BB304 to [0 .. 3.402823e+38] *************** Finishing PHASE Compute preds Trees after Compute preds ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB31 ( cond ) i bwd BB16 [0015] 1 BB15 1 [0CA..0CF)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [2EE..30D) i BB80 [0207] 1 BB79 1 [000..000)-> BB82 (always) i internal BB81 [0208] 0 1 [000..000) i internal BB82 [0209] 2 BB80,BB81 1 [000..000)-> BB83 (always) i internal BB83 [0211] 1 BB82 1 [000..000) i internal BB84 [0212] 1 BB83 1 [???..???)-> BB124 ( cond ) internal BB85 [0079] 1 BB84 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A) i bwd BB98 [0218] 1 BB97 1 [383..384)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB98 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB98 1 [383..384)-> BB101 (always) i bwd BB101 [0223] 1 BB100 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB101 1 [???..???) internal bwd BB103 [0226] 1 BB102 1 [000..000)-> BB113 ( cond ) i internal bwd BB104 [0227] 1 BB103 1 [000..000) i internal bwd BB105 [0231] 1 BB104 1 [000..000) i internal bwd BB106 [0232] 1 BB105 1 [000..000)-> BB112 (always) i internal bwd BB107 [0233] 0 1 [000..000) i internal bwd BB108 [0236] 1 BB107 1 [000..000)-> BB110 ( cond ) i internal bwd BB109 [0237] 1 BB108 1 [000..000)-> BB111 (always) i internal bwd BB110 [0238] 1 BB108 1 [000..000) i internal bwd BB111 [0239] 2 BB109,BB110 1 [???..???) internal bwd BB112 [0234] 2 BB106,BB111 1 [???..???)-> BB114 (always) internal bwd BB113 [0228] 1 BB103 1 [000..000) i internal bwd BB114 [0229] 2 BB112,BB113 1 [???..???) i internal bwd BB115 [0241] 1 BB114 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB115 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB115 1 [391..392)-> BB118 (always) i bwd BB118 [0246] 1 BB117 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB118 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB84,BB85,BB95,BB123 1 [3C8..3D0)-> BB135 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB135 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB135 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8) i BB128 [0250] 1 BB127 1 [3DC..3DD)-> BB130 ( cond ) i BB129 [0251] 1 BB128 1 [3DC..3DD)-> BB134 (always) i BB130 [0252] 1 BB128 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 3 BB129,BB132,BB133 1 [???..???) internal BB135 [0100] 4 BB124,BB125,BB126,BB134 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [42C..435) i bwd BB145 [0259] 1 BB144 1 [000..000)-> BB147 ( cond ) i internal bwd BB146 [0260] 1 BB145 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB145 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461) i bwd BB153 [0265] 1 BB152 1 [44F..450)-> BB155 ( cond ) i bwd BB154 [0266] 1 BB153 1 [44F..450)-> BB159 (always) i bwd BB155 [0267] 1 BB153 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB154,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB212 ( cond ) i bwd BB170 [0124] 1 BB169 1 [4E4..4E9)-> BB291 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D) i bwd BB184 [0273] 1 BB183 1 [521..522)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB184 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB184 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559) i bwd BB192 [0279] 1 BB191 1 [547..548)-> BB194 ( cond ) i bwd BB193 [0280] 1 BB192 1 [547..548)-> BB198 (always) i bwd BB194 [0281] 1 BB192 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB193,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598) i bwd BB205 [0288] 1 BB204 1 [584..585)-> BB207 ( cond ) i bwd BB206 [0289] 1 BB205 1 [584..585)-> BB211 (always) i bwd BB207 [0290] 1 BB205 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB206,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB212 [0148] 1 BB169 1 [598..5A9) i bwd BB213 [0297] 1 BB212 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 BB213 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB214,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB263 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 1 BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 4 BB249,BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB170 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB135,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 ***** BB01 STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct V41 tmp1 [000010] ----------- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct V75 tmp35 [000019] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct V42 tmp2 [001480] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct V42 tmp2 [001481] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct V42 tmp2 [000020] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] n---------- arg0 +--* OBJ struct [000031] ----------- | \--* ADDR byref [000028] -------N--- | \--* LCL_VAR struct V42 tmp2 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct V77 tmp37 [000065] n---------- \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct V77 tmp37 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB31 (cond), preds={BB14} succs={BB16,BB31} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* EQ int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB16 [0CA..0CF) -> BB48 (always), preds={BB15} succs={BB48} ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] n---------- arg0 +--* OBJ struct [001160] ----------- | \--* ADDR byref [001157] -------N--- | \--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB79 [2EE..30D), preds={BB74,BB78} succs={BB80} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct V48 tmp8 [000164] ----------- \--* CNS_INT int 0 ------------ BB80 [000..000) -> BB82 (always), preds={BB79} succs={BB82} ***** BB80 STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] ----------- * NOP void ------------ BB81 [000..000), preds={} succs={BB82} ***** BB81 STMT00326 ( INL09 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class ------------ BB82 [000..000) -> BB83 (always), preds={BB80,BB81} succs={BB83} ------------ BB83 [000..000), preds={BB82} succs={BB84} ***** BB83 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct V48 tmp8 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 ***** BB83 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct V48 tmp8 [001556] ----------- \--* CNS_INT int 4 ------------ BB84 [???..???) -> BB124 (cond), preds={BB83} succs={BB85,BB124} ***** BB84 STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct V25 loc21 [000169] ----------- \--* LCL_VAR struct V48 tmp8 ***** BB84 STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct V19 loc15 [000172] ----------- \--* LCL_VAR struct V25 loc21 ***** BB84 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 ***** BB84 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB84} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB123 (always), preds={BB92,BB93} succs={BB123} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB97 [373..39A), preds={BB96} succs={BB98} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* FIELD int :_length [001576] ----------- | \--* ADDR byref [001577] -------N--- | \--* LCL_VAR struct V19 loc15 [001065] ----------- \--* CNS_INT int 2 ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct V78 tmp38 [001581] ----------- \--* CNS_INT int 0 ------------ BB98 [383..384) -> BB100 (cond), preds={BB97} succs={BB99,BB100} ***** BB98 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB98} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct V78 tmp38 [001613] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384) -> BB101 (always), preds={BB98} succs={BB101} ------------ BB101 [383..384), preds={BB100} succs={BB102} ***** BB101 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct V78 tmp38 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 ***** BB101 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct V78 tmp38 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB102 [???..???), preds={BB99,BB101} succs={BB103} ***** BB102 STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct V68 tmp28 [001586] ----------- \--* LCL_VAR struct V78 tmp38 ***** BB102 STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct V79 tmp39 [001081] n---------- \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 ------------ BB103 [000..000) -> BB113 (cond), preds={BB102} succs={BB104,BB113} ***** BB103 STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB103 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001647] ----------- \--* FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct V79 tmp39 ------------ BB104 [000..000), preds={BB103} succs={BB105} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* FIELD byref :_reference [001632] ----------- \--* ADDR byref [001631] -------N--- \--* LCL_VAR struct V79 tmp39 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* FIELD byref :_reference [001634] ----------- \--* ADDR byref [001635] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB105 [000..000), preds={BB104} succs={BB106} ***** BB105 STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] ----------- * NOP void ------------ BB106 [000..000) -> BB112 (always), preds={BB105} succs={BB112} ***** BB106 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB107 [000..000), preds={} succs={BB108} ***** BB107 STMT00350 ( INL19 @ 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001690] -A--------- * ASG long [001689] D------N--- +--* LCL_VAR long V84 tmp44 [001659] ----------- \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 ------------ BB108 [000..000) -> BB110 (cond), preds={BB107} succs={BB109,BB110} ***** BB108 STMT00347 ( INL21 @ 0x000[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001682] ----------- * JTRUE void [001681] N--------U- \--* GT int [001678] ----------- +--* LCL_VAR long V84 tmp44 [001680] ----------- \--* CNS_INT long 0x400 ------------ BB109 [000..000) -> BB111 (always), preds={BB108} succs={BB111} ***** BB109 STMT00349 ( INL21 @ 0x009[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001688] --C-G------ * CALL r2r_ind void [001685] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001686] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001687] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------ BB110 [000..000), preds={BB108} succs={BB111} ***** BB110 STMT00348 ( INL21 @ 0x012[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001684] --C-G------ * CALL r2r_ind void [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001683] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------ BB111 [???..???), preds={BB109,BB110} succs={BB112} ------------ BB112 [???..???) -> BB114 (always), preds={BB106,BB111} succs={BB114} ------------ BB113 [000..000), preds={BB103} succs={BB114} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() ------------ BB114 [???..???), preds={BB112,BB113} succs={BB115} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct V85 tmp45 [001693] ----------- \--* CNS_INT int 0 ------------ BB115 [391..392) -> BB117 (cond), preds={BB114} succs={BB116,BB117} ***** BB115 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB115} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct V85 tmp45 [001725] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392) -> BB118 (always), preds={BB115} succs={BB118} ------------ BB118 [391..392), preds={BB117} succs={BB119} ***** BB118 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct V85 tmp45 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 ***** BB118 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct V85 tmp45 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB118} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct V19 loc15 [001698] ----------- \--* LCL_VAR struct V85 tmp45 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* FIELD int :_length [001023] ----------- | | \--* ADDR byref [001022] -------N--- | | \--* LCL_VAR struct V19 loc15 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* FIELD byref :_reference [001027] ----------- | | \--* ADDR byref [001026] -------N--- | | \--* LCL_VAR struct V19 loc15 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB94,BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB135 (cond), preds={BB84,BB85,BB95,BB123} succs={BB125,BB135} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB135 (cond), preds={BB124} succs={BB126,BB135} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB135 (cond), preds={BB125} succs={BB127,BB135} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8), preds={BB126} succs={BB128} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB128 [3DC..3DD) -> BB130 (cond), preds={BB127} succs={BB129,BB130} ***** BB128 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* NE int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB129 [3DC..3DD) -> BB134 (always), preds={BB128} succs={BB134} ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB128} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------ BB134 [???..???), preds={BB129,BB132,BB133} succs={BB135} ------------ BB135 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB134} succs={BB296} ***** BB135 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 ***** BB135 STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct V90 tmp50 [000193] n---------- \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB135 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct V90 tmp50 ***** BB135 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 ***** BB135 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB144 [42C..435), preds={BB142,BB143} succs={BB145} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 ------------ BB145 [000..000) -> BB147 (cond), preds={BB144} succs={BB146,BB147} ***** BB145 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB145 STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB145 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 ------------ BB146 [000..000) -> BB148 (always), preds={BB145} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB145} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* FIELD int :_length [000884] ----------- | | \--* ADDR byref [000883] -------N--- | | \--* LCL_VAR struct V19 loc15 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* FIELD byref :_reference [000888] ----------- | | \--* ADDR byref [000887] -------N--- | | \--* LCL_VAR struct V19 loc15 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 ------------ BB152 [44F..461), preds={BB151} succs={BB153} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB153 [44F..450) -> BB155 (cond), preds={BB152} succs={BB154,BB155} ***** BB153 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* NE int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB154 [44F..450) -> BB159 (always), preds={BB153} succs={BB159} ------------ BB155 [44F..450) -> BB158 (cond), preds={BB153} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------ BB159 [???..???), preds={BB154,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB212 (cond), preds={BB168} succs={BB170,BB212} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* EQ int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB170 [4E4..4E9) -> BB291 (always), preds={BB169} succs={BB291} ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 ------------ BB183 [521..52D), preds={BB182} succs={BB184} ------------ BB184 [521..522) -> BB186 (cond), preds={BB183} succs={BB185,BB186} ***** BB184 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 ***** BB184 STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 ***** BB184 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 ------------ BB185 [521..522) -> BB187 (always), preds={BB184} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB184} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* FIELD int :_length [000691] ----------- | | \--* ADDR byref [000690] -------N--- | | \--* LCL_VAR struct V19 loc15 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* FIELD byref :_reference [000695] ----------- | | \--* ADDR byref [000694] -------N--- | | \--* LCL_VAR struct V19 loc15 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 ------------ BB191 [547..559), preds={BB190} succs={BB192} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB192 [547..548) -> BB194 (cond), preds={BB191} succs={BB193,BB194} ***** BB192 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* NE int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB193 [547..548) -> BB198 (always), preds={BB192} succs={BB198} ------------ BB194 [547..548) -> BB197 (cond), preds={BB192} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------ BB198 [???..???), preds={BB193,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 ------------ BB204 [584..598), preds={BB201,BB203} succs={BB205} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB205 [584..585) -> BB207 (cond), preds={BB204} succs={BB206,BB207} ***** BB205 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* NE int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB206 [584..585) -> BB211 (always), preds={BB205} succs={BB211} ------------ BB207 [584..585) -> BB210 (cond), preds={BB205} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------ BB211 [???..???) -> BB296 (always), preds={BB206,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 ------------ BB212 [598..5A9), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB213 [598..599) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* NE int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB214 [598..599) -> BB219 (always), preds={BB213} succs={BB219} ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 ------------ BB217 [598..599) -> BB219 (always), preds={BB216} succs={BB219} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB218 [598..599), preds={BB215,BB216} succs={BB219} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------ BB219 [???..???) -> BB296 (always), preds={BB214,BB217,BB218} succs={BB296} ------------ BB220 [5A9..5BA), preds={BB163} succs={BB221} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB221 [5A9..5AA) -> BB223 (cond), preds={BB220} succs={BB222,BB223} ***** BB221 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* NE int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB222 [5A9..5AA) -> BB227 (always), preds={BB221} succs={BB227} ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB221} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 ------------ BB225 [5A9..5AA) -> BB227 (always), preds={BB224} succs={BB227} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA), preds={BB223,BB224} succs={BB227} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------ BB227 [???..???) -> BB296 (always), preds={BB222,BB225,BB226} succs={BB296} ------------ BB228 [5BA..5CE), preds={BB235} succs={BB229} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 ------------ BB229 [000..000) -> BB231 (cond), preds={BB228} succs={BB230,BB231} ***** BB229 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 ***** BB229 STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 ***** BB229 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 ------------ BB230 [000..000) -> BB232 (always), preds={BB229} succs={BB232} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB229} succs={BB232} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------ BB232 [???..???), preds={BB230,BB231} succs={BB233} ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB232} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 ------------ BB241 [634..64D), preds={BB240} succs={BB242} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 ------------ BB242 [000..000) -> BB244 (cond), preds={BB241} succs={BB243,BB244} ***** BB242 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 ***** BB242 STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 ***** BB242 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 ------------ BB243 [000..000) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB244 [000..000), preds={BB242} succs={BB245} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------ BB245 [???..???) -> BB296 (always), preds={BB243,BB244} succs={BB296} ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB248 [665..672) -> BB250 (cond), preds={BB247} succs={BB249,BB250} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* NE int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 ------------ BB249 [672..67A) -> BB263 (always), preds={BB248} succs={BB263} ***** BB249 STMT00124 ( 0x672[E-] ... 0x676 ) [000580] -A--------- * ASG int [000579] D------N--- +--* LCL_VAR int V38 loc34 [000578] ----------- \--* ADD int [000576] ----------- +--* LCL_VAR int V38 loc34 [000577] ----------- \--* CNS_INT int 1 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE), preds={BB254,BB255,BB256} succs={BB258} ------------ BB258 [6D1..6D2) -> BB260 (cond), preds={BB257} succs={BB259,BB260} ***** BB258 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 ***** BB258 STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 ***** BB258 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 ------------ BB259 [6D1..6D2) -> BB261 (always), preds={BB258} succs={BB261} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2), preds={BB258} succs={BB261} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB261 [???..???) -> BB296 (always), preds={BB259,BB260} succs={BB296} ------------ BB262 [6DE..6E4), preds={BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB249,BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 ------------ BB271 [731..744), preds={BB246} succs={BB272} ------------ BB272 [731..732) -> BB274 (cond), preds={BB271} succs={BB273,BB274} ***** BB272 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 ***** BB272 STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 ***** BB272 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 ------------ BB273 [731..732) -> BB275 (always), preds={BB272} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB272} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB288 (cond), preds={BB276} succs={BB278,BB288} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 ------------ BB278 [75E..774), preds={BB276,BB277} succs={BB279} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 ------------ BB279 [000..000) -> BB281 (cond), preds={BB278} succs={BB280,BB281} ***** BB279 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 ***** BB279 STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 ***** BB279 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 ------------ BB280 [000..000) -> BB282 (always), preds={BB279} succs={BB282} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB281 [000..000), preds={BB279} succs={BB282} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------ BB282 [???..???) -> BB288 (always), preds={BB280,BB281} succs={BB288} ------------ BB283 [774..788), preds={BB289} succs={BB284} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 ------------ BB284 [000..000) -> BB286 (cond), preds={BB283} succs={BB285,BB286} ***** BB284 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 ***** BB284 STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 ***** BB284 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 ------------ BB285 [000..000) -> BB287 (always), preds={BB284} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB284} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------ BB287 [???..???), preds={BB285,BB286} succs={BB288} ------------ BB288 [788..793) -> BB296 (cond), preds={BB277,BB282,BB287} succs={BB289,BB296} ***** BB288 STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB288} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA), preds={BB163(2),BB164(2),BB166,BB170} succs={BB292} ------------ BB292 [7A2..7A3) -> BB294 (cond), preds={BB291} succs={BB293,BB294} ***** BB292 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 ***** BB292 STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 ***** BB292 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 ------------ BB293 [7A2..7A3) -> BB295 (always), preds={BB292} succs={BB295} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB292} succs={BB295} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB295 [???..???), preds={BB293,BB294} succs={BB296} ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB135,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Tail merge A set of 2 preds of BB263 end with the same tree STMT00124 ( 0x672[E-] ... 0x676 ) [000580] -A--------- * ASG int [000579] D------N--- +--* LCL_VAR int V38 loc34 [000578] ----------- \--* ADD int [000576] ----------- +--* LCL_VAR int V38 loc34 [000577] ----------- \--* CNS_INT int 1 Will cross-jump to BB262 unlinking STMT00124 ( 0x672[E-] ... 0x676 ) [000580] -A--------- * ASG int [000579] D------N--- +--* LCL_VAR int V38 loc34 [000578] ----------- \--* ADD int [000576] ----------- +--* LCL_VAR int V38 loc34 [000577] ----------- \--* CNS_INT int 1 from BB249 BB249 becomes empty Setting edge weights for BB249 -> BB262 to [0 .. 3.402823e+38] Did 1 tail merges in BB263 *************** Finishing PHASE Tail merge Trees after Tail merge ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB31 ( cond ) i bwd BB16 [0015] 1 BB15 1 [0CA..0CF)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [2EE..30D) i BB80 [0207] 1 BB79 1 [000..000)-> BB82 (always) i internal BB81 [0208] 0 1 [000..000) i internal BB82 [0209] 2 BB80,BB81 1 [000..000)-> BB83 (always) i internal BB83 [0211] 1 BB82 1 [000..000) i internal BB84 [0212] 1 BB83 1 [???..???)-> BB124 ( cond ) internal BB85 [0079] 1 BB84 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A) i bwd BB98 [0218] 1 BB97 1 [383..384)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB98 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB98 1 [383..384)-> BB101 (always) i bwd BB101 [0223] 1 BB100 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB101 1 [???..???) internal bwd BB103 [0226] 1 BB102 1 [000..000)-> BB113 ( cond ) i internal bwd BB104 [0227] 1 BB103 1 [000..000) i internal bwd BB105 [0231] 1 BB104 1 [000..000) i internal bwd BB106 [0232] 1 BB105 1 [000..000)-> BB112 (always) i internal bwd BB107 [0233] 0 1 [000..000) i internal bwd BB108 [0236] 1 BB107 1 [000..000)-> BB110 ( cond ) i internal bwd BB109 [0237] 1 BB108 1 [000..000)-> BB111 (always) i internal bwd BB110 [0238] 1 BB108 1 [000..000) i internal bwd BB111 [0239] 2 BB109,BB110 1 [???..???) internal bwd BB112 [0234] 2 BB106,BB111 1 [???..???)-> BB114 (always) internal bwd BB113 [0228] 1 BB103 1 [000..000) i internal bwd BB114 [0229] 2 BB112,BB113 1 [???..???) i internal bwd BB115 [0241] 1 BB114 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB115 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB115 1 [391..392)-> BB118 (always) i bwd BB118 [0246] 1 BB117 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB118 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB84,BB85,BB95,BB123 1 [3C8..3D0)-> BB135 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB135 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB135 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8) i BB128 [0250] 1 BB127 1 [3DC..3DD)-> BB130 ( cond ) i BB129 [0251] 1 BB128 1 [3DC..3DD)-> BB134 (always) i BB130 [0252] 1 BB128 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 3 BB129,BB132,BB133 1 [???..???) internal BB135 [0100] 4 BB124,BB125,BB126,BB134 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [42C..435) i bwd BB145 [0259] 1 BB144 1 [000..000)-> BB147 ( cond ) i internal bwd BB146 [0260] 1 BB145 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB145 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461) i bwd BB153 [0265] 1 BB152 1 [44F..450)-> BB155 ( cond ) i bwd BB154 [0266] 1 BB153 1 [44F..450)-> BB159 (always) i bwd BB155 [0267] 1 BB153 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB154,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB212 ( cond ) i bwd BB170 [0124] 1 BB169 1 [4E4..4E9)-> BB291 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D) i bwd BB184 [0273] 1 BB183 1 [521..522)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB184 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB184 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559) i bwd BB192 [0279] 1 BB191 1 [547..548)-> BB194 ( cond ) i bwd BB193 [0280] 1 BB192 1 [547..548)-> BB198 (always) i bwd BB194 [0281] 1 BB192 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB193,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598) i bwd BB205 [0288] 1 BB204 1 [584..585)-> BB207 ( cond ) i bwd BB206 [0289] 1 BB205 1 [584..585)-> BB211 (always) i bwd BB207 [0290] 1 BB205 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB206,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB212 [0148] 1 BB169 1 [598..5A9) i bwd BB213 [0297] 1 BB212 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 BB213 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB214,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB170 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB135,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 ***** BB01 STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct V41 tmp1 [000010] ----------- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct V75 tmp35 [000019] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct V42 tmp2 [001480] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct V42 tmp2 [001481] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct V42 tmp2 [000020] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] n---------- arg0 +--* OBJ struct [000031] ----------- | \--* ADDR byref [000028] -------N--- | \--* LCL_VAR struct V42 tmp2 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct V77 tmp37 [000065] n---------- \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct V77 tmp37 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB31 (cond), preds={BB14} succs={BB16,BB31} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* EQ int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB16 [0CA..0CF) -> BB48 (always), preds={BB15} succs={BB48} ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] n---------- arg0 +--* OBJ struct [001160] ----------- | \--* ADDR byref [001157] -------N--- | \--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB79 [2EE..30D), preds={BB74,BB78} succs={BB80} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct V48 tmp8 [000164] ----------- \--* CNS_INT int 0 ------------ BB80 [000..000) -> BB82 (always), preds={BB79} succs={BB82} ***** BB80 STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] ----------- * NOP void ------------ BB81 [000..000), preds={} succs={BB82} ***** BB81 STMT00326 ( INL09 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class ------------ BB82 [000..000) -> BB83 (always), preds={BB80,BB81} succs={BB83} ------------ BB83 [000..000), preds={BB82} succs={BB84} ***** BB83 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct V48 tmp8 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 ***** BB83 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct V48 tmp8 [001556] ----------- \--* CNS_INT int 4 ------------ BB84 [???..???) -> BB124 (cond), preds={BB83} succs={BB85,BB124} ***** BB84 STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct V25 loc21 [000169] ----------- \--* LCL_VAR struct V48 tmp8 ***** BB84 STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct V19 loc15 [000172] ----------- \--* LCL_VAR struct V25 loc21 ***** BB84 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 ***** BB84 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB84} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB123 (always), preds={BB92,BB93} succs={BB123} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB97 [373..39A), preds={BB96} succs={BB98} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* FIELD int :_length [001576] ----------- | \--* ADDR byref [001577] -------N--- | \--* LCL_VAR struct V19 loc15 [001065] ----------- \--* CNS_INT int 2 ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct V78 tmp38 [001581] ----------- \--* CNS_INT int 0 ------------ BB98 [383..384) -> BB100 (cond), preds={BB97} succs={BB99,BB100} ***** BB98 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB98} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct V78 tmp38 [001613] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384) -> BB101 (always), preds={BB98} succs={BB101} ------------ BB101 [383..384), preds={BB100} succs={BB102} ***** BB101 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct V78 tmp38 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 ***** BB101 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct V78 tmp38 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB102 [???..???), preds={BB99,BB101} succs={BB103} ***** BB102 STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct V68 tmp28 [001586] ----------- \--* LCL_VAR struct V78 tmp38 ***** BB102 STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct V79 tmp39 [001081] n---------- \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 ------------ BB103 [000..000) -> BB113 (cond), preds={BB102} succs={BB104,BB113} ***** BB103 STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB103 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001647] ----------- \--* FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct V79 tmp39 ------------ BB104 [000..000), preds={BB103} succs={BB105} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* FIELD byref :_reference [001632] ----------- \--* ADDR byref [001631] -------N--- \--* LCL_VAR struct V79 tmp39 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* FIELD byref :_reference [001634] ----------- \--* ADDR byref [001635] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB105 [000..000), preds={BB104} succs={BB106} ***** BB105 STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] ----------- * NOP void ------------ BB106 [000..000) -> BB112 (always), preds={BB105} succs={BB112} ***** BB106 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB107 [000..000), preds={} succs={BB108} ***** BB107 STMT00350 ( INL19 @ 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001690] -A--------- * ASG long [001689] D------N--- +--* LCL_VAR long V84 tmp44 [001659] ----------- \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 ------------ BB108 [000..000) -> BB110 (cond), preds={BB107} succs={BB109,BB110} ***** BB108 STMT00347 ( INL21 @ 0x000[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001682] ----------- * JTRUE void [001681] N--------U- \--* GT int [001678] ----------- +--* LCL_VAR long V84 tmp44 [001680] ----------- \--* CNS_INT long 0x400 ------------ BB109 [000..000) -> BB111 (always), preds={BB108} succs={BB111} ***** BB109 STMT00349 ( INL21 @ 0x009[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001688] --C-G------ * CALL r2r_ind void [001685] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001686] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001687] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------ BB110 [000..000), preds={BB108} succs={BB111} ***** BB110 STMT00348 ( INL21 @ 0x012[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001684] --C-G------ * CALL r2r_ind void [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001683] ----------- arg2 \--* LCL_VAR long V84 tmp44 ------------ BB111 [???..???), preds={BB109,BB110} succs={BB112} ------------ BB112 [???..???) -> BB114 (always), preds={BB106,BB111} succs={BB114} ------------ BB113 [000..000), preds={BB103} succs={BB114} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() ------------ BB114 [???..???), preds={BB112,BB113} succs={BB115} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct V85 tmp45 [001693] ----------- \--* CNS_INT int 0 ------------ BB115 [391..392) -> BB117 (cond), preds={BB114} succs={BB116,BB117} ***** BB115 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB115} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct V85 tmp45 [001725] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392) -> BB118 (always), preds={BB115} succs={BB118} ------------ BB118 [391..392), preds={BB117} succs={BB119} ***** BB118 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct V85 tmp45 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 ***** BB118 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct V85 tmp45 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB118} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct V19 loc15 [001698] ----------- \--* LCL_VAR struct V85 tmp45 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* FIELD int :_length [001023] ----------- | | \--* ADDR byref [001022] -------N--- | | \--* LCL_VAR struct V19 loc15 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* FIELD byref :_reference [001027] ----------- | | \--* ADDR byref [001026] -------N--- | | \--* LCL_VAR struct V19 loc15 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB94,BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB135 (cond), preds={BB84,BB85,BB95,BB123} succs={BB125,BB135} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB135 (cond), preds={BB124} succs={BB126,BB135} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB135 (cond), preds={BB125} succs={BB127,BB135} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8), preds={BB126} succs={BB128} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB128 [3DC..3DD) -> BB130 (cond), preds={BB127} succs={BB129,BB130} ***** BB128 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* NE int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB129 [3DC..3DD) -> BB134 (always), preds={BB128} succs={BB134} ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB128} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------ BB134 [???..???), preds={BB129,BB132,BB133} succs={BB135} ------------ BB135 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB134} succs={BB296} ***** BB135 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 ***** BB135 STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct V90 tmp50 [000193] n---------- \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB135 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct V90 tmp50 ***** BB135 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 ***** BB135 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB144 [42C..435), preds={BB142,BB143} succs={BB145} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 ------------ BB145 [000..000) -> BB147 (cond), preds={BB144} succs={BB146,BB147} ***** BB145 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB145 STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB145 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 ------------ BB146 [000..000) -> BB148 (always), preds={BB145} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB145} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* FIELD int :_length [000884] ----------- | | \--* ADDR byref [000883] -------N--- | | \--* LCL_VAR struct V19 loc15 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* FIELD byref :_reference [000888] ----------- | | \--* ADDR byref [000887] -------N--- | | \--* LCL_VAR struct V19 loc15 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 ------------ BB152 [44F..461), preds={BB151} succs={BB153} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB153 [44F..450) -> BB155 (cond), preds={BB152} succs={BB154,BB155} ***** BB153 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* NE int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB154 [44F..450) -> BB159 (always), preds={BB153} succs={BB159} ------------ BB155 [44F..450) -> BB158 (cond), preds={BB153} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------ BB159 [???..???), preds={BB154,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB212 (cond), preds={BB168} succs={BB170,BB212} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* EQ int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB170 [4E4..4E9) -> BB291 (always), preds={BB169} succs={BB291} ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 ------------ BB183 [521..52D), preds={BB182} succs={BB184} ------------ BB184 [521..522) -> BB186 (cond), preds={BB183} succs={BB185,BB186} ***** BB184 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 ***** BB184 STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 ***** BB184 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 ------------ BB185 [521..522) -> BB187 (always), preds={BB184} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB184} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* FIELD int :_length [000691] ----------- | | \--* ADDR byref [000690] -------N--- | | \--* LCL_VAR struct V19 loc15 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* FIELD byref :_reference [000695] ----------- | | \--* ADDR byref [000694] -------N--- | | \--* LCL_VAR struct V19 loc15 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 ------------ BB191 [547..559), preds={BB190} succs={BB192} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB192 [547..548) -> BB194 (cond), preds={BB191} succs={BB193,BB194} ***** BB192 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* NE int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB193 [547..548) -> BB198 (always), preds={BB192} succs={BB198} ------------ BB194 [547..548) -> BB197 (cond), preds={BB192} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------ BB198 [???..???), preds={BB193,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 ------------ BB204 [584..598), preds={BB201,BB203} succs={BB205} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB205 [584..585) -> BB207 (cond), preds={BB204} succs={BB206,BB207} ***** BB205 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* NE int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB206 [584..585) -> BB211 (always), preds={BB205} succs={BB211} ------------ BB207 [584..585) -> BB210 (cond), preds={BB205} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------ BB211 [???..???) -> BB296 (always), preds={BB206,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 ------------ BB212 [598..5A9), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB213 [598..599) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* NE int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB214 [598..599) -> BB219 (always), preds={BB213} succs={BB219} ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 ------------ BB217 [598..599) -> BB219 (always), preds={BB216} succs={BB219} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB218 [598..599), preds={BB215,BB216} succs={BB219} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------ BB219 [???..???) -> BB296 (always), preds={BB214,BB217,BB218} succs={BB296} ------------ BB220 [5A9..5BA), preds={BB163} succs={BB221} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB221 [5A9..5AA) -> BB223 (cond), preds={BB220} succs={BB222,BB223} ***** BB221 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* NE int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB222 [5A9..5AA) -> BB227 (always), preds={BB221} succs={BB227} ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB221} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 ------------ BB225 [5A9..5AA) -> BB227 (always), preds={BB224} succs={BB227} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA), preds={BB223,BB224} succs={BB227} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------ BB227 [???..???) -> BB296 (always), preds={BB222,BB225,BB226} succs={BB296} ------------ BB228 [5BA..5CE), preds={BB235} succs={BB229} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 ------------ BB229 [000..000) -> BB231 (cond), preds={BB228} succs={BB230,BB231} ***** BB229 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 ***** BB229 STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 ***** BB229 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 ------------ BB230 [000..000) -> BB232 (always), preds={BB229} succs={BB232} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB229} succs={BB232} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------ BB232 [???..???), preds={BB230,BB231} succs={BB233} ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB232} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 ------------ BB241 [634..64D), preds={BB240} succs={BB242} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 ------------ BB242 [000..000) -> BB244 (cond), preds={BB241} succs={BB243,BB244} ***** BB242 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 ***** BB242 STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 ***** BB242 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 ------------ BB243 [000..000) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB244 [000..000), preds={BB242} succs={BB245} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------ BB245 [???..???) -> BB296 (always), preds={BB243,BB244} succs={BB296} ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB248 [665..672) -> BB250 (cond), preds={BB247} succs={BB249,BB250} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* NE int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 ------------ BB249 [672..67A) -> BB262 (always), preds={BB248} succs={BB262} ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE), preds={BB254,BB255,BB256} succs={BB258} ------------ BB258 [6D1..6D2) -> BB260 (cond), preds={BB257} succs={BB259,BB260} ***** BB258 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 ***** BB258 STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 ***** BB258 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 ------------ BB259 [6D1..6D2) -> BB261 (always), preds={BB258} succs={BB261} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2), preds={BB258} succs={BB261} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB261 [???..???) -> BB296 (always), preds={BB259,BB260} succs={BB296} ------------ BB262 [6DE..6E4), preds={BB249,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 ------------ BB271 [731..744), preds={BB246} succs={BB272} ------------ BB272 [731..732) -> BB274 (cond), preds={BB271} succs={BB273,BB274} ***** BB272 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 ***** BB272 STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 ***** BB272 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 ------------ BB273 [731..732) -> BB275 (always), preds={BB272} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB272} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB288 (cond), preds={BB276} succs={BB278,BB288} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 ------------ BB278 [75E..774), preds={BB276,BB277} succs={BB279} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 ------------ BB279 [000..000) -> BB281 (cond), preds={BB278} succs={BB280,BB281} ***** BB279 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 ***** BB279 STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 ***** BB279 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 ------------ BB280 [000..000) -> BB282 (always), preds={BB279} succs={BB282} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB281 [000..000), preds={BB279} succs={BB282} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------ BB282 [???..???) -> BB288 (always), preds={BB280,BB281} succs={BB288} ------------ BB283 [774..788), preds={BB289} succs={BB284} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 ------------ BB284 [000..000) -> BB286 (cond), preds={BB283} succs={BB285,BB286} ***** BB284 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 ***** BB284 STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 ***** BB284 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 ------------ BB285 [000..000) -> BB287 (always), preds={BB284} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB284} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------ BB287 [???..???), preds={BB285,BB286} succs={BB288} ------------ BB288 [788..793) -> BB296 (cond), preds={BB277,BB282,BB287} succs={BB289,BB296} ***** BB288 STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB288} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA), preds={BB163(2),BB164(2),BB166,BB170} succs={BB292} ------------ BB292 [7A2..7A3) -> BB294 (cond), preds={BB291} succs={BB293,BB294} ***** BB292 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 ***** BB292 STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 ***** BB292 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 ------------ BB293 [7A2..7A3) -> BB295 (always), preds={BB292} succs={BB295} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB292} succs={BB295} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB295 [???..???), preds={BB293,BB294} succs={BB296} ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB135,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Scanning the 2 candidates *** Does not return call [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() in BB113 is unique, marking it as canonical *** Does not return call [001563] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class in BB81 is unique, marking it as canonical *************** no throws can be tail merged, sorry *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass Moving BB31 after BB16 to enable reversal Reversing a conditional jump around an unconditional jump (BB15 -> BB31, BB16 -> BB48) Setting edge weights for BB15 -> BB48 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [2EE..30D) i BB80 [0207] 1 BB79 1 [000..000)-> BB82 (always) i internal BB81 [0208] 0 1 [000..000) i internal BB82 [0209] 2 BB80,BB81 1 [000..000)-> BB83 (always) i internal BB83 [0211] 1 BB82 1 [000..000) i internal BB84 [0212] 1 BB83 1 [???..???)-> BB124 ( cond ) internal BB85 [0079] 1 BB84 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A) i bwd BB98 [0218] 1 BB97 1 [383..384)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB98 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB98 1 [383..384)-> BB101 (always) i bwd BB101 [0223] 1 BB100 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB101 1 [???..???) internal bwd BB103 [0226] 1 BB102 1 [000..000)-> BB113 ( cond ) i internal bwd BB104 [0227] 1 BB103 1 [000..000) i internal bwd BB105 [0231] 1 BB104 1 [000..000) i internal bwd BB106 [0232] 1 BB105 1 [000..000)-> BB112 (always) i internal bwd BB107 [0233] 0 1 [000..000) i internal bwd BB108 [0236] 1 BB107 1 [000..000)-> BB110 ( cond ) i internal bwd BB109 [0237] 1 BB108 1 [000..000)-> BB111 (always) i internal bwd BB110 [0238] 1 BB108 1 [000..000) i internal bwd BB111 [0239] 2 BB109,BB110 1 [???..???) internal bwd BB112 [0234] 2 BB106,BB111 1 [???..???)-> BB114 (always) internal bwd BB113 [0228] 1 BB103 1 [000..000) i internal bwd BB114 [0229] 2 BB112,BB113 1 [???..???) i internal bwd BB115 [0241] 1 BB114 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB115 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB115 1 [391..392)-> BB118 (always) i bwd BB118 [0246] 1 BB117 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB118 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB84,BB85,BB95,BB123 1 [3C8..3D0)-> BB135 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB135 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB135 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8) i BB128 [0250] 1 BB127 1 [3DC..3DD)-> BB130 ( cond ) i BB129 [0251] 1 BB128 1 [3DC..3DD)-> BB134 (always) i BB130 [0252] 1 BB128 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 3 BB129,BB132,BB133 1 [???..???) internal BB135 [0100] 4 BB124,BB125,BB126,BB134 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [42C..435) i bwd BB145 [0259] 1 BB144 1 [000..000)-> BB147 ( cond ) i internal bwd BB146 [0260] 1 BB145 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB145 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461) i bwd BB153 [0265] 1 BB152 1 [44F..450)-> BB155 ( cond ) i bwd BB154 [0266] 1 BB153 1 [44F..450)-> BB159 (always) i bwd BB155 [0267] 1 BB153 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB154,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB212 ( cond ) i bwd BB170 [0124] 1 BB169 1 [4E4..4E9)-> BB291 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D) i bwd BB184 [0273] 1 BB183 1 [521..522)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB184 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB184 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559) i bwd BB192 [0279] 1 BB191 1 [547..548)-> BB194 ( cond ) i bwd BB193 [0280] 1 BB192 1 [547..548)-> BB198 (always) i bwd BB194 [0281] 1 BB192 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB193,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598) i bwd BB205 [0288] 1 BB204 1 [584..585)-> BB207 ( cond ) i bwd BB206 [0289] 1 BB205 1 [584..585)-> BB211 (always) i bwd BB207 [0290] 1 BB205 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB206,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB212 [0148] 1 BB169 1 [598..5A9) i bwd BB213 [0297] 1 BB212 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 BB213 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB214,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB170 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB135,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB79 and BB80: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB79 -> BB82 -> BB83) Setting edge weights for BB79 -> BB83 to [0 .. 3.402823e+38] Compacting blocks BB81 and BB82: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB81 -> BB83) (converted BB81 to fall-through) fgRemoveBlock BB81, unreachable=true Removing unreachable BB81 removing useless STMT00326 ( INL09 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001563] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowInvalidTypeWithPointersNotSupported(System.Type) [001562] --C-G------ arg0 \--* CALL help ref CORINFO_HELP_TYPEHANDLE_TO_RUNTIMETYPE [001560] #---------- arg0 \--* IND long [001559] H---------- \--* CNS_INT(h) long 0x4000000000421a50 class from BB81 BB81 becomes empty Compacting blocks BB83 and BB84: *************** In fgDebugCheckBBlist Compacting blocks BB97 and BB98: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB97 -> BB100 -> BB101) Setting edge weights for BB97 -> BB101 to [0 .. 3.402823e+38] Removing unconditional jump to next block (BB100 -> BB101) (converted BB100 to fall-through) Compacting blocks BB100 and BB101: Second block has multiple incoming edges Setting edge weights for BB97 -> BB100 to [0 .. 3.402823e+38] *************** In fgDebugCheckBBlist Compacting blocks BB102 and BB103: *************** In fgDebugCheckBBlist Compacting blocks BB104 and BB105: *************** In fgDebugCheckBBlist Compacting blocks BB104 and BB106: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB104 -> BB112 -> BB114) Setting edge weights for BB104 -> BB114 to [0 .. 3.402823e+38] Compacting blocks BB107 and BB108: *************** In fgDebugCheckBBlist fgRemoveBlock BB107, unreachable=true Removing unreachable BB107 removing useless STMT00350 ( INL19 @ 0x022[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001690] -A--------- * ASG long [001689] D------N--- +--* LCL_VAR long V84 tmp44 [001659] ----------- \--* MUL long [001656] ----------- +--* LCL_VAR long V83 tmp43 [001658] ----------- \--* CNS_INT long 4 from BB107 removing useless STMT00347 ( INL21 @ 0x000[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001682] ----------- * JTRUE void [001681] N--------U- \--* GT int [001678] ----------- +--* LCL_VAR long V84 tmp44 [001680] ----------- \--* CNS_INT long 0x400 from BB107 BB107 becomes empty fgRemoveBlock BB109, unreachable=true Removing unreachable BB109 removing useless STMT00349 ( INL21 @ 0x009[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001688] --C-G------ * CALL r2r_ind void [001685] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001686] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001687] ----------- arg2 \--* LCL_VAR long V84 tmp44 from BB109 BB109 becomes empty Compacting blocks BB110 and BB111: *************** In fgDebugCheckBBlist Compacting blocks BB110 and BB112: *************** In fgDebugCheckBBlist fgRemoveBlock BB110, unreachable=true Removing unreachable BB110 removing useless STMT00348 ( INL21 @ 0x012[E-] ... ??? ) <- INL19 @ 0x022[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001684] --C-G------ * CALL r2r_ind void [001654] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001655] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001683] ----------- arg2 \--* LCL_VAR long V84 tmp44 from BB110 BB110 becomes empty Compacting blocks BB114 and BB115: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB114 -> BB117 -> BB118) Setting edge weights for BB114 -> BB118 to [0 .. 3.402823e+38] Removing unconditional jump to next block (BB117 -> BB118) (converted BB117 to fall-through) Compacting blocks BB117 and BB118: Second block has multiple incoming edges Setting edge weights for BB114 -> BB117 to [0 .. 3.402823e+38] *************** In fgDebugCheckBBlist Compacting blocks BB127 and BB128: *************** In fgDebugCheckBBlist Reversing a conditional jump around an unconditional jump (BB127 -> BB130, BB129 -> BB134) Setting edge weights for BB127 -> BB134 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D) i BB83 [0211] 1 BB79 1 [000..000)-> BB124 ( cond ) i internal BB85 [0079] 1 BB83 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB83,BB85,BB95,BB123 1 [3C8..3D0)-> BB135 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB135 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB135 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 3 BB127,BB132,BB133 1 [???..???) internal BB135 [0100] 4 BB124,BB125,BB126,BB134 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [42C..435) i bwd BB145 [0259] 1 BB144 1 [000..000)-> BB147 ( cond ) i internal bwd BB146 [0260] 1 BB145 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB145 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461) i bwd BB153 [0265] 1 BB152 1 [44F..450)-> BB155 ( cond ) i bwd BB154 [0266] 1 BB153 1 [44F..450)-> BB159 (always) i bwd BB155 [0267] 1 BB153 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB154,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB212 ( cond ) i bwd BB170 [0124] 1 BB169 1 [4E4..4E9)-> BB291 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D) i bwd BB184 [0273] 1 BB183 1 [521..522)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB184 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB184 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559) i bwd BB192 [0279] 1 BB191 1 [547..548)-> BB194 ( cond ) i bwd BB193 [0280] 1 BB192 1 [547..548)-> BB198 (always) i bwd BB194 [0281] 1 BB192 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB193,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598) i bwd BB205 [0288] 1 BB204 1 [584..585)-> BB207 ( cond ) i bwd BB206 [0289] 1 BB205 1 [584..585)-> BB211 (always) i bwd BB207 [0290] 1 BB205 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB206,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB212 [0148] 1 BB169 1 [598..5A9) i bwd BB213 [0297] 1 BB212 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 BB213 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB214,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB170 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB135,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB134 and BB135: Second block has multiple incoming edges Setting edge weights for BB124 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB125 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB126 -> BB134 to [0 .. 3.402823e+38] *************** In fgDebugCheckBBlist Compacting blocks BB144 and BB145: *************** In fgDebugCheckBBlist Compacting blocks BB152 and BB153: *************** In fgDebugCheckBBlist Reversing a conditional jump around an unconditional jump (BB152 -> BB155, BB154 -> BB159) Setting edge weights for BB152 -> BB159 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D) i BB83 [0211] 1 BB79 1 [000..000)-> BB124 ( cond ) i internal BB85 [0079] 1 BB83 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB83,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB212 ( cond ) i bwd BB170 [0124] 1 BB169 1 [4E4..4E9)-> BB291 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D) i bwd BB184 [0273] 1 BB183 1 [521..522)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB184 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB184 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559) i bwd BB192 [0279] 1 BB191 1 [547..548)-> BB194 ( cond ) i bwd BB193 [0280] 1 BB192 1 [547..548)-> BB198 (always) i bwd BB194 [0281] 1 BB192 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB193,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598) i bwd BB205 [0288] 1 BB204 1 [584..585)-> BB207 ( cond ) i bwd BB206 [0289] 1 BB205 1 [584..585)-> BB211 (always) i bwd BB207 [0290] 1 BB205 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB206,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB212 [0148] 1 BB169 1 [598..5A9) i bwd BB213 [0297] 1 BB212 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 BB213 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB214,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB170 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Moving BB212 after BB170 to enable reversal New Basic Block BB305 [0361] created. Setting edge weights for BB212 -> BB305 to [0 .. 3.402823e+38] Setting edge weights for BB305 -> BB213 to [0 .. 3.402823e+38] Reversing a conditional jump around an unconditional jump (BB169 -> BB212, BB170 -> BB291) Setting edge weights for BB169 -> BB291 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D) i BB83 [0211] 1 BB79 1 [000..000)-> BB124 ( cond ) i internal BB85 [0079] 1 BB83 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB83,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9) i bwd BB305 [0361] 1 BB212 1 [???..???)-> BB213 (always) internal BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D) i bwd BB184 [0273] 1 BB183 1 [521..522)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB184 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB184 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559) i bwd BB192 [0279] 1 BB191 1 [547..548)-> BB194 ( cond ) i bwd BB193 [0280] 1 BB192 1 [547..548)-> BB198 (always) i bwd BB194 [0281] 1 BB192 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB193,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598) i bwd BB205 [0288] 1 BB204 1 [584..585)-> BB207 ( cond ) i bwd BB206 [0289] 1 BB205 1 [584..585)-> BB211 (always) i bwd BB207 [0290] 1 BB205 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB206,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB305 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 BB213 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB214,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB212 and BB305: *************** In fgDebugCheckBBlist Compacting blocks BB183 and BB184: *************** In fgDebugCheckBBlist Compacting blocks BB191 and BB192: *************** In fgDebugCheckBBlist Reversing a conditional jump around an unconditional jump (BB191 -> BB194, BB193 -> BB198) Setting edge weights for BB191 -> BB198 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D) i BB83 [0211] 1 BB79 1 [000..000)-> BB124 ( cond ) i internal BB85 [0079] 1 BB83 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB83,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598) i bwd BB205 [0288] 1 BB204 1 [584..585)-> BB207 ( cond ) i bwd BB206 [0289] 1 BB205 1 [584..585)-> BB211 (always) i bwd BB207 [0290] 1 BB205 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB206,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 BB213 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB214,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB204 and BB205: *************** In fgDebugCheckBBlist Reversing a conditional jump around an unconditional jump (BB204 -> BB207, BB206 -> BB211) Setting edge weights for BB204 -> BB211 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D) i BB83 [0211] 1 BB79 1 [000..000)-> BB124 ( cond ) i internal BB85 [0079] 1 BB83 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB83,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB215 ( cond ) i bwd BB214 [0298] 1 BB213 1 [598..599)-> BB219 (always) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB214,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Reversing a conditional jump around an unconditional jump (BB213 -> BB215, BB214 -> BB219) Setting edge weights for BB213 -> BB219 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D) i BB83 [0211] 1 BB79 1 [000..000)-> BB124 ( cond ) i internal BB85 [0079] 1 BB83 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB83,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB219 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB219 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599) i bwd BB219 [0303] 3 BB213,BB217,BB218 1 [???..???)-> BB296 (always) internal bwd BB220 [0149] 1 BB163 1 [5A9..5BA) i bwd BB221 [0306] 1 BB220 1 [5A9..5AA)-> BB223 ( cond ) i bwd BB222 [0307] 1 BB221 1 [5A9..5AA)-> BB227 (always) i bwd BB223 [0308] 1 BB221 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB222,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 21 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB219,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Optimizing a jump to an unconditional jump (BB213 -> BB219 -> BB296) Setting edge weights for BB213 -> BB296 to [0 .. 3.402823e+38] Optimizing a jump to an unconditional jump (BB217 -> BB219 -> BB296) Setting edge weights for BB217 -> BB296 to [0 .. 3.402823e+38] Compacting blocks BB218 and BB219: *************** In fgDebugCheckBBlist Compacting blocks BB220 and BB221: *************** In fgDebugCheckBBlist Reversing a conditional jump around an unconditional jump (BB220 -> BB223, BB222 -> BB227) Setting edge weights for BB220 -> BB227 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D) i BB83 [0211] 1 BB79 1 [000..000)-> BB124 ( cond ) i internal BB85 [0079] 1 BB83 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB83,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB227 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB227 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA) i bwd BB227 [0312] 3 BB220,BB225,BB226 1 [???..???)-> BB296 (always) internal bwd BB228 [0150] 1 BB235 1 [5BA..5CE) i bwd bwd-target BB229 [0314] 1 BB228 1 [000..000)-> BB231 ( cond ) i internal bwd BB230 [0315] 1 BB229 1 [000..000)-> BB232 (always) i internal bwd BB231 [0316] 1 BB229 1 [000..000) i internal bwd BB232 [0317] 2 BB230,BB231 1 [???..???) internal bwd BB233 [0151] 3 BB163(2),BB232 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [634..64D) i bwd BB242 [0322] 1 BB241 1 [000..000)-> BB244 ( cond ) i internal bwd BB243 [0323] 1 BB242 1 [000..000)-> BB245 (always) i internal bwd BB244 [0324] 1 BB242 1 [000..000) i internal bwd BB245 [0325] 2 BB243,BB244 1 [???..???)-> BB296 (always) internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB250 ( cond ) i bwd BB249 [0163] 1 BB248 1 [672..67A)-> BB262 (always) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB249,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 23 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB227,BB236,BB237,BB238,BB239,BB240,BB245,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Optimizing a jump to an unconditional jump (BB220 -> BB227 -> BB296) Setting edge weights for BB220 -> BB296 to [0 .. 3.402823e+38] Optimizing a jump to an unconditional jump (BB225 -> BB227 -> BB296) Setting edge weights for BB225 -> BB296 to [0 .. 3.402823e+38] Compacting blocks BB226 and BB227: *************** In fgDebugCheckBBlist Compacting blocks BB228 and BB229: *************** In fgDebugCheckBBlist fgRemoveBlock BB232, unreachable=false Removing empty BB232 Setting edge weights for BB230 -> BB233 to [0 .. 3.402823e+38] Setting edge weights for BB231 -> BB233 to [0 .. 3.402823e+38] Compacting blocks BB241 and BB242: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB243 -> BB245 -> BB296) Setting edge weights for BB243 -> BB296 to [0 .. 3.402823e+38] Compacting blocks BB244 and BB245: *************** In fgDebugCheckBBlist Reversing a conditional jump around an unconditional jump (BB248 -> BB250, BB249 -> BB262) Setting edge weights for BB248 -> BB262 to [0 .. 3.402823e+38] After reversing the jump: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D) i BB83 [0211] 1 BB79 1 [000..000)-> BB124 ( cond ) i internal BB85 [0079] 1 BB83 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB83,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal bwd BB231 [0316] 1 BB228 1 [000..000) i internal bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE) i bwd BB258 [0330] 1 BB257 1 [6D1..6D2)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB258 1 [6D1..6D2)-> BB261 (always) i bwd BB260 [0332] 1 BB258 1 [6D1..6D2) i bwd BB261 [0333] 2 BB259,BB260 1 [???..???)-> BB296 (always) internal bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744) i bwd BB272 [0336] 1 BB271 1 [731..732)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB272 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB272 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB288 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [75E..774) i bwd BB279 [0342] 1 BB278 1 [000..000)-> BB281 ( cond ) i internal bwd BB280 [0343] 1 BB279 1 [000..000)-> BB282 (always) i internal bwd BB281 [0344] 1 BB279 1 [000..000) i internal bwd BB282 [0345] 2 BB280,BB281 1 [???..???)-> BB288 (always) internal bwd BB283 [0185] 1 BB289 1 [774..788) i bwd bwd-target BB284 [0347] 1 BB283 1 [000..000)-> BB286 ( cond ) i internal bwd BB285 [0348] 1 BB284 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB284 1 [000..000) i internal bwd BB287 [0350] 2 BB285,BB286 1 [???..???) internal bwd BB288 [0186] 3 BB277,BB282,BB287 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB288 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA) i bwd BB292 [0353] 1 BB291 1 [7A2..7A3)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB292 1 [7A2..7A3)-> BB295 (always) i bwd BB294 [0355] 1 BB292 1 [7A2..7A3) i bwd BB295 [0356] 2 BB293,BB294 1 [???..???) internal bwd BB296 [0190] 26 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB261,BB270,BB275,BB288,BB290,BB295 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB257 and BB258: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB259 -> BB261 -> BB296) Setting edge weights for BB259 -> BB296 to [0 .. 3.402823e+38] Compacting blocks BB260 and BB261: *************** In fgDebugCheckBBlist Compacting blocks BB271 and BB272: *************** In fgDebugCheckBBlist Compacting blocks BB278 and BB279: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB280 -> BB282 -> BB288) Setting edge weights for BB280 -> BB288 to [0 .. 3.402823e+38] Compacting blocks BB281 and BB282: *************** In fgDebugCheckBBlist Compacting blocks BB283 and BB284: *************** In fgDebugCheckBBlist Compacting blocks BB287 and BB288: Second block has multiple incoming edges Setting edge weights for BB277 -> BB287 to [0 .. 3.402823e+38] Setting edge weights for BB280 -> BB287 to [0 .. 3.402823e+38] Setting edge weights for BB281 -> BB287 to [0 .. 3.402823e+38] *************** In fgDebugCheckBBlist Compacting blocks BB291 and BB292: *************** In fgDebugCheckBBlist fgRemoveBlock BB295, unreachable=false Removing empty BB295 Setting edge weights for BB293 -> BB296 to [0 .. 3.402823e+38] Setting edge weights for BB294 -> BB296 to [0 .. 3.402823e+38] Compacting blocks BB79 and BB83: *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph early pass Trees after Update flow graph early pass ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB79,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal bwd BB231 [0316] 1 BB228 1 [000..000) i internal bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB271 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB283 1 [000..000) i internal bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 ***** BB01 STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct V41 tmp1 [000010] ----------- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct V75 tmp35 [000019] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct V42 tmp2 [001480] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct V42 tmp2 [001481] ----------- \--* LCL_VAR struct V75 tmp35 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct V42 tmp2 [000020] ----------- \--* LCL_VAR struct V41 tmp1 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] n---------- arg0 +--* OBJ struct [000031] ----------- | \--* ADDR byref [000028] -------N--- | \--* LCL_VAR struct V42 tmp2 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct V77 tmp37 [000065] n---------- \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct V77 tmp37 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* NE int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] n---------- arg0 +--* OBJ struct [001160] ----------- | \--* ADDR byref [001157] -------N--- | \--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct V48 tmp8 [000164] ----------- \--* CNS_INT int 0 ***** BB79 STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] ----------- * NOP void ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct V48 tmp8 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct V48 tmp8 [001556] ----------- \--* CNS_INT int 4 ***** BB79 STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct V25 loc21 [000169] ----------- \--* LCL_VAR struct V48 tmp8 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct V19 loc15 [000172] ----------- \--* LCL_VAR struct V25 loc21 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB123 (always), preds={BB92,BB93} succs={BB123} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct V19 loc15 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* FIELD int :_length [001576] ----------- | \--* ADDR byref [001577] -------N--- | \--* LCL_VAR struct V19 loc15 [001065] ----------- \--* CNS_INT int 2 ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct V78 tmp38 [001581] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct V78 tmp38 [001613] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct V78 tmp38 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct V78 tmp38 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct V68 tmp28 [001586] ----------- \--* LCL_VAR struct V78 tmp38 ***** BB102 STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct V79 tmp39 [001081] n---------- \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct V68 tmp28 ***** BB102 STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001647] ----------- \--* FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct V79 tmp39 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* FIELD byref :_reference [001632] ----------- \--* ADDR byref [001631] -------N--- \--* LCL_VAR struct V79 tmp39 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* FIELD byref :_reference [001634] ----------- \--* ADDR byref [001635] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct V19 loc15 ***** BB104 STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] ----------- * NOP void ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB113 [000..000), preds={BB102} succs={BB114} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() ------------ BB114 [391..392) -> BB117 (cond), preds={BB104,BB113} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct V85 tmp45 [001693] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct V85 tmp45 [001725] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct V85 tmp45 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct V85 tmp45 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct V19 loc15 [001698] ----------- \--* LCL_VAR struct V85 tmp45 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* FIELD int :_length [001023] ----------- | | \--* ADDR byref [001022] -------N--- | | \--* LCL_VAR struct V19 loc15 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* FIELD byref :_reference [001027] ----------- | | \--* ADDR byref [001026] -------N--- | | \--* LCL_VAR struct V19 loc15 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB94,BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB95,BB123} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* EQ int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct V90 tmp50 [000193] n---------- \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct V90 tmp50 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB144 STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* FIELD int :_length [000884] ----------- | | \--* ADDR byref [000883] -------N--- | | \--* LCL_VAR struct V19 loc15 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* FIELD byref :_reference [000888] ----------- | | \--* ADDR byref [000887] -------N--- | | \--* LCL_VAR struct V19 loc15 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* EQ int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* NE int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 ***** BB183 STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* FIELD int :_length [000691] ----------- | | \--* ADDR byref [000690] -------N--- | | \--* LCL_VAR struct V19 loc15 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* FIELD byref :_reference [000695] ----------- | | \--* ADDR byref [000694] -------N--- | | \--* LCL_VAR struct V19 loc15 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* EQ int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* EQ int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* EQ int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* EQ int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 ***** BB228 STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 ***** BB241 STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* EQ int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 ***** BB257 STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 ***** BB271 STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 ***** BB278 STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 ***** BB291 STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Morph - Promote Structs lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 byref ptr ; V01 arg1 byref ptr ; V02 arg2 struct multireg-arg ld-addr-op ; V03 arg3 ref class-hnd ptr ; V04 loc0 int ; V05 loc1 int ; V06 loc2 int ; V07 loc3 int ; V08 loc4 int ; V09 loc5 bool ; V10 loc6 int ; V11 loc7 int ; V12 loc8 bool ; V13 loc9 int ; V14 loc10 int ; V15 loc11 int ; V16 loc12 int ; V17 loc13 long ptr ; V18 loc14 ushort ; V19 loc15 struct ld-addr-op ; V20 loc16 int ; V21 loc17 bool ; V22 loc18 long ptr ; V23 loc19 byref pinned ptr ; V24 loc20 int ; V25 loc21 struct ; V26 loc22 ref class-hnd ptr ; V27 loc23 int ; V28 loc24 int ; V29 loc25 int ; V30 loc26 int ; V31 loc27 int ; V32 loc28 int ; V33 loc29 ref class-hnd exact ptr ; V34 loc30 long ptr ; V35 loc31 byref pinned ptr ; V36 loc32 long ptr ; V37 loc33 bool ; V38 loc34 int ; V39 loc35 int ; V40 OutArgs lclBlk "OutgoingArgSpace" ; V41 tmp1 struct ; V42 tmp2 struct ; V43 tmp3 int ; V44 tmp4 int ; V45 tmp5 int ; V46 tmp6 int ; V47 tmp7 blk ld-addr-op unsafe-buffer "stackallocLocal" ; V48 tmp8 struct ld-addr-op "NewObj constructor temp" ; V49 tmp9 int "impSpillLclRefs" ; V50 tmp10 int "dup spill" ; V51 tmp11 int "impSpillLclRefs" ; V52 tmp12 int "impSpillLclRefs" ; V53 tmp13 int "impSpillLclRefs" ; V54 tmp14 int "dup spill" ; V55 tmp15 int ; V56 tmp16 long "impSpillLclRefs" ; V57 tmp17 int ; V58 tmp18 int ; V59 tmp19 int "impSpillLclRefs" ; V60 tmp20 byref ; V61 tmp21 long "impSpillLclRefs" ; V62 tmp22 byref ; V63 tmp23 int ; V64 tmp24 int ; V65 tmp25 int ; V66 tmp26 int ; V67 tmp27 int ; V68 tmp28 struct "struct address for call/obj" ; V69 tmp29 byref "dup spill" ; V70 tmp30 int ; V71 tmp31 int "impSpillLclRefs" ; V72 tmp32 int "dup spill" ; V73 tmp33 int "dup spill" ; V74 tmp34 int "impSpillLclRefs" ; V75 tmp35 struct ; V76 tmp36 byref "Span.get_Item ptrToSpan" ; V77 tmp37 struct ld-addr-op "Inlining Arg" ; V78 tmp38 struct ld-addr-op "NewObj constructor temp" ; V79 tmp39 struct ld-addr-op "Inlining Arg" ; V80 tmp40 int "impAppendStmt" ; V81 tmp41 byref "Inlining Arg" ; V82 tmp42 byref "Inlining Arg" ; V83 tmp43 long "Inlining Arg" ; V84 tmp44 long "Inlining Arg" ; V85 tmp45 struct ld-addr-op "NewObj constructor temp" ; V86 tmp46 ref class-hnd "Inlining Arg" ; V87 tmp47 int "Inline stloc first use temp" ; V88 tmp48 byref "Span.get_Item ptrToSpan" ; V89 tmp49 byref "Inlining Arg" ; V90 tmp50 struct ld-addr-op "Inlining Arg" ; V91 tmp51 int "Inline stloc first use temp" ; V92 tmp52 ushort "Inlining Arg" ; V93 tmp53 byref "Span.get_Item ptrToSpan" ; V94 tmp54 byref "Inlining Arg" ; V95 tmp55 ref class-hnd "Inlining Arg" ; V96 tmp56 int "Inline stloc first use temp" ; V97 tmp57 byref "Span.get_Item ptrToSpan" ; V98 tmp58 byref "Inlining Arg" ; V99 tmp59 int "Inline stloc first use temp" ; V100 tmp60 byref "Span.get_Item ptrToSpan" ; V101 tmp61 byref "Inlining Arg" ; V102 tmp62 ref class-hnd "Inlining Arg" ; V103 tmp63 int "Inline stloc first use temp" ; V104 tmp64 byref "Span.get_Item ptrToSpan" ; V105 tmp65 byref "Inlining Arg" ; V106 tmp66 ref class-hnd "Inlining Arg" ; V107 tmp67 int "Inline stloc first use temp" ; V108 tmp68 byref "Span.get_Item ptrToSpan" ; V109 tmp69 byref "Inlining Arg" ; V110 tmp70 ref class-hnd "Inlining Arg" ; V111 tmp71 int "Inline stloc first use temp" ; V112 tmp72 byref "Span.get_Item ptrToSpan" ; V113 tmp73 byref "Inlining Arg" ; V114 tmp74 ref class-hnd "Inlining Arg" ; V115 tmp75 int "Inline stloc first use temp" ; V116 tmp76 byref "Span.get_Item ptrToSpan" ; V117 tmp77 byref "Inlining Arg" ; V118 tmp78 int "Inline stloc first use temp" ; V119 tmp79 ushort "Inlining Arg" ; V120 tmp80 byref "Span.get_Item ptrToSpan" ; V121 tmp81 byref "Inlining Arg" ; V122 tmp82 int "Inline stloc first use temp" ; V123 tmp83 ushort "Inlining Arg" ; V124 tmp84 byref "Span.get_Item ptrToSpan" ; V125 tmp85 byref "Inlining Arg" ; V126 tmp86 int "Inline stloc first use temp" ; V127 tmp87 byref "Span.get_Item ptrToSpan" ; V128 tmp88 byref "Inlining Arg" ; V129 tmp89 int "Inline stloc first use temp" ; V130 tmp90 byref "Span.get_Item ptrToSpan" ; V131 tmp91 byref "Inlining Arg" ; V132 tmp92 int "Inline stloc first use temp" ; V133 tmp93 ushort "Inlining Arg" ; V134 tmp94 byref "Span.get_Item ptrToSpan" ; V135 tmp95 byref "Inlining Arg" ; V136 tmp96 int "Inline stloc first use temp" ; V137 tmp97 ushort "Inlining Arg" ; V138 tmp98 byref "Span.get_Item ptrToSpan" ; V139 tmp99 byref "Inlining Arg" ; V140 tmp100 int "Inline stloc first use temp" ; V141 tmp101 byref "Span.get_Item ptrToSpan" ; V142 tmp102 byref "Inlining Arg" struct promotion of V02 is disabled because lvIsParam and compGSReorderStackLayout Promoting struct local V19 (System.Span`1[int]): lvaGrabTemp returning 143 (V143 tmp103) (a long lifetime temp) called for field V19._reference (fldOffset=0x0). lvaGrabTemp returning 144 (V144 tmp104) (a long lifetime temp) called for field V19._length (fldOffset=0x8). Promoting struct local V25 (System.Span`1[int]): lvaGrabTemp returning 145 (V145 tmp105) (a long lifetime temp) called for field V25._reference (fldOffset=0x0). lvaGrabTemp returning 146 (V146 tmp106) (a long lifetime temp) called for field V25._length (fldOffset=0x8). Promoting struct local V41 (System.ReadOnlySpan`1[ushort]): lvaGrabTemp returning 147 (V147 tmp107) (a long lifetime temp) called for field V41._reference (fldOffset=0x0). lvaGrabTemp returning 148 (V148 tmp108) (a long lifetime temp) called for field V41._length (fldOffset=0x8). Promoting struct local V42 (System.ReadOnlySpan`1[ushort]): lvaGrabTemp returning 149 (V149 tmp109) (a long lifetime temp) called for field V42._reference (fldOffset=0x0). lvaGrabTemp returning 150 (V150 tmp110) (a long lifetime temp) called for field V42._length (fldOffset=0x8). Promoting struct local V48 (System.Span`1[int]): lvaGrabTemp returning 151 (V151 tmp111) (a long lifetime temp) called for field V48._reference (fldOffset=0x0). lvaGrabTemp returning 152 (V152 tmp112) (a long lifetime temp) called for field V48._length (fldOffset=0x8). Promoting struct local V68 (System.Span`1[int]): lvaGrabTemp returning 153 (V153 tmp113) (a long lifetime temp) called for field V68._reference (fldOffset=0x0). lvaGrabTemp returning 154 (V154 tmp114) (a long lifetime temp) called for field V68._length (fldOffset=0x8). Promoting struct local V75 (System.ReadOnlySpan`1[ushort]): lvaGrabTemp returning 155 (V155 tmp115) (a long lifetime temp) called for field V75._reference (fldOffset=0x0). lvaGrabTemp returning 156 (V156 tmp116) (a long lifetime temp) called for field V75._length (fldOffset=0x8). Promoting struct local V77 (System.ReadOnlySpan`1[ushort]): lvaGrabTemp returning 157 (V157 tmp117) (a long lifetime temp) called for field V77._reference (fldOffset=0x0). lvaGrabTemp returning 158 (V158 tmp118) (a long lifetime temp) called for field V77._length (fldOffset=0x8). Promoting struct local V78 (System.Span`1[int]): lvaGrabTemp returning 159 (V159 tmp119) (a long lifetime temp) called for field V78._reference (fldOffset=0x0). lvaGrabTemp returning 160 (V160 tmp120) (a long lifetime temp) called for field V78._length (fldOffset=0x8). Promoting struct local V79 (System.Span`1[int]): lvaGrabTemp returning 161 (V161 tmp121) (a long lifetime temp) called for field V79._reference (fldOffset=0x0). lvaGrabTemp returning 162 (V162 tmp122) (a long lifetime temp) called for field V79._length (fldOffset=0x8). Promoting struct local V85 (System.Span`1[int]): lvaGrabTemp returning 163 (V163 tmp123) (a long lifetime temp) called for field V85._reference (fldOffset=0x0). lvaGrabTemp returning 164 (V164 tmp124) (a long lifetime temp) called for field V85._length (fldOffset=0x8). Promoting struct local V90 (System.ReadOnlySpan`1[ushort]): lvaGrabTemp returning 165 (V165 tmp125) (a long lifetime temp) called for field V90._reference (fldOffset=0x0). lvaGrabTemp returning 166 (V166 tmp126) (a long lifetime temp) called for field V90._length (fldOffset=0x8). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 byref ptr ; V01 arg1 byref ptr ; V02 arg2 struct multireg-arg ld-addr-op ; V03 arg3 ref class-hnd ptr ; V04 loc0 int ; V05 loc1 int ; V06 loc2 int ; V07 loc3 int ; V08 loc4 int ; V09 loc5 bool ; V10 loc6 int ; V11 loc7 int ; V12 loc8 bool ; V13 loc9 int ; V14 loc10 int ; V15 loc11 int ; V16 loc12 int ; V17 loc13 long ptr ; V18 loc14 ushort ; V19 loc15 struct ld-addr-op ; V20 loc16 int ; V21 loc17 bool ; V22 loc18 long ptr ; V23 loc19 byref pinned ptr ; V24 loc20 int ; V25 loc21 struct ; V26 loc22 ref class-hnd ptr ; V27 loc23 int ; V28 loc24 int ; V29 loc25 int ; V30 loc26 int ; V31 loc27 int ; V32 loc28 int ; V33 loc29 ref class-hnd exact ptr ; V34 loc30 long ptr ; V35 loc31 byref pinned ptr ; V36 loc32 long ptr ; V37 loc33 bool ; V38 loc34 int ; V39 loc35 int ; V40 OutArgs lclBlk "OutgoingArgSpace" ; V41 tmp1 struct ; V42 tmp2 struct ; V43 tmp3 int ; V44 tmp4 int ; V45 tmp5 int ; V46 tmp6 int ; V47 tmp7 blk ld-addr-op unsafe-buffer "stackallocLocal" ; V48 tmp8 struct ld-addr-op "NewObj constructor temp" ; V49 tmp9 int "impSpillLclRefs" ; V50 tmp10 int "dup spill" ; V51 tmp11 int "impSpillLclRefs" ; V52 tmp12 int "impSpillLclRefs" ; V53 tmp13 int "impSpillLclRefs" ; V54 tmp14 int "dup spill" ; V55 tmp15 int ; V56 tmp16 long "impSpillLclRefs" ; V57 tmp17 int ; V58 tmp18 int ; V59 tmp19 int "impSpillLclRefs" ; V60 tmp20 byref ; V61 tmp21 long "impSpillLclRefs" ; V62 tmp22 byref ; V63 tmp23 int ; V64 tmp24 int ; V65 tmp25 int ; V66 tmp26 int ; V67 tmp27 int ; V68 tmp28 struct "struct address for call/obj" ; V69 tmp29 byref "dup spill" ; V70 tmp30 int ; V71 tmp31 int "impSpillLclRefs" ; V72 tmp32 int "dup spill" ; V73 tmp33 int "dup spill" ; V74 tmp34 int "impSpillLclRefs" ; V75 tmp35 struct ; V76 tmp36 byref "Span.get_Item ptrToSpan" ; V77 tmp37 struct ld-addr-op "Inlining Arg" ; V78 tmp38 struct ld-addr-op "NewObj constructor temp" ; V79 tmp39 struct ld-addr-op "Inlining Arg" ; V80 tmp40 int "impAppendStmt" ; V81 tmp41 byref "Inlining Arg" ; V82 tmp42 byref "Inlining Arg" ; V83 tmp43 long "Inlining Arg" ; V84 tmp44 long "Inlining Arg" ; V85 tmp45 struct ld-addr-op "NewObj constructor temp" ; V86 tmp46 ref class-hnd "Inlining Arg" ; V87 tmp47 int "Inline stloc first use temp" ; V88 tmp48 byref "Span.get_Item ptrToSpan" ; V89 tmp49 byref "Inlining Arg" ; V90 tmp50 struct ld-addr-op "Inlining Arg" ; V91 tmp51 int "Inline stloc first use temp" ; V92 tmp52 ushort "Inlining Arg" ; V93 tmp53 byref "Span.get_Item ptrToSpan" ; V94 tmp54 byref "Inlining Arg" ; V95 tmp55 ref class-hnd "Inlining Arg" ; V96 tmp56 int "Inline stloc first use temp" ; V97 tmp57 byref "Span.get_Item ptrToSpan" ; V98 tmp58 byref "Inlining Arg" ; V99 tmp59 int "Inline stloc first use temp" ; V100 tmp60 byref "Span.get_Item ptrToSpan" ; V101 tmp61 byref "Inlining Arg" ; V102 tmp62 ref class-hnd "Inlining Arg" ; V103 tmp63 int "Inline stloc first use temp" ; V104 tmp64 byref "Span.get_Item ptrToSpan" ; V105 tmp65 byref "Inlining Arg" ; V106 tmp66 ref class-hnd "Inlining Arg" ; V107 tmp67 int "Inline stloc first use temp" ; V108 tmp68 byref "Span.get_Item ptrToSpan" ; V109 tmp69 byref "Inlining Arg" ; V110 tmp70 ref class-hnd "Inlining Arg" ; V111 tmp71 int "Inline stloc first use temp" ; V112 tmp72 byref "Span.get_Item ptrToSpan" ; V113 tmp73 byref "Inlining Arg" ; V114 tmp74 ref class-hnd "Inlining Arg" ; V115 tmp75 int "Inline stloc first use temp" ; V116 tmp76 byref "Span.get_Item ptrToSpan" ; V117 tmp77 byref "Inlining Arg" ; V118 tmp78 int "Inline stloc first use temp" ; V119 tmp79 ushort "Inlining Arg" ; V120 tmp80 byref "Span.get_Item ptrToSpan" ; V121 tmp81 byref "Inlining Arg" ; V122 tmp82 int "Inline stloc first use temp" ; V123 tmp83 ushort "Inlining Arg" ; V124 tmp84 byref "Span.get_Item ptrToSpan" ; V125 tmp85 byref "Inlining Arg" ; V126 tmp86 int "Inline stloc first use temp" ; V127 tmp87 byref "Span.get_Item ptrToSpan" ; V128 tmp88 byref "Inlining Arg" ; V129 tmp89 int "Inline stloc first use temp" ; V130 tmp90 byref "Span.get_Item ptrToSpan" ; V131 tmp91 byref "Inlining Arg" ; V132 tmp92 int "Inline stloc first use temp" ; V133 tmp93 ushort "Inlining Arg" ; V134 tmp94 byref "Span.get_Item ptrToSpan" ; V135 tmp95 byref "Inlining Arg" ; V136 tmp96 int "Inline stloc first use temp" ; V137 tmp97 ushort "Inlining Arg" ; V138 tmp98 byref "Span.get_Item ptrToSpan" ; V139 tmp99 byref "Inlining Arg" ; V140 tmp100 int "Inline stloc first use temp" ; V141 tmp101 byref "Span.get_Item ptrToSpan" ; V142 tmp102 byref "Inlining Arg" ; V143 tmp103 byref V19._reference(offs=0x00) P-INDEP "field V19._reference (fldOffset=0x0)" ; V144 tmp104 int V19._length(offs=0x08) P-INDEP "field V19._length (fldOffset=0x8)" ; V145 tmp105 byref V25._reference(offs=0x00) P-INDEP "field V25._reference (fldOffset=0x0)" ; V146 tmp106 int V25._length(offs=0x08) P-INDEP "field V25._length (fldOffset=0x8)" ; V147 tmp107 byref V41._reference(offs=0x00) P-INDEP "field V41._reference (fldOffset=0x0)" ; V148 tmp108 int V41._length(offs=0x08) P-INDEP "field V41._length (fldOffset=0x8)" ; V149 tmp109 byref V42._reference(offs=0x00) P-INDEP "field V42._reference (fldOffset=0x0)" ; V150 tmp110 int V42._length(offs=0x08) P-INDEP "field V42._length (fldOffset=0x8)" ; V151 tmp111 byref V48._reference(offs=0x00) P-INDEP "field V48._reference (fldOffset=0x0)" ; V152 tmp112 int V48._length(offs=0x08) P-INDEP "field V48._length (fldOffset=0x8)" ; V153 tmp113 byref V68._reference(offs=0x00) P-INDEP "field V68._reference (fldOffset=0x0)" ; V154 tmp114 int V68._length(offs=0x08) P-INDEP "field V68._length (fldOffset=0x8)" ; V155 tmp115 byref V75._reference(offs=0x00) P-INDEP "field V75._reference (fldOffset=0x0)" ; V156 tmp116 int V75._length(offs=0x08) P-INDEP "field V75._length (fldOffset=0x8)" ; V157 tmp117 byref V77._reference(offs=0x00) P-INDEP "field V77._reference (fldOffset=0x0)" ; V158 tmp118 int V77._length(offs=0x08) P-INDEP "field V77._length (fldOffset=0x8)" ; V159 tmp119 byref V78._reference(offs=0x00) P-INDEP "field V78._reference (fldOffset=0x0)" ; V160 tmp120 int V78._length(offs=0x08) P-INDEP "field V78._length (fldOffset=0x8)" ; V161 tmp121 byref V79._reference(offs=0x00) P-INDEP "field V79._reference (fldOffset=0x0)" ; V162 tmp122 int V79._length(offs=0x08) P-INDEP "field V79._length (fldOffset=0x8)" ; V163 tmp123 byref V85._reference(offs=0x00) P-INDEP "field V85._reference (fldOffset=0x0)" ; V164 tmp124 int V85._length(offs=0x08) P-INDEP "field V85._length (fldOffset=0x8)" ; V165 tmp125 byref V90._reference(offs=0x00) P-INDEP "field V90._reference (fldOffset=0x0)" ; V166 tmp126 int V90._length(offs=0x08) P-INDEP "field V90._length (fldOffset=0x8)" *************** Finishing PHASE Morph - Promote Structs Trees after Morph - Promote Structs ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB79,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal bwd BB231 [0316] 1 BB228 1 [000..000) i internal bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB271 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB283 1 [000..000) i internal bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 ***** BB01 STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct(P) V41 tmp1 +--* byref V41.:_reference (offs=0x00) -> V147 tmp107 +--* int V41.:_length (offs=0x08) -> V148 tmp108 [000010] ----------- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct(P) V75 tmp35 +--* byref V75.:_reference (offs=0x00) -> V155 tmp115 +--* int V75.:_length (offs=0x08) -> V156 tmp116 [000019] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001480] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001481] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000020] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] n---------- arg0 +--* OBJ struct [000031] ----------- | \--* ADDR byref [000028] -------N--- | \--* LCL_VAR struct(P) V42 tmp2 | \--* byref V42.:_reference (offs=0x00) -> V149 tmp109 | \--* int V42.:_length (offs=0x08) -> V150 tmp110 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct(P) V77 tmp37 +--* byref V77.:_reference (offs=0x00) -> V157 tmp117 +--* int V77.:_length (offs=0x08) -> V158 tmp118 [000065] n---------- \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct(P) V77 tmp37 \--* byref V77.:_reference (offs=0x00) -> V157 tmp117 \--* int V77.:_length (offs=0x08) -> V158 tmp118 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* NE int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] n---------- arg0 +--* OBJ struct [001160] ----------- | \--* ADDR byref [001157] -------N--- | \--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct(P) V48 tmp8 +--* byref V48.:_reference (offs=0x00) -> V151 tmp111 +--* int V48.:_length (offs=0x08) -> V152 tmp112 [000164] ----------- \--* CNS_INT int 0 ***** BB79 STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] ----------- * NOP void ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct(P) V48 tmp8 | \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 | \--* int V48.:_length (offs=0x08) -> V152 tmp112 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct(P) V48 tmp8 | \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 | \--* int V48.:_length (offs=0x08) -> V152 tmp112 [001556] ----------- \--* CNS_INT int 4 ***** BB79 STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct(P) V25 loc21 +--* byref V25.:_reference (offs=0x00) -> V145 tmp105 +--* int V25.:_length (offs=0x08) -> V146 tmp106 [000169] ----------- \--* LCL_VAR struct(P) V48 tmp8 \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 \--* int V48.:_length (offs=0x08) -> V152 tmp112 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [000172] ----------- \--* LCL_VAR struct(P) V25 loc21 \--* byref V25.:_reference (offs=0x00) -> V145 tmp105 \--* int V25.:_length (offs=0x08) -> V146 tmp106 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB123 (always), preds={BB92,BB93} succs={BB123} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct(P) V19 loc15 \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 \--* int V19.:_length (offs=0x08) -> V144 tmp104 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* FIELD int :_length [001576] ----------- | \--* ADDR byref [001577] -------N--- | \--* LCL_VAR struct(P) V19 loc15 | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [001065] ----------- \--* CNS_INT int 2 ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001581] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001613] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct(P) V78 tmp38 | \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 | \--* int V78.:_length (offs=0x08) -> V160 tmp120 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct(P) V78 tmp38 | \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 | \--* int V78.:_length (offs=0x08) -> V160 tmp120 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct(P) V68 tmp28 +--* byref V68.:_reference (offs=0x00) -> V153 tmp113 +--* int V68.:_length (offs=0x08) -> V154 tmp114 [001586] ----------- \--* LCL_VAR struct(P) V78 tmp38 \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 \--* int V78.:_length (offs=0x08) -> V160 tmp120 ***** BB102 STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct(P) V79 tmp39 +--* byref V79.:_reference (offs=0x00) -> V161 tmp121 +--* int V79.:_length (offs=0x08) -> V162 tmp122 [001081] n---------- \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct(P) V68 tmp28 \--* byref V68.:_reference (offs=0x00) -> V153 tmp113 \--* int V68.:_length (offs=0x08) -> V154 tmp114 ***** BB102 STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct(P) V19 loc15 \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 \--* int V19.:_length (offs=0x08) -> V144 tmp104 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001647] ----------- \--* FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct(P) V79 tmp39 \--* byref V79.:_reference (offs=0x00) -> V161 tmp121 \--* int V79.:_length (offs=0x08) -> V162 tmp122 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* FIELD byref :_reference [001632] ----------- \--* ADDR byref [001631] -------N--- \--* LCL_VAR struct(P) V79 tmp39 \--* byref V79.:_reference (offs=0x00) -> V161 tmp121 \--* int V79.:_length (offs=0x08) -> V162 tmp122 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* FIELD byref :_reference [001634] ----------- \--* ADDR byref [001635] -------N--- \--* LCL_VAR struct(P) V19 loc15 \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 \--* int V19.:_length (offs=0x08) -> V144 tmp104 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct(P) V19 loc15 \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 \--* int V19.:_length (offs=0x08) -> V144 tmp104 ***** BB104 STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] ----------- * NOP void ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB113 [000..000), preds={BB102} succs={BB114} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() ------------ BB114 [391..392) -> BB117 (cond), preds={BB104,BB113} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001693] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001725] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct(P) V85 tmp45 | \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 | \--* int V85.:_length (offs=0x08) -> V164 tmp124 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct(P) V85 tmp45 | \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 | \--* int V85.:_length (offs=0x08) -> V164 tmp124 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [001698] ----------- \--* LCL_VAR struct(P) V85 tmp45 \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 \--* int V85.:_length (offs=0x08) -> V164 tmp124 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* FIELD int :_length [001023] ----------- | | \--* ADDR byref [001022] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* FIELD byref :_reference [001027] ----------- | | \--* ADDR byref [001026] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB94,BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB95,BB123} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* EQ int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct(P) V90 tmp50 +--* byref V90.:_reference (offs=0x00) -> V165 tmp125 +--* int V90.:_length (offs=0x08) -> V166 tmp126 [000193] n---------- \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct(P) V90 tmp50 \--* byref V90.:_reference (offs=0x00) -> V165 tmp125 \--* int V90.:_length (offs=0x08) -> V166 tmp126 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB144 STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* FIELD int :_length [000884] ----------- | | \--* ADDR byref [000883] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* FIELD byref :_reference [000888] ----------- | | \--* ADDR byref [000887] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* EQ int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* NE int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 ***** BB183 STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* FIELD int :_length [000691] ----------- | | \--* ADDR byref [000690] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* FIELD byref :_reference [000695] ----------- | | \--* ADDR byref [000694] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* EQ int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* EQ int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* EQ int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* EQ int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 ***** BB228 STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 ***** BB241 STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* EQ int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 ***** BB257 STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 ***** BB271 STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 ***** BB278 STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 ***** BB291 STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Morph - Structs/AddrExp LocalAddressVisitor visiting statement: STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 LocalAddressVisitor visiting statement: STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 LocalAddressVisitor visiting statement: STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 LocalAddressVisitor visiting statement: STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct(P) V41 tmp1 +--* byref V41.:_reference (offs=0x00) -> V147 tmp107 +--* int V41.:_length (offs=0x08) -> V148 tmp108 [000010] ----------- \--* LCL_VAR struct V02 arg2 LocalAddressVisitor visiting statement: STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct(P) V75 tmp35 +--* byref V75.:_reference (offs=0x00) -> V155 tmp115 +--* int V75.:_length (offs=0x08) -> V156 tmp116 [000019] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 LocalAddressVisitor visiting statement: STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001480] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 LocalAddressVisitor visiting statement: STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001481] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 LocalAddressVisitor visiting statement: STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000020] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 LocalAddressVisitor visiting statement: STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] n---------- arg0 +--* OBJ struct [000031] ----------- | \--* ADDR byref [000028] -------N--- | \--* LCL_VAR struct(P) V42 tmp2 | \--* byref V42.:_reference (offs=0x00) -> V149 tmp109 | \--* int V42.:_length (offs=0x08) -> V150 tmp110 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 LocalAddressVisitor modified statement: STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] ----------- arg0 +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 LocalAddressVisitor visiting statement: STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 LocalAddressVisitor visiting statement: STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF LocalAddressVisitor visiting statement: STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 LocalAddressVisitor visiting statement: STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 LocalAddressVisitor visiting statement: STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct(P) V77 tmp37 +--* byref V77.:_reference (offs=0x00) -> V157 tmp117 +--* int V77.:_length (offs=0x08) -> V158 tmp118 [000065] n---------- \--* OBJ struct [000064] ----------- \--* ADDR byref [000062] -------N--- \--* LCL_VAR struct V02 arg2 LocalAddressVisitor modified statement: STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct(P) V77 tmp37 +--* byref V77.:_reference (offs=0x00) -> V157 tmp117 +--* int V77.:_length (offs=0x08) -> V158 tmp118 [000065] ----------- \--* LCL_VAR struct V02 arg2 LocalAddressVisitor visiting statement: STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* FIELD byref :_reference [001511] ----------- \--* ADDR byref [001510] -------N--- \--* LCL_VAR struct(P) V77 tmp37 \--* byref V77.:_reference (offs=0x00) -> V157 tmp117 \--* int V77.:_length (offs=0x08) -> V158 tmp118 Replacing the field in promoted struct with local var V157 LocalAddressVisitor modified statement: STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* LCL_VAR byref V157 tmp117 LocalAddressVisitor visiting statement: STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 LocalAddressVisitor visiting statement: STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 LocalAddressVisitor visiting statement: STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 LocalAddressVisitor visiting statement: STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 LocalAddressVisitor visiting statement: STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 LocalAddressVisitor visiting statement: STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 LocalAddressVisitor visiting statement: STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 LocalAddressVisitor visiting statement: STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* NE int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 LocalAddressVisitor visiting statement: STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 LocalAddressVisitor visiting statement: STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF LocalAddressVisitor visiting statement: STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 LocalAddressVisitor visiting statement: STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 LocalAddressVisitor visiting statement: STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 LocalAddressVisitor visiting statement: STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 LocalAddressVisitor visiting statement: STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 LocalAddressVisitor visiting statement: STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* FIELD int :_length [001516] ----------- \--* ADDR byref [001517] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 LocalAddressVisitor visiting statement: STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* FIELD int :_length [001520] ----------- \--* ADDR byref [001521] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* FIELD int :_length [001524] ----------- \--* ADDR byref [001525] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* FIELD int :_length [001528] ----------- \--* ADDR byref [001529] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 LocalAddressVisitor visiting statement: STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 LocalAddressVisitor visiting statement: STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 LocalAddressVisitor visiting statement: STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* FIELD int :_length [001532] ----------- \--* ADDR byref [001533] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* FIELD int :_length [001536] ----------- \--* ADDR byref [001537] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 LocalAddressVisitor visiting statement: STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 LocalAddressVisitor visiting statement: STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 LocalAddressVisitor visiting statement: STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 LocalAddressVisitor visiting statement: STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 LocalAddressVisitor visiting statement: STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 LocalAddressVisitor visiting statement: STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 LocalAddressVisitor visiting statement: STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 LocalAddressVisitor visiting statement: STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 LocalAddressVisitor visiting statement: STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 LocalAddressVisitor visiting statement: STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] n---------- arg0 +--* OBJ struct [001160] ----------- | \--* ADDR byref [001157] -------N--- | \--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 LocalAddressVisitor modified statement: STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] ----------- arg0 +--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 LocalAddressVisitor visiting statement: STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 LocalAddressVisitor visiting statement: STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 LocalAddressVisitor visiting statement: STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 LocalAddressVisitor visiting statement: STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 LocalAddressVisitor visiting statement: STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 LocalAddressVisitor visiting statement: STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 LocalAddressVisitor visiting statement: STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 LocalAddressVisitor visiting statement: STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 LocalAddressVisitor visiting statement: STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 LocalAddressVisitor visiting statement: STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct(P) V48 tmp8 +--* byref V48.:_reference (offs=0x00) -> V151 tmp111 +--* int V48.:_length (offs=0x08) -> V152 tmp112 [000164] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] ----------- * NOP void LocalAddressVisitor visiting statement: STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] -------N--- +--* FIELD byref :_reference [001548] ----------- | \--* ADDR byref [001549] -------N--- | \--* LCL_VAR struct(P) V48 tmp8 | \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 | \--* int V48.:_length (offs=0x08) -> V152 tmp112 [001550] ----------- \--* ADDR long [001551] -------N--- \--* LCL_VAR blk V47 tmp7 Replacing the field in promoted struct with local var V151 Local V47 should not be enregistered because: it is address exposed LocalAddressVisitor modified statement: STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] D------N--- +--* LCL_VAR byref V151 tmp111 [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 LocalAddressVisitor visiting statement: STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] -------N--- +--* FIELD int :_length [001554] ----------- | \--* ADDR byref [001555] -------N--- | \--* LCL_VAR struct(P) V48 tmp8 | \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 | \--* int V48.:_length (offs=0x08) -> V152 tmp112 [001556] ----------- \--* CNS_INT int 4 Replacing the field in promoted struct with local var V152 LocalAddressVisitor modified statement: STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] D------N--- +--* LCL_VAR int V152 tmp112 [001556] ----------- \--* CNS_INT int 4 LocalAddressVisitor visiting statement: STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct(P) V25 loc21 +--* byref V25.:_reference (offs=0x00) -> V145 tmp105 +--* int V25.:_length (offs=0x08) -> V146 tmp106 [000169] ----------- \--* LCL_VAR struct(P) V48 tmp8 \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 \--* int V48.:_length (offs=0x08) -> V152 tmp112 LocalAddressVisitor visiting statement: STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [000172] ----------- \--* LCL_VAR struct(P) V25 loc21 \--* byref V25.:_reference (offs=0x00) -> V145 tmp105 \--* int V25.:_length (offs=0x08) -> V146 tmp106 LocalAddressVisitor visiting statement: STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 LocalAddressVisitor visiting statement: STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 LocalAddressVisitor visiting statement: STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 LocalAddressVisitor visiting statement: STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 LocalAddressVisitor visiting statement: STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 LocalAddressVisitor visiting statement: STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 LocalAddressVisitor visiting statement: STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 LocalAddressVisitor visiting statement: STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 LocalAddressVisitor visiting statement: STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 LocalAddressVisitor visiting statement: STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 LocalAddressVisitor visiting statement: STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 LocalAddressVisitor visiting statement: STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 LocalAddressVisitor visiting statement: STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 LocalAddressVisitor visiting statement: STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* FIELD int :_length [001572] ----------- \--* ADDR byref [001573] -------N--- \--* LCL_VAR struct(P) V19 loc15 \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 \--* int V19.:_length (offs=0x08) -> V144 tmp104 Replacing the field in promoted struct with local var V144 LocalAddressVisitor modified statement: STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* LCL_VAR int V144 tmp104 LocalAddressVisitor visiting statement: STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* FIELD int :_length [001576] ----------- | \--* ADDR byref [001577] -------N--- | \--* LCL_VAR struct(P) V19 loc15 | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [001065] ----------- \--* CNS_INT int 2 Replacing the field in promoted struct with local var V144 LocalAddressVisitor modified statement: STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* LCL_VAR int V144 tmp104 [001065] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001581] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001613] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] -------N--- +--* FIELD byref :_reference [001598] ----------- | \--* ADDR byref [001599] -------N--- | \--* LCL_VAR struct(P) V78 tmp38 | \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 | \--* int V78.:_length (offs=0x08) -> V160 tmp120 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 Replacing the field in promoted struct with local var V159 LocalAddressVisitor modified statement: STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] D------N--- +--* LCL_VAR byref V159 tmp119 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 LocalAddressVisitor visiting statement: STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] -------N--- +--* FIELD int :_length [001605] ----------- | \--* ADDR byref [001606] -------N--- | \--* LCL_VAR struct(P) V78 tmp38 | \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 | \--* int V78.:_length (offs=0x08) -> V160 tmp120 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 Replacing the field in promoted struct with local var V160 LocalAddressVisitor modified statement: STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] D------N--- +--* LCL_VAR int V160 tmp120 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 LocalAddressVisitor visiting statement: STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct(P) V68 tmp28 +--* byref V68.:_reference (offs=0x00) -> V153 tmp113 +--* int V68.:_length (offs=0x08) -> V154 tmp114 [001586] ----------- \--* LCL_VAR struct(P) V78 tmp38 \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 \--* int V78.:_length (offs=0x08) -> V160 tmp120 LocalAddressVisitor visiting statement: STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct(P) V79 tmp39 +--* byref V79.:_reference (offs=0x00) -> V161 tmp121 +--* int V79.:_length (offs=0x08) -> V162 tmp122 [001081] n---------- \--* OBJ struct [001080] ----------- \--* ADDR byref [001079] -------N--- \--* LCL_VAR struct(P) V68 tmp28 \--* byref V68.:_reference (offs=0x00) -> V153 tmp113 \--* int V68.:_length (offs=0x08) -> V154 tmp114 LocalAddressVisitor modified statement: STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct(P) V79 tmp39 +--* byref V79.:_reference (offs=0x00) -> V161 tmp121 +--* int V79.:_length (offs=0x08) -> V162 tmp122 [001081] ----------- \--* LCL_VAR struct(P) V68 tmp28 \--* byref V68.:_reference (offs=0x00) -> V153 tmp113 \--* int V68.:_length (offs=0x08) -> V154 tmp114 LocalAddressVisitor visiting statement: STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* FIELD int :_length [001618] ----------- \--* ADDR byref [001619] -------N--- \--* LCL_VAR struct(P) V19 loc15 \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 \--* int V19.:_length (offs=0x08) -> V144 tmp104 Replacing the field in promoted struct with local var V144 LocalAddressVisitor modified statement: STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* LCL_VAR int V144 tmp104 LocalAddressVisitor visiting statement: STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001647] ----------- \--* FIELD int :_length [001645] ----------- \--* ADDR byref [001646] -------N--- \--* LCL_VAR struct(P) V79 tmp39 \--* byref V79.:_reference (offs=0x00) -> V161 tmp121 \--* int V79.:_length (offs=0x08) -> V162 tmp122 Replacing the field in promoted struct with local var V162 LocalAddressVisitor modified statement: STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001647] ----------- \--* LCL_VAR int V162 tmp122 LocalAddressVisitor visiting statement: STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* FIELD byref :_reference [001632] ----------- \--* ADDR byref [001631] -------N--- \--* LCL_VAR struct(P) V79 tmp39 \--* byref V79.:_reference (offs=0x00) -> V161 tmp121 \--* int V79.:_length (offs=0x08) -> V162 tmp122 Replacing the field in promoted struct with local var V161 LocalAddressVisitor modified statement: STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* LCL_VAR byref V161 tmp121 LocalAddressVisitor visiting statement: STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* FIELD byref :_reference [001634] ----------- \--* ADDR byref [001635] -------N--- \--* LCL_VAR struct(P) V19 loc15 \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 \--* int V19.:_length (offs=0x08) -> V144 tmp104 Replacing the field in promoted struct with local var V143 LocalAddressVisitor modified statement: STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* LCL_VAR byref V143 tmp103 LocalAddressVisitor visiting statement: STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* FIELD int :_length [001637] ----------- \--* ADDR byref [001638] -------N--- \--* LCL_VAR struct(P) V19 loc15 \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 \--* int V19.:_length (offs=0x08) -> V144 tmp104 Replacing the field in promoted struct with local var V144 LocalAddressVisitor modified statement: STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* LCL_VAR int V144 tmp104 LocalAddressVisitor visiting statement: STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] ----------- * NOP void LocalAddressVisitor visiting statement: STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 LocalAddressVisitor visiting statement: STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() LocalAddressVisitor visiting statement: STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001693] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001725] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] -------N--- +--* FIELD byref :_reference [001710] ----------- | \--* ADDR byref [001711] -------N--- | \--* LCL_VAR struct(P) V85 tmp45 | \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 | \--* int V85.:_length (offs=0x08) -> V164 tmp124 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 Replacing the field in promoted struct with local var V163 LocalAddressVisitor modified statement: STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] D------N--- +--* LCL_VAR byref V163 tmp123 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 LocalAddressVisitor visiting statement: STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] -------N--- +--* FIELD int :_length [001717] ----------- | \--* ADDR byref [001718] -------N--- | \--* LCL_VAR struct(P) V85 tmp45 | \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 | \--* int V85.:_length (offs=0x08) -> V164 tmp124 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 Replacing the field in promoted struct with local var V164 LocalAddressVisitor modified statement: STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] D------N--- +--* LCL_VAR int V164 tmp124 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 LocalAddressVisitor visiting statement: STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [001698] ----------- \--* LCL_VAR struct(P) V85 tmp45 \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 \--* int V85.:_length (offs=0x08) -> V164 tmp124 LocalAddressVisitor visiting statement: STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* FIELD int :_length [001023] ----------- | | \--* ADDR byref [001022] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* FIELD byref :_reference [001027] ----------- | | \--* ADDR byref [001026] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 Replacing the field in promoted struct with local var V144 Replacing the field in promoted struct with local var V143 LocalAddressVisitor modified statement: STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* LCL_VAR int V144 tmp104 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* LCL_VAR byref V143 tmp103 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 LocalAddressVisitor visiting statement: STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 LocalAddressVisitor visiting statement: STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 LocalAddressVisitor visiting statement: STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 LocalAddressVisitor visiting statement: STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* EQ int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 LocalAddressVisitor visiting statement: STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 LocalAddressVisitor visiting statement: STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct(P) V90 tmp50 +--* byref V90.:_reference (offs=0x00) -> V165 tmp125 +--* int V90.:_length (offs=0x08) -> V166 tmp126 [000193] n---------- \--* OBJ struct [000192] ----------- \--* ADDR byref [000190] -------N--- \--* LCL_VAR struct V02 arg2 LocalAddressVisitor modified statement: STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct(P) V90 tmp50 +--* byref V90.:_reference (offs=0x00) -> V165 tmp125 +--* int V90.:_length (offs=0x08) -> V166 tmp126 [000193] ----------- \--* LCL_VAR struct V02 arg2 LocalAddressVisitor visiting statement: STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* FIELD byref :_reference [001791] ----------- \--* ADDR byref [001790] -------N--- \--* LCL_VAR struct(P) V90 tmp50 \--* byref V90.:_reference (offs=0x00) -> V165 tmp125 \--* int V90.:_length (offs=0x08) -> V166 tmp126 Replacing the field in promoted struct with local var V165 LocalAddressVisitor modified statement: STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* LCL_VAR byref V165 tmp125 LocalAddressVisitor visiting statement: STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 LocalAddressVisitor visiting statement: STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 LocalAddressVisitor visiting statement: STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 LocalAddressVisitor visiting statement: STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 LocalAddressVisitor visiting statement: STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 LocalAddressVisitor visiting statement: STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 LocalAddressVisitor visiting statement: STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 LocalAddressVisitor visiting statement: STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 LocalAddressVisitor visiting statement: STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 LocalAddressVisitor visiting statement: STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 LocalAddressVisitor visiting statement: STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 LocalAddressVisitor visiting statement: STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 LocalAddressVisitor visiting statement: STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 LocalAddressVisitor visiting statement: STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 LocalAddressVisitor visiting statement: STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 LocalAddressVisitor visiting statement: STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* FIELD int :_length [000884] ----------- | | \--* ADDR byref [000883] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* FIELD byref :_reference [000888] ----------- | | \--* ADDR byref [000887] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 Replacing the field in promoted struct with local var V144 Replacing the field in promoted struct with local var V143 LocalAddressVisitor modified statement: STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* LCL_VAR int V144 tmp104 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* LCL_VAR byref V143 tmp103 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* EQ int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 LocalAddressVisitor visiting statement: STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 LocalAddressVisitor visiting statement: STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 LocalAddressVisitor visiting statement: STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 LocalAddressVisitor visiting statement: STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 LocalAddressVisitor visiting statement: STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 LocalAddressVisitor visiting statement: STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 LocalAddressVisitor visiting statement: STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 LocalAddressVisitor visiting statement: STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* NE int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 LocalAddressVisitor visiting statement: STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 LocalAddressVisitor visiting statement: STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 LocalAddressVisitor visiting statement: STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 LocalAddressVisitor visiting statement: STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 LocalAddressVisitor visiting statement: STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 LocalAddressVisitor visiting statement: STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 LocalAddressVisitor visiting statement: STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 LocalAddressVisitor visiting statement: STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* FIELD int :_length [000691] ----------- | | \--* ADDR byref [000690] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* FIELD byref :_reference [000695] ----------- | | \--* ADDR byref [000694] -------N--- | | \--* LCL_VAR struct(P) V19 loc15 | | \--* byref V19.:_reference (offs=0x00) -> V143 tmp103 | | \--* int V19.:_length (offs=0x08) -> V144 tmp104 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 Replacing the field in promoted struct with local var V144 Replacing the field in promoted struct with local var V143 LocalAddressVisitor modified statement: STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* LCL_VAR int V144 tmp104 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* LCL_VAR byref V143 tmp103 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* EQ int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 LocalAddressVisitor visiting statement: STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 LocalAddressVisitor visiting statement: STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 LocalAddressVisitor visiting statement: STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* EQ int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 LocalAddressVisitor visiting statement: STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 LocalAddressVisitor visiting statement: STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* EQ int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 LocalAddressVisitor visiting statement: STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 LocalAddressVisitor visiting statement: STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* EQ int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 LocalAddressVisitor visiting statement: STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 LocalAddressVisitor visiting statement: STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 LocalAddressVisitor visiting statement: STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 LocalAddressVisitor visiting statement: STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 LocalAddressVisitor visiting statement: STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 LocalAddressVisitor visiting statement: STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* FIELD int :_length [002232] ----------- \--* ADDR byref [002233] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* FIELD int :_length [002236] ----------- \--* ADDR byref [002237] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* FIELD int :_length [002240] ----------- \--* ADDR byref [002241] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 LocalAddressVisitor visiting statement: STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 LocalAddressVisitor visiting statement: STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 LocalAddressVisitor visiting statement: STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 LocalAddressVisitor visiting statement: STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* FIELD int :_length [002290] ----------- \--* ADDR byref [002291] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* EQ int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* FIELD int :_length [002294] ----------- \--* ADDR byref [002295] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 LocalAddressVisitor visiting statement: STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* FIELD int :_length [002298] ----------- \--* ADDR byref [002299] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 LocalAddressVisitor visiting statement: STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 LocalAddressVisitor visiting statement: STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 LocalAddressVisitor visiting statement: STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* FIELD int :_length [002345] ----------- \--* ADDR byref [002346] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 LocalAddressVisitor visiting statement: STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 LocalAddressVisitor visiting statement: STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 LocalAddressVisitor visiting statement: STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 LocalAddressVisitor visiting statement: STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 LocalAddressVisitor visiting statement: STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 LocalAddressVisitor visiting statement: STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* FIELD int :_length [002392] ----------- \--* ADDR byref [002393] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 LocalAddressVisitor visiting statement: STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 LocalAddressVisitor visiting statement: STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 LocalAddressVisitor visiting statement: STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 LocalAddressVisitor visiting statement: STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 LocalAddressVisitor visiting statement: STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 LocalAddressVisitor visiting statement: STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 LocalAddressVisitor visiting statement: STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 LocalAddressVisitor visiting statement: STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 LocalAddressVisitor visiting statement: STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 LocalAddressVisitor visiting statement: STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* FIELD int :_length [002488] ----------- \--* ADDR byref [002489] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 LocalAddressVisitor visiting statement: STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 LocalAddressVisitor visiting statement: STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 LocalAddressVisitor visiting statement: STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 LocalAddressVisitor visiting statement: STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* FIELD int :_length [002535] ----------- \--* ADDR byref [002536] -------N--- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* LCL_FLD int V02 arg2 [+8] LocalAddressVisitor visiting statement: STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 LocalAddressVisitor visiting statement: STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 LocalAddressVisitor visiting statement: STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 LocalAddressVisitor visiting statement: STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 LocalAddressVisitor visiting statement: STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void *************** Finishing PHASE Morph - Structs/AddrExp Trees after Morph - Structs/AddrExp ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB79,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal bwd BB231 [0316] 1 BB228 1 [000..000) i internal bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB271 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB283 1 [000..000) i internal bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 ***** BB01 STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct(P) V41 tmp1 +--* byref V41.:_reference (offs=0x00) -> V147 tmp107 +--* int V41.:_length (offs=0x08) -> V148 tmp108 [000010] ----------- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct(P) V75 tmp35 +--* byref V75.:_reference (offs=0x00) -> V155 tmp115 +--* int V75.:_length (offs=0x08) -> V156 tmp116 [000019] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001480] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001481] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000020] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] ----------- arg0 +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct(P) V77 tmp37 +--* byref V77.:_reference (offs=0x00) -> V157 tmp117 +--* int V77.:_length (offs=0x08) -> V158 tmp118 [000065] ----------- \--* LCL_VAR struct V02 arg2 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -AC-------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* NE int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --C-G------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001149] ----------- arg1 +--* LCL_VAR int V24 loc20 [001150] ----------- arg2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] ----------- arg0 +--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct(P) V48 tmp8 +--* byref V48.:_reference (offs=0x00) -> V151 tmp111 +--* int V48.:_length (offs=0x08) -> V152 tmp112 [000164] ----------- \--* CNS_INT int 0 ***** BB79 STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] ----------- * NOP void ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] D------N--- +--* LCL_VAR byref V151 tmp111 [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] D------N--- +--* LCL_VAR int V152 tmp112 [001556] ----------- \--* CNS_INT int 4 ***** BB79 STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct(P) V25 loc21 +--* byref V25.:_reference (offs=0x00) -> V145 tmp105 +--* int V25.:_length (offs=0x08) -> V146 tmp106 [000169] ----------- \--* LCL_VAR struct(P) V48 tmp8 \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 \--* int V48.:_length (offs=0x08) -> V152 tmp112 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [000172] ----------- \--* LCL_VAR struct(P) V25 loc21 \--* byref V25.:_reference (offs=0x00) -> V145 tmp105 \--* int V25.:_length (offs=0x08) -> V146 tmp106 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB123 (always), preds={BB92,BB93} succs={BB123} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* LCL_VAR int V144 tmp104 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* LCL_VAR int V144 tmp104 [001065] ----------- \--* CNS_INT int 2 ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001581] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001613] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] D------N--- +--* LCL_VAR byref V159 tmp119 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] D------N--- +--* LCL_VAR int V160 tmp120 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00231 ( 0x383[E-] ... ??? ) [001078] -AC-------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct(P) V68 tmp28 +--* byref V68.:_reference (offs=0x00) -> V153 tmp113 +--* int V68.:_length (offs=0x08) -> V154 tmp114 [001586] ----------- \--* LCL_VAR struct(P) V78 tmp38 \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 \--* int V78.:_length (offs=0x08) -> V160 tmp120 ***** BB102 STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct(P) V79 tmp39 +--* byref V79.:_reference (offs=0x00) -> V161 tmp121 +--* int V79.:_length (offs=0x08) -> V162 tmp122 [001081] ----------- \--* LCL_VAR struct(P) V68 tmp28 \--* byref V68.:_reference (offs=0x00) -> V153 tmp113 \--* int V68.:_length (offs=0x08) -> V154 tmp114 ***** BB102 STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* LCL_VAR int V144 tmp104 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] --C-------- * JTRUE void [001628] N-C------U- \--* GT int [001626] ----------- +--* LCL_VAR int V80 tmp40 [001647] ----------- \--* LCL_VAR int V162 tmp122 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* LCL_VAR byref V161 tmp121 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* LCL_VAR byref V143 tmp103 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* LCL_VAR int V144 tmp104 ***** BB104 STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] ----------- * NOP void ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB113 [000..000), preds={BB102} succs={BB114} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() ------------ BB114 [391..392) -> BB117 (cond), preds={BB104,BB113} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001693] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001725] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] D------N--- +--* LCL_VAR byref V163 tmp123 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] D------N--- +--* LCL_VAR int V164 tmp124 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [001698] ----------- \--* LCL_VAR struct(P) V85 tmp45 \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 \--* int V85.:_length (offs=0x08) -> V164 tmp124 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* LCL_VAR int V144 tmp104 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* LCL_VAR byref V143 tmp103 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB94,BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB95,BB123} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* EQ int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] --C-------- * JTRUE void [001752] N-C------U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001785] ----------- \--* LCL_VAR byref V89 tmp49 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct(P) V90 tmp50 +--* byref V90.:_reference (offs=0x00) -> V165 tmp125 +--* int V90.:_length (offs=0x08) -> V166 tmp126 [000193] ----------- \--* LCL_VAR struct V02 arg2 ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -AC-------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* LCL_VAR byref V165 tmp125 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB144 STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] --C-------- * JTRUE void [001805] N-C------U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001838] ----------- \--* LCL_VAR byref V94 tmp54 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* LCL_VAR int V144 tmp104 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* LCL_VAR byref V143 tmp103 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* EQ int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] --C-------- * JTRUE void [001865] N-C------U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001898] ----------- \--* LCL_VAR byref V98 tmp58 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* NE int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 ***** BB183 STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] --C-------- * JTRUE void [001911] N-C------U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001941] ----------- \--* LCL_VAR byref V101 tmp61 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* LCL_VAR int V144 tmp104 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* LCL_VAR byref V143 tmp103 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* EQ int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] --C-------- * JTRUE void [001968] N-C------U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [002001] ----------- \--* LCL_VAR byref V105 tmp65 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* EQ int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] --C-------- * JTRUE void [002028] N-C------U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002061] ----------- \--* LCL_VAR byref V109 tmp69 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* EQ int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] --C-------- * JTRUE void [002088] N-C------U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002121] ----------- \--* LCL_VAR byref V113 tmp73 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* EQ int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] --C-------- * JTRUE void [002148] N-C------U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002181] ----------- \--* LCL_VAR byref V117 tmp77 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 ***** BB228 STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] --C-------- * JTRUE void [002194] N-C------U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002227] ----------- \--* LCL_VAR byref V121 tmp81 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 ***** BB241 STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] --C-------- * JTRUE void [002252] N-C------U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002285] ----------- \--* LCL_VAR byref V125 tmp85 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* EQ int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 ***** BB257 STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] --C-------- * JTRUE void [002310] N-C------U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002340] ----------- \--* LCL_VAR byref V128 tmp88 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --C-G------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000504] ----------- arg2 +--* LCL_VAR int V39 loc35 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 ***** BB271 STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] --C-------- * JTRUE void [002357] N-C------U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002387] ----------- \--* LCL_VAR byref V131 tmp91 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 ***** BB278 STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] --C-------- * JTRUE void [002404] N-C------U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002437] ----------- \--* LCL_VAR byref V135 tmp95 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] --C-------- * JTRUE void [002450] N-C------U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002483] ----------- \--* LCL_VAR byref V139 tmp99 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 ***** BB291 STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] --C-------- * JTRUE void [002500] N-C------U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002530] ----------- \--* LCL_VAR byref V142 tmp102 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Forward Substitution ===> BB01 [000004]: not asg (single-use lcl) [001500]: not asg (single-use lcl) [000009]: not asg (single-use lcl) [000017]: not asg (single-use lcl) ===> BB02 [001478]: not asg (single-use lcl) ===> BB03 [001491]: not asg (single-use lcl) ===> BB04 [001484]: not asg (single-use lcl) ===> BB05 [000023]: not asg (single-use lcl) ===> BB06 ===> BB07 [000037]: not asg (single-use lcl) [000040]: not asg (single-use lcl) [000043]: not asg (single-use lcl) [000046]: not asg (single-use lcl) [000049]: not asg (single-use lcl) [000052]: not asg (single-use lcl) [000055]: not asg (single-use lcl) [000058]: not asg (single-use lcl) [000061]: not asg (single-use lcl) [001514]: no next stmt use [000068]: pinned local ===> BB08 ===> BB09 ===> BB10 ===> BB11 ===> BB12 ===> BB13 ===> BB14 ===> BB15 ===> BB31 ===> BB17 ===> BB18 ===> BB19 ===> BB20 [001381]: not asg (single-use lcl) ===> BB21 ===> BB22 ===> BB23 ===> BB24 ===> BB25 ===> BB26 ===> BB27 ===> BB28 ===> BB29 [001409]: not asg (single-use lcl) ===> BB30 ===> BB32 ===> BB33 ===> BB34 [001461]: no next stmt use [001459]: not asg (single-use lcl) ===> BB35 ===> BB36 ===> BB37 ===> BB38 ===> BB39 ===> BB40 ===> BB41 ===> BB42 ===> BB43 ===> BB44 ===> BB45 [001305]: not asg (single-use lcl) [001309]: not asg (single-use lcl) ===> BB46 ===> BB47 ===> BB48 ===> BB49 [001205]: no next stmt use [001203]: not asg (single-use lcl) [001214]: not asg (single-use lcl) [001218]: not asg (single-use lcl) ===> BB50 ===> BB51 [000083]: pinned local ===> BB52 ===> BB53 ===> BB54 ===> BB55 ===> BB56 ===> BB57 ===> BB58 [001129]: not asg (single-use lcl) ===> BB59 ===> BB60 ===> BB61 [001147]: [001149] is only use of [001146] (V24) -- fwd subbing [001145]; new next stmt is STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001145] ----------- arg1 +--* LCL_VAR int V70 tmp30 [001150] ----------- arg2 \--* CNS_INT int 0 removing useless STMT00249 ( ??? ... 0x26F ) [001147] -A--------- * ASG int [001146] D------N--- +--* LCL_VAR int V24 loc20 [001145] ----------- \--* LCL_VAR int V70 tmp30 from BB61 ===> BB62 [001163]: not asg (single-use lcl) ===> BB63 ===> BB64 ===> BB65 ===> BB66 ===> BB67 ===> BB68 ===> BB69 ===> BB70 [000118]: not asg (single-use lcl) ===> BB71 ===> BB72 ===> BB73 [000131]: not asg (single-use lcl) ===> BB74 [001110]: not asg (single-use lcl) ===> BB75 ===> BB76 ===> BB77 ===> BB78 [000148]: not asg (single-use lcl) ===> BB79 [000157]: not asg (single-use lcl) [000165]: not asg (single-use lcl) [001553]: not asg (single-use lcl) [001558]: not asg (single-use lcl) [000171]: [000172] is only use of [000170] (V25) -- fwd subbing [000169]; new next stmt is STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [000169] ----------- \--* LCL_VAR struct(P) V48 tmp8 \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 \--* int V48.:_length (offs=0x08) -> V152 tmp112 removing useless STMT00043 ( 0x2FD[--] ... ??? ) [000171] -A--------- * ASG struct (copy) [000170] D------N--- +--* LCL_VAR struct(P) V25 loc21 +--* byref V25.:_reference (offs=0x00) -> V145 tmp105 +--* int V25.:_length (offs=0x08) -> V146 tmp106 [000169] ----------- \--* LCL_VAR struct(P) V48 tmp8 \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 \--* int V48.:_length (offs=0x08) -> V152 tmp112 from BB79 [001558]: not asg (single-use lcl) [000174]: not asg (single-use lcl) [000177]: not asg (single-use lcl) ===> BB85 ===> BB86 [000951]: not asg (single-use lcl) [000954]: not asg (single-use lcl) [000957]: not asg (single-use lcl) [000961]: not asg (single-use lcl) ===> BB87 ===> BB88 [000968]: not asg (single-use lcl) [000975]: not asg (single-use lcl) ===> BB89 [001093]: not asg (single-use lcl) ===> BB90 [000981]: not asg (single-use lcl) ===> BB91 [000990]: not asg (single-use lcl) ===> BB92 ===> BB93 ===> BB94 ===> BB95 ===> BB96 [001014]: not asg (single-use lcl) ===> BB97 [001070]: not asg (single-use lcl) [001582]: not asg (single-use lcl) ===> BB99 ===> BB100 [001604]: not asg (single-use lcl) ===> BB102 [001078]: [001081] is only use of [001077] (V68) -- fwd subbing [001586]; new next stmt is STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct(P) V79 tmp39 +--* byref V79.:_reference (offs=0x00) -> V161 tmp121 +--* int V79.:_length (offs=0x08) -> V162 tmp122 [001586] ----------- \--* LCL_VAR struct(P) V78 tmp38 \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 \--* int V78.:_length (offs=0x08) -> V160 tmp120 removing useless STMT00231 ( 0x383[E-] ... ??? ) [001078] -A--------- * ASG struct (copy) [001077] D------N--- +--* LCL_VAR struct(P) V68 tmp28 +--* byref V68.:_reference (offs=0x00) -> V153 tmp113 +--* int V68.:_length (offs=0x08) -> V154 tmp114 [001586] ----------- \--* LCL_VAR struct(P) V78 tmp38 \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 \--* int V78.:_length (offs=0x08) -> V160 tmp120 from BB102 [001643]: not asg (single-use lcl) [001625]: [001626] is only use of [001624] (V80) -- fwd subbing [001620]; new next stmt is STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] ----------- * JTRUE void [001628] N--------U- \--* GT int [001620] ----------- +--* LCL_VAR int V144 tmp104 [001647] ----------- \--* LCL_VAR int V162 tmp122 removing useless STMT00335 ( INL17 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001625] -A--------- * ASG int [001624] D------N--- +--* LCL_VAR int V80 tmp40 [001620] ----------- \--* LCL_VAR int V144 tmp104 from BB102 [001643]: not asg (single-use lcl) ===> BB104 [001669]: no next stmt use [001671]: no next stmt use [001673]: no next stmt use ===> BB113 ===> BB114 [001694]: not asg (single-use lcl) ===> BB116 ===> BB117 [001716]: not asg (single-use lcl) ===> BB119 ===> BB120 ===> BB121 [001054]: not asg (single-use lcl) ===> BB122 ===> BB123 ===> BB124 ===> BB125 ===> BB126 ===> BB127 [001783]: not asg (single-use lcl) ===> BB130 [001738]: not asg (single-use lcl) ===> BB131 [001788]: [001785] is only use of [001787] (V89) -- fwd subbing [001749]; new next stmt is STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG------ * JTRUE void [001752] N--XG----U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00368 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001788] -A-XG------ * ASG byref [001787] D------N--- +--* LCL_VAR byref V89 tmp49 [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 from BB131 ===> BB132 [001759]: not asg (single-use lcl) ===> BB133 ===> BB134 [000189]: not asg (single-use lcl) [001794]: no next stmt use [000196]: pinned local [000200]: not asg (single-use lcl) ===> BB136 ===> BB137 ===> BB138 ===> BB139 ===> BB140 ===> BB141 [000836]: not asg (single-use lcl) ===> BB142 [000914]: not asg (single-use lcl) ===> BB143 [000848]: no next stmt use [000846]: not asg (single-use lcl) [000852]: not asg (single-use lcl) ===> BB144 [001836]: not asg (single-use lcl) [001799]: not asg (single-use lcl) [001841]: [001838] is only use of [001840] (V94) -- fwd subbing [001802]; new next stmt is STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG------ * JTRUE void [001805] N--XG----U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 removing useless STMT00378 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001841] -A-XG------ * ASG byref [001840] D------N--- +--* LCL_VAR byref V94 tmp54 [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 from BB144 [001799]: not asg (single-use lcl) ===> BB146 [001815]: not asg (single-use lcl) ===> BB147 ===> BB148 ===> BB149 ===> BB150 ===> BB151 ===> BB152 [001896]: not asg (single-use lcl) ===> BB155 [001851]: not asg (single-use lcl) ===> BB156 [001901]: [001898] is only use of [001900] (V98) -- fwd subbing [001862]; new next stmt is STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG------ * JTRUE void [001865] N--XG----U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00389 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001901] -A-XG------ * ASG byref [001900] D------N--- +--* LCL_VAR byref V98 tmp58 [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 from BB156 ===> BB157 [001872]: not asg (single-use lcl) ===> BB158 ===> BB159 ===> BB160 [000868]: not asg (single-use lcl) ===> BB161 ===> BB162 ===> BB163 ===> BB164 ===> BB165 ===> BB166 ===> BB167 ===> BB168 ===> BB169 ===> BB212 ===> BB171 ===> BB172 [000735]: not asg (single-use lcl) ===> BB173 ===> BB174 ===> BB175 ===> BB176 ===> BB177 ===> BB178 ===> BB179 ===> BB180 [000656]: no next stmt use [000654]: not asg (single-use lcl) ===> BB181 ===> BB182 ===> BB183 [001905]: not asg (single-use lcl) [001944]: [001941] is only use of [001943] (V101) -- fwd subbing [001908]; new next stmt is STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG------ * JTRUE void [001911] N--XG----U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00397 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001944] -A-XG------ * ASG byref [001943] D------N--- +--* LCL_VAR byref V101 tmp61 [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 from BB183 [001905]: not asg (single-use lcl) ===> BB185 [001920]: not asg (single-use lcl) ===> BB186 ===> BB187 ===> BB188 ===> BB189 ===> BB190 ===> BB191 [001999]: not asg (single-use lcl) ===> BB194 [001954]: not asg (single-use lcl) ===> BB195 [002004]: [002001] is only use of [002003] (V105) -- fwd subbing [001965]; new next stmt is STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG------ * JTRUE void [001968] N--XG----U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00408 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [002004] -A-XG------ * ASG byref [002003] D------N--- +--* LCL_VAR byref V105 tmp65 [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 from BB195 ===> BB196 [001975]: not asg (single-use lcl) ===> BB197 ===> BB198 ===> BB199 ===> BB200 ===> BB201 ===> BB202 ===> BB203 ===> BB204 [002059]: not asg (single-use lcl) ===> BB207 [002014]: not asg (single-use lcl) ===> BB208 [002064]: [002061] is only use of [002063] (V109) -- fwd subbing [002025]; new next stmt is STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG------ * JTRUE void [002028] N--XG----U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00419 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002064] -A-XG------ * ASG byref [002063] D------N--- +--* LCL_VAR byref V109 tmp69 [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 from BB208 ===> BB209 [002035]: not asg (single-use lcl) ===> BB210 ===> BB211 ===> BB213 ===> BB215 [002074]: not asg (single-use lcl) ===> BB216 [002124]: [002121] is only use of [002123] (V113) -- fwd subbing [002085]; new next stmt is STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG------ * JTRUE void [002088] N--XG----U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00430 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002124] -A-XG------ * ASG byref [002123] D------N--- +--* LCL_VAR byref V113 tmp73 [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 from BB216 ===> BB217 [002095]: not asg (single-use lcl) ===> BB218 ===> BB220 [002179]: not asg (single-use lcl) ===> BB223 [002134]: not asg (single-use lcl) ===> BB224 [002184]: [002181] is only use of [002183] (V117) -- fwd subbing [002145]; new next stmt is STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG------ * JTRUE void [002148] N--XG----U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00441 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002184] -A-XG------ * ASG byref [002183] D------N--- +--* LCL_VAR byref V117 tmp77 [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 from BB224 ===> BB225 [002155]: not asg (single-use lcl) ===> BB226 ===> BB228 [000812]: no next stmt use [000810]: not asg (single-use lcl) [002225]: not asg (single-use lcl) [002188]: not asg (single-use lcl) [002230]: [002227] is only use of [002229] (V121) -- fwd subbing [002191]; new next stmt is STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG------ * JTRUE void [002194] N--XG----U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00450 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002230] -A-XG------ * ASG byref [002229] D------N--- +--* LCL_VAR byref V121 tmp81 [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 from BB228 [002188]: not asg (single-use lcl) ===> BB230 [002204]: not asg (single-use lcl) ===> BB231 ===> BB233 ===> BB234 ===> BB235 ===> BB236 ===> BB237 ===> BB238 ===> BB239 ===> BB240 ===> BB241 [000310]: no next stmt use [000308]: not asg (single-use lcl) [002283]: not asg (single-use lcl) [002246]: not asg (single-use lcl) [002288]: [002285] is only use of [002287] (V125) -- fwd subbing [002249]; new next stmt is STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG------ * JTRUE void [002252] N--XG----U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00459 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002288] -A-XG------ * ASG byref [002287] D------N--- +--* LCL_VAR byref V125 tmp85 [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 from BB241 [002246]: not asg (single-use lcl) ===> BB243 [002262]: not asg (single-use lcl) ===> BB244 ===> BB246 [000325]: not asg (single-use lcl) [000328]: not asg (single-use lcl) ===> BB247 ===> BB248 ===> BB250 ===> BB251 ===> BB252 ===> BB253 ===> BB254 ===> BB255 ===> BB256 ===> BB257 [002304]: not asg (single-use lcl) [002343]: [002340] is only use of [002342] (V128) -- fwd subbing [002307]; new next stmt is STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG------ * JTRUE void [002310] N--XG----U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00467 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002343] -A-XG------ * ASG byref [002342] D------N--- +--* LCL_VAR byref V128 tmp88 [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 from BB257 [002304]: not asg (single-use lcl) ===> BB259 [002319]: not asg (single-use lcl) ===> BB260 ===> BB262 ===> BB263 [000475]: not asg (single-use lcl) [000479]: not asg (single-use lcl) ===> BB264 ===> BB265 ===> BB266 ===> BB267 ===> BB268 ===> BB269 ===> BB270 [000501]: [000504] is only use of [000500] (V39) -- fwd subbing [000499]; new next stmt is STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000499] ----------- arg2 +--* LCL_VAR int V55 tmp15 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 removing useless STMT00113 ( ??? ... 0x71B ) [000501] -A--------- * ASG int [000500] D------N--- +--* LCL_VAR int V39 loc35 [000499] ----------- \--* LCL_VAR int V55 tmp15 from BB270 ===> BB271 [002351]: not asg (single-use lcl) [002390]: [002387] is only use of [002389] (V131) -- fwd subbing [002354]; new next stmt is STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG------ * JTRUE void [002357] N--XG----U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00475 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002390] -A-XG------ * ASG byref [002389] D------N--- +--* LCL_VAR byref V131 tmp91 [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 from BB271 [002351]: not asg (single-use lcl) ===> BB273 [002366]: not asg (single-use lcl) ===> BB274 ===> BB275 ===> BB276 ===> BB277 ===> BB278 [000363]: no next stmt use [000361]: not asg (single-use lcl) [002435]: not asg (single-use lcl) [002398]: not asg (single-use lcl) [002440]: [002437] is only use of [002439] (V135) -- fwd subbing [002401]; new next stmt is STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG------ * JTRUE void [002404] N--XG----U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00484 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002440] -A-XG------ * ASG byref [002439] D------N--- +--* LCL_VAR byref V135 tmp95 [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 from BB278 [002398]: not asg (single-use lcl) ===> BB280 [002414]: not asg (single-use lcl) ===> BB281 ===> BB283 [000399]: no next stmt use [000397]: not asg (single-use lcl) [002481]: not asg (single-use lcl) [002444]: not asg (single-use lcl) [002486]: [002483] is only use of [002485] (V139) -- fwd subbing [002447]; new next stmt is STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG------ * JTRUE void [002450] N--XG----U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00493 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002486] -A-XG------ * ASG byref [002485] D------N--- +--* LCL_VAR byref V139 tmp99 [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 from BB283 [002444]: not asg (single-use lcl) ===> BB285 [002460]: not asg (single-use lcl) ===> BB286 ===> BB287 ===> BB289 ===> BB290 ===> BB291 [002494]: not asg (single-use lcl) [002533]: [002530] is only use of [002532] (V142) -- fwd subbing [002497]; new next stmt is STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG------ * JTRUE void [002500] N--XG----U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 removing useless STMT00501 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002533] -A-XG------ * ASG byref [002532] D------N--- +--* LCL_VAR byref V142 tmp102 [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 from BB291 [002494]: not asg (single-use lcl) ===> BB293 [002509]: not asg (single-use lcl) ===> BB294 ===> BB296 ===> BB297 [000250]: no next stmt use [000248]: not asg (single-use lcl) [000259]: not asg (single-use lcl) [000263]: not asg (single-use lcl) ===> BB298 ===> BB299 [000214]: pinned local ===> BB300 ===> BB301 ===> BB302 ===> BB303 ===> BB304 *************** Finishing PHASE Forward Substitution Trees after Forward Substitution ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal bwd BB113 [0228] 1 BB102 1 [000..000) i internal bwd BB114 [0229] 2 BB104,BB113 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB79,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal bwd BB147 [0261] 1 BB144 1 [000..000) i internal bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i bwd BB186 [0275] 1 BB183 1 [521..522) i bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal bwd BB231 [0316] 1 BB228 1 [000..000) i internal bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i bwd BB274 [0338] 1 BB271 1 [731..732) i bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal bwd BB286 [0349] 1 BB283 1 [000..000) i internal bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 ***** BB01 STMT00005 ( ??? ... 0x015 ) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct(P) V41 tmp1 +--* byref V41.:_reference (offs=0x00) -> V147 tmp107 +--* int V41.:_length (offs=0x08) -> V148 tmp108 [000010] ----------- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct(P) V75 tmp35 +--* byref V75.:_reference (offs=0x00) -> V155 tmp115 +--* int V75.:_length (offs=0x08) -> V156 tmp116 [000019] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001480] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001481] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000020] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] ----------- arg0 +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct(P) V77 tmp37 +--* byref V77.:_reference (offs=0x00) -> V157 tmp117 +--* int V77.:_length (offs=0x08) -> V158 tmp118 [000065] ----------- \--* LCL_VAR struct V02 arg2 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A--------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] ----------- * JTRUE void [001354] ----------- \--* NE int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001145] ----------- arg1 +--* LCL_VAR int V70 tmp30 [001150] ----------- arg2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] ----------- arg0 +--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct(P) V48 tmp8 +--* byref V48.:_reference (offs=0x00) -> V151 tmp111 +--* int V48.:_length (offs=0x08) -> V152 tmp112 [000164] ----------- \--* CNS_INT int 0 ***** BB79 STMT00323 ( INL09 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001544] ----------- * NOP void ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A--------- * ASG byref [001552] D------N--- +--* LCL_VAR byref V151 tmp111 [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A--------- * ASG int [001557] D------N--- +--* LCL_VAR int V152 tmp112 [001556] ----------- \--* CNS_INT int 4 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [000169] ----------- \--* LCL_VAR struct(P) V48 tmp8 \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 \--* int V48.:_length (offs=0x08) -> V152 tmp112 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB123 (always), preds={BB92,BB93} succs={BB123} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* LCL_VAR int V144 tmp104 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* LCL_VAR int V144 tmp104 [001065] ----------- \--* CNS_INT int 2 ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001581] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001613] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -AC-------- * ASG byref [001603] D------N--- +--* LCL_VAR byref V159 tmp119 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X------- * ASG int [001609] D------N--- +--* LCL_VAR int V160 tmp120 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00339 ( ??? ... ??? ) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct(P) V79 tmp39 +--* byref V79.:_reference (offs=0x00) -> V161 tmp121 +--* int V79.:_length (offs=0x08) -> V162 tmp122 [001586] ----------- \--* LCL_VAR struct(P) V78 tmp38 \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 \--* int V78.:_length (offs=0x08) -> V160 tmp120 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] ----------- * JTRUE void [001628] N--------U- \--* GT int [001620] ----------- +--* LCL_VAR int V144 tmp104 [001647] ----------- \--* LCL_VAR int V162 tmp122 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* LCL_VAR byref V161 tmp121 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* LCL_VAR byref V143 tmp103 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* LCL_VAR int V144 tmp104 ***** BB104 STMT00341 ( INL19 @ 0x000[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001653] ----------- * NOP void ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 ------------ BB113 [000..000), preds={BB102} succs={BB114} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() ------------ BB114 [391..392) -> BB117 (cond), preds={BB104,BB113} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001693] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001725] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -AC-------- * ASG byref [001715] D------N--- +--* LCL_VAR byref V163 tmp123 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X------- * ASG int [001721] D------N--- +--* LCL_VAR int V164 tmp124 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [001698] ----------- \--* LCL_VAR struct(P) V85 tmp45 \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 \--* int V85.:_length (offs=0x08) -> V164 tmp124 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* LCL_VAR int V144 tmp104 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* LCL_VAR byref V143 tmp103 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB94,BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB95,BB123} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] ----------- * JTRUE void [001734] ----------- \--* EQ int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG------ * JTRUE void [001752] N--XG----U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct(P) V90 tmp50 +--* byref V90.:_reference (offs=0x00) -> V165 tmp125 +--* int V90.:_length (offs=0x08) -> V166 tmp126 [000193] ----------- \--* LCL_VAR struct V02 arg2 ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A--------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* LCL_VAR byref V165 tmp125 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG------ * JTRUE void [001805] N--XG----U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* LCL_VAR int V144 tmp104 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* LCL_VAR byref V143 tmp103 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] ----------- * JTRUE void [001847] ----------- \--* EQ int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG------ * JTRUE void [001865] N--XG----U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] ----------- * JTRUE void [000583] ----------- \--* NE int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG------ * JTRUE void [001911] N--XG----U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* LCL_VAR int V144 tmp104 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* LCL_VAR byref V143 tmp103 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] ----------- * JTRUE void [001950] ----------- \--* EQ int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG------ * JTRUE void [001968] N--XG----U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] ----------- * JTRUE void [002010] ----------- \--* EQ int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG------ * JTRUE void [002028] N--XG----U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] ----------- * JTRUE void [002070] ----------- \--* EQ int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG------ * JTRUE void [002088] N--XG----U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] ----------- * JTRUE void [002130] ----------- \--* EQ int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG------ * JTRUE void [002148] N--XG----U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG------ * JTRUE void [002194] N--XG----U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG------ * JTRUE void [002252] N--XG----U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* EQ int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG------ * JTRUE void [002310] N--XG----U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000499] ----------- arg2 +--* LCL_VAR int V55 tmp15 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG------ * JTRUE void [002357] N--XG----U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG------ * JTRUE void [002404] N--XG----U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG------ * JTRUE void [002450] N--XG----U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG------ * JTRUE void [002500] N--XG----U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs [no changes] *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB01, STMT00000 (before) [000001] --C-G------ * CALL r2r_ind void [000000] ----------- this \--* LCL_VAR byref V01 arg1 Initializing arg info for 1.CALL: Args for call [000001] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000000].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[002543].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] Morphing args for 1.CALL: Sorting the arguments: Deferred argument ('x0'): [000000] -----+----- * LCL_VAR byref V01 arg1 Moved to late list Deferred argument ('x11'): [002543] H----+----- * CNS_INT(h) long 0x400000000046ac80 ftn Moved to late list Register placement order: x0 x11 Args for [000001].CALL after fgMorphArgs: CallArg[[000000].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[002543].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] OutgoingArgsStackSize is 0 fgMorphTree BB01, STMT00000 (after) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn fgMorphTree BB01, STMT00001 (before) [000004] -A--------- * ASG int [000003] D------N--- +--* LCL_VAR int V11 loc7 [000002] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000004] -A---+----- * ASG int In BB01 New Local Constant Assertion: V11 == 0, index = #01 fgMorphTree BB01, STMT00320 (before) [001500] -A-XG------ * ASG byref [001499] D------N--- +--* LCL_VAR byref V76 tmp36 [001496] ---XG------ \--* FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 Before explicit null check morphing: [001496] ---XG------ * FIELD_ADDR byref : [000005] ----------- \--* LCL_VAR byref V01 arg1 After adding explicit null check: [002549] ---X-O----- * COMMA byref [002545] ---X-O----- +--* NULLCHECK byte [002544] ----------- | \--* LCL_VAR byref V01 arg1 [002548] -----O----- \--* ADD byref [002546] -----O----- +--* LCL_VAR byref V01 arg1 [002547] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002549] ---X-+-N--- * COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 fgMorphTree BB01, STMT00320 (after) [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 fgMorphTree BB01, STMT00003 (before) [000009] -AC-------- * ASG long [000008] D------N--- +--* LCL_VAR long V17 loc13 [001508] ---XGO----- \--* CAST long <- byref [001507] ---XGO----- \--* COMMA byref [001504] ---XGO----- +--* BOUNDS_CHECK_Rng void [001497] ----------- | +--* CNS_INT int 0 [001503] ----G------ | \--* FIELD int : [001502] ----------- | \--* LCL_VAR byref V76 tmp36 [001506] ----GO----- \--* ADD byref [001505] ----G------ +--* FIELD byref : [001501] ----------- | \--* LCL_VAR byref V76 tmp36 [001498] ----------- \--* CNS_INT long 0 lvaGrabTemp returning 167 (V167 tmp127) called for Cast away GC. Final value of Compiler::fgMorphField after morphing: [001503] ---XG------ * IND int [002556] -----+----- \--* ADD byref [001502] -----+----- +--* LCL_VAR byref V76 tmp36 [002555] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [001505] ---XG------ * IND byref [001501] -----+----- \--* LCL_VAR byref V76 tmp36 GenTreeNode creates assertion: [000009] -A-XG+----- * ASG long In BB01 New Local Copy Assertion: V17 == V167, index = #02 fgMorphTree BB01, STMT00003 (after) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 fgMorphTree BB01, STMT00005 (before) [000017] -A--------- * ASG struct (copy) [000016] D------N--- +--* LCL_VAR struct(P) V41 tmp1 +--* byref V41.:_reference (offs=0x00) -> V147 tmp107 +--* int V41.:_length (offs=0x08) -> V148 tmp108 [000010] ----------- \--* LCL_VAR struct V02 arg2 MorphCopyBlock: MorphBlock for dst tree, before: [000016] D----+-N--- * LCL_VAR struct(P) V41 tmp1 * byref V41.:_reference (offs=0x00) -> V147 tmp107 * int V41.:_length (offs=0x08) -> V148 tmp108 MorphBlock after: [000016] D----+-N--- * LCL_VAR struct(P) V41 tmp1 * byref V41.:_reference (offs=0x00) -> V147 tmp107 * int V41.:_length (offs=0x08) -> V148 tmp108 PrepareDst for [000016] have found a local var V41. MorphBlock for src tree, before: [000010] -----+----- * LCL_VAR struct V02 arg2 MorphBlock after: [000010] -----+----- * LCL_VAR struct V02 arg2 GenTreeNode creates assertion: [000017] -A--------- * ASG struct (copy) In BB01 New Local Copy Assertion: V41 == V02, index = #03 block assignment to morph: [000017] -A--------- * ASG struct (copy) [000016] D----+-N--- +--* LCL_VAR struct(P) V41 tmp1 +--* byref V41.:_reference (offs=0x00) -> V147 tmp107 +--* int V41.:_length (offs=0x08) -> V148 tmp108 [000010] -----+----- \--* LCL_VAR struct V02 arg2 (m_dstDoFldAsg=true) using field by field assignments. Local V02 should not be enregistered because: was accessed as a local field Local V02 should not be enregistered because: was accessed as a local field MorphCopyBlock (after): [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] fgMorphTree BB01, STMT00005 (after) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] fgMorphTree BB01, STMT00004 (before) [000015] ---XG------ * JTRUE void [000014] ---XG------ \--* EQ int [000012] ---XG------ +--* IND ubyte [000011] ----------- | \--* LCL_VAR long V17 loc13 [000013] ----------- \--* CNS_INT int 0 Assertion prop in BB01: Copy Assertion: V17 == V167, index = #02 [000011] ----------- * LCL_VAR long V167 tmp127 fgMorphTree BB01, STMT00004 (after) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 Morphing BB02 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB02, STMT00315 (before) [001478] -A--------- * ASG struct (copy) [001477] D------N--- +--* LCL_VAR struct(P) V75 tmp35 +--* byref V75.:_reference (offs=0x00) -> V155 tmp115 +--* int V75.:_length (offs=0x08) -> V156 tmp116 [000019] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 MorphCopyBlock: MorphBlock for dst tree, before: [001477] D----+-N--- * LCL_VAR struct(P) V75 tmp35 * byref V75.:_reference (offs=0x00) -> V155 tmp115 * int V75.:_length (offs=0x08) -> V156 tmp116 MorphBlock after: [001477] D----+-N--- * LCL_VAR struct(P) V75 tmp35 * byref V75.:_reference (offs=0x00) -> V155 tmp115 * int V75.:_length (offs=0x08) -> V156 tmp116 PrepareDst for [001477] have found a local var V75. MorphBlock for src tree, before: [000019] -----+----- * LCL_VAR struct(P) V41 tmp1 * byref V41.:_reference (offs=0x00) -> V147 tmp107 * int V41.:_length (offs=0x08) -> V148 tmp108 MorphBlock after: [000019] -----+----- * LCL_VAR struct(P) V41 tmp1 * byref V41.:_reference (offs=0x00) -> V147 tmp107 * int V41.:_length (offs=0x08) -> V148 tmp108 GenTreeNode creates assertion: [001478] -A--------- * ASG struct (copy) In BB02 New Local Copy Assertion: V75 == V41, index = #01 block assignment to morph: [001478] -A--------- * ASG struct (copy) [001477] D----+-N--- +--* LCL_VAR struct(P) V75 tmp35 +--* byref V75.:_reference (offs=0x00) -> V155 tmp115 +--* int V75.:_length (offs=0x08) -> V156 tmp116 [000019] -----+----- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 (m_dstDoFldAsg=true) (m_srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [002566] -A--------- * ASG byref In BB02 New Local Copy Assertion: V155 == V147, index = #02 GenTreeNode creates assertion: [002569] -A--------- * ASG int In BB02 New Local Copy Assertion: V156 == V148, index = #03 MorphCopyBlock (after): [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 fgMorphTree BB02, STMT00315 (after) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 fgMorphTree BB02, STMT00314 (before) [001476] ---XG------ * JTRUE void [001475] ---XG------ \--* NE int [001473] ---XG------ +--* FIELD bool : [001472] ----------- | \--* LCL_VAR byref V01 arg1 [001474] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [001473] ---XG------ * IND bool [002572] -----+----- \--* ADD byref [001472] -----+----- +--* LCL_VAR byref V01 arg1 [002571] -----+----- \--* CNS_INT long 8 fgMorphTree BB02, STMT00314 (after) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 Morphing BB03 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB03, STMT00318 (before) [001491] -A--------- * ASG struct (copy) [001490] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001480] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 MorphCopyBlock: MorphBlock for dst tree, before: [001490] D----+-N--- * LCL_VAR struct(P) V42 tmp2 * byref V42.:_reference (offs=0x00) -> V149 tmp109 * int V42.:_length (offs=0x08) -> V150 tmp110 MorphBlock after: [001490] D----+-N--- * LCL_VAR struct(P) V42 tmp2 * byref V42.:_reference (offs=0x00) -> V149 tmp109 * int V42.:_length (offs=0x08) -> V150 tmp110 PrepareDst for [001490] have found a local var V42. MorphBlock for src tree, before: [001480] -----+----- * LCL_VAR struct(P) V75 tmp35 * byref V75.:_reference (offs=0x00) -> V155 tmp115 * int V75.:_length (offs=0x08) -> V156 tmp116 MorphBlock after: [001480] -----+----- * LCL_VAR struct(P) V75 tmp35 * byref V75.:_reference (offs=0x00) -> V155 tmp115 * int V75.:_length (offs=0x08) -> V156 tmp116 GenTreeNode creates assertion: [001491] -A--------- * ASG struct (copy) In BB03 New Local Copy Assertion: V42 == V75, index = #01 block assignment to morph: [001491] -A--------- * ASG struct (copy) [001490] D----+-N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001480] -----+----- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 (m_dstDoFldAsg=true) (m_srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [002575] -A--------- * ASG byref In BB03 New Local Copy Assertion: V149 == V155, index = #02 GenTreeNode creates assertion: [002578] -A--------- * ASG int In BB03 New Local Copy Assertion: V150 == V156, index = #03 MorphCopyBlock (after): [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 fgMorphTree BB03, STMT00318 (after) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 fgMorphTree BB03, STMT00319 (before) [001494] -A--------- * ASG int [001493] D------N--- +--* LCL_VAR int V43 tmp3 [001489] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [001494] -A---+----- * ASG int In BB03 New Local Constant Assertion: V43 == 0, index = #04 Morphing BB04 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB04, STMT00316 (before) [001484] -A--------- * ASG struct (copy) [001483] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001481] ----------- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 MorphCopyBlock: MorphBlock for dst tree, before: [001483] D----+-N--- * LCL_VAR struct(P) V42 tmp2 * byref V42.:_reference (offs=0x00) -> V149 tmp109 * int V42.:_length (offs=0x08) -> V150 tmp110 MorphBlock after: [001483] D----+-N--- * LCL_VAR struct(P) V42 tmp2 * byref V42.:_reference (offs=0x00) -> V149 tmp109 * int V42.:_length (offs=0x08) -> V150 tmp110 PrepareDst for [001483] have found a local var V42. MorphBlock for src tree, before: [001481] -----+----- * LCL_VAR struct(P) V75 tmp35 * byref V75.:_reference (offs=0x00) -> V155 tmp115 * int V75.:_length (offs=0x08) -> V156 tmp116 MorphBlock after: [001481] -----+----- * LCL_VAR struct(P) V75 tmp35 * byref V75.:_reference (offs=0x00) -> V155 tmp115 * int V75.:_length (offs=0x08) -> V156 tmp116 GenTreeNode creates assertion: [001484] -A--------- * ASG struct (copy) In BB04 New Local Copy Assertion: V42 == V75, index = #01 block assignment to morph: [001484] -A--------- * ASG struct (copy) [001483] D----+-N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [001481] -----+----- \--* LCL_VAR struct(P) V75 tmp35 \--* byref V75.:_reference (offs=0x00) -> V155 tmp115 \--* int V75.:_length (offs=0x08) -> V156 tmp116 (m_dstDoFldAsg=true) (m_srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [002582] -A--------- * ASG byref In BB04 New Local Copy Assertion: V149 == V155, index = #02 GenTreeNode creates assertion: [002585] -A--------- * ASG int In BB04 New Local Copy Assertion: V150 == V156, index = #03 MorphCopyBlock (after): [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 fgMorphTree BB04, STMT00316 (after) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 fgMorphTree BB04, STMT00317 (before) [001487] -A--------- * ASG int [001486] D------N--- +--* LCL_VAR int V43 tmp3 [001482] ----------- \--* CNS_INT int 1 GenTreeNode creates assertion: [001487] -A---+----- * ASG int In BB04 New Local Constant Assertion: V43 == 1, index = #04 Morphing BB05 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB05, STMT00006 (before) [000023] -A--------- * ASG struct (copy) [000022] D------N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000020] ----------- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 MorphCopyBlock: MorphBlock for dst tree, before: [000022] D----+-N--- * LCL_VAR struct(P) V42 tmp2 * byref V42.:_reference (offs=0x00) -> V149 tmp109 * int V42.:_length (offs=0x08) -> V150 tmp110 MorphBlock after: [000022] D----+-N--- * LCL_VAR struct(P) V42 tmp2 * byref V42.:_reference (offs=0x00) -> V149 tmp109 * int V42.:_length (offs=0x08) -> V150 tmp110 PrepareDst for [000022] have found a local var V42. MorphBlock for src tree, before: [000020] -----+----- * LCL_VAR struct(P) V41 tmp1 * byref V41.:_reference (offs=0x00) -> V147 tmp107 * int V41.:_length (offs=0x08) -> V148 tmp108 MorphBlock after: [000020] -----+----- * LCL_VAR struct(P) V41 tmp1 * byref V41.:_reference (offs=0x00) -> V147 tmp107 * int V41.:_length (offs=0x08) -> V148 tmp108 GenTreeNode creates assertion: [000023] -A--------- * ASG struct (copy) In BB05 New Local Copy Assertion: V42 == V41, index = #01 block assignment to morph: [000023] -A--------- * ASG struct (copy) [000022] D----+-N--- +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000020] -----+----- \--* LCL_VAR struct(P) V41 tmp1 \--* byref V41.:_reference (offs=0x00) -> V147 tmp107 \--* int V41.:_length (offs=0x08) -> V148 tmp108 (m_dstDoFldAsg=true) (m_srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [002589] -A--------- * ASG byref In BB05 New Local Copy Assertion: V149 == V147, index = #02 GenTreeNode creates assertion: [002592] -A--------- * ASG int In BB05 New Local Copy Assertion: V150 == V148, index = #03 MorphCopyBlock (after): [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 fgMorphTree BB05, STMT00006 (after) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 fgMorphTree BB05, STMT00007 (before) [000026] -A--------- * ASG int [000025] D------N--- +--* LCL_VAR int V43 tmp3 [000021] ----------- \--* CNS_INT int 2 GenTreeNode creates assertion: [000026] -A---+----- * ASG int In BB05 New Local Constant Assertion: V43 == 2, index = #04 Morphing BB06 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB06, STMT00008 (before) [000034] -AC-G------ * ASG int [000033] D------N--- +--* LCL_VAR int V15 loc11 [000030] --C-G------ \--* CALL r2r_ind int [000032] ----------- arg0 +--* LCL_VAR struct(P) V42 tmp2 +--* byref V42.:_reference (offs=0x00) -> V149 tmp109 +--* int V42.:_length (offs=0x08) -> V150 tmp110 [000029] ----------- arg1 \--* LCL_VAR int V43 tmp3 Initializing arg info for 30.CALL: Args for call [000030] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002594].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[000032].LCL_VAR struct (By value), 2 regs: x0 x1, byteAlignment=8, isStruct] CallArg[[000029].LCL_VAR int (By value), 1 reg: x2, byteAlignment=8] Morphing args for 30.CALL: Sorting the arguments: Deferred argument ('x0'): ( 9, 6) [000032] ----------- * LCL_VAR struct(P) V42 tmp2 * byref V42.:_reference (offs=0x00) -> V149 tmp109 * int V42.:_length (offs=0x08) -> V150 tmp110 Moved to late list Deferred argument ('x2'): [000029] -----+----- * LCL_VAR int V43 tmp3 Moved to late list Deferred argument ('x11'): [002594] H----+----- * CNS_INT(h) long 0x40000000005401e8 ftn Moved to late list Register placement order: x0 x2 x11 Multireg struct argument V42 : CallArg[[000032].LCL_VAR struct (By value), 2 regs: x0 x1, byteAlignment=8, isLate, processed, isStruct] fgMorphMultiregStructArg created tree: [002595] -c--------- * FIELD_LIST struct [002596] ----------- ofs 0 +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 \--* LCL_VAR int V150 tmp110 Args for [000030].CALL after fgMorphArgs: CallArg[[002594].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002595].FIELD_LIST struct (By value), 2 regs: x0 x1, byteAlignment=8, isLate, processed, isStruct] CallArg[[000029].LCL_VAR int (By value), 1 reg: x2, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB06, STMT00008 (after) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn Morphing BB07 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB07, STMT00009 (before) [000037] -A--------- * ASG int [000036] D------N--- +--* LCL_VAR int V04 loc0 [000035] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000037] -A---+----- * ASG int In BB07 New Local Constant Assertion: V04 == 0, index = #01 fgMorphTree BB07, STMT00010 (before) [000040] -A--------- * ASG int [000039] D------N--- +--* LCL_VAR int V05 loc1 [000038] ----------- \--* CNS_INT int -1 GenTreeNode creates assertion: [000040] -A---+----- * ASG int In BB07 New Local Constant Assertion: V05 == -1, index = #02 fgMorphTree BB07, STMT00011 (before) [000043] -A--------- * ASG int [000042] D------N--- +--* LCL_VAR int V06 loc2 [000041] ----------- \--* CNS_INT int 0x7FFFFFFF GenTreeNode creates assertion: [000043] -A---+----- * ASG int In BB07 New Local Constant Assertion: V06 == 2147483647, index = #03 fgMorphTree BB07, STMT00012 (before) [000046] -A--------- * ASG int [000045] D------N--- +--* LCL_VAR int V07 loc3 [000044] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000046] -A---+----- * ASG int In BB07 New Local Constant Assertion: V07 == 0, index = #04 fgMorphTree BB07, STMT00013 (before) [000049] -A--------- * ASG int [000048] D------N--- +--* LCL_VAR int V09 loc5 [000047] ----------- \--* CNS_INT int 0 Folding operator with constant nodes into a constant: [002598] ----------- * CAST int <- bool <- int [000047] -----+----- \--* CNS_INT int 0 Bashed to int constant: [002598] ----------- * CNS_INT int 0 GenTreeNode creates assertion: [000049] -A---+----- * ASG int In BB07 New Local Constant Assertion: V09 == 0, index = #05 fgMorphTree BB07, STMT00014 (before) [000052] -A--------- * ASG int [000051] D------N--- +--* LCL_VAR int V10 loc6 [000050] ----------- \--* CNS_INT int -1 GenTreeNode creates assertion: [000052] -A---+----- * ASG int In BB07 New Local Constant Assertion: V10 == -1, index = #06 fgMorphTree BB07, STMT00015 (before) [000055] -A--------- * ASG int [000054] D------N--- +--* LCL_VAR int V12 loc8 [000053] ----------- \--* CNS_INT int 0 Folding operator with constant nodes into a constant: [002599] ----------- * CAST int <- bool <- int [000053] -----+----- \--* CNS_INT int 0 Bashed to int constant: [002599] ----------- * CNS_INT int 0 GenTreeNode creates assertion: [000055] -A---+----- * ASG int In BB07 New Local Constant Assertion: V12 == 0, index = #07 fgMorphTree BB07, STMT00016 (before) [000058] -A--------- * ASG int [000057] D------N--- +--* LCL_VAR int V13 loc9 [000056] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000058] -A---+----- * ASG int In BB07 New Local Constant Assertion: V13 == 0, index = #08 fgMorphTree BB07, STMT00017 (before) [000061] -A--------- * ASG int [000060] D------N--- +--* LCL_VAR int V16 loc12 [000059] ----------- \--* LCL_VAR int V15 loc11 GenTreeNode creates assertion: [000061] -A---+----- * ASG int In BB07 New Local Copy Assertion: V16 == V15, index = #09 fgMorphTree BB07, STMT00321 (before) [001514] -A--------- * ASG struct (copy) [001513] D------N--- +--* LCL_VAR struct(P) V77 tmp37 +--* byref V77.:_reference (offs=0x00) -> V157 tmp117 +--* int V77.:_length (offs=0x08) -> V158 tmp118 [000065] ----------- \--* LCL_VAR struct V02 arg2 MorphCopyBlock: MorphBlock for dst tree, before: [001513] D----+-N--- * LCL_VAR struct(P) V77 tmp37 * byref V77.:_reference (offs=0x00) -> V157 tmp117 * int V77.:_length (offs=0x08) -> V158 tmp118 MorphBlock after: [001513] D----+-N--- * LCL_VAR struct(P) V77 tmp37 * byref V77.:_reference (offs=0x00) -> V157 tmp117 * int V77.:_length (offs=0x08) -> V158 tmp118 PrepareDst for [001513] have found a local var V77. MorphBlock for src tree, before: [000065] -----+----- * LCL_VAR struct V02 arg2 MorphBlock after: [000065] -----+----- * LCL_VAR struct V02 arg2 GenTreeNode creates assertion: [001514] -A--------- * ASG struct (copy) In BB07 New Local Copy Assertion: V77 == V02, index = #10 block assignment to morph: [001514] -A--------- * ASG struct (copy) [001513] D----+-N--- +--* LCL_VAR struct(P) V77 tmp37 +--* byref V77.:_reference (offs=0x00) -> V157 tmp117 +--* int V77.:_length (offs=0x08) -> V158 tmp118 [000065] -----+----- \--* LCL_VAR struct V02 arg2 (m_dstDoFldAsg=true) using field by field assignments. Local V02 should not be enregistered because: was accessed as a local field Local V02 should not be enregistered because: was accessed as a local field MorphCopyBlock (after): [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] fgMorphTree BB07, STMT00321 (after) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] fgMorphTree BB07, STMT00019 (before) [000068] -A--------- * ASG byref [000067] D------N--- +--* LCL_VAR byref V23 loc19 [001512] ----------- \--* LCL_VAR byref V157 tmp117 GenTreeNode creates assertion: [000068] -A---+----- * ASG byref In BB07 New Local Copy Assertion: V23 == V157, index = #11 fgMorphTree BB07, STMT00020 (before) [000072] -A--------- * ASG long [000071] D------N--- +--* LCL_VAR long V22 loc18 [000070] ---------U- \--* CAST long <- ulong <- byref [000069] ----------- \--* LCL_VAR byref V23 loc19 lvaGrabTemp returning 168 (V168 tmp128) called for Cast away GC. Assertion prop in BB07: Copy Assertion: V23 == V157, index = #11 [000069] ----------- * LCL_VAR byref V157 tmp117 GenTreeNode creates assertion: [000072] -A---+----- * ASG long In BB07 New Local Copy Assertion: V22 == V168, index = #12 fgMorphTree BB07, STMT00020 (after) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 Morphing BB08 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB08, STMT00266 (before) [001229] ----------- * JTRUE void [001228] N--------U- \--* GT int [001226] ----------- +--* LCL_VAR int V18 loc14 [001227] ----------- \--* CNS_INT int 69 Morphing BB09 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB09, STMT00289 (before) [001364] ----------- * SWITCH void [001363] ----------- \--* SUB int [001361] ----------- +--* LCL_VAR int V18 loc14 [001362] ----------- \--* CNS_INT int 34 fgMorphTree BB09, STMT00289 (after) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 Morphing BB10 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB10, STMT00290 (before) [001368] ----------- * SWITCH void [001367] ----------- \--* SUB int [001365] ----------- +--* LCL_VAR int V18 loc14 [001366] ----------- \--* CNS_INT int 44 fgMorphTree BB10, STMT00290 (after) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 Morphing BB11 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB11, STMT00291 (before) [001372] ----------- * JTRUE void [001371] ----------- \--* EQ int [001369] ----------- +--* LCL_VAR int V18 loc14 [001370] ----------- \--* CNS_INT int 69 Morphing BB12 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' Morphing BB13 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB13, STMT00267 (before) [001233] ----------- * JTRUE void [001232] ----------- \--* EQ int [001230] ----------- +--* LCL_VAR int V18 loc14 [001231] ----------- \--* CNS_INT int 92 Morphing BB14 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB14, STMT00272 (before) [001260] ----------- * JTRUE void [001259] ----------- \--* EQ int [001257] ----------- +--* LCL_VAR int V18 loc14 [001258] ----------- \--* CNS_INT int 101 Morphing BB15 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB15, STMT00287 (before) [001355] ----------- * JTRUE void [001354] ----------- \--* NE int [001352] ----------- +--* LCL_VAR int V18 loc14 [001353] ----------- \--* CNS_INT int 0x2030 Morphing BB31 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB31, STMT00288 (before) [001360] -A--------- * ASG int [001359] D------N--- +--* LCL_VAR int V13 loc9 [001358] ----------- \--* ADD int [001356] ----------- +--* LCL_VAR int V13 loc9 [001357] ----------- \--* CNS_INT int 3 Morphing BB17 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB17, STMT00307 (before) [001434] -A--------- * ASG int [001433] D------N--- +--* LCL_VAR int V04 loc0 [001432] ----------- \--* ADD int [001430] ----------- +--* LCL_VAR int V04 loc0 [001431] ----------- \--* CNS_INT int 1 Morphing BB18 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB18, STMT00292 (before) [001376] ----------- * JTRUE void [001375] N--------U- \--* NE int [001373] ----------- +--* LCL_VAR int V06 loc2 [001374] ----------- \--* CNS_INT int 0x7FFFFFFF Morphing BB19 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB19, STMT00295 (before) [001387] -A--------- * ASG int [001386] D------N--- +--* LCL_VAR int V06 loc2 [001385] ----------- \--* LCL_VAR int V04 loc0 GenTreeNode creates assertion: [001387] -A---+----- * ASG int In BB19 New Local Copy Assertion: V06 == V04, index = #01 Morphing BB20 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB20, STMT00293 (before) [001381] -A--------- * ASG int [001380] D------N--- +--* LCL_VAR int V04 loc0 [001379] ----------- \--* ADD int [001377] ----------- +--* LCL_VAR int V04 loc0 [001378] ----------- \--* CNS_INT int 1 fgMorphTree BB20, STMT00294 (before) [001384] -A--------- * ASG int [001383] D------N--- +--* LCL_VAR int V07 loc3 [001382] ----------- \--* LCL_VAR int V04 loc0 GenTreeNode creates assertion: [001384] -A---+----- * ASG int In BB20 New Local Copy Assertion: V07 == V04, index = #01 Morphing BB21 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB21, STMT00296 (before) [001391] ----------- * JTRUE void [001390] ----------- \--* GE int [001388] ----------- +--* LCL_VAR int V05 loc1 [001389] ----------- \--* CNS_INT int 0 Morphing BB22 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB22, STMT00297 (before) [001394] -A--------- * ASG int [001393] D------N--- +--* LCL_VAR int V05 loc1 [001392] ----------- \--* LCL_VAR int V04 loc0 GenTreeNode creates assertion: [001394] -A---+----- * ASG int In BB22 New Local Copy Assertion: V05 == V04, index = #01 Morphing BB23 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB23, STMT00298 (before) [001398] ----------- * JTRUE void [001397] ----------- \--* LE int [001395] ----------- +--* LCL_VAR int V04 loc0 [001396] ----------- \--* CNS_INT int 0 Morphing BB24 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB24, STMT00299 (before) [001402] ----------- * JTRUE void [001401] ----------- \--* GE int [001399] ----------- +--* LCL_VAR int V05 loc1 [001400] ----------- \--* CNS_INT int 0 Morphing BB25 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB25, STMT00300 (before) [001406] ----------- * JTRUE void [001405] ----------- \--* LT int [001403] ----------- +--* LCL_VAR int V10 loc6 [001404] ----------- \--* CNS_INT int 0 Morphing BB26 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB26, STMT00303 (before) [001416] ----------- * JTRUE void [001415] N--------U- \--* NE int [001413] ----------- +--* LCL_VAR int V10 loc6 [001414] ----------- \--* LCL_VAR int V04 loc0 Morphing BB27 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB27, STMT00305 (before) [001424] -A--------- * ASG int [001423] D------N--- +--* LCL_VAR int V11 loc7 [001422] ----------- \--* ADD int [001420] ----------- +--* LCL_VAR int V11 loc7 [001421] ----------- \--* CNS_INT int 1 Morphing BB28 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB28, STMT00304 (before) [001419] -A--------- * ASG int [001418] D------N--- +--* LCL_VAR int V12 loc8 [001417] ----------- \--* CNS_INT int 1 Folding operator with constant nodes into a constant: [002612] ----------- * CAST int <- bool <- int [001417] -----+----- \--* CNS_INT int 1 Bashed to int constant: [002612] ----------- * CNS_INT int 1 GenTreeNode creates assertion: [001419] -A---+----- * ASG int In BB28 New Local Constant Assertion: V12 == 1, index = #01 Morphing BB29 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB29, STMT00301 (before) [001409] -A--------- * ASG int [001408] D------N--- +--* LCL_VAR int V10 loc6 [001407] ----------- \--* LCL_VAR int V04 loc0 GenTreeNode creates assertion: [001409] -A---+----- * ASG int In BB29 New Local Copy Assertion: V10 == V04, index = #01 fgMorphTree BB29, STMT00302 (before) [001412] -A--------- * ASG int [001411] D------N--- +--* LCL_VAR int V11 loc7 [001410] ----------- \--* CNS_INT int 1 GenTreeNode creates assertion: [001412] -A---+----- * ASG int In BB29 New Local Constant Assertion: V11 == 1, index = #02 Morphing BB30 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB30, STMT00306 (before) [001429] -A--------- * ASG int [001428] D------N--- +--* LCL_VAR int V13 loc9 [001427] ----------- \--* ADD int [001425] ----------- +--* LCL_VAR int V13 loc9 [001426] ----------- \--* CNS_INT int 2 Morphing BB32 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB32, STMT00309 (before) [001441] --C-------- * JTRUE void [001440] --C-------- \--* GE int [001435] ----------- +--* LCL_VAR int V16 loc12 [001518] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB33 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB33, STMT00310 (before) [001452] ---XG------ * JTRUE void [001451] ---XG------ \--* EQ int [001449] ---XG------ +--* IND ushort [001448] ----------- | \--* ADD long [001442] ----------- | +--* LCL_VAR long V22 loc18 [001447] ----------- | \--* MUL long [001444] ----------- | +--* CAST long <- int [001443] ----------- | | \--* LCL_VAR int V16 loc12 [001446] ----------- | \--* CAST long <- int [001445] ----------- | \--* CNS_INT int 2 [001450] ----------- \--* CNS_INT int 0 Folding long operator with constant nodes into a constant: [001446] ----------- * CAST long <- int [001445] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001446] ----------- * CNS_INT long 2 fgMorphTree BB33, STMT00310 (after) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 Morphing BB34 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB34, STMT00312 (before) [001461] -A--------- * ASG int [001460] D------N--- +--* LCL_VAR int V74 tmp34 [001454] ----------- \--* LCL_VAR int V16 loc12 GenTreeNode creates assertion: [001461] -A---+----- * ASG int In BB34 New Local Copy Assertion: V74 == V16, index = #01 fgMorphTree BB34, STMT00311 (before) [001459] -A--------- * ASG int [001458] D------N--- +--* LCL_VAR int V16 loc12 [001457] ----------- \--* ADD int [001455] ----------- +--* LCL_VAR int V16 loc12 [001456] ----------- \--* CNS_INT int 1 The assignment [001459] using V74 removes: Copy Assertion: V74 == V16 fgMorphTree BB34, STMT00313 (before) [001471] ---XG------ * JTRUE void [001470] N--XG----U- \--* NE int [001468] ---XG------ +--* IND ushort [001467] ----------- | \--* ADD long [001453] ----------- | +--* LCL_VAR long V22 loc18 [001466] ----------- | \--* MUL long [001463] ----------- | +--* CAST long <- int [001462] ----------- | | \--* LCL_VAR int V74 tmp34 [001465] ----------- | \--* CAST long <- int [001464] ----------- | \--* CNS_INT int 2 [001469] ----------- \--* LCL_VAR int V18 loc14 Folding long operator with constant nodes into a constant: [001465] ----------- * CAST long <- int [001464] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001465] ----------- * CNS_INT long 2 fgMorphTree BB34, STMT00313 (after) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 Morphing BB35 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' Morphing BB36 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB36, STMT00269 (before) [001240] --C-------- * JTRUE void [001239] --C-------- \--* GE int [001234] ----------- +--* LCL_VAR int V16 loc12 [001522] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB37 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB37, STMT00270 (before) [001251] ---XG------ * JTRUE void [001250] ---XG------ \--* EQ int [001248] ---XG------ +--* IND ushort [001247] ----------- | \--* ADD long [001241] ----------- | +--* LCL_VAR long V22 loc18 [001246] ----------- | \--* MUL long [001243] ----------- | +--* CAST long <- int [001242] ----------- | | \--* LCL_VAR int V16 loc12 [001245] ----------- | \--* CAST long <- int [001244] ----------- | \--* CNS_INT int 2 [001249] ----------- \--* CNS_INT int 0 Folding long operator with constant nodes into a constant: [001245] ----------- * CAST long <- int [001244] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001245] ----------- * CNS_INT long 2 fgMorphTree BB37, STMT00270 (after) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 Morphing BB38 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB38, STMT00271 (before) [001256] -A--------- * ASG int [001255] D------N--- +--* LCL_VAR int V16 loc12 [001254] ----------- \--* ADD int [001252] ----------- +--* LCL_VAR int V16 loc12 [001253] ----------- \--* CNS_INT int 1 Morphing BB39 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB39, STMT00274 (before) [001267] --C-------- * JTRUE void [001266] --C-------- \--* GE int [001261] ----------- +--* LCL_VAR int V16 loc12 [001526] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB40 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB40, STMT00286 (before) [001351] ---XG------ * JTRUE void [001350] ---XG------ \--* EQ int [001348] ---XG------ +--* IND ushort [001347] ----------- | \--* ADD long [001341] ----------- | +--* LCL_VAR long V22 loc18 [001346] ----------- | \--* MUL long [001343] ----------- | +--* CAST long <- int [001342] ----------- | | \--* LCL_VAR int V16 loc12 [001345] ----------- | \--* CAST long <- int [001344] ----------- | \--* CNS_INT int 2 [001349] ----------- \--* CNS_INT int 48 Folding long operator with constant nodes into a constant: [001345] ----------- * CAST long <- int [001344] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001345] ----------- * CNS_INT long 2 fgMorphTree BB40, STMT00286 (after) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 Morphing BB41 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB41, STMT00276 (before) [001276] --C-------- * JTRUE void [001275] --C-------- \--* GE int [001270] ----------- +--* ADD int [001268] ----------- | +--* LCL_VAR int V16 loc12 [001269] ----------- | \--* CNS_INT int 1 [001530] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB42 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB42, STMT00277 (before) [001287] ---XG------ * JTRUE void [001286] ---XG------ \--* EQ int [001284] ---XG------ +--* IND ushort [001283] ----------- | \--* ADD long [001277] ----------- | +--* LCL_VAR long V22 loc18 [001282] ----------- | \--* MUL long [001279] ----------- | +--* CAST long <- int [001278] ----------- | | \--* LCL_VAR int V16 loc12 [001281] ----------- | \--* CAST long <- int [001280] ----------- | \--* CNS_INT int 2 [001285] ----------- \--* CNS_INT int 43 Folding long operator with constant nodes into a constant: [001281] ----------- * CAST long <- int [001280] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001281] ----------- * CNS_INT long 2 fgMorphTree BB42, STMT00277 (after) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 Morphing BB43 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB43, STMT00285 (before) [001340] ---XG------ * JTRUE void [001339] N--XG----U- \--* NE int [001337] ---XG------ +--* IND ushort [001336] ----------- | \--* ADD long [001330] ----------- | +--* LCL_VAR long V22 loc18 [001335] ----------- | \--* MUL long [001332] ----------- | +--* CAST long <- int [001331] ----------- | | \--* LCL_VAR int V16 loc12 [001334] ----------- | \--* CAST long <- int [001333] ----------- | \--* CNS_INT int 2 [001338] ----------- \--* CNS_INT int 45 Folding long operator with constant nodes into a constant: [001334] ----------- * CAST long <- int [001333] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001334] ----------- * CNS_INT long 2 fgMorphTree BB43, STMT00285 (after) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 Morphing BB44 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB44, STMT00278 (before) [001300] ---XG------ * JTRUE void [001299] N--XG----U- \--* NE int [001297] ---XG------ +--* IND ushort [001296] ----------- | \--* ADD long [001288] ----------- | +--* LCL_VAR long V22 loc18 [001295] ----------- | \--* MUL long [001292] ----------- | +--* CAST long <- int [001291] ----------- | | \--* ADD int [001289] ----------- | | +--* LCL_VAR int V16 loc12 [001290] ----------- | | \--* CNS_INT int 1 [001294] ----------- | \--* CAST long <- int [001293] ----------- | \--* CNS_INT int 2 [001298] ----------- \--* CNS_INT int 48 Folding long operator with constant nodes into a constant: [001294] ----------- * CAST long <- int [001293] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001294] ----------- * CNS_INT long 2 fgMorphTree BB44, STMT00278 (after) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 Morphing BB45 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB45, STMT00279 (before) [001305] -A--------- * ASG int [001304] D------N--- +--* LCL_VAR int V73 tmp33 [001303] ----------- \--* ADD int [001301] ----------- +--* LCL_VAR int V16 loc12 [001302] ----------- \--* CNS_INT int 1 fgMorphTree BB45, STMT00280 (before) [001309] -A--------- * ASG int [001308] D------N--- +--* LCL_VAR int V16 loc12 [001307] ----------- \--* LCL_VAR int V73 tmp33 GenTreeNode creates assertion: [001309] -A---+----- * ASG int In BB45 New Local Copy Assertion: V16 == V73, index = #01 fgMorphTree BB45, STMT00282 (before) [001315] --C-------- * JTRUE void [001314] --C-------- \--* GE int [001306] ----------- +--* LCL_VAR int V73 tmp33 [001534] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB46 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB46, STMT00284 (before) [001329] ---XG------ * JTRUE void [001328] ---XG------ \--* EQ int [001326] ---XG------ +--* IND ushort [001325] ----------- | \--* ADD long [001319] ----------- | +--* LCL_VAR long V22 loc18 [001324] ----------- | \--* MUL long [001321] ----------- | +--* CAST long <- int [001320] ----------- | | \--* LCL_VAR int V16 loc12 [001323] ----------- | \--* CAST long <- int [001322] ----------- | \--* CNS_INT int 2 [001327] ----------- \--* CNS_INT int 48 Folding long operator with constant nodes into a constant: [001323] ----------- * CAST long <- int [001322] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001323] ----------- * CNS_INT long 2 fgMorphTree BB46, STMT00284 (after) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 Morphing BB47 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB47, STMT00283 (before) [001318] -A--------- * ASG int [001317] D------N--- +--* LCL_VAR int V09 loc5 [001316] ----------- \--* CNS_INT int 1 Folding operator with constant nodes into a constant: [002613] ----------- * CAST int <- bool <- int [001316] -----+----- \--* CNS_INT int 1 Bashed to int constant: [002613] ----------- * CNS_INT int 1 GenTreeNode creates assertion: [001318] -A---+----- * ASG int In BB47 New Local Constant Assertion: V09 == 1, index = #01 Morphing BB48 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB48, STMT00022 (before) [000079] --C-------- * JTRUE void [000078] --C-------- \--* GE int [000073] ----------- +--* LCL_VAR int V16 loc12 [001538] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB49 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB49, STMT00261 (before) [001205] -A--------- * ASG int [001204] D------N--- +--* LCL_VAR int V71 tmp31 [001198] ----------- \--* LCL_VAR int V16 loc12 GenTreeNode creates assertion: [001205] -A---+----- * ASG int In BB49 New Local Copy Assertion: V71 == V16, index = #01 fgMorphTree BB49, STMT00260 (before) [001203] -A--------- * ASG int [001202] D------N--- +--* LCL_VAR int V16 loc12 [001201] ----------- \--* ADD int [001199] ----------- +--* LCL_VAR int V16 loc12 [001200] ----------- \--* CNS_INT int 1 The assignment [001203] using V71 removes: Copy Assertion: V71 == V16 fgMorphTree BB49, STMT00262 (before) [001214] -A-XG------ * ASG int [001213] D------N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG------ \--* IND ushort [001211] ----------- \--* ADD long [001197] ----------- +--* LCL_VAR long V22 loc18 [001210] ----------- \--* MUL long [001207] ----------- +--* CAST long <- int [001206] ----------- | \--* LCL_VAR int V71 tmp31 [001209] ----------- \--* CAST long <- int [001208] ----------- \--* CNS_INT int 2 Folding long operator with constant nodes into a constant: [001209] ----------- * CAST long <- int [001208] -----+----- \--* CNS_INT int 2 Bashed to long constant: [001209] ----------- * CNS_INT long 2 GenTreeNode creates assertion: [001214] -A-XG+----- * ASG int In BB49 New Local Subrange Assertion: V72 in [0..65535], index = #01 fgMorphTree BB49, STMT00262 (after) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 fgMorphTree BB49, STMT00263 (before) [001218] -A--------- * ASG int [001217] D------N--- +--* LCL_VAR int V18 loc14 [001216] ----------- \--* LCL_VAR int V72 tmp32 Subrange prop for index #01 in BB49: [002614] ----------- * CAST int <- ushort <- int fgMorphTree BB49, STMT00264 (before) [001221] ----------- * JTRUE void [001220] ----------- \--* EQ int [001215] ----------- +--* LCL_VAR int V72 tmp32 [001219] ----------- \--* CNS_INT int 0 Morphing BB50 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB50, STMT00265 (before) [001225] ----------- * JTRUE void [001224] N--------U- \--* NE int [001222] ----------- +--* LCL_VAR int V18 loc14 [001223] ----------- \--* CNS_INT int 59 Morphing BB51 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB51, STMT00023 (before) [000083] -A--------- * ASG byref [000082] D------N--- +--* LCL_VAR byref V23 loc19 [000081] ----------- \--* CNS_INT long 0 GenTreeNode creates assertion: [000083] -A---+----- * ASG byref In BB51 New Local Constant Assertion: V23 == 0, index = #01 fgMorphTree BB51, STMT00024 (before) [000087] ----------- * JTRUE void [000086] ----------- \--* GE int [000084] ----------- +--* LCL_VAR int V05 loc1 [000085] ----------- \--* CNS_INT int 0 Morphing BB52 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB52, STMT00259 (before) [001196] -A--------- * ASG int [001195] D------N--- +--* LCL_VAR int V05 loc1 [001194] ----------- \--* LCL_VAR int V04 loc0 GenTreeNode creates assertion: [001196] -A---+----- * ASG int In BB52 New Local Copy Assertion: V05 == V04, index = #01 Morphing BB53 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB53, STMT00025 (before) [000091] ----------- * JTRUE void [000090] ----------- \--* LT int [000088] ----------- +--* LCL_VAR int V10 loc6 [000089] ----------- \--* CNS_INT int 0 Morphing BB54 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB54, STMT00256 (before) [001183] ----------- * JTRUE void [001182] N--------U- \--* NE int [001180] ----------- +--* LCL_VAR int V10 loc6 [001181] ----------- \--* LCL_VAR int V05 loc1 Morphing BB55 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB55, STMT00258 (before) [001193] -A--------- * ASG int [001192] D------N--- +--* LCL_VAR int V13 loc9 [001191] ----------- \--* SUB int [001187] ----------- +--* LCL_VAR int V13 loc9 [001190] ----------- \--* MUL int [001188] ----------- +--* LCL_VAR int V11 loc7 [001189] ----------- \--* CNS_INT int 3 Morphing BB56 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB56, STMT00257 (before) [001186] -A--------- * ASG int [001185] D------N--- +--* LCL_VAR int V12 loc8 [001184] ----------- \--* CNS_INT int 1 Folding operator with constant nodes into a constant: [002615] ----------- * CAST int <- bool <- int [001184] -----+----- \--* CNS_INT int 1 Bashed to int constant: [002615] ----------- * CNS_INT int 1 GenTreeNode creates assertion: [001186] -A---+----- * ASG int In BB56 New Local Constant Assertion: V12 == 1, index = #01 Morphing BB57 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB57, STMT00026 (before) [000096] ---XG------ * JTRUE void [000095] ---XG------ \--* EQ int [000093] ---XG------ +--* IND ubyte [000092] ----------- | \--* LCL_VAR long V17 loc13 [000094] ----------- \--* CNS_INT int 0 Morphing BB58 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB58, STMT00245 (before) [001129] -A-XG------ * ASG byref [001128] D------N--- +--* LCL_VAR byref V69 tmp29 [001127] ---XG------ \--* FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 Before explicit null check morphing: [001127] ---XG------ * FIELD_ADDR byref : [001126] ----------- \--* LCL_VAR byref V01 arg1 After adding explicit null check: [002621] ---X-O----- * COMMA byref [002617] ---X-O----- +--* NULLCHECK byte [002616] ----------- | \--* LCL_VAR byref V01 arg1 [002620] -----O----- \--* ADD byref [002618] -----O----- +--* LCL_VAR byref V01 arg1 [002619] ----------- \--* CNS_INT long 4 Final value of Compiler::fgMorphField after morphing: [002621] ---X-+-N--- * COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 fgMorphTree BB58, STMT00245 (after) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 fgMorphTree BB58, STMT00246 (before) [001136] -A-XG------ * ASG int [001135] ---XG--N--- +--* IND int [001130] ----------- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG------ \--* ADD int [001132] ---XG------ +--* IND int [001131] ----------- | \--* LCL_VAR byref V69 tmp29 [001133] ----------- \--* LCL_VAR int V13 loc9 fgMorphTree BB58, STMT00247 (before) [001140] ----------- * JTRUE void [001139] ----------- \--* NE int [001137] ----------- +--* LCL_VAR int V09 loc5 [001138] ----------- \--* CNS_INT int 0 Morphing BB59 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB59, STMT00255 (before) [001178] -A-XG------ * ASG int [001177] D------N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG------ \--* SUB int [001174] ---XG------ +--* ADD int [001172] ---XG------ | +--* FIELD int : [001171] ----------- | | \--* LCL_VAR byref V01 arg1 [001173] ----------- | \--* LCL_VAR int V04 loc0 [001175] ----------- \--* LCL_VAR int V05 loc1 Final value of Compiler::fgMorphField after morphing: [001172] ---XG------ * IND int [002623] -----+----- \--* ADD byref [001171] -----+----- +--* LCL_VAR byref V01 arg1 [002622] -----+----- \--* CNS_INT long 4 fgMorphTree BB59, STMT00255 (after) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 Morphing BB60 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB60, STMT00248 (before) [001143] -A--------- * ASG int [001142] D------N--- +--* LCL_VAR int V70 tmp30 [001141] ----------- \--* LCL_VAR int V04 loc0 GenTreeNode creates assertion: [001143] -A---+----- * ASG int In BB60 New Local Copy Assertion: V70 == V04, index = #01 Morphing BB61 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB61, STMT00250 (before) [001151] --CXG------ * CALL r2r_ind void [001148] ----------- arg0 +--* LCL_VAR byref V01 arg1 [001145] ----------- arg1 +--* LCL_VAR int V70 tmp30 [001150] ----------- arg2 \--* CNS_INT int 0 Initializing arg info for 1151.CALL: Args for call [001151] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002624].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[001148].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8] CallArg[[001145].LCL_VAR int (By value), 1 reg: x1, byteAlignment=8] CallArg[[001150].CNS_INT bool (By value), 1 reg: x2, byteAlignment=8] Morphing args for 1151.CALL: Sorting the arguments: Deferred argument ('x1'): [001145] -----+----- * LCL_VAR int V70 tmp30 Moved to late list Deferred argument ('x0'): [001148] -----+----- * LCL_VAR byref V01 arg1 Moved to late list Deferred argument ('x11'): [002624] H----+----- * CNS_INT(h) long 0x400000000046acb8 ftn Moved to late list Deferred argument ('x2'): [001150] -----+----- * CNS_INT int 0 Moved to late list Register placement order: x1 x0 x11 x2 Args for [001151].CALL after fgMorphArgs: CallArg[[002624].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[001148].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed] CallArg[[001145].LCL_VAR int (By value), 1 reg: x1, byteAlignment=8, isLate, processed] CallArg[[001150].CNS_INT bool (By value), 1 reg: x2, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB61, STMT00250 (after) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 fgMorphTree BB61, STMT00251 (before) [001156] ---XG------ * JTRUE void [001155] ---XG------ \--* NE int [001153] ---XG------ +--* IND ubyte [001152] ----------- | \--* LCL_VAR long V17 loc13 [001154] ----------- \--* CNS_INT int 0 Morphing BB62 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB62, STMT00252 (before) [001163] -AC-G------ * ASG int [001162] D------N--- +--* LCL_VAR int V16 loc12 [001159] --C-G------ \--* CALL r2r_ind int [001161] ----------- arg0 +--* LCL_VAR struct V02 arg2 [001158] ----------- arg1 \--* CNS_INT int 2 Initializing arg info for 1159.CALL: Args for call [001159] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002625].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[001161].LCL_VAR struct (By value), 2 regs: x0 x1, byteAlignment=8, isStruct] CallArg[[001158].CNS_INT int (By value), 1 reg: x2, byteAlignment=8] Morphing args for 1159.CALL: Sorting the arguments: Deferred argument ('x0'): ( 9, 6) [001161] ----------- * LCL_VAR struct V02 arg2 Moved to late list Deferred argument ('x11'): [002625] H----+----- * CNS_INT(h) long 0x40000000005401e8 ftn Moved to late list Deferred argument ('x2'): [001158] -----+----- * CNS_INT int 2 Moved to late list Register placement order: x0 x11 x2 Multireg struct argument V02 : CallArg[[001161].LCL_VAR struct (By value), 2 regs: x0 x1, byteAlignment=8, isLate, processed, isStruct] Local V02 should not be enregistered because: was accessed as a local field fgMorphMultiregStructArg created tree: [002626] -c--------- * FIELD_LIST struct [002627] ----------- ofs 0 +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 \--* LCL_FLD long V02 arg2 [+8] Args for [001159].CALL after fgMorphArgs: CallArg[[002625].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002626].FIELD_LIST struct (By value), 2 regs: x0 x1, byteAlignment=8, isLate, processed, isStruct] CallArg[[001158].CNS_INT int (By value), 1 reg: x2, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB62, STMT00252 (after) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 fgMorphTree BB62, STMT00253 (before) [001167] ----------- * JTRUE void [001166] ----------- \--* EQ int [001164] ----------- +--* LCL_VAR int V16 loc12 [001165] ----------- \--* LCL_VAR int V15 loc11 Morphing BB63 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB63, STMT00254 (before) [001170] -A--------- * ASG int [001169] D------N--- +--* LCL_VAR int V15 loc11 [001168] ----------- \--* LCL_VAR int V16 loc12 GenTreeNode creates assertion: [001170] -A---+----- * ASG int In BB63 New Local Copy Assertion: V15 == V16, index = #01 Morphing BB64 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB64, STMT00027 (before) [000101] ---XG------ * JTRUE void [000100] ---XG------ \--* EQ int [000098] ---XG------ +--* FIELD ubyte : [000097] ----------- | \--* LCL_VAR byref V01 arg1 [000099] ----------- \--* CNS_INT int 3 Final value of Compiler::fgMorphField after morphing: [000098] ---XG------ * IND ubyte [002630] -----+----- \--* ADD byref [000097] -----+----- +--* LCL_VAR byref V01 arg1 [002629] -----+----- \--* CNS_INT long 10 fgMorphTree BB64, STMT00027 (after) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 Morphing BB65 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB65, STMT00244 (before) [001125] -A-XG------ * ASG bool [001124] ---XG--N--- +--* FIELD bool : [001122] ----------- | \--* LCL_VAR byref V01 arg1 [001123] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [001124] ---XG--N--- * IND bool [002632] -----+----- \--* ADD byref [001122] -----+----- +--* LCL_VAR byref V01 arg1 [002631] -----+----- \--* CNS_INT long 8 fgMorphTree BB65, STMT00244 (after) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 Morphing BB66 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB66, STMT00028 (before) [000105] -A-XG------ * ASG int [000104] ---XG--N--- +--* FIELD int : [000102] ----------- | \--* LCL_VAR byref V01 arg1 [000103] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [000104] ---XG--N--- * IND int [002634] -----+----- \--* ADD byref [000102] -----+----- +--* LCL_VAR byref V01 arg1 [002633] -----+----- \--* CNS_INT long 4 fgMorphTree BB66, STMT00028 (after) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 Morphing BB67 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB67, STMT00029 (before) [000109] ----------- * JTRUE void [000108] ----------- \--* LT int [000106] ----------- +--* LCL_VAR int V06 loc2 [000107] ----------- \--* LCL_VAR int V05 loc1 Morphing BB68 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB68, STMT00243 (before) [001120] -A--------- * ASG int [001119] D------N--- +--* LCL_VAR int V44 tmp4 [001118] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [001120] -A---+----- * ASG int In BB68 New Local Constant Assertion: V44 == 0, index = #01 Morphing BB69 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB69, STMT00030 (before) [000114] -A--------- * ASG int [000113] D------N--- +--* LCL_VAR int V44 tmp4 [000112] ----------- \--* SUB int [000110] ----------- +--* LCL_VAR int V05 loc1 [000111] ----------- \--* LCL_VAR int V06 loc2 Morphing BB70 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB70, STMT00031 (before) [000118] -A--------- * ASG int [000117] D------N--- +--* LCL_VAR int V06 loc2 [000116] ----------- \--* LCL_VAR int V44 tmp4 GenTreeNode creates assertion: [000118] -A---+----- * ASG int In BB70 New Local Copy Assertion: V06 == V44, index = #01 fgMorphTree BB70, STMT00032 (before) [000122] ----------- * JTRUE void [000121] ----------- \--* GT int [000119] ----------- +--* LCL_VAR int V07 loc3 [000120] ----------- \--* LCL_VAR int V05 loc1 Morphing BB71 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB71, STMT00242 (before) [001116] -A--------- * ASG int [001115] D------N--- +--* LCL_VAR int V45 tmp5 [001114] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [001116] -A---+----- * ASG int In BB71 New Local Constant Assertion: V45 == 0, index = #01 Morphing BB72 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB72, STMT00033 (before) [000127] -A--------- * ASG int [000126] D------N--- +--* LCL_VAR int V45 tmp5 [000125] ----------- \--* SUB int [000123] ----------- +--* LCL_VAR int V05 loc1 [000124] ----------- \--* LCL_VAR int V07 loc3 Morphing BB73 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB73, STMT00034 (before) [000131] -A--------- * ASG int [000130] D------N--- +--* LCL_VAR int V07 loc3 [000129] ----------- \--* LCL_VAR int V45 tmp5 GenTreeNode creates assertion: [000131] -A---+----- * ASG int In BB73 New Local Copy Assertion: V07 == V45, index = #01 fgMorphTree BB73, STMT00035 (before) [000135] ----------- * JTRUE void [000134] ----------- \--* EQ int [000132] ----------- +--* LCL_VAR int V09 loc5 [000133] ----------- \--* CNS_INT int 0 Morphing BB74 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB74, STMT00240 (before) [001110] -A--------- * ASG int [001109] D------N--- +--* LCL_VAR int V08 loc4 [001108] ----------- \--* LCL_VAR int V05 loc1 GenTreeNode creates assertion: [001110] -A---+----- * ASG int In BB74 New Local Copy Assertion: V08 == V05, index = #01 fgMorphTree BB74, STMT00241 (before) [001113] -A--------- * ASG int [001112] D------N--- +--* LCL_VAR int V14 loc10 [001111] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [001113] -A---+----- * ASG int In BB74 New Local Constant Assertion: V14 == 0, index = #02 Morphing BB75 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB75, STMT00036 (before) [000140] ---XG------ * JTRUE void [000139] ---XG------ \--* GT int [000137] ---XG------ +--* FIELD int : [000136] ----------- | \--* LCL_VAR byref V01 arg1 [000138] ----------- \--* LCL_VAR int V05 loc1 Final value of Compiler::fgMorphField after morphing: [000137] ---XG------ * IND int [002636] -----+----- \--* ADD byref [000136] -----+----- +--* LCL_VAR byref V01 arg1 [002635] -----+----- \--* CNS_INT long 4 fgMorphTree BB75, STMT00036 (after) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 Morphing BB76 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB76, STMT00239 (before) [001106] -A--------- * ASG int [001105] D------N--- +--* LCL_VAR int V46 tmp6 [001104] ----------- \--* LCL_VAR int V05 loc1 GenTreeNode creates assertion: [001106] -A---+----- * ASG int In BB76 New Local Copy Assertion: V46 == V05, index = #01 Morphing BB77 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB77, STMT00037 (before) [000144] -A-XG------ * ASG int [000143] D------N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG------ \--* FIELD int : [000141] ----------- \--* LCL_VAR byref V01 arg1 Final value of Compiler::fgMorphField after morphing: [000142] ---XG------ * IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 fgMorphTree BB77, STMT00037 (after) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 Morphing BB78 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB78, STMT00038 (before) [000148] -A--------- * ASG int [000147] D------N--- +--* LCL_VAR int V08 loc4 [000146] ----------- \--* LCL_VAR int V46 tmp6 GenTreeNode creates assertion: [000148] -A---+----- * ASG int In BB78 New Local Copy Assertion: V08 == V46, index = #01 fgMorphTree BB78, STMT00039 (before) [000154] -A-XG------ * ASG int [000153] D------N--- +--* LCL_VAR int V14 loc10 [000152] ---XG------ \--* SUB int [000150] ---XG------ +--* FIELD int : [000149] ----------- | \--* LCL_VAR byref V01 arg1 [000151] ----------- \--* LCL_VAR int V05 loc1 Final value of Compiler::fgMorphField after morphing: [000150] ---XG------ * IND int [002640] -----+----- \--* ADD byref [000149] -----+----- +--* LCL_VAR byref V01 arg1 [002639] -----+----- \--* CNS_INT long 4 fgMorphTree BB78, STMT00039 (after) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 Morphing BB79 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB79, STMT00040 (before) [000157] -A--------- * ASG int [000156] D------N--- +--* LCL_VAR int V16 loc12 [000155] ----------- \--* LCL_VAR int V15 loc11 GenTreeNode creates assertion: [000157] -A---+----- * ASG int In BB79 New Local Copy Assertion: V16 == V15, index = #01 fgMorphTree BB79, STMT00041 (before) [000165] IA--------- * ASG struct (init) [000163] D------N--- +--* LCL_VAR struct(P) V48 tmp8 +--* byref V48.:_reference (offs=0x00) -> V151 tmp111 +--* int V48.:_length (offs=0x08) -> V152 tmp112 [000164] ----------- \--* CNS_INT int 0 MorphInitBlock: MorphBlock for dst tree, before: [000163] D----+-N--- * LCL_VAR struct(P) V48 tmp8 * byref V48.:_reference (offs=0x00) -> V151 tmp111 * int V48.:_length (offs=0x08) -> V152 tmp112 MorphBlock after: [000163] D----+-N--- * LCL_VAR struct(P) V48 tmp8 * byref V48.:_reference (offs=0x00) -> V151 tmp111 * int V48.:_length (offs=0x08) -> V152 tmp112 PrepareDst for [000163] have found a local var V48. GenTreeNode creates assertion: [000165] IA--------- * ASG struct (init) In BB79 New Local Constant Assertion: V48 == ZeroObj, index = #02 using field by field initialization. GenTreeNode creates assertion: [002643] -A--------- * ASG byref In BB79 New Local Constant Assertion: V151 == 0, index = #03 GenTreeNode creates assertion: [002646] -A--------- * ASG int In BB79 New Local Constant Assertion: V152 == 0, index = #04 MorphInitBlock (after): [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 fgMorphTree BB79, STMT00041 (after) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 fgMorphTree BB79, STMT00323 (before) [001544] ----------- * NOP void fgMorphTree BB79, STMT00324 (before) [001553] -A--------- * ASG byref [001552] D------N--- +--* LCL_VAR byref V151 tmp111 [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 The assignment [001553] using V151 removes: Constant Assertion: V151 == 0 The assignment [001553] using V48 removes: Constant Assertion: V48 == ZeroObj fgMorphTree BB79, STMT00325 (before) [001558] -A--------- * ASG int [001557] D------N--- +--* LCL_VAR int V152 tmp112 [001556] ----------- \--* CNS_INT int 4 The assignment [001558] using V152 removes: Constant Assertion: V152 == 0 GenTreeNode creates assertion: [001558] -A---+----- * ASG int In BB79 New Local Constant Assertion: V152 == 4, index = #02 fgMorphTree BB79, STMT00044 (before) [000174] -A--------- * ASG struct (copy) [000173] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [000169] ----------- \--* LCL_VAR struct(P) V48 tmp8 \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 \--* int V48.:_length (offs=0x08) -> V152 tmp112 MorphCopyBlock: MorphBlock for dst tree, before: [000173] D----+-N--- * LCL_VAR struct(P) V19 loc15 * byref V19.:_reference (offs=0x00) -> V143 tmp103 * int V19.:_length (offs=0x08) -> V144 tmp104 MorphBlock after: [000173] D----+-N--- * LCL_VAR struct(P) V19 loc15 * byref V19.:_reference (offs=0x00) -> V143 tmp103 * int V19.:_length (offs=0x08) -> V144 tmp104 PrepareDst for [000173] have found a local var V19. MorphBlock for src tree, before: [000169] -----+----- * LCL_VAR struct(P) V48 tmp8 * byref V48.:_reference (offs=0x00) -> V151 tmp111 * int V48.:_length (offs=0x08) -> V152 tmp112 MorphBlock after: [000169] -----+----- * LCL_VAR struct(P) V48 tmp8 * byref V48.:_reference (offs=0x00) -> V151 tmp111 * int V48.:_length (offs=0x08) -> V152 tmp112 GenTreeNode creates assertion: [000174] -A--------- * ASG struct (copy) In BB79 New Local Copy Assertion: V19 == V48, index = #03 block assignment to morph: [000174] -A--------- * ASG struct (copy) [000173] D----+-N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [000169] -----+----- \--* LCL_VAR struct(P) V48 tmp8 \--* byref V48.:_reference (offs=0x00) -> V151 tmp111 \--* int V48.:_length (offs=0x08) -> V152 tmp112 (m_dstDoFldAsg=true) (m_srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [002650] -A--------- * ASG byref In BB79 New Local Copy Assertion: V143 == V151, index = #04 GenTreeNode creates assertion: [002653] -A--------- * ASG int In BB79 New Local Copy Assertion: V144 == V152, index = #05 MorphCopyBlock (after): [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 fgMorphTree BB79, STMT00044 (after) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 fgMorphTree BB79, STMT00045 (before) [000177] -A--------- * ASG int [000176] D------N--- +--* LCL_VAR int V20 loc16 [000175] ----------- \--* CNS_INT int -1 GenTreeNode creates assertion: [000177] -A---+----- * ASG int In BB79 New Local Constant Assertion: V20 == -1, index = #06 fgMorphTree BB79, STMT00046 (before) [000181] ----------- * JTRUE void [000180] ----------- \--* EQ int [000178] ----------- +--* LCL_VAR int V12 loc8 [000179] ----------- \--* CNS_INT int 0 Morphing BB85 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB85, STMT00203 (before) [000947] --CX------- * JTRUE void [000946] --CX------- \--* LE int [000944] --CX------- +--* ARR_LENGTH int [001570] ---XG------ | \--* FIELD ref : [000941] ----------- | \--* LCL_VAR ref V03 arg3 [000945] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [001570] ---XG------ * IND ref [002656] -----+----- \--* ADD byref [000941] -----+----- +--* LCL_VAR ref V03 arg3 [002655] -----+----- \--* CNS_INT long 56 Fseq[] GenTreeNode creates assertion: [001570] ---XG+----- * IND ref In BB85 New Local Constant Assertion: V03 != null, index = #01 fgMorphTree BB85, STMT00203 (after) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 Morphing BB86 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB86, STMT00204 (before) [000951] -A-XG------ * ASG ref [000950] D------N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG------ \--* FIELD ref : [000948] ----------- \--* LCL_VAR ref V03 arg3 Final value of Compiler::fgMorphField after morphing: [000949] ---XG------ * IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] GenTreeNode creates assertion: [000949] ---XG+----- * IND ref In BB86 New Local Constant Assertion: V03 != null, index = #01 fgMorphTree BB86, STMT00204 (after) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] fgMorphTree BB86, STMT00205 (before) [000954] -A--------- * ASG int [000953] D------N--- +--* LCL_VAR int V27 loc23 [000952] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000954] -A---+----- * ASG int In BB86 New Local Constant Assertion: V27 == 0, index = #02 fgMorphTree BB86, STMT00206 (before) [000957] -A--------- * ASG int [000956] D------N--- +--* LCL_VAR int V28 loc24 [000955] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000957] -A---+----- * ASG int In BB86 New Local Constant Assertion: V28 == 0, index = #03 fgMorphTree BB86, STMT00207 (before) [000961] -A-X------- * ASG int [000960] D------N--- +--* LCL_VAR int V29 loc25 [000959] ---X------- \--* ARR_LENGTH int [000958] ----------- \--* LCL_VAR ref V26 loc22 GenTreeNode creates assertion: [000959] ---X-+----- * ARR_LENGTH int In BB86 New Local Constant Assertion: V26 != null, index = #04 GenTreeNode creates assertion: [000961] -A-X-+----- * ASG int In BB86 New Local Subrange Assertion: V29 in [0..2147483591], index = #05 fgMorphTree BB86, STMT00208 (before) [000965] ----------- * JTRUE void [000964] ----------- \--* EQ int [000962] ----------- +--* LCL_VAR int V29 loc25 [000963] ----------- \--* CNS_INT int 0 Morphing BB87 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB87, STMT00238 (before) [001103] -A-XG------ * ASG int [001102] D------N--- +--* LCL_VAR int V28 loc24 [001101] n--XG------ \--* IND int [001100] ---XG------ \--* INDEX_ADDR byref int[] [001098] ----------- +--* LCL_VAR ref V26 loc22 [001099] ----------- \--* LCL_VAR int V27 loc23 fgMorphIndexAddr (before remorph): [002670] ---X-O----- * COMMA byref [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void [001099] ----------- | +--* LCL_VAR int V27 loc23 [002661] ---X------- | \--* ARR_LENGTH int [001098] ----------- | \--* LCL_VAR ref V26 loc22 [002669] -----O----- \--* ARR_ADDR byref int[] [002668] ----------- \--* ADD byref [002667] ----------- +--* ADD byref [002659] ----------- | +--* LCL_VAR ref V26 loc22 [002666] ----------- | \--* CNS_INT long 16 [002665] ----------- \--* MUL long [002663] ---------U- +--* CAST long <- uint [002660] ----------- | \--* LCL_VAR int V27 loc23 [002664] -------N--- \--* CNS_INT long 4 GenTreeNode creates assertion: [002661] ---X-+----- * ARR_LENGTH int In BB87 New Local Constant Assertion: V26 != null, index = #01 fgMorphIndexAddr (after remorph): [002670] ---X-+----- * COMMA byref [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 fgMorphTree BB87, STMT00238 (after) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 Morphing BB88 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB88, STMT00209 (before) [000968] -A--------- * ASG int [000967] D------N--- +--* LCL_VAR int V30 loc26 [000966] ----------- \--* LCL_VAR int V28 loc24 GenTreeNode creates assertion: [000968] -A---+----- * ASG int In BB88 New Local Copy Assertion: V30 == V28, index = #01 fgMorphTree BB88, STMT00211 (before) [000975] -A--------- * ASG int [000974] D------N--- +--* LCL_VAR int V64 tmp24 [000969] ----------- \--* LCL_VAR int V08 loc4 GenTreeNode creates assertion: [000975] -A---+----- * ASG int In BB88 New Local Copy Assertion: V64 == V08, index = #02 fgMorphTree BB88, STMT00210 (before) [000973] ----------- * JTRUE void [000972] ----------- \--* LT int [000970] ----------- +--* LCL_VAR int V14 loc10 [000971] ----------- \--* CNS_INT int 0 Morphing BB89 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB89, STMT00236 (before) [001093] -A--------- * ASG int [001092] D------N--- +--* LCL_VAR int V65 tmp25 [000977] ----------- \--* LCL_VAR int V64 tmp24 GenTreeNode creates assertion: [001093] -A---+----- * ASG int In BB89 New Local Copy Assertion: V65 == V64, index = #01 fgMorphTree BB89, STMT00237 (before) [001096] -A--------- * ASG int [001095] D------N--- +--* LCL_VAR int V66 tmp26 [001091] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [001096] -A---+----- * ASG int In BB89 New Local Constant Assertion: V66 == 0, index = #02 Morphing BB90 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB90, STMT00212 (before) [000981] -A--------- * ASG int [000980] D------N--- +--* LCL_VAR int V65 tmp25 [000978] ----------- \--* LCL_VAR int V64 tmp24 GenTreeNode creates assertion: [000981] -A---+----- * ASG int In BB90 New Local Copy Assertion: V65 == V64, index = #01 fgMorphTree BB90, STMT00213 (before) [000984] -A--------- * ASG int [000983] D------N--- +--* LCL_VAR int V66 tmp26 [000979] ----------- \--* LCL_VAR int V14 loc10 GenTreeNode creates assertion: [000984] -A---+----- * ASG int In BB90 New Local Copy Assertion: V66 == V14, index = #02 Morphing BB91 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB91, STMT00214 (before) [000990] -A--------- * ASG int [000989] D------N--- +--* LCL_VAR int V31 loc27 [000988] ----------- \--* ADD int [000986] ----------- +--* LCL_VAR int V65 tmp25 [000987] ----------- \--* LCL_VAR int V66 tmp26 fgMorphTree BB91, STMT00215 (before) [000994] ----------- * JTRUE void [000993] ----------- \--* GT int [000991] ----------- +--* LCL_VAR int V06 loc2 [000992] ----------- \--* LCL_VAR int V31 loc27 Morphing BB92 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB92, STMT00235 (before) [001089] -A--------- * ASG int [001088] D------N--- +--* LCL_VAR int V67 tmp27 [001087] ----------- \--* LCL_VAR int V31 loc27 GenTreeNode creates assertion: [001089] -A---+----- * ASG int In BB92 New Local Copy Assertion: V67 == V31, index = #01 Morphing BB93 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB93, STMT00216 (before) [000997] -A--------- * ASG int [000996] D------N--- +--* LCL_VAR int V67 tmp27 [000995] ----------- \--* LCL_VAR int V06 loc2 GenTreeNode creates assertion: [000997] -A---+----- * ASG int In BB93 New Local Copy Assertion: V67 == V06, index = #01 Morphing BB94 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB94, STMT00217 (before) [001001] -A--------- * ASG int [001000] D------N--- +--* LCL_VAR int V32 loc28 [000999] ----------- \--* LCL_VAR int V67 tmp27 GenTreeNode creates assertion: [001001] -A---+----- * ASG int In BB94 New Local Copy Assertion: V32 == V67, index = #01 Morphing BB95 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB95, STMT00219 (before) [001009] ----------- * JTRUE void [001008] ----------- \--* EQ int [001006] ----------- +--* LCL_VAR int V30 loc26 [001007] ----------- \--* CNS_INT int 0 Morphing BB96 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB96, STMT00220 (before) [001014] -A--------- * ASG int [001013] D------N--- +--* LCL_VAR int V20 loc16 [001012] ----------- \--* ADD int [001010] ----------- +--* LCL_VAR int V20 loc16 [001011] ----------- \--* CNS_INT int 1 fgMorphTree BB96, STMT00222 (before) [001021] --C-------- * JTRUE void [001020] --C-------- \--* LT int [001015] ----------- +--* LCL_VAR int V20 loc16 [001574] ----------- \--* LCL_VAR int V144 tmp104 Morphing BB97 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB97, STMT00229 (before) [001070] -ACXG------ * ASG ref [001069] D------N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] --C-------- arg0 \--* CAST long <- int [001066] --C-------- \--* MUL int [001578] ----------- +--* LCL_VAR int V144 tmp104 [001065] ----------- \--* CNS_INT int 2 Initializing arg info for 1068.CALL: Args for call [001068] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002672].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[001067].CAST long (By value), 1 reg: x0, byteAlignment=8] Morphing args for 1068.CALL: Sorting the arguments: Deferred argument ('x0'): [001067] -----+----- * CAST long <- int [001066] -----+----- \--* LSH int [001578] -----+----- +--* LCL_VAR int V144 tmp104 [001065] -----+----- \--* CNS_INT int 1 Moved to late list Deferred argument ('x11'): [002672] H----+----- * CNS_INT(h) long 0x4000000000421858 ftn Moved to late list Register placement order: x0 x11 Args for [001068].CALL after fgMorphArgs: CallArg[[002672].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[001067].CAST long (By value), 1 reg: x0, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB97, STMT00229 (after) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn fgMorphTree BB97, STMT00327 (before) [001582] IA--------- * ASG struct (init) [001580] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001581] ----------- \--* CNS_INT int 0 MorphInitBlock: MorphBlock for dst tree, before: [001580] D----+-N--- * LCL_VAR struct(P) V78 tmp38 * byref V78.:_reference (offs=0x00) -> V159 tmp119 * int V78.:_length (offs=0x08) -> V160 tmp120 MorphBlock after: [001580] D----+-N--- * LCL_VAR struct(P) V78 tmp38 * byref V78.:_reference (offs=0x00) -> V159 tmp119 * int V78.:_length (offs=0x08) -> V160 tmp120 PrepareDst for [001580] have found a local var V78. GenTreeNode creates assertion: [001582] IA--------- * ASG struct (init) In BB97 New Local Constant Assertion: V78 == ZeroObj, index = #01 using field by field initialization. GenTreeNode creates assertion: [002675] -A--------- * ASG byref In BB97 New Local Constant Assertion: V159 == 0, index = #02 GenTreeNode creates assertion: [002678] -A--------- * ASG int In BB97 New Local Constant Assertion: V160 == 0, index = #03 MorphInitBlock (after): [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 fgMorphTree BB97, STMT00327 (after) [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 fgMorphTree BB97, STMT00329 (before) [001590] ----------- * JTRUE void [001589] ----------- \--* NE int [001073] ----------- +--* LCL_VAR ref V33 loc29 [001588] ----------- \--* CNS_INT ref null Morphing BB99 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB99, STMT00333 (before) [001614] IA--------- * ASG struct (init) [001612] D------N--- +--* LCL_VAR struct(P) V78 tmp38 +--* byref V78.:_reference (offs=0x00) -> V159 tmp119 +--* int V78.:_length (offs=0x08) -> V160 tmp120 [001613] ----------- \--* CNS_INT int 0 MorphInitBlock: MorphBlock for dst tree, before: [001612] D----+-N--- * LCL_VAR struct(P) V78 tmp38 * byref V78.:_reference (offs=0x00) -> V159 tmp119 * int V78.:_length (offs=0x08) -> V160 tmp120 MorphBlock after: [001612] D----+-N--- * LCL_VAR struct(P) V78 tmp38 * byref V78.:_reference (offs=0x00) -> V159 tmp119 * int V78.:_length (offs=0x08) -> V160 tmp120 PrepareDst for [001612] have found a local var V78. GenTreeNode creates assertion: [001614] IA--------- * ASG struct (init) In BB99 New Local Constant Assertion: V78 == ZeroObj, index = #01 using field by field initialization. GenTreeNode creates assertion: [002682] -A--------- * ASG byref In BB99 New Local Constant Assertion: V159 == 0, index = #02 GenTreeNode creates assertion: [002685] -A--------- * ASG int In BB99 New Local Constant Assertion: V160 == 0, index = #03 MorphInitBlock (after): [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 fgMorphTree BB99, STMT00333 (after) [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 Morphing BB100 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB100, STMT00331 (before) [001604] -AC-------- * ASG byref [001603] D------N--- +--* LCL_VAR byref V159 tmp119 [001616] ---XG------ \--* FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 Before explicit null check morphing: [001616] ---XG------ * FIELD_ADDR byref : [001600] ----------- \--* LCL_VAR ref V33 loc29 After adding explicit null check: [002692] ---X-O----- * COMMA byref [002688] ---X-O----- +--* NULLCHECK byte [002687] ----------- | \--* LCL_VAR ref V33 loc29 [002691] -----O----- \--* ADD byref [002689] -----O----- +--* LCL_VAR ref V33 loc29 [002690] ----------- \--* CNS_INT long 16 Fseq[] GenTreeNode creates assertion: [002688] ---X-+----- * NULLCHECK byte In BB100 New Local Constant Assertion: V33 != null, index = #01 Final value of Compiler::fgMorphField after morphing: [002692] ---X-+-N--- * COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] fgMorphTree BB100, STMT00331 (after) [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] fgMorphTree BB100, STMT00332 (before) [001610] -A-X------- * ASG int [001609] D------N--- +--* LCL_VAR int V160 tmp120 [001608] ---X------- \--* ARR_LENGTH int [001607] ----------- \--* LCL_VAR ref V33 loc29 GenTreeNode creates assertion: [001610] -A-X-+----- * ASG int In BB100 New Local Subrange Assertion: V160 in [0..2147483591], index = #02 Morphing BB102 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB102, STMT00339 (before) [001643] -A--------- * ASG struct (copy) [001642] D------N--- +--* LCL_VAR struct(P) V79 tmp39 +--* byref V79.:_reference (offs=0x00) -> V161 tmp121 +--* int V79.:_length (offs=0x08) -> V162 tmp122 [001586] ----------- \--* LCL_VAR struct(P) V78 tmp38 \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 \--* int V78.:_length (offs=0x08) -> V160 tmp120 MorphCopyBlock: MorphBlock for dst tree, before: [001642] D----+-N--- * LCL_VAR struct(P) V79 tmp39 * byref V79.:_reference (offs=0x00) -> V161 tmp121 * int V79.:_length (offs=0x08) -> V162 tmp122 MorphBlock after: [001642] D----+-N--- * LCL_VAR struct(P) V79 tmp39 * byref V79.:_reference (offs=0x00) -> V161 tmp121 * int V79.:_length (offs=0x08) -> V162 tmp122 PrepareDst for [001642] have found a local var V79. MorphBlock for src tree, before: [001586] -----+----- * LCL_VAR struct(P) V78 tmp38 * byref V78.:_reference (offs=0x00) -> V159 tmp119 * int V78.:_length (offs=0x08) -> V160 tmp120 MorphBlock after: [001586] -----+----- * LCL_VAR struct(P) V78 tmp38 * byref V78.:_reference (offs=0x00) -> V159 tmp119 * int V78.:_length (offs=0x08) -> V160 tmp120 GenTreeNode creates assertion: [001643] -A--------- * ASG struct (copy) In BB102 New Local Copy Assertion: V79 == V78, index = #01 block assignment to morph: [001643] -A--------- * ASG struct (copy) [001642] D----+-N--- +--* LCL_VAR struct(P) V79 tmp39 +--* byref V79.:_reference (offs=0x00) -> V161 tmp121 +--* int V79.:_length (offs=0x08) -> V162 tmp122 [001586] -----+----- \--* LCL_VAR struct(P) V78 tmp38 \--* byref V78.:_reference (offs=0x00) -> V159 tmp119 \--* int V78.:_length (offs=0x08) -> V160 tmp120 (m_dstDoFldAsg=true) (m_srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [002695] -A--------- * ASG byref In BB102 New Local Copy Assertion: V161 == V159, index = #02 GenTreeNode creates assertion: [002698] -A--------- * ASG int In BB102 New Local Copy Assertion: V162 == V160, index = #03 MorphCopyBlock (after): [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 fgMorphTree BB102, STMT00339 (after) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 fgMorphTree BB102, STMT00336 (before) [001629] ----------- * JTRUE void [001628] N--------U- \--* GT int [001620] ----------- +--* LCL_VAR int V144 tmp104 [001647] ----------- \--* LCL_VAR int V162 tmp122 Assertion prop in BB102: Copy Assertion: V162 == V160, index = #03 [001647] ----------- * LCL_VAR int V160 tmp120 fgMorphTree BB102, STMT00336 (after) [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 Morphing BB104 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB104, STMT00344 (before) [001669] -A--------- * ASG byref [001668] D------N--- +--* LCL_VAR byref V81 tmp41 [001633] ----------- \--* LCL_VAR byref V161 tmp121 GenTreeNode creates assertion: [001669] -A---+----- * ASG byref In BB104 New Local Copy Assertion: V81 == V161, index = #01 fgMorphTree BB104, STMT00345 (before) [001671] -A--------- * ASG byref [001670] D------N--- +--* LCL_VAR byref V82 tmp42 [001636] ----------- \--* LCL_VAR byref V143 tmp103 GenTreeNode creates assertion: [001671] -A---+----- * ASG byref In BB104 New Local Copy Assertion: V82 == V143, index = #02 fgMorphTree BB104, STMT00346 (before) [001673] -A--------- * ASG long [001672] D------N--- +--* LCL_VAR long V83 tmp43 [001640] ---------U- \--* CAST long <- ulong <- uint [001639] ----------- \--* LCL_VAR int V144 tmp104 GenTreeNode creates assertion: [001673] -A---+----- * ASG long In BB104 New Local Subrange Assertion: V83 in [0..4294967295], index = #03 fgMorphTree BB104, STMT00341 (before) [001653] ----------- * NOP void fgMorphTree BB104, STMT00343 (before) [001667] --C-G------ * CALL r2r_ind void [001661] ----------- arg0 +--* LCL_VAR byref V81 tmp41 [001662] ----------- arg1 +--* LCL_VAR byref V82 tmp42 [001666] ----------- arg2 \--* MUL long [001663] ----------- +--* LCL_VAR long V83 tmp43 [001665] ----------- \--* CNS_INT long 4 Initializing arg info for 1667.CALL: Args for call [001667] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002700].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[001661].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8] CallArg[[001662].LCL_VAR byref (By value), 1 reg: x1, byteAlignment=8] CallArg[[001666].MUL long (By value), 1 reg: x2, byteAlignment=8] Morphing args for 1667.CALL: Assertion prop in BB104: Copy Assertion: V81 == V161, index = #01 [001661] ----------- * LCL_VAR byref V161 tmp121 Assertion prop in BB104: Copy Assertion: V82 == V143, index = #02 [001662] ----------- * LCL_VAR byref V143 tmp103 Sorting the arguments: Deferred argument ('x2'): [001666] -----+----- * LSH long [001663] -----+----- +--* LCL_VAR long V83 tmp43 [001665] -----+----- \--* CNS_INT long 2 Moved to late list Deferred argument ('x0'): [001661] -----+----- * LCL_VAR byref V161 tmp121 Moved to late list Deferred argument ('x1'): [001662] -----+----- * LCL_VAR byref V143 tmp103 Moved to late list Deferred argument ('x11'): [002700] H----+----- * CNS_INT(h) long 0x4000000000420490 ftn Moved to late list Register placement order: x2 x0 x1 x11 Args for [001667].CALL after fgMorphArgs: CallArg[[002700].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[001661].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed] CallArg[[001662].LCL_VAR byref (By value), 1 reg: x1, byteAlignment=8, isLate, processed] CallArg[[001666].LSH long (By value), 1 reg: x2, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB104, STMT00343 (after) [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn Morphing BB113 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB113, STMT00337 (before) [001630] --C-G------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() Initializing arg info for 1630.CALL: Args for call [001630] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002701].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] Morphing args for 1630.CALL: Sorting the arguments: Deferred argument ('x11'): [002701] H----+----- * CNS_INT(h) long 0x4000000000424a20 ftn Moved to late list Register placement order: x11 Args for [001630].CALL after fgMorphArgs: CallArg[[002701].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] OutgoingArgsStackSize is 0 fgMorphTree BB113, STMT00337 (after) [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn Converting BB113 to BBJ_THROW Morphing BB114 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB114, STMT00351 (before) [001694] IA--------- * ASG struct (init) [001692] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001693] ----------- \--* CNS_INT int 0 MorphInitBlock: MorphBlock for dst tree, before: [001692] D----+-N--- * LCL_VAR struct(P) V85 tmp45 * byref V85.:_reference (offs=0x00) -> V163 tmp123 * int V85.:_length (offs=0x08) -> V164 tmp124 MorphBlock after: [001692] D----+-N--- * LCL_VAR struct(P) V85 tmp45 * byref V85.:_reference (offs=0x00) -> V163 tmp123 * int V85.:_length (offs=0x08) -> V164 tmp124 PrepareDst for [001692] have found a local var V85. GenTreeNode creates assertion: [001694] IA--------- * ASG struct (init) In BB114 New Local Constant Assertion: V85 == ZeroObj, index = #01 using field by field initialization. GenTreeNode creates assertion: [002704] -A--------- * ASG byref In BB114 New Local Constant Assertion: V163 == 0, index = #02 GenTreeNode creates assertion: [002707] -A--------- * ASG int In BB114 New Local Constant Assertion: V164 == 0, index = #03 MorphInitBlock (after): [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 fgMorphTree BB114, STMT00351 (after) [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 fgMorphTree BB114, STMT00353 (before) [001702] ----------- * JTRUE void [001701] ----------- \--* NE int [001082] ----------- +--* LCL_VAR ref V33 loc29 [001700] ----------- \--* CNS_INT ref null Morphing BB116 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB116, STMT00357 (before) [001726] IA--------- * ASG struct (init) [001724] D------N--- +--* LCL_VAR struct(P) V85 tmp45 +--* byref V85.:_reference (offs=0x00) -> V163 tmp123 +--* int V85.:_length (offs=0x08) -> V164 tmp124 [001725] ----------- \--* CNS_INT int 0 MorphInitBlock: MorphBlock for dst tree, before: [001724] D----+-N--- * LCL_VAR struct(P) V85 tmp45 * byref V85.:_reference (offs=0x00) -> V163 tmp123 * int V85.:_length (offs=0x08) -> V164 tmp124 MorphBlock after: [001724] D----+-N--- * LCL_VAR struct(P) V85 tmp45 * byref V85.:_reference (offs=0x00) -> V163 tmp123 * int V85.:_length (offs=0x08) -> V164 tmp124 PrepareDst for [001724] have found a local var V85. GenTreeNode creates assertion: [001726] IA--------- * ASG struct (init) In BB116 New Local Constant Assertion: V85 == ZeroObj, index = #01 using field by field initialization. GenTreeNode creates assertion: [002711] -A--------- * ASG byref In BB116 New Local Constant Assertion: V163 == 0, index = #02 GenTreeNode creates assertion: [002714] -A--------- * ASG int In BB116 New Local Constant Assertion: V164 == 0, index = #03 MorphInitBlock (after): [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 fgMorphTree BB116, STMT00357 (after) [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 Morphing BB117 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB117, STMT00355 (before) [001716] -AC-------- * ASG byref [001715] D------N--- +--* LCL_VAR byref V163 tmp123 [001728] ---XG------ \--* FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 Before explicit null check morphing: [001728] ---XG------ * FIELD_ADDR byref : [001712] ----------- \--* LCL_VAR ref V33 loc29 After adding explicit null check: [002721] ---X-O----- * COMMA byref [002717] ---X-O----- +--* NULLCHECK byte [002716] ----------- | \--* LCL_VAR ref V33 loc29 [002720] -----O----- \--* ADD byref [002718] -----O----- +--* LCL_VAR ref V33 loc29 [002719] ----------- \--* CNS_INT long 16 Fseq[] GenTreeNode creates assertion: [002717] ---X-+----- * NULLCHECK byte In BB117 New Local Constant Assertion: V33 != null, index = #01 Final value of Compiler::fgMorphField after morphing: [002721] ---X-+-N--- * COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] fgMorphTree BB117, STMT00355 (after) [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] fgMorphTree BB117, STMT00356 (before) [001722] -A-X------- * ASG int [001721] D------N--- +--* LCL_VAR int V164 tmp124 [001720] ---X------- \--* ARR_LENGTH int [001719] ----------- \--* LCL_VAR ref V33 loc29 GenTreeNode creates assertion: [001722] -A-X-+----- * ASG int In BB117 New Local Subrange Assertion: V164 in [0..2147483591], index = #02 Morphing BB119 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB119, STMT00234 (before) [001086] -AC-------- * ASG struct (copy) [001085] D------N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [001698] ----------- \--* LCL_VAR struct(P) V85 tmp45 \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 \--* int V85.:_length (offs=0x08) -> V164 tmp124 MorphCopyBlock: MorphBlock for dst tree, before: [001085] D----+-N--- * LCL_VAR struct(P) V19 loc15 * byref V19.:_reference (offs=0x00) -> V143 tmp103 * int V19.:_length (offs=0x08) -> V144 tmp104 MorphBlock after: [001085] D----+-N--- * LCL_VAR struct(P) V19 loc15 * byref V19.:_reference (offs=0x00) -> V143 tmp103 * int V19.:_length (offs=0x08) -> V144 tmp104 PrepareDst for [001085] have found a local var V19. MorphBlock for src tree, before: [001698] -----+----- * LCL_VAR struct(P) V85 tmp45 * byref V85.:_reference (offs=0x00) -> V163 tmp123 * int V85.:_length (offs=0x08) -> V164 tmp124 MorphBlock after: [001698] -----+----- * LCL_VAR struct(P) V85 tmp45 * byref V85.:_reference (offs=0x00) -> V163 tmp123 * int V85.:_length (offs=0x08) -> V164 tmp124 GenTreeNode creates assertion: [001086] -A--------- * ASG struct (copy) In BB119 New Local Copy Assertion: V19 == V85, index = #01 block assignment to morph: [001086] -A--------- * ASG struct (copy) [001085] D----+-N--- +--* LCL_VAR struct(P) V19 loc15 +--* byref V19.:_reference (offs=0x00) -> V143 tmp103 +--* int V19.:_length (offs=0x08) -> V144 tmp104 [001698] -----+----- \--* LCL_VAR struct(P) V85 tmp45 \--* byref V85.:_reference (offs=0x00) -> V163 tmp123 \--* int V85.:_length (offs=0x08) -> V164 tmp124 (m_dstDoFldAsg=true) (m_srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [002724] -A--------- * ASG byref In BB119 New Local Copy Assertion: V143 == V163, index = #02 GenTreeNode creates assertion: [002727] -A--------- * ASG int In BB119 New Local Copy Assertion: V144 == V164, index = #03 MorphCopyBlock (after): [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 fgMorphTree BB119, STMT00234 (after) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 Morphing BB120 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB120, STMT00223 (before) [001038] -A-XGO----- * ASG int [001037] ---XGO-N--- +--* IND int [001035] ---X-O----- | \--* COMMA byref [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void [001024] ----------- | | +--* LCL_VAR int V20 loc16 [001028] ----------- | | \--* LCL_VAR int V144 tmp104 [001034] -----O----- | \--* ADD byref [001033] ----------- | +--* LCL_VAR byref V143 tmp103 [001032] ----------- | \--* MUL long [001030] ---------U- | +--* CAST long <- uint [001025] ----------- | | \--* LCL_VAR int V20 loc16 [001031] ----------- | \--* CNS_INT long 4 [001036] ----------- \--* LCL_VAR int V28 loc24 fgMorphTree BB120, STMT00223 (after) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 fgMorphTree BB120, STMT00224 (before) [001044] ----------- * JTRUE void [001043] ----------- \--* GE int [001039] ----------- +--* LCL_VAR int V27 loc23 [001042] ----------- \--* SUB int [001040] ----------- +--* LCL_VAR int V29 loc25 [001041] ----------- \--* CNS_INT int 1 fgMorphTree BB120, STMT00224 (after) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 Morphing BB121 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB121, STMT00226 (before) [001054] -A--------- * ASG int [001053] D------N--- +--* LCL_VAR int V27 loc23 [001052] ----------- \--* ADD int [001050] ----------- +--* LCL_VAR int V27 loc23 [001051] ----------- \--* CNS_INT int 1 fgMorphTree BB121, STMT00227 (before) [001060] -A-XG------ * ASG int [001059] D------N--- +--* LCL_VAR int V30 loc26 [001058] n--XG------ \--* IND int [001057] ---XG------ \--* INDEX_ADDR byref int[] [001055] ----------- +--* LCL_VAR ref V26 loc22 [001056] ----------- \--* LCL_VAR int V27 loc23 fgMorphIndexAddr (before remorph): [002741] ---X-O----- * COMMA byref [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void [001056] ----------- | +--* LCL_VAR int V27 loc23 [002732] ---X------- | \--* ARR_LENGTH int [001055] ----------- | \--* LCL_VAR ref V26 loc22 [002740] -----O----- \--* ARR_ADDR byref int[] [002739] ----------- \--* ADD byref [002738] ----------- +--* ADD byref [002730] ----------- | +--* LCL_VAR ref V26 loc22 [002737] ----------- | \--* CNS_INT long 16 [002736] ----------- \--* MUL long [002734] ---------U- +--* CAST long <- uint [002731] ----------- | \--* LCL_VAR int V27 loc23 [002735] -------N--- \--* CNS_INT long 4 GenTreeNode creates assertion: [002732] ---X-+----- * ARR_LENGTH int In BB121 New Local Constant Assertion: V26 != null, index = #01 fgMorphIndexAddr (after remorph): [002741] ---X-+----- * COMMA byref [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 fgMorphTree BB121, STMT00227 (after) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 Morphing BB122 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB122, STMT00225 (before) [001049] -A--------- * ASG int [001048] D------N--- +--* LCL_VAR int V28 loc24 [001047] ----------- \--* ADD int [001045] ----------- +--* LCL_VAR int V28 loc24 [001046] ----------- \--* LCL_VAR int V30 loc26 Morphing BB123 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB123, STMT00218 (before) [001005] ----------- * JTRUE void [001004] ----------- \--* GT int [001002] ----------- +--* LCL_VAR int V32 loc28 [001003] ----------- \--* LCL_VAR int V28 loc24 Morphing BB124 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB124, STMT00047 (before) [000186] ---XG------ * JTRUE void [000185] ---XG------ \--* EQ int [000183] ---XG------ +--* FIELD bool : [000182] ----------- | \--* LCL_VAR byref V01 arg1 [000184] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [000183] ---XG------ * IND bool [002744] -----+----- \--* ADD byref [000182] -----+----- +--* LCL_VAR byref V01 arg1 [002743] -----+----- \--* CNS_INT long 8 fgMorphTree BB124, STMT00047 (after) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 Morphing BB125 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB125, STMT00198 (before) [000930] ----------- * JTRUE void [000929] ----------- \--* NE int [000927] ----------- +--* LCL_VAR int V15 loc11 [000928] ----------- \--* CNS_INT int 0 Morphing BB126 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB126, STMT00199 (before) [000935] ---XG------ * JTRUE void [000934] ---XG------ \--* EQ int [000932] ---XG------ +--* FIELD int : [000931] ----------- | \--* LCL_VAR byref V01 arg1 [000933] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [000932] ---XG------ * IND int [002746] -----+----- \--* ADD byref [000931] -----+----- +--* LCL_VAR byref V01 arg1 [002745] -----+----- \--* CNS_INT long 4 fgMorphTree BB126, STMT00199 (after) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 Morphing BB127 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB127, STMT00367 (before) [001783] -A-XG------ * ASG ref [001782] D------N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG------ \--* FIELD ref : [000937] ----------- \--* LCL_VAR ref V03 arg3 Final value of Compiler::fgMorphField after morphing: [001730] ---XG------ * IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] GenTreeNode creates assertion: [001730] ---XG+----- * IND ref In BB127 New Local Constant Assertion: V03 != null, index = #01 fgMorphTree BB127, STMT00367 (after) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] fgMorphTree BB127, STMT00358 (before) [001735] ----------- * JTRUE void [001734] ----------- \--* EQ int [001732] ----------- +--* LCL_VAR ref V86 tmp46 [001733] ----------- \--* CNS_INT ref null Morphing BB130 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB130, STMT00359 (before) [001738] -A-XG------ * ASG int [001737] D------N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG------ \--* FIELD int : [000936] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [001736] ---XG------ * IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 fgMorphTree BB130, STMT00359 (after) [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 fgMorphTree BB130, STMT00360 (before) [001743] ---X------- * JTRUE void [001742] N--X-----U- \--* NE int [001740] ---X------- +--* ARR_LENGTH int [001739] ----------- | \--* LCL_VAR ref V86 tmp46 [001741] ----------- \--* CNS_INT int 1 GenTreeNode creates assertion: [001740] ---X-+----- * ARR_LENGTH int In BB130 New Local Constant Assertion: V86 != null, index = #01 Morphing BB131 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB131, STMT00363 (before) [001753] ---XG------ * JTRUE void [001752] N--XG----U- \--* GE int [001747] ----------- +--* LCL_VAR int V87 tmp47 [001786] ---XG------ \--* FIELD int : [001749] ---XG------ \--* FIELD_ADDR byref : [001748] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002754] -----+----- * ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [002755] ----------- * ADD long [002753] -----+----- +--* CNS_INT long 16 [002751] -----+----- \--* CNS_INT long 8 Bashed to long constant: [002755] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [001786] ---XG------ * IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 fgMorphTree BB131, STMT00363 (after) [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 Morphing BB132 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB132, STMT00364 (before) [001759] -A-XG------ * ASG byref [001758] D------N--- +--* LCL_VAR byref V88 tmp48 [001755] ---XG------ \--* FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [001755] ---XG------ * FIELD_ADDR byref : [001754] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [002761] ---X-O----- * COMMA byref [002757] ---X-O----- +--* NULLCHECK byte [002756] ----------- | \--* LCL_VAR byref V00 arg0 [002760] -----O----- \--* ADD byref [002758] -----O----- +--* LCL_VAR byref V00 arg0 [002759] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002761] ---X-+-N--- * COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 fgMorphTree BB132, STMT00364 (after) [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 fgMorphTree BB132, STMT00365 (before) [001775] -A-XGO----- * ASG short [001774] ---XGO-N--- +--* IND short [001769] ---XGO----- | \--* COMMA byref [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001756] ----------- | | +--* LCL_VAR int V87 tmp47 [001762] ----G------ | | \--* FIELD int : [001761] ----------- | | \--* LCL_VAR byref V88 tmp48 [001768] ----GO----- | \--* ADD byref [001767] ----G------ | +--* FIELD byref : [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 [001766] ----------- | \--* MUL long [001764] ---------U- | +--* CAST long <- uint [001757] ----------- | | \--* LCL_VAR int V87 tmp47 [001765] ----------- | \--* CNS_INT long 2 [001773] n--XG------ \--* IND ushort [001772] ---XG------ \--* INDEX_ADDR byref ushort[] [001770] ----------- +--* LCL_VAR ref V86 tmp46 [001771] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [001762] ---XG------ * IND int [002763] -----+----- \--* ADD byref [001761] -----+----- +--* LCL_VAR byref V88 tmp48 [002762] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [001767] ---XG------ * IND byref [001760] -----+----- \--* LCL_VAR byref V88 tmp48 fgMorphIndexAddr (before remorph): [002775] ---X-O----- * COMMA byref [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void [001771] ----------- | +--* CNS_INT int 0 [002767] ---X------- | \--* ARR_LENGTH int [001770] ----------- | \--* LCL_VAR ref V86 tmp46 [002774] -----O----- \--* ARR_ADDR byref ushort[] [002773] ----------- \--* ADD byref [002772] ----------- +--* ADD byref [002765] ----------- | +--* LCL_VAR ref V86 tmp46 [002771] ----------- | \--* CNS_INT long 12 [002770] ----------- \--* MUL long [002766] ----------- +--* CNS_INT long 0 [002769] -------N--- \--* CNS_INT long 2 GenTreeNode creates assertion: [002767] ---X-+----- * ARR_LENGTH int In BB132 New Local Constant Assertion: V86 != null, index = #01 Folding long operator with constant nodes into a constant: [002770] ----------- * MUL long [002766] -----+----- +--* CNS_INT long 0 [002769] -----+-N--- \--* CNS_INT long 2 Bashed to long constant: [002770] ----------- * CNS_INT long 0 Folding long operator with constant nodes into a constant: [002776] ----------- * ADD long [002771] -----+----- +--* CNS_INT long 12 [002770] -----+----- \--* CNS_INT long 0 Bashed to long constant: [002776] ----------- * CNS_INT long 12 fgMorphIndexAddr (after remorph): [002775] ---X-+----- * COMMA byref [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 fgMorphTree BB132, STMT00365 (after) [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 fgMorphTree BB132, STMT00366 (before) [001781] -A-XG------ * ASG int [001780] ---XG--N--- +--* FIELD int : [001776] ----------- | \--* LCL_VAR byref V00 arg0 [001779] ----------- \--* ADD int [001777] ----------- +--* LCL_VAR int V87 tmp47 [001778] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [001780] ---XG--N--- * IND int [002779] -----+----- \--* ADD byref [001776] -----+----- +--* LCL_VAR byref V00 arg0 [002778] -----+----- \--* CNS_INT long 8 fgMorphTree BB132, STMT00366 (after) [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 Morphing BB133 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB133, STMT00361 (before) [001746] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] ----------- this +--* LCL_VAR byref V00 arg0 [001745] ----------- arg1 \--* LCL_VAR ref V86 tmp46 Initializing arg info for 1746.CALL: Args for call [001746] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[001744].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[002780].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[001745].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8] Morphing args for 1746.CALL: Sorting the arguments: Deferred argument ('x0'): [001744] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [001745] -----+----- * LCL_VAR ref V86 tmp46 Moved to late list Deferred argument ('x11'): [002780] H----+----- * CNS_INT(h) long 0x4000000000431d58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [001746].CALL after fgMorphArgs: CallArg[[001744].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[002780].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[001745].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB133, STMT00361 (after) [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn Morphing BB134 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB134, STMT00048 (before) [000189] -A--------- * ASG int [000188] D------N--- +--* LCL_VAR int V21 loc17 [000187] ----------- \--* CNS_INT int 0 Folding operator with constant nodes into a constant: [002781] ----------- * CAST int <- bool <- int [000187] -----+----- \--* CNS_INT int 0 Bashed to int constant: [002781] ----------- * CNS_INT int 0 GenTreeNode creates assertion: [000189] -A---+----- * ASG int In BB134 New Local Constant Assertion: V21 == 0, index = #01 fgMorphTree BB134, STMT00369 (before) [001794] -A--------- * ASG struct (copy) [001793] D------N--- +--* LCL_VAR struct(P) V90 tmp50 +--* byref V90.:_reference (offs=0x00) -> V165 tmp125 +--* int V90.:_length (offs=0x08) -> V166 tmp126 [000193] ----------- \--* LCL_VAR struct V02 arg2 MorphCopyBlock: MorphBlock for dst tree, before: [001793] D----+-N--- * LCL_VAR struct(P) V90 tmp50 * byref V90.:_reference (offs=0x00) -> V165 tmp125 * int V90.:_length (offs=0x08) -> V166 tmp126 MorphBlock after: [001793] D----+-N--- * LCL_VAR struct(P) V90 tmp50 * byref V90.:_reference (offs=0x00) -> V165 tmp125 * int V90.:_length (offs=0x08) -> V166 tmp126 PrepareDst for [001793] have found a local var V90. MorphBlock for src tree, before: [000193] -----+----- * LCL_VAR struct V02 arg2 MorphBlock after: [000193] -----+----- * LCL_VAR struct V02 arg2 GenTreeNode creates assertion: [001794] -A--------- * ASG struct (copy) In BB134 New Local Copy Assertion: V90 == V02, index = #02 block assignment to morph: [001794] -A--------- * ASG struct (copy) [001793] D----+-N--- +--* LCL_VAR struct(P) V90 tmp50 +--* byref V90.:_reference (offs=0x00) -> V165 tmp125 +--* int V90.:_length (offs=0x08) -> V166 tmp126 [000193] -----+----- \--* LCL_VAR struct V02 arg2 (m_dstDoFldAsg=true) using field by field assignments. Local V02 should not be enregistered because: was accessed as a local field Local V02 should not be enregistered because: was accessed as a local field MorphCopyBlock (after): [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] fgMorphTree BB134, STMT00369 (after) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] fgMorphTree BB134, STMT00050 (before) [000196] -A--------- * ASG byref [000195] D------N--- +--* LCL_VAR byref V35 loc31 [001792] ----------- \--* LCL_VAR byref V165 tmp125 GenTreeNode creates assertion: [000196] -A---+----- * ASG byref In BB134 New Local Copy Assertion: V35 == V165, index = #03 fgMorphTree BB134, STMT00051 (before) [000200] -A--------- * ASG long [000199] D------N--- +--* LCL_VAR long V34 loc30 [000198] ---------U- \--* CAST long <- ulong <- byref [000197] ----------- \--* LCL_VAR byref V35 loc31 lvaGrabTemp returning 169 (V169 tmp129) called for Cast away GC. Assertion prop in BB134: Copy Assertion: V35 == V165, index = #03 [000197] ----------- * LCL_VAR byref V165 tmp125 GenTreeNode creates assertion: [000200] -A---+----- * ASG long In BB134 New Local Copy Assertion: V34 == V169, index = #04 fgMorphTree BB134, STMT00051 (after) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 fgMorphTree BB134, STMT00052 (before) [000203] -A--------- * ASG long [000202] D------N--- +--* LCL_VAR long V36 loc32 [000201] ----------- \--* LCL_VAR long V17 loc13 GenTreeNode creates assertion: [000203] -A---+----- * ASG long In BB134 New Local Copy Assertion: V36 == V17, index = #05 Morphing BB136 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB136, STMT00070 (before) [000274] ----------- * JTRUE void [000273] ----------- \--* LE int [000271] ----------- +--* LCL_VAR int V14 loc10 [000272] ----------- \--* CNS_INT int 0 Morphing BB137 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB137, STMT00176 (before) [000824] ----------- * JTRUE void [000823] ----------- \--* EQ int [000821] ----------- +--* LCL_VAR int V18 loc14 [000822] ----------- \--* CNS_INT int 35 Morphing BB138 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB138, STMT00196 (before) [000922] ----------- * JTRUE void [000921] ----------- \--* EQ int [000919] ----------- +--* LCL_VAR int V18 loc14 [000920] ----------- \--* CNS_INT int 46 Morphing BB139 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB139, STMT00197 (before) [000926] ----------- * JTRUE void [000925] ----------- \--* EQ int [000923] ----------- +--* LCL_VAR int V18 loc14 [000924] ----------- \--* CNS_INT int 48 Morphing BB140 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' Morphing BB141 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB141, STMT00179 (before) [000836] -A--------- * ASG byref [000835] D------N--- +--* LCL_VAR byref V60 tmp20 [000829] ----------- \--* LCL_VAR byref V00 arg0 GenTreeNode creates assertion: [000836] -A---+----- * ASG byref In BB141 New Local Copy Assertion: V60 == V00, index = #01 fgMorphTree BB141, STMT00178 (before) [000834] ---XG------ * JTRUE void [000833] ---XG------ \--* NE int [000831] ---XG------ +--* IND ubyte [000830] ----------- | \--* LCL_VAR long V36 loc32 [000832] ----------- \--* CNS_INT int 0 Morphing BB142 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB142, STMT00194 (before) [000914] -A--------- * ASG byref [000913] D------N--- +--* LCL_VAR byref V62 tmp22 [000838] ----------- \--* LCL_VAR byref V60 tmp20 GenTreeNode creates assertion: [000914] -A---+----- * ASG byref In BB142 New Local Copy Assertion: V62 == V60, index = #01 fgMorphTree BB142, STMT00195 (before) [000917] -A--------- * ASG int [000916] D------N--- +--* LCL_VAR int V63 tmp23 [000912] ----------- \--* CNS_INT int 48 GenTreeNode creates assertion: [000917] -A---+----- * ASG int In BB142 New Local Constant Assertion: V63 == 48, index = #02 Morphing BB143 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB143, STMT00181 (before) [000848] -A--------- * ASG long [000847] D------N--- +--* LCL_VAR long V61 tmp21 [000840] ----------- \--* LCL_VAR long V36 loc32 GenTreeNode creates assertion: [000848] -A---+----- * ASG long In BB143 New Local Copy Assertion: V61 == V36, index = #01 fgMorphTree BB143, STMT00180 (before) [000846] -A--------- * ASG long [000845] D------N--- +--* LCL_VAR long V36 loc32 [000844] ----------- \--* ADD long [000841] ----------- +--* LCL_VAR long V36 loc32 [000843] ----------- \--* CAST long <- int [000842] ----------- \--* CNS_INT int 1 Folding long operator with constant nodes into a constant: [000843] ----------- * CAST long <- int [000842] -----+----- \--* CNS_INT int 1 Bashed to long constant: [000843] ----------- * CNS_INT long 1 The assignment [000846] using V61 removes: Copy Assertion: V61 == V36 fgMorphTree BB143, STMT00180 (after) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 fgMorphTree BB143, STMT00182 (before) [000852] -A--------- * ASG byref [000851] D------N--- +--* LCL_VAR byref V62 tmp22 [000839] ----------- \--* LCL_VAR byref V60 tmp20 GenTreeNode creates assertion: [000852] -A---+----- * ASG byref In BB143 New Local Copy Assertion: V62 == V60, index = #01 fgMorphTree BB143, STMT00183 (before) [000855] -A-XG------ * ASG int [000854] D------N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG------ \--* IND ubyte [000849] ----------- \--* LCL_VAR long V61 tmp21 GenTreeNode creates assertion: [000855] -A-XG+----- * ASG int In BB143 New Local Subrange Assertion: V63 in [0..255], index = #02 Morphing BB144 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB144, STMT00377 (before) [001836] -A--------- * ASG ushort [001835] D------N--- +--* LCL_VAR ushort V92 tmp52 [001796] ----------- \--* CAST int <- ushort <- int [000858] ----------- \--* LCL_VAR int V63 tmp23 GenTreeNode creates assertion: [001836] -A---+----- * ASG ushort In BB144 New Local Subrange Assertion: V92 in [0..65535], index = #01 fgMorphTree BB144, STMT00370 (before) [001799] -A-XG------ * ASG int [001798] D------N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG------ \--* FIELD int : [000857] ----------- \--* LCL_VAR byref V62 tmp22 Final value of Compiler::fgMorphField after morphing: [001797] ---XG------ * IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 fgMorphTree BB144, STMT00370 (after) [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 fgMorphTree BB144, STMT00372 (before) [001806] ---XG------ * JTRUE void [001805] N--XG----U- \--* GE int [001800] ----------- +--* LCL_VAR int V91 tmp51 [001839] ---XG------ \--* FIELD int : [001802] ---XG------ \--* FIELD_ADDR byref : [001801] ----------- \--* LCL_VAR byref V62 tmp22 Final value of Compiler::fgMorphField after morphing: [002799] -----+----- * ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [002800] ----------- * ADD long [002798] -----+----- +--* CNS_INT long 16 [002796] -----+----- \--* CNS_INT long 8 Bashed to long constant: [002800] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [001839] ---XG------ * IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 fgMorphTree BB144, STMT00372 (after) [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 Morphing BB146 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB146, STMT00374 (before) [001815] -A-XG------ * ASG byref [001814] D------N--- +--* LCL_VAR byref V93 tmp53 [001811] ---XG------ \--* FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 Before explicit null check morphing: [001811] ---XG------ * FIELD_ADDR byref : [001810] ----------- \--* LCL_VAR byref V62 tmp22 After adding explicit null check: [002806] ---X-O----- * COMMA byref [002802] ---X-O----- +--* NULLCHECK byte [002801] ----------- | \--* LCL_VAR byref V62 tmp22 [002805] -----O----- \--* ADD byref [002803] -----O----- +--* LCL_VAR byref V62 tmp22 [002804] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002806] ---X-+-N--- * COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 fgMorphTree BB146, STMT00374 (after) [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 fgMorphTree BB146, STMT00375 (before) [001828] -A-XGO----- * ASG short [001827] ---XGO-N--- +--* IND short [001825] ---XGO----- | \--* COMMA byref [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001812] ----------- | | +--* LCL_VAR int V91 tmp51 [001818] ----G------ | | \--* FIELD int : [001817] ----------- | | \--* LCL_VAR byref V93 tmp53 [001824] ----GO----- | \--* ADD byref [001823] ----G------ | +--* FIELD byref : [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 [001822] ----------- | \--* MUL long [001820] ---------U- | +--* CAST long <- uint [001813] ----------- | | \--* LCL_VAR int V91 tmp51 [001821] ----------- | \--* CNS_INT long 2 [001826] ----------- \--* LCL_VAR int V92 tmp52 Final value of Compiler::fgMorphField after morphing: [001818] ---XG------ * IND int [002808] -----+----- \--* ADD byref [001817] -----+----- +--* LCL_VAR byref V93 tmp53 [002807] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [001823] ---XG------ * IND byref [001816] -----+----- \--* LCL_VAR byref V93 tmp53 fgMorphTree BB146, STMT00375 (after) [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 fgMorphTree BB146, STMT00376 (before) [001834] -A-XG------ * ASG int [001833] ---XG--N--- +--* FIELD int : [001829] ----------- | \--* LCL_VAR byref V62 tmp22 [001832] ----------- \--* ADD int [001830] ----------- +--* LCL_VAR int V91 tmp51 [001831] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [001833] ---XG--N--- * IND int [002811] -----+----- \--* ADD byref [001829] -----+----- +--* LCL_VAR byref V62 tmp22 [002810] -----+----- \--* CNS_INT long 8 fgMorphTree BB146, STMT00376 (after) [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 Morphing BB147 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB147, STMT00373 (before) [001809] --C-G------ * CALL r2r_ind void [001807] ----------- this +--* LCL_VAR byref V62 tmp22 [001808] ----------- arg1 \--* LCL_VAR int V92 tmp52 Initializing arg info for 1809.CALL: Args for call [001809] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[001807].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[002812].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[001808].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 1809.CALL: Sorting the arguments: Deferred argument ('x0'): [001807] -----+----- * LCL_VAR byref V62 tmp22 Moved to late list Deferred argument ('x1'): [001808] -----+----- * LCL_VAR int V92 tmp52 Moved to late list Deferred argument ('x11'): [002812] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [001809].CALL after fgMorphArgs: CallArg[[001807].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[002812].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[001808].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB147, STMT00373 (after) [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB148 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB148, STMT00185 (before) [000863] ----------- * JTRUE void [000862] ----------- \--* EQ int [000860] ----------- +--* LCL_VAR int V12 loc8 [000861] ----------- \--* CNS_INT int 0 Morphing BB149 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB149, STMT00188 (before) [000877] ----------- * JTRUE void [000876] ----------- \--* LE int [000874] ----------- +--* LCL_VAR int V08 loc4 [000875] ----------- \--* CNS_INT int 1 Morphing BB150 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB150, STMT00189 (before) [000881] ----------- * JTRUE void [000880] ----------- \--* LT int [000878] ----------- +--* LCL_VAR int V20 loc16 [000879] ----------- \--* CNS_INT int 0 Morphing BB151 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB151, STMT00190 (before) [000901] ---XGO----- * JTRUE void [000900] N--XGO---U- \--* NE int [000882] ----------- +--* LCL_VAR int V08 loc4 [000899] ---XGO----- \--* ADD int [000897] ---XGO----- +--* IND int [000896] ---X-O----- | \--* COMMA byref [000890] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000885] ----------- | | +--* LCL_VAR int V20 loc16 [000889] ----------- | | \--* LCL_VAR int V144 tmp104 [000895] -----O----- | \--* ADD byref [000894] ----------- | +--* LCL_VAR byref V143 tmp103 [000893] ----------- | \--* MUL long [000891] ---------U- | +--* CAST long <- uint [000886] ----------- | | \--* LCL_VAR int V20 loc16 [000892] ----------- | \--* CNS_INT long 4 [000898] ----------- \--* CNS_INT int 1 fgMorphTree BB151, STMT00190 (after) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 Morphing BB152 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB152, STMT00388 (before) [001896] -A-XG------ * ASG ref [001895] D------N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG------ \--* FIELD ref : [000903] ----------- \--* LCL_VAR ref V03 arg3 Final value of Compiler::fgMorphField after morphing: [001843] ---XG------ * IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] GenTreeNode creates assertion: [001843] ---XG+----- * IND ref In BB152 New Local Constant Assertion: V03 != null, index = #01 fgMorphTree BB152, STMT00388 (after) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] fgMorphTree BB152, STMT00379 (before) [001848] ----------- * JTRUE void [001847] ----------- \--* EQ int [001845] ----------- +--* LCL_VAR ref V95 tmp55 [001846] ----------- \--* CNS_INT ref null Morphing BB155 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB155, STMT00380 (before) [001851] -A-XG------ * ASG int [001850] D------N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG------ \--* FIELD int : [000902] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [001849] ---XG------ * IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 fgMorphTree BB155, STMT00380 (after) [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 fgMorphTree BB155, STMT00381 (before) [001856] ---X------- * JTRUE void [001855] N--X-----U- \--* NE int [001853] ---X------- +--* ARR_LENGTH int [001852] ----------- | \--* LCL_VAR ref V95 tmp55 [001854] ----------- \--* CNS_INT int 1 GenTreeNode creates assertion: [001853] ---X-+----- * ARR_LENGTH int In BB155 New Local Constant Assertion: V95 != null, index = #01 Morphing BB156 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB156, STMT00384 (before) [001866] ---XG------ * JTRUE void [001865] N--XG----U- \--* GE int [001860] ----------- +--* LCL_VAR int V96 tmp56 [001899] ---XG------ \--* FIELD int : [001862] ---XG------ \--* FIELD_ADDR byref : [001861] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002821] -----+----- * ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [002822] ----------- * ADD long [002820] -----+----- +--* CNS_INT long 16 [002818] -----+----- \--* CNS_INT long 8 Bashed to long constant: [002822] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [001899] ---XG------ * IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 fgMorphTree BB156, STMT00384 (after) [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 Morphing BB157 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB157, STMT00385 (before) [001872] -A-XG------ * ASG byref [001871] D------N--- +--* LCL_VAR byref V97 tmp57 [001868] ---XG------ \--* FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [001868] ---XG------ * FIELD_ADDR byref : [001867] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [002828] ---X-O----- * COMMA byref [002824] ---X-O----- +--* NULLCHECK byte [002823] ----------- | \--* LCL_VAR byref V00 arg0 [002827] -----O----- \--* ADD byref [002825] -----O----- +--* LCL_VAR byref V00 arg0 [002826] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002828] ---X-+-N--- * COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 fgMorphTree BB157, STMT00385 (after) [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 fgMorphTree BB157, STMT00386 (before) [001888] -A-XGO----- * ASG short [001887] ---XGO-N--- +--* IND short [001882] ---XGO----- | \--* COMMA byref [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001869] ----------- | | +--* LCL_VAR int V96 tmp56 [001875] ----G------ | | \--* FIELD int : [001874] ----------- | | \--* LCL_VAR byref V97 tmp57 [001881] ----GO----- | \--* ADD byref [001880] ----G------ | +--* FIELD byref : [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 [001879] ----------- | \--* MUL long [001877] ---------U- | +--* CAST long <- uint [001870] ----------- | | \--* LCL_VAR int V96 tmp56 [001878] ----------- | \--* CNS_INT long 2 [001886] n--XG------ \--* IND ushort [001885] ---XG------ \--* INDEX_ADDR byref ushort[] [001883] ----------- +--* LCL_VAR ref V95 tmp55 [001884] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [001875] ---XG------ * IND int [002830] -----+----- \--* ADD byref [001874] -----+----- +--* LCL_VAR byref V97 tmp57 [002829] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [001880] ---XG------ * IND byref [001873] -----+----- \--* LCL_VAR byref V97 tmp57 fgMorphIndexAddr (before remorph): [002842] ---X-O----- * COMMA byref [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void [001884] ----------- | +--* CNS_INT int 0 [002834] ---X------- | \--* ARR_LENGTH int [001883] ----------- | \--* LCL_VAR ref V95 tmp55 [002841] -----O----- \--* ARR_ADDR byref ushort[] [002840] ----------- \--* ADD byref [002839] ----------- +--* ADD byref [002832] ----------- | +--* LCL_VAR ref V95 tmp55 [002838] ----------- | \--* CNS_INT long 12 [002837] ----------- \--* MUL long [002833] ----------- +--* CNS_INT long 0 [002836] -------N--- \--* CNS_INT long 2 GenTreeNode creates assertion: [002834] ---X-+----- * ARR_LENGTH int In BB157 New Local Constant Assertion: V95 != null, index = #01 Folding long operator with constant nodes into a constant: [002837] ----------- * MUL long [002833] -----+----- +--* CNS_INT long 0 [002836] -----+-N--- \--* CNS_INT long 2 Bashed to long constant: [002837] ----------- * CNS_INT long 0 Folding long operator with constant nodes into a constant: [002843] ----------- * ADD long [002838] -----+----- +--* CNS_INT long 12 [002837] -----+----- \--* CNS_INT long 0 Bashed to long constant: [002843] ----------- * CNS_INT long 12 fgMorphIndexAddr (after remorph): [002842] ---X-+----- * COMMA byref [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 fgMorphTree BB157, STMT00386 (after) [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 fgMorphTree BB157, STMT00387 (before) [001894] -A-XG------ * ASG int [001893] ---XG--N--- +--* FIELD int : [001889] ----------- | \--* LCL_VAR byref V00 arg0 [001892] ----------- \--* ADD int [001890] ----------- +--* LCL_VAR int V96 tmp56 [001891] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [001893] ---XG--N--- * IND int [002846] -----+----- \--* ADD byref [001889] -----+----- +--* LCL_VAR byref V00 arg0 [002845] -----+----- \--* CNS_INT long 8 fgMorphTree BB157, STMT00387 (after) [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 Morphing BB158 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB158, STMT00382 (before) [001859] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] ----------- this +--* LCL_VAR byref V00 arg0 [001858] ----------- arg1 \--* LCL_VAR ref V95 tmp55 Initializing arg info for 1859.CALL: Args for call [001859] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[001857].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[002847].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[001858].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8] Morphing args for 1859.CALL: Sorting the arguments: Deferred argument ('x0'): [001857] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [001858] -----+----- * LCL_VAR ref V95 tmp55 Moved to late list Deferred argument ('x11'): [002847] H----+----- * CNS_INT(h) long 0x4000000000431d58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [001859].CALL after fgMorphArgs: CallArg[[001857].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[002847].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[001858].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB158, STMT00382 (after) [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn Morphing BB159 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB159, STMT00193 (before) [000911] -A--------- * ASG int [000910] D------N--- +--* LCL_VAR int V20 loc16 [000909] ----------- \--* SUB int [000907] ----------- +--* LCL_VAR int V20 loc16 [000908] ----------- \--* CNS_INT int 1 fgMorphTree BB159, STMT00193 (after) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 Morphing BB160 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB160, STMT00186 (before) [000868] -A--------- * ASG int [000867] D------N--- +--* LCL_VAR int V08 loc4 [000866] ----------- \--* SUB int [000864] ----------- +--* LCL_VAR int V08 loc4 [000865] ----------- \--* CNS_INT int 1 fgMorphTree BB160, STMT00186 (after) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 fgMorphTree BB160, STMT00187 (before) [000873] -A--------- * ASG int [000872] D------N--- +--* LCL_VAR int V14 loc10 [000871] ----------- \--* SUB int [000869] ----------- +--* LCL_VAR int V14 loc10 [000870] ----------- \--* CNS_INT int 1 fgMorphTree BB160, STMT00187 (after) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 Morphing BB161 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB161, STMT00177 (before) [000828] ----------- * JTRUE void [000827] ----------- \--* GT int [000825] ----------- +--* LCL_VAR int V14 loc10 [000826] ----------- \--* CNS_INT int 0 Morphing BB162 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB162, STMT00071 (before) [000278] ----------- * JTRUE void [000277] N--------U- \--* GT int [000275] ----------- +--* LCL_VAR int V18 loc14 [000276] ----------- \--* CNS_INT int 69 Morphing BB163 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB163, STMT00129 (before) [000596] ----------- * SWITCH void [000595] ----------- \--* SUB int [000593] ----------- +--* LCL_VAR int V18 loc14 [000594] ----------- \--* CNS_INT int 34 fgMorphTree BB163, STMT00129 (after) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 Morphing BB164 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB164, STMT00130 (before) [000600] ----------- * SWITCH void [000599] ----------- \--* SUB int [000597] ----------- +--* LCL_VAR int V18 loc14 [000598] ----------- \--* CNS_INT int 44 fgMorphTree BB164, STMT00130 (after) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 Morphing BB165 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB165, STMT00131 (before) [000604] ----------- * JTRUE void [000603] ----------- \--* EQ int [000601] ----------- +--* LCL_VAR int V18 loc14 [000602] ----------- \--* CNS_INT int 69 Morphing BB166 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' Morphing BB167 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB167, STMT00072 (before) [000282] ----------- * JTRUE void [000281] ----------- \--* EQ int [000279] ----------- +--* LCL_VAR int V18 loc14 [000280] ----------- \--* CNS_INT int 92 Morphing BB168 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB168, STMT00079 (before) [000322] ----------- * JTRUE void [000321] ----------- \--* EQ int [000319] ----------- +--* LCL_VAR int V18 loc14 [000320] ----------- \--* CNS_INT int 101 Morphing BB169 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB169, STMT00125 (before) [000584] ----------- * JTRUE void [000583] ----------- \--* NE int [000581] ----------- +--* LCL_VAR int V18 loc14 [000582] ----------- \--* CNS_INT int 0x2030 Morphing BB212 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB212, STMT00429 (before) [002119] -A-XG------ * ASG ref [002118] D------N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG------ \--* FIELD ref : [000586] ----------- \--* LCL_VAR ref V03 arg3 Final value of Compiler::fgMorphField after morphing: [002066] ---XG------ * IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] GenTreeNode creates assertion: [002066] ---XG+----- * IND ref In BB212 New Local Constant Assertion: V03 != null, index = #01 fgMorphTree BB212, STMT00429 (after) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] Morphing BB171 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB171, STMT00141 (before) [000642] ----------- * JTRUE void [000641] ----------- \--* GE int [000639] ----------- +--* LCL_VAR int V14 loc10 [000640] ----------- \--* CNS_INT int 0 Morphing BB172 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB172, STMT00160 (before) [000735] -A--------- * ASG int [000734] D------N--- +--* LCL_VAR int V14 loc10 [000733] ----------- \--* ADD int [000731] ----------- +--* LCL_VAR int V14 loc10 [000732] ----------- \--* CNS_INT int 1 fgMorphTree BB172, STMT00161 (before) [000739] ----------- * JTRUE void [000738] ----------- \--* LE int [000736] ----------- +--* LCL_VAR int V08 loc4 [000737] ----------- \--* LCL_VAR int V06 loc2 Morphing BB173 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB173, STMT00164 (before) [000749] -A--------- * ASG int [000748] D------N--- +--* LCL_VAR int V58 tmp18 [000747] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000749] -A---+----- * ASG int In BB173 New Local Constant Assertion: V58 == 0, index = #01 Morphing BB174 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB174, STMT00162 (before) [000742] -A--------- * ASG int [000741] D------N--- +--* LCL_VAR int V58 tmp18 [000740] ----------- \--* CNS_INT int 48 GenTreeNode creates assertion: [000742] -A---+----- * ASG int In BB174 New Local Constant Assertion: V58 == 48, index = #01 Morphing BB175 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB175, STMT00163 (before) [000746] -A--------- * ASG int [000745] D------N--- +--* LCL_VAR int V18 loc14 [000744] ----------- \--* LCL_VAR int V58 tmp18 GenTreeNode creates assertion: [000746] -A---+----- * ASG int In BB175 New Local Subrange Assertion: V18 in [0..65535], index = #01 fgMorphTree BB175, STMT00163 (after) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 Morphing BB176 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB176, STMT00142 (before) [000647] ---XG------ * JTRUE void [000646] ---XG------ \--* NE int [000644] ---XG------ +--* IND ubyte [000643] ----------- | \--* LCL_VAR long V36 loc32 [000645] ----------- \--* CNS_INT int 0 Morphing BB177 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB177, STMT00157 (before) [000722] ----------- * JTRUE void [000721] ----------- \--* GT int [000719] ----------- +--* LCL_VAR int V08 loc4 [000720] ----------- \--* LCL_VAR int V07 loc3 Morphing BB178 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB178, STMT00159 (before) [000729] -A--------- * ASG int [000728] D------N--- +--* LCL_VAR int V57 tmp17 [000727] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000729] -A---+----- * ASG int In BB178 New Local Constant Assertion: V57 == 0, index = #01 Morphing BB179 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB179, STMT00158 (before) [000725] -A--------- * ASG int [000724] D------N--- +--* LCL_VAR int V57 tmp17 [000723] ----------- \--* CNS_INT int 48 GenTreeNode creates assertion: [000725] -A---+----- * ASG int In BB179 New Local Constant Assertion: V57 == 48, index = #01 Morphing BB180 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB180, STMT00144 (before) [000656] -A--------- * ASG long [000655] D------N--- +--* LCL_VAR long V56 tmp16 [000648] ----------- \--* LCL_VAR long V36 loc32 GenTreeNode creates assertion: [000656] -A---+----- * ASG long In BB180 New Local Copy Assertion: V56 == V36, index = #01 fgMorphTree BB180, STMT00143 (before) [000654] -A--------- * ASG long [000653] D------N--- +--* LCL_VAR long V36 loc32 [000652] ----------- \--* ADD long [000649] ----------- +--* LCL_VAR long V36 loc32 [000651] ----------- \--* CAST long <- int [000650] ----------- \--* CNS_INT int 1 Folding long operator with constant nodes into a constant: [000651] ----------- * CAST long <- int [000650] -----+----- \--* CNS_INT int 1 Bashed to long constant: [000651] ----------- * CNS_INT long 1 The assignment [000654] using V56 removes: Copy Assertion: V56 == V36 fgMorphTree BB180, STMT00143 (after) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 fgMorphTree BB180, STMT00145 (before) [000660] -A-XG------ * ASG int [000659] D------N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG------ \--* IND ubyte [000657] ----------- \--* LCL_VAR long V56 tmp16 GenTreeNode creates assertion: [000660] -A-XG+----- * ASG int In BB180 New Local Subrange Assertion: V57 in [0..255], index = #01 Morphing BB181 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB181, STMT00146 (before) [000664] -A--------- * ASG int [000663] D------N--- +--* LCL_VAR int V18 loc14 [000662] ----------- \--* LCL_VAR int V57 tmp17 GenTreeNode creates assertion: [000664] -A---+----- * ASG int In BB181 New Local Subrange Assertion: V18 in [0..65535], index = #01 fgMorphTree BB181, STMT00146 (after) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 Morphing BB182 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB182, STMT00147 (before) [000668] ----------- * JTRUE void [000667] ----------- \--* EQ int [000665] ----------- +--* LCL_VAR int V18 loc14 [000666] ----------- \--* CNS_INT int 0 Morphing BB183 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB183, STMT00390 (before) [001905] -A-XG------ * ASG int [001904] D------N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG------ \--* FIELD int : [000674] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [001903] ---XG------ * IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 fgMorphTree BB183, STMT00390 (after) [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 fgMorphTree BB183, STMT00392 (before) [001912] ---XG------ * JTRUE void [001911] N--XG----U- \--* GE int [001906] ----------- +--* LCL_VAR int V99 tmp59 [001942] ---XG------ \--* FIELD int : [001908] ---XG------ \--* FIELD_ADDR byref : [001907] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002857] -----+----- * ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [002858] ----------- * ADD long [002856] -----+----- +--* CNS_INT long 16 [002854] -----+----- \--* CNS_INT long 8 Bashed to long constant: [002858] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [001942] ---XG------ * IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 fgMorphTree BB183, STMT00392 (after) [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 Morphing BB185 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB185, STMT00394 (before) [001920] -A-XG------ * ASG byref [001919] D------N--- +--* LCL_VAR byref V100 tmp60 [001916] ---XG------ \--* FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [001916] ---XG------ * FIELD_ADDR byref : [001915] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [002864] ---X-O----- * COMMA byref [002860] ---X-O----- +--* NULLCHECK byte [002859] ----------- | \--* LCL_VAR byref V00 arg0 [002863] -----O----- \--* ADD byref [002861] -----O----- +--* LCL_VAR byref V00 arg0 [002862] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002864] ---X-+-N--- * COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 fgMorphTree BB185, STMT00394 (after) [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 fgMorphTree BB185, STMT00395 (before) [001933] -A-XGO----- * ASG short [001932] ---XGO-N--- +--* IND short [001930] ---XGO----- | \--* COMMA byref [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001917] ----------- | | +--* LCL_VAR int V99 tmp59 [001923] ----G------ | | \--* FIELD int : [001922] ----------- | | \--* LCL_VAR byref V100 tmp60 [001929] ----GO----- | \--* ADD byref [001928] ----G------ | +--* FIELD byref : [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 [001927] ----------- | \--* MUL long [001925] ---------U- | +--* CAST long <- uint [001918] ----------- | | \--* LCL_VAR int V99 tmp59 [001926] ----------- | \--* CNS_INT long 2 [001931] ----------- \--* LCL_VAR int V18 loc14 Final value of Compiler::fgMorphField after morphing: [001923] ---XG------ * IND int [002866] -----+----- \--* ADD byref [001922] -----+----- +--* LCL_VAR byref V100 tmp60 [002865] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [001928] ---XG------ * IND byref [001921] -----+----- \--* LCL_VAR byref V100 tmp60 fgMorphTree BB185, STMT00395 (after) [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 fgMorphTree BB185, STMT00396 (before) [001939] -A-XG------ * ASG int [001938] ---XG--N--- +--* FIELD int : [001934] ----------- | \--* LCL_VAR byref V00 arg0 [001937] ----------- \--* ADD int [001935] ----------- +--* LCL_VAR int V99 tmp59 [001936] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [001938] ---XG--N--- * IND int [002869] -----+----- \--* ADD byref [001934] -----+----- +--* LCL_VAR byref V00 arg0 [002868] -----+----- \--* CNS_INT long 8 fgMorphTree BB185, STMT00396 (after) [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 Morphing BB186 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB186, STMT00393 (before) [001914] --C-G------ * CALL r2r_ind void [001913] ----------- this +--* LCL_VAR byref V00 arg0 [000675] ----------- arg1 \--* LCL_VAR int V18 loc14 Initializing arg info for 1914.CALL: Args for call [001914] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[001913].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[002870].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[000675].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 1914.CALL: Sorting the arguments: Deferred argument ('x0'): [001913] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [000675] -----+----- * LCL_VAR int V18 loc14 Moved to late list Deferred argument ('x11'): [002870] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [001914].CALL after fgMorphArgs: CallArg[[001913].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[002870].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[000675].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB186, STMT00393 (after) [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB187 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB187, STMT00150 (before) [000680] ----------- * JTRUE void [000679] ----------- \--* EQ int [000677] ----------- +--* LCL_VAR int V12 loc8 [000678] ----------- \--* CNS_INT int 0 Morphing BB188 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB188, STMT00151 (before) [000684] ----------- * JTRUE void [000683] ----------- \--* LE int [000681] ----------- +--* LCL_VAR int V08 loc4 [000682] ----------- \--* CNS_INT int 1 Morphing BB189 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB189, STMT00152 (before) [000688] ----------- * JTRUE void [000687] ----------- \--* LT int [000685] ----------- +--* LCL_VAR int V20 loc16 [000686] ----------- \--* CNS_INT int 0 Morphing BB190 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB190, STMT00153 (before) [000708] ---XGO----- * JTRUE void [000707] N--XGO---U- \--* NE int [000689] ----------- +--* LCL_VAR int V08 loc4 [000706] ---XGO----- \--* ADD int [000704] ---XGO----- +--* IND int [000703] ---X-O----- | \--* COMMA byref [000697] ---X-O----- | +--* BOUNDS_CHECK_Rng void [000692] ----------- | | +--* LCL_VAR int V20 loc16 [000696] ----------- | | \--* LCL_VAR int V144 tmp104 [000702] -----O----- | \--* ADD byref [000701] ----------- | +--* LCL_VAR byref V143 tmp103 [000700] ----------- | \--* MUL long [000698] ---------U- | +--* CAST long <- uint [000693] ----------- | | \--* LCL_VAR int V20 loc16 [000699] ----------- | \--* CNS_INT long 4 [000705] ----------- \--* CNS_INT int 1 fgMorphTree BB190, STMT00153 (after) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 Morphing BB191 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB191, STMT00407 (before) [001999] -A-XG------ * ASG ref [001998] D------N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG------ \--* FIELD ref : [000710] ----------- \--* LCL_VAR ref V03 arg3 Final value of Compiler::fgMorphField after morphing: [001946] ---XG------ * IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] GenTreeNode creates assertion: [001946] ---XG+----- * IND ref In BB191 New Local Constant Assertion: V03 != null, index = #01 fgMorphTree BB191, STMT00407 (after) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] fgMorphTree BB191, STMT00398 (before) [001951] ----------- * JTRUE void [001950] ----------- \--* EQ int [001948] ----------- +--* LCL_VAR ref V102 tmp62 [001949] ----------- \--* CNS_INT ref null Morphing BB194 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB194, STMT00399 (before) [001954] -A-XG------ * ASG int [001953] D------N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG------ \--* FIELD int : [000709] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [001952] ---XG------ * IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 fgMorphTree BB194, STMT00399 (after) [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 fgMorphTree BB194, STMT00400 (before) [001959] ---X------- * JTRUE void [001958] N--X-----U- \--* NE int [001956] ---X------- +--* ARR_LENGTH int [001955] ----------- | \--* LCL_VAR ref V102 tmp62 [001957] ----------- \--* CNS_INT int 1 GenTreeNode creates assertion: [001956] ---X-+----- * ARR_LENGTH int In BB194 New Local Constant Assertion: V102 != null, index = #01 Morphing BB195 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB195, STMT00403 (before) [001969] ---XG------ * JTRUE void [001968] N--XG----U- \--* GE int [001963] ----------- +--* LCL_VAR int V103 tmp63 [002002] ---XG------ \--* FIELD int : [001965] ---XG------ \--* FIELD_ADDR byref : [001964] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002879] -----+----- * ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [002880] ----------- * ADD long [002878] -----+----- +--* CNS_INT long 16 [002876] -----+----- \--* CNS_INT long 8 Bashed to long constant: [002880] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002002] ---XG------ * IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 fgMorphTree BB195, STMT00403 (after) [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 Morphing BB196 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB196, STMT00404 (before) [001975] -A-XG------ * ASG byref [001974] D------N--- +--* LCL_VAR byref V104 tmp64 [001971] ---XG------ \--* FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [001971] ---XG------ * FIELD_ADDR byref : [001970] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [002886] ---X-O----- * COMMA byref [002882] ---X-O----- +--* NULLCHECK byte [002881] ----------- | \--* LCL_VAR byref V00 arg0 [002885] -----O----- \--* ADD byref [002883] -----O----- +--* LCL_VAR byref V00 arg0 [002884] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002886] ---X-+-N--- * COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 fgMorphTree BB196, STMT00404 (after) [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 fgMorphTree BB196, STMT00405 (before) [001991] -A-XGO----- * ASG short [001990] ---XGO-N--- +--* IND short [001985] ---XGO----- | \--* COMMA byref [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void [001972] ----------- | | +--* LCL_VAR int V103 tmp63 [001978] ----G------ | | \--* FIELD int : [001977] ----------- | | \--* LCL_VAR byref V104 tmp64 [001984] ----GO----- | \--* ADD byref [001983] ----G------ | +--* FIELD byref : [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 [001982] ----------- | \--* MUL long [001980] ---------U- | +--* CAST long <- uint [001973] ----------- | | \--* LCL_VAR int V103 tmp63 [001981] ----------- | \--* CNS_INT long 2 [001989] n--XG------ \--* IND ushort [001988] ---XG------ \--* INDEX_ADDR byref ushort[] [001986] ----------- +--* LCL_VAR ref V102 tmp62 [001987] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [001978] ---XG------ * IND int [002888] -----+----- \--* ADD byref [001977] -----+----- +--* LCL_VAR byref V104 tmp64 [002887] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [001983] ---XG------ * IND byref [001976] -----+----- \--* LCL_VAR byref V104 tmp64 fgMorphIndexAddr (before remorph): [002900] ---X-O----- * COMMA byref [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void [001987] ----------- | +--* CNS_INT int 0 [002892] ---X------- | \--* ARR_LENGTH int [001986] ----------- | \--* LCL_VAR ref V102 tmp62 [002899] -----O----- \--* ARR_ADDR byref ushort[] [002898] ----------- \--* ADD byref [002897] ----------- +--* ADD byref [002890] ----------- | +--* LCL_VAR ref V102 tmp62 [002896] ----------- | \--* CNS_INT long 12 [002895] ----------- \--* MUL long [002891] ----------- +--* CNS_INT long 0 [002894] -------N--- \--* CNS_INT long 2 GenTreeNode creates assertion: [002892] ---X-+----- * ARR_LENGTH int In BB196 New Local Constant Assertion: V102 != null, index = #01 Folding long operator with constant nodes into a constant: [002895] ----------- * MUL long [002891] -----+----- +--* CNS_INT long 0 [002894] -----+-N--- \--* CNS_INT long 2 Bashed to long constant: [002895] ----------- * CNS_INT long 0 Folding long operator with constant nodes into a constant: [002901] ----------- * ADD long [002896] -----+----- +--* CNS_INT long 12 [002895] -----+----- \--* CNS_INT long 0 Bashed to long constant: [002901] ----------- * CNS_INT long 12 fgMorphIndexAddr (after remorph): [002900] ---X-+----- * COMMA byref [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 fgMorphTree BB196, STMT00405 (after) [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 fgMorphTree BB196, STMT00406 (before) [001997] -A-XG------ * ASG int [001996] ---XG--N--- +--* FIELD int : [001992] ----------- | \--* LCL_VAR byref V00 arg0 [001995] ----------- \--* ADD int [001993] ----------- +--* LCL_VAR int V103 tmp63 [001994] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [001996] ---XG--N--- * IND int [002904] -----+----- \--* ADD byref [001992] -----+----- +--* LCL_VAR byref V00 arg0 [002903] -----+----- \--* CNS_INT long 8 fgMorphTree BB196, STMT00406 (after) [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 Morphing BB197 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB197, STMT00401 (before) [001962] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] ----------- this +--* LCL_VAR byref V00 arg0 [001961] ----------- arg1 \--* LCL_VAR ref V102 tmp62 Initializing arg info for 1962.CALL: Args for call [001962] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[001960].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[002905].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[001961].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8] Morphing args for 1962.CALL: Sorting the arguments: Deferred argument ('x0'): [001960] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [001961] -----+----- * LCL_VAR ref V102 tmp62 Moved to late list Deferred argument ('x11'): [002905] H----+----- * CNS_INT(h) long 0x4000000000431d58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [001962].CALL after fgMorphArgs: CallArg[[001960].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[002905].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[001961].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB197, STMT00401 (after) [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn Morphing BB198 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB198, STMT00156 (before) [000718] -A--------- * ASG int [000717] D------N--- +--* LCL_VAR int V20 loc16 [000716] ----------- \--* SUB int [000714] ----------- +--* LCL_VAR int V20 loc16 [000715] ----------- \--* CNS_INT int 1 fgMorphTree BB198, STMT00156 (after) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 Morphing BB199 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB199, STMT00148 (before) [000673] -A--------- * ASG int [000672] D------N--- +--* LCL_VAR int V08 loc4 [000671] ----------- \--* SUB int [000669] ----------- +--* LCL_VAR int V08 loc4 [000670] ----------- \--* CNS_INT int 1 fgMorphTree BB199, STMT00148 (after) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 Morphing BB200 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB200, STMT00132 (before) [000612] ----------- * JTRUE void [000611] ----------- \--* NE int [000609] ----------- +--* OR int [000607] ----------- | +--* NE int [000605] ----------- | | +--* LCL_VAR int V08 loc4 [000606] ----------- | | \--* CNS_INT int 0 [000608] ----------- | \--* LCL_VAR int V21 loc17 [000610] ----------- \--* CNS_INT int 0 Morphing BB201 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB201, STMT00133 (before) [000616] ----------- * JTRUE void [000615] ----------- \--* LT int [000613] ----------- +--* LCL_VAR int V07 loc3 [000614] ----------- \--* CNS_INT int 0 Morphing BB202 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB202, STMT00137 (before) [000628] ----------- * JTRUE void [000627] ----------- \--* GE int [000625] ----------- +--* LCL_VAR int V05 loc1 [000626] ----------- \--* LCL_VAR int V04 loc0 Morphing BB203 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB203, STMT00138 (before) [000633] ---XG------ * JTRUE void [000632] ---XG------ \--* EQ int [000630] ---XG------ +--* IND ubyte [000629] ----------- | \--* LCL_VAR long V36 loc32 [000631] ----------- \--* CNS_INT int 0 Morphing BB204 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB204, STMT00418 (before) [002059] -A-XG------ * ASG ref [002058] D------N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG------ \--* FIELD ref : [000618] ----------- \--* LCL_VAR ref V03 arg3 Final value of Compiler::fgMorphField after morphing: [002006] ---XG------ * IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] GenTreeNode creates assertion: [002006] ---XG+----- * IND ref In BB204 New Local Constant Assertion: V03 != null, index = #01 fgMorphTree BB204, STMT00418 (after) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] fgMorphTree BB204, STMT00409 (before) [002011] ----------- * JTRUE void [002010] ----------- \--* EQ int [002008] ----------- +--* LCL_VAR ref V106 tmp66 [002009] ----------- \--* CNS_INT ref null Morphing BB207 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB207, STMT00410 (before) [002014] -A-XG------ * ASG int [002013] D------N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG------ \--* FIELD int : [000617] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002012] ---XG------ * IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 fgMorphTree BB207, STMT00410 (after) [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 fgMorphTree BB207, STMT00411 (before) [002019] ---X------- * JTRUE void [002018] N--X-----U- \--* NE int [002016] ---X------- +--* ARR_LENGTH int [002015] ----------- | \--* LCL_VAR ref V106 tmp66 [002017] ----------- \--* CNS_INT int 1 GenTreeNode creates assertion: [002016] ---X-+----- * ARR_LENGTH int In BB207 New Local Constant Assertion: V106 != null, index = #01 Morphing BB208 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB208, STMT00414 (before) [002029] ---XG------ * JTRUE void [002028] N--XG----U- \--* GE int [002023] ----------- +--* LCL_VAR int V107 tmp67 [002062] ---XG------ \--* FIELD int : [002025] ---XG------ \--* FIELD_ADDR byref : [002024] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002913] -----+----- * ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [002914] ----------- * ADD long [002912] -----+----- +--* CNS_INT long 16 [002910] -----+----- \--* CNS_INT long 8 Bashed to long constant: [002914] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002062] ---XG------ * IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 fgMorphTree BB208, STMT00414 (after) [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 Morphing BB209 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB209, STMT00415 (before) [002035] -A-XG------ * ASG byref [002034] D------N--- +--* LCL_VAR byref V108 tmp68 [002031] ---XG------ \--* FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002031] ---XG------ * FIELD_ADDR byref : [002030] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [002920] ---X-O----- * COMMA byref [002916] ---X-O----- +--* NULLCHECK byte [002915] ----------- | \--* LCL_VAR byref V00 arg0 [002919] -----O----- \--* ADD byref [002917] -----O----- +--* LCL_VAR byref V00 arg0 [002918] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002920] ---X-+-N--- * COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 fgMorphTree BB209, STMT00415 (after) [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 fgMorphTree BB209, STMT00416 (before) [002051] -A-XGO----- * ASG short [002050] ---XGO-N--- +--* IND short [002045] ---XGO----- | \--* COMMA byref [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002032] ----------- | | +--* LCL_VAR int V107 tmp67 [002038] ----G------ | | \--* FIELD int : [002037] ----------- | | \--* LCL_VAR byref V108 tmp68 [002044] ----GO----- | \--* ADD byref [002043] ----G------ | +--* FIELD byref : [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 [002042] ----------- | \--* MUL long [002040] ---------U- | +--* CAST long <- uint [002033] ----------- | | \--* LCL_VAR int V107 tmp67 [002041] ----------- | \--* CNS_INT long 2 [002049] n--XG------ \--* IND ushort [002048] ---XG------ \--* INDEX_ADDR byref ushort[] [002046] ----------- +--* LCL_VAR ref V106 tmp66 [002047] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [002038] ---XG------ * IND int [002922] -----+----- \--* ADD byref [002037] -----+----- +--* LCL_VAR byref V108 tmp68 [002921] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002043] ---XG------ * IND byref [002036] -----+----- \--* LCL_VAR byref V108 tmp68 fgMorphIndexAddr (before remorph): [002934] ---X-O----- * COMMA byref [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void [002047] ----------- | +--* CNS_INT int 0 [002926] ---X------- | \--* ARR_LENGTH int [002046] ----------- | \--* LCL_VAR ref V106 tmp66 [002933] -----O----- \--* ARR_ADDR byref ushort[] [002932] ----------- \--* ADD byref [002931] ----------- +--* ADD byref [002924] ----------- | +--* LCL_VAR ref V106 tmp66 [002930] ----------- | \--* CNS_INT long 12 [002929] ----------- \--* MUL long [002925] ----------- +--* CNS_INT long 0 [002928] -------N--- \--* CNS_INT long 2 GenTreeNode creates assertion: [002926] ---X-+----- * ARR_LENGTH int In BB209 New Local Constant Assertion: V106 != null, index = #01 Folding long operator with constant nodes into a constant: [002929] ----------- * MUL long [002925] -----+----- +--* CNS_INT long 0 [002928] -----+-N--- \--* CNS_INT long 2 Bashed to long constant: [002929] ----------- * CNS_INT long 0 Folding long operator with constant nodes into a constant: [002935] ----------- * ADD long [002930] -----+----- +--* CNS_INT long 12 [002929] -----+----- \--* CNS_INT long 0 Bashed to long constant: [002935] ----------- * CNS_INT long 12 fgMorphIndexAddr (after remorph): [002934] ---X-+----- * COMMA byref [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 fgMorphTree BB209, STMT00416 (after) [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 fgMorphTree BB209, STMT00417 (before) [002057] -A-XG------ * ASG int [002056] ---XG--N--- +--* FIELD int : [002052] ----------- | \--* LCL_VAR byref V00 arg0 [002055] ----------- \--* ADD int [002053] ----------- +--* LCL_VAR int V107 tmp67 [002054] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002056] ---XG--N--- * IND int [002938] -----+----- \--* ADD byref [002052] -----+----- +--* LCL_VAR byref V00 arg0 [002937] -----+----- \--* CNS_INT long 8 fgMorphTree BB209, STMT00417 (after) [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 Morphing BB210 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB210, STMT00412 (before) [002022] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] ----------- this +--* LCL_VAR byref V00 arg0 [002021] ----------- arg1 \--* LCL_VAR ref V106 tmp66 Initializing arg info for 2022.CALL: Args for call [002022] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002020].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[002939].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[002021].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2022.CALL: Sorting the arguments: Deferred argument ('x0'): [002020] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [002021] -----+----- * LCL_VAR ref V106 tmp66 Moved to late list Deferred argument ('x11'): [002939] H----+----- * CNS_INT(h) long 0x4000000000431d58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002022].CALL after fgMorphArgs: CallArg[[002020].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[002939].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002021].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB210, STMT00412 (after) [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn Morphing BB211 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB211, STMT00136 (before) [000624] -A--------- * ASG int [000623] D------N--- +--* LCL_VAR int V21 loc17 [000622] ----------- \--* CNS_INT int 1 Folding operator with constant nodes into a constant: [002940] ----------- * CAST int <- bool <- int [000622] -----+----- \--* CNS_INT int 1 Bashed to int constant: [002940] ----------- * CNS_INT int 1 GenTreeNode creates assertion: [000624] -A---+----- * ASG int In BB211 New Local Constant Assertion: V21 == 1, index = #01 Morphing BB213 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB213, STMT00420 (before) [002071] ----------- * JTRUE void [002070] ----------- \--* EQ int [002068] ----------- +--* LCL_VAR ref V110 tmp70 [002069] ----------- \--* CNS_INT ref null Morphing BB215 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB215, STMT00421 (before) [002074] -A-XG------ * ASG int [002073] D------N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG------ \--* FIELD int : [000585] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002072] ---XG------ * IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 fgMorphTree BB215, STMT00421 (after) [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 fgMorphTree BB215, STMT00422 (before) [002079] ---X------- * JTRUE void [002078] N--X-----U- \--* NE int [002076] ---X------- +--* ARR_LENGTH int [002075] ----------- | \--* LCL_VAR ref V110 tmp70 [002077] ----------- \--* CNS_INT int 1 GenTreeNode creates assertion: [002076] ---X-+----- * ARR_LENGTH int In BB215 New Local Constant Assertion: V110 != null, index = #01 Morphing BB216 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB216, STMT00425 (before) [002089] ---XG------ * JTRUE void [002088] N--XG----U- \--* GE int [002083] ----------- +--* LCL_VAR int V111 tmp71 [002122] ---XG------ \--* FIELD int : [002085] ---XG------ \--* FIELD_ADDR byref : [002084] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002946] -----+----- * ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [002947] ----------- * ADD long [002945] -----+----- +--* CNS_INT long 16 [002943] -----+----- \--* CNS_INT long 8 Bashed to long constant: [002947] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002122] ---XG------ * IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 fgMorphTree BB216, STMT00425 (after) [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 Morphing BB217 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB217, STMT00426 (before) [002095] -A-XG------ * ASG byref [002094] D------N--- +--* LCL_VAR byref V112 tmp72 [002091] ---XG------ \--* FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002091] ---XG------ * FIELD_ADDR byref : [002090] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [002953] ---X-O----- * COMMA byref [002949] ---X-O----- +--* NULLCHECK byte [002948] ----------- | \--* LCL_VAR byref V00 arg0 [002952] -----O----- \--* ADD byref [002950] -----O----- +--* LCL_VAR byref V00 arg0 [002951] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002953] ---X-+-N--- * COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 fgMorphTree BB217, STMT00426 (after) [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 fgMorphTree BB217, STMT00427 (before) [002111] -A-XGO----- * ASG short [002110] ---XGO-N--- +--* IND short [002105] ---XGO----- | \--* COMMA byref [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002092] ----------- | | +--* LCL_VAR int V111 tmp71 [002098] ----G------ | | \--* FIELD int : [002097] ----------- | | \--* LCL_VAR byref V112 tmp72 [002104] ----GO----- | \--* ADD byref [002103] ----G------ | +--* FIELD byref : [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 [002102] ----------- | \--* MUL long [002100] ---------U- | +--* CAST long <- uint [002093] ----------- | | \--* LCL_VAR int V111 tmp71 [002101] ----------- | \--* CNS_INT long 2 [002109] n--XG------ \--* IND ushort [002108] ---XG------ \--* INDEX_ADDR byref ushort[] [002106] ----------- +--* LCL_VAR ref V110 tmp70 [002107] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [002098] ---XG------ * IND int [002955] -----+----- \--* ADD byref [002097] -----+----- +--* LCL_VAR byref V112 tmp72 [002954] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002103] ---XG------ * IND byref [002096] -----+----- \--* LCL_VAR byref V112 tmp72 fgMorphIndexAddr (before remorph): [002967] ---X-O----- * COMMA byref [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void [002107] ----------- | +--* CNS_INT int 0 [002959] ---X------- | \--* ARR_LENGTH int [002106] ----------- | \--* LCL_VAR ref V110 tmp70 [002966] -----O----- \--* ARR_ADDR byref ushort[] [002965] ----------- \--* ADD byref [002964] ----------- +--* ADD byref [002957] ----------- | +--* LCL_VAR ref V110 tmp70 [002963] ----------- | \--* CNS_INT long 12 [002962] ----------- \--* MUL long [002958] ----------- +--* CNS_INT long 0 [002961] -------N--- \--* CNS_INT long 2 GenTreeNode creates assertion: [002959] ---X-+----- * ARR_LENGTH int In BB217 New Local Constant Assertion: V110 != null, index = #01 Folding long operator with constant nodes into a constant: [002962] ----------- * MUL long [002958] -----+----- +--* CNS_INT long 0 [002961] -----+-N--- \--* CNS_INT long 2 Bashed to long constant: [002962] ----------- * CNS_INT long 0 Folding long operator with constant nodes into a constant: [002968] ----------- * ADD long [002963] -----+----- +--* CNS_INT long 12 [002962] -----+----- \--* CNS_INT long 0 Bashed to long constant: [002968] ----------- * CNS_INT long 12 fgMorphIndexAddr (after remorph): [002967] ---X-+----- * COMMA byref [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 fgMorphTree BB217, STMT00427 (after) [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 fgMorphTree BB217, STMT00428 (before) [002117] -A-XG------ * ASG int [002116] ---XG--N--- +--* FIELD int : [002112] ----------- | \--* LCL_VAR byref V00 arg0 [002115] ----------- \--* ADD int [002113] ----------- +--* LCL_VAR int V111 tmp71 [002114] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002116] ---XG--N--- * IND int [002971] -----+----- \--* ADD byref [002112] -----+----- +--* LCL_VAR byref V00 arg0 [002970] -----+----- \--* CNS_INT long 8 fgMorphTree BB217, STMT00428 (after) [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 Morphing BB218 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB218, STMT00423 (before) [002082] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] ----------- this +--* LCL_VAR byref V00 arg0 [002081] ----------- arg1 \--* LCL_VAR ref V110 tmp70 Initializing arg info for 2082.CALL: Args for call [002082] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002080].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[002972].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[002081].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2082.CALL: Sorting the arguments: Deferred argument ('x0'): [002080] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [002081] -----+----- * LCL_VAR ref V110 tmp70 Moved to late list Deferred argument ('x11'): [002972] H----+----- * CNS_INT(h) long 0x4000000000431d58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002082].CALL after fgMorphArgs: CallArg[[002080].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[002972].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002081].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB218, STMT00423 (after) [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn Morphing BB220 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB220, STMT00440 (before) [002179] -A-XG------ * ASG ref [002178] D------N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG------ \--* FIELD ref : [000635] ----------- \--* LCL_VAR ref V03 arg3 Final value of Compiler::fgMorphField after morphing: [002126] ---XG------ * IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] GenTreeNode creates assertion: [002126] ---XG+----- * IND ref In BB220 New Local Constant Assertion: V03 != null, index = #01 fgMorphTree BB220, STMT00440 (after) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] fgMorphTree BB220, STMT00431 (before) [002131] ----------- * JTRUE void [002130] ----------- \--* EQ int [002128] ----------- +--* LCL_VAR ref V114 tmp74 [002129] ----------- \--* CNS_INT ref null Morphing BB223 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB223, STMT00432 (before) [002134] -A-XG------ * ASG int [002133] D------N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG------ \--* FIELD int : [000634] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002132] ---XG------ * IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 fgMorphTree BB223, STMT00432 (after) [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 fgMorphTree BB223, STMT00433 (before) [002139] ---X------- * JTRUE void [002138] N--X-----U- \--* NE int [002136] ---X------- +--* ARR_LENGTH int [002135] ----------- | \--* LCL_VAR ref V114 tmp74 [002137] ----------- \--* CNS_INT int 1 GenTreeNode creates assertion: [002136] ---X-+----- * ARR_LENGTH int In BB223 New Local Constant Assertion: V114 != null, index = #01 Morphing BB224 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB224, STMT00436 (before) [002149] ---XG------ * JTRUE void [002148] N--XG----U- \--* GE int [002143] ----------- +--* LCL_VAR int V115 tmp75 [002182] ---XG------ \--* FIELD int : [002145] ---XG------ \--* FIELD_ADDR byref : [002144] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002980] -----+----- * ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [002981] ----------- * ADD long [002979] -----+----- +--* CNS_INT long 16 [002977] -----+----- \--* CNS_INT long 8 Bashed to long constant: [002981] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002182] ---XG------ * IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 fgMorphTree BB224, STMT00436 (after) [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 Morphing BB225 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB225, STMT00437 (before) [002155] -A-XG------ * ASG byref [002154] D------N--- +--* LCL_VAR byref V116 tmp76 [002151] ---XG------ \--* FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002151] ---XG------ * FIELD_ADDR byref : [002150] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [002987] ---X-O----- * COMMA byref [002983] ---X-O----- +--* NULLCHECK byte [002982] ----------- | \--* LCL_VAR byref V00 arg0 [002986] -----O----- \--* ADD byref [002984] -----O----- +--* LCL_VAR byref V00 arg0 [002985] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [002987] ---X-+-N--- * COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 fgMorphTree BB225, STMT00437 (after) [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 fgMorphTree BB225, STMT00438 (before) [002171] -A-XGO----- * ASG short [002170] ---XGO-N--- +--* IND short [002165] ---XGO----- | \--* COMMA byref [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002152] ----------- | | +--* LCL_VAR int V115 tmp75 [002158] ----G------ | | \--* FIELD int : [002157] ----------- | | \--* LCL_VAR byref V116 tmp76 [002164] ----GO----- | \--* ADD byref [002163] ----G------ | +--* FIELD byref : [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 [002162] ----------- | \--* MUL long [002160] ---------U- | +--* CAST long <- uint [002153] ----------- | | \--* LCL_VAR int V115 tmp75 [002161] ----------- | \--* CNS_INT long 2 [002169] n--XG------ \--* IND ushort [002168] ---XG------ \--* INDEX_ADDR byref ushort[] [002166] ----------- +--* LCL_VAR ref V114 tmp74 [002167] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [002158] ---XG------ * IND int [002989] -----+----- \--* ADD byref [002157] -----+----- +--* LCL_VAR byref V116 tmp76 [002988] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002163] ---XG------ * IND byref [002156] -----+----- \--* LCL_VAR byref V116 tmp76 fgMorphIndexAddr (before remorph): [003001] ---X-O----- * COMMA byref [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void [002167] ----------- | +--* CNS_INT int 0 [002993] ---X------- | \--* ARR_LENGTH int [002166] ----------- | \--* LCL_VAR ref V114 tmp74 [003000] -----O----- \--* ARR_ADDR byref ushort[] [002999] ----------- \--* ADD byref [002998] ----------- +--* ADD byref [002991] ----------- | +--* LCL_VAR ref V114 tmp74 [002997] ----------- | \--* CNS_INT long 12 [002996] ----------- \--* MUL long [002992] ----------- +--* CNS_INT long 0 [002995] -------N--- \--* CNS_INT long 2 GenTreeNode creates assertion: [002993] ---X-+----- * ARR_LENGTH int In BB225 New Local Constant Assertion: V114 != null, index = #01 Folding long operator with constant nodes into a constant: [002996] ----------- * MUL long [002992] -----+----- +--* CNS_INT long 0 [002995] -----+-N--- \--* CNS_INT long 2 Bashed to long constant: [002996] ----------- * CNS_INT long 0 Folding long operator with constant nodes into a constant: [003002] ----------- * ADD long [002997] -----+----- +--* CNS_INT long 12 [002996] -----+----- \--* CNS_INT long 0 Bashed to long constant: [003002] ----------- * CNS_INT long 12 fgMorphIndexAddr (after remorph): [003001] ---X-+----- * COMMA byref [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 fgMorphTree BB225, STMT00438 (after) [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 fgMorphTree BB225, STMT00439 (before) [002177] -A-XG------ * ASG int [002176] ---XG--N--- +--* FIELD int : [002172] ----------- | \--* LCL_VAR byref V00 arg0 [002175] ----------- \--* ADD int [002173] ----------- +--* LCL_VAR int V115 tmp75 [002174] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002176] ---XG--N--- * IND int [003005] -----+----- \--* ADD byref [002172] -----+----- +--* LCL_VAR byref V00 arg0 [003004] -----+----- \--* CNS_INT long 8 fgMorphTree BB225, STMT00439 (after) [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 Morphing BB226 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB226, STMT00434 (before) [002142] --C-G------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] ----------- this +--* LCL_VAR byref V00 arg0 [002141] ----------- arg1 \--* LCL_VAR ref V114 tmp74 Initializing arg info for 2142.CALL: Args for call [002142] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002140].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003006].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[002141].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2142.CALL: Sorting the arguments: Deferred argument ('x0'): [002140] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [002141] -----+----- * LCL_VAR ref V114 tmp74 Moved to late list Deferred argument ('x11'): [003006] H----+----- * CNS_INT(h) long 0x4000000000431d58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002142].CALL after fgMorphArgs: CallArg[[002140].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003006].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002141].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB226, STMT00434 (after) [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn Morphing BB228 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB228, STMT00174 (before) [000812] -A--------- * ASG int [000811] D------N--- +--* LCL_VAR int V59 tmp19 [000805] ----------- \--* LCL_VAR int V16 loc12 GenTreeNode creates assertion: [000812] -A---+----- * ASG int In BB228 New Local Copy Assertion: V59 == V16, index = #01 fgMorphTree BB228, STMT00173 (before) [000810] -A--------- * ASG int [000809] D------N--- +--* LCL_VAR int V16 loc12 [000808] ----------- \--* ADD int [000806] ----------- +--* LCL_VAR int V16 loc12 [000807] ----------- \--* CNS_INT int 1 The assignment [000810] using V59 removes: Copy Assertion: V59 == V16 fgMorphTree BB228, STMT00449 (before) [002225] -A-XG------ * ASG ushort [002224] D------N--- +--* LCL_VAR ushort V119 tmp79 [000819] ---XG------ \--* IND ushort [000818] ----------- \--* ADD long [000804] ----------- +--* LCL_VAR long V34 loc30 [000817] ----------- \--* MUL long [000814] ----------- +--* CAST long <- int [000813] ----------- | \--* LCL_VAR int V59 tmp19 [000816] ----------- \--* CAST long <- int [000815] ----------- \--* CNS_INT int 2 Folding long operator with constant nodes into a constant: [000816] ----------- * CAST long <- int [000815] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000816] ----------- * CNS_INT long 2 GenTreeNode creates assertion: [002225] -A-XG+----- * ASG ushort In BB228 New Local Subrange Assertion: V119 in [0..65535], index = #01 fgMorphTree BB228, STMT00449 (after) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 fgMorphTree BB228, STMT00442 (before) [002188] -A-XG------ * ASG int [002187] D------N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG------ \--* FIELD int : [000803] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002186] ---XG------ * IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 fgMorphTree BB228, STMT00442 (after) [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 fgMorphTree BB228, STMT00444 (before) [002195] ---XG------ * JTRUE void [002194] N--XG----U- \--* GE int [002189] ----------- +--* LCL_VAR int V118 tmp78 [002228] ---XG------ \--* FIELD int : [002191] ---XG------ \--* FIELD_ADDR byref : [002190] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [003012] -----+----- * ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [003013] ----------- * ADD long [003011] -----+----- +--* CNS_INT long 16 [003009] -----+----- \--* CNS_INT long 8 Bashed to long constant: [003013] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002228] ---XG------ * IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 fgMorphTree BB228, STMT00444 (after) [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 Morphing BB230 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB230, STMT00446 (before) [002204] -A-XG------ * ASG byref [002203] D------N--- +--* LCL_VAR byref V120 tmp80 [002200] ---XG------ \--* FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002200] ---XG------ * FIELD_ADDR byref : [002199] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [003019] ---X-O----- * COMMA byref [003015] ---X-O----- +--* NULLCHECK byte [003014] ----------- | \--* LCL_VAR byref V00 arg0 [003018] -----O----- \--* ADD byref [003016] -----O----- +--* LCL_VAR byref V00 arg0 [003017] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [003019] ---X-+-N--- * COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 fgMorphTree BB230, STMT00446 (after) [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 fgMorphTree BB230, STMT00447 (before) [002217] -A-XGO----- * ASG short [002216] ---XGO-N--- +--* IND short [002214] ---XGO----- | \--* COMMA byref [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002201] ----------- | | +--* LCL_VAR int V118 tmp78 [002207] ----G------ | | \--* FIELD int : [002206] ----------- | | \--* LCL_VAR byref V120 tmp80 [002213] ----GO----- | \--* ADD byref [002212] ----G------ | +--* FIELD byref : [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 [002211] ----------- | \--* MUL long [002209] ---------U- | +--* CAST long <- uint [002202] ----------- | | \--* LCL_VAR int V118 tmp78 [002210] ----------- | \--* CNS_INT long 2 [002215] ----------- \--* LCL_VAR int V119 tmp79 Final value of Compiler::fgMorphField after morphing: [002207] ---XG------ * IND int [003021] -----+----- \--* ADD byref [002206] -----+----- +--* LCL_VAR byref V120 tmp80 [003020] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002212] ---XG------ * IND byref [002205] -----+----- \--* LCL_VAR byref V120 tmp80 fgMorphTree BB230, STMT00447 (after) [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 fgMorphTree BB230, STMT00448 (before) [002223] -A-XG------ * ASG int [002222] ---XG--N--- +--* FIELD int : [002218] ----------- | \--* LCL_VAR byref V00 arg0 [002221] ----------- \--* ADD int [002219] ----------- +--* LCL_VAR int V118 tmp78 [002220] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002222] ---XG--N--- * IND int [003024] -----+----- \--* ADD byref [002218] -----+----- +--* LCL_VAR byref V00 arg0 [003023] -----+----- \--* CNS_INT long 8 fgMorphTree BB230, STMT00448 (after) [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 Morphing BB231 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB231, STMT00445 (before) [002198] --C-G------ * CALL r2r_ind void [002196] ----------- this +--* LCL_VAR byref V00 arg0 [002197] ----------- arg1 \--* LCL_VAR int V119 tmp79 Initializing arg info for 2198.CALL: Args for call [002198] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002196].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003025].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[002197].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2198.CALL: Sorting the arguments: Deferred argument ('x0'): [002196] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [002197] -----+----- * LCL_VAR int V119 tmp79 Moved to late list Deferred argument ('x11'): [003025] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002198].CALL after fgMorphArgs: CallArg[[002196].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003025].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002197].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB231, STMT00445 (after) [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB233 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB233, STMT00166 (before) [000757] --C-------- * JTRUE void [000756] --C-------- \--* GE int [000751] ----------- +--* LCL_VAR int V16 loc12 [002234] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB234 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB234, STMT00171 (before) [000791] ---XG------ * JTRUE void [000790] ---XG------ \--* EQ int [000788] ---XG------ +--* IND ushort [000787] ----------- | \--* ADD long [000781] ----------- | +--* LCL_VAR long V34 loc30 [000786] ----------- | \--* MUL long [000783] ----------- | +--* CAST long <- int [000782] ----------- | | \--* LCL_VAR int V16 loc12 [000785] ----------- | \--* CAST long <- int [000784] ----------- | \--* CNS_INT int 2 [000789] ----------- \--* CNS_INT int 0 Folding long operator with constant nodes into a constant: [000785] ----------- * CAST long <- int [000784] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000785] ----------- * CNS_INT long 2 fgMorphTree BB234, STMT00171 (after) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 Morphing BB235 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB235, STMT00172 (before) [000802] ---XG------ * JTRUE void [000801] N--XG----U- \--* NE int [000799] ---XG------ +--* IND ushort [000798] ----------- | \--* ADD long [000792] ----------- | +--* LCL_VAR long V34 loc30 [000797] ----------- | \--* MUL long [000794] ----------- | +--* CAST long <- int [000793] ----------- | | \--* LCL_VAR int V16 loc12 [000796] ----------- | \--* CAST long <- int [000795] ----------- | \--* CNS_INT int 2 [000800] ----------- \--* LCL_VAR int V18 loc14 Folding long operator with constant nodes into a constant: [000796] ----------- * CAST long <- int [000795] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000796] ----------- * CNS_INT long 2 fgMorphTree BB235, STMT00172 (after) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 Morphing BB236 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB236, STMT00168 (before) [000764] --C-------- * JTRUE void [000763] --C-------- \--* GE int [000758] ----------- +--* LCL_VAR int V16 loc12 [002238] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB237 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB237, STMT00169 (before) [000775] ---XG------ * JTRUE void [000774] ---XG------ \--* EQ int [000772] ---XG------ +--* IND ushort [000771] ----------- | \--* ADD long [000765] ----------- | +--* LCL_VAR long V34 loc30 [000770] ----------- | \--* MUL long [000767] ----------- | +--* CAST long <- int [000766] ----------- | | \--* LCL_VAR int V16 loc12 [000769] ----------- | \--* CAST long <- int [000768] ----------- | \--* CNS_INT int 2 [000773] ----------- \--* CNS_INT int 0 Folding long operator with constant nodes into a constant: [000769] ----------- * CAST long <- int [000768] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000769] ----------- * CNS_INT long 2 fgMorphTree BB237, STMT00169 (after) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 Morphing BB238 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB238, STMT00170 (before) [000780] -A--------- * ASG int [000779] D------N--- +--* LCL_VAR int V16 loc12 [000778] ----------- \--* ADD int [000776] ----------- +--* LCL_VAR int V16 loc12 [000777] ----------- \--* CNS_INT int 1 Morphing BB239 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB239, STMT00074 (before) [000289] --C-------- * JTRUE void [000288] --C-------- \--* GE int [000283] ----------- +--* LCL_VAR int V16 loc12 [002242] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB240 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB240, STMT00075 (before) [000300] ---XG------ * JTRUE void [000299] ---XG------ \--* EQ int [000297] ---XG------ +--* IND ushort [000296] ----------- | \--* ADD long [000290] ----------- | +--* LCL_VAR long V34 loc30 [000295] ----------- | \--* MUL long [000292] ----------- | +--* CAST long <- int [000291] ----------- | | \--* LCL_VAR int V16 loc12 [000294] ----------- | \--* CAST long <- int [000293] ----------- | \--* CNS_INT int 2 [000298] ----------- \--* CNS_INT int 0 Folding long operator with constant nodes into a constant: [000294] ----------- * CAST long <- int [000293] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000294] ----------- * CNS_INT long 2 fgMorphTree BB240, STMT00075 (after) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 Morphing BB241 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB241, STMT00077 (before) [000310] -A--------- * ASG int [000309] D------N--- +--* LCL_VAR int V51 tmp11 [000303] ----------- \--* LCL_VAR int V16 loc12 GenTreeNode creates assertion: [000310] -A---+----- * ASG int In BB241 New Local Copy Assertion: V51 == V16, index = #01 fgMorphTree BB241, STMT00076 (before) [000308] -A--------- * ASG int [000307] D------N--- +--* LCL_VAR int V16 loc12 [000306] ----------- \--* ADD int [000304] ----------- +--* LCL_VAR int V16 loc12 [000305] ----------- \--* CNS_INT int 1 The assignment [000308] using V51 removes: Copy Assertion: V51 == V16 fgMorphTree BB241, STMT00458 (before) [002283] -A-XG------ * ASG ushort [002282] D------N--- +--* LCL_VAR ushort V123 tmp83 [000317] ---XG------ \--* IND ushort [000316] ----------- \--* ADD long [000302] ----------- +--* LCL_VAR long V34 loc30 [000315] ----------- \--* MUL long [000312] ----------- +--* CAST long <- int [000311] ----------- | \--* LCL_VAR int V51 tmp11 [000314] ----------- \--* CAST long <- int [000313] ----------- \--* CNS_INT int 2 Folding long operator with constant nodes into a constant: [000314] ----------- * CAST long <- int [000313] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000314] ----------- * CNS_INT long 2 GenTreeNode creates assertion: [002283] -A-XG+----- * ASG ushort In BB241 New Local Subrange Assertion: V123 in [0..65535], index = #01 fgMorphTree BB241, STMT00458 (after) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 fgMorphTree BB241, STMT00451 (before) [002246] -A-XG------ * ASG int [002245] D------N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG------ \--* FIELD int : [000301] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002244] ---XG------ * IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 fgMorphTree BB241, STMT00451 (after) [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 fgMorphTree BB241, STMT00453 (before) [002253] ---XG------ * JTRUE void [002252] N--XG----U- \--* GE int [002247] ----------- +--* LCL_VAR int V122 tmp82 [002286] ---XG------ \--* FIELD int : [002249] ---XG------ \--* FIELD_ADDR byref : [002248] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [003031] -----+----- * ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [003032] ----------- * ADD long [003030] -----+----- +--* CNS_INT long 16 [003028] -----+----- \--* CNS_INT long 8 Bashed to long constant: [003032] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002286] ---XG------ * IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 fgMorphTree BB241, STMT00453 (after) [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 Morphing BB243 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB243, STMT00455 (before) [002262] -A-XG------ * ASG byref [002261] D------N--- +--* LCL_VAR byref V124 tmp84 [002258] ---XG------ \--* FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002258] ---XG------ * FIELD_ADDR byref : [002257] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [003038] ---X-O----- * COMMA byref [003034] ---X-O----- +--* NULLCHECK byte [003033] ----------- | \--* LCL_VAR byref V00 arg0 [003037] -----O----- \--* ADD byref [003035] -----O----- +--* LCL_VAR byref V00 arg0 [003036] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [003038] ---X-+-N--- * COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 fgMorphTree BB243, STMT00455 (after) [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 fgMorphTree BB243, STMT00456 (before) [002275] -A-XGO----- * ASG short [002274] ---XGO-N--- +--* IND short [002272] ---XGO----- | \--* COMMA byref [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002259] ----------- | | +--* LCL_VAR int V122 tmp82 [002265] ----G------ | | \--* FIELD int : [002264] ----------- | | \--* LCL_VAR byref V124 tmp84 [002271] ----GO----- | \--* ADD byref [002270] ----G------ | +--* FIELD byref : [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 [002269] ----------- | \--* MUL long [002267] ---------U- | +--* CAST long <- uint [002260] ----------- | | \--* LCL_VAR int V122 tmp82 [002268] ----------- | \--* CNS_INT long 2 [002273] ----------- \--* LCL_VAR int V123 tmp83 Final value of Compiler::fgMorphField after morphing: [002265] ---XG------ * IND int [003040] -----+----- \--* ADD byref [002264] -----+----- +--* LCL_VAR byref V124 tmp84 [003039] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002270] ---XG------ * IND byref [002263] -----+----- \--* LCL_VAR byref V124 tmp84 fgMorphTree BB243, STMT00456 (after) [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 fgMorphTree BB243, STMT00457 (before) [002281] -A-XG------ * ASG int [002280] ---XG--N--- +--* FIELD int : [002276] ----------- | \--* LCL_VAR byref V00 arg0 [002279] ----------- \--* ADD int [002277] ----------- +--* LCL_VAR int V122 tmp82 [002278] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002280] ---XG--N--- * IND int [003043] -----+----- \--* ADD byref [002276] -----+----- +--* LCL_VAR byref V00 arg0 [003042] -----+----- \--* CNS_INT long 8 fgMorphTree BB243, STMT00457 (after) [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 Morphing BB244 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB244, STMT00454 (before) [002256] --C-G------ * CALL r2r_ind void [002254] ----------- this +--* LCL_VAR byref V00 arg0 [002255] ----------- arg1 \--* LCL_VAR int V123 tmp83 Initializing arg info for 2256.CALL: Args for call [002256] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002254].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003044].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[002255].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2256.CALL: Sorting the arguments: Deferred argument ('x0'): [002254] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [002255] -----+----- * LCL_VAR int V123 tmp83 Moved to late list Deferred argument ('x11'): [003044] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002256].CALL after fgMorphArgs: CallArg[[002254].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003044].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002255].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB244, STMT00454 (after) [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB246 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB246, STMT00080 (before) [000325] -A--------- * ASG int [000324] D------N--- +--* LCL_VAR int V37 loc33 [000323] ----------- \--* CNS_INT int 0 Folding operator with constant nodes into a constant: [003045] ----------- * CAST int <- bool <- int [000323] -----+----- \--* CNS_INT int 0 Bashed to int constant: [003045] ----------- * CNS_INT int 0 GenTreeNode creates assertion: [000325] -A---+----- * ASG int In BB246 New Local Constant Assertion: V37 == 0, index = #01 fgMorphTree BB246, STMT00081 (before) [000328] -A--------- * ASG int [000327] D------N--- +--* LCL_VAR int V38 loc34 [000326] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000328] -A---+----- * ASG int In BB246 New Local Constant Assertion: V38 == 0, index = #02 fgMorphTree BB246, STMT00082 (before) [000332] ----------- * JTRUE void [000331] ----------- \--* EQ int [000329] ----------- +--* LCL_VAR int V09 loc5 [000330] ----------- \--* CNS_INT int 0 Morphing BB247 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB247, STMT00098 (before) [000425] --C-------- * JTRUE void [000424] --C-------- \--* GE int [000419] ----------- +--* LCL_VAR int V16 loc12 [002292] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB248 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB248, STMT00123 (before) [000575] ---XG------ * JTRUE void [000574] N--XG----U- \--* EQ int [000572] ---XG------ +--* IND ushort [000571] ----------- | \--* ADD long [000565] ----------- | +--* LCL_VAR long V34 loc30 [000570] ----------- | \--* MUL long [000567] ----------- | +--* CAST long <- int [000566] ----------- | | \--* LCL_VAR int V16 loc12 [000569] ----------- | \--* CAST long <- int [000568] ----------- | \--* CNS_INT int 2 [000573] ----------- \--* CNS_INT int 48 Folding long operator with constant nodes into a constant: [000569] ----------- * CAST long <- int [000568] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000569] ----------- * CNS_INT long 2 fgMorphTree BB248, STMT00123 (after) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 Morphing BB250 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB250, STMT00100 (before) [000434] --C-------- * JTRUE void [000433] --C-------- \--* GE int [000428] ----------- +--* ADD int [000426] ----------- | +--* LCL_VAR int V16 loc12 [000427] ----------- | \--* CNS_INT int 1 [002296] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB251 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB251, STMT00120 (before) [000548] ---XG------ * JTRUE void [000547] N--XG----U- \--* NE int [000545] ---XG------ +--* IND ushort [000544] ----------- | \--* ADD long [000538] ----------- | +--* LCL_VAR long V34 loc30 [000543] ----------- | \--* MUL long [000540] ----------- | +--* CAST long <- int [000539] ----------- | | \--* LCL_VAR int V16 loc12 [000542] ----------- | \--* CAST long <- int [000541] ----------- | \--* CNS_INT int 2 [000546] ----------- \--* CNS_INT int 43 Folding long operator with constant nodes into a constant: [000542] ----------- * CAST long <- int [000541] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000542] ----------- * CNS_INT long 2 fgMorphTree BB251, STMT00120 (after) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 Morphing BB252 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB252, STMT00121 (before) [000561] ---XG------ * JTRUE void [000560] N--XG----U- \--* NE int [000558] ---XG------ +--* IND ushort [000557] ----------- | \--* ADD long [000549] ----------- | +--* LCL_VAR long V34 loc30 [000556] ----------- | \--* MUL long [000553] ----------- | +--* CAST long <- int [000552] ----------- | | \--* ADD int [000550] ----------- | | +--* LCL_VAR int V16 loc12 [000551] ----------- | | \--* CNS_INT int 1 [000555] ----------- | \--* CAST long <- int [000554] ----------- | \--* CNS_INT int 2 [000559] ----------- \--* CNS_INT int 48 Folding long operator with constant nodes into a constant: [000555] ----------- * CAST long <- int [000554] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000555] ----------- * CNS_INT long 2 fgMorphTree BB252, STMT00121 (after) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 Morphing BB253 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB253, STMT00122 (before) [000564] -A--------- * ASG int [000563] D------N--- +--* LCL_VAR int V37 loc33 [000562] ----------- \--* CNS_INT int 1 Folding operator with constant nodes into a constant: [003046] ----------- * CAST int <- bool <- int [000562] -----+----- \--* CNS_INT int 1 Bashed to int constant: [003046] ----------- * CNS_INT int 1 GenTreeNode creates assertion: [000564] -A---+----- * ASG int In BB253 New Local Constant Assertion: V37 == 1, index = #01 Morphing BB254 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB254, STMT00102 (before) [000443] --C-------- * JTRUE void [000442] --C-------- \--* GE int [000437] ----------- +--* ADD int [000435] ----------- | +--* LCL_VAR int V16 loc12 [000436] ----------- | \--* CNS_INT int 1 [002300] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB255 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB255, STMT00104 (before) [000457] ---XG------ * JTRUE void [000456] N--XG----U- \--* NE int [000454] ---XG------ +--* IND ushort [000453] ----------- | \--* ADD long [000447] ----------- | +--* LCL_VAR long V34 loc30 [000452] ----------- | \--* MUL long [000449] ----------- | +--* CAST long <- int [000448] ----------- | | \--* LCL_VAR int V16 loc12 [000451] ----------- | \--* CAST long <- int [000450] ----------- | \--* CNS_INT int 2 [000455] ----------- \--* CNS_INT int 45 Folding long operator with constant nodes into a constant: [000451] ----------- * CAST long <- int [000450] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000451] ----------- * CNS_INT long 2 fgMorphTree BB255, STMT00104 (after) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 Morphing BB256 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB256, STMT00105 (before) [000470] ---XG------ * JTRUE void [000469] ---XG------ \--* EQ int [000467] ---XG------ +--* IND ushort [000466] ----------- | \--* ADD long [000458] ----------- | +--* LCL_VAR long V34 loc30 [000465] ----------- | \--* MUL long [000462] ----------- | +--* CAST long <- int [000461] ----------- | | \--* ADD int [000459] ----------- | | +--* LCL_VAR int V16 loc12 [000460] ----------- | | \--* CNS_INT int 1 [000464] ----------- | \--* CAST long <- int [000463] ----------- | \--* CNS_INT int 2 [000468] ----------- \--* CNS_INT int 48 Folding long operator with constant nodes into a constant: [000464] ----------- * CAST long <- int [000463] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000464] ----------- * CNS_INT long 2 fgMorphTree BB256, STMT00105 (after) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 Morphing BB257 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB257, STMT00460 (before) [002304] -A-XG------ * ASG int [002303] D------N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG------ \--* FIELD int : [000444] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002302] ---XG------ * IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 fgMorphTree BB257, STMT00460 (after) [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 fgMorphTree BB257, STMT00462 (before) [002311] ---XG------ * JTRUE void [002310] N--XG----U- \--* GE int [002305] ----------- +--* LCL_VAR int V126 tmp86 [002341] ---XG------ \--* FIELD int : [002307] ---XG------ \--* FIELD_ADDR byref : [002306] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [003052] -----+----- * ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [003053] ----------- * ADD long [003051] -----+----- +--* CNS_INT long 16 [003049] -----+----- \--* CNS_INT long 8 Bashed to long constant: [003053] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002341] ---XG------ * IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 fgMorphTree BB257, STMT00462 (after) [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 Morphing BB259 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB259, STMT00464 (before) [002319] -A-XG------ * ASG byref [002318] D------N--- +--* LCL_VAR byref V127 tmp87 [002315] ---XG------ \--* FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002315] ---XG------ * FIELD_ADDR byref : [002314] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [003059] ---X-O----- * COMMA byref [003055] ---X-O----- +--* NULLCHECK byte [003054] ----------- | \--* LCL_VAR byref V00 arg0 [003058] -----O----- \--* ADD byref [003056] -----O----- +--* LCL_VAR byref V00 arg0 [003057] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [003059] ---X-+-N--- * COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 fgMorphTree BB259, STMT00464 (after) [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 fgMorphTree BB259, STMT00465 (before) [002332] -A-XGO----- * ASG short [002331] ---XGO-N--- +--* IND short [002329] ---XGO----- | \--* COMMA byref [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002316] ----------- | | +--* LCL_VAR int V126 tmp86 [002322] ----G------ | | \--* FIELD int : [002321] ----------- | | \--* LCL_VAR byref V127 tmp87 [002328] ----GO----- | \--* ADD byref [002327] ----G------ | +--* FIELD byref : [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 [002326] ----------- | \--* MUL long [002324] ---------U- | +--* CAST long <- uint [002317] ----------- | | \--* LCL_VAR int V126 tmp86 [002325] ----------- | \--* CNS_INT long 2 [002330] ----------- \--* LCL_VAR int V18 loc14 Final value of Compiler::fgMorphField after morphing: [002322] ---XG------ * IND int [003061] -----+----- \--* ADD byref [002321] -----+----- +--* LCL_VAR byref V127 tmp87 [003060] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002327] ---XG------ * IND byref [002320] -----+----- \--* LCL_VAR byref V127 tmp87 fgMorphTree BB259, STMT00465 (after) [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 fgMorphTree BB259, STMT00466 (before) [002338] -A-XG------ * ASG int [002337] ---XG--N--- +--* FIELD int : [002333] ----------- | \--* LCL_VAR byref V00 arg0 [002336] ----------- \--* ADD int [002334] ----------- +--* LCL_VAR int V126 tmp86 [002335] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002337] ---XG--N--- * IND int [003064] -----+----- \--* ADD byref [002333] -----+----- +--* LCL_VAR byref V00 arg0 [003063] -----+----- \--* CNS_INT long 8 fgMorphTree BB259, STMT00466 (after) [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 Morphing BB260 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB260, STMT00463 (before) [002313] --C-G------ * CALL r2r_ind void [002312] ----------- this +--* LCL_VAR byref V00 arg0 [000445] ----------- arg1 \--* LCL_VAR int V18 loc14 Initializing arg info for 2313.CALL: Args for call [002313] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002312].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003065].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[000445].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2313.CALL: Sorting the arguments: Deferred argument ('x0'): [002312] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [000445] -----+----- * LCL_VAR int V18 loc14 Moved to late list Deferred argument ('x11'): [003065] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002313].CALL after fgMorphArgs: CallArg[[002312].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003065].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[000445].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB260, STMT00463 (after) [002313] --CXG+----- * CALL r2r_ind void [002312] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000445] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003065] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB262 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB262, STMT00119 (before) [000537] -A--------- * ASG int [000536] D------N--- +--* LCL_VAR int V38 loc34 [000535] ----------- \--* ADD int [000533] ----------- +--* LCL_VAR int V38 loc34 [000534] ----------- \--* CNS_INT int 1 Morphing BB263 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB263, STMT00106 (before) [000475] -A--------- * ASG int [000474] D------N--- +--* LCL_VAR int V54 tmp14 [000473] ----------- \--* ADD int [000471] ----------- +--* LCL_VAR int V16 loc12 [000472] ----------- \--* CNS_INT int 1 fgMorphTree BB263, STMT00107 (before) [000479] -A--------- * ASG int [000478] D------N--- +--* LCL_VAR int V16 loc12 [000477] ----------- \--* LCL_VAR int V54 tmp14 GenTreeNode creates assertion: [000479] -A---+----- * ASG int In BB263 New Local Copy Assertion: V16 == V54, index = #01 fgMorphTree BB263, STMT00109 (before) [000485] --C-------- * JTRUE void [000484] --C-------- \--* GE int [000476] ----------- +--* LCL_VAR int V54 tmp14 [002347] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB264 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB264, STMT00118 (before) [000532] ---XG------ * JTRUE void [000531] ---XG------ \--* EQ int [000529] ---XG------ +--* IND ushort [000528] ----------- | \--* ADD long [000522] ----------- | +--* LCL_VAR long V34 loc30 [000527] ----------- | \--* MUL long [000524] ----------- | +--* CAST long <- int [000523] ----------- | | \--* LCL_VAR int V16 loc12 [000526] ----------- | \--* CAST long <- int [000525] ----------- | \--* CNS_INT int 2 [000530] ----------- \--* CNS_INT int 48 Folding long operator with constant nodes into a constant: [000526] ----------- * CAST long <- int [000525] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000526] ----------- * CNS_INT long 2 fgMorphTree BB264, STMT00118 (after) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 Morphing BB265 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB265, STMT00110 (before) [000489] ----------- * JTRUE void [000488] ----------- \--* LE int [000486] ----------- +--* LCL_VAR int V38 loc34 [000487] ----------- \--* CNS_INT int 10 Morphing BB266 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB266, STMT00117 (before) [000521] -A--------- * ASG int [000520] D------N--- +--* LCL_VAR int V38 loc34 [000519] ----------- \--* CNS_INT int 10 GenTreeNode creates assertion: [000521] -A---+----- * ASG int In BB266 New Local Constant Assertion: V38 == 10, index = #01 Morphing BB267 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB267, STMT00111 (before) [000494] ---XG------ * JTRUE void [000493] ---XG------ \--* EQ int [000491] ---XG------ +--* IND ubyte [000490] ----------- | \--* LCL_VAR long V17 loc13 [000492] ----------- \--* CNS_INT int 0 Morphing BB268 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB268, STMT00116 (before) [000517] -A-XG------ * ASG int [000516] D------N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG------ \--* SUB int [000513] ---XG------ +--* FIELD int : [000512] ----------- | \--* LCL_VAR byref V01 arg1 [000514] ----------- \--* LCL_VAR int V05 loc1 Final value of Compiler::fgMorphField after morphing: [000513] ---XG------ * IND int [003067] -----+----- \--* ADD byref [000512] -----+----- +--* LCL_VAR byref V01 arg1 [003066] -----+----- \--* CNS_INT long 4 fgMorphTree BB268, STMT00116 (after) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 Morphing BB269 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB269, STMT00112 (before) [000497] -A--------- * ASG int [000496] D------N--- +--* LCL_VAR int V55 tmp15 [000495] ----------- \--* CNS_INT int 0 GenTreeNode creates assertion: [000497] -A---+----- * ASG int In BB269 New Local Constant Assertion: V55 == 0, index = #01 Morphing BB270 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB270, STMT00114 (before) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000502] ----------- arg0 +--* LCL_VAR byref V00 arg0 [000503] ----------- arg1 +--* LCL_VAR ref V03 arg3 [000499] ----------- arg2 +--* LCL_VAR int V55 tmp15 [000505] ----------- arg3 +--* LCL_VAR int V18 loc14 [000506] ----------- arg4 +--* LCL_VAR int V38 loc34 [000507] ----------- arg5 \--* LCL_VAR int V37 loc33 Initializing arg info for 508.CALL: Args for call [000508] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[003068].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[000502].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8] CallArg[[000503].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8] CallArg[[000499].LCL_VAR int (By value), 1 reg: x2, byteAlignment=8] CallArg[[000505].LCL_VAR ushort (By value), 1 reg: x3, byteAlignment=8] CallArg[[000506].LCL_VAR int (By value), 1 reg: x4, byteAlignment=8] CallArg[[000507].LCL_VAR bool (By value), 1 reg: x5, byteAlignment=8] Morphing args for 508.CALL: Sorting the arguments: Deferred argument ('x5'): [000507] -----+----- * LCL_VAR int V37 loc33 Moved to late list Deferred argument ('x0'): [000502] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [000503] -----+----- * LCL_VAR ref V03 arg3 Moved to late list Deferred argument ('x2'): [000499] -----+----- * LCL_VAR int V55 tmp15 Moved to late list Deferred argument ('x3'): [000505] -----+----- * LCL_VAR int V18 loc14 Moved to late list Deferred argument ('x4'): [000506] -----+----- * LCL_VAR int V38 loc34 Moved to late list Deferred argument ('x11'): [003068] H----+----- * CNS_INT(h) long 0x4000000000540240 ftn Moved to late list Register placement order: x5 x0 x1 x2 x3 x4 x11 Args for [000508].CALL after fgMorphArgs: CallArg[[003068].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[000502].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed] CallArg[[000503].LCL_VAR ref (By value), 1 reg: x1, byteAlignment=8, isLate, processed] CallArg[[000499].LCL_VAR int (By value), 1 reg: x2, byteAlignment=8, isLate, processed] CallArg[[000505].LCL_VAR ushort (By value), 1 reg: x3, byteAlignment=8, isLate, processed] CallArg[[000506].LCL_VAR int (By value), 1 reg: x4, byteAlignment=8, isLate, processed] CallArg[[000507].LCL_VAR bool (By value), 1 reg: x5, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB270, STMT00114 (after) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn fgMorphTree BB270, STMT00115 (before) [000511] -A--------- * ASG int [000510] D------N--- +--* LCL_VAR int V09 loc5 [000509] ----------- \--* CNS_INT int 0 Folding operator with constant nodes into a constant: [003069] ----------- * CAST int <- bool <- int [000509] -----+----- \--* CNS_INT int 0 Bashed to int constant: [003069] ----------- * CNS_INT int 0 GenTreeNode creates assertion: [000511] -A---+----- * ASG int In BB270 New Local Constant Assertion: V09 == 0, index = #01 Morphing BB271 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB271, STMT00468 (before) [002351] -A-XG------ * ASG int [002350] D------N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG------ \--* FIELD int : [000333] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002349] ---XG------ * IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 fgMorphTree BB271, STMT00468 (after) [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 fgMorphTree BB271, STMT00470 (before) [002358] ---XG------ * JTRUE void [002357] N--XG----U- \--* GE int [002352] ----------- +--* LCL_VAR int V129 tmp89 [002388] ---XG------ \--* FIELD int : [002354] ---XG------ \--* FIELD_ADDR byref : [002353] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [003075] -----+----- * ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [003076] ----------- * ADD long [003074] -----+----- +--* CNS_INT long 16 [003072] -----+----- \--* CNS_INT long 8 Bashed to long constant: [003076] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002388] ---XG------ * IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 fgMorphTree BB271, STMT00470 (after) [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 Morphing BB273 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB273, STMT00472 (before) [002366] -A-XG------ * ASG byref [002365] D------N--- +--* LCL_VAR byref V130 tmp90 [002362] ---XG------ \--* FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002362] ---XG------ * FIELD_ADDR byref : [002361] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [003082] ---X-O----- * COMMA byref [003078] ---X-O----- +--* NULLCHECK byte [003077] ----------- | \--* LCL_VAR byref V00 arg0 [003081] -----O----- \--* ADD byref [003079] -----O----- +--* LCL_VAR byref V00 arg0 [003080] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [003082] ---X-+-N--- * COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 fgMorphTree BB273, STMT00472 (after) [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 fgMorphTree BB273, STMT00473 (before) [002379] -A-XGO----- * ASG short [002378] ---XGO-N--- +--* IND short [002376] ---XGO----- | \--* COMMA byref [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002363] ----------- | | +--* LCL_VAR int V129 tmp89 [002369] ----G------ | | \--* FIELD int : [002368] ----------- | | \--* LCL_VAR byref V130 tmp90 [002375] ----GO----- | \--* ADD byref [002374] ----G------ | +--* FIELD byref : [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 [002373] ----------- | \--* MUL long [002371] ---------U- | +--* CAST long <- uint [002364] ----------- | | \--* LCL_VAR int V129 tmp89 [002372] ----------- | \--* CNS_INT long 2 [002377] ----------- \--* LCL_VAR int V18 loc14 Final value of Compiler::fgMorphField after morphing: [002369] ---XG------ * IND int [003084] -----+----- \--* ADD byref [002368] -----+----- +--* LCL_VAR byref V130 tmp90 [003083] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002374] ---XG------ * IND byref [002367] -----+----- \--* LCL_VAR byref V130 tmp90 fgMorphTree BB273, STMT00473 (after) [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 fgMorphTree BB273, STMT00474 (before) [002385] -A-XG------ * ASG int [002384] ---XG--N--- +--* FIELD int : [002380] ----------- | \--* LCL_VAR byref V00 arg0 [002383] ----------- \--* ADD int [002381] ----------- +--* LCL_VAR int V129 tmp89 [002382] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002384] ---XG--N--- * IND int [003087] -----+----- \--* ADD byref [002380] -----+----- +--* LCL_VAR byref V00 arg0 [003086] -----+----- \--* CNS_INT long 8 fgMorphTree BB273, STMT00474 (after) [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 Morphing BB274 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB274, STMT00471 (before) [002360] --C-G------ * CALL r2r_ind void [002359] ----------- this +--* LCL_VAR byref V00 arg0 [000334] ----------- arg1 \--* LCL_VAR int V18 loc14 Initializing arg info for 2360.CALL: Args for call [002360] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002359].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003088].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[000334].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2360.CALL: Sorting the arguments: Deferred argument ('x0'): [002359] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [000334] -----+----- * LCL_VAR int V18 loc14 Moved to late list Deferred argument ('x11'): [003088] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002360].CALL after fgMorphArgs: CallArg[[002359].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003088].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[000334].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB274, STMT00471 (after) [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB275 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB275, STMT00085 (before) [000342] --C-------- * JTRUE void [000341] --C-------- \--* GE int [000336] ----------- +--* LCL_VAR int V16 loc12 [002394] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB276 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB276, STMT00086 (before) [000353] ---XG------ * JTRUE void [000352] ---XG------ \--* EQ int [000350] ---XG------ +--* IND ushort [000349] ----------- | \--* ADD long [000343] ----------- | +--* LCL_VAR long V34 loc30 [000348] ----------- | \--* MUL long [000345] ----------- | +--* CAST long <- int [000344] ----------- | | \--* LCL_VAR int V16 loc12 [000347] ----------- | \--* CAST long <- int [000346] ----------- | \--* CNS_INT int 2 [000351] ----------- \--* CNS_INT int 43 Folding long operator with constant nodes into a constant: [000347] ----------- * CAST long <- int [000346] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000347] ----------- * CNS_INT long 2 fgMorphTree BB276, STMT00086 (after) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 Morphing BB277 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB277, STMT00096 (before) [000418] ---XG------ * JTRUE void [000417] N--XG----U- \--* NE int [000415] ---XG------ +--* IND ushort [000414] ----------- | \--* ADD long [000408] ----------- | +--* LCL_VAR long V34 loc30 [000413] ----------- | \--* MUL long [000410] ----------- | +--* CAST long <- int [000409] ----------- | | \--* LCL_VAR int V16 loc12 [000412] ----------- | \--* CAST long <- int [000411] ----------- | \--* CNS_INT int 2 [000416] ----------- \--* CNS_INT int 45 Folding long operator with constant nodes into a constant: [000412] ----------- * CAST long <- int [000411] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000412] ----------- * CNS_INT long 2 fgMorphTree BB277, STMT00096 (after) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 Morphing BB278 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB278, STMT00088 (before) [000363] -A--------- * ASG int [000362] D------N--- +--* LCL_VAR int V52 tmp12 [000356] ----------- \--* LCL_VAR int V16 loc12 GenTreeNode creates assertion: [000363] -A---+----- * ASG int In BB278 New Local Copy Assertion: V52 == V16, index = #01 fgMorphTree BB278, STMT00087 (before) [000361] -A--------- * ASG int [000360] D------N--- +--* LCL_VAR int V16 loc12 [000359] ----------- \--* ADD int [000357] ----------- +--* LCL_VAR int V16 loc12 [000358] ----------- \--* CNS_INT int 1 The assignment [000361] using V52 removes: Copy Assertion: V52 == V16 fgMorphTree BB278, STMT00483 (before) [002435] -A-XG------ * ASG ushort [002434] D------N--- +--* LCL_VAR ushort V133 tmp93 [000370] ---XG------ \--* IND ushort [000369] ----------- \--* ADD long [000355] ----------- +--* LCL_VAR long V34 loc30 [000368] ----------- \--* MUL long [000365] ----------- +--* CAST long <- int [000364] ----------- | \--* LCL_VAR int V52 tmp12 [000367] ----------- \--* CAST long <- int [000366] ----------- \--* CNS_INT int 2 Folding long operator with constant nodes into a constant: [000367] ----------- * CAST long <- int [000366] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000367] ----------- * CNS_INT long 2 GenTreeNode creates assertion: [002435] -A-XG+----- * ASG ushort In BB278 New Local Subrange Assertion: V133 in [0..65535], index = #01 fgMorphTree BB278, STMT00483 (after) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 fgMorphTree BB278, STMT00476 (before) [002398] -A-XG------ * ASG int [002397] D------N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG------ \--* FIELD int : [000354] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002396] ---XG------ * IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 fgMorphTree BB278, STMT00476 (after) [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 fgMorphTree BB278, STMT00478 (before) [002405] ---XG------ * JTRUE void [002404] N--XG----U- \--* GE int [002399] ----------- +--* LCL_VAR int V132 tmp92 [002438] ---XG------ \--* FIELD int : [002401] ---XG------ \--* FIELD_ADDR byref : [002400] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [003094] -----+----- * ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [003095] ----------- * ADD long [003093] -----+----- +--* CNS_INT long 16 [003091] -----+----- \--* CNS_INT long 8 Bashed to long constant: [003095] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002438] ---XG------ * IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 fgMorphTree BB278, STMT00478 (after) [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 Morphing BB280 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB280, STMT00480 (before) [002414] -A-XG------ * ASG byref [002413] D------N--- +--* LCL_VAR byref V134 tmp94 [002410] ---XG------ \--* FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002410] ---XG------ * FIELD_ADDR byref : [002409] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [003101] ---X-O----- * COMMA byref [003097] ---X-O----- +--* NULLCHECK byte [003096] ----------- | \--* LCL_VAR byref V00 arg0 [003100] -----O----- \--* ADD byref [003098] -----O----- +--* LCL_VAR byref V00 arg0 [003099] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [003101] ---X-+-N--- * COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 fgMorphTree BB280, STMT00480 (after) [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 fgMorphTree BB280, STMT00481 (before) [002427] -A-XGO----- * ASG short [002426] ---XGO-N--- +--* IND short [002424] ---XGO----- | \--* COMMA byref [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002411] ----------- | | +--* LCL_VAR int V132 tmp92 [002417] ----G------ | | \--* FIELD int : [002416] ----------- | | \--* LCL_VAR byref V134 tmp94 [002423] ----GO----- | \--* ADD byref [002422] ----G------ | +--* FIELD byref : [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 [002421] ----------- | \--* MUL long [002419] ---------U- | +--* CAST long <- uint [002412] ----------- | | \--* LCL_VAR int V132 tmp92 [002420] ----------- | \--* CNS_INT long 2 [002425] ----------- \--* LCL_VAR int V133 tmp93 Final value of Compiler::fgMorphField after morphing: [002417] ---XG------ * IND int [003103] -----+----- \--* ADD byref [002416] -----+----- +--* LCL_VAR byref V134 tmp94 [003102] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002422] ---XG------ * IND byref [002415] -----+----- \--* LCL_VAR byref V134 tmp94 fgMorphTree BB280, STMT00481 (after) [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 fgMorphTree BB280, STMT00482 (before) [002433] -A-XG------ * ASG int [002432] ---XG--N--- +--* FIELD int : [002428] ----------- | \--* LCL_VAR byref V00 arg0 [002431] ----------- \--* ADD int [002429] ----------- +--* LCL_VAR int V132 tmp92 [002430] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002432] ---XG--N--- * IND int [003106] -----+----- \--* ADD byref [002428] -----+----- +--* LCL_VAR byref V00 arg0 [003105] -----+----- \--* CNS_INT long 8 fgMorphTree BB280, STMT00482 (after) [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 Morphing BB281 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB281, STMT00479 (before) [002408] --C-G------ * CALL r2r_ind void [002406] ----------- this +--* LCL_VAR byref V00 arg0 [002407] ----------- arg1 \--* LCL_VAR int V133 tmp93 Initializing arg info for 2408.CALL: Args for call [002408] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002406].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003107].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[002407].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2408.CALL: Sorting the arguments: Deferred argument ('x0'): [002406] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [002407] -----+----- * LCL_VAR int V133 tmp93 Moved to late list Deferred argument ('x11'): [003107] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002408].CALL after fgMorphArgs: CallArg[[002406].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003107].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002407].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB281, STMT00479 (after) [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB283 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB283, STMT00094 (before) [000399] -A--------- * ASG int [000398] D------N--- +--* LCL_VAR int V53 tmp13 [000392] ----------- \--* LCL_VAR int V16 loc12 GenTreeNode creates assertion: [000399] -A---+----- * ASG int In BB283 New Local Copy Assertion: V53 == V16, index = #01 fgMorphTree BB283, STMT00093 (before) [000397] -A--------- * ASG int [000396] D------N--- +--* LCL_VAR int V16 loc12 [000395] ----------- \--* ADD int [000393] ----------- +--* LCL_VAR int V16 loc12 [000394] ----------- \--* CNS_INT int 1 The assignment [000397] using V53 removes: Copy Assertion: V53 == V16 fgMorphTree BB283, STMT00492 (before) [002481] -A-XG------ * ASG ushort [002480] D------N--- +--* LCL_VAR ushort V137 tmp97 [000406] ---XG------ \--* IND ushort [000405] ----------- \--* ADD long [000391] ----------- +--* LCL_VAR long V34 loc30 [000404] ----------- \--* MUL long [000401] ----------- +--* CAST long <- int [000400] ----------- | \--* LCL_VAR int V53 tmp13 [000403] ----------- \--* CAST long <- int [000402] ----------- \--* CNS_INT int 2 Folding long operator with constant nodes into a constant: [000403] ----------- * CAST long <- int [000402] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000403] ----------- * CNS_INT long 2 GenTreeNode creates assertion: [002481] -A-XG+----- * ASG ushort In BB283 New Local Subrange Assertion: V137 in [0..65535], index = #01 fgMorphTree BB283, STMT00492 (after) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 fgMorphTree BB283, STMT00485 (before) [002444] -A-XG------ * ASG int [002443] D------N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG------ \--* FIELD int : [000390] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002442] ---XG------ * IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 fgMorphTree BB283, STMT00485 (after) [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 fgMorphTree BB283, STMT00487 (before) [002451] ---XG------ * JTRUE void [002450] N--XG----U- \--* GE int [002445] ----------- +--* LCL_VAR int V136 tmp96 [002484] ---XG------ \--* FIELD int : [002447] ---XG------ \--* FIELD_ADDR byref : [002446] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [003113] -----+----- * ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [003114] ----------- * ADD long [003112] -----+----- +--* CNS_INT long 16 [003110] -----+----- \--* CNS_INT long 8 Bashed to long constant: [003114] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002484] ---XG------ * IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 fgMorphTree BB283, STMT00487 (after) [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 Morphing BB285 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB285, STMT00489 (before) [002460] -A-XG------ * ASG byref [002459] D------N--- +--* LCL_VAR byref V138 tmp98 [002456] ---XG------ \--* FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002456] ---XG------ * FIELD_ADDR byref : [002455] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [003120] ---X-O----- * COMMA byref [003116] ---X-O----- +--* NULLCHECK byte [003115] ----------- | \--* LCL_VAR byref V00 arg0 [003119] -----O----- \--* ADD byref [003117] -----O----- +--* LCL_VAR byref V00 arg0 [003118] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [003120] ---X-+-N--- * COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 fgMorphTree BB285, STMT00489 (after) [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 fgMorphTree BB285, STMT00490 (before) [002473] -A-XGO----- * ASG short [002472] ---XGO-N--- +--* IND short [002470] ---XGO----- | \--* COMMA byref [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002457] ----------- | | +--* LCL_VAR int V136 tmp96 [002463] ----G------ | | \--* FIELD int : [002462] ----------- | | \--* LCL_VAR byref V138 tmp98 [002469] ----GO----- | \--* ADD byref [002468] ----G------ | +--* FIELD byref : [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 [002467] ----------- | \--* MUL long [002465] ---------U- | +--* CAST long <- uint [002458] ----------- | | \--* LCL_VAR int V136 tmp96 [002466] ----------- | \--* CNS_INT long 2 [002471] ----------- \--* LCL_VAR int V137 tmp97 Final value of Compiler::fgMorphField after morphing: [002463] ---XG------ * IND int [003122] -----+----- \--* ADD byref [002462] -----+----- +--* LCL_VAR byref V138 tmp98 [003121] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002468] ---XG------ * IND byref [002461] -----+----- \--* LCL_VAR byref V138 tmp98 fgMorphTree BB285, STMT00490 (after) [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 fgMorphTree BB285, STMT00491 (before) [002479] -A-XG------ * ASG int [002478] ---XG--N--- +--* FIELD int : [002474] ----------- | \--* LCL_VAR byref V00 arg0 [002477] ----------- \--* ADD int [002475] ----------- +--* LCL_VAR int V136 tmp96 [002476] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002478] ---XG--N--- * IND int [003125] -----+----- \--* ADD byref [002474] -----+----- +--* LCL_VAR byref V00 arg0 [003124] -----+----- \--* CNS_INT long 8 fgMorphTree BB285, STMT00491 (after) [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 Morphing BB286 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB286, STMT00488 (before) [002454] --C-G------ * CALL r2r_ind void [002452] ----------- this +--* LCL_VAR byref V00 arg0 [002453] ----------- arg1 \--* LCL_VAR int V137 tmp97 Initializing arg info for 2454.CALL: Args for call [002454] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002452].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003126].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[002453].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2454.CALL: Sorting the arguments: Deferred argument ('x0'): [002452] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [002453] -----+----- * LCL_VAR int V137 tmp97 Moved to late list Deferred argument ('x11'): [003126] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002454].CALL after fgMorphArgs: CallArg[[002452].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003126].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002453].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB286, STMT00488 (after) [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB287 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB287, STMT00091 (before) [000378] --C-------- * JTRUE void [000377] --C-------- \--* GE int [000372] ----------- +--* LCL_VAR int V16 loc12 [002490] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB289 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB289, STMT00092 (before) [000389] ---XG------ * JTRUE void [000388] ---XG------ \--* EQ int [000386] ---XG------ +--* IND ushort [000385] ----------- | \--* ADD long [000379] ----------- | +--* LCL_VAR long V34 loc30 [000384] ----------- | \--* MUL long [000381] ----------- | +--* CAST long <- int [000380] ----------- | | \--* LCL_VAR int V16 loc12 [000383] ----------- | \--* CAST long <- int [000382] ----------- | \--* CNS_INT int 2 [000387] ----------- \--* CNS_INT int 48 Folding long operator with constant nodes into a constant: [000383] ----------- * CAST long <- int [000382] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000383] ----------- * CNS_INT long 2 fgMorphTree BB289, STMT00092 (after) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 Morphing BB290 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' Morphing BB291 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB291, STMT00494 (before) [002494] -A-XG------ * ASG int [002493] D------N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG------ \--* FIELD int : [000590] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [002492] ---XG------ * IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 fgMorphTree BB291, STMT00494 (after) [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 fgMorphTree BB291, STMT00496 (before) [002501] ---XG------ * JTRUE void [002500] N--XG----U- \--* GE int [002495] ----------- +--* LCL_VAR int V140 tmp100 [002531] ---XG------ \--* FIELD int : [002497] ---XG------ \--* FIELD_ADDR byref : [002496] ----------- \--* LCL_VAR byref V00 arg0 Final value of Compiler::fgMorphField after morphing: [003132] -----+----- * ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 16 Folding long operator with constant nodes into a constant: [003133] ----------- * ADD long [003131] -----+----- +--* CNS_INT long 16 [003129] -----+----- \--* CNS_INT long 8 Bashed to long constant: [003133] ----------- * CNS_INT long 24 Final value of Compiler::fgMorphField after morphing: [002531] ---XG------ * IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 fgMorphTree BB291, STMT00496 (after) [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 Morphing BB293 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB293, STMT00498 (before) [002509] -A-XG------ * ASG byref [002508] D------N--- +--* LCL_VAR byref V141 tmp101 [002505] ---XG------ \--* FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 Before explicit null check morphing: [002505] ---XG------ * FIELD_ADDR byref : [002504] ----------- \--* LCL_VAR byref V00 arg0 After adding explicit null check: [003139] ---X-O----- * COMMA byref [003135] ---X-O----- +--* NULLCHECK byte [003134] ----------- | \--* LCL_VAR byref V00 arg0 [003138] -----O----- \--* ADD byref [003136] -----O----- +--* LCL_VAR byref V00 arg0 [003137] ----------- \--* CNS_INT long 16 Final value of Compiler::fgMorphField after morphing: [003139] ---X-+-N--- * COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 fgMorphTree BB293, STMT00498 (after) [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 fgMorphTree BB293, STMT00499 (before) [002522] -A-XGO----- * ASG short [002521] ---XGO-N--- +--* IND short [002519] ---XGO----- | \--* COMMA byref [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void [002506] ----------- | | +--* LCL_VAR int V140 tmp100 [002512] ----G------ | | \--* FIELD int : [002511] ----------- | | \--* LCL_VAR byref V141 tmp101 [002518] ----GO----- | \--* ADD byref [002517] ----G------ | +--* FIELD byref : [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 [002516] ----------- | \--* MUL long [002514] ---------U- | +--* CAST long <- uint [002507] ----------- | | \--* LCL_VAR int V140 tmp100 [002515] ----------- | \--* CNS_INT long 2 [002520] ----------- \--* LCL_VAR int V18 loc14 Final value of Compiler::fgMorphField after morphing: [002512] ---XG------ * IND int [003141] -----+----- \--* ADD byref [002511] -----+----- +--* LCL_VAR byref V141 tmp101 [003140] -----+----- \--* CNS_INT long 8 Final value of Compiler::fgMorphField after morphing: [002517] ---XG------ * IND byref [002510] -----+----- \--* LCL_VAR byref V141 tmp101 fgMorphTree BB293, STMT00499 (after) [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 fgMorphTree BB293, STMT00500 (before) [002528] -A-XG------ * ASG int [002527] ---XG--N--- +--* FIELD int : [002523] ----------- | \--* LCL_VAR byref V00 arg0 [002526] ----------- \--* ADD int [002524] ----------- +--* LCL_VAR int V140 tmp100 [002525] ----------- \--* CNS_INT int 1 Final value of Compiler::fgMorphField after morphing: [002527] ---XG--N--- * IND int [003144] -----+----- \--* ADD byref [002523] -----+----- +--* LCL_VAR byref V00 arg0 [003143] -----+----- \--* CNS_INT long 8 fgMorphTree BB293, STMT00500 (after) [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 Morphing BB294 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB294, STMT00497 (before) [002503] --C-G------ * CALL r2r_ind void [002502] ----------- this +--* LCL_VAR byref V00 arg0 [000591] ----------- arg1 \--* LCL_VAR int V18 loc14 Initializing arg info for 2503.CALL: Args for call [002503] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[002502].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003145].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[000591].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8] Morphing args for 2503.CALL: Sorting the arguments: Deferred argument ('x0'): [002502] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x1'): [000591] -----+----- * LCL_VAR int V18 loc14 Moved to late list Deferred argument ('x11'): [003145] H----+----- * CNS_INT(h) long 0x4000000000435c58 ftn Moved to late list Register placement order: x0 x1 x11 Args for [002503].CALL after fgMorphArgs: CallArg[[002502].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003145].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[000591].LCL_VAR ushort (By value), 1 reg: x1, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB294, STMT00497 (after) [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Morphing BB296 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB296, STMT00054 (before) [000210] --C-------- * JTRUE void [000209] --C-------- \--* GE int [000204] ----------- +--* LCL_VAR int V16 loc12 [002537] ----------- \--* LCL_FLD int V02 arg2 [+8] Morphing BB297 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB297, STMT00065 (before) [000250] -A--------- * ASG int [000249] D------N--- +--* LCL_VAR int V49 tmp9 [000243] ----------- \--* LCL_VAR int V16 loc12 GenTreeNode creates assertion: [000250] -A---+----- * ASG int In BB297 New Local Copy Assertion: V49 == V16, index = #01 fgMorphTree BB297, STMT00064 (before) [000248] -A--------- * ASG int [000247] D------N--- +--* LCL_VAR int V16 loc12 [000246] ----------- \--* ADD int [000244] ----------- +--* LCL_VAR int V16 loc12 [000245] ----------- \--* CNS_INT int 1 The assignment [000248] using V49 removes: Copy Assertion: V49 == V16 fgMorphTree BB297, STMT00066 (before) [000259] -A-XG------ * ASG int [000258] D------N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG------ \--* IND ushort [000256] ----------- \--* ADD long [000242] ----------- +--* LCL_VAR long V34 loc30 [000255] ----------- \--* MUL long [000252] ----------- +--* CAST long <- int [000251] ----------- | \--* LCL_VAR int V49 tmp9 [000254] ----------- \--* CAST long <- int [000253] ----------- \--* CNS_INT int 2 Folding long operator with constant nodes into a constant: [000254] ----------- * CAST long <- int [000253] -----+----- \--* CNS_INT int 2 Bashed to long constant: [000254] ----------- * CNS_INT long 2 GenTreeNode creates assertion: [000259] -A-XG+----- * ASG int In BB297 New Local Subrange Assertion: V50 in [0..65535], index = #01 fgMorphTree BB297, STMT00066 (after) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 fgMorphTree BB297, STMT00067 (before) [000263] -A--------- * ASG int [000262] D------N--- +--* LCL_VAR int V18 loc14 [000261] ----------- \--* LCL_VAR int V50 tmp10 Subrange prop for index #01 in BB297: [003146] ----------- * CAST int <- ushort <- int fgMorphTree BB297, STMT00068 (before) [000266] ----------- * JTRUE void [000265] ----------- \--* EQ int [000260] ----------- +--* LCL_VAR int V50 tmp10 [000264] ----------- \--* CNS_INT int 0 Morphing BB298 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB298, STMT00069 (before) [000270] ----------- * JTRUE void [000269] N--------U- \--* NE int [000267] ----------- +--* LCL_VAR int V18 loc14 [000268] ----------- \--* CNS_INT int 59 Morphing BB299 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB299, STMT00055 (before) [000214] -A--------- * ASG byref [000213] D------N--- +--* LCL_VAR byref V35 loc31 [000212] ----------- \--* CNS_INT long 0 GenTreeNode creates assertion: [000214] -A---+----- * ASG byref In BB299 New Local Constant Assertion: V35 == 0, index = #01 fgMorphTree BB299, STMT00056 (before) [000219] ---XG------ * JTRUE void [000218] ---XG------ \--* EQ int [000216] ---XG------ +--* FIELD bool : [000215] ----------- | \--* LCL_VAR byref V01 arg1 [000217] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [000216] ---XG------ * IND bool [003148] -----+----- \--* ADD byref [000215] -----+----- +--* LCL_VAR byref V01 arg1 [003147] -----+----- \--* CNS_INT long 8 fgMorphTree BB299, STMT00056 (after) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 Morphing BB300 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB300, STMT00058 (before) [000224] ----------- * JTRUE void [000223] ----------- \--* NE int [000221] ----------- +--* LCL_VAR int V15 loc11 [000222] ----------- \--* CNS_INT int 0 Morphing BB301 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB301, STMT00059 (before) [000229] ---XG------ * JTRUE void [000228] ---XG------ \--* NE int [000226] ---XG------ +--* FIELD int : [000225] ----------- | \--* LCL_VAR byref V01 arg1 [000227] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [000226] ---XG------ * IND int [003150] -----+----- \--* ADD byref [000225] -----+----- +--* LCL_VAR byref V01 arg1 [003149] -----+----- \--* CNS_INT long 4 fgMorphTree BB301, STMT00059 (after) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 Morphing BB302 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB302, STMT00061 (before) [000235] --C-------- * JTRUE void [000234] --C-------- \--* LE int [002539] ---XG------ +--* FIELD int : [000230] ----------- | \--* LCL_VAR byref V00 arg0 [000233] ----------- \--* CNS_INT int 0 Final value of Compiler::fgMorphField after morphing: [002539] ---XG------ * IND int [003152] -----+----- \--* ADD byref [000230] -----+----- +--* LCL_VAR byref V00 arg0 [003151] -----+----- \--* CNS_INT long 8 fgMorphTree BB302, STMT00061 (after) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 Morphing BB303 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB303, STMT00063 (before) [000241] --C-G------ * CALL r2r_ind void [000236] ----------- this +--* LCL_VAR byref V00 arg0 [000237] ----------- arg1 +--* CNS_INT int 0 [002541] ---XG------ arg2 \--* FIELD ref : [000238] ----------- \--* LCL_VAR ref V03 arg3 Rejecting tail call in morph for call [000241]: Local address taken V02 Initializing arg info for 241.CALL: Args for call [000241] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000236].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[003153].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, wellKnown[R2RIndirectionCell]] CallArg[[000237].CNS_INT int (By value), 1 reg: x1, byteAlignment=8] CallArg[[002541].FIELD ref (By value), 1 reg: x2, byteAlignment=8] Morphing args for 241.CALL: Final value of Compiler::fgMorphField after morphing: [002541] ---XG------ * IND ref [003155] -----+----- \--* ADD byref [000238] -----+----- +--* LCL_VAR ref V03 arg3 [003154] -----+----- \--* CNS_INT long 40 Fseq[] GenTreeNode creates assertion: [002541] ---XG+----- * IND ref In BB303 New Local Constant Assertion: V03 != null, index = #01 Sorting the arguments: Deferred argument ('x2'): [002541] ---XG+----- * IND ref [003155] -----+----- \--* ADD byref [000238] -----+----- +--* LCL_VAR ref V03 arg3 [003154] -----+----- \--* CNS_INT long 40 Fseq[] Moved to late list Deferred argument ('x0'): [000236] -----+----- * LCL_VAR byref V00 arg0 Moved to late list Deferred argument ('x11'): [003153] H----+----- * CNS_INT(h) long 0x4000000000540210 ftn Moved to late list Deferred argument ('x1'): [000237] -----+----- * CNS_INT int 0 Moved to late list Register placement order: x2 x0 x11 x1 Args for [000241].CALL after fgMorphArgs: CallArg[[000236].LCL_VAR byref (By value), 1 reg: x0, byteAlignment=8, isLate, processed, wellKnown[ThisPointer]] CallArg[[003153].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[000237].CNS_INT int (By value), 1 reg: x1, byteAlignment=8, isLate, processed] CallArg[[002541].IND ref (By value), 1 reg: x2, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB303, STMT00063 (after) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 Morphing BB304 of 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' fgMorphTree BB304, STMT00057 (before) [000220] ----------- * RETURN void *************** In fgMarkDemotedImplicitByRefArgs() *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB79,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB123 (always), preds={BB92,BB93} succs={BB123} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ------------ BB113 [000..000) (throw), preds={BB102} succs={} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB114 [391..392) -> BB117 (cond), preds={BB104} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB94,BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] -----+----- * JTRUE void [001004] J----+-N--- \--* GT int [001002] -----+----- +--* LCL_VAR int V32 loc28 [001003] -----+----- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB95,BB123} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --CXG+----- * CALL r2r_ind void [002312] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000445] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003065] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE GS Cookie lvaGrabTemp returning 170 (V170 tmp130) (a long lifetime temp) called for GSSecurityCookie. Local V170 should not be enregistered because: it is address exposed Equivalence assign group isPtr : V00 arg0 V60 tmp20 V62 tmp22 V87 tmp47 V88 tmp48 V91 tmp51 V93 tmp53 V96 tmp56 V97 tmp57 V99 tmp59 V100 tmp60 V103 tmp63 V104 tmp64 V107 tmp67 V108 tmp68 V111 tmp71 V112 tmp72 V115 tmp75 V116 tmp76 V118 tmp78 V120 tmp80 V122 tmp82 V124 tmp84 V126 tmp86 V127 tmp87 V129 tmp89 V130 tmp90 V132 tmp92 V134 tmp94 V136 tmp96 V138 tmp98 V140 tmp100 V141 tmp101 Equivalence assign group isPtr : V01 arg1 V04 loc0 V05 loc1 V06 loc2 V07 loc3 V08 loc4 V10 loc6 V14 loc10 V31 loc27 V32 loc28 V44 tmp4 V45 tmp5 V46 tmp6 V55 tmp15 V64 tmp24 V65 tmp25 V66 tmp26 V67 tmp27 V69 tmp29 V70 tmp30 V76 tmp36 Equivalence assign group isPtr : V02 arg2 V23 loc19 V35 loc31 V147 tmp107 V148 tmp108 V149 tmp109 V150 tmp110 V155 tmp115 V156 tmp116 V157 tmp117 V158 tmp118 V165 tmp125 V166 tmp126 Equivalence assign group isPtr : V03 arg3 V26 loc22 V29 loc25 V86 tmp46 V95 tmp55 V102 tmp62 V106 tmp66 V110 tmp70 V114 tmp74 Equivalence assign group isPtr : V15 loc11 V16 loc12 V49 tmp9 V51 tmp11 V52 tmp12 V53 tmp13 V54 tmp14 V59 tmp19 V71 tmp31 V73 tmp33 V74 tmp34 Equivalence assign group isPtr : V01 arg1 V17 loc13 V36 loc32 V56 tmp16 V57 tmp17 V61 tmp21 V63 tmp23 V76 tmp36 V92 tmp52 V167 tmp127 Equivalence assign group isPtr : V01 arg1 V02 arg2 V15 loc11 V16 loc12 V17 loc13 V18 loc14 V22 loc18 V23 loc19 V34 loc30 V35 loc31 V36 loc32 V49 tmp9 V50 tmp10 V51 tmp11 V52 tmp12 V53 tmp13 V54 tmp14 V56 tmp16 V57 tmp17 V58 tmp18 V59 tmp19 V61 tmp21 V63 tmp23 V71 tmp31 V72 tmp32 V73 tmp33 V74 tmp34 V76 tmp36 V92 tmp52 V119 tmp79 V123 tmp83 V133 tmp93 V137 tmp97 V147 tmp107 V148 tmp108 V149 tmp109 V150 tmp110 V155 tmp115 V156 tmp116 V157 tmp117 V158 tmp118 V165 tmp125 V166 tmp126 V167 tmp127 V168 tmp128 V169 tmp129 Equivalence assign group isPtr : V20 loc16 Equivalence assign group isPtr : V03 arg3 V26 loc22 V27 loc23 V28 loc24 V29 loc25 V30 loc26 Equivalence assign group isPtr : V33 loc29 V81 tmp41 V159 tmp119 V160 tmp120 V161 tmp121 V162 tmp122 V163 tmp123 V164 tmp124 Equivalence assign group isPtr : V33 loc29 V81 tmp41 V82 tmp42 V143 tmp103 V151 tmp111 V159 tmp119 V160 tmp120 V161 tmp121 V162 tmp122 V163 tmp123 V164 tmp124 Equivalence assign group isPtr : V33 loc29 V81 tmp41 V83 tmp43 V144 tmp104 V152 tmp112 V159 tmp119 V160 tmp120 V161 tmp121 V162 tmp122 V163 tmp123 V164 tmp124 *************** Finishing PHASE GS Cookie Trees after GS Cookie ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB79,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB123 (always), preds={BB92,BB93} succs={BB123} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ------------ BB113 [000..000) (throw), preds={BB102} succs={} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB114 [391..392) -> BB117 (cond), preds={BB104} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB94,BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) [001005] -----+----- * JTRUE void [001004] J----+-N--- \--* GT int [001002] -----+----- +--* LCL_VAR int V32 loc28 [001003] -----+----- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB95,BB123} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --CXG+----- * CALL r2r_ind void [002312] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000445] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003065] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Compute edge weights (1, false) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB123 (always) i BB95 [0089] 1 BB123 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 2 BB94,BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 4 BB79,BB85,BB95,BB123 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count -- not optimizing or no profile data, so not computing edge weights *************** Finishing PHASE Compute edge weights (1, false) [no changes] *************** Starting PHASE Create EH funclets *************** Finishing PHASE Create EH funclets [no changes] *************** Starting PHASE Invert loops Duplication of loop condition [001005] is performed, because the cost of duplication (7) is less or equal than 34, loopIterations = 8.000, optInvertTotalInfo.sharedStaticHelperCount >= 0, validProfileWeights = false New Basic Block BB306 [0362] created. Setting edge weights for BB94 -> BB306 to [0 .. 3.402823e+38] Setting edge weights for BB306 -> BB95 to [0 .. 3.402823e+38] Setting edge weights for BB306 -> BB124 to [0 .. 3.402823e+38] Duplicated loop exit block at BB306 for loop (BB95 - BB123) Estimated code size expansion is 7 ------------ BB306 [???..???) -> BB124 (cond), preds={BB94} succs={BB95,BB124} ***** BB306 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 *************** Finishing PHASE Invert loops Trees after Invert loops ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E) i BB306 [0362] 1 BB94 1 [???..???)-> BB124 ( cond ) internal BB95 [0089] 2 BB123,BB306 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 1 BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 5 BB79,BB85,BB95,BB123,BB306 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E), preds={BB92,BB93} succs={BB306} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ------------ BB306 [???..???) -> BB124 (cond), preds={BB94} succs={BB95,BB124} ***** BB306 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB123,BB306} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ------------ BB113 [000..000) (throw), preds={BB102} succs={} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB114 [391..392) -> BB117 (cond), preds={BB104} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB122 [3BB..3C2), preds={BB120,BB121} succs={BB123} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ------------ BB123 [3C2..3C8) -> BB95 (cond), preds={BB122} succs={BB124,BB95} ***** BB123 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB95,BB123,BB306} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --CXG+----- * CALL r2r_ind void [002312] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000445] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003065] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Optimize control flow *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E) i BB306 [0362] 1 BB94 1 [???..???)-> BB124 ( cond ) internal BB95 [0089] 2 BB123,BB306 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C2) i bwd BB123 [0095] 1 BB122 1 [3C2..3C8)-> BB95 ( cond ) i bwd bwd-src BB124 [0096] 5 BB79,BB85,BB95,BB123,BB306 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Considering uncond to cond BB03 -> BB06 Considering uncond to cond BB04 -> BB06 Considering uncond to cond BB05 -> BB06 Considering uncond to cond BB06 -> BB07 Considering uncond to cond BB07 -> BB48 Considering uncond to cond BB12 -> BB48 Considering uncond to cond BB31 -> BB48 Considering uncond to cond BB17 -> BB48 Considering uncond to cond BB19 -> BB20 Considering uncond to cond BB20 -> BB48 Considering uncond to cond BB22 -> BB48 Considering uncond to cond BB27 -> BB48 Considering uncond to cond BB28 -> BB29 Considering uncond to cond BB29 -> BB48 Considering uncond to cond BB30 -> BB48 Considering uncond to cond BB35 -> BB48 Considering uncond to cond BB38 -> BB48 Considering uncond to cond BB47 -> BB48 Considering uncond to cond BB52 -> BB53 Considering uncond to cond BB55 -> BB57 Considering uncond to cond BB56 -> BB57 Considering uncond to cond BB59 -> BB61 Considering uncond to cond BB60 -> BB61 Considering uncond to cond BB63 -> BB07 Considering uncond to cond BB65 -> BB66 Considering uncond to cond BB66 -> BB67 Considering uncond to cond BB68 -> BB70 Considering uncond to cond BB69 -> BB70 Considering uncond to cond BB71 -> BB73 Considering uncond to cond BB72 -> BB73 Considering uncond to cond BB74 -> BB79 Considering uncond to cond BB76 -> BB78 Considering uncond to cond BB77 -> BB78 Considering uncond to cond BB78 -> BB79 Considering uncond to cond BB87 -> BB88 Considering uncond to cond BB89 -> BB91 Considering uncond to cond BB90 -> BB91 Considering uncond to cond BB92 -> BB94 Considering uncond to cond BB93 -> BB94 Considering uncond to cond BB94 -> BB306 Compacting blocks BB94 and BB306: *************** In fgDebugCheckBBlist Considering uncond to cond BB99 -> BB102 Considering uncond to cond BB100 -> BB102 Considering uncond to cond BB104 -> BB114 Considering uncond to cond BB116 -> BB119 Considering uncond to cond BB117 -> BB119 Considering uncond to cond BB119 -> BB120 Considering uncond to cond BB121 -> BB122 Considering uncond to cond BB122 -> BB123 Compacting blocks BB122 and BB123: *************** In fgDebugCheckBBlist Considering uncond to cond BB132 -> BB134 Considering uncond to cond BB133 -> BB134 Considering uncond to cond BB134 -> BB296 Considering uncond to cond BB140 -> BB162 Considering uncond to cond BB142 -> BB144 Considering uncond to cond BB143 -> BB144 Considering uncond to cond BB146 -> BB148 Considering uncond to cond BB147 -> BB148 Considering uncond to cond BB157 -> BB159 Considering uncond to cond BB158 -> BB159 Considering uncond to cond BB159 -> BB160 Considering uncond to cond BB160 -> BB161 Considering uncond to cond BB166 -> BB291 Considering uncond to cond BB212 -> BB213 Considering uncond to cond BB173 -> BB175 Considering uncond to cond BB174 -> BB175 Considering uncond to cond BB175 -> BB182 Considering uncond to cond BB178 -> BB181 Considering uncond to cond BB179 -> BB181 Considering uncond to cond BB180 -> BB181 Considering uncond to cond BB181 -> BB182 Considering uncond to cond BB185 -> BB187 Considering uncond to cond BB186 -> BB187 Considering uncond to cond BB196 -> BB198 Considering uncond to cond BB197 -> BB198 Considering uncond to cond BB198 -> BB199 Considering uncond to cond BB199 -> BB296 Considering uncond to cond BB209 -> BB211 Considering uncond to cond BB210 -> BB211 Considering uncond to cond BB211 -> BB296 Considering uncond to cond BB217 -> BB296 Considering uncond to cond BB218 -> BB296 Considering uncond to cond BB225 -> BB296 Considering uncond to cond BB226 -> BB296 Considering uncond to cond BB230 -> BB233 Considering uncond to cond BB231 -> BB233 Considering uncond to cond BB238 -> BB296 Considering uncond to cond BB243 -> BB296 Considering uncond to cond BB244 -> BB296 Considering uncond to cond BB253 -> BB263 Considering uncond to cond BB259 -> BB296 Considering uncond to cond BB260 -> BB296 Considering uncond to cond BB262 -> BB263 Considering uncond to cond BB266 -> BB267 Considering uncond to cond BB268 -> BB270 Considering uncond to cond BB269 -> BB270 Considering uncond to cond BB270 -> BB296 Considering uncond to cond BB273 -> BB275 Considering uncond to cond BB274 -> BB275 Considering uncond to cond BB280 -> BB287 Considering uncond to cond BB281 -> BB287 Considering uncond to cond BB285 -> BB287 Considering uncond to cond BB286 -> BB287 Considering uncond to cond BB290 -> BB296 Considering uncond to cond BB293 -> BB296 Considering uncond to cond BB294 -> BB296 Considering uncond to cond BB303 -> BB304 Considering uncond to cond BB03 -> BB06 Considering uncond to cond BB04 -> BB06 Considering uncond to cond BB05 -> BB06 Considering uncond to cond BB06 -> BB07 Considering uncond to cond BB07 -> BB48 Considering uncond to cond BB12 -> BB48 Considering uncond to cond BB31 -> BB48 Considering uncond to cond BB17 -> BB48 Considering uncond to cond BB19 -> BB20 Considering uncond to cond BB20 -> BB48 Considering uncond to cond BB22 -> BB48 Considering uncond to cond BB27 -> BB48 Considering uncond to cond BB28 -> BB29 Considering uncond to cond BB29 -> BB48 Considering uncond to cond BB30 -> BB48 Considering uncond to cond BB35 -> BB48 Considering uncond to cond BB38 -> BB48 Considering uncond to cond BB47 -> BB48 Considering uncond to cond BB52 -> BB53 Considering uncond to cond BB55 -> BB57 Considering uncond to cond BB56 -> BB57 Considering uncond to cond BB59 -> BB61 Considering uncond to cond BB60 -> BB61 Considering uncond to cond BB63 -> BB07 Considering uncond to cond BB65 -> BB66 Considering uncond to cond BB66 -> BB67 Considering uncond to cond BB68 -> BB70 Considering uncond to cond BB69 -> BB70 Considering uncond to cond BB71 -> BB73 Considering uncond to cond BB72 -> BB73 Considering uncond to cond BB74 -> BB79 Considering uncond to cond BB76 -> BB78 Considering uncond to cond BB77 -> BB78 Considering uncond to cond BB78 -> BB79 Considering uncond to cond BB87 -> BB88 Considering uncond to cond BB89 -> BB91 Considering uncond to cond BB90 -> BB91 Considering uncond to cond BB92 -> BB94 Considering uncond to cond BB93 -> BB94 Considering uncond to cond BB99 -> BB102 Considering uncond to cond BB100 -> BB102 Considering uncond to cond BB104 -> BB114 Considering uncond to cond BB116 -> BB119 Considering uncond to cond BB117 -> BB119 Considering uncond to cond BB119 -> BB120 Considering uncond to cond BB121 -> BB122 Considering uncond to cond BB132 -> BB134 Considering uncond to cond BB133 -> BB134 Considering uncond to cond BB134 -> BB296 Considering uncond to cond BB140 -> BB162 Considering uncond to cond BB142 -> BB144 Considering uncond to cond BB143 -> BB144 Considering uncond to cond BB146 -> BB148 Considering uncond to cond BB147 -> BB148 Considering uncond to cond BB157 -> BB159 Considering uncond to cond BB158 -> BB159 Considering uncond to cond BB159 -> BB160 Considering uncond to cond BB160 -> BB161 Considering uncond to cond BB166 -> BB291 Considering uncond to cond BB212 -> BB213 Considering uncond to cond BB173 -> BB175 Considering uncond to cond BB174 -> BB175 Considering uncond to cond BB175 -> BB182 Considering uncond to cond BB178 -> BB181 Considering uncond to cond BB179 -> BB181 Considering uncond to cond BB180 -> BB181 Considering uncond to cond BB181 -> BB182 Considering uncond to cond BB185 -> BB187 Considering uncond to cond BB186 -> BB187 Considering uncond to cond BB196 -> BB198 Considering uncond to cond BB197 -> BB198 Considering uncond to cond BB198 -> BB199 Considering uncond to cond BB199 -> BB296 Considering uncond to cond BB209 -> BB211 Considering uncond to cond BB210 -> BB211 Considering uncond to cond BB211 -> BB296 Considering uncond to cond BB217 -> BB296 Considering uncond to cond BB218 -> BB296 Considering uncond to cond BB225 -> BB296 Considering uncond to cond BB226 -> BB296 Considering uncond to cond BB230 -> BB233 Considering uncond to cond BB231 -> BB233 Considering uncond to cond BB238 -> BB296 Considering uncond to cond BB243 -> BB296 Considering uncond to cond BB244 -> BB296 Considering uncond to cond BB253 -> BB263 Considering uncond to cond BB259 -> BB296 Considering uncond to cond BB260 -> BB296 Considering uncond to cond BB262 -> BB263 Considering uncond to cond BB266 -> BB267 Considering uncond to cond BB268 -> BB270 Considering uncond to cond BB269 -> BB270 Considering uncond to cond BB270 -> BB296 Considering uncond to cond BB273 -> BB275 Considering uncond to cond BB274 -> BB275 Considering uncond to cond BB280 -> BB287 Considering uncond to cond BB281 -> BB287 Considering uncond to cond BB285 -> BB287 Considering uncond to cond BB286 -> BB287 Considering uncond to cond BB290 -> BB296 Considering uncond to cond BB293 -> BB296 Considering uncond to cond BB294 -> BB296 Considering uncond to cond BB303 -> BB304 After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB124 ( cond ) i BB95 [0089] 2 BB94,BB122 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C8)-> BB95 ( cond ) i bwd BB124 [0096] 5 BB79,BB85,BB94,BB95,BB122 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB124 ( cond ) i BB95 [0089] 2 BB94,BB122 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C8)-> BB95 ( cond ) i bwd BB124 [0096] 5 BB79,BB85,BB94,BB95,BB122 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB124 ( cond ) i BB95 [0089] 2 BB94,BB122 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C8)-> BB95 ( cond ) i bwd BB124 [0096] 5 BB79,BB85,BB94,BB95,BB122 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize control flow Trees after Optimize control flow ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB124 ( cond ) i BB95 [0089] 2 BB94,BB122 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C8)-> BB95 ( cond ) i bwd BB124 [0096] 5 BB79,BB85,BB94,BB95,BB122 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB296 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 1 BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 28 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB124 (cond), preds={BB92,BB93} succs={BB95,BB124} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ***** BB94 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB94,BB122} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ------------ BB113 [000..000) (throw), preds={BB102} succs={} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB114 [391..392) -> BB117 (cond), preds={BB104} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB122 [3BB..3C8) -> BB95 (cond), preds={BB120,BB121} succs={BB124,BB95} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ***** BB122 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB94,BB95,BB122} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB260 STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --CXG+----- * CALL r2r_ind void [002312] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000445] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003065] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB260,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Post-morph tail merge A set of 2 preds of BB296 end with the same tree STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --CXG+----- * CALL r2r_ind void [002312] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000445] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003065] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn Will cross-jump to BB294 unlinking STMT00463 ( INL58 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002313] --CXG+----- * CALL r2r_ind void [002312] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000445] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003065] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn from BB260 BB260 becomes empty Setting edge weights for BB260 -> BB294 to [0 .. 3.402823e+38] Did 1 tail merges in BB296 *************** Finishing PHASE Post-morph tail merge Trees after Post-morph tail merge ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB124 ( cond ) i BB95 [0089] 2 BB94,BB122 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C8)-> BB95 ( cond ) i bwd BB124 [0096] 5 BB79,BB85,BB94,BB95,BB122 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB294 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 2 BB260,BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 27 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB48 (always), preds={BB06,BB63} succs={BB48} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB50} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB32,BB48} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB48} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB39 (cond), preds={BB10} succs={BB12,BB39} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB48 (always), preds={BB11} succs={BB48} ------------ BB13 [0AF..0B8) -> BB36 (cond), preds={BB08} succs={BB14,BB36} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB39 (cond), preds={BB13} succs={BB15,BB39} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB48 (cond), preds={BB14} succs={BB31,BB48} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB31 [137..142) -> BB48 (always), preds={BB15} succs={BB48} ***** BB31 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB48 (always), preds={BB09} succs={BB48} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB48 (always), preds={BB18,BB19} succs={BB48} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB48 (cond), preds={BB10} succs={BB22,BB48} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB48 (always), preds={BB21} succs={BB48} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB48 (cond), preds={BB10} succs={BB24,BB48} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB48 (cond), preds={BB23} succs={BB25,BB48} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB48 (always), preds={BB26} succs={BB48} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB48 (always), preds={BB25,BB28} succs={BB48} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB48 (always), preds={BB09} succs={BB48} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB32 [142..150) -> BB48 (cond), preds={BB09(2),BB34} succs={BB33,BB48} ***** BB32 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB33 [150..15E) -> BB48 (cond), preds={BB32} succs={BB34,BB48} ***** BB33 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB34 [15E..170) -> BB32 (cond), preds={BB33} succs={BB35,BB32} ***** BB34 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB34 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB34 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB35 [170..175) -> BB48 (always), preds={BB34} succs={BB48} ------------ BB36 [175..183) -> BB48 (cond), preds={BB13} succs={BB37,BB48} ***** BB36 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB37 [183..18E) -> BB48 (cond), preds={BB36} succs={BB38,BB48} ***** BB37 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB38 [18E..196) -> BB48 (always), preds={BB37} succs={BB48} ***** BB38 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB39 [196..1A1) -> BB41 (cond), preds={BB11,BB14} succs={BB40,BB41} ***** BB39 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB40 [1A1..1AE) -> BB45 (cond), preds={BB39} succs={BB41,BB45} ***** BB40 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB41 [1AE..1BB) -> BB48 (cond), preds={BB39,BB40} succs={BB42,BB48} ***** BB41 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB42 [1BB..1C8) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB43 [1C8..1D5) -> BB48 (cond), preds={BB42} succs={BB44,BB48} ***** BB43 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB44 [1D5..1E4) -> BB48 (cond), preds={BB42,BB43} succs={BB45,BB48} ***** BB44 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB45 [1E4..1F4) -> BB47 (cond), preds={BB40,BB44,BB46} succs={BB46,BB47} ***** BB45 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB45 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB45 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB46 [1F4..201) -> BB45 (cond), preds={BB45} succs={BB47,BB45} ***** BB46 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB47 [201..204), preds={BB45,BB46} succs={BB48} ***** BB47 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB48 [204..20F) -> BB51 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47} succs={BB49,BB51} ***** BB48 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB49 [20F..222) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB49 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB49 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB49 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB49 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB50 [222..22B) -> BB08 (cond), preds={BB49} succs={BB51,BB08} ***** BB50 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB51 [22B..233) -> BB53 (cond), preds={BB48,BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB51 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB52 [233..235), preds={BB51} succs={BB53} ***** BB52 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB53 [235..23A) -> BB57 (cond), preds={BB51,BB52} succs={BB54,BB57} ***** BB53 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB54 [23A..23F) -> BB56 (cond), preds={BB53} succs={BB55,BB56} ***** BB54 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB55 [23F..24A) -> BB57 (always), preds={BB54} succs={BB57} ***** BB55 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB56 [24A..24D), preds={BB54} succs={BB57} ***** BB56 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB57 [24D..252) -> BB64 (cond), preds={BB53,BB55,BB56} succs={BB58,BB64} ***** BB57 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB58 [252..262) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB58 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB58 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB59 [262..26E) -> BB61 (always), preds={BB58} succs={BB61} ***** BB59 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB60 [26E..26F), preds={BB58} succs={BB61} ***** BB60 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB61 [26F..27F) -> BB67 (cond), preds={BB59,BB60} succs={BB62,BB67} ***** BB61 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB61 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB62 [27F..28E) -> BB67 (cond), preds={BB61} succs={BB63,BB67} ***** BB62 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB62 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB63 [28E..297) -> BB07 (always), preds={BB62} succs={BB07} ***** BB63 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB64 [297..2A0) -> BB66 (cond), preds={BB57} succs={BB65,BB66} ***** BB64 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB65 [2A0..2A7), preds={BB64} succs={BB66} ***** BB65 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB66 [2A7..2AE), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB67 [2AE..2B2) -> BB69 (cond), preds={BB61,BB62,BB66} succs={BB68,BB69} ***** BB67 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB68 [2B2..2B5) -> BB70 (always), preds={BB67} succs={BB70} ***** BB68 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB69 [2B5..2B8), preds={BB67} succs={BB70} ***** BB69 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB70 [2B8..2BD) -> BB72 (cond), preds={BB68,BB69} succs={BB71,BB72} ***** BB70 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB70 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB71 [2BD..2C0) -> BB73 (always), preds={BB70} succs={BB73} ***** BB71 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB72 [2C0..2C3), preds={BB70} succs={BB73} ***** BB72 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB73 [2C3..2C8) -> BB75 (cond), preds={BB71,BB72} succs={BB74,BB75} ***** BB73 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB73 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB74 [2C8..2D0) -> BB79 (always), preds={BB73} succs={BB79} ***** BB74 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB74 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB75 [2D0..2D9) -> BB77 (cond), preds={BB73} succs={BB76,BB77} ***** BB75 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2D9..2DC) -> BB78 (always), preds={BB75} succs={BB78} ***** BB76 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB77 [2DC..2E2), preds={BB75} succs={BB78} ***** BB77 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB78 [2E2..2EE), preds={BB76,BB77} succs={BB79} ***** BB78 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB78 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB79 [000..30D) -> BB124 (cond), preds={BB74,BB78} succs={BB85,BB124} ***** BB79 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB79 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB79 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB79 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB79 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB79 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB79 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB85 [30D..31E) -> BB124 (cond), preds={BB79} succs={BB86,BB124} ***** BB85 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB86 [31E..336) -> BB88 (cond), preds={BB85} succs={BB87,BB88} ***** BB86 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB86 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB86 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB86 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB87 [336..33D), preds={BB86} succs={BB88} ***** BB87 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB88 [33D..348) -> BB90 (cond), preds={BB86,BB87} succs={BB89,BB90} ***** BB88 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB88 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB88 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB89 [348..34B) -> BB91 (always), preds={BB88} succs={BB91} ***** BB89 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB89 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB90 [34B..34D), preds={BB88} succs={BB91} ***** BB90 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB90 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB91 [34D..355) -> BB93 (cond), preds={BB89,BB90} succs={BB92,BB93} ***** BB91 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB91 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB92 [355..359) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB93 [359..35A), preds={BB91} succs={BB94} ***** BB93 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB94 [35A..35E) -> BB124 (cond), preds={BB92,BB93} succs={BB95,BB124} ***** BB94 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ***** BB94 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB95 [35E..362) -> BB124 (cond), preds={BB94,BB122} succs={BB96,BB124} ***** BB95 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB96 [362..373) -> BB120 (cond), preds={BB95} succs={BB97,BB120} ***** BB96 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB96 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB97 [373..39A) -> BB100 (cond), preds={BB96} succs={BB99,BB100} ***** BB97 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB97 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB97 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB99 [383..384) -> BB102 (always), preds={BB97} succs={BB102} ***** BB99 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB100 [383..384), preds={BB97} succs={BB102} ***** BB100 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB100 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB102 [000..000) -> BB113 (cond), preds={BB99,BB100} succs={BB104,BB113} ***** BB102 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB102 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB104 [000..000) -> BB114 (always), preds={BB102} succs={BB114} ***** BB104 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB104 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB104 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB104 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ------------ BB113 [000..000) (throw), preds={BB102} succs={} ***** BB113 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB114 [391..392) -> BB117 (cond), preds={BB104} succs={BB116,BB117} ***** BB114 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB114 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB116 [391..392) -> BB119 (always), preds={BB114} succs={BB119} ***** BB116 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB117 [391..392), preds={BB114} succs={BB119} ***** BB117 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB117 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB119 [???..???), preds={BB116,BB117} succs={BB120} ***** BB119 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB120 [39A..3AE) -> BB122 (cond), preds={BB96,BB119} succs={BB121,BB122} ***** BB120 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB120 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB121 [3AE..3BB), preds={BB120} succs={BB122} ***** BB121 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB121 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB122 [3BB..3C8) -> BB95 (cond), preds={BB120,BB121} succs={BB124,BB95} ***** BB122 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ***** BB122 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB124 [3C8..3D0) -> BB134 (cond), preds={BB79,BB85,BB94,BB95,BB122} succs={BB125,BB134} ***** BB124 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB125 [3D0..3D4) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB126 [3D4..3DC) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB127 [3DC..3E8) -> BB134 (cond), preds={BB126} succs={BB130,BB134} ***** BB127 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB127 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB130 [3DC..3DD) -> BB133 (cond), preds={BB127} succs={BB131,BB133} ***** BB130 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB130 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB131 [3DC..3DD) -> BB133 (cond), preds={BB130} succs={BB132,BB133} ***** BB131 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB132 [3DC..3DD) -> BB134 (always), preds={BB131} succs={BB134} ***** BB132 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB132 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB132 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB133 [3DC..3DD), preds={BB130,BB131} succs={BB134} ***** BB133 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB134 [3E8..401) -> BB296 (always), preds={BB124,BB125,BB126,BB127,BB132,BB133} succs={BB296} ***** BB134 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB134 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB134 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB134 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB134 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB136 [401..406) -> BB162 (cond), preds={BB298} succs={BB137,BB162} ***** BB136 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB137 [406..40C) -> BB161 (cond), preds={BB136} succs={BB138,BB161} ***** BB137 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB138 [40C..412) -> BB161 (cond), preds={BB137} succs={BB139,BB161} ***** BB138 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB139 [412..418) -> BB161 (cond), preds={BB138} succs={BB140,BB161} ***** BB139 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB140 [418..41A) -> BB162 (always), preds={BB139} succs={BB162} ------------ BB141 [41A..420) -> BB143 (cond), preds={BB161} succs={BB142,BB143} ***** BB141 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB141 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB142 [420..424) -> BB144 (always), preds={BB141} succs={BB144} ***** BB142 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB142 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB143 [424..42C), preds={BB141} succs={BB144} ***** BB143 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB143 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB143 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB143 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB144 [000..435) -> BB147 (cond), preds={BB142,BB143} succs={BB146,BB147} ***** BB144 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB144 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB144 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB146 [000..000) -> BB148 (always), preds={BB144} succs={BB148} ***** BB146 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB146 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB146 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB147 [000..000), preds={BB144} succs={BB148} ***** BB147 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB148 [???..???) -> BB160 (cond), preds={BB146,BB147} succs={BB149,BB160} ***** BB148 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB149 [435..43A) -> BB160 (cond), preds={BB148} succs={BB150,BB160} ***** BB149 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB150 [43A..43F) -> BB160 (cond), preds={BB149} succs={BB151,BB160} ***** BB150 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB151 [43F..44F) -> BB160 (cond), preds={BB150} succs={BB152,BB160} ***** BB151 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB152 [44F..461) -> BB159 (cond), preds={BB151} succs={BB155,BB159} ***** BB152 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB152 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB155 [44F..450) -> BB158 (cond), preds={BB152} succs={BB156,BB158} ***** BB155 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB155 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB156 [44F..450) -> BB158 (cond), preds={BB155} succs={BB157,BB158} ***** BB156 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB157 [44F..450) -> BB159 (always), preds={BB156} succs={BB159} ***** BB157 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB157 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB157 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB158 [44F..450), preds={BB155,BB156} succs={BB159} ***** BB158 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB159 [???..???), preds={BB152,BB157,BB158} succs={BB160} ***** BB159 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB160 [461..46D), preds={BB148,BB149,BB150,BB151,BB159} succs={BB161} ***** BB160 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB160 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB161 [46D..472) -> BB141 (cond), preds={BB137,BB138,BB139,BB160} succs={BB162,BB141} ***** BB161 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB162 [472..478) -> BB167 (cond), preds={BB136,BB140,BB161} succs={BB163,BB167} ***** BB162 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB163 [478..49A) -> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch), preds={BB162} succs={BB164,BB171,BB220,BB233,BB291} ***** BB163 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB164 [49A..4B8) -> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch), preds={BB163} succs={BB165,BB171,BB200,BB291,BB296} ***** BB164 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB165 [4B8..4C1) -> BB246 (cond), preds={BB164} succs={BB166,BB246} ***** BB165 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB166 [4C1..4C6) -> BB291 (always), preds={BB165} succs={BB291} ------------ BB167 [4C6..4CF) -> BB239 (cond), preds={BB162} succs={BB168,BB239} ***** BB167 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB168 [4CF..4D8) -> BB246 (cond), preds={BB167} succs={BB169,BB246} ***** BB168 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB169 [4D8..4E4) -> BB291 (cond), preds={BB168} succs={BB212,BB291} ***** BB169 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB212 [598..5A9) -> BB213 (always), preds={BB169} succs={BB213} ***** BB212 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB171 [4E9..4EE) -> BB176 (cond), preds={BB163,BB164} succs={BB172,BB176} ***** BB171 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB172 [4EE..4F9) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB172 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB173 [4F9..4FC) -> BB175 (always), preds={BB172} succs={BB175} ***** BB173 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB174 [4FC..4FE), preds={BB172} succs={BB175} ***** BB174 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB175 [4FE..502) -> BB182 (always), preds={BB173,BB174} succs={BB182} ***** BB175 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB176 [502..507) -> BB180 (cond), preds={BB171} succs={BB177,BB180} ***** BB176 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB177 [507..50C) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB178 [50C..50F) -> BB181 (always), preds={BB177} succs={BB181} ***** BB178 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB179 [50F..513) -> BB181 (always), preds={BB177} succs={BB181} ***** BB179 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB180 [513..51B), preds={BB176} succs={BB181} ***** BB180 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB180 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB180 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB181 [51B..51D), preds={BB178,BB179,BB180} succs={BB182} ***** BB181 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB182 [51D..521) -> BB199 (cond), preds={BB175,BB181} succs={BB183,BB199} ***** BB182 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB183 [521..52D) -> BB186 (cond), preds={BB182} succs={BB185,BB186} ***** BB183 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB183 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB185 [521..522) -> BB187 (always), preds={BB183} succs={BB187} ***** BB185 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB185 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB185 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB186 [521..522), preds={BB183} succs={BB187} ***** BB186 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB187 [???..???) -> BB199 (cond), preds={BB185,BB186} succs={BB188,BB199} ***** BB187 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB188 [52D..532) -> BB199 (cond), preds={BB187} succs={BB189,BB199} ***** BB188 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB189 [532..537) -> BB199 (cond), preds={BB188} succs={BB190,BB199} ***** BB189 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB190 [537..547) -> BB199 (cond), preds={BB189} succs={BB191,BB199} ***** BB190 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB191 [547..559) -> BB198 (cond), preds={BB190} succs={BB194,BB198} ***** BB191 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB191 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB194 [547..548) -> BB197 (cond), preds={BB191} succs={BB195,BB197} ***** BB194 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB194 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB195 [547..548) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB196 [547..548) -> BB198 (always), preds={BB195} succs={BB198} ***** BB196 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB196 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB196 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB197 [547..548), preds={BB194,BB195} succs={BB198} ***** BB197 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB198 [???..???), preds={BB191,BB196,BB197} succs={BB199} ***** BB198 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB199 [559..564) -> BB296 (always), preds={BB182,BB187,BB188,BB189,BB190,BB198} succs={BB296} ***** BB199 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB200 [564..571) -> BB296 (cond), preds={BB164} succs={BB201,BB296} ***** BB200 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB201 [571..575) -> BB204 (cond), preds={BB200} succs={BB202,BB204} ***** BB201 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB202 [575..57C) -> BB296 (cond), preds={BB201} succs={BB203,BB296} ***** BB202 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB203 [57C..584) -> BB296 (cond), preds={BB202} succs={BB204,BB296} ***** BB203 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB204 [584..598) -> BB211 (cond), preds={BB201,BB203} succs={BB207,BB211} ***** BB204 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB204 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB207 [584..585) -> BB210 (cond), preds={BB204} succs={BB208,BB210} ***** BB207 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB207 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB208 [584..585) -> BB210 (cond), preds={BB207} succs={BB209,BB210} ***** BB208 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB209 [584..585) -> BB211 (always), preds={BB208} succs={BB211} ***** BB209 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB209 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB209 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB210 [584..585), preds={BB207,BB208} succs={BB211} ***** BB210 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB211 [???..???) -> BB296 (always), preds={BB204,BB209,BB210} succs={BB296} ***** BB211 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB213 [598..599) -> BB296 (cond), preds={BB212} succs={BB215,BB296} ***** BB213 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB215 [598..599) -> BB218 (cond), preds={BB213} succs={BB216,BB218} ***** BB215 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB216 [598..599) -> BB218 (cond), preds={BB215} succs={BB217,BB218} ***** BB216 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB217 [598..599) -> BB296 (always), preds={BB216} succs={BB296} ***** BB217 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB217 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB217 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB218 [598..599) -> BB296 (always), preds={BB215,BB216} succs={BB296} ***** BB218 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB220 [5A9..5BA) -> BB296 (cond), preds={BB163} succs={BB223,BB296} ***** BB220 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB220 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB223 [5A9..5AA) -> BB226 (cond), preds={BB220} succs={BB224,BB226} ***** BB223 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB223 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB224 [5A9..5AA) -> BB226 (cond), preds={BB223} succs={BB225,BB226} ***** BB224 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB225 [5A9..5AA) -> BB296 (always), preds={BB224} succs={BB296} ***** BB225 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB225 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB225 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB226 [5A9..5AA) -> BB296 (always), preds={BB223,BB224} succs={BB296} ***** BB226 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB228 [000..5CE) -> BB231 (cond), preds={BB235} succs={BB230,BB231} ***** BB228 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB228 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB228 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB228 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB228 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB230 [000..000) -> BB233 (always), preds={BB228} succs={BB233} ***** BB230 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB230 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB230 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB231 [000..000), preds={BB228} succs={BB233} ***** BB231 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB233 [5CE..5D9) -> BB236 (cond), preds={BB163(2),BB230,BB231} succs={BB234,BB236} ***** BB233 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB234 [5D9..5E4) -> BB236 (cond), preds={BB233} succs={BB235,BB236} ***** BB234 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB235 [5E4..5F1) -> BB228 (cond), preds={BB234} succs={BB236,BB228} ***** BB235 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB236 [5F1..5FF) -> BB296 (cond), preds={BB233,BB234,BB235} succs={BB237,BB296} ***** BB236 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB237 [5FF..60D) -> BB296 (cond), preds={BB236} succs={BB238,BB296} ***** BB237 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB238 [60D..618) -> BB296 (always), preds={BB237} succs={BB296} ***** BB238 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB239 [618..626) -> BB296 (cond), preds={BB167} succs={BB240,BB296} ***** BB239 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [626..634) -> BB296 (cond), preds={BB239} succs={BB241,BB296} ***** BB240 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB241 [000..64D) -> BB244 (cond), preds={BB240} succs={BB243,BB244} ***** BB241 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB241 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB241 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB241 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB241 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB243 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB243 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB243 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB244 [000..000) -> BB296 (always), preds={BB241} succs={BB296} ***** BB244 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB246 [64D..65A) -> BB271 (cond), preds={BB165,BB168} succs={BB247,BB271} ***** BB246 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB246 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB247 [65A..665) -> BB250 (cond), preds={BB246} succs={BB248,BB250} ***** BB247 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB248 [665..672) -> BB262 (cond), preds={BB247} succs={BB250,BB262} ***** BB248 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB250 [67A..687) -> BB254 (cond), preds={BB247,BB248} succs={BB251,BB254} ***** BB250 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB251 [687..694) -> BB254 (cond), preds={BB250} succs={BB252,BB254} ***** BB251 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB252 [694..6A3) -> BB254 (cond), preds={BB251} succs={BB253,BB254} ***** BB252 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB253 [6A3..6A8) -> BB263 (always), preds={BB252} succs={BB263} ***** BB253 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB254 [6A8..6B5) -> BB257 (cond), preds={BB250,BB251,BB252} succs={BB255,BB257} ***** BB254 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB255 [6B5..6C2) -> BB257 (cond), preds={BB254} succs={BB256,BB257} ***** BB255 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB256 [6C2..6D1) -> BB263 (cond), preds={BB255} succs={BB257,BB263} ***** BB256 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB257 [6D1..6DE) -> BB260 (cond), preds={BB254,BB255,BB256} succs={BB259,BB260} ***** BB257 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB257 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB259 [6D1..6D2) -> BB296 (always), preds={BB257} succs={BB296} ***** BB259 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB259 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB259 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB260 [6D1..6D2) -> BB294 (always), preds={BB257} succs={BB294} ------------ BB262 [6DE..6E4), preds={BB248,BB264} succs={BB263} ***** BB262 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB263 [6E4..6F4) -> BB265 (cond), preds={BB253,BB256,BB262} succs={BB264,BB265} ***** BB263 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB263 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB263 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB264 [6F4..701) -> BB262 (cond), preds={BB263} succs={BB265,BB262} ***** BB264 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB265 [701..707) -> BB267 (cond), preds={BB263,BB264} succs={BB266,BB267} ***** BB265 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB266 [707..70B), preds={BB265} succs={BB267} ***** BB266 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB267 [70B..710) -> BB269 (cond), preds={BB265,BB266} succs={BB268,BB269} ***** BB267 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB268 [710..71A) -> BB270 (always), preds={BB267} succs={BB270} ***** BB268 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB269 [71A..71B), preds={BB267} succs={BB270} ***** BB269 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB270 [71B..731) -> BB296 (always), preds={BB268,BB269} succs={BB296} ***** BB270 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB270 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB271 [731..744) -> BB274 (cond), preds={BB246} succs={BB273,BB274} ***** BB271 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB271 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB273 [731..732) -> BB275 (always), preds={BB271} succs={BB275} ***** BB273 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB273 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB273 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB274 [731..732), preds={BB271} succs={BB275} ***** BB274 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB275 [???..???) -> BB296 (cond), preds={BB273,BB274} succs={BB276,BB296} ***** BB275 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB276 [744..751) -> BB278 (cond), preds={BB275} succs={BB277,BB278} ***** BB276 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB277 [751..75E) -> BB287 (cond), preds={BB276} succs={BB278,BB287} ***** BB277 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB278 [000..774) -> BB281 (cond), preds={BB276,BB277} succs={BB280,BB281} ***** BB278 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB278 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB278 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB278 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB278 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB280 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB280 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB280 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB280 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB281 [000..000) -> BB287 (always), preds={BB278} succs={BB287} ***** BB281 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB283 [000..788) -> BB286 (cond), preds={BB289} succs={BB285,BB286} ***** BB283 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB283 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB283 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB283 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB283 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB285 [000..000) -> BB287 (always), preds={BB283} succs={BB287} ***** BB285 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB285 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB285 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB286 [000..000), preds={BB283} succs={BB287} ***** BB286 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB287 [788..793) -> BB296 (cond), preds={BB277,BB280,BB281,BB285,BB286} succs={BB289,BB296} ***** BB287 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB289 [793..7A0) -> BB283 (cond), preds={BB287} succs={BB290,BB283} ***** BB289 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB290 [7A0..7A2) -> BB296 (always), preds={BB289} succs={BB296} ------------ BB291 [7A2..7AA) -> BB294 (cond), preds={BB163(2),BB164(2),BB166,BB169} succs={BB293,BB294} ***** BB291 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB291 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB293 [7A2..7A3) -> BB296 (always), preds={BB291} succs={BB296} ***** BB293 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB293 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB293 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB294 [7A2..7A3), preds={BB260,BB291} succs={BB296} ***** BB294 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB296 [7AA..7B5) -> BB299 (cond), preds={BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB270,BB275,BB287,BB290,BB293,BB294} succs={BB297,BB299} ***** BB296 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB297 [7B5..7C8) -> BB299 (cond), preds={BB296} succs={BB298,BB299} ***** BB297 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB297 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB297 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB297 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB297 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB298 [7C8..7D1) -> BB136 (cond), preds={BB297} succs={BB299,BB136} ***** BB298 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB299 [7D1..7DD) -> BB304 (cond), preds={BB296,BB297,BB298} succs={BB300,BB304} ***** BB299 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB299 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB300 [7DD..7E1) -> BB304 (cond), preds={BB299} succs={BB301,BB304} ***** BB300 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB301 [7E1..7E9) -> BB304 (cond), preds={BB300} succs={BB302,BB304} ***** BB301 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB302 [7E9..7F2) -> BB304 (cond), preds={BB301} succs={BB303,BB304} ***** BB302 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB303 [7F2..7FF), preds={BB302} succs={BB304} ***** BB303 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB304 [7FF..800) (return), preds={BB299,BB300,BB301,BB302,BB303} succs={} ***** BB304 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Compute blocks reachability Return blocks: BB304 Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB63 1 [02D..05B)-> BB48 (always) i bwd bwd-target BB08 [0007] 1 BB50 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB32,BB17,BB48,BB30,BB48,BB32,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB48,BB21,BB48,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB39 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB48 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB36 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB39 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB48 ( cond ) i bwd BB31 [0030] 1 BB15 1 [137..142)-> BB48 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB48 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB48 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB48 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB48 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB48 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB48 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB48 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB48 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB48 (always) i bwd BB32 [0031] 3 BB09(2),BB34 1 [142..150)-> BB48 ( cond ) i bwd bwd-target BB33 [0032] 1 BB32 1 [150..15E)-> BB48 ( cond ) i bwd BB34 [0033] 1 BB33 1 [15E..170)-> BB32 ( cond ) i bwd bwd-src BB35 [0034] 1 BB34 1 [170..175)-> BB48 (always) i bwd BB36 [0035] 1 BB13 1 [175..183)-> BB48 ( cond ) i bwd BB37 [0036] 1 BB36 1 [183..18E)-> BB48 ( cond ) i bwd BB38 [0037] 1 BB37 1 [18E..196)-> BB48 (always) i bwd BB39 [0038] 2 BB11,BB14 1 [196..1A1)-> BB41 ( cond ) i bwd BB40 [0039] 1 BB39 1 [1A1..1AE)-> BB45 ( cond ) i bwd BB41 [0040] 2 BB39,BB40 1 [1AE..1BB)-> BB48 ( cond ) i bwd BB42 [0041] 1 BB41 1 [1BB..1C8)-> BB44 ( cond ) i bwd BB43 [0042] 1 BB42 1 [1C8..1D5)-> BB48 ( cond ) i bwd BB44 [0043] 2 BB42,BB43 1 [1D5..1E4)-> BB48 ( cond ) i bwd BB45 [0044] 3 BB40,BB44,BB46 1 [1E4..1F4)-> BB47 ( cond ) i bwd bwd-target BB46 [0045] 1 BB45 1 [1F4..201)-> BB45 ( cond ) i bwd bwd-src BB47 [0046] 2 BB45,BB46 1 [201..204) i bwd BB48 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB33,BB35,BB36,BB37,BB38,BB41,BB43,BB44,BB47 1 [204..20F)-> BB51 ( cond ) i bwd BB49 [0048] 1 BB48 1 [20F..222)-> BB51 ( cond ) i bwd BB50 [0049] 1 BB49 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB51 [0050] 3 BB48,BB49,BB50 1 [22B..233)-> BB53 ( cond ) i bwd BB52 [0051] 1 BB51 1 [233..235) i bwd BB53 [0052] 2 BB51,BB52 1 [235..23A)-> BB57 ( cond ) i bwd BB54 [0053] 1 BB53 1 [23A..23F)-> BB56 ( cond ) i bwd BB55 [0054] 1 BB54 1 [23F..24A)-> BB57 (always) i bwd BB56 [0055] 1 BB54 1 [24A..24D) i bwd BB57 [0056] 3 BB53,BB55,BB56 1 [24D..252)-> BB64 ( cond ) i bwd BB58 [0057] 1 BB57 1 [252..262)-> BB60 ( cond ) i nullcheck bwd BB59 [0058] 1 BB58 1 [262..26E)-> BB61 (always) i bwd BB60 [0059] 1 BB58 1 [26E..26F) i bwd BB61 [0060] 2 BB59,BB60 1 [26F..27F)-> BB67 ( cond ) i hascall gcsafe bwd BB62 [0061] 1 BB61 1 [27F..28E)-> BB67 ( cond ) i hascall gcsafe bwd BB63 [0062] 1 BB62 1 [28E..297)-> BB07 (always) i bwd bwd-src BB64 [0063] 1 BB57 1 [297..2A0)-> BB66 ( cond ) i BB65 [0064] 1 BB64 1 [2A0..2A7) i BB66 [0065] 2 BB64,BB65 1 [2A7..2AE) i BB67 [0066] 3 BB61,BB62,BB66 1 [2AE..2B2)-> BB69 ( cond ) i BB68 [0067] 1 BB67 1 [2B2..2B5)-> BB70 (always) i BB69 [0068] 1 BB67 1 [2B5..2B8) i BB70 [0069] 2 BB68,BB69 1 [2B8..2BD)-> BB72 ( cond ) i BB71 [0070] 1 BB70 1 [2BD..2C0)-> BB73 (always) i BB72 [0071] 1 BB70 1 [2C0..2C3) i BB73 [0072] 2 BB71,BB72 1 [2C3..2C8)-> BB75 ( cond ) i BB74 [0073] 1 BB73 1 [2C8..2D0)-> BB79 (always) i BB75 [0074] 1 BB73 1 [2D0..2D9)-> BB77 ( cond ) i BB76 [0075] 1 BB75 1 [2D9..2DC)-> BB78 (always) i BB77 [0076] 1 BB75 1 [2DC..2E2) i BB78 [0077] 2 BB76,BB77 1 [2E2..2EE) i BB79 [0078] 2 BB74,BB78 1 [000..30D)-> BB124 ( cond ) i BB85 [0079] 1 BB79 1 [30D..31E)-> BB124 ( cond ) i idxlen BB86 [0080] 1 BB85 1 [31E..336)-> BB88 ( cond ) i idxlen BB87 [0081] 1 BB86 1 [336..33D) i idxlen BB88 [0082] 2 BB86,BB87 1 [33D..348)-> BB90 ( cond ) i BB89 [0083] 1 BB88 1 [348..34B)-> BB91 (always) i BB90 [0084] 1 BB88 1 [34B..34D) i BB91 [0085] 2 BB89,BB90 1 [34D..355)-> BB93 ( cond ) i BB92 [0086] 1 BB91 1 [355..359)-> BB94 (always) i BB93 [0087] 1 BB91 1 [359..35A) i BB94 [0088] 2 BB92,BB93 1 [35A..35E)-> BB124 ( cond ) i BB95 [0089] 2 BB94,BB122 1 [35E..362)-> BB124 ( cond ) i bwd bwd-target BB96 [0090] 1 BB95 1 [362..373)-> BB120 ( cond ) i bwd BB97 [0091] 1 BB96 1 [373..39A)-> BB100 ( cond ) i hascall bwd BB99 [0219] 1 BB97 1 [383..384)-> BB102 (always) i bwd BB100 [0220] 1 BB97 1 [383..384) i idxlen nullcheck bwd BB102 [0224] 2 BB99,BB100 1 [000..000)-> BB113 ( cond ) internal bwd BB104 [0227] 1 BB102 1 [000..000)-> BB114 (always) i internal hascall gcsafe bwd BB113 [0228] 1 BB102 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB114 [0229] 1 BB104 1 [391..392)-> BB117 ( cond ) i bwd BB116 [0242] 1 BB114 1 [391..392)-> BB119 (always) i bwd BB117 [0243] 1 BB114 1 [391..392) i idxlen nullcheck bwd BB119 [0247] 2 BB116,BB117 1 [???..???) internal bwd BB120 [0092] 2 BB96,BB119 1 [39A..3AE)-> BB122 ( cond ) i bwd BB121 [0093] 1 BB120 1 [3AE..3BB) i idxlen bwd BB122 [0094] 2 BB120,BB121 1 [3BB..3C8)-> BB95 ( cond ) i bwd BB124 [0096] 5 BB79,BB85,BB94,BB95,BB122 1 [3C8..3D0)-> BB134 ( cond ) i BB125 [0097] 1 BB124 1 [3D0..3D4)-> BB134 ( cond ) i BB126 [0098] 1 BB125 1 [3D4..3DC)-> BB134 ( cond ) i BB127 [0099] 1 BB126 1 [3DC..3E8)-> BB134 ( cond ) i BB130 [0252] 1 BB127 1 [3DC..3DD)-> BB133 ( cond ) i idxlen BB131 [0253] 1 BB130 1 [3DC..3DD)-> BB133 ( cond ) i BB132 [0254] 1 BB131 1 [3DC..3DD)-> BB134 (always) i idxlen nullcheck BB133 [0255] 2 BB130,BB131 1 [3DC..3DD) i hascall gcsafe BB134 [0256] 6 BB124,BB125,BB126,BB127,BB132,BB133 1 [3E8..401)-> BB296 (always) i BB136 [0101] 1 BB298 1 [401..406)-> BB162 ( cond ) i bwd bwd-target BB137 [0102] 1 BB136 1 [406..40C)-> BB161 ( cond ) i bwd BB138 [0103] 1 BB137 1 [40C..412)-> BB161 ( cond ) i bwd BB139 [0104] 1 BB138 1 [412..418)-> BB161 ( cond ) i bwd BB140 [0105] 1 BB139 1 [418..41A)-> BB162 (always) i bwd BB141 [0106] 1 BB161 1 [41A..420)-> BB143 ( cond ) i bwd bwd-target BB142 [0107] 1 BB141 1 [420..424)-> BB144 (always) i bwd BB143 [0108] 1 BB141 1 [424..42C) i bwd BB144 [0109] 2 BB142,BB143 1 [000..435)-> BB147 ( cond ) i bwd BB146 [0260] 1 BB144 1 [000..000)-> BB148 (always) i internal nullcheck bwd BB147 [0261] 1 BB144 1 [000..000) i internal hascall gcsafe bwd BB148 [0262] 2 BB146,BB147 1 [???..???)-> BB160 ( cond ) internal bwd BB149 [0110] 1 BB148 1 [435..43A)-> BB160 ( cond ) i bwd BB150 [0111] 1 BB149 1 [43A..43F)-> BB160 ( cond ) i bwd BB151 [0112] 1 BB150 1 [43F..44F)-> BB160 ( cond ) i bwd BB152 [0113] 1 BB151 1 [44F..461)-> BB159 ( cond ) i bwd BB155 [0267] 1 BB152 1 [44F..450)-> BB158 ( cond ) i idxlen bwd BB156 [0268] 1 BB155 1 [44F..450)-> BB158 ( cond ) i bwd BB157 [0269] 1 BB156 1 [44F..450)-> BB159 (always) i idxlen nullcheck bwd BB158 [0270] 2 BB155,BB156 1 [44F..450) i hascall gcsafe bwd BB159 [0271] 3 BB152,BB157,BB158 1 [???..???) internal bwd BB160 [0114] 5 BB148,BB149,BB150,BB151,BB159 1 [461..46D) i bwd BB161 [0115] 4 BB137,BB138,BB139,BB160 1 [46D..472)-> BB141 ( cond ) i bwd bwd-src BB162 [0116] 3 BB136,BB140,BB161 1 [472..478)-> BB167 ( cond ) i bwd BB163 [0117] 1 BB162 1 [478..49A)-> BB233,BB171,BB291,BB220,BB291,BB233,BB164[def] (switch) i bwd BB164 [0118] 1 BB163 1 [49A..4B8)-> BB296,BB291,BB200,BB291,BB171,BB165[def] (switch) i bwd BB165 [0119] 1 BB164 1 [4B8..4C1)-> BB246 ( cond ) i bwd BB166 [0120] 1 BB165 1 [4C1..4C6)-> BB291 (always) i bwd BB167 [0121] 1 BB162 1 [4C6..4CF)-> BB239 ( cond ) i bwd BB168 [0122] 1 BB167 1 [4CF..4D8)-> BB246 ( cond ) i bwd BB169 [0123] 1 BB168 1 [4D8..4E4)-> BB291 ( cond ) i bwd BB212 [0148] 1 BB169 1 [598..5A9)-> BB213 (always) i bwd BB171 [0125] 2 BB163,BB164 1 [4E9..4EE)-> BB176 ( cond ) i bwd BB172 [0126] 1 BB171 1 [4EE..4F9)-> BB174 ( cond ) i bwd BB173 [0127] 1 BB172 1 [4F9..4FC)-> BB175 (always) i bwd BB174 [0128] 1 BB172 1 [4FC..4FE) i bwd BB175 [0129] 2 BB173,BB174 1 [4FE..502)-> BB182 (always) i bwd BB176 [0130] 1 BB171 1 [502..507)-> BB180 ( cond ) i bwd BB177 [0131] 1 BB176 1 [507..50C)-> BB179 ( cond ) i bwd BB178 [0132] 1 BB177 1 [50C..50F)-> BB181 (always) i bwd BB179 [0133] 1 BB177 1 [50F..513)-> BB181 (always) i bwd BB180 [0134] 1 BB176 1 [513..51B) i bwd BB181 [0135] 3 BB178,BB179,BB180 1 [51B..51D) i bwd BB182 [0136] 2 BB175,BB181 1 [51D..521)-> BB199 ( cond ) i bwd BB183 [0137] 1 BB182 1 [521..52D)-> BB186 ( cond ) i bwd BB185 [0274] 1 BB183 1 [521..522)-> BB187 (always) i nullcheck bwd BB186 [0275] 1 BB183 1 [521..522) i hascall gcsafe bwd BB187 [0276] 2 BB185,BB186 1 [???..???)-> BB199 ( cond ) internal bwd BB188 [0138] 1 BB187 1 [52D..532)-> BB199 ( cond ) i bwd BB189 [0139] 1 BB188 1 [532..537)-> BB199 ( cond ) i bwd BB190 [0140] 1 BB189 1 [537..547)-> BB199 ( cond ) i bwd BB191 [0141] 1 BB190 1 [547..559)-> BB198 ( cond ) i bwd BB194 [0281] 1 BB191 1 [547..548)-> BB197 ( cond ) i idxlen bwd BB195 [0282] 1 BB194 1 [547..548)-> BB197 ( cond ) i bwd BB196 [0283] 1 BB195 1 [547..548)-> BB198 (always) i idxlen nullcheck bwd BB197 [0284] 2 BB194,BB195 1 [547..548) i hascall gcsafe bwd BB198 [0285] 3 BB191,BB196,BB197 1 [???..???) internal bwd BB199 [0142] 6 BB182,BB187,BB188,BB189,BB190,BB198 1 [559..564)-> BB296 (always) i bwd BB200 [0143] 1 BB164 1 [564..571)-> BB296 ( cond ) i bwd BB201 [0144] 1 BB200 1 [571..575)-> BB204 ( cond ) i bwd BB202 [0145] 1 BB201 1 [575..57C)-> BB296 ( cond ) i bwd BB203 [0146] 1 BB202 1 [57C..584)-> BB296 ( cond ) i bwd BB204 [0147] 2 BB201,BB203 1 [584..598)-> BB211 ( cond ) i bwd BB207 [0290] 1 BB204 1 [584..585)-> BB210 ( cond ) i idxlen bwd BB208 [0291] 1 BB207 1 [584..585)-> BB210 ( cond ) i bwd BB209 [0292] 1 BB208 1 [584..585)-> BB211 (always) i idxlen nullcheck bwd BB210 [0293] 2 BB207,BB208 1 [584..585) i hascall gcsafe bwd BB211 [0294] 3 BB204,BB209,BB210 1 [???..???)-> BB296 (always) internal bwd BB213 [0297] 1 BB212 1 [598..599)-> BB296 ( cond ) i bwd BB215 [0299] 1 BB213 1 [598..599)-> BB218 ( cond ) i idxlen bwd BB216 [0300] 1 BB215 1 [598..599)-> BB218 ( cond ) i bwd BB217 [0301] 1 BB216 1 [598..599)-> BB296 (always) i idxlen nullcheck bwd BB218 [0302] 2 BB215,BB216 1 [598..599)-> BB296 (always) i hascall gcsafe bwd BB220 [0149] 1 BB163 1 [5A9..5BA)-> BB296 ( cond ) i bwd BB223 [0308] 1 BB220 1 [5A9..5AA)-> BB226 ( cond ) i idxlen bwd BB224 [0309] 1 BB223 1 [5A9..5AA)-> BB226 ( cond ) i bwd BB225 [0310] 1 BB224 1 [5A9..5AA)-> BB296 (always) i idxlen nullcheck bwd BB226 [0311] 2 BB223,BB224 1 [5A9..5AA)-> BB296 (always) i hascall gcsafe bwd BB228 [0150] 1 BB235 1 [000..5CE)-> BB231 ( cond ) i bwd bwd-target BB230 [0315] 1 BB228 1 [000..000)-> BB233 (always) i internal nullcheck bwd BB231 [0316] 1 BB228 1 [000..000) i internal hascall gcsafe bwd BB233 [0151] 4 BB163(2),BB230,BB231 1 [5CE..5D9)-> BB236 ( cond ) i bwd BB234 [0152] 1 BB233 1 [5D9..5E4)-> BB236 ( cond ) i bwd BB235 [0153] 1 BB234 1 [5E4..5F1)-> BB228 ( cond ) i bwd bwd-src BB236 [0154] 3 BB233,BB234,BB235 1 [5F1..5FF)-> BB296 ( cond ) i bwd BB237 [0155] 1 BB236 1 [5FF..60D)-> BB296 ( cond ) i bwd BB238 [0156] 1 BB237 1 [60D..618)-> BB296 (always) i bwd BB239 [0157] 1 BB167 1 [618..626)-> BB296 ( cond ) i bwd BB240 [0158] 1 BB239 1 [626..634)-> BB296 ( cond ) i bwd BB241 [0159] 1 BB240 1 [000..64D)-> BB244 ( cond ) i bwd BB243 [0323] 1 BB241 1 [000..000)-> BB296 (always) i internal nullcheck bwd BB244 [0324] 1 BB241 1 [000..000)-> BB296 (always) i internal hascall gcsafe bwd BB246 [0160] 2 BB165,BB168 1 [64D..65A)-> BB271 ( cond ) i bwd BB247 [0161] 1 BB246 1 [65A..665)-> BB250 ( cond ) i bwd BB248 [0162] 1 BB247 1 [665..672)-> BB262 ( cond ) i bwd BB250 [0164] 2 BB247,BB248 1 [67A..687)-> BB254 ( cond ) i bwd BB251 [0165] 1 BB250 1 [687..694)-> BB254 ( cond ) i bwd BB252 [0166] 1 BB251 1 [694..6A3)-> BB254 ( cond ) i bwd BB253 [0167] 1 BB252 1 [6A3..6A8)-> BB263 (always) i bwd BB254 [0168] 3 BB250,BB251,BB252 1 [6A8..6B5)-> BB257 ( cond ) i bwd BB255 [0169] 1 BB254 1 [6B5..6C2)-> BB257 ( cond ) i bwd BB256 [0170] 1 BB255 1 [6C2..6D1)-> BB263 ( cond ) i bwd BB257 [0171] 3 BB254,BB255,BB256 1 [6D1..6DE)-> BB260 ( cond ) i bwd BB259 [0331] 1 BB257 1 [6D1..6D2)-> BB296 (always) i nullcheck bwd BB260 [0332] 1 BB257 1 [6D1..6D2)-> BB294 (always) i hascall gcsafe bwd BB262 [0172] 2 BB248,BB264 1 [6DE..6E4) i bwd bwd-target BB263 [0173] 3 BB253,BB256,BB262 1 [6E4..6F4)-> BB265 ( cond ) i bwd BB264 [0174] 1 BB263 1 [6F4..701)-> BB262 ( cond ) i bwd bwd-src BB265 [0175] 2 BB263,BB264 1 [701..707)-> BB267 ( cond ) i bwd BB266 [0176] 1 BB265 1 [707..70B) i bwd BB267 [0177] 2 BB265,BB266 1 [70B..710)-> BB269 ( cond ) i bwd BB268 [0178] 1 BB267 1 [710..71A)-> BB270 (always) i bwd BB269 [0179] 1 BB267 1 [71A..71B) i bwd BB270 [0180] 2 BB268,BB269 1 [71B..731)-> BB296 (always) i hascall gcsafe bwd BB271 [0181] 1 BB246 1 [731..744)-> BB274 ( cond ) i bwd BB273 [0337] 1 BB271 1 [731..732)-> BB275 (always) i nullcheck bwd BB274 [0338] 1 BB271 1 [731..732) i hascall gcsafe bwd BB275 [0339] 2 BB273,BB274 1 [???..???)-> BB296 ( cond ) i internal bwd BB276 [0182] 1 BB275 1 [744..751)-> BB278 ( cond ) i bwd BB277 [0183] 1 BB276 1 [751..75E)-> BB287 ( cond ) i bwd BB278 [0184] 2 BB276,BB277 1 [000..774)-> BB281 ( cond ) i bwd BB280 [0343] 1 BB278 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB281 [0344] 1 BB278 1 [000..000)-> BB287 (always) i internal hascall gcsafe bwd BB283 [0185] 1 BB289 1 [000..788)-> BB286 ( cond ) i bwd bwd-target BB285 [0348] 1 BB283 1 [000..000)-> BB287 (always) i internal nullcheck bwd BB286 [0349] 1 BB283 1 [000..000) i internal hascall gcsafe bwd BB287 [0350] 5 BB277,BB280,BB281,BB285,BB286 1 [788..793)-> BB296 ( cond ) i bwd BB289 [0187] 1 BB287 1 [793..7A0)-> BB283 ( cond ) i bwd bwd-src BB290 [0188] 1 BB289 1 [7A0..7A2)-> BB296 (always) i bwd BB291 [0189] 6 BB163(2),BB164(2),BB166,BB169 1 [7A2..7AA)-> BB294 ( cond ) i bwd BB293 [0354] 1 BB291 1 [7A2..7A3)-> BB296 (always) i nullcheck bwd BB294 [0355] 2 BB260,BB291 1 [7A2..7A3) i hascall gcsafe bwd BB296 [0190] 27 BB134,BB164,BB199,BB200,BB202,BB203,BB211,BB213,BB217,BB218,BB220,BB225,BB226,BB236,BB237,BB238,BB239,BB240,BB243,BB244,BB259,BB270,BB275,BB287,BB290,BB293,BB294 1 [7AA..7B5)-> BB299 ( cond ) i bwd BB297 [0191] 1 BB296 1 [7B5..7C8)-> BB299 ( cond ) i bwd BB298 [0192] 1 BB297 1 [7C8..7D1)-> BB136 ( cond ) i bwd bwd-src BB299 [0193] 3 BB296,BB297,BB298 1 [7D1..7DD)-> BB304 ( cond ) i BB300 [0194] 1 BB299 1 [7DD..7E1)-> BB304 ( cond ) i BB301 [0195] 1 BB300 1 [7E1..7E9)-> BB304 ( cond ) i BB302 [0196] 1 BB301 1 [7E9..7F2)-> BB304 ( cond ) i BB303 [0197] 1 BB302 1 [7F2..7FF) i hascall gcsafe BB304 [0198] 5 BB299,BB300,BB301,BB302,BB303 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB31 to BB16 Renumber BB32 to BB31 Renumber BB33 to BB32 Renumber BB34 to BB33 Renumber BB35 to BB34 Renumber BB36 to BB35 Renumber BB37 to BB36 Renumber BB38 to BB37 Renumber BB39 to BB38 Renumber BB40 to BB39 Renumber BB41 to BB40 Renumber BB42 to BB41 Renumber BB43 to BB42 Renumber BB44 to BB43 Renumber BB45 to BB44 Renumber BB46 to BB45 Renumber BB47 to BB46 Renumber BB48 to BB47 Renumber BB49 to BB48 Renumber BB50 to BB49 Renumber BB51 to BB50 Renumber BB52 to BB51 Renumber BB53 to BB52 Renumber BB54 to BB53 Renumber BB55 to BB54 Renumber BB56 to BB55 Renumber BB57 to BB56 Renumber BB58 to BB57 Renumber BB59 to BB58 Renumber BB60 to BB59 Renumber BB61 to BB60 Renumber BB62 to BB61 Renumber BB63 to BB62 Renumber BB64 to BB63 Renumber BB65 to BB64 Renumber BB66 to BB65 Renumber BB67 to BB66 Renumber BB68 to BB67 Renumber BB69 to BB68 Renumber BB70 to BB69 Renumber BB71 to BB70 Renumber BB72 to BB71 Renumber BB73 to BB72 Renumber BB74 to BB73 Renumber BB75 to BB74 Renumber BB76 to BB75 Renumber BB77 to BB76 Renumber BB78 to BB77 Renumber BB79 to BB78 Renumber BB85 to BB79 Renumber BB86 to BB80 Renumber BB87 to BB81 Renumber BB88 to BB82 Renumber BB89 to BB83 Renumber BB90 to BB84 Renumber BB91 to BB85 Renumber BB92 to BB86 Renumber BB93 to BB87 Renumber BB94 to BB88 Renumber BB95 to BB89 Renumber BB96 to BB90 Renumber BB97 to BB91 Renumber BB99 to BB92 Renumber BB100 to BB93 Renumber BB102 to BB94 Renumber BB104 to BB95 Renumber BB113 to BB96 Renumber BB114 to BB97 Renumber BB116 to BB98 Renumber BB117 to BB99 Renumber BB119 to BB100 Renumber BB120 to BB101 Renumber BB121 to BB102 Renumber BB122 to BB103 Renumber BB124 to BB104 Renumber BB125 to BB105 Renumber BB126 to BB106 Renumber BB127 to BB107 Renumber BB130 to BB108 Renumber BB131 to BB109 Renumber BB132 to BB110 Renumber BB133 to BB111 Renumber BB134 to BB112 Renumber BB136 to BB113 Renumber BB137 to BB114 Renumber BB138 to BB115 Renumber BB139 to BB116 Renumber BB140 to BB117 Renumber BB141 to BB118 Renumber BB142 to BB119 Renumber BB143 to BB120 Renumber BB144 to BB121 Renumber BB146 to BB122 Renumber BB147 to BB123 Renumber BB148 to BB124 Renumber BB149 to BB125 Renumber BB150 to BB126 Renumber BB151 to BB127 Renumber BB152 to BB128 Renumber BB155 to BB129 Renumber BB156 to BB130 Renumber BB157 to BB131 Renumber BB158 to BB132 Renumber BB159 to BB133 Renumber BB160 to BB134 Renumber BB161 to BB135 Renumber BB162 to BB136 Renumber BB163 to BB137 Renumber BB164 to BB138 Renumber BB165 to BB139 Renumber BB166 to BB140 Renumber BB167 to BB141 Renumber BB168 to BB142 Renumber BB169 to BB143 Renumber BB212 to BB144 Renumber BB171 to BB145 Renumber BB172 to BB146 Renumber BB173 to BB147 Renumber BB174 to BB148 Renumber BB175 to BB149 Renumber BB176 to BB150 Renumber BB177 to BB151 Renumber BB178 to BB152 Renumber BB179 to BB153 Renumber BB180 to BB154 Renumber BB181 to BB155 Renumber BB182 to BB156 Renumber BB183 to BB157 Renumber BB185 to BB158 Renumber BB186 to BB159 Renumber BB187 to BB160 Renumber BB188 to BB161 Renumber BB189 to BB162 Renumber BB190 to BB163 Renumber BB191 to BB164 Renumber BB194 to BB165 Renumber BB195 to BB166 Renumber BB196 to BB167 Renumber BB197 to BB168 Renumber BB198 to BB169 Renumber BB199 to BB170 Renumber BB200 to BB171 Renumber BB201 to BB172 Renumber BB202 to BB173 Renumber BB203 to BB174 Renumber BB204 to BB175 Renumber BB207 to BB176 Renumber BB208 to BB177 Renumber BB209 to BB178 Renumber BB210 to BB179 Renumber BB211 to BB180 Renumber BB213 to BB181 Renumber BB215 to BB182 Renumber BB216 to BB183 Renumber BB217 to BB184 Renumber BB218 to BB185 Renumber BB220 to BB186 Renumber BB223 to BB187 Renumber BB224 to BB188 Renumber BB225 to BB189 Renumber BB226 to BB190 Renumber BB228 to BB191 Renumber BB230 to BB192 Renumber BB231 to BB193 Renumber BB233 to BB194 Renumber BB234 to BB195 Renumber BB235 to BB196 Renumber BB236 to BB197 Renumber BB237 to BB198 Renumber BB238 to BB199 Renumber BB239 to BB200 Renumber BB240 to BB201 Renumber BB241 to BB202 Renumber BB243 to BB203 Renumber BB244 to BB204 Renumber BB246 to BB205 Renumber BB247 to BB206 Renumber BB248 to BB207 Renumber BB250 to BB208 Renumber BB251 to BB209 Renumber BB252 to BB210 Renumber BB253 to BB211 Renumber BB254 to BB212 Renumber BB255 to BB213 Renumber BB256 to BB214 Renumber BB257 to BB215 Renumber BB259 to BB216 Renumber BB260 to BB217 Renumber BB262 to BB218 Renumber BB263 to BB219 Renumber BB264 to BB220 Renumber BB265 to BB221 Renumber BB266 to BB222 Renumber BB267 to BB223 Renumber BB268 to BB224 Renumber BB269 to BB225 Renumber BB270 to BB226 Renumber BB271 to BB227 Renumber BB273 to BB228 Renumber BB274 to BB229 Renumber BB275 to BB230 Renumber BB276 to BB231 Renumber BB277 to BB232 Renumber BB278 to BB233 Renumber BB280 to BB234 Renumber BB281 to BB235 Renumber BB283 to BB236 Renumber BB285 to BB237 Renumber BB286 to BB238 Renumber BB287 to BB239 Renumber BB289 to BB240 Renumber BB290 to BB241 Renumber BB291 to BB242 Renumber BB293 to BB243 Renumber BB294 to BB244 Renumber BB296 to BB245 Renumber BB297 to BB246 Renumber BB298 to BB247 Renumber BB299 to BB248 Renumber BB300 to BB249 Renumber BB301 to BB250 Renumber BB302 to BB251 Renumber BB303 to BB252 Renumber BB304 to BB253 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i BB05 [0004] 1 BB01 1 [025..026) i BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 1 [02D..05B)-> BB47 (always) i bwd bwd-target BB08 [0007] 1 BB49 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 1 [142..150)-> BB47 ( cond ) i bwd bwd-target BB32 [0032] 1 BB31 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 1 [1E4..1F4)-> BB46 ( cond ) i bwd bwd-target BB45 [0045] 1 BB44 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 1 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 1 [233..235) i bwd BB52 [0052] 2 BB50,BB51 1 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 1 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 1 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 1 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 1 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 1 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 1 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 1 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 1 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 1 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 1 [28E..297)-> BB07 (always) i bwd bwd-src BB63 [0063] 1 BB56 1 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 1 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 1 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 1 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 1 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 1 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 1 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 1 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 1 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 1 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 1 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 1 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB104 ( cond ) i BB79 [0079] 1 BB78 1 [30D..31E)-> BB104 ( cond ) i idxlen BB80 [0080] 1 BB79 1 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 1 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 1 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 1 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 1 [34B..34D) i BB85 [0085] 2 BB83,BB84 1 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 1 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 1 [359..35A) i BB88 [0088] 2 BB86,BB87 1 [35A..35E)-> BB104 ( cond ) i BB89 [0089] 2 BB88,BB103 1 [35E..362)-> BB104 ( cond ) i bwd bwd-target BB90 [0090] 1 BB89 1 [362..373)-> BB101 ( cond ) i bwd BB91 [0091] 1 BB90 1 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 1 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 1 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 1 [000..000)-> BB96 ( cond ) internal bwd BB95 [0227] 1 BB94 1 [000..000)-> BB97 (always) i internal hascall gcsafe bwd BB96 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB97 [0229] 1 BB95 1 [391..392)-> BB99 ( cond ) i bwd BB98 [0242] 1 BB97 1 [391..392)-> BB100 (always) i bwd BB99 [0243] 1 BB97 1 [391..392) i idxlen nullcheck bwd BB100 [0247] 2 BB98,BB99 1 [???..???) internal bwd BB101 [0092] 2 BB90,BB100 1 [39A..3AE)-> BB103 ( cond ) i bwd BB102 [0093] 1 BB101 1 [3AE..3BB) i idxlen bwd BB103 [0094] 2 BB101,BB102 1 [3BB..3C8)-> BB89 ( cond ) i bwd BB104 [0096] 5 BB78,BB79,BB88,BB89,BB103 1 [3C8..3D0)-> BB112 ( cond ) i BB105 [0097] 1 BB104 1 [3D0..3D4)-> BB112 ( cond ) i BB106 [0098] 1 BB105 1 [3D4..3DC)-> BB112 ( cond ) i BB107 [0099] 1 BB106 1 [3DC..3E8)-> BB112 ( cond ) i BB108 [0252] 1 BB107 1 [3DC..3DD)-> BB111 ( cond ) i idxlen BB109 [0253] 1 BB108 1 [3DC..3DD)-> BB111 ( cond ) i BB110 [0254] 1 BB109 1 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB111 [0255] 2 BB108,BB109 1 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB104,BB105,BB106,BB107,BB110,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 1 [401..406)-> BB136 ( cond ) i bwd bwd-target BB114 [0102] 1 BB113 1 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 1 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 1 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 1 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 1 [41A..420)-> BB120 ( cond ) i bwd bwd-target BB119 [0107] 1 BB118 1 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 1 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 1 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 1 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 1 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 1 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 1 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 1 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 1 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 1 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 1 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 1 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 1 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 1 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 1 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 1 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 1 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 1 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 1 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 1 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 1 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 1 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 1 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 1 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 1 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 1 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 1 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 1 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 1 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 1 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 1 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 1 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 1 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 1 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 1 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 1 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 1 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 1 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 1 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 1 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 1 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 1 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 1 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 1 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 1 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 1 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 1 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 1 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 1 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 1 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 1 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 1 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 1 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 1 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 1 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 1 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 1 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 1 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 1 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 1 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 1 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 1 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 1 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 1 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 1 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 1 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 1 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 1 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 1 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 1 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 1 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 1 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 1 [000..5CE)-> BB193 ( cond ) i bwd bwd-target BB192 [0315] 1 BB191 1 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 1 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 1 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 1 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 1 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 1 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 1 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 1 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 1 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 1 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 1 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 1 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 1 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 1 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 1 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 1 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 1 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 1 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 1 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 1 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 1 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 1 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 1 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 1 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 1 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 1 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 1 [6DE..6E4) i bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 1 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 1 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 1 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 1 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 1 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 1 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 1 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 1 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 1 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 1 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 1 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 1 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 1 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 1 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 1 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 1 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 1 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 1 [000..788)-> BB238 ( cond ) i bwd bwd-target BB237 [0348] 1 BB236 1 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 1 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 1 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 1 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 1 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 1 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 1 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 1 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 1 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 1 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 1 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 1 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 1 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 1 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 1 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 3, # of blocks (including unused BB00): 254, bitset array size: 4 (long) Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB02 BB03 BB04 : BB01 BB02 BB04 BB05 : BB01 BB05 BB06 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB08 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 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BB01 BB184: BB184 BB183 BB182 BB181 BB144 BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB185: BB185 BB182 BB181 BB144 BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB242: BB242 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB243: BB243 BB242 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB205: BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB206: BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB207: BB207 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB208: BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB209: BB209 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB210: BB210 BB209 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB211: BB211 BB210 BB209 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB212: BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB213: BB213 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB214: BB214 BB213 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB219: BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB220: BB220 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB218: BB218 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB221: BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB222: BB222 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB223: BB223 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB224: BB224 BB223 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB225: BB225 BB223 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB226: BB226 BB223 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB215: BB215 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB216: BB216 BB215 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB217: BB217 BB215 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB244: BB244 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB227: BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB228: BB228 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB229: BB229 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB230: BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB231: BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB232: BB232 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB233: BB233 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB234: BB234 BB233 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB235: BB235 BB233 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB239: BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB240: BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB241: BB241 BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB236: BB236 BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB237: BB237 BB236 BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB238: BB238 BB236 BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB200: BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB201: BB201 BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB202: BB202 BB201 BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB203: BB203 BB202 BB201 BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB204: BB204 BB202 BB201 BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB248: BB248 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB249: BB249 BB248 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB250: BB250 BB249 BB248 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB251: BB251 BB250 BB249 BB248 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB252: BB252 BB251 BB250 BB249 BB248 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB253: BB253 BB248 BB245 BB112 BB104 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB06 BB05 BB02 BB02 : BB04 BB03 BB06 : BB07 BB07 : BB47 BB08 : BB38 BB13 BB09 BB09 : BB31 BB30 BB17 BB10 BB10 : BB23 BB21 BB18 BB11 BB11 : BB12 BB13 : BB35 BB14 BB14 : BB15 BB15 : BB16 BB18 : BB20 BB19 BB21 : BB22 BB23 : BB24 BB24 : BB25 BB25 : BB29 BB26 BB26 : BB28 BB27 BB31 : BB32 BB32 : BB33 BB33 : BB34 BB35 : BB36 BB36 : BB37 BB38 : BB44 BB40 BB39 BB40 : BB41 BB41 : BB43 BB42 BB44 : BB46 BB45 BB47 : BB50 BB48 BB48 : BB49 BB49 : BB08 BB50 : BB52 BB51 BB52 : BB56 BB53 BB53 : BB55 BB54 BB56 : BB66 BB63 BB57 BB57 : BB60 BB59 BB58 BB60 : BB61 BB61 : BB62 BB63 : BB65 BB64 BB66 : BB69 BB68 BB67 BB69 : BB72 BB71 BB70 BB72 : BB78 BB74 BB73 BB74 : BB77 BB76 BB75 BB78 : BB104 BB79 BB79 : BB80 BB80 : BB82 BB81 BB82 : BB85 BB84 BB83 BB85 : BB88 BB87 BB86 BB88 : BB89 BB89 : BB90 BB90 : BB101 BB91 BB91 : BB94 BB93 BB92 BB94 : BB96 BB95 BB95 : BB97 BB97 : BB100 BB99 BB98 BB101 : BB103 BB102 BB104 : BB112 BB105 BB105 : BB106 BB106 : BB107 BB107 : BB108 BB108 : BB111 BB109 BB109 : BB110 BB112 : BB245 BB113 : BB136 BB114 BB114 : BB135 BB115 BB115 : BB116 BB116 : BB117 BB118 : BB121 BB120 BB119 BB121 : BB124 BB123 BB122 BB124 : BB134 BB125 BB125 : BB126 BB126 : BB127 BB127 : BB128 BB128 : BB133 BB129 BB129 : BB132 BB130 BB130 : BB131 BB135 : BB118 BB136 : BB244 BB242 BB205 BB141 BB137 BB137 : BB194 BB186 BB145 BB138 BB138 : BB171 BB139 BB139 : BB140 BB141 : BB200 BB142 BB142 : BB143 BB143 : BB144 BB144 : BB181 BB145 : BB156 BB150 BB146 BB146 : BB149 BB148 BB147 BB150 : BB155 BB154 BB151 BB151 : BB153 BB152 BB156 : BB170 BB157 BB157 : BB160 BB159 BB158 BB160 : BB161 BB161 : BB162 BB162 : BB163 BB163 : BB164 BB164 : BB169 BB165 BB165 : BB168 BB166 BB166 : BB167 BB171 : BB172 BB172 : BB175 BB173 BB173 : BB174 BB175 : BB180 BB176 BB176 : BB179 BB177 BB177 : BB178 BB181 : BB182 BB182 : BB185 BB183 BB183 : BB184 BB186 : BB187 BB187 : BB190 BB188 BB188 : BB189 BB191 : BB193 BB192 BB194 : BB197 BB195 BB195 : BB196 BB196 : BB191 BB197 : BB198 BB198 : BB199 BB200 : BB201 BB201 : BB202 BB202 : BB204 BB203 BB205 : BB227 BB206 BB206 : BB219 BB218 BB208 BB207 BB208 : BB212 BB209 BB209 : BB210 BB210 : BB211 BB212 : BB215 BB213 BB213 : BB214 BB215 : BB217 BB216 BB219 : BB221 BB220 BB221 : BB223 BB222 BB223 : BB226 BB225 BB224 BB227 : BB230 BB229 BB228 BB230 : BB231 BB231 : BB239 BB233 BB232 BB233 : BB235 BB234 BB236 : BB238 BB237 BB239 : BB240 BB240 : BB241 BB236 BB242 : BB243 BB245 : BB248 BB246 BB246 : BB247 BB247 : BB113 BB248 : BB253 BB249 BB249 : BB250 BB250 : BB251 BB251 : BB252 After numbering the dominator tree: BB01: pre=01, post=253 BB02: pre=251, post=252 BB03: pre=253, post=251 BB04: pre=252, post=250 BB05: pre=250, post=249 BB06: pre=02, post=248 BB07: pre=03, post=247 BB08: pre=211, post=243 BB09: pre=228, post=242 BB10: pre=235, post=241 BB11: pre=248, post=240 BB12: pre=249, post=239 BB13: pre=221, post=220 BB14: pre=225, post=219 BB15: pre=226, post=218 BB16: pre=227, post=217 BB17: pre=234, post=226 BB18: pre=245, post=238 BB19: pre=247, post=237 BB20: pre=246, post=236 BB21: pre=243, post=235 BB22: pre=244, post=234 BB23: pre=236, post=233 BB24: pre=237, post=232 BB25: pre=238, post=231 BB26: pre=240, post=230 BB27: pre=242, post=229 BB28: pre=241, post=228 BB29: pre=239, post=227 BB30: pre=233, post=225 BB31: pre=229, post=224 BB32: pre=230, post=223 BB33: pre=231, post=222 BB34: pre=232, post=221 BB35: pre=222, post=216 BB36: pre=223, post=215 BB37: pre=224, post=214 BB38: pre=212, post=213 BB39: pre=220, post=212 BB40: pre=216, post=211 BB41: pre=217, post=210 BB42: pre=219, post=209 BB43: pre=218, post=208 BB44: pre=213, post=207 BB45: pre=215, post=206 BB46: pre=214, post=205 BB47: pre=04, post=246 BB48: pre=209, post=245 BB49: pre=210, post=244 BB50: pre=05, post=204 BB51: pre=208, post=203 BB52: pre=06, post=202 BB53: pre=205, post=201 BB54: pre=207, post=200 BB55: pre=206, post=199 BB56: pre=07, post=198 BB57: pre=199, post=197 BB58: pre=204, post=196 BB59: pre=203, post=195 BB60: pre=200, post=194 BB61: pre=201, post=193 BB62: pre=202, post=192 BB63: pre=196, post=191 BB64: pre=198, post=190 BB65: pre=197, post=189 BB66: pre=08, post=188 BB67: pre=195, post=187 BB68: pre=194, post=186 BB69: pre=09, post=185 BB70: pre=193, post=184 BB71: pre=192, post=183 BB72: pre=10, post=182 BB73: pre=191, post=181 BB74: pre=187, post=180 BB75: pre=190, post=179 BB76: pre=189, post=178 BB77: pre=188, post=177 BB78: pre=11, post=176 BB79: pre=162, post=175 BB80: pre=163, post=174 BB81: pre=186, post=173 BB82: pre=164, post=172 BB83: pre=185, post=171 BB84: pre=184, post=170 BB85: pre=165, post=169 BB86: pre=183, post=168 BB87: pre=182, post=167 BB88: pre=166, post=166 BB89: pre=167, post=165 BB90: pre=168, post=164 BB91: pre=172, post=163 BB92: pre=181, post=162 BB93: pre=180, post=161 BB94: pre=173, post=160 BB95: pre=175, post=159 BB96: pre=174, post=154 BB97: pre=176, post=158 BB98: pre=179, post=157 BB99: pre=178, post=156 BB100: pre=177, post=155 BB101: pre=169, post=153 BB102: pre=171, post=152 BB103: pre=170, post=151 BB104: pre=12, post=150 BB105: pre=155, post=149 BB106: pre=156, post=148 BB107: pre=157, post=147 BB108: pre=158, post=146 BB109: pre=160, post=145 BB110: pre=161, post=144 BB111: pre=159, post=143 BB112: pre=13, post=142 BB113: pre=23, post=138 BB114: pre=133, post=137 BB115: pre=152, post=136 BB116: pre=153, post=135 BB117: pre=154, post=134 BB118: pre=135, post=132 BB119: pre=151, post=131 BB120: pre=150, post=130 BB121: pre=136, post=129 BB122: pre=149, post=128 BB123: pre=148, post=127 BB124: pre=137, post=126 BB125: pre=139, post=125 BB126: pre=140, post=124 BB127: pre=141, post=123 BB128: pre=142, post=122 BB129: pre=144, post=121 BB130: pre=146, post=120 BB131: pre=147, post=119 BB132: pre=145, post=118 BB133: pre=143, post=117 BB134: pre=138, post=116 BB135: pre=134, post=133 BB136: pre=24, post=115 BB137: pre=79, post=114 BB138: pre=120, post=113 BB139: pre=131, post=112 BB140: pre=132, post=111 BB141: pre=65, post=60 BB142: pre=71, post=59 BB143: pre=72, post=58 BB144: pre=73, post=57 BB145: pre=94, post=100 BB146: pre=116, post=99 BB147: pre=119, post=98 BB148: pre=118, post=97 BB149: pre=117, post=96 BB150: pre=110, post=95 BB151: pre=113, post=94 BB152: pre=115, post=93 BB153: pre=114, post=92 BB154: pre=112, post=91 BB155: pre=111, post=90 BB156: pre=95, post=89 BB157: pre=97, post=88 BB158: pre=109, post=87 BB159: pre=108, post=86 BB160: pre=98, post=85 BB161: pre=99, post=84 BB162: pre=100, post=83 BB163: pre=101, post=82 BB164: pre=102, post=81 BB165: pre=104, post=80 BB166: pre=106, post=79 BB167: pre=107, post=78 BB168: pre=105, post=77 BB169: pre=103, post=76 BB170: pre=96, post=75 BB171: pre=121, post=110 BB172: pre=122, post=109 BB173: pre=129, post=108 BB174: pre=130, post=107 BB175: pre=123, post=106 BB176: pre=125, post=105 BB177: pre=127, post=104 BB178: pre=128, post=103 BB179: pre=126, post=102 BB180: pre=124, post=101 BB181: pre=74, post=56 BB182: pre=75, post=55 BB183: pre=77, post=54 BB184: pre=78, post=53 BB185: pre=76, post=52 BB186: pre=89, post=74 BB187: pre=90, post=73 BB188: pre=92, post=72 BB189: pre=93, post=71 BB190: pre=91, post=70 BB191: pre=86, post=66 BB192: pre=88, post=65 BB193: pre=87, post=64 BB194: pre=80, post=69 BB195: pre=84, post=68 BB196: pre=85, post=67 BB197: pre=81, post=63 BB198: pre=82, post=62 BB199: pre=83, post=61 BB200: pre=66, post=51 BB201: pre=67, post=50 BB202: pre=68, post=49 BB203: pre=70, post=48 BB204: pre=69, post=47 BB205: pre=28, post=46 BB206: pre=44, post=45 BB207: pre=64, post=44 BB208: pre=54, post=43 BB209: pre=61, post=42 BB210: pre=62, post=41 BB211: pre=63, post=40 BB212: pre=55, post=39 BB213: pre=59, post=38 BB214: pre=60, post=37 BB215: pre=56, post=36 BB216: pre=58, post=35 BB217: pre=57, post=34 BB218: pre=53, post=33 BB219: pre=45, post=32 BB220: pre=52, post=31 BB221: pre=46, post=30 BB222: pre=51, post=29 BB223: pre=47, post=28 BB224: pre=50, post=27 BB225: pre=49, post=26 BB226: pre=48, post=25 BB227: pre=29, post=24 BB228: pre=43, post=23 BB229: pre=42, post=22 BB230: pre=30, post=21 BB231: pre=31, post=20 BB232: pre=41, post=19 BB233: pre=38, post=18 BB234: pre=40, post=17 BB235: pre=39, post=16 BB236: pre=35, post=13 BB237: pre=37, post=12 BB238: pre=36, post=11 BB239: pre=32, post=15 BB240: pre=33, post=14 BB241: pre=34, post=10 BB242: pre=26, post=09 BB243: pre=27, post=08 BB244: pre=25, post=07 BB245: pre=14, post=141 BB246: pre=21, post=140 BB247: pre=22, post=139 BB248: pre=15, post=06 BB249: pre=17, post=05 BB250: pre=18, post=04 BB251: pre=19, post=03 BB252: pre=20, post=02 BB253: pre=16, post=01 *************** Finishing PHASE Compute blocks reachability Trees after Compute blocks reachability ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 1 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 1 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 1 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 1 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 1 [02D..05B)-> BB47 (always) i gcsafe bwd bwd-target BB08 [0007] 1 BB49 1 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 1 [142..150)-> BB47 ( cond ) i bwd bwd-target BB32 [0032] 1 BB31 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 1 [1E4..1F4)-> BB46 ( cond ) i bwd bwd-target BB45 [0045] 1 BB44 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 1 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 1 [233..235) i bwd BB52 [0052] 2 BB50,BB51 1 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 1 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 1 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 1 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 1 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 1 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 1 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 1 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 1 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 1 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 1 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 1 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 1 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 1 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 1 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 1 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 1 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 1 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 1 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 1 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 1 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 1 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 1 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB104 ( cond ) i BB79 [0079] 1 BB78 1 [30D..31E)-> BB104 ( cond ) i idxlen BB80 [0080] 1 BB79 1 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 1 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 1 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 1 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 1 [34B..34D) i BB85 [0085] 2 BB83,BB84 1 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 1 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 1 [359..35A) i BB88 [0088] 2 BB86,BB87 1 [35A..35E)-> BB104 ( cond ) i BB89 [0089] 2 BB88,BB103 1 [35E..362)-> BB104 ( cond ) i bwd bwd-target BB90 [0090] 1 BB89 1 [362..373)-> BB101 ( cond ) i bwd BB91 [0091] 1 BB90 1 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 1 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 1 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 1 [000..000)-> BB96 ( cond ) internal bwd BB95 [0227] 1 BB94 1 [000..000)-> BB97 (always) i internal hascall gcsafe bwd BB96 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB97 [0229] 1 BB95 1 [391..392)-> BB99 ( cond ) i gcsafe bwd BB98 [0242] 1 BB97 1 [391..392)-> BB100 (always) i gcsafe bwd BB99 [0243] 1 BB97 1 [391..392) i gcsafe idxlen nullcheck bwd BB100 [0247] 2 BB98,BB99 1 [???..???) internal gcsafe bwd BB101 [0092] 2 BB90,BB100 1 [39A..3AE)-> BB103 ( cond ) i bwd BB102 [0093] 1 BB101 1 [3AE..3BB) i idxlen bwd BB103 [0094] 2 BB101,BB102 1 [3BB..3C8)-> BB89 ( cond ) i bwd BB104 [0096] 5 BB78,BB79,BB88,BB89,BB103 1 [3C8..3D0)-> BB112 ( cond ) i BB105 [0097] 1 BB104 1 [3D0..3D4)-> BB112 ( cond ) i BB106 [0098] 1 BB105 1 [3D4..3DC)-> BB112 ( cond ) i BB107 [0099] 1 BB106 1 [3DC..3E8)-> BB112 ( cond ) i BB108 [0252] 1 BB107 1 [3DC..3DD)-> BB111 ( cond ) i idxlen BB109 [0253] 1 BB108 1 [3DC..3DD)-> BB111 ( cond ) i BB110 [0254] 1 BB109 1 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB111 [0255] 2 BB108,BB109 1 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB104,BB105,BB106,BB107,BB110,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 1 [401..406)-> BB136 ( cond ) i bwd bwd-target BB114 [0102] 1 BB113 1 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 1 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 1 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 1 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 1 [41A..420)-> BB120 ( cond ) i bwd bwd-target BB119 [0107] 1 BB118 1 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 1 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 1 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 1 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 1 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 1 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 1 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 1 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 1 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 1 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 1 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 1 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 1 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 1 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 1 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 1 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 1 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 1 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 1 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 1 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 1 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 1 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 1 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 1 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 1 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 1 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 1 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 1 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 1 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 1 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 1 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 1 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 1 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 1 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 1 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 1 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 1 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 1 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 1 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 1 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 1 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 1 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 1 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 1 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 1 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 1 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 1 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 1 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 1 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 1 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 1 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 1 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 1 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 1 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 1 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 1 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 1 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 1 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 1 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 1 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 1 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 1 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 1 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 1 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 1 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 1 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 1 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 1 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 1 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 1 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 1 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 1 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 1 [000..5CE)-> BB193 ( cond ) i bwd bwd-target BB192 [0315] 1 BB191 1 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 1 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 1 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 1 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 1 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 1 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 1 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 1 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 1 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 1 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 1 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 1 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 1 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 1 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 1 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 1 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 1 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 1 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 1 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 1 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 1 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 1 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 1 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 1 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 1 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 1 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 1 [6DE..6E4) i bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 1 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 1 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 1 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 1 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 1 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 1 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 1 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 1 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 1 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 1 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 1 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 1 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 1 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 1 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 1 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 1 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 1 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 1 [000..788)-> BB238 ( cond ) i bwd bwd-target BB237 [0348] 1 BB236 1 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 1 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 1 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 1 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 1 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 1 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 1 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 1 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 1 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 1 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 1 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 1 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 1 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 1 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 1 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB44 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB48 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB78 [000..30D) -> BB104 (cond), preds={BB73,BB77} succs={BB79,BB104} ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB104 (cond), preds={BB78} succs={BB80,BB104} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB82 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB83 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB88 [35A..35E) -> BB104 (cond), preds={BB86,BB87} succs={BB89,BB104} ***** BB88 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB89 [35E..362) -> BB104 (cond), preds={BB88,BB103} succs={BB90,BB104} ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB101 (cond), preds={BB89} succs={BB91,BB101} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB94 [000..000) -> BB96 (cond), preds={BB92,BB93} succs={BB95,BB96} ***** BB94 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB95 [000..000) -> BB97 (always), preds={BB94} succs={BB97} ***** BB95 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB95 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB95 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB95 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ------------ BB96 [000..000) (throw), preds={BB94} succs={} ***** BB96 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB97 [391..392) -> BB99 (cond), preds={BB95} succs={BB98,BB99} ***** BB97 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB97 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB98 [391..392) -> BB100 (always), preds={BB97} succs={BB100} ***** BB98 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB99 [391..392), preds={BB97} succs={BB100} ***** BB99 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB99 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB100 [???..???), preds={BB98,BB99} succs={BB101} ***** BB100 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB101 [39A..3AE) -> BB103 (cond), preds={BB90,BB100} succs={BB102,BB103} ***** BB101 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB101 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB102 [3AE..3BB), preds={BB101} succs={BB103} ***** BB102 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB102 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB103 [3BB..3C8) -> BB89 (cond), preds={BB101,BB102} succs={BB104,BB89} ***** BB103 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ***** BB103 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB104 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB103} succs={BB105,BB112} ***** BB104 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB105 [3D0..3D4) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB106 [3D4..3DC) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB107 [3DC..3E8) -> BB112 (cond), preds={BB106} succs={BB108,BB112} ***** BB107 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB107 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB108 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB109 [3DC..3DD) -> BB111 (cond), preds={BB108} succs={BB110,BB111} ***** BB109 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB110 [3DC..3DD) -> BB112 (always), preds={BB109} succs={BB112} ***** BB110 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB110 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB110 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB111 [3DC..3DD), preds={BB108,BB109} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB104,BB105,BB106,BB107,BB110,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB119 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB120 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB120 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB219 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Set block weights *************** Finishing PHASE Set block weights Trees after Set block weights ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 1 [02D..05B)-> BB47 (always) i gcsafe bwd bwd-target BB08 [0007] 1 BB49 0.50 [05B..061)-> BB13 ( cond ) i bwd bwd-target BB09 [0008] 1 BB08 0.50 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 0.50 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 0.50 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 0.50 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 0.50 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 0.50 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 0.50 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 0.50 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 0.50 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 0.50 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 0.50 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 0.50 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 0.50 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 0.50 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 0.50 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 0.50 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 0.50 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 0.50 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 0.50 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 0.50 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 0.50 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 0.50 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 0.50 [142..150)-> BB47 ( cond ) i bwd bwd-target BB32 [0032] 1 BB31 0.50 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 0.50 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 0.50 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 0.50 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 0.50 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 0.50 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 0.50 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 0.50 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 0.50 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 0.50 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 0.50 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 0.50 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 0.50 [1E4..1F4)-> BB46 ( cond ) i bwd bwd-target BB45 [0045] 1 BB44 0.50 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 0.50 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 0.50 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 0.50 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 1 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 0.50 [233..235) i bwd BB52 [0052] 2 BB50,BB51 1 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 0.50 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 0.50 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 0.50 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 1 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 0.50 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 0.50 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 0.50 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 0.50 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 0.50 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 0.50 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB104 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB104 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB104 ( cond ) i BB89 [0089] 2 BB88,BB103 0.50 [35E..362)-> BB104 ( cond ) i bwd bwd-target BB90 [0090] 1 BB89 0.50 [362..373)-> BB101 ( cond ) i bwd BB91 [0091] 1 BB90 0.50 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 0.50 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 0.50 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 0.50 [000..000)-> BB96 ( cond ) internal bwd BB95 [0227] 1 BB94 0.50 [000..000)-> BB97 (always) i internal hascall gcsafe bwd BB96 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB97 [0229] 1 BB95 0.50 [391..392)-> BB99 ( cond ) i gcsafe bwd BB98 [0242] 1 BB97 0.50 [391..392)-> BB100 (always) i gcsafe bwd BB99 [0243] 1 BB97 0.50 [391..392) i gcsafe idxlen nullcheck bwd BB100 [0247] 2 BB98,BB99 0.50 [???..???) internal gcsafe bwd BB101 [0092] 2 BB90,BB100 0.50 [39A..3AE)-> BB103 ( cond ) i bwd BB102 [0093] 1 BB101 0.50 [3AE..3BB) i idxlen bwd BB103 [0094] 2 BB101,BB102 0.50 [3BB..3C8)-> BB89 ( cond ) i bwd BB104 [0096] 5 BB78,BB79,BB88,BB89,BB103 1 [3C8..3D0)-> BB112 ( cond ) i BB105 [0097] 1 BB104 0.50 [3D0..3D4)-> BB112 ( cond ) i BB106 [0098] 1 BB105 0.50 [3D4..3DC)-> BB112 ( cond ) i BB107 [0099] 1 BB106 0.50 [3DC..3E8)-> BB112 ( cond ) i BB108 [0252] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB109 [0253] 1 BB108 0.50 [3DC..3DD)-> BB111 ( cond ) i BB110 [0254] 1 BB109 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB111 [0255] 2 BB108,BB109 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB104,BB105,BB106,BB107,BB110,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 0.50 [401..406)-> BB136 ( cond ) i bwd bwd-target BB114 [0102] 1 BB113 0.50 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 0.50 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 0.50 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 0.50 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 0.50 [41A..420)-> BB120 ( cond ) i bwd bwd-target BB119 [0107] 1 BB118 0.50 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 0.50 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 0.50 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 0.50 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 0.50 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 0.50 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 0.50 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 0.50 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 0.50 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 0.50 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 0.50 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 0.50 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 0.50 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 0.50 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 0.50 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 0.50 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 0.50 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 0.50 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 0.50 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 0.50 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 0.50 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 0.50 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 0.50 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 0.50 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 0.50 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 0.50 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 0.50 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 0.50 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 0.50 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 0.50 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 0.50 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 0.50 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 0.50 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 0.50 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 0.50 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 0.50 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 0.50 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 0.50 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 0.50 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 0.50 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 0.50 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 0.50 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 0.50 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 0.50 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 0.50 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 0.50 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 0.50 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 0.50 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 0.50 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 0.50 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 0.50 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 0.50 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 0.50 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 0.50 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 0.50 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 0.50 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 0.50 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 0.50 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 0.50 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 0.50 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 0.50 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 0.50 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 0.50 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 0.50 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 0.50 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 0.50 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 0.50 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 0.50 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 0.50 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 0.50 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 0.50 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 0.50 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 0.50 [000..5CE)-> BB193 ( cond ) i bwd bwd-target BB192 [0315] 1 BB191 0.50 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 0.50 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 0.50 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 0.50 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 0.50 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 0.50 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 0.50 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 0.50 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 0.50 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 0.50 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 0.50 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 0.50 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 0.50 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 0.50 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 0.50 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 0.50 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 0.50 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 0.50 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 0.50 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 0.50 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 0.50 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 0.50 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 0.50 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 0.50 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 0.50 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 0.50 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 0.50 [6DE..6E4) i bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 0.50 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 0.50 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 0.50 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 0.50 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 0.50 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 0.50 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 0.50 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 0.50 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 0.50 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 0.50 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 0.50 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 0.50 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 0.50 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 0.50 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 0.50 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 0.50 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 0.50 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 0.50 [000..788)-> BB238 ( cond ) i bwd bwd-target BB237 [0348] 1 BB236 0.50 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 0.50 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 0.50 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 0.50 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 0.50 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 0.50 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 0.50 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 0.50 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 1 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 0.50 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 0.50 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB44 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB48 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB78 [000..30D) -> BB104 (cond), preds={BB73,BB77} succs={BB79,BB104} ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB104 (cond), preds={BB78} succs={BB80,BB104} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB82 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB83 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB88 [35A..35E) -> BB104 (cond), preds={BB86,BB87} succs={BB89,BB104} ***** BB88 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB89 [35E..362) -> BB104 (cond), preds={BB88,BB103} succs={BB90,BB104} ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB101 (cond), preds={BB89} succs={BB91,BB101} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB94 [000..000) -> BB96 (cond), preds={BB92,BB93} succs={BB95,BB96} ***** BB94 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB95 [000..000) -> BB97 (always), preds={BB94} succs={BB97} ***** BB95 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB95 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB95 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB95 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ------------ BB96 [000..000) (throw), preds={BB94} succs={} ***** BB96 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB97 [391..392) -> BB99 (cond), preds={BB95} succs={BB98,BB99} ***** BB97 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB97 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB98 [391..392) -> BB100 (always), preds={BB97} succs={BB100} ***** BB98 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB99 [391..392), preds={BB97} succs={BB100} ***** BB99 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB99 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB100 [???..???), preds={BB98,BB99} succs={BB101} ***** BB100 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB101 [39A..3AE) -> BB103 (cond), preds={BB90,BB100} succs={BB102,BB103} ***** BB101 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB101 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB102 [3AE..3BB), preds={BB101} succs={BB103} ***** BB102 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB102 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB103 [3BB..3C8) -> BB89 (cond), preds={BB101,BB102} succs={BB104,BB89} ***** BB103 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ***** BB103 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB104 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB103} succs={BB105,BB112} ***** BB104 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB105 [3D0..3D4) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB106 [3D4..3DC) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB107 [3DC..3E8) -> BB112 (cond), preds={BB106} succs={BB108,BB112} ***** BB107 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB107 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB108 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB109 [3DC..3DD) -> BB111 (cond), preds={BB108} succs={BB110,BB111} ***** BB109 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB110 [3DC..3DD) -> BB112 (always), preds={BB109} succs={BB112} ***** BB110 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB110 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB110 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB111 [3DC..3DD), preds={BB108,BB109} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB104,BB105,BB106,BB107,BB110,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB119 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB120 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB120 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB219 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Find loops *************** In optFindLoops() *************** In optMarkLoopHeads() 10 loop heads marked *************** In optFindNaturalLoops() FindLoop: checking head:BB01 top:BB02 bottom:BB01 BB01->BB02 is not a backedge FindLoop: checking head:BB02 top:BB03 bottom:BB02 BB02->BB03 is not a backedge FindLoop: checking head:BB03 top:BB04 bottom:BB02 BB02->BB04 is not a backedge FindLoop: checking head:BB04 top:BB05 bottom:BB01 BB01->BB05 is not a backedge FindLoop: checking head:BB05 top:BB06 bottom:BB03 BB03->BB06 is not a backedge FindLoop: checking head:BB05 top:BB06 bottom:BB04 BB04->BB06 is not a backedge FindLoop: checking head:BB05 top:BB06 bottom:BB05 BB05->BB06 is not a backedge FindLoop: checking head:BB06 top:BB07 bottom:BB06 BB06->BB07 is not a backedge FindLoop: checking head:BB06 top:BB07 bottom:BB62 (find cycle) found cycle New loop epoch 1 Recorded loop L00, from BB07 to BB62 (Head=BB06, Entry=BB07, ExitCnt=3) FindLoop: checking head:BB07 top:BB08 bottom:BB49 (find cycle) found cycle L01: couldn't find init/test/incr; not LPFLG_ITER loop Recorded loop L01, from BB08 to BB49 (Head=BB07, Entry=BB47, ExitCnt=3) FindLoop: checking head:BB08 top:BB09 bottom:BB08 BB08->BB09 is not a backedge FindLoop: checking head:BB09 top:BB10 bottom:BB09 BB09->BB10 is not a backedge FindLoop: checking head:BB10 top:BB11 bottom:BB10 BB10->BB11 is not a backedge FindLoop: checking head:BB11 top:BB12 bottom:BB11 BB11->BB12 is not a backedge FindLoop: checking head:BB12 top:BB13 bottom:BB08 BB08->BB13 is not a backedge FindLoop: checking head:BB13 top:BB14 bottom:BB13 BB13->BB14 is not a backedge FindLoop: checking head:BB14 top:BB15 bottom:BB14 BB14->BB15 is not a backedge FindLoop: checking head:BB15 top:BB16 bottom:BB15 BB15->BB16 is not a backedge FindLoop: checking head:BB16 top:BB17 bottom:BB09 BB09->BB17 is not a backedge FindLoop: checking head:BB17 top:BB18 bottom:BB10 BB10->BB18 is not a backedge FindLoop: checking head:BB18 top:BB19 bottom:BB18 BB18->BB19 is not a backedge FindLoop: checking head:BB19 top:BB20 bottom:BB18 BB18->BB20 is not a backedge FindLoop: checking head:BB19 top:BB20 bottom:BB19 BB19->BB20 is not a backedge FindLoop: checking head:BB20 top:BB21 bottom:BB10 BB10->BB21 is not a backedge FindLoop: checking head:BB21 top:BB22 bottom:BB21 BB21->BB22 is not a backedge FindLoop: checking head:BB22 top:BB23 bottom:BB10 BB10->BB23 is not a backedge FindLoop: checking head:BB23 top:BB24 bottom:BB23 BB23->BB24 is not a backedge FindLoop: checking head:BB24 top:BB25 bottom:BB24 BB24->BB25 is not a backedge FindLoop: checking head:BB25 top:BB26 bottom:BB25 BB25->BB26 is not a backedge FindLoop: checking head:BB26 top:BB27 bottom:BB26 BB26->BB27 is not a backedge FindLoop: checking head:BB27 top:BB28 bottom:BB26 BB26->BB28 is not a backedge FindLoop: checking head:BB28 top:BB29 bottom:BB25 BB25->BB29 is not a backedge FindLoop: checking head:BB28 top:BB29 bottom:BB28 BB28->BB29 is not a backedge FindLoop: checking head:BB29 top:BB30 bottom:BB09 BB09->BB30 is not a backedge FindLoop: checking head:BB30 top:BB31 bottom:BB09 BB09->BB31 is not a backedge FindLoop: checking head:BB30 top:BB31 bottom:BB33 can't find entry FindLoop: checking head:BB31 top:BB32 bottom:BB31 BB31->BB32 is not a backedge FindLoop: checking head:BB32 top:BB33 bottom:BB32 BB32->BB33 is not a backedge FindLoop: checking head:BB33 top:BB34 bottom:BB33 BB33->BB34 is not a backedge FindLoop: checking head:BB34 top:BB35 bottom:BB13 BB13->BB35 is not a backedge FindLoop: checking head:BB35 top:BB36 bottom:BB35 BB35->BB36 is not a backedge FindLoop: checking head:BB36 top:BB37 bottom:BB36 BB36->BB37 is not a backedge FindLoop: checking head:BB37 top:BB38 bottom:BB11 BB11->BB38 is not a backedge FindLoop: checking head:BB37 top:BB38 bottom:BB14 BB14->BB38 is not a backedge FindLoop: checking head:BB38 top:BB39 bottom:BB38 BB38->BB39 is not a backedge FindLoop: checking head:BB39 top:BB40 bottom:BB38 BB38->BB40 is not a backedge FindLoop: checking head:BB39 top:BB40 bottom:BB39 BB39->BB40 is not a backedge FindLoop: checking head:BB40 top:BB41 bottom:BB40 BB40->BB41 is not a backedge FindLoop: checking head:BB41 top:BB42 bottom:BB41 BB41->BB42 is not a backedge FindLoop: checking head:BB42 top:BB43 bottom:BB41 BB41->BB43 is not a backedge FindLoop: checking head:BB42 top:BB43 bottom:BB42 BB42->BB43 is not a backedge FindLoop: checking head:BB43 top:BB44 bottom:BB39 BB39->BB44 is not a backedge FindLoop: checking head:BB43 top:BB44 bottom:BB43 BB43->BB44 is not a backedge FindLoop: checking head:BB43 top:BB44 bottom:BB45 (find cycle) multiple entry:BB44 not single entry cycle FindLoop: checking head:BB44 top:BB45 bottom:BB44 BB44->BB45 is not a backedge FindLoop: checking head:BB45 top:BB46 bottom:BB44 BB44->BB46 is not a backedge FindLoop: checking head:BB45 top:BB46 bottom:BB45 BB45->BB46 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB07 BB07->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB09 BB09->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB10 BB10->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB12 BB12->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB15 BB15->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB16 BB16->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB17 BB17->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB20 BB20->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB21 BB21->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB22 BB22->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB23 BB23->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB24 BB24->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB27 BB27->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB29 BB29->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB30 BB30->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB31 BB31->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB32 BB32->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB34 BB34->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB35 BB35->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB36 BB36->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB37 BB37->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB40 BB40->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB42 BB42->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB43 BB43->BB47 is not a backedge FindLoop: checking head:BB46 top:BB47 bottom:BB46 BB46->BB47 is not a backedge FindLoop: checking head:BB47 top:BB48 bottom:BB47 BB47->BB48 is not a backedge FindLoop: checking head:BB48 top:BB49 bottom:BB48 BB48->BB49 is not a backedge FindLoop: checking head:BB49 top:BB50 bottom:BB47 BB47->BB50 is not a backedge FindLoop: checking head:BB49 top:BB50 bottom:BB48 BB48->BB50 is not a backedge FindLoop: checking head:BB49 top:BB50 bottom:BB49 BB49->BB50 is not a backedge FindLoop: checking head:BB50 top:BB51 bottom:BB50 BB50->BB51 is not a backedge FindLoop: checking head:BB51 top:BB52 bottom:BB50 BB50->BB52 is not a backedge FindLoop: checking head:BB51 top:BB52 bottom:BB51 BB51->BB52 is not a backedge FindLoop: checking head:BB52 top:BB53 bottom:BB52 BB52->BB53 is not a backedge FindLoop: checking head:BB53 top:BB54 bottom:BB53 BB53->BB54 is not a backedge FindLoop: checking head:BB54 top:BB55 bottom:BB53 BB53->BB55 is not a backedge FindLoop: checking head:BB55 top:BB56 bottom:BB52 BB52->BB56 is not a backedge FindLoop: checking head:BB55 top:BB56 bottom:BB54 BB54->BB56 is not a backedge FindLoop: checking head:BB55 top:BB56 bottom:BB55 BB55->BB56 is not a backedge FindLoop: checking head:BB56 top:BB57 bottom:BB56 BB56->BB57 is not a backedge FindLoop: checking head:BB57 top:BB58 bottom:BB57 BB57->BB58 is not a backedge FindLoop: checking head:BB58 top:BB59 bottom:BB57 BB57->BB59 is not a backedge FindLoop: checking head:BB59 top:BB60 bottom:BB58 BB58->BB60 is not a backedge FindLoop: checking head:BB59 top:BB60 bottom:BB59 BB59->BB60 is not a backedge FindLoop: checking head:BB60 top:BB61 bottom:BB60 BB60->BB61 is not a backedge FindLoop: checking head:BB61 top:BB62 bottom:BB61 BB61->BB62 is not a backedge FindLoop: checking head:BB62 top:BB63 bottom:BB56 BB56->BB63 is not a backedge FindLoop: checking head:BB63 top:BB64 bottom:BB63 BB63->BB64 is not a backedge FindLoop: checking head:BB64 top:BB65 bottom:BB63 BB63->BB65 is not a backedge FindLoop: checking head:BB64 top:BB65 bottom:BB64 BB64->BB65 is not a backedge FindLoop: checking head:BB65 top:BB66 bottom:BB60 BB60->BB66 is not a backedge FindLoop: checking head:BB65 top:BB66 bottom:BB61 BB61->BB66 is not a backedge FindLoop: checking head:BB65 top:BB66 bottom:BB65 BB65->BB66 is not a backedge FindLoop: checking head:BB66 top:BB67 bottom:BB66 BB66->BB67 is not a backedge FindLoop: checking head:BB67 top:BB68 bottom:BB66 BB66->BB68 is not a backedge FindLoop: checking head:BB68 top:BB69 bottom:BB67 BB67->BB69 is not a backedge FindLoop: checking head:BB68 top:BB69 bottom:BB68 BB68->BB69 is not a backedge FindLoop: checking head:BB69 top:BB70 bottom:BB69 BB69->BB70 is not a backedge FindLoop: checking head:BB70 top:BB71 bottom:BB69 BB69->BB71 is not a backedge FindLoop: checking head:BB71 top:BB72 bottom:BB70 BB70->BB72 is not a backedge FindLoop: checking head:BB71 top:BB72 bottom:BB71 BB71->BB72 is not a backedge FindLoop: checking head:BB72 top:BB73 bottom:BB72 BB72->BB73 is not a backedge FindLoop: checking head:BB73 top:BB74 bottom:BB72 BB72->BB74 is not a backedge FindLoop: checking head:BB74 top:BB75 bottom:BB74 BB74->BB75 is not a backedge FindLoop: checking head:BB75 top:BB76 bottom:BB74 BB74->BB76 is not a backedge FindLoop: checking head:BB76 top:BB77 bottom:BB75 BB75->BB77 is not a backedge FindLoop: checking head:BB76 top:BB77 bottom:BB76 BB76->BB77 is not a backedge FindLoop: checking head:BB77 top:BB78 bottom:BB73 BB73->BB78 is not a backedge FindLoop: checking head:BB77 top:BB78 bottom:BB77 BB77->BB78 is not a backedge FindLoop: checking head:BB78 top:BB79 bottom:BB78 BB78->BB79 is not a backedge FindLoop: checking head:BB79 top:BB80 bottom:BB79 BB79->BB80 is not a backedge FindLoop: checking head:BB80 top:BB81 bottom:BB80 BB80->BB81 is not a backedge FindLoop: checking head:BB81 top:BB82 bottom:BB80 BB80->BB82 is not a backedge FindLoop: checking head:BB81 top:BB82 bottom:BB81 BB81->BB82 is not a backedge FindLoop: checking head:BB82 top:BB83 bottom:BB82 BB82->BB83 is not a backedge FindLoop: checking head:BB83 top:BB84 bottom:BB82 BB82->BB84 is not a backedge FindLoop: checking head:BB84 top:BB85 bottom:BB83 BB83->BB85 is not a backedge FindLoop: checking head:BB84 top:BB85 bottom:BB84 BB84->BB85 is not a backedge FindLoop: checking head:BB85 top:BB86 bottom:BB85 BB85->BB86 is not a backedge FindLoop: checking head:BB86 top:BB87 bottom:BB85 BB85->BB87 is not a backedge FindLoop: checking head:BB87 top:BB88 bottom:BB86 BB86->BB88 is not a backedge FindLoop: checking head:BB87 top:BB88 bottom:BB87 BB87->BB88 is not a backedge FindLoop: checking head:BB88 top:BB89 bottom:BB88 BB88->BB89 is not a backedge FindLoop: checking head:BB88 top:BB89 bottom:BB103 (find cycle) found cycle Relocated block [BB96..BB96] inserted after BB110 Removing unconditional jump to next block (BB95 -> BB97) (converted BB95 to fall-through) Moving stmts from BB95 to BB97 L02: couldn't find init/test/incr; not LPFLG_ITER loop Recorded loop L02, from BB89 to BB103 (Head=BB88, Entry=BB89, ExitCnt=3) FindLoop: checking head:BB89 top:BB90 bottom:BB89 BB89->BB90 is not a backedge FindLoop: checking head:BB90 top:BB91 bottom:BB90 BB90->BB91 is not a backedge FindLoop: checking head:BB91 top:BB92 bottom:BB91 BB91->BB92 is not a backedge FindLoop: checking head:BB92 top:BB93 bottom:BB91 BB91->BB93 is not a backedge FindLoop: checking head:BB93 top:BB94 bottom:BB92 BB92->BB94 is not a backedge FindLoop: checking head:BB93 top:BB94 bottom:BB93 BB93->BB94 is not a backedge FindLoop: checking head:BB94 top:BB95 bottom:BB94 BB94->BB95 is not a backedge FindLoop: checking head:BB95 top:BB97 bottom:BB95 BB95->BB97 is not a backedge FindLoop: checking head:BB97 top:BB98 bottom:BB97 BB97->BB98 is not a backedge FindLoop: checking head:BB98 top:BB99 bottom:BB97 BB97->BB99 is not a backedge FindLoop: checking head:BB99 top:BB100 bottom:BB98 BB98->BB100 is not a backedge FindLoop: checking head:BB99 top:BB100 bottom:BB99 BB99->BB100 is not a backedge FindLoop: checking head:BB100 top:BB101 bottom:BB90 BB90->BB101 is not a backedge FindLoop: checking head:BB100 top:BB101 bottom:BB100 BB100->BB101 is not a backedge FindLoop: checking head:BB101 top:BB102 bottom:BB101 BB101->BB102 is not a backedge FindLoop: checking head:BB102 top:BB103 bottom:BB101 BB101->BB103 is not a backedge FindLoop: checking head:BB102 top:BB103 bottom:BB102 BB102->BB103 is not a backedge FindLoop: checking head:BB103 top:BB104 bottom:BB78 BB78->BB104 is not a backedge FindLoop: checking head:BB103 top:BB104 bottom:BB79 BB79->BB104 is not a backedge FindLoop: checking head:BB103 top:BB104 bottom:BB88 BB88->BB104 is not a backedge FindLoop: checking head:BB103 top:BB104 bottom:BB89 BB89->BB104 is not a backedge FindLoop: checking head:BB103 top:BB104 bottom:BB103 BB103->BB104 is not a backedge FindLoop: checking head:BB104 top:BB105 bottom:BB104 BB104->BB105 is not a backedge FindLoop: checking head:BB105 top:BB106 bottom:BB105 BB105->BB106 is not a backedge FindLoop: checking head:BB106 top:BB107 bottom:BB106 BB106->BB107 is not a backedge FindLoop: checking head:BB107 top:BB108 bottom:BB107 BB107->BB108 is not a backedge FindLoop: checking head:BB108 top:BB109 bottom:BB108 BB108->BB109 is not a backedge FindLoop: checking head:BB109 top:BB110 bottom:BB109 BB109->BB110 is not a backedge FindLoop: checking head:BB96 top:BB111 bottom:BB108 BB108->BB111 is not a backedge FindLoop: checking head:BB96 top:BB111 bottom:BB109 BB109->BB111 is not a backedge FindLoop: checking head:BB111 top:BB112 bottom:BB104 BB104->BB112 is not a backedge FindLoop: checking head:BB111 top:BB112 bottom:BB105 BB105->BB112 is not a backedge FindLoop: checking head:BB111 top:BB112 bottom:BB106 BB106->BB112 is not a backedge FindLoop: checking head:BB111 top:BB112 bottom:BB107 BB107->BB112 is not a backedge FindLoop: checking head:BB111 top:BB112 bottom:BB110 BB110->BB112 is not a backedge FindLoop: checking head:BB111 top:BB112 bottom:BB111 BB111->BB112 is not a backedge FindLoop: checking head:BB112 top:BB113 bottom:BB247 (find cycle) found cycle L03: couldn't find init/test/incr; not LPFLG_ITER loop Recorded loop L03, from BB113 to BB247 (Head=BB112, Entry=BB245, ExitCnt=3) FindLoop: checking head:BB113 top:BB114 bottom:BB113 BB113->BB114 is not a backedge FindLoop: checking head:BB114 top:BB115 bottom:BB114 BB114->BB115 is not a backedge FindLoop: checking head:BB115 top:BB116 bottom:BB115 BB115->BB116 is not a backedge FindLoop: checking head:BB116 top:BB117 bottom:BB116 BB116->BB117 is not a backedge FindLoop: checking head:BB117 top:BB118 bottom:BB135 can't find entry FindLoop: checking head:BB118 top:BB119 bottom:BB118 BB118->BB119 is not a backedge FindLoop: checking head:BB119 top:BB120 bottom:BB118 BB118->BB120 is not a backedge FindLoop: checking head:BB120 top:BB121 bottom:BB119 BB119->BB121 is not a backedge FindLoop: checking head:BB120 top:BB121 bottom:BB120 BB120->BB121 is not a backedge FindLoop: checking head:BB121 top:BB122 bottom:BB121 BB121->BB122 is not a backedge FindLoop: checking head:BB122 top:BB123 bottom:BB121 BB121->BB123 is not a backedge FindLoop: checking head:BB123 top:BB124 bottom:BB122 BB122->BB124 is not a backedge FindLoop: checking head:BB123 top:BB124 bottom:BB123 BB123->BB124 is not a backedge FindLoop: checking head:BB124 top:BB125 bottom:BB124 BB124->BB125 is not a backedge FindLoop: checking head:BB125 top:BB126 bottom:BB125 BB125->BB126 is not a backedge FindLoop: checking head:BB126 top:BB127 bottom:BB126 BB126->BB127 is not a backedge FindLoop: checking head:BB127 top:BB128 bottom:BB127 BB127->BB128 is not a backedge FindLoop: checking head:BB128 top:BB129 bottom:BB128 BB128->BB129 is not a backedge FindLoop: checking head:BB129 top:BB130 bottom:BB129 BB129->BB130 is not a backedge FindLoop: checking head:BB130 top:BB131 bottom:BB130 BB130->BB131 is not a backedge FindLoop: checking head:BB131 top:BB132 bottom:BB129 BB129->BB132 is not a backedge FindLoop: checking head:BB131 top:BB132 bottom:BB130 BB130->BB132 is not a backedge FindLoop: checking head:BB132 top:BB133 bottom:BB128 BB128->BB133 is not a backedge FindLoop: checking head:BB132 top:BB133 bottom:BB131 BB131->BB133 is not a backedge FindLoop: checking head:BB132 top:BB133 bottom:BB132 BB132->BB133 is not a backedge FindLoop: checking head:BB133 top:BB134 bottom:BB124 BB124->BB134 is not a backedge FindLoop: checking head:BB133 top:BB134 bottom:BB125 BB125->BB134 is not a backedge FindLoop: checking head:BB133 top:BB134 bottom:BB126 BB126->BB134 is not a backedge FindLoop: checking head:BB133 top:BB134 bottom:BB127 BB127->BB134 is not a backedge FindLoop: checking head:BB133 top:BB134 bottom:BB133 BB133->BB134 is not a backedge FindLoop: checking head:BB134 top:BB135 bottom:BB114 BB114->BB135 is not a backedge FindLoop: checking head:BB134 top:BB135 bottom:BB115 BB115->BB135 is not a backedge FindLoop: checking head:BB134 top:BB135 bottom:BB116 BB116->BB135 is not a backedge FindLoop: checking head:BB134 top:BB135 bottom:BB134 BB134->BB135 is not a backedge FindLoop: checking head:BB135 top:BB136 bottom:BB113 BB113->BB136 is not a backedge FindLoop: checking head:BB135 top:BB136 bottom:BB117 BB117->BB136 is not a backedge FindLoop: checking head:BB135 top:BB136 bottom:BB135 BB135->BB136 is not a backedge FindLoop: checking head:BB136 top:BB137 bottom:BB136 BB136->BB137 is not a backedge FindLoop: checking head:BB137 top:BB138 bottom:BB137 BB137->BB138 is not a backedge FindLoop: checking head:BB138 top:BB139 bottom:BB138 BB138->BB139 is not a backedge FindLoop: checking head:BB139 top:BB140 bottom:BB139 BB139->BB140 is not a backedge FindLoop: checking head:BB140 top:BB141 bottom:BB136 BB136->BB141 is not a backedge FindLoop: checking head:BB141 top:BB142 bottom:BB141 BB141->BB142 is not a backedge FindLoop: checking head:BB142 top:BB143 bottom:BB142 BB142->BB143 is not a backedge FindLoop: checking head:BB143 top:BB144 bottom:BB143 BB143->BB144 is not a backedge FindLoop: checking head:BB144 top:BB145 bottom:BB137 BB137->BB145 is not a backedge FindLoop: checking head:BB144 top:BB145 bottom:BB138 BB138->BB145 is not a backedge FindLoop: checking head:BB145 top:BB146 bottom:BB145 BB145->BB146 is not a backedge FindLoop: checking head:BB146 top:BB147 bottom:BB146 BB146->BB147 is not a backedge FindLoop: checking head:BB147 top:BB148 bottom:BB146 BB146->BB148 is not a backedge FindLoop: checking head:BB148 top:BB149 bottom:BB147 BB147->BB149 is not a backedge FindLoop: checking head:BB148 top:BB149 bottom:BB148 BB148->BB149 is not a backedge FindLoop: checking head:BB149 top:BB150 bottom:BB145 BB145->BB150 is not a backedge FindLoop: checking head:BB150 top:BB151 bottom:BB150 BB150->BB151 is not a backedge FindLoop: checking head:BB151 top:BB152 bottom:BB151 BB151->BB152 is not a backedge FindLoop: checking head:BB152 top:BB153 bottom:BB151 BB151->BB153 is not a backedge FindLoop: checking head:BB153 top:BB154 bottom:BB150 BB150->BB154 is not a backedge FindLoop: checking head:BB154 top:BB155 bottom:BB152 BB152->BB155 is not a backedge FindLoop: checking head:BB154 top:BB155 bottom:BB153 BB153->BB155 is not a backedge FindLoop: checking head:BB154 top:BB155 bottom:BB154 BB154->BB155 is not a backedge FindLoop: checking head:BB155 top:BB156 bottom:BB149 BB149->BB156 is not a backedge FindLoop: checking head:BB155 top:BB156 bottom:BB155 BB155->BB156 is not a backedge FindLoop: checking head:BB156 top:BB157 bottom:BB156 BB156->BB157 is not a backedge FindLoop: checking head:BB157 top:BB158 bottom:BB157 BB157->BB158 is not a backedge FindLoop: checking head:BB158 top:BB159 bottom:BB157 BB157->BB159 is not a backedge FindLoop: checking head:BB159 top:BB160 bottom:BB158 BB158->BB160 is not a backedge FindLoop: checking head:BB159 top:BB160 bottom:BB159 BB159->BB160 is not a backedge FindLoop: checking head:BB160 top:BB161 bottom:BB160 BB160->BB161 is not a backedge FindLoop: checking head:BB161 top:BB162 bottom:BB161 BB161->BB162 is not a backedge FindLoop: checking head:BB162 top:BB163 bottom:BB162 BB162->BB163 is not a backedge FindLoop: checking head:BB163 top:BB164 bottom:BB163 BB163->BB164 is not a backedge FindLoop: checking head:BB164 top:BB165 bottom:BB164 BB164->BB165 is not a backedge FindLoop: checking head:BB165 top:BB166 bottom:BB165 BB165->BB166 is not a backedge FindLoop: checking head:BB166 top:BB167 bottom:BB166 BB166->BB167 is not a backedge FindLoop: checking head:BB167 top:BB168 bottom:BB165 BB165->BB168 is not a backedge FindLoop: checking head:BB167 top:BB168 bottom:BB166 BB166->BB168 is not a backedge FindLoop: checking head:BB168 top:BB169 bottom:BB164 BB164->BB169 is not a backedge FindLoop: checking head:BB168 top:BB169 bottom:BB167 BB167->BB169 is not a backedge FindLoop: checking head:BB168 top:BB169 bottom:BB168 BB168->BB169 is not a backedge FindLoop: checking head:BB169 top:BB170 bottom:BB156 BB156->BB170 is not a backedge FindLoop: checking head:BB169 top:BB170 bottom:BB160 BB160->BB170 is not a backedge FindLoop: checking head:BB169 top:BB170 bottom:BB161 BB161->BB170 is not a backedge FindLoop: checking head:BB169 top:BB170 bottom:BB162 BB162->BB170 is not a backedge FindLoop: checking head:BB169 top:BB170 bottom:BB163 BB163->BB170 is not a backedge FindLoop: checking head:BB169 top:BB170 bottom:BB169 BB169->BB170 is not a backedge FindLoop: checking head:BB170 top:BB171 bottom:BB138 BB138->BB171 is not a backedge FindLoop: checking head:BB171 top:BB172 bottom:BB171 BB171->BB172 is not a backedge FindLoop: checking head:BB172 top:BB173 bottom:BB172 BB172->BB173 is not a backedge FindLoop: checking head:BB173 top:BB174 bottom:BB173 BB173->BB174 is not a backedge FindLoop: checking head:BB174 top:BB175 bottom:BB172 BB172->BB175 is not a backedge FindLoop: checking head:BB174 top:BB175 bottom:BB174 BB174->BB175 is not a backedge FindLoop: checking head:BB175 top:BB176 bottom:BB175 BB175->BB176 is not a backedge FindLoop: checking head:BB176 top:BB177 bottom:BB176 BB176->BB177 is not a backedge FindLoop: checking head:BB177 top:BB178 bottom:BB177 BB177->BB178 is not a backedge FindLoop: checking head:BB178 top:BB179 bottom:BB176 BB176->BB179 is not a backedge FindLoop: checking head:BB178 top:BB179 bottom:BB177 BB177->BB179 is not a backedge FindLoop: checking head:BB179 top:BB180 bottom:BB175 BB175->BB180 is not a backedge FindLoop: checking head:BB179 top:BB180 bottom:BB178 BB178->BB180 is not a backedge FindLoop: checking head:BB179 top:BB180 bottom:BB179 BB179->BB180 is not a backedge FindLoop: checking head:BB180 top:BB181 bottom:BB144 BB144->BB181 is not a backedge FindLoop: checking head:BB181 top:BB182 bottom:BB181 BB181->BB182 is not a backedge FindLoop: checking head:BB182 top:BB183 bottom:BB182 BB182->BB183 is not a backedge FindLoop: checking head:BB183 top:BB184 bottom:BB183 BB183->BB184 is not a backedge FindLoop: checking head:BB184 top:BB185 bottom:BB182 BB182->BB185 is not a backedge FindLoop: checking head:BB184 top:BB185 bottom:BB183 BB183->BB185 is not a backedge FindLoop: checking head:BB185 top:BB186 bottom:BB137 BB137->BB186 is not a backedge FindLoop: checking head:BB186 top:BB187 bottom:BB186 BB186->BB187 is not a backedge FindLoop: checking head:BB187 top:BB188 bottom:BB187 BB187->BB188 is not a backedge FindLoop: checking head:BB188 top:BB189 bottom:BB188 BB188->BB189 is not a backedge FindLoop: checking head:BB189 top:BB190 bottom:BB187 BB187->BB190 is not a backedge FindLoop: checking head:BB189 top:BB190 bottom:BB188 BB188->BB190 is not a backedge FindLoop: checking head:BB190 top:BB191 bottom:BB196 can't find entry FindLoop: checking head:BB191 top:BB192 bottom:BB191 BB191->BB192 is not a backedge FindLoop: checking head:BB192 top:BB193 bottom:BB191 BB191->BB193 is not a backedge FindLoop: checking head:BB193 top:BB194 bottom:BB137 BB137->BB194 is not a backedge FindLoop: checking head:BB193 top:BB194 bottom:BB192 BB192->BB194 is not a backedge FindLoop: checking head:BB193 top:BB194 bottom:BB193 BB193->BB194 is not a backedge FindLoop: checking head:BB194 top:BB195 bottom:BB194 BB194->BB195 is not a backedge FindLoop: checking head:BB195 top:BB196 bottom:BB195 BB195->BB196 is not a backedge FindLoop: checking head:BB196 top:BB197 bottom:BB194 BB194->BB197 is not a backedge FindLoop: checking head:BB196 top:BB197 bottom:BB195 BB195->BB197 is not a backedge FindLoop: checking head:BB196 top:BB197 bottom:BB196 BB196->BB197 is not a backedge FindLoop: checking head:BB197 top:BB198 bottom:BB197 BB197->BB198 is not a backedge FindLoop: checking head:BB198 top:BB199 bottom:BB198 BB198->BB199 is not a backedge FindLoop: checking head:BB199 top:BB200 bottom:BB141 BB141->BB200 is not a backedge FindLoop: checking head:BB200 top:BB201 bottom:BB200 BB200->BB201 is not a backedge FindLoop: checking head:BB201 top:BB202 bottom:BB201 BB201->BB202 is not a backedge FindLoop: checking head:BB202 top:BB203 bottom:BB202 BB202->BB203 is not a backedge FindLoop: checking head:BB203 top:BB204 bottom:BB202 BB202->BB204 is not a backedge FindLoop: checking head:BB204 top:BB205 bottom:BB139 BB139->BB205 is not a backedge FindLoop: checking head:BB204 top:BB205 bottom:BB142 BB142->BB205 is not a backedge FindLoop: checking head:BB205 top:BB206 bottom:BB205 BB205->BB206 is not a backedge FindLoop: checking head:BB206 top:BB207 bottom:BB206 BB206->BB207 is not a backedge FindLoop: checking head:BB207 top:BB208 bottom:BB206 BB206->BB208 is not a backedge FindLoop: checking head:BB207 top:BB208 bottom:BB207 BB207->BB208 is not a backedge FindLoop: checking head:BB208 top:BB209 bottom:BB208 BB208->BB209 is not a backedge FindLoop: checking head:BB209 top:BB210 bottom:BB209 BB209->BB210 is not a backedge FindLoop: checking head:BB210 top:BB211 bottom:BB210 BB210->BB211 is not a backedge FindLoop: checking head:BB211 top:BB212 bottom:BB208 BB208->BB212 is not a backedge FindLoop: checking head:BB211 top:BB212 bottom:BB209 BB209->BB212 is not a backedge FindLoop: checking head:BB211 top:BB212 bottom:BB210 BB210->BB212 is not a backedge FindLoop: checking head:BB212 top:BB213 bottom:BB212 BB212->BB213 is not a backedge FindLoop: checking head:BB213 top:BB214 bottom:BB213 BB213->BB214 is not a backedge FindLoop: checking head:BB214 top:BB215 bottom:BB212 BB212->BB215 is not a backedge FindLoop: checking head:BB214 top:BB215 bottom:BB213 BB213->BB215 is not a backedge FindLoop: checking head:BB214 top:BB215 bottom:BB214 BB214->BB215 is not a backedge FindLoop: checking head:BB215 top:BB216 bottom:BB215 BB215->BB216 is not a backedge FindLoop: checking head:BB216 top:BB217 bottom:BB215 BB215->BB217 is not a backedge FindLoop: checking head:BB217 top:BB218 bottom:BB207 BB207->BB218 is not a backedge FindLoop: checking head:BB217 top:BB218 bottom:BB220 can't find entry FindLoop: checking head:BB218 top:BB219 bottom:BB211 BB211->BB219 is not a backedge FindLoop: checking head:BB218 top:BB219 bottom:BB214 BB214->BB219 is not a backedge FindLoop: checking head:BB218 top:BB219 bottom:BB218 BB218->BB219 is not a backedge FindLoop: checking head:BB219 top:BB220 bottom:BB219 BB219->BB220 is not a backedge FindLoop: checking head:BB220 top:BB221 bottom:BB219 BB219->BB221 is not a backedge FindLoop: checking head:BB220 top:BB221 bottom:BB220 BB220->BB221 is not a backedge FindLoop: checking head:BB221 top:BB222 bottom:BB221 BB221->BB222 is not a backedge FindLoop: checking head:BB222 top:BB223 bottom:BB221 BB221->BB223 is not a backedge FindLoop: checking head:BB222 top:BB223 bottom:BB222 BB222->BB223 is not a backedge FindLoop: checking head:BB223 top:BB224 bottom:BB223 BB223->BB224 is not a backedge FindLoop: checking head:BB224 top:BB225 bottom:BB223 BB223->BB225 is not a backedge FindLoop: checking head:BB225 top:BB226 bottom:BB224 BB224->BB226 is not a backedge FindLoop: checking head:BB225 top:BB226 bottom:BB225 BB225->BB226 is not a backedge FindLoop: checking head:BB226 top:BB227 bottom:BB205 BB205->BB227 is not a backedge FindLoop: checking head:BB227 top:BB228 bottom:BB227 BB227->BB228 is not a backedge FindLoop: checking head:BB228 top:BB229 bottom:BB227 BB227->BB229 is not a backedge FindLoop: checking head:BB229 top:BB230 bottom:BB228 BB228->BB230 is not a backedge FindLoop: checking head:BB229 top:BB230 bottom:BB229 BB229->BB230 is not a backedge FindLoop: checking head:BB230 top:BB231 bottom:BB230 BB230->BB231 is not a backedge FindLoop: checking head:BB231 top:BB232 bottom:BB231 BB231->BB232 is not a backedge FindLoop: checking head:BB232 top:BB233 bottom:BB231 BB231->BB233 is not a backedge FindLoop: checking head:BB232 top:BB233 bottom:BB232 BB232->BB233 is not a backedge FindLoop: checking head:BB233 top:BB234 bottom:BB233 BB233->BB234 is not a backedge FindLoop: checking head:BB234 top:BB235 bottom:BB233 BB233->BB235 is not a backedge FindLoop: checking head:BB235 top:BB236 bottom:BB240 (find cycle) multiple entry:BB239 not single entry cycle FindLoop: checking head:BB236 top:BB237 bottom:BB236 BB236->BB237 is not a backedge FindLoop: checking head:BB237 top:BB238 bottom:BB236 BB236->BB238 is not a backedge FindLoop: checking head:BB238 top:BB239 bottom:BB232 BB232->BB239 is not a backedge FindLoop: checking head:BB238 top:BB239 bottom:BB234 BB234->BB239 is not a backedge FindLoop: checking head:BB238 top:BB239 bottom:BB235 BB235->BB239 is not a backedge FindLoop: checking head:BB238 top:BB239 bottom:BB237 BB237->BB239 is not a backedge FindLoop: checking head:BB238 top:BB239 bottom:BB238 BB238->BB239 is not a backedge FindLoop: checking head:BB239 top:BB240 bottom:BB239 BB239->BB240 is not a backedge FindLoop: checking head:BB240 top:BB241 bottom:BB240 BB240->BB241 is not a backedge FindLoop: checking head:BB241 top:BB242 bottom:BB137 BB137->BB242 is not a backedge FindLoop: checking head:BB241 top:BB242 bottom:BB138 BB138->BB242 is not a backedge FindLoop: checking head:BB241 top:BB242 bottom:BB140 BB140->BB242 is not a backedge FindLoop: checking head:BB241 top:BB242 bottom:BB143 BB143->BB242 is not a backedge FindLoop: checking head:BB242 top:BB243 bottom:BB242 BB242->BB243 is not a backedge FindLoop: checking head:BB243 top:BB244 bottom:BB217 BB217->BB244 is not a backedge FindLoop: checking head:BB243 top:BB244 bottom:BB242 BB242->BB244 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB112 BB112->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB138 BB138->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB170 BB170->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB171 BB171->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB173 BB173->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB174 BB174->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB180 BB180->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB181 BB181->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB184 BB184->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB185 BB185->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB186 BB186->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB189 BB189->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB190 BB190->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB197 BB197->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB198 BB198->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB199 BB199->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB200 BB200->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB201 BB201->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB203 BB203->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB204 BB204->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB216 BB216->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB226 BB226->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB230 BB230->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB239 BB239->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB241 BB241->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB243 BB243->BB245 is not a backedge FindLoop: checking head:BB244 top:BB245 bottom:BB244 BB244->BB245 is not a backedge FindLoop: checking head:BB245 top:BB246 bottom:BB245 BB245->BB246 is not a backedge FindLoop: checking head:BB246 top:BB247 bottom:BB246 BB246->BB247 is not a backedge FindLoop: checking head:BB247 top:BB248 bottom:BB245 BB245->BB248 is not a backedge FindLoop: checking head:BB247 top:BB248 bottom:BB246 BB246->BB248 is not a backedge FindLoop: checking head:BB247 top:BB248 bottom:BB247 BB247->BB248 is not a backedge FindLoop: checking head:BB248 top:BB249 bottom:BB248 BB248->BB249 is not a backedge FindLoop: checking head:BB249 top:BB250 bottom:BB249 BB249->BB250 is not a backedge FindLoop: checking head:BB250 top:BB251 bottom:BB250 BB250->BB251 is not a backedge FindLoop: checking head:BB251 top:BB252 bottom:BB251 BB251->BB252 is not a backedge FindLoop: checking head:BB252 top:BB253 bottom:BB248 BB248->BB253 is not a backedge FindLoop: checking head:BB252 top:BB253 bottom:BB249 BB249->BB253 is not a backedge FindLoop: checking head:BB252 top:BB253 bottom:BB250 BB250->BB253 is not a backedge FindLoop: checking head:BB252 top:BB253 bottom:BB251 BB251->BB253 is not a backedge FindLoop: checking head:BB252 top:BB253 bottom:BB252 BB252->BB253 is not a backedge *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 1 [02D..05B)-> BB47 (always) i Loop gcsafe bwd bwd-target BB08 [0007] 1 BB49 0.50 [05B..061)-> BB13 ( cond ) i Loop bwd bwd-target BB09 [0008] 1 BB08 0.50 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 0.50 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 0.50 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 0.50 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 0.50 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 0.50 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 0.50 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 0.50 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 0.50 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 0.50 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 0.50 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 0.50 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 0.50 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 0.50 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 0.50 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 0.50 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 0.50 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 0.50 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 0.50 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 0.50 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 0.50 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 0.50 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 0.50 [142..150)-> BB47 ( cond ) i Loop bwd bwd-target BB32 [0032] 1 BB31 0.50 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 0.50 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 0.50 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 0.50 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 0.50 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 0.50 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 0.50 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 0.50 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 0.50 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 0.50 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 0.50 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 0.50 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 0.50 [1E4..1F4)-> BB46 ( cond ) i Loop bwd bwd-target BB45 [0045] 1 BB44 0.50 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 0.50 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 0.50 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 0.50 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 1 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 0.50 [233..235) i bwd BB52 [0052] 2 BB50,BB51 1 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 0.50 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 0.50 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 0.50 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 1 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 0.50 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 0.50 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 0.50 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 0.50 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 0.50 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 0.50 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB104 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB104 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB104 ( cond ) i BB89 [0089] 2 BB88,BB103 0.50 [35E..362)-> BB104 ( cond ) i Loop bwd bwd-target BB90 [0090] 1 BB89 0.50 [362..373)-> BB101 ( cond ) i bwd BB91 [0091] 1 BB90 0.50 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 0.50 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 0.50 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 0.50 [000..000)-> BB96 ( cond ) internal bwd BB95 [0227] 1 BB94 0.50 [000..000) i internal hascall gcsafe bwd BB97 [0229] 1 BB95 0.50 [391..392)-> BB99 ( cond ) i gcsafe bwd BB98 [0242] 1 BB97 0.50 [391..392)-> BB100 (always) i gcsafe bwd BB99 [0243] 1 BB97 0.50 [391..392) i gcsafe idxlen nullcheck bwd BB100 [0247] 2 BB98,BB99 0.50 [???..???) internal gcsafe bwd BB101 [0092] 2 BB90,BB100 0.50 [39A..3AE)-> BB103 ( cond ) i bwd BB102 [0093] 1 BB101 0.50 [3AE..3BB) i idxlen bwd BB103 [0094] 2 BB101,BB102 0.50 [3BB..3C8)-> BB89 ( cond ) i bwd BB104 [0096] 5 BB78,BB79,BB88,BB89,BB103 1 [3C8..3D0)-> BB112 ( cond ) i BB105 [0097] 1 BB104 0.50 [3D0..3D4)-> BB112 ( cond ) i BB106 [0098] 1 BB105 0.50 [3D4..3DC)-> BB112 ( cond ) i BB107 [0099] 1 BB106 0.50 [3DC..3E8)-> BB112 ( cond ) i BB108 [0252] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB109 [0253] 1 BB108 0.50 [3DC..3DD)-> BB111 ( cond ) i BB110 [0254] 1 BB109 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB96 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB108,BB109 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB104,BB105,BB106,BB107,BB110,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 0.50 [401..406)-> BB136 ( cond ) i Loop bwd bwd-target BB114 [0102] 1 BB113 0.50 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 0.50 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 0.50 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 0.50 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 0.50 [41A..420)-> BB120 ( cond ) i Loop bwd bwd-target BB119 [0107] 1 BB118 0.50 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 0.50 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 0.50 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 0.50 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 0.50 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 0.50 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 0.50 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 0.50 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 0.50 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 0.50 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 0.50 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 0.50 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 0.50 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 0.50 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 0.50 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 0.50 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 0.50 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 0.50 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 0.50 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 0.50 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 0.50 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 0.50 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 0.50 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 0.50 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 0.50 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 0.50 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 0.50 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 0.50 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 0.50 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 0.50 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 0.50 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 0.50 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 0.50 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 0.50 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 0.50 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 0.50 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 0.50 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 0.50 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 0.50 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 0.50 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 0.50 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 0.50 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 0.50 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 0.50 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 0.50 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 0.50 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 0.50 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 0.50 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 0.50 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 0.50 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 0.50 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 0.50 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 0.50 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 0.50 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 0.50 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 0.50 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 0.50 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 0.50 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 0.50 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 0.50 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 0.50 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 0.50 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 0.50 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 0.50 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 0.50 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 0.50 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 0.50 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 0.50 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 0.50 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 0.50 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 0.50 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 0.50 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 0.50 [000..5CE)-> BB193 ( cond ) i Loop bwd bwd-target BB192 [0315] 1 BB191 0.50 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 0.50 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 0.50 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 0.50 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 0.50 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 0.50 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 0.50 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 0.50 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 0.50 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 0.50 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 0.50 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 0.50 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 0.50 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 0.50 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 0.50 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 0.50 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 0.50 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 0.50 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 0.50 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 0.50 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 0.50 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 0.50 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 0.50 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 0.50 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 0.50 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 0.50 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 0.50 [6DE..6E4) i Loop bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 0.50 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 0.50 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 0.50 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 0.50 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 0.50 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 0.50 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 0.50 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 0.50 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 0.50 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 0.50 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 0.50 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 0.50 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 0.50 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 0.50 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 0.50 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 0.50 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 0.50 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 0.50 [000..788)-> BB238 ( cond ) i Loop bwd bwd-target BB237 [0348] 1 BB236 0.50 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 0.50 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 0.50 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 0.50 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 0.50 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 0.50 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 0.50 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 0.50 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 1 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 0.50 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 0.50 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB97 to BB96 Renumber BB98 to BB97 Renumber BB99 to BB98 Renumber BB100 to BB99 Renumber BB101 to BB100 Renumber BB102 to BB101 Renumber BB103 to BB102 Renumber BB104 to BB103 Renumber BB105 to BB104 Renumber BB106 to BB105 Renumber BB107 to BB106 Renumber BB108 to BB107 Renumber BB109 to BB108 Renumber BB110 to BB109 Renumber BB96 to BB110 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 1 [02D..05B)-> BB47 (always) i Loop gcsafe bwd bwd-target BB08 [0007] 1 BB49 0.50 [05B..061)-> BB13 ( cond ) i Loop bwd bwd-target BB09 [0008] 1 BB08 0.50 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 0.50 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 0.50 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 0.50 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 0.50 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 0.50 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 0.50 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 0.50 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 0.50 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 0.50 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 0.50 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 0.50 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 0.50 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 0.50 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 0.50 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 0.50 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 0.50 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 0.50 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 0.50 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 0.50 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 0.50 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 0.50 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 0.50 [142..150)-> BB47 ( cond ) i Loop bwd bwd-target BB32 [0032] 1 BB31 0.50 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 0.50 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 0.50 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 0.50 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 0.50 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 0.50 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 0.50 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 0.50 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 0.50 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 0.50 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 0.50 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 0.50 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 0.50 [1E4..1F4)-> BB46 ( cond ) i Loop bwd bwd-target BB45 [0045] 1 BB44 0.50 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 0.50 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 0.50 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 0.50 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 1 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 0.50 [233..235) i bwd BB52 [0052] 2 BB50,BB51 1 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 0.50 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 0.50 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 0.50 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 1 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 0.50 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 0.50 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 0.50 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 0.50 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 0.50 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 0.50 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 0.50 [35E..362)-> BB103 ( cond ) i Loop bwd bwd-target BB90 [0090] 1 BB89 0.50 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 0.50 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 0.50 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 0.50 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 0.50 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 0.50 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 0.50 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 0.50 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 0.50 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 0.50 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 0.50 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 0.50 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 0.50 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 0.50 [401..406)-> BB136 ( cond ) i Loop bwd bwd-target BB114 [0102] 1 BB113 0.50 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 0.50 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 0.50 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 0.50 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 0.50 [41A..420)-> BB120 ( cond ) i Loop bwd bwd-target BB119 [0107] 1 BB118 0.50 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 0.50 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 0.50 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 0.50 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 0.50 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 0.50 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 0.50 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 0.50 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 0.50 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 0.50 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 0.50 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 0.50 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 0.50 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 0.50 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 0.50 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 0.50 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 0.50 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 0.50 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 0.50 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 0.50 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 0.50 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 0.50 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 0.50 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 0.50 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 0.50 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 0.50 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 0.50 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 0.50 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 0.50 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 0.50 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 0.50 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 0.50 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 0.50 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 0.50 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 0.50 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 0.50 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 0.50 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 0.50 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 0.50 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 0.50 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 0.50 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 0.50 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 0.50 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 0.50 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 0.50 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 0.50 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 0.50 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 0.50 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 0.50 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 0.50 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 0.50 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 0.50 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 0.50 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 0.50 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 0.50 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 0.50 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 0.50 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 0.50 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 0.50 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 0.50 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 0.50 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 0.50 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 0.50 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 0.50 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 0.50 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 0.50 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 0.50 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 0.50 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 0.50 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 0.50 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 0.50 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 0.50 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 0.50 [000..5CE)-> BB193 ( cond ) i Loop bwd bwd-target BB192 [0315] 1 BB191 0.50 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 0.50 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 0.50 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 0.50 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 0.50 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 0.50 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 0.50 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 0.50 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 0.50 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 0.50 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 0.50 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 0.50 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 0.50 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 0.50 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 0.50 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 0.50 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 0.50 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 0.50 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 0.50 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 0.50 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 0.50 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 0.50 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 0.50 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 0.50 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 0.50 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 0.50 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 0.50 [6DE..6E4) i Loop bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 0.50 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 0.50 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 0.50 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 0.50 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 0.50 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 0.50 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 0.50 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 0.50 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 0.50 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 0.50 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 0.50 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 0.50 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 0.50 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 0.50 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 0.50 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 0.50 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 0.50 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 0.50 [000..788)-> BB238 ( cond ) i Loop bwd bwd-target BB237 [0348] 1 BB236 0.50 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 0.50 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 0.50 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 0.50 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 0.50 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 0.50 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 0.50 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 0.50 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 1 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 0.50 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 0.50 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 4, # of blocks (including unused BB00): 254, bitset array size: 4 (long) Renumbering the basic blocks for fgUpdateChangeFlowGraph *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 1 0 [02D..05B)-> BB47 (always) i Loop gcsafe bwd bwd-target BB08 [0007] 1 BB49 0.50 1 [05B..061)-> BB13 ( cond ) i Loop bwd bwd-target BB09 [0008] 1 BB08 0.50 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 0.50 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 0.50 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 0.50 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 0.50 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 0.50 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 0.50 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 0.50 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 0.50 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 0.50 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 0.50 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 0.50 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 0.50 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 0.50 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 0.50 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 0.50 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 0.50 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 0.50 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 0.50 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 0.50 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 0.50 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 0.50 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 0.50 1 [142..150)-> BB47 ( cond ) i Loop bwd bwd-target BB32 [0032] 1 BB31 0.50 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 0.50 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 0.50 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 0.50 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 0.50 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 0.50 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 0.50 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 0.50 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 0.50 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 0.50 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 0.50 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 0.50 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 0.50 1 [1E4..1F4)-> BB46 ( cond ) i Loop bwd bwd-target BB45 [0045] 1 BB44 0.50 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 0.50 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 1 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 0.50 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 0.50 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 1 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 0.50 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 1 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 0.50 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 0.50 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 0.50 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 1 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 0.50 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 0.50 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 0.50 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 0.50 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 0.50 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 0.50 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 0.50 2 [35E..362)-> BB103 ( cond ) i Loop bwd bwd-target BB90 [0090] 1 BB89 0.50 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 0.50 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 0.50 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 0.50 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 0.50 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 0.50 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 0.50 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 0.50 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 0.50 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 0.50 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 0.50 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 0.50 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 0.50 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 0.50 3 [401..406)-> BB136 ( cond ) i Loop bwd bwd-target BB114 [0102] 1 BB113 0.50 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 0.50 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 0.50 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 0.50 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 0.50 3 [41A..420)-> BB120 ( cond ) i Loop bwd bwd-target BB119 [0107] 1 BB118 0.50 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 0.50 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 0.50 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 0.50 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 0.50 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 0.50 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 0.50 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 0.50 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 0.50 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 0.50 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 0.50 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 0.50 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 0.50 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 0.50 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 0.50 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 0.50 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 0.50 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 0.50 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 0.50 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 0.50 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 0.50 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 0.50 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 0.50 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 0.50 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 0.50 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 0.50 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 0.50 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 0.50 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 0.50 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 0.50 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 0.50 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 0.50 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 0.50 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 0.50 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 0.50 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 0.50 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 0.50 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 0.50 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 0.50 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 0.50 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 0.50 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 0.50 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 0.50 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 0.50 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 0.50 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 0.50 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 0.50 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 0.50 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 0.50 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 0.50 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 0.50 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 0.50 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 0.50 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 0.50 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 0.50 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 0.50 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 0.50 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 0.50 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 0.50 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 0.50 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 0.50 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 0.50 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 0.50 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 0.50 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 0.50 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 0.50 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 0.50 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 0.50 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 0.50 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 0.50 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 0.50 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 0.50 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 0.50 3 [000..5CE)-> BB193 ( cond ) i Loop bwd bwd-target BB192 [0315] 1 BB191 0.50 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 0.50 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 0.50 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 0.50 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 0.50 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 0.50 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 0.50 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 0.50 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 0.50 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 0.50 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 0.50 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 0.50 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 0.50 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 0.50 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 0.50 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 0.50 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 0.50 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 0.50 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 0.50 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 0.50 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 0.50 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 0.50 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 0.50 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 0.50 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 0.50 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 0.50 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 0.50 3 [6DE..6E4) i Loop bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 0.50 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 0.50 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 0.50 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 0.50 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 0.50 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 0.50 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 0.50 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 0.50 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 0.50 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 0.50 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 0.50 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 0.50 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 0.50 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 0.50 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 0.50 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 0.50 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 0.50 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 0.50 3 [000..788)-> BB238 ( cond ) i Loop bwd bwd-target BB237 [0348] 1 BB236 0.50 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 0.50 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 0.50 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 0.50 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 0.50 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 0.50 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 0.50 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 0.50 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 1 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 0.50 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 0.50 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! Setting edge weights for BB01 -> BB05 to [0 .. 3.402823e+38] Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38] Setting edge weights for BB02 -> BB04 to [0 .. 3.402823e+38] Setting edge weights for BB02 -> BB03 to [0 .. 3.402823e+38] Setting edge weights for BB03 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB04 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB05 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB06 -> BB07 to [0 .. 3.402823e+38] Setting edge weights for BB07 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB08 -> BB13 to [0 .. 3.402823e+38] Setting edge weights for BB08 -> BB09 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB31 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB17 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB30 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB10 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB23 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB21 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB18 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB11 to [0 .. 3.402823e+38] Setting edge weights for BB11 -> BB38 to [0 .. 3.402823e+38] Setting edge weights for BB11 -> BB12 to [0 .. 3.402823e+38] Setting edge weights for BB12 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB13 -> BB35 to [0 .. 3.402823e+38] Setting edge weights for BB13 -> BB14 to [0 .. 3.402823e+38] Setting edge weights for BB14 -> BB38 to [0 .. 3.402823e+38] Setting edge weights for BB14 -> BB15 to [0 .. 3.402823e+38] Setting edge weights for BB15 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB15 -> BB16 to [0 .. 3.402823e+38] Setting edge weights for BB16 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB17 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB18 -> BB20 to [0 .. 3.402823e+38] Setting edge weights for BB18 -> BB19 to [0 .. 3.402823e+38] Setting edge weights for BB19 -> BB20 to [0 .. 3.402823e+38] Setting edge weights for BB20 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB21 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB21 -> BB22 to [0 .. 3.402823e+38] Setting edge weights for BB22 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB23 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB23 -> BB24 to [0 .. 3.402823e+38] Setting edge weights for BB24 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB24 -> BB25 to [0 .. 3.402823e+38] Setting edge weights for BB25 -> BB29 to [0 .. 3.402823e+38] Setting edge weights for BB25 -> BB26 to [0 .. 3.402823e+38] Setting edge weights for BB26 -> BB28 to [0 .. 3.402823e+38] Setting edge weights for BB26 -> BB27 to [0 .. 3.402823e+38] Setting edge weights for BB27 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB28 -> BB29 to [0 .. 3.402823e+38] Setting edge weights for BB29 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB30 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB31 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB31 -> BB32 to [0 .. 3.402823e+38] Setting edge weights for BB32 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB32 -> BB33 to [0 .. 3.402823e+38] Setting edge weights for BB33 -> BB31 to [0 .. 3.402823e+38] Setting edge weights for BB33 -> BB34 to [0 .. 3.402823e+38] Setting edge weights for BB34 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB35 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB35 -> BB36 to [0 .. 3.402823e+38] Setting edge weights for BB36 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB36 -> BB37 to [0 .. 3.402823e+38] Setting edge weights for BB37 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB38 -> BB40 to [0 .. 3.402823e+38] Setting edge weights for BB38 -> BB39 to [0 .. 3.402823e+38] Setting edge weights for BB39 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB39 -> BB40 to [0 .. 3.402823e+38] Setting edge weights for BB40 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB40 -> BB41 to [0 .. 3.402823e+38] Setting edge weights for BB41 -> BB43 to [0 .. 3.402823e+38] Setting edge weights for BB41 -> BB42 to [0 .. 3.402823e+38] Setting edge weights for BB42 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB42 -> BB43 to [0 .. 3.402823e+38] Setting edge weights for BB43 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB43 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB44 -> BB46 to [0 .. 3.402823e+38] Setting edge weights for BB44 -> BB45 to [0 .. 3.402823e+38] Setting edge weights for BB45 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB45 -> BB46 to [0 .. 3.402823e+38] Setting edge weights for BB46 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB47 -> BB50 to [0 .. 3.402823e+38] Setting edge weights for BB47 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB48 -> BB50 to [0 .. 3.402823e+38] Setting edge weights for BB48 -> BB49 to [0 .. 3.402823e+38] Setting edge weights for BB49 -> BB08 to [0 .. 3.402823e+38] Setting edge weights for BB49 -> BB50 to [0 .. 3.402823e+38] Setting edge weights for BB50 -> BB52 to [0 .. 3.402823e+38] Setting edge weights for BB50 -> BB51 to [0 .. 3.402823e+38] Setting edge weights for BB51 -> BB52 to [0 .. 3.402823e+38] Setting edge weights for BB52 -> BB56 to [0 .. 3.402823e+38] Setting edge weights for BB52 -> BB53 to [0 .. 3.402823e+38] Setting edge weights for BB53 -> BB55 to [0 .. 3.402823e+38] Setting edge weights for BB53 -> BB54 to [0 .. 3.402823e+38] Setting edge weights for BB54 -> BB56 to [0 .. 3.402823e+38] Setting edge weights for BB55 -> BB56 to [0 .. 3.402823e+38] Setting edge weights for BB56 -> BB63 to [0 .. 3.402823e+38] Setting edge weights for BB56 -> BB57 to [0 .. 3.402823e+38] Setting edge weights for BB57 -> BB59 to [0 .. 3.402823e+38] Setting edge weights for BB57 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB58 -> BB60 to [0 .. 3.402823e+38] Setting edge weights for BB59 -> BB60 to [0 .. 3.402823e+38] Setting edge weights for BB60 -> BB66 to [0 .. 3.402823e+38] Setting edge weights for BB60 -> BB61 to [0 .. 3.402823e+38] Setting edge weights for BB61 -> BB66 to [0 .. 3.402823e+38] Setting edge weights for BB61 -> BB62 to [0 .. 3.402823e+38] Setting edge weights for BB62 -> BB07 to [0 .. 3.402823e+38] Setting edge weights for BB63 -> BB65 to [0 .. 3.402823e+38] Setting edge weights for BB63 -> BB64 to [0 .. 3.402823e+38] Setting edge weights for BB64 -> BB65 to [0 .. 3.402823e+38] Setting edge weights for BB65 -> BB66 to [0 .. 3.402823e+38] Setting edge weights for BB66 -> BB68 to [0 .. 3.402823e+38] Setting edge weights for BB66 -> BB67 to [0 .. 3.402823e+38] Setting edge weights for BB67 -> BB69 to [0 .. 3.402823e+38] Setting edge weights for BB68 -> BB69 to [0 .. 3.402823e+38] Setting edge weights for BB69 -> BB71 to [0 .. 3.402823e+38] Setting edge weights for BB69 -> BB70 to [0 .. 3.402823e+38] Setting edge weights for BB70 -> BB72 to [0 .. 3.402823e+38] Setting edge weights for BB71 -> BB72 to [0 .. 3.402823e+38] Setting edge weights for BB72 -> BB74 to [0 .. 3.402823e+38] Setting edge weights for BB72 -> BB73 to [0 .. 3.402823e+38] Setting edge weights for BB73 -> BB78 to [0 .. 3.402823e+38] Setting edge weights for BB74 -> BB76 to [0 .. 3.402823e+38] Setting edge weights for BB74 -> BB75 to [0 .. 3.402823e+38] Setting edge weights for BB75 -> BB77 to [0 .. 3.402823e+38] Setting edge weights for BB76 -> BB77 to [0 .. 3.402823e+38] Setting edge weights for BB77 -> BB78 to [0 .. 3.402823e+38] Setting edge weights for BB78 -> BB103 to [0 .. 3.402823e+38] Setting edge weights for BB78 -> BB79 to [0 .. 3.402823e+38] Setting edge weights for BB79 -> BB103 to [0 .. 3.402823e+38] Setting edge weights for BB79 -> BB80 to [0 .. 3.402823e+38] Setting edge weights for BB80 -> BB82 to [0 .. 3.402823e+38] Setting edge weights for BB80 -> BB81 to [0 .. 3.402823e+38] Setting edge weights for BB81 -> BB82 to [0 .. 3.402823e+38] Setting edge weights for BB82 -> BB84 to [0 .. 3.402823e+38] Setting edge weights for BB82 -> BB83 to [0 .. 3.402823e+38] Setting edge weights for BB83 -> BB85 to [0 .. 3.402823e+38] Setting edge weights for BB84 -> BB85 to [0 .. 3.402823e+38] Setting edge weights for BB85 -> BB87 to [0 .. 3.402823e+38] Setting edge weights for BB85 -> BB86 to [0 .. 3.402823e+38] Setting edge weights for BB86 -> BB88 to [0 .. 3.402823e+38] Setting edge weights for BB87 -> BB88 to [0 .. 3.402823e+38] Setting edge weights for BB88 -> BB103 to [0 .. 3.402823e+38] Setting edge weights for BB88 -> BB89 to [0 .. 3.402823e+38] Setting edge weights for BB89 -> BB103 to [0 .. 3.402823e+38] Setting edge weights for BB89 -> BB90 to [0 .. 3.402823e+38] Setting edge weights for BB90 -> BB100 to [0 .. 3.402823e+38] Setting edge weights for BB90 -> BB91 to [0 .. 3.402823e+38] Setting edge weights for BB91 -> BB93 to [0 .. 3.402823e+38] Setting edge weights for BB91 -> BB92 to [0 .. 3.402823e+38] Setting edge weights for BB92 -> BB94 to [0 .. 3.402823e+38] Setting edge weights for BB93 -> BB94 to [0 .. 3.402823e+38] Setting edge weights for BB94 -> BB110 to [0 .. 3.402823e+38] Setting edge weights for BB94 -> BB95 to [0 .. 3.402823e+38] Setting edge weights for BB95 -> BB96 to [0 .. 3.402823e+38] Setting edge weights for BB96 -> BB98 to [0 .. 3.402823e+38] Setting edge weights for BB96 -> BB97 to [0 .. 3.402823e+38] Setting edge weights for BB97 -> BB99 to [0 .. 3.402823e+38] Setting edge weights for BB98 -> BB99 to [0 .. 3.402823e+38] Setting edge weights for BB99 -> BB100 to [0 .. 3.402823e+38] Setting edge weights for BB100 -> BB102 to [0 .. 3.402823e+38] Setting edge weights for BB100 -> BB101 to [0 .. 3.402823e+38] Setting edge weights for BB101 -> BB102 to [0 .. 3.402823e+38] Setting edge weights for BB102 -> BB89 to [0 .. 3.402823e+38] Setting edge weights for BB102 -> BB103 to [0 .. 3.402823e+38] Setting edge weights for BB103 -> BB112 to [0 .. 3.402823e+38] Setting edge weights for BB103 -> BB104 to [0 .. 3.402823e+38] Setting edge weights for BB104 -> BB112 to [0 .. 3.402823e+38] Setting edge weights for BB104 -> BB105 to [0 .. 3.402823e+38] Setting edge weights for BB105 -> BB112 to [0 .. 3.402823e+38] Setting edge weights for BB105 -> BB106 to [0 .. 3.402823e+38] Setting edge weights for BB106 -> BB112 to [0 .. 3.402823e+38] Setting edge weights for BB106 -> BB107 to [0 .. 3.402823e+38] Setting edge weights for BB107 -> BB111 to [0 .. 3.402823e+38] Setting edge weights for BB107 -> BB108 to [0 .. 3.402823e+38] Setting edge weights for BB108 -> BB111 to [0 .. 3.402823e+38] Setting edge weights for BB108 -> BB109 to [0 .. 3.402823e+38] Setting edge weights for BB109 -> BB112 to [0 .. 3.402823e+38] Setting edge weights for BB111 -> BB112 to [0 .. 3.402823e+38] Setting edge weights for BB112 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB113 -> BB136 to [0 .. 3.402823e+38] Setting edge weights for BB113 -> BB114 to [0 .. 3.402823e+38] Setting edge weights for BB114 -> BB135 to [0 .. 3.402823e+38] Setting edge weights for BB114 -> BB115 to [0 .. 3.402823e+38] Setting edge weights for BB115 -> BB135 to [0 .. 3.402823e+38] Setting edge weights for BB115 -> BB116 to [0 .. 3.402823e+38] Setting edge weights for BB116 -> BB135 to [0 .. 3.402823e+38] Setting edge weights for BB116 -> BB117 to [0 .. 3.402823e+38] Setting edge weights for BB117 -> BB136 to [0 .. 3.402823e+38] Setting edge weights for BB118 -> BB120 to [0 .. 3.402823e+38] Setting edge weights for BB118 -> BB119 to [0 .. 3.402823e+38] Setting edge weights for BB119 -> BB121 to [0 .. 3.402823e+38] Setting edge weights for BB120 -> BB121 to [0 .. 3.402823e+38] Setting edge weights for BB121 -> BB123 to [0 .. 3.402823e+38] Setting edge weights for BB121 -> BB122 to [0 .. 3.402823e+38] Setting edge weights for BB122 -> BB124 to [0 .. 3.402823e+38] Setting edge weights for BB123 -> BB124 to [0 .. 3.402823e+38] Setting edge weights for BB124 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB124 -> BB125 to [0 .. 3.402823e+38] Setting edge weights for BB125 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB125 -> BB126 to [0 .. 3.402823e+38] Setting edge weights for BB126 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB126 -> BB127 to [0 .. 3.402823e+38] Setting edge weights for BB127 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB127 -> BB128 to [0 .. 3.402823e+38] Setting edge weights for BB128 -> BB133 to [0 .. 3.402823e+38] Setting edge weights for BB128 -> BB129 to [0 .. 3.402823e+38] Setting edge weights for BB129 -> BB132 to [0 .. 3.402823e+38] Setting edge weights for BB129 -> BB130 to [0 .. 3.402823e+38] Setting edge weights for BB130 -> BB132 to [0 .. 3.402823e+38] Setting edge weights for BB130 -> BB131 to [0 .. 3.402823e+38] Setting edge weights for BB131 -> BB133 to [0 .. 3.402823e+38] Setting edge weights for BB132 -> BB133 to [0 .. 3.402823e+38] Setting edge weights for BB133 -> BB134 to [0 .. 3.402823e+38] Setting edge weights for BB134 -> BB135 to [0 .. 3.402823e+38] Setting edge weights for BB135 -> BB118 to [0 .. 3.402823e+38] Setting edge weights for BB135 -> BB136 to [0 .. 3.402823e+38] Setting edge weights for BB136 -> BB141 to [0 .. 3.402823e+38] Setting edge weights for BB136 -> BB137 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB194 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB145 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB242 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB186 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB138 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB242 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB171 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB145 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB139 to [0 .. 3.402823e+38] Setting edge weights for BB139 -> BB205 to [0 .. 3.402823e+38] Setting edge weights for BB139 -> BB140 to [0 .. 3.402823e+38] Setting edge weights for BB140 -> BB242 to [0 .. 3.402823e+38] Setting edge weights for BB141 -> BB200 to [0 .. 3.402823e+38] Setting edge weights for BB141 -> BB142 to [0 .. 3.402823e+38] Setting edge weights for BB142 -> BB205 to [0 .. 3.402823e+38] Setting edge weights for BB142 -> BB143 to [0 .. 3.402823e+38] Setting edge weights for BB143 -> BB242 to [0 .. 3.402823e+38] Setting edge weights for BB143 -> BB144 to [0 .. 3.402823e+38] Setting edge weights for BB144 -> BB181 to [0 .. 3.402823e+38] Setting edge weights for BB145 -> BB150 to [0 .. 3.402823e+38] Setting edge weights for BB145 -> BB146 to [0 .. 3.402823e+38] Setting edge weights for BB146 -> BB148 to [0 .. 3.402823e+38] Setting edge weights for BB146 -> BB147 to [0 .. 3.402823e+38] Setting edge weights for BB147 -> BB149 to [0 .. 3.402823e+38] Setting edge weights for BB148 -> BB149 to [0 .. 3.402823e+38] Setting edge weights for BB149 -> BB156 to [0 .. 3.402823e+38] Setting edge weights for BB150 -> BB154 to [0 .. 3.402823e+38] Setting edge weights for BB150 -> BB151 to [0 .. 3.402823e+38] Setting edge weights for BB151 -> BB153 to [0 .. 3.402823e+38] Setting edge weights for BB151 -> BB152 to [0 .. 3.402823e+38] Setting edge weights for BB152 -> BB155 to [0 .. 3.402823e+38] Setting edge weights for BB153 -> BB155 to [0 .. 3.402823e+38] Setting edge weights for BB154 -> BB155 to [0 .. 3.402823e+38] Setting edge weights for BB155 -> BB156 to [0 .. 3.402823e+38] Setting edge weights for BB156 -> BB170 to [0 .. 3.402823e+38] Setting edge weights for BB156 -> BB157 to [0 .. 3.402823e+38] Setting edge weights for BB157 -> BB159 to [0 .. 3.402823e+38] Setting edge weights for BB157 -> BB158 to [0 .. 3.402823e+38] Setting edge weights for BB158 -> BB160 to [0 .. 3.402823e+38] Setting edge weights for BB159 -> BB160 to [0 .. 3.402823e+38] Setting edge weights for BB160 -> BB170 to [0 .. 3.402823e+38] Setting edge weights for BB160 -> BB161 to [0 .. 3.402823e+38] Setting edge weights for BB161 -> BB170 to [0 .. 3.402823e+38] Setting edge weights for BB161 -> BB162 to [0 .. 3.402823e+38] Setting edge weights for BB162 -> BB170 to [0 .. 3.402823e+38] Setting edge weights for BB162 -> BB163 to [0 .. 3.402823e+38] Setting edge weights for BB163 -> BB170 to [0 .. 3.402823e+38] Setting edge weights for BB163 -> BB164 to [0 .. 3.402823e+38] Setting edge weights for BB164 -> BB169 to [0 .. 3.402823e+38] Setting edge weights for BB164 -> BB165 to [0 .. 3.402823e+38] Setting edge weights for BB165 -> BB168 to [0 .. 3.402823e+38] Setting edge weights for BB165 -> BB166 to [0 .. 3.402823e+38] Setting edge weights for BB166 -> BB168 to [0 .. 3.402823e+38] Setting edge weights for BB166 -> BB167 to [0 .. 3.402823e+38] Setting edge weights for BB167 -> BB169 to [0 .. 3.402823e+38] Setting edge weights for BB168 -> BB169 to [0 .. 3.402823e+38] Setting edge weights for BB169 -> BB170 to [0 .. 3.402823e+38] Setting edge weights for BB170 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB171 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB171 -> BB172 to [0 .. 3.402823e+38] Setting edge weights for BB172 -> BB175 to [0 .. 3.402823e+38] Setting edge weights for BB172 -> BB173 to [0 .. 3.402823e+38] Setting edge weights for BB173 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB173 -> BB174 to [0 .. 3.402823e+38] Setting edge weights for BB174 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB174 -> BB175 to [0 .. 3.402823e+38] Setting edge weights for BB175 -> BB180 to [0 .. 3.402823e+38] Setting edge weights for BB175 -> BB176 to [0 .. 3.402823e+38] Setting edge weights for BB176 -> BB179 to [0 .. 3.402823e+38] Setting edge weights for BB176 -> BB177 to [0 .. 3.402823e+38] Setting edge weights for BB177 -> BB179 to [0 .. 3.402823e+38] Setting edge weights for BB177 -> BB178 to [0 .. 3.402823e+38] Setting edge weights for BB178 -> BB180 to [0 .. 3.402823e+38] Setting edge weights for BB179 -> BB180 to [0 .. 3.402823e+38] Setting edge weights for BB180 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB181 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB181 -> BB182 to [0 .. 3.402823e+38] Setting edge weights for BB182 -> BB185 to [0 .. 3.402823e+38] Setting edge weights for BB182 -> BB183 to [0 .. 3.402823e+38] Setting edge weights for BB183 -> BB185 to [0 .. 3.402823e+38] Setting edge weights for BB183 -> BB184 to [0 .. 3.402823e+38] Setting edge weights for BB184 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB185 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB186 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB186 -> BB187 to [0 .. 3.402823e+38] Setting edge weights for BB187 -> BB190 to [0 .. 3.402823e+38] Setting edge weights for BB187 -> BB188 to [0 .. 3.402823e+38] Setting edge weights for BB188 -> BB190 to [0 .. 3.402823e+38] Setting edge weights for BB188 -> BB189 to [0 .. 3.402823e+38] Setting edge weights for BB189 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB190 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB191 -> BB193 to [0 .. 3.402823e+38] Setting edge weights for BB191 -> BB192 to [0 .. 3.402823e+38] Setting edge weights for BB192 -> BB194 to [0 .. 3.402823e+38] Setting edge weights for BB193 -> BB194 to [0 .. 3.402823e+38] Setting edge weights for BB194 -> BB197 to [0 .. 3.402823e+38] Setting edge weights for BB194 -> BB195 to [0 .. 3.402823e+38] Setting edge weights for BB195 -> BB197 to [0 .. 3.402823e+38] Setting edge weights for BB195 -> BB196 to [0 .. 3.402823e+38] Setting edge weights for BB196 -> BB191 to [0 .. 3.402823e+38] Setting edge weights for BB196 -> BB197 to [0 .. 3.402823e+38] Setting edge weights for BB197 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB197 -> BB198 to [0 .. 3.402823e+38] Setting edge weights for BB198 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB198 -> BB199 to [0 .. 3.402823e+38] Setting edge weights for BB199 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB200 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB200 -> BB201 to [0 .. 3.402823e+38] Setting edge weights for BB201 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB201 -> BB202 to [0 .. 3.402823e+38] Setting edge weights for BB202 -> BB204 to [0 .. 3.402823e+38] Setting edge weights for BB202 -> BB203 to [0 .. 3.402823e+38] Setting edge weights for BB203 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB204 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB205 -> BB227 to [0 .. 3.402823e+38] Setting edge weights for BB205 -> BB206 to [0 .. 3.402823e+38] Setting edge weights for BB206 -> BB208 to [0 .. 3.402823e+38] Setting edge weights for BB206 -> BB207 to [0 .. 3.402823e+38] Setting edge weights for BB207 -> BB218 to [0 .. 3.402823e+38] Setting edge weights for BB207 -> BB208 to [0 .. 3.402823e+38] Setting edge weights for BB208 -> BB212 to [0 .. 3.402823e+38] Setting edge weights for BB208 -> BB209 to [0 .. 3.402823e+38] Setting edge weights for BB209 -> BB212 to [0 .. 3.402823e+38] Setting edge weights for BB209 -> BB210 to [0 .. 3.402823e+38] Setting edge weights for BB210 -> BB212 to [0 .. 3.402823e+38] Setting edge weights for BB210 -> BB211 to [0 .. 3.402823e+38] Setting edge weights for BB211 -> BB219 to [0 .. 3.402823e+38] Setting edge weights for BB212 -> BB215 to [0 .. 3.402823e+38] Setting edge weights for BB212 -> BB213 to [0 .. 3.402823e+38] Setting edge weights for BB213 -> BB215 to [0 .. 3.402823e+38] Setting edge weights for BB213 -> BB214 to [0 .. 3.402823e+38] Setting edge weights for BB214 -> BB219 to [0 .. 3.402823e+38] Setting edge weights for BB214 -> BB215 to [0 .. 3.402823e+38] Setting edge weights for BB215 -> BB217 to [0 .. 3.402823e+38] Setting edge weights for BB215 -> BB216 to [0 .. 3.402823e+38] Setting edge weights for BB216 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB217 -> BB244 to [0 .. 3.402823e+38] Setting edge weights for BB218 -> BB219 to [0 .. 3.402823e+38] Setting edge weights for BB219 -> BB221 to [0 .. 3.402823e+38] Setting edge weights for BB219 -> BB220 to [0 .. 3.402823e+38] Setting edge weights for BB220 -> BB218 to [0 .. 3.402823e+38] Setting edge weights for BB220 -> BB221 to [0 .. 3.402823e+38] Setting edge weights for BB221 -> BB223 to [0 .. 3.402823e+38] Setting edge weights for BB221 -> BB222 to [0 .. 3.402823e+38] Setting edge weights for BB222 -> BB223 to [0 .. 3.402823e+38] Setting edge weights for BB223 -> BB225 to [0 .. 3.402823e+38] Setting edge weights for BB223 -> BB224 to [0 .. 3.402823e+38] Setting edge weights for BB224 -> BB226 to [0 .. 3.402823e+38] Setting edge weights for BB225 -> BB226 to [0 .. 3.402823e+38] Setting edge weights for BB226 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB227 -> BB229 to [0 .. 3.402823e+38] Setting edge weights for BB227 -> BB228 to [0 .. 3.402823e+38] Setting edge weights for BB228 -> BB230 to [0 .. 3.402823e+38] Setting edge weights for BB229 -> BB230 to [0 .. 3.402823e+38] Setting edge weights for BB230 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB230 -> BB231 to [0 .. 3.402823e+38] Setting edge weights for BB231 -> BB233 to [0 .. 3.402823e+38] Setting edge weights for BB231 -> BB232 to [0 .. 3.402823e+38] Setting edge weights for BB232 -> BB239 to [0 .. 3.402823e+38] Setting edge weights for BB232 -> BB233 to [0 .. 3.402823e+38] Setting edge weights for BB233 -> BB235 to [0 .. 3.402823e+38] Setting edge weights for BB233 -> BB234 to [0 .. 3.402823e+38] Setting edge weights for BB234 -> BB239 to [0 .. 3.402823e+38] Setting edge weights for BB235 -> BB239 to [0 .. 3.402823e+38] Setting edge weights for BB236 -> BB238 to [0 .. 3.402823e+38] Setting edge weights for BB236 -> BB237 to [0 .. 3.402823e+38] Setting edge weights for BB237 -> BB239 to [0 .. 3.402823e+38] Setting edge weights for BB238 -> BB239 to [0 .. 3.402823e+38] Setting edge weights for BB239 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB239 -> BB240 to [0 .. 3.402823e+38] Setting edge weights for BB240 -> BB236 to [0 .. 3.402823e+38] Setting edge weights for BB240 -> BB241 to [0 .. 3.402823e+38] Setting edge weights for BB241 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB242 -> BB244 to [0 .. 3.402823e+38] Setting edge weights for BB242 -> BB243 to [0 .. 3.402823e+38] Setting edge weights for BB243 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB244 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB245 -> BB248 to [0 .. 3.402823e+38] Setting edge weights for BB245 -> BB246 to [0 .. 3.402823e+38] Setting edge weights for BB246 -> BB248 to [0 .. 3.402823e+38] Setting edge weights for BB246 -> BB247 to [0 .. 3.402823e+38] Setting edge weights for BB247 -> BB113 to [0 .. 3.402823e+38] Setting edge weights for BB247 -> BB248 to [0 .. 3.402823e+38] Setting edge weights for BB248 -> BB253 to [0 .. 3.402823e+38] Setting edge weights for BB248 -> BB249 to [0 .. 3.402823e+38] Setting edge weights for BB249 -> BB253 to [0 .. 3.402823e+38] Setting edge weights for BB249 -> BB250 to [0 .. 3.402823e+38] Setting edge weights for BB250 -> BB253 to [0 .. 3.402823e+38] Setting edge weights for BB250 -> BB251 to [0 .. 3.402823e+38] Setting edge weights for BB251 -> BB253 to [0 .. 3.402823e+38] Setting edge weights for BB251 -> BB252 to [0 .. 3.402823e+38] Setting edge weights for BB252 -> BB253 to [0 .. 3.402823e+38] Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB02 BB03 BB04 : BB01 BB02 BB04 BB05 : BB01 BB05 BB06 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB08 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB09 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB10 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB11 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB12 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB13 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB14 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB15 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB16 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB17 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB18 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB19 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB20 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB21 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 BB61 BB62 BB22 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB40 BB41 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 BB60 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BB01 BB176: BB176 BB175 BB172 BB171 BB138 BB137 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB177: BB177 BB176 BB175 BB172 BB171 BB138 BB137 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB178: BB178 BB177 BB176 BB175 BB172 BB171 BB138 BB137 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB179: BB179 BB176 BB175 BB172 BB171 BB138 BB137 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB180: BB180 BB175 BB172 BB171 BB138 BB137 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB139: BB139 BB138 BB137 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB140: BB140 BB139 BB138 BB137 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB141: BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB142: BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB143: BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB144: BB144 BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB181: BB181 BB144 BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB182: BB182 BB181 BB144 BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB183: BB183 BB182 BB181 BB144 BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB184: BB184 BB183 BB182 BB181 BB144 BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB185: BB185 BB182 BB181 BB144 BB143 BB142 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB242: BB242 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB243: BB243 BB242 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB205: BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB206: BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB207: BB207 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB208: BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB209: BB209 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB210: BB210 BB209 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB211: BB211 BB210 BB209 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB212: BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB213: BB213 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB214: BB214 BB213 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB219: BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB220: BB220 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB218: BB218 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB221: BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB222: BB222 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB223: BB223 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB224: BB224 BB223 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB225: BB225 BB223 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB226: BB226 BB223 BB221 BB219 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB215: BB215 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB216: BB216 BB215 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB217: BB217 BB215 BB212 BB208 BB206 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB244: BB244 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB227: BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB228: BB228 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB229: BB229 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB230: BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB231: BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB232: BB232 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB233: BB233 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB234: BB234 BB233 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB235: BB235 BB233 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB239: BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB240: BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB241: BB241 BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB236: BB236 BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB237: BB237 BB236 BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB238: BB238 BB236 BB240 BB239 BB231 BB230 BB227 BB205 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB200: BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB201: BB201 BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB202: BB202 BB201 BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB203: BB203 BB202 BB201 BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB204: BB204 BB202 BB201 BB200 BB141 BB136 BB113 BB247 BB246 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB248: BB248 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB249: BB249 BB248 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB250: BB250 BB249 BB248 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB251: BB251 BB250 BB249 BB248 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB252: BB252 BB251 BB250 BB249 BB248 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 BB253: BB253 BB248 BB245 BB112 BB103 BB78 BB72 BB69 BB66 BB56 BB52 BB50 BB47 BB07 BB06 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB06 BB05 BB02 BB02 : BB04 BB03 BB06 : BB07 BB07 : BB47 BB08 : BB38 BB13 BB09 BB09 : BB31 BB30 BB17 BB10 BB10 : BB23 BB21 BB18 BB11 BB11 : BB12 BB13 : BB35 BB14 BB14 : BB15 BB15 : BB16 BB18 : BB20 BB19 BB21 : BB22 BB23 : BB24 BB24 : BB25 BB25 : BB29 BB26 BB26 : BB28 BB27 BB31 : BB32 BB32 : BB33 BB33 : BB34 BB35 : BB36 BB36 : BB37 BB38 : BB44 BB40 BB39 BB40 : BB41 BB41 : BB43 BB42 BB44 : BB46 BB45 BB47 : BB50 BB48 BB48 : BB49 BB49 : BB08 BB50 : BB52 BB51 BB52 : BB56 BB53 BB53 : BB55 BB54 BB56 : BB66 BB63 BB57 BB57 : BB60 BB59 BB58 BB60 : BB61 BB61 : BB62 BB63 : BB65 BB64 BB66 : BB69 BB68 BB67 BB69 : BB72 BB71 BB70 BB72 : BB78 BB74 BB73 BB74 : BB77 BB76 BB75 BB78 : BB103 BB79 BB79 : BB80 BB80 : BB82 BB81 BB82 : BB85 BB84 BB83 BB85 : BB88 BB87 BB86 BB88 : BB89 BB89 : BB90 BB90 : BB100 BB91 BB91 : BB94 BB93 BB92 BB94 : BB110 BB95 BB95 : BB96 BB96 : BB99 BB98 BB97 BB100 : BB102 BB101 BB103 : BB112 BB104 BB104 : BB105 BB105 : BB106 BB106 : BB107 BB107 : BB111 BB108 BB108 : BB109 BB112 : BB245 BB113 : BB136 BB114 BB114 : BB135 BB115 BB115 : BB116 BB116 : BB117 BB118 : BB121 BB120 BB119 BB121 : BB124 BB123 BB122 BB124 : BB134 BB125 BB125 : BB126 BB126 : BB127 BB127 : BB128 BB128 : BB133 BB129 BB129 : BB132 BB130 BB130 : BB131 BB135 : BB118 BB136 : BB244 BB242 BB205 BB141 BB137 BB137 : BB194 BB186 BB145 BB138 BB138 : BB171 BB139 BB139 : BB140 BB141 : BB200 BB142 BB142 : BB143 BB143 : BB144 BB144 : BB181 BB145 : BB156 BB150 BB146 BB146 : BB149 BB148 BB147 BB150 : BB155 BB154 BB151 BB151 : BB153 BB152 BB156 : BB170 BB157 BB157 : BB160 BB159 BB158 BB160 : BB161 BB161 : BB162 BB162 : BB163 BB163 : BB164 BB164 : BB169 BB165 BB165 : BB168 BB166 BB166 : BB167 BB171 : BB172 BB172 : BB175 BB173 BB173 : BB174 BB175 : BB180 BB176 BB176 : BB179 BB177 BB177 : BB178 BB181 : BB182 BB182 : BB185 BB183 BB183 : BB184 BB186 : BB187 BB187 : BB190 BB188 BB188 : BB189 BB191 : BB193 BB192 BB194 : BB197 BB195 BB195 : BB196 BB196 : BB191 BB197 : BB198 BB198 : BB199 BB200 : BB201 BB201 : BB202 BB202 : BB204 BB203 BB205 : BB227 BB206 BB206 : BB219 BB218 BB208 BB207 BB208 : BB212 BB209 BB209 : BB210 BB210 : BB211 BB212 : BB215 BB213 BB213 : BB214 BB215 : BB217 BB216 BB219 : BB221 BB220 BB221 : BB223 BB222 BB223 : BB226 BB225 BB224 BB227 : BB230 BB229 BB228 BB230 : BB231 BB231 : BB239 BB233 BB232 BB233 : BB235 BB234 BB236 : BB238 BB237 BB239 : BB240 BB240 : BB241 BB236 BB242 : BB243 BB245 : BB248 BB246 BB246 : BB247 BB247 : BB113 BB248 : BB253 BB249 BB249 : BB250 BB250 : BB251 BB251 : BB252 After numbering the dominator tree: BB01: pre=01, post=253 BB02: pre=251, post=252 BB03: pre=253, post=251 BB04: pre=252, post=250 BB05: pre=250, post=249 BB06: pre=02, post=248 BB07: pre=03, post=247 BB08: pre=211, post=243 BB09: pre=228, post=242 BB10: pre=235, post=241 BB11: pre=248, post=240 BB12: pre=249, post=239 BB13: pre=221, post=220 BB14: pre=225, post=219 BB15: pre=226, post=218 BB16: pre=227, post=217 BB17: pre=234, post=226 BB18: pre=245, post=238 BB19: pre=247, post=237 BB20: pre=246, post=236 BB21: pre=243, post=235 BB22: pre=244, post=234 BB23: pre=236, post=233 BB24: pre=237, post=232 BB25: pre=238, post=231 BB26: pre=240, post=230 BB27: pre=242, post=229 BB28: pre=241, post=228 BB29: pre=239, post=227 BB30: pre=233, post=225 BB31: pre=229, post=224 BB32: pre=230, post=223 BB33: pre=231, post=222 BB34: pre=232, post=221 BB35: pre=222, post=216 BB36: pre=223, post=215 BB37: pre=224, post=214 BB38: pre=212, post=213 BB39: pre=220, post=212 BB40: pre=216, post=211 BB41: pre=217, post=210 BB42: pre=219, post=209 BB43: pre=218, post=208 BB44: pre=213, post=207 BB45: pre=215, post=206 BB46: pre=214, post=205 BB47: pre=04, post=246 BB48: pre=209, post=245 BB49: pre=210, post=244 BB50: pre=05, post=204 BB51: pre=208, post=203 BB52: pre=06, post=202 BB53: pre=205, post=201 BB54: pre=207, post=200 BB55: pre=206, post=199 BB56: pre=07, post=198 BB57: pre=199, post=197 BB58: pre=204, post=196 BB59: pre=203, post=195 BB60: pre=200, post=194 BB61: pre=201, post=193 BB62: pre=202, post=192 BB63: pre=196, post=191 BB64: pre=198, post=190 BB65: pre=197, post=189 BB66: pre=08, post=188 BB67: pre=195, post=187 BB68: pre=194, post=186 BB69: pre=09, post=185 BB70: pre=193, post=184 BB71: pre=192, post=183 BB72: pre=10, post=182 BB73: pre=191, post=181 BB74: pre=187, post=180 BB75: pre=190, post=179 BB76: pre=189, post=178 BB77: pre=188, post=177 BB78: pre=11, post=176 BB79: pre=162, post=175 BB80: pre=163, post=174 BB81: pre=186, post=173 BB82: pre=164, post=172 BB83: pre=185, post=171 BB84: pre=184, post=170 BB85: pre=165, post=169 BB86: pre=183, post=168 BB87: pre=182, post=167 BB88: pre=166, post=166 BB89: pre=167, post=165 BB90: pre=168, post=164 BB91: pre=172, post=163 BB92: pre=181, post=162 BB93: pre=180, post=161 BB94: pre=173, post=160 BB95: pre=175, post=159 BB96: pre=176, post=158 BB97: pre=179, post=157 BB98: pre=178, post=156 BB99: pre=177, post=155 BB100: pre=169, post=153 BB101: pre=171, post=152 BB102: pre=170, post=151 BB103: pre=12, post=150 BB104: pre=155, post=149 BB105: pre=156, post=148 BB106: pre=157, post=147 BB107: pre=158, post=146 BB108: pre=160, post=145 BB109: pre=161, post=144 BB110: pre=174, post=154 BB111: pre=159, post=143 BB112: pre=13, post=142 BB113: pre=23, post=138 BB114: pre=133, post=137 BB115: pre=152, post=136 BB116: pre=153, post=135 BB117: pre=154, post=134 BB118: pre=135, post=132 BB119: pre=151, post=131 BB120: pre=150, post=130 BB121: pre=136, post=129 BB122: pre=149, post=128 BB123: pre=148, post=127 BB124: pre=137, post=126 BB125: pre=139, post=125 BB126: pre=140, post=124 BB127: pre=141, post=123 BB128: pre=142, post=122 BB129: pre=144, post=121 BB130: pre=146, post=120 BB131: pre=147, post=119 BB132: pre=145, post=118 BB133: pre=143, post=117 BB134: pre=138, post=116 BB135: pre=134, post=133 BB136: pre=24, post=115 BB137: pre=79, post=114 BB138: pre=120, post=113 BB139: pre=131, post=112 BB140: pre=132, post=111 BB141: pre=65, post=60 BB142: pre=71, post=59 BB143: pre=72, post=58 BB144: pre=73, post=57 BB145: pre=94, post=100 BB146: pre=116, post=99 BB147: pre=119, post=98 BB148: pre=118, post=97 BB149: pre=117, post=96 BB150: pre=110, post=95 BB151: pre=113, post=94 BB152: pre=115, post=93 BB153: pre=114, post=92 BB154: pre=112, post=91 BB155: pre=111, post=90 BB156: pre=95, post=89 BB157: pre=97, post=88 BB158: pre=109, post=87 BB159: pre=108, post=86 BB160: pre=98, post=85 BB161: pre=99, post=84 BB162: pre=100, post=83 BB163: pre=101, post=82 BB164: pre=102, post=81 BB165: pre=104, post=80 BB166: pre=106, post=79 BB167: pre=107, post=78 BB168: pre=105, post=77 BB169: pre=103, post=76 BB170: pre=96, post=75 BB171: pre=121, post=110 BB172: pre=122, post=109 BB173: pre=129, post=108 BB174: pre=130, post=107 BB175: pre=123, post=106 BB176: pre=125, post=105 BB177: pre=127, post=104 BB178: pre=128, post=103 BB179: pre=126, post=102 BB180: pre=124, post=101 BB181: pre=74, post=56 BB182: pre=75, post=55 BB183: pre=77, post=54 BB184: pre=78, post=53 BB185: pre=76, post=52 BB186: pre=89, post=74 BB187: pre=90, post=73 BB188: pre=92, post=72 BB189: pre=93, post=71 BB190: pre=91, post=70 BB191: pre=86, post=66 BB192: pre=88, post=65 BB193: pre=87, post=64 BB194: pre=80, post=69 BB195: pre=84, post=68 BB196: pre=85, post=67 BB197: pre=81, post=63 BB198: pre=82, post=62 BB199: pre=83, post=61 BB200: pre=66, post=51 BB201: pre=67, post=50 BB202: pre=68, post=49 BB203: pre=70, post=48 BB204: pre=69, post=47 BB205: pre=28, post=46 BB206: pre=44, post=45 BB207: pre=64, post=44 BB208: pre=54, post=43 BB209: pre=61, post=42 BB210: pre=62, post=41 BB211: pre=63, post=40 BB212: pre=55, post=39 BB213: pre=59, post=38 BB214: pre=60, post=37 BB215: pre=56, post=36 BB216: pre=58, post=35 BB217: pre=57, post=34 BB218: pre=53, post=33 BB219: pre=45, post=32 BB220: pre=52, post=31 BB221: pre=46, post=30 BB222: pre=51, post=29 BB223: pre=47, post=28 BB224: pre=50, post=27 BB225: pre=49, post=26 BB226: pre=48, post=25 BB227: pre=29, post=24 BB228: pre=43, post=23 BB229: pre=42, post=22 BB230: pre=30, post=21 BB231: pre=31, post=20 BB232: pre=41, post=19 BB233: pre=38, post=18 BB234: pre=40, post=17 BB235: pre=39, post=16 BB236: pre=35, post=13 BB237: pre=37, post=12 BB238: pre=36, post=11 BB239: pre=32, post=15 BB240: pre=33, post=14 BB241: pre=34, post=10 BB242: pre=26, post=09 BB243: pre=27, post=08 BB244: pre=25, post=07 BB245: pre=14, post=141 BB246: pre=21, post=140 BB247: pre=22, post=139 BB248: pre=15, post=06 BB249: pre=17, post=05 BB250: pre=18, post=04 BB251: pre=19, post=03 BB252: pre=20, post=02 BB253: pre=16, post=01 *************** Natural loop table L00, from BB07 to BB62 (Head=BB06, Entry=BB07, ExitCnt=3), child loop = L01 L01, from BB08 to BB49 (Head=BB07, Entry=BB47, ExitCnt=3, parent=L00) L02, from BB89 to BB102 (Head=BB88, Entry=BB89, ExitCnt=3) L03, from BB113 to BB247 (Head=BB112, Entry=BB245, ExitCnt=3) *************** In optFindAndScaleGeneralLoopBlocks() Marking a loop from BB07 to BB62 BB07(wt=800) BB08(wt=200) BB09(wt=200) BB10(wt=200) BB11(wt=200) BB12(wt=200) BB13(wt=200) BB14(wt=200) BB15(wt=200) BB16(wt=200) BB17(wt=200) BB18(wt=200) BB19(wt=200) BB20(wt=200) BB21(wt=200) BB22(wt=200) BB23(wt=200) BB24(wt=200) BB25(wt=200) BB26(wt=200) BB27(wt=200) BB28(wt=200) BB29(wt=200) BB30(wt=200) BB31(wt=200) BB32(wt=200) BB33(wt=200) BB34(wt=200) BB35(wt=200) BB36(wt=200) BB37(wt=200) BB38(wt=200) BB39(wt=200) BB40(wt=200) BB41(wt=200) BB42(wt=200) BB43(wt=200) BB44(wt=200) BB45(wt=200) BB46(wt=200) BB47(wt=800) BB48(wt=200) BB49(wt=200) BB50(wt=800) BB51(wt=200) BB52(wt=800) BB53(wt=200) BB54(wt=200) BB55(wt=200) BB56(wt=800) BB57(wt=400) BB58(wt=200) BB59(wt=200) BB60(wt=400) BB61(wt=400) BB62(wt=400) Marking a loop from BB08 to BB49 BB08(wt=800) BB09(wt=800) BB10(wt=800) BB11(wt=800) BB12(wt=800) BB13(wt=800) BB14(wt=800) BB15(wt=800) BB16(wt=800) BB17(wt=800) BB18(wt=800) BB19(wt=800) BB20(wt=800) BB21(wt=800) BB22(wt=800) BB23(wt=800) BB24(wt=800) BB25(wt=800) BB26(wt=800) BB27(wt=800) BB28(wt=800) BB29(wt=800) BB30(wt=800) BB31(wt=800) BB32(wt=800) BB33(wt=800) BB34(wt=800) BB35(wt=800) BB36(wt=800) BB37(wt=800) BB38(wt=800) BB39(wt=800) BB40(wt=800) BB41(wt=800) BB42(wt=800) BB43(wt=800) BB44(wt=800) BB45(wt=800) BB46(wt=800) BB47(wt=6400) BB48(wt=1600) BB49(wt=1600) Marking a loop from BB31 to BB33 BB31(wt=6400) BB32(wt=6400) BB33(wt=6400) Marking a loop from BB44 to BB45 BB44(wt=6400) BB45(wt=6400) Marking a loop from BB89 to BB102 BB89(wt=400) BB90(wt=400) BB91(wt=200) BB92(wt=200) BB93(wt=200) BB94(wt=200) BB95(wt=200) BB96(wt=200) BB97(wt=200) BB98(wt=200) BB99(wt=200) BB100(wt=400) BB101(wt=200) BB102(wt=400) Marking a loop from BB113 to BB247 BB113(wt=200) BB114(wt=200) BB115(wt=200) BB116(wt=200) BB117(wt=200) BB118(wt=200) BB119(wt=200) BB120(wt=200) BB121(wt=200) BB122(wt=200) BB123(wt=200) BB124(wt=200) BB125(wt=200) BB126(wt=200) BB127(wt=200) BB128(wt=200) BB129(wt=200) BB130(wt=200) BB131(wt=200) BB132(wt=200) BB133(wt=200) BB134(wt=200) BB135(wt=200) BB136(wt=200) BB137(wt=200) BB138(wt=200) BB139(wt=200) BB140(wt=200) BB141(wt=200) BB142(wt=200) BB143(wt=200) BB144(wt=200) BB145(wt=200) BB146(wt=200) BB147(wt=200) BB148(wt=200) BB149(wt=200) BB150(wt=200) BB151(wt=200) BB152(wt=200) BB153(wt=200) BB154(wt=200) BB155(wt=200) BB156(wt=200) BB157(wt=200) BB158(wt=200) BB159(wt=200) BB160(wt=200) BB161(wt=200) BB162(wt=200) BB163(wt=200) BB164(wt=200) BB165(wt=200) BB166(wt=200) BB167(wt=200) BB168(wt=200) BB169(wt=200) BB170(wt=200) BB171(wt=200) BB172(wt=200) BB173(wt=200) BB174(wt=200) BB175(wt=200) BB176(wt=200) BB177(wt=200) BB178(wt=200) BB179(wt=200) BB180(wt=200) BB181(wt=200) BB182(wt=200) BB183(wt=200) BB184(wt=200) BB185(wt=200) BB186(wt=200) BB187(wt=200) BB188(wt=200) BB189(wt=200) BB190(wt=200) BB191(wt=200) BB192(wt=200) BB193(wt=200) BB194(wt=200) BB195(wt=200) BB196(wt=200) BB197(wt=200) BB198(wt=200) BB199(wt=200) BB200(wt=200) BB201(wt=200) BB202(wt=200) BB203(wt=200) BB204(wt=200) BB205(wt=200) BB206(wt=200) BB207(wt=200) BB208(wt=200) BB209(wt=200) BB210(wt=200) BB211(wt=200) BB212(wt=200) BB213(wt=200) BB214(wt=200) BB215(wt=200) BB216(wt=200) BB217(wt=200) BB218(wt=200) BB219(wt=200) BB220(wt=200) BB221(wt=200) BB222(wt=200) BB223(wt=200) BB224(wt=200) BB225(wt=200) BB226(wt=200) BB227(wt=200) BB228(wt=200) BB229(wt=200) BB230(wt=200) BB231(wt=200) BB232(wt=200) BB233(wt=200) BB234(wt=200) BB235(wt=200) BB236(wt=200) BB237(wt=200) BB238(wt=200) BB239(wt=200) BB240(wt=200) BB241(wt=200) BB242(wt=200) BB243(wt=200) BB244(wt=200) BB245(wt=800) BB246(wt=400) BB247(wt=400) Marking a loop from BB118 to BB135 BB118(wt=800) BB119(wt=800) BB120(wt=800) BB121(wt=800) BB122(wt=800) BB123(wt=800) BB124(wt=800) BB125(wt=800) BB126(wt=800) BB127(wt=800) BB128(wt=800) BB129(wt=800) BB130(wt=800) BB131(wt=800) BB132(wt=800) BB133(wt=800) BB134(wt=800) BB135(wt=1600) Marking a loop from BB191 to BB196 BB191(wt=800) BB192(wt=800) BB193(wt=800) BB194(wt=1600) BB195(wt=1600) BB196(wt=1600) Marking a loop from BB218 to BB220 BB218(wt=800) BB219(wt=1600) BB220(wt=1600) Marking a loop from BB236 to BB240 BB236(wt=800) BB237(wt=800) BB238(wt=800) BB239(wt=1600) BB240(wt=1600) Found a total of 10 general loops. *************** Finishing PHASE Find loops Trees after Find loops ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB44 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB48 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB82 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB83 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB96 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB119 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB120 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB120 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB219 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Clone loops *************** In optCloneLoops() Considering loop L00 to clone for optimizations. Loop cloning: rejecting loop L00. No LPFLG_ITER flag. ------------------------------------------------------------ Considering loop L01 to clone for optimizations. Loop cloning: rejecting loop L01. No LPFLG_ITER flag. ------------------------------------------------------------ Considering loop L02 to clone for optimizations. Loop cloning: rejecting loop L02. No LPFLG_ITER flag. ------------------------------------------------------------ Considering loop L03 to clone for optimizations. Loop cloning: rejecting loop L03. No LPFLG_ITER flag. ------------------------------------------------------------ No clonable loops *************** Finishing PHASE Clone loops Trees after Clone loops ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB44 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB48 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB82 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB83 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB96 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB119 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB120 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB120 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB219 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Unroll loops *************** In optUnrollLoops() *************** In fgDebugCheckBBlist *************** Finishing PHASE Unroll loops Trees after Unroll loops ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 ***** BB44 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 ***** BB48 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 ***** BB82 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB83 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 ***** BB96 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB119 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 ***** BB120 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 ***** BB120 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 ***** BB219 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Clear loop info *************** Finishing PHASE Clear loop info [no changes] *************** Starting PHASE Morph array ops No multi-dimensional array references in the function *************** Finishing PHASE Morph array ops [no changes] *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00000 ( 0x000[E-] ... 0x007 ) [000001] --CXG+----- * CALL r2r_ind void [000000] -----+----- this in x0 +--* LCL_VAR byref V01 arg1 [002543] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn New refCnts for V01: refCnt = 1, refCntWtd = 1 STMT00001 ( 0x006[E-] ... ??? ) [000004] -A---+----- * ASG int [000003] D----+-N--- +--* LCL_VAR int V11 loc7 [000002] -----+----- \--* CNS_INT int 0 New refCnts for V11: refCnt = 1, refCntWtd = 1 V11 needs explicit zero init. Disqualified as a single-def register candidate. STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] [001500] -A-XG+----- * ASG byref [001499] D----+-N--- +--* LCL_VAR byref V76 tmp36 [002549] ---X-+-N--- \--* COMMA byref [002545] ---X-+----- +--* NULLCHECK byte [002544] -----+----- | \--* LCL_VAR byref V01 arg1 [002548] -----+----- \--* ADD byref [002546] -----+----- +--* LCL_VAR byref V01 arg1 [002547] -----+----- \--* CNS_INT long 16 New refCnts for V76: refCnt = 1, refCntWtd = 2 Marking EH Var V76 as a register candidate. New refCnts for V01: refCnt = 2, refCntWtd = 2 New refCnts for V01: refCnt = 3, refCntWtd = 3 STMT00003 ( 0x009[E-] ... ??? ) [000009] -A-XG+----- * ASG long [000008] D----+-N--- +--* LCL_VAR long V17 loc13 [002554] -A-XG+----- \--* COMMA long [002551] -A-XG+----- +--* ASG long [002550] D----+-N--- | +--* LCL_VAR long V167 tmp127 [001507] ---XG+----- | \--* COMMA byref [001504] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001497] -----+----- | | +--* CNS_INT int 0 [001503] ---XG+----- | | \--* IND int [002556] -----+----- | | \--* ADD byref [001502] -----+----- | | +--* LCL_VAR byref V76 tmp36 [002555] -----+----- | | \--* CNS_INT long 8 [001505] ---XG+----- | \--* IND byref [001501] -----+----- | \--* LCL_VAR byref V76 tmp36 [002552] -----+----- \--* LCL_VAR long V167 tmp127 New refCnts for V17: refCnt = 1, refCntWtd = 1 V17 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V167: refCnt = 1, refCntWtd = 2 V167 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V76: refCnt = 2, refCntWtd = 4 New refCnts for V76: refCnt = 3, refCntWtd = 6 New refCnts for V167: refCnt = 2, refCntWtd = 4 STMT00005 ( ??? ... 0x015 ) [002563] -A---+----- * COMMA void [002559] -A--------- +--* ASG byref [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002562] -A--------- \--* ASG int [002560] D------N--- +--* LCL_VAR int V148 tmp108 [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V147: refCnt = 1, refCntWtd = 1 Marking EH Var V147 as a register candidate. New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V148: refCnt = 1, refCntWtd = 1 V148 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V02: refCnt = 2, refCntWtd = 2 STMT00004 ( 0x011[E-] ... 0x015 ) [000015] ---XG+----- * JTRUE void [000014] J--XG+-N--- \--* EQ int [000012] ---XG+----- +--* IND ubyte [000011] -----+----- | \--* LCL_VAR long V167 tmp127 [000013] -----+----- \--* CNS_INT int 0 New refCnts for V167: refCnt = 3, refCntWtd = 6 *** marking local variables in block BB02 (weight=0.50) STMT00315 ( ??? ... 0x01D ) [002570] -A---+----- * COMMA void [002566] -A--------- +--* ASG byref [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 [002565] ----------- | \--* LCL_VAR byref V147 tmp107 [002569] -A--------- \--* ASG int [002567] D------N--- +--* LCL_VAR int V156 tmp116 [002568] ----------- \--* LCL_VAR int V148 tmp108 New refCnts for V155: refCnt = 1, refCntWtd = 0.50 Marking EH Var V155 as a register candidate. New refCnts for V147: refCnt = 2, refCntWtd = 1.50 New refCnts for V156: refCnt = 1, refCntWtd = 0.50 V156 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V148: refCnt = 2, refCntWtd = 1.50 STMT00314 ( ??? ... 0x01D ) [001476] ---XG+----- * JTRUE void [001475] J--XG+-N--- \--* NE int [001473] ---XG+----- +--* IND bool [002572] -----+----- | \--* ADD byref [001472] -----+----- | +--* LCL_VAR byref V01 arg1 [002571] -----+----- | \--* CNS_INT long 8 [001474] -----+----- \--* CNS_INT int 0 New refCnts for V01: refCnt = 4, refCntWtd = 3.50 *** marking local variables in block BB03 (weight=0.50) STMT00318 ( ??? ... 0x020 ) [002579] -A---+----- * COMMA void [002575] -A--------- +--* ASG byref [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 [002574] ----------- | \--* LCL_VAR byref V155 tmp115 [002578] -A--------- \--* ASG int [002576] D------N--- +--* LCL_VAR int V150 tmp110 [002577] ----------- \--* LCL_VAR int V156 tmp116 New refCnts for V149: refCnt = 1, refCntWtd = 0.50 Marking EH Var V149 as a register candidate. New refCnts for V155: refCnt = 2, refCntWtd = 1 New refCnts for V150: refCnt = 1, refCntWtd = 0.50 V150 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V156: refCnt = 2, refCntWtd = 1 STMT00319 ( ??? ... ??? ) [001494] -A---+----- * ASG int [001493] D----+-N--- +--* LCL_VAR int V43 tmp3 [001489] -----+----- \--* CNS_INT int 0 New refCnts for V43: refCnt = 1, refCntWtd = 0.50 V43 needs explicit zero init. Disqualified as a single-def register candidate. *** marking local variables in block BB04 (weight=0.50) STMT00316 ( ??? ... 0x023 ) [002586] -A---+----- * COMMA void [002582] -A--------- +--* ASG byref [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 [002581] ----------- | \--* LCL_VAR byref V155 tmp115 [002585] -A--------- \--* ASG int [002583] D------N--- +--* LCL_VAR int V150 tmp110 [002584] ----------- \--* LCL_VAR int V156 tmp116 New refCnts for V149: refCnt = 2, refCntWtd = 1 V149 has multiple definitions. Disqualified as a single-def register candidate. New refCnts for V155: refCnt = 3, refCntWtd = 1.50 New refCnts for V150: refCnt = 2, refCntWtd = 1 New refCnts for V156: refCnt = 3, refCntWtd = 1.50 STMT00317 ( ??? ... ??? ) [001487] -A---+----- * ASG int [001486] D----+-N--- +--* LCL_VAR int V43 tmp3 [001482] -----+----- \--* CNS_INT int 1 New refCnts for V43: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB05 (weight=0.50) STMT00006 ( ??? ... 0x025 ) [002593] -A---+----- * COMMA void [002589] -A--------- +--* ASG byref [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 [002588] ----------- | \--* LCL_VAR byref V147 tmp107 [002592] -A--------- \--* ASG int [002590] D------N--- +--* LCL_VAR int V150 tmp110 [002591] ----------- \--* LCL_VAR int V148 tmp108 New refCnts for V149: refCnt = 3, refCntWtd = 1.50 New refCnts for V147: refCnt = 3, refCntWtd = 2 New refCnts for V150: refCnt = 3, refCntWtd = 1.50 New refCnts for V148: refCnt = 3, refCntWtd = 2 STMT00007 ( ??? ... ??? ) [000026] -A---+----- * ASG int [000025] D----+-N--- +--* LCL_VAR int V43 tmp3 [000021] -----+----- \--* CNS_INT int 2 New refCnts for V43: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB06 (weight=1 ) STMT00008 ( ??? ... 0x02B ) [000034] -ACXG+----- * ASG int [000033] D----+-N--- +--* LCL_VAR int V15 loc11 [000030] --CXG+----- \--* CALL r2r_ind int [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 [000029] -----+----- arg2 in x2 +--* LCL_VAR int V43 tmp3 [002594] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn New refCnts for V15: refCnt = 1, refCntWtd = 1 V15 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V149: refCnt = 4, refCntWtd = 2.50 New refCnts for V150: refCnt = 4, refCntWtd = 2.50 New refCnts for V43: refCnt = 4, refCntWtd = 2.50 *** marking local variables in block BB07 (weight=8 ) STMT00009 ( 0x02D[E-] ... 0x02E ) [000037] -A---+----- * ASG int [000036] D----+-N--- +--* LCL_VAR int V04 loc0 [000035] -----+----- \--* CNS_INT int 0 New refCnts for V04: refCnt = 1, refCntWtd = 8 V04 needs explicit zero init. Disqualified as a single-def register candidate. STMT00010 ( 0x02F[E-] ... 0x030 ) [000040] -A---+----- * ASG int [000039] D----+-N--- +--* LCL_VAR int V05 loc1 [000038] -----+----- \--* CNS_INT int -1 New refCnts for V05: refCnt = 1, refCntWtd = 8 V05 needs explicit zero init. Disqualified as a single-def register candidate. STMT00011 ( 0x031[E-] ... 0x036 ) [000043] -A---+----- * ASG int [000042] D----+-N--- +--* LCL_VAR int V06 loc2 [000041] -----+----- \--* CNS_INT int 0x7FFFFFFF New refCnts for V06: refCnt = 1, refCntWtd = 8 V06 needs explicit zero init. Disqualified as a single-def register candidate. STMT00012 ( 0x037[E-] ... 0x038 ) [000046] -A---+----- * ASG int [000045] D----+-N--- +--* LCL_VAR int V07 loc3 [000044] -----+----- \--* CNS_INT int 0 New refCnts for V07: refCnt = 1, refCntWtd = 8 V07 needs explicit zero init. Disqualified as a single-def register candidate. STMT00013 ( 0x039[E-] ... 0x03A ) [000049] -A---+----- * ASG int [000048] D----+-N--- +--* LCL_VAR int V09 loc5 [002598] -----+----- \--* CNS_INT int 0 New refCnts for V09: refCnt = 1, refCntWtd = 8 V09 needs explicit zero init. Disqualified as a single-def register candidate. STMT00014 ( 0x03C[E-] ... 0x03D ) [000052] -A---+----- * ASG int [000051] D----+-N--- +--* LCL_VAR int V10 loc6 [000050] -----+----- \--* CNS_INT int -1 New refCnts for V10: refCnt = 1, refCntWtd = 8 V10 needs explicit zero init. Disqualified as a single-def register candidate. STMT00015 ( 0x03F[E-] ... 0x040 ) [000055] -A---+----- * ASG int [000054] D----+-N--- +--* LCL_VAR int V12 loc8 [002599] -----+----- \--* CNS_INT int 0 New refCnts for V12: refCnt = 1, refCntWtd = 8 V12 needs explicit zero init. Disqualified as a single-def register candidate. STMT00016 ( 0x042[E-] ... 0x043 ) [000058] -A---+----- * ASG int [000057] D----+-N--- +--* LCL_VAR int V13 loc9 [000056] -----+----- \--* CNS_INT int 0 New refCnts for V13: refCnt = 1, refCntWtd = 8 V13 needs explicit zero init. Disqualified as a single-def register candidate. STMT00017 ( 0x045[E-] ... 0x047 ) [000061] -A---+----- * ASG int [000060] D----+-N--- +--* LCL_VAR int V16 loc12 [000059] -----+----- \--* LCL_VAR int V15 loc11 New refCnts for V16: refCnt = 1, refCntWtd = 8 V16 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V15: refCnt = 2, refCntWtd = 9 STMT00321 ( 0x049[E-] ... ??? ) [002606] -A---+----- * COMMA void [002602] -A--------- +--* ASG byref [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002605] -A--------- \--* ASG int [002603] D------N--- +--* LCL_VAR int V158 tmp118 [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V157: refCnt = 1, refCntWtd = 8 V157 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V02: refCnt = 3, refCntWtd = 10 New refCnts for V158: refCnt = 1, refCntWtd = 8 V158 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V02: refCnt = 4, refCntWtd = 18 STMT00019 ( 0x049[E-] ... ??? ) [000068] -A---+----- * ASG byref [000067] D----+-N--- +--* LCL_VAR byref V23 loc19 [001512] -----+----- \--* LCL_VAR byref V157 tmp117 New refCnts for V23: refCnt = 1, refCntWtd = 8 V23 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V157: refCnt = 2, refCntWtd = 16 STMT00020 ( 0x051[E-] ... 0x054 ) [000072] -A---+----- * ASG long [000071] D----+-N--- +--* LCL_VAR long V22 loc18 [002611] -A---+----- \--* COMMA long [002608] -A---+----- +--* ASG long [002607] D----+-N--- | +--* LCL_VAR long V168 tmp128 [000069] -----+----- | \--* LCL_VAR byref V157 tmp117 [002609] -----+----- \--* LCL_VAR long V168 tmp128 New refCnts for V22: refCnt = 1, refCntWtd = 8 V22 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V168: refCnt = 1, refCntWtd = 16 V168 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V157: refCnt = 3, refCntWtd = 24 New refCnts for V168: refCnt = 2, refCntWtd = 32 *** marking local variables in block BB08 (weight=8 ) STMT00266 ( 0x05B[E-] ... 0x05F ) [001229] -----+----- * JTRUE void [001228] N----+-N-U- \--* GT int [001226] -----+----- +--* LCL_VAR int V18 loc14 [001227] -----+----- \--* CNS_INT int 69 New refCnts for V18: refCnt = 1, refCntWtd = 8 *** marking local variables in block BB09 (weight=8 ) STMT00289 ( 0x061[E-] ... 0x066 ) [001364] -----+----- * SWITCH void [001363] -----+----- \--* ADD int [001361] -----+----- +--* LCL_VAR int V18 loc14 [001362] -----+----- \--* CNS_INT int -34 New refCnts for V18: refCnt = 2, refCntWtd = 16 *** marking local variables in block BB10 (weight=8 ) STMT00290 ( 0x083[E-] ... 0x088 ) [001368] -----+----- * SWITCH void [001367] -----+----- \--* ADD int [001365] -----+----- +--* LCL_VAR int V18 loc14 [001366] -----+----- \--* CNS_INT int -44 New refCnts for V18: refCnt = 3, refCntWtd = 24 *** marking local variables in block BB11 (weight=8 ) STMT00291 ( 0x0A1[E-] ... 0x0A5 ) [001372] -----+----- * JTRUE void [001371] J----+-N--- \--* EQ int [001369] -----+----- +--* LCL_VAR int V18 loc14 [001370] -----+----- \--* CNS_INT int 69 New refCnts for V18: refCnt = 4, refCntWtd = 32 *** marking local variables in block BB12 (weight=8 ) *** marking local variables in block BB13 (weight=8 ) STMT00267 ( 0x0AF[E-] ... 0x0B3 ) [001233] -----+----- * JTRUE void [001232] J----+-N--- \--* EQ int [001230] -----+----- +--* LCL_VAR int V18 loc14 [001231] -----+----- \--* CNS_INT int 92 New refCnts for V18: refCnt = 5, refCntWtd = 40 *** marking local variables in block BB14 (weight=8 ) STMT00272 ( 0x0B8[E-] ... 0x0BC ) [001260] -----+----- * JTRUE void [001259] J----+-N--- \--* EQ int [001257] -----+----- +--* LCL_VAR int V18 loc14 [001258] -----+----- \--* CNS_INT int 101 New refCnts for V18: refCnt = 6, refCntWtd = 48 *** marking local variables in block BB15 (weight=8 ) STMT00287 ( 0x0C1[E-] ... 0x0C8 ) [001355] -----+----- * JTRUE void [001354] J----+-N--- \--* NE int [001352] -----+----- +--* LCL_VAR int V18 loc14 [001353] -----+----- \--* CNS_INT int 0x2030 New refCnts for V18: refCnt = 7, refCntWtd = 56 *** marking local variables in block BB16 (weight=8 ) STMT00288 ( 0x137[E-] ... 0x13B ) [001360] -A---+----- * ASG int [001359] D----+-N--- +--* LCL_VAR int V13 loc9 [001358] -----+----- \--* ADD int [001356] -----+----- +--* LCL_VAR int V13 loc9 [001357] -----+----- \--* CNS_INT int 3 New refCnts for V13: refCnt = 2, refCntWtd = 16 New refCnts for V13: refCnt = 3, refCntWtd = 24 *** marking local variables in block BB17 (weight=8 ) STMT00307 ( 0x0CF[E-] ... 0x0D2 ) [001434] -A---+----- * ASG int [001433] D----+-N--- +--* LCL_VAR int V04 loc0 [001432] -----+----- \--* ADD int [001430] -----+----- +--* LCL_VAR int V04 loc0 [001431] -----+----- \--* CNS_INT int 1 New refCnts for V04: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 3, refCntWtd = 24 *** marking local variables in block BB18 (weight=8 ) STMT00292 ( 0x0D8[E-] ... 0x0DE ) [001376] -----+----- * JTRUE void [001375] N----+-N-U- \--* NE int [001373] -----+----- +--* LCL_VAR int V06 loc2 [001374] -----+----- \--* CNS_INT int 0x7FFFFFFF New refCnts for V06: refCnt = 2, refCntWtd = 16 *** marking local variables in block BB19 (weight=8 ) STMT00295 ( 0x0E0[E-] ... 0x0E1 ) [001387] -A---+----- * ASG int [001386] D----+-N--- +--* LCL_VAR int V06 loc2 [001385] -----+----- \--* LCL_VAR int V04 loc0 New refCnts for V06: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 4, refCntWtd = 32 *** marking local variables in block BB20 (weight=8 ) STMT00293 ( 0x0E2[E-] ... 0x0E5 ) [001381] -A---+----- * ASG int [001380] D----+-N--- +--* LCL_VAR int V04 loc0 [001379] -----+----- \--* ADD int [001377] -----+----- +--* LCL_VAR int V04 loc0 [001378] -----+----- \--* CNS_INT int 1 New refCnts for V04: refCnt = 5, refCntWtd = 40 New refCnts for V04: refCnt = 6, refCntWtd = 48 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) [001384] -A---+----- * ASG int [001383] D----+-N--- +--* LCL_VAR int V07 loc3 [001382] -----+----- \--* LCL_VAR int V04 loc0 New refCnts for V07: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 7, refCntWtd = 56 *** marking local variables in block BB21 (weight=8 ) STMT00296 ( 0x0ED[E-] ... 0x0EF ) [001391] -----+----- * JTRUE void [001390] J----+-N--- \--* GE int [001388] -----+----- +--* LCL_VAR int V05 loc1 [001389] -----+----- \--* CNS_INT int 0 New refCnts for V05: refCnt = 2, refCntWtd = 16 *** marking local variables in block BB22 (weight=8 ) STMT00297 ( 0x0F4[E-] ... 0x0F5 ) [001394] -A---+----- * ASG int [001393] D----+-N--- +--* LCL_VAR int V05 loc1 [001392] -----+----- \--* LCL_VAR int V04 loc0 New refCnts for V05: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 8, refCntWtd = 64 *** marking local variables in block BB23 (weight=8 ) STMT00298 ( 0x0FB[E-] ... 0x0FD ) [001398] -----+----- * JTRUE void [001397] J----+-N--- \--* LE int [001395] -----+----- +--* LCL_VAR int V04 loc0 [001396] -----+----- \--* CNS_INT int 0 New refCnts for V04: refCnt = 9, refCntWtd = 72 *** marking local variables in block BB24 (weight=8 ) STMT00299 ( 0x102[E-] ... 0x104 ) [001402] -----+----- * JTRUE void [001401] J----+-N--- \--* GE int [001399] -----+----- +--* LCL_VAR int V05 loc1 [001400] -----+----- \--* CNS_INT int 0 New refCnts for V05: refCnt = 4, refCntWtd = 32 *** marking local variables in block BB25 (weight=8 ) STMT00300 ( 0x109[E-] ... 0x10C ) [001406] -----+----- * JTRUE void [001405] J----+-N--- \--* LT int [001403] -----+----- +--* LCL_VAR int V10 loc6 [001404] -----+----- \--* CNS_INT int 0 New refCnts for V10: refCnt = 2, refCntWtd = 16 *** marking local variables in block BB26 (weight=8 ) STMT00303 ( 0x10E[E-] ... 0x111 ) [001416] -----+----- * JTRUE void [001415] N----+-N-U- \--* NE int [001413] -----+----- +--* LCL_VAR int V10 loc6 [001414] -----+----- \--* LCL_VAR int V04 loc0 New refCnts for V10: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 10, refCntWtd = 80 *** marking local variables in block BB27 (weight=8 ) STMT00305 ( 0x113[E-] ... 0x117 ) [001424] -A---+----- * ASG int [001423] D----+-N--- +--* LCL_VAR int V11 loc7 [001422] -----+----- \--* ADD int [001420] -----+----- +--* LCL_VAR int V11 loc7 [001421] -----+----- \--* CNS_INT int 1 New refCnts for V11: refCnt = 2, refCntWtd = 9 New refCnts for V11: refCnt = 3, refCntWtd = 17 *** marking local variables in block BB28 (weight=8 ) STMT00304 ( 0x11E[E-] ... 0x11F ) [001419] -A---+----- * ASG int [001418] D----+-N--- +--* LCL_VAR int V12 loc8 [002612] -----+----- \--* CNS_INT int 1 New refCnts for V12: refCnt = 2, refCntWtd = 16 *** marking local variables in block BB29 (weight=8 ) STMT00301 ( 0x121[E-] ... 0x122 ) [001409] -A---+----- * ASG int [001408] D----+-N--- +--* LCL_VAR int V10 loc6 [001407] -----+----- \--* LCL_VAR int V04 loc0 New refCnts for V10: refCnt = 4, refCntWtd = 32 New refCnts for V04: refCnt = 11, refCntWtd = 88 STMT00302 ( 0x124[E-] ... 0x125 ) [001412] -A---+----- * ASG int [001411] D----+-N--- +--* LCL_VAR int V11 loc7 [001410] -----+----- \--* CNS_INT int 1 New refCnts for V11: refCnt = 4, refCntWtd = 25 *** marking local variables in block BB30 (weight=8 ) STMT00306 ( 0x12C[E-] ... 0x130 ) [001429] -A---+----- * ASG int [001428] D----+-N--- +--* LCL_VAR int V13 loc9 [001427] -----+----- \--* ADD int [001425] -----+----- +--* LCL_VAR int V13 loc9 [001426] -----+----- \--* CNS_INT int 2 New refCnts for V13: refCnt = 4, refCntWtd = 32 New refCnts for V13: refCnt = 5, refCntWtd = 40 *** marking local variables in block BB31 (weight=64 ) STMT00309 ( 0x142[E-] ... ??? ) [001441] -----+----- * JTRUE void [001440] J----+-N--- \--* GE int [001435] -----+----- +--* LCL_VAR int V16 loc12 [001518] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 2, refCntWtd = 72 New refCnts for V02: refCnt = 5, refCntWtd = 82 *** marking local variables in block BB32 (weight=64 ) STMT00310 ( 0x150[E-] ... 0x159 ) [001452] ---XG+----- * JTRUE void [001451] J--XG+-N--- \--* EQ int [001449] ---XG+----- +--* IND ushort [001448] -----+----- | \--* ADD long [001442] -----+----- | +--* LCL_VAR long V22 loc18 [001447] -----+----- | \--* LSH long [001444] -----+----- | +--* CAST long <- int [001443] -----+----- | | \--* LCL_VAR int V16 loc12 [001446] -----+----- | \--* CNS_INT long 1 [001450] -----+----- \--* CNS_INT int 0 New refCnts for V22: refCnt = 2, refCntWtd = 72 New refCnts for V16: refCnt = 3, refCntWtd = 136 *** marking local variables in block BB33 (weight=64 ) STMT00312 ( 0x15E[E-] ... 0x165 ) [001461] -A---+----- * ASG int [001460] D----+-N--- +--* LCL_VAR int V74 tmp34 [001454] -----+----- \--* LCL_VAR int V16 loc12 New refCnts for V74: refCnt = 1, refCntWtd = 128 V74 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 4, refCntWtd = 200 STMT00311 ( 0x15E[E-] ... ??? ) [001459] -A---+----- * ASG int [001458] D----+-N--- +--* LCL_VAR int V16 loc12 [001457] -----+----- \--* ADD int [001455] -----+----- +--* LCL_VAR int V16 loc12 [001456] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 5, refCntWtd = 264 New refCnts for V16: refCnt = 6, refCntWtd = 328 STMT00313 ( ??? ... 0x16E ) [001471] ---XG+----- * JTRUE void [001470] N--XG+-N-U- \--* NE int [001468] ---XG+----- +--* IND ushort [001467] -----+----- | \--* ADD long [001453] -----+----- | +--* LCL_VAR long V22 loc18 [001466] -----+----- | \--* LSH long [001463] -----+----- | +--* CAST long <- int [001462] -----+----- | | \--* LCL_VAR int V74 tmp34 [001465] -----+----- | \--* CNS_INT long 1 [001469] -----+----- \--* LCL_VAR int V18 loc14 New refCnts for V22: refCnt = 3, refCntWtd = 136 New refCnts for V74: refCnt = 2, refCntWtd = 256 New refCnts for V18: refCnt = 8, refCntWtd = 120 *** marking local variables in block BB34 (weight=8 ) *** marking local variables in block BB35 (weight=8 ) STMT00269 ( 0x175[E-] ... ??? ) [001240] -----+----- * JTRUE void [001239] J----+-N--- \--* GE int [001234] -----+----- +--* LCL_VAR int V16 loc12 [001522] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 7, refCntWtd = 336 New refCnts for V02: refCnt = 6, refCntWtd = 90 *** marking local variables in block BB36 (weight=8 ) STMT00270 ( 0x183[E-] ... 0x18C ) [001251] ---XG+----- * JTRUE void [001250] J--XG+-N--- \--* EQ int [001248] ---XG+----- +--* IND ushort [001247] -----+----- | \--* ADD long [001241] -----+----- | +--* LCL_VAR long V22 loc18 [001246] -----+----- | \--* LSH long [001243] -----+----- | +--* CAST long <- int [001242] -----+----- | | \--* LCL_VAR int V16 loc12 [001245] -----+----- | \--* CNS_INT long 1 [001249] -----+----- \--* CNS_INT int 0 New refCnts for V22: refCnt = 4, refCntWtd = 144 New refCnts for V16: refCnt = 8, refCntWtd = 344 *** marking local variables in block BB37 (weight=8 ) STMT00271 ( 0x18E[E-] ... 0x192 ) [001256] -A---+----- * ASG int [001255] D----+-N--- +--* LCL_VAR int V16 loc12 [001254] -----+----- \--* ADD int [001252] -----+----- +--* LCL_VAR int V16 loc12 [001253] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 9, refCntWtd = 352 New refCnts for V16: refCnt = 10, refCntWtd = 360 *** marking local variables in block BB38 (weight=8 ) STMT00274 ( 0x196[E-] ... ??? ) [001267] -----+----- * JTRUE void [001266] J----+-N--- \--* GE int [001261] -----+----- +--* LCL_VAR int V16 loc12 [001526] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 11, refCntWtd = 368 New refCnts for V02: refCnt = 7, refCntWtd = 98 *** marking local variables in block BB39 (weight=8 ) STMT00286 ( 0x1A1[E-] ... 0x1AC ) [001351] ---XG+----- * JTRUE void [001350] J--XG+-N--- \--* EQ int [001348] ---XG+----- +--* IND ushort [001347] -----+----- | \--* ADD long [001341] -----+----- | +--* LCL_VAR long V22 loc18 [001346] -----+----- | \--* LSH long [001343] -----+----- | +--* CAST long <- int [001342] -----+----- | | \--* LCL_VAR int V16 loc12 [001345] -----+----- | \--* CNS_INT long 1 [001349] -----+----- \--* CNS_INT int 48 New refCnts for V22: refCnt = 5, refCntWtd = 152 New refCnts for V16: refCnt = 12, refCntWtd = 376 *** marking local variables in block BB40 (weight=8 ) STMT00276 ( 0x1AE[E-] ... ??? ) [001276] -----+----- * JTRUE void [001275] J----+-N--- \--* GE int [001270] -----+----- +--* ADD int [001268] -----+----- | +--* LCL_VAR int V16 loc12 [001269] -----+----- | \--* CNS_INT int 1 [001530] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 13, refCntWtd = 384 New refCnts for V02: refCnt = 8, refCntWtd = 106 *** marking local variables in block BB41 (weight=8 ) STMT00277 ( 0x1BB[E-] ... 0x1C6 ) [001287] ---XG+----- * JTRUE void [001286] J--XG+-N--- \--* EQ int [001284] ---XG+----- +--* IND ushort [001283] -----+----- | \--* ADD long [001277] -----+----- | +--* LCL_VAR long V22 loc18 [001282] -----+----- | \--* LSH long [001279] -----+----- | +--* CAST long <- int [001278] -----+----- | | \--* LCL_VAR int V16 loc12 [001281] -----+----- | \--* CNS_INT long 1 [001285] -----+----- \--* CNS_INT int 43 New refCnts for V22: refCnt = 6, refCntWtd = 160 New refCnts for V16: refCnt = 14, refCntWtd = 392 *** marking local variables in block BB42 (weight=8 ) STMT00285 ( 0x1C8[E-] ... 0x1D3 ) [001340] ---XG+----- * JTRUE void [001339] N--XG+-N-U- \--* NE int [001337] ---XG+----- +--* IND ushort [001336] -----+----- | \--* ADD long [001330] -----+----- | +--* LCL_VAR long V22 loc18 [001335] -----+----- | \--* LSH long [001332] -----+----- | +--* CAST long <- int [001331] -----+----- | | \--* LCL_VAR int V16 loc12 [001334] -----+----- | \--* CNS_INT long 1 [001338] -----+----- \--* CNS_INT int 45 New refCnts for V22: refCnt = 7, refCntWtd = 168 New refCnts for V16: refCnt = 15, refCntWtd = 400 *** marking local variables in block BB43 (weight=8 ) STMT00278 ( 0x1D5[E-] ... 0x1E2 ) [001300] ---XG+----- * JTRUE void [001299] N--XG+-N-U- \--* NE int [001297] ---XG+----- +--* IND ushort [001296] -----+----- | \--* ADD long [001288] -----+----- | +--* LCL_VAR long V22 loc18 [001295] -----+----- | \--* LSH long [001292] -----+----- | +--* CAST long <- int [001291] -----+----- | | \--* ADD int [001289] -----+----- | | +--* LCL_VAR int V16 loc12 [001290] -----+----- | | \--* CNS_INT int 1 [001294] -----+----- | \--* CNS_INT long 1 [001298] -----+----- \--* CNS_INT int 48 New refCnts for V22: refCnt = 8, refCntWtd = 176 New refCnts for V16: refCnt = 16, refCntWtd = 408 *** marking local variables in block BB44 (weight=64 ) STMT00279 ( 0x1E4[E-] ... 0x1E9 ) [001305] -A---+----- * ASG int [001304] D----+-N--- +--* LCL_VAR int V73 tmp33 [001303] -----+----- \--* ADD int [001301] -----+----- +--* LCL_VAR int V16 loc12 [001302] -----+----- \--* CNS_INT int 1 New refCnts for V73: refCnt = 1, refCntWtd = 128 V73 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 17, refCntWtd = 472 STMT00280 ( ??? ... ??? ) [001309] -A---+----- * ASG int [001308] D----+-N--- +--* LCL_VAR int V16 loc12 [001307] -----+----- \--* LCL_VAR int V73 tmp33 New refCnts for V16: refCnt = 18, refCntWtd = 536 New refCnts for V73: refCnt = 2, refCntWtd = 256 STMT00282 ( ??? ... ??? ) [001315] -----+----- * JTRUE void [001314] J----+-N--- \--* GE int [001306] -----+----- +--* LCL_VAR int V73 tmp33 [001534] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V73: refCnt = 3, refCntWtd = 384 New refCnts for V02: refCnt = 9, refCntWtd = 170 *** marking local variables in block BB45 (weight=64 ) STMT00284 ( 0x1F4[E-] ... 0x1FF ) [001329] ---XG+----- * JTRUE void [001328] J--XG+-N--- \--* EQ int [001326] ---XG+----- +--* IND ushort [001325] -----+----- | \--* ADD long [001319] -----+----- | +--* LCL_VAR long V22 loc18 [001324] -----+----- | \--* LSH long [001321] -----+----- | +--* CAST long <- int [001320] -----+----- | | \--* LCL_VAR int V16 loc12 [001323] -----+----- | \--* CNS_INT long 1 [001327] -----+----- \--* CNS_INT int 48 New refCnts for V22: refCnt = 9, refCntWtd = 240 New refCnts for V16: refCnt = 19, refCntWtd = 600 *** marking local variables in block BB46 (weight=8 ) STMT00283 ( 0x201[E-] ... 0x202 ) [001318] -A---+----- * ASG int [001317] D----+-N--- +--* LCL_VAR int V09 loc5 [002613] -----+----- \--* CNS_INT int 1 New refCnts for V09: refCnt = 2, refCntWtd = 16 *** marking local variables in block BB47 (weight=64 ) STMT00022 ( 0x204[E-] ... ??? ) [000079] -----+----- * JTRUE void [000078] J----+-N--- \--* GE int [000073] -----+----- +--* LCL_VAR int V16 loc12 [001538] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 20, refCntWtd = 664 New refCnts for V02: refCnt = 10, refCntWtd = 234 *** marking local variables in block BB48 (weight=16 ) STMT00261 ( 0x20F[E-] ... 0x216 ) [001205] -A---+----- * ASG int [001204] D----+-N--- +--* LCL_VAR int V71 tmp31 [001198] -----+----- \--* LCL_VAR int V16 loc12 New refCnts for V71: refCnt = 1, refCntWtd = 32 V71 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 21, refCntWtd = 680 STMT00260 ( 0x20F[E-] ... ??? ) [001203] -A---+----- * ASG int [001202] D----+-N--- +--* LCL_VAR int V16 loc12 [001201] -----+----- \--* ADD int [001199] -----+----- +--* LCL_VAR int V16 loc12 [001200] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 22, refCntWtd = 696 New refCnts for V16: refCnt = 23, refCntWtd = 712 STMT00262 ( ??? ... 0x21E ) [001214] -A-XG+----- * ASG int [001213] D----+-N--- +--* LCL_VAR int V72 tmp32 [001212] ---XG+----- \--* IND ushort [001211] -----+----- \--* ADD long [001197] -----+----- +--* LCL_VAR long V22 loc18 [001210] -----+----- \--* LSH long [001207] -----+----- +--* CAST long <- int [001206] -----+----- | \--* LCL_VAR int V71 tmp31 [001209] -----+----- \--* CNS_INT long 1 New refCnts for V72: refCnt = 1, refCntWtd = 32 V72 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V22: refCnt = 10, refCntWtd = 256 New refCnts for V71: refCnt = 2, refCntWtd = 64 STMT00263 ( ??? ... ??? ) [001218] -A---+----- * ASG int [001217] D----+-N--- +--* LCL_VAR int V18 loc14 [001216] -----+----- \--* LCL_VAR int V72 tmp32 New refCnts for V18: refCnt = 9, refCntWtd = 136 V18 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V72: refCnt = 2, refCntWtd = 64 STMT00264 ( ??? ... 0x220 ) [001221] -----+----- * JTRUE void [001220] J----+-N--- \--* EQ int [001215] -----+----- +--* LCL_VAR int V72 tmp32 [001219] -----+----- \--* CNS_INT int 0 New refCnts for V72: refCnt = 3, refCntWtd = 96 *** marking local variables in block BB49 (weight=16 ) STMT00265 ( 0x222[E-] ... 0x226 ) [001225] -----+----- * JTRUE void [001224] N----+-N-U- \--* NE int [001222] -----+----- +--* LCL_VAR int V18 loc14 [001223] -----+----- \--* CNS_INT int 59 New refCnts for V18: refCnt = 10, refCntWtd = 152 *** marking local variables in block BB50 (weight=8 ) STMT00023 ( 0x22B[E-] ... 0x22D ) [000083] -A---+----- * ASG byref [000082] D----+-N--- +--* LCL_VAR byref V23 loc19 [000081] -----+----- \--* CNS_INT long 0 New refCnts for V23: refCnt = 2, refCntWtd = 16 STMT00024 ( 0x22F[E-] ... 0x231 ) [000087] -----+----- * JTRUE void [000086] J----+-N--- \--* GE int [000084] -----+----- +--* LCL_VAR int V05 loc1 [000085] -----+----- \--* CNS_INT int 0 New refCnts for V05: refCnt = 5, refCntWtd = 40 *** marking local variables in block BB51 (weight=2 ) STMT00259 ( 0x233[E-] ... 0x234 ) [001196] -A---+----- * ASG int [001195] D----+-N--- +--* LCL_VAR int V05 loc1 [001194] -----+----- \--* LCL_VAR int V04 loc0 New refCnts for V05: refCnt = 6, refCntWtd = 42 New refCnts for V04: refCnt = 12, refCntWtd = 90 *** marking local variables in block BB52 (weight=8 ) STMT00025 ( 0x235[E-] ... 0x238 ) [000091] -----+----- * JTRUE void [000090] J----+-N--- \--* LT int [000088] -----+----- +--* LCL_VAR int V10 loc6 [000089] -----+----- \--* CNS_INT int 0 New refCnts for V10: refCnt = 5, refCntWtd = 40 *** marking local variables in block BB53 (weight=2 ) STMT00256 ( 0x23A[E-] ... 0x23D ) [001183] -----+----- * JTRUE void [001182] N----+-N-U- \--* NE int [001180] -----+----- +--* LCL_VAR int V10 loc6 [001181] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V10: refCnt = 6, refCntWtd = 42 New refCnts for V05: refCnt = 7, refCntWtd = 44 *** marking local variables in block BB54 (weight=2 ) STMT00258 ( 0x23F[E-] ... 0x246 ) [001193] -A---+----- * ASG int [001192] D----+-N--- +--* LCL_VAR int V13 loc9 [001191] -----+----- \--* SUB int [001187] -----+----- +--* LCL_VAR int V13 loc9 [001190] -----+----- \--* MUL int [001188] -----+----- +--* LCL_VAR int V11 loc7 [001189] -----+----- \--* CNS_INT int 3 New refCnts for V13: refCnt = 6, refCntWtd = 42 New refCnts for V13: refCnt = 7, refCntWtd = 44 New refCnts for V11: refCnt = 5, refCntWtd = 27 *** marking local variables in block BB55 (weight=2 ) STMT00257 ( 0x24A[E-] ... 0x24B ) [001186] -A---+----- * ASG int [001185] D----+-N--- +--* LCL_VAR int V12 loc8 [002615] -----+----- \--* CNS_INT int 1 New refCnts for V12: refCnt = 3, refCntWtd = 18 *** marking local variables in block BB56 (weight=8 ) STMT00026 ( 0x24D[E-] ... 0x250 ) [000096] ---XG+----- * JTRUE void [000095] J--XG+-N--- \--* EQ int [000093] ---XG+----- +--* IND ubyte [000092] -----+----- | \--* LCL_VAR long V17 loc13 [000094] -----+----- \--* CNS_INT int 0 New refCnts for V17: refCnt = 2, refCntWtd = 9 *** marking local variables in block BB57 (weight=4 ) STMT00245 ( 0x252[E-] ... 0x25D ) [001129] -A-XG+----- * ASG byref [001128] D----+-N--- +--* LCL_VAR byref V69 tmp29 [002621] ---X-+-N--- \--* COMMA byref [002617] ---X-+----- +--* NULLCHECK byte [002616] -----+----- | \--* LCL_VAR byref V01 arg1 [002620] -----+----- \--* ADD byref [002618] -----+----- +--* LCL_VAR byref V01 arg1 [002619] -----+----- \--* CNS_INT long 4 New refCnts for V69: refCnt = 1, refCntWtd = 8 V69 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V01: refCnt = 5, refCntWtd = 7.50 New refCnts for V01: refCnt = 6, refCntWtd = 11.50 STMT00246 ( ??? ... ??? ) [001136] -A-XG+----- * ASG int [001135] ---XG+-N--- +--* IND int [001130] -----+----- | \--* LCL_VAR byref V69 tmp29 [001134] ---XG+----- \--* ADD int [001132] ---XG+----- +--* IND int [001131] -----+----- | \--* LCL_VAR byref V69 tmp29 [001133] -----+----- \--* LCL_VAR int V13 loc9 New refCnts for V69: refCnt = 2, refCntWtd = 16 New refCnts for V69: refCnt = 3, refCntWtd = 24 New refCnts for V13: refCnt = 8, refCntWtd = 48 STMT00247 ( 0x25E[E-] ... 0x260 ) [001140] -----+----- * JTRUE void [001139] J----+-N--- \--* NE int [001137] -----+----- +--* LCL_VAR int V09 loc5 [001138] -----+----- \--* CNS_INT int 0 New refCnts for V09: refCnt = 3, refCntWtd = 20 *** marking local variables in block BB58 (weight=2 ) STMT00255 ( 0x262[E-] ... 0x26C ) [001178] -A-XG+----- * ASG int [001177] D----+-N--- +--* LCL_VAR int V70 tmp30 [001176] ---XG+----- \--* SUB int [001174] ---XG+----- +--* ADD int [001172] ---XG+----- | +--* IND int [002623] -----+----- | | \--* ADD byref [001171] -----+----- | | +--* LCL_VAR byref V01 arg1 [002622] -----+----- | | \--* CNS_INT long 4 [001173] -----+----- | \--* LCL_VAR int V04 loc0 [001175] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V70: refCnt = 1, refCntWtd = 2 V70 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V01: refCnt = 7, refCntWtd = 13.50 New refCnts for V04: refCnt = 13, refCntWtd = 92 New refCnts for V05: refCnt = 8, refCntWtd = 46 *** marking local variables in block BB59 (weight=2 ) STMT00248 ( 0x26E[E-] ... 0x26E ) [001143] -A---+----- * ASG int [001142] D----+-N--- +--* LCL_VAR int V70 tmp30 [001141] -----+----- \--* LCL_VAR int V04 loc0 New refCnts for V70: refCnt = 2, refCntWtd = 4 New refCnts for V04: refCnt = 14, refCntWtd = 94 *** marking local variables in block BB60 (weight=4 ) STMT00250 ( 0x271[E-] ... 0x27D ) [001151] --CXG+----- * CALL r2r_ind void [001145] -----+----- arg2 in x1 +--* LCL_VAR int V70 tmp30 [001148] -----+----- arg1 in x0 +--* LCL_VAR byref V01 arg1 [002624] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn [001150] -----+----- arg3 in x2 \--* CNS_INT int 0 New refCnts for V70: refCnt = 3, refCntWtd = 8 New refCnts for V01: refCnt = 8, refCntWtd = 17.50 STMT00251 ( 0x27A[E-] ... ??? ) [001156] ---XG+----- * JTRUE void [001155] J--XG+-N--- \--* NE int [001153] ---XG+----- +--* IND ubyte [001152] -----+----- | \--* LCL_VAR long V17 loc13 [001154] -----+----- \--* CNS_INT int 0 New refCnts for V17: refCnt = 3, refCntWtd = 13 *** marking local variables in block BB61 (weight=4 ) STMT00252 ( 0x27F[E-] ... 0x286 ) [001163] -ACXG+----- * ASG int [001162] D----+-N--- +--* LCL_VAR int V16 loc12 [001159] --CXG+----- \--* CALL r2r_ind int [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] [002625] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn [001158] -----+----- arg2 in x2 \--* CNS_INT int 2 New refCnts for V16: refCnt = 24, refCntWtd = 716 New refCnts for V02: refCnt = 11, refCntWtd = 238 New refCnts for V02: refCnt = 12, refCntWtd = 242 STMT00253 ( 0x288[E-] ... 0x28C ) [001167] -----+----- * JTRUE void [001166] J----+-N--- \--* EQ int [001164] -----+----- +--* LCL_VAR int V16 loc12 [001165] -----+----- \--* LCL_VAR int V15 loc11 New refCnts for V16: refCnt = 25, refCntWtd = 720 New refCnts for V15: refCnt = 3, refCntWtd = 13 *** marking local variables in block BB62 (weight=4 ) STMT00254 ( 0x28E[E-] ... 0x290 ) [001170] -A---+----- * ASG int [001169] D----+-N--- +--* LCL_VAR int V15 loc11 [001168] -----+----- \--* LCL_VAR int V16 loc12 New refCnts for V15: refCnt = 4, refCntWtd = 17 New refCnts for V16: refCnt = 26, refCntWtd = 724 *** marking local variables in block BB63 (weight=0.50) STMT00027 ( 0x297[E-] ... 0x29E ) [000101] ---XG+----- * JTRUE void [000100] J--XG+-N--- \--* EQ int [000098] ---XG+----- +--* IND ubyte [002630] -----+----- | \--* ADD byref [000097] -----+----- | +--* LCL_VAR byref V01 arg1 [002629] -----+----- | \--* CNS_INT long 10 [000099] -----+----- \--* CNS_INT int 3 New refCnts for V01: refCnt = 9, refCntWtd = 18 *** marking local variables in block BB64 (weight=0.50) STMT00244 ( 0x2A0[E-] ... 0x2A2 ) [001125] -A-XG+----- * ASG bool [001124] ---XG+-N--- +--* IND bool [002632] -----+----- | \--* ADD byref [001122] -----+----- | +--* LCL_VAR byref V01 arg1 [002631] -----+----- | \--* CNS_INT long 8 [001123] -----+----- \--* CNS_INT int 0 New refCnts for V01: refCnt = 10, refCntWtd = 18.50 *** marking local variables in block BB65 (weight=0.50) STMT00028 ( 0x2A7[E-] ... 0x2A9 ) [000105] -A-XG+----- * ASG int [000104] ---XG+-N--- +--* IND int [002634] -----+----- | \--* ADD byref [000102] -----+----- | +--* LCL_VAR byref V01 arg1 [002633] -----+----- | \--* CNS_INT long 4 [000103] -----+----- \--* CNS_INT int 0 New refCnts for V01: refCnt = 11, refCntWtd = 19 *** marking local variables in block BB66 (weight=1 ) STMT00029 ( 0x2AE[E-] ... 0x2B0 ) [000109] -----+----- * JTRUE void [000108] J----+-N--- \--* LT int [000106] -----+----- +--* LCL_VAR int V06 loc2 [000107] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V06: refCnt = 4, refCntWtd = 25 New refCnts for V05: refCnt = 9, refCntWtd = 47 *** marking local variables in block BB67 (weight=0.50) STMT00243 ( 0x2B2[E-] ... 0x2B3 ) [001120] -A---+----- * ASG int [001119] D----+-N--- +--* LCL_VAR int V44 tmp4 [001118] -----+----- \--* CNS_INT int 0 New refCnts for V44: refCnt = 1, refCntWtd = 0.50 V44 needs explicit zero init. Disqualified as a single-def register candidate. *** marking local variables in block BB68 (weight=0.50) STMT00030 ( 0x2B5[E-] ... 0x2B7 ) [000114] -A---+----- * ASG int [000113] D----+-N--- +--* LCL_VAR int V44 tmp4 [000112] -----+----- \--* SUB int [000110] -----+----- +--* LCL_VAR int V05 loc1 [000111] -----+----- \--* LCL_VAR int V06 loc2 New refCnts for V44: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 10, refCntWtd = 47.50 New refCnts for V06: refCnt = 5, refCntWtd = 25.50 *** marking local variables in block BB69 (weight=1 ) STMT00031 ( ??? ... 0x2B8 ) [000118] -A---+----- * ASG int [000117] D----+-N--- +--* LCL_VAR int V06 loc2 [000116] -----+----- \--* LCL_VAR int V44 tmp4 New refCnts for V06: refCnt = 6, refCntWtd = 26.50 New refCnts for V44: refCnt = 3, refCntWtd = 2 STMT00032 ( 0x2B9[E-] ... 0x2BB ) [000122] -----+----- * JTRUE void [000121] J----+-N--- \--* GT int [000119] -----+----- +--* LCL_VAR int V07 loc3 [000120] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V07: refCnt = 3, refCntWtd = 17 New refCnts for V05: refCnt = 11, refCntWtd = 48.50 *** marking local variables in block BB70 (weight=0.50) STMT00242 ( 0x2BD[E-] ... 0x2BE ) [001116] -A---+----- * ASG int [001115] D----+-N--- +--* LCL_VAR int V45 tmp5 [001114] -----+----- \--* CNS_INT int 0 New refCnts for V45: refCnt = 1, refCntWtd = 0.50 V45 needs explicit zero init. Disqualified as a single-def register candidate. *** marking local variables in block BB71 (weight=0.50) STMT00033 ( 0x2C0[E-] ... 0x2C2 ) [000127] -A---+----- * ASG int [000126] D----+-N--- +--* LCL_VAR int V45 tmp5 [000125] -----+----- \--* SUB int [000123] -----+----- +--* LCL_VAR int V05 loc1 [000124] -----+----- \--* LCL_VAR int V07 loc3 New refCnts for V45: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 12, refCntWtd = 49 New refCnts for V07: refCnt = 4, refCntWtd = 17.50 *** marking local variables in block BB72 (weight=1 ) STMT00034 ( ??? ... 0x2C3 ) [000131] -A---+----- * ASG int [000130] D----+-N--- +--* LCL_VAR int V07 loc3 [000129] -----+----- \--* LCL_VAR int V45 tmp5 New refCnts for V07: refCnt = 5, refCntWtd = 18.50 New refCnts for V45: refCnt = 3, refCntWtd = 2 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) [000135] -----+----- * JTRUE void [000134] J----+-N--- \--* EQ int [000132] -----+----- +--* LCL_VAR int V09 loc5 [000133] -----+----- \--* CNS_INT int 0 New refCnts for V09: refCnt = 4, refCntWtd = 21 *** marking local variables in block BB73 (weight=0.50) STMT00240 ( 0x2C8[E-] ... 0x2C9 ) [001110] -A---+----- * ASG int [001109] D----+-N--- +--* LCL_VAR int V08 loc4 [001108] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V08: refCnt = 1, refCntWtd = 0.50 V08 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V05: refCnt = 13, refCntWtd = 49.50 STMT00241 ( 0x2CB[E-] ... 0x2CC ) [001113] -A---+----- * ASG int [001112] D----+-N--- +--* LCL_VAR int V14 loc10 [001111] -----+----- \--* CNS_INT int 0 New refCnts for V14: refCnt = 1, refCntWtd = 0.50 V14 needs explicit zero init. Disqualified as a single-def register candidate. *** marking local variables in block BB74 (weight=0.50) STMT00036 ( 0x2D0[E-] ... 0x2D7 ) [000140] ---XG+----- * JTRUE void [000139] J--XG+-N--- \--* GT int [000137] ---XG+----- +--* IND int [002636] -----+----- | \--* ADD byref [000136] -----+----- | +--* LCL_VAR byref V01 arg1 [002635] -----+----- | \--* CNS_INT long 4 [000138] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V01: refCnt = 12, refCntWtd = 19.50 New refCnts for V05: refCnt = 14, refCntWtd = 50 *** marking local variables in block BB75 (weight=0.50) STMT00239 ( 0x2D9[E-] ... 0x2DA ) [001106] -A---+----- * ASG int [001105] D----+-N--- +--* LCL_VAR int V46 tmp6 [001104] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V46: refCnt = 1, refCntWtd = 0.50 V46 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V05: refCnt = 15, refCntWtd = 50.50 *** marking local variables in block BB76 (weight=0.50) STMT00037 ( 0x2DC[E-] ... 0x2DD ) [000144] -A-XG+----- * ASG int [000143] D----+-N--- +--* LCL_VAR int V46 tmp6 [000142] ---XG+----- \--* IND int [002638] -----+----- \--* ADD byref [000141] -----+----- +--* LCL_VAR byref V01 arg1 [002637] -----+----- \--* CNS_INT long 4 New refCnts for V46: refCnt = 2, refCntWtd = 1 New refCnts for V01: refCnt = 13, refCntWtd = 20 *** marking local variables in block BB77 (weight=0.50) STMT00038 ( ??? ... 0x2E2 ) [000148] -A---+----- * ASG int [000147] D----+-N--- +--* LCL_VAR int V08 loc4 [000146] -----+----- \--* LCL_VAR int V46 tmp6 New refCnts for V08: refCnt = 2, refCntWtd = 1 New refCnts for V46: refCnt = 3, refCntWtd = 1.50 STMT00039 ( 0x2E4[E-] ... 0x2EC ) [000154] -A-XG+----- * ASG int [000153] D----+-N--- +--* LCL_VAR int V14 loc10 [000152] ---XG+----- \--* SUB int [000150] ---XG+----- +--* IND int [002640] -----+----- | \--* ADD byref [000149] -----+----- | +--* LCL_VAR byref V01 arg1 [002639] -----+----- | \--* CNS_INT long 4 [000151] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V14: refCnt = 2, refCntWtd = 1 New refCnts for V01: refCnt = 14, refCntWtd = 20.50 New refCnts for V05: refCnt = 16, refCntWtd = 51 *** marking local variables in block BB78 (weight=1 ) STMT00040 ( 0x2EE[E-] ... 0x2F0 ) [000157] -A---+----- * ASG int [000156] D----+-N--- +--* LCL_VAR int V16 loc12 [000155] -----+----- \--* LCL_VAR int V15 loc11 New refCnts for V16: refCnt = 27, refCntWtd = 725 New refCnts for V15: refCnt = 5, refCntWtd = 18 STMT00041 ( 0x2F2[E-] ... 0x2FD ) [002647] -A---+----- * COMMA void [002643] -A--------- +--* ASG byref [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 [002642] ----------- | \--* CNS_INT byref 0 [002646] -A--------- \--* ASG int [002644] D------N--- +--* LCL_VAR int V152 tmp112 [002645] ----------- \--* CNS_INT int 0 New refCnts for V151: refCnt = 1, refCntWtd = 1 Marking EH Var V151 as a register candidate. New refCnts for V152: refCnt = 1, refCntWtd = 1 V152 needs explicit zero init. Disqualified as a single-def register candidate. STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? [001553] -A---+----- * ASG byref [001552] D----+-N--- +--* LCL_VAR byref V151 tmp111 [001550] -----+----- \--* LCL_VAR_ADDR long V47 tmp7 New refCnts for V151: refCnt = 2, refCntWtd = 2 V151 has multiple definitions. Disqualified as a single-def register candidate. New refCnts for V47: refCnt = 1, refCntWtd = 1 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? [001558] -A---+----- * ASG int [001557] D----+-N--- +--* LCL_VAR int V152 tmp112 [001556] -----+----- \--* CNS_INT int 4 New refCnts for V152: refCnt = 2, refCntWtd = 2 STMT00044 ( 0x2FF[E-] ... 0x301 ) [002654] -A---+----- * COMMA void [002650] -A--------- +--* ASG byref [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 [002649] ----------- | \--* LCL_VAR byref V151 tmp111 [002653] -A--------- \--* ASG int [002651] D------N--- +--* LCL_VAR int V144 tmp104 [002652] ----------- \--* LCL_VAR int V152 tmp112 New refCnts for V143: refCnt = 1, refCntWtd = 1 Marking EH Var V143 as a register candidate. New refCnts for V151: refCnt = 3, refCntWtd = 3 New refCnts for V144: refCnt = 1, refCntWtd = 1 V144 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V152: refCnt = 3, refCntWtd = 3 STMT00045 ( 0x303[E-] ... 0x304 ) [000177] -A---+----- * ASG int [000176] D----+-N--- +--* LCL_VAR int V20 loc16 [000175] -----+----- \--* CNS_INT int -1 New refCnts for V20: refCnt = 1, refCntWtd = 1 V20 needs explicit zero init. Disqualified as a single-def register candidate. STMT00046 ( 0x306[E-] ... 0x308 ) [000181] -----+----- * JTRUE void [000180] J----+-N--- \--* EQ int [000178] -----+----- +--* LCL_VAR int V12 loc8 [000179] -----+----- \--* CNS_INT int 0 New refCnts for V12: refCnt = 4, refCntWtd = 19 *** marking local variables in block BB79 (weight=0.50) STMT00203 ( 0x30D[E-] ... ??? ) [000947] ---XG+----- * JTRUE void [000946] J--XG+-N--- \--* LE int [000944] ---XG+----- +--* ARR_LENGTH int [001570] ---XG+----- | \--* IND ref [002656] -----+----- | \--* ADD byref [000941] -----+----- | +--* LCL_VAR ref V03 arg3 [002655] -----+----- | \--* CNS_INT long 56 Fseq[] [000945] -----+----- \--* CNS_INT int 0 New refCnts for V03: refCnt = 1, refCntWtd = 0.50 *** marking local variables in block BB80 (weight=0.50) STMT00204 ( 0x31E[E-] ... 0x324 ) [000951] -A-XG+----- * ASG ref [000950] D----+-N--- +--* LCL_VAR ref V26 loc22 [000949] ---XG+----- \--* IND ref [002658] -----+----- \--* ADD byref [000948] -----+----- +--* LCL_VAR ref V03 arg3 [002657] -----+----- \--* CNS_INT long 8 Fseq[] New refCnts for V26: refCnt = 1, refCntWtd = 0.50 Marking EH Var V26 as a register candidate. New refCnts for V03: refCnt = 2, refCntWtd = 1 STMT00205 ( 0x326[E-] ... 0x327 ) [000954] -A---+----- * ASG int [000953] D----+-N--- +--* LCL_VAR int V27 loc23 [000952] -----+----- \--* CNS_INT int 0 New refCnts for V27: refCnt = 1, refCntWtd = 0.50 V27 needs explicit zero init. Disqualified as a single-def register candidate. STMT00206 ( 0x329[E-] ... 0x32A ) [000957] -A---+----- * ASG int [000956] D----+-N--- +--* LCL_VAR int V28 loc24 [000955] -----+----- \--* CNS_INT int 0 New refCnts for V28: refCnt = 1, refCntWtd = 0.50 V28 needs explicit zero init. Disqualified as a single-def register candidate. STMT00207 ( 0x32C[E-] ... 0x330 ) [000961] -A-X-+----- * ASG int [000960] D----+-N--- +--* LCL_VAR int V29 loc25 [000959] ---X-+----- \--* ARR_LENGTH int [000958] -----+----- \--* LCL_VAR ref V26 loc22 New refCnts for V29: refCnt = 1, refCntWtd = 0.50 V29 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V26: refCnt = 2, refCntWtd = 1 STMT00208 ( 0x332[E-] ... 0x334 ) [000965] -----+----- * JTRUE void [000964] J----+-N--- \--* EQ int [000962] -----+----- +--* LCL_VAR int V29 loc25 [000963] -----+----- \--* CNS_INT int 0 New refCnts for V29: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB81 (weight=0.50) STMT00238 ( 0x336[E-] ... 0x33B ) [001103] -A-XG+----- * ASG int [001102] D----+-N--- +--* LCL_VAR int V28 loc24 [002670] ---XG+----- \--* COMMA int [002662] ---X-+----- +--* BOUNDS_CHECK_Rng void [001099] -----+----- | +--* LCL_VAR int V27 loc23 [002661] ---X-+----- | \--* ARR_LENGTH int [001098] -----+----- | \--* LCL_VAR ref V26 loc22 [002671] n---G+----- \--* IND int [002669] -----+----- \--* ARR_ADDR byref int[] [002668] -----+----- \--* ADD byref [002667] -----+----- +--* ADD byref [002659] -----+----- | +--* LCL_VAR ref V26 loc22 [002666] -----+----- | \--* CNS_INT long 16 [002665] -----+----- \--* LSH long [002663] -----+---U- +--* CAST long <- uint [002660] -----+----- | \--* LCL_VAR int V27 loc23 [002664] -----+-N--- \--* CNS_INT long 2 New refCnts for V28: refCnt = 2, refCntWtd = 1 New refCnts for V27: refCnt = 2, refCntWtd = 1 New refCnts for V26: refCnt = 3, refCntWtd = 1.50 New refCnts for V26: refCnt = 4, refCntWtd = 2 New refCnts for V27: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB82 (weight=0.50) STMT00209 ( 0x33D[E-] ... 0x33F ) [000968] -A---+----- * ASG int [000967] D----+-N--- +--* LCL_VAR int V30 loc26 [000966] -----+----- \--* LCL_VAR int V28 loc24 New refCnts for V30: refCnt = 1, refCntWtd = 0.50 V30 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V28: refCnt = 3, refCntWtd = 1.50 STMT00211 ( ??? ... 0x346 ) [000975] -A---+----- * ASG int [000974] D----+-N--- +--* LCL_VAR int V64 tmp24 [000969] -----+----- \--* LCL_VAR int V08 loc4 New refCnts for V64: refCnt = 1, refCntWtd = 0.50 V64 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V08: refCnt = 3, refCntWtd = 1.50 STMT00210 ( 0x341[E-] ... 0x346 ) [000973] -----+----- * JTRUE void [000972] J----+-N--- \--* LT int [000970] -----+----- +--* LCL_VAR int V14 loc10 [000971] -----+----- \--* CNS_INT int 0 New refCnts for V14: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB83 (weight=0.50) STMT00236 ( ??? ... 0x349 ) [001093] -A---+----- * ASG int [001092] D----+-N--- +--* LCL_VAR int V65 tmp25 [000977] -----+----- \--* LCL_VAR int V64 tmp24 New refCnts for V65: refCnt = 1, refCntWtd = 0.50 V65 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V64: refCnt = 2, refCntWtd = 1 STMT00237 ( ??? ... ??? ) [001096] -A---+----- * ASG int [001095] D----+-N--- +--* LCL_VAR int V66 tmp26 [001091] -----+----- \--* CNS_INT int 0 New refCnts for V66: refCnt = 1, refCntWtd = 0.50 V66 needs explicit zero init. Disqualified as a single-def register candidate. *** marking local variables in block BB84 (weight=0.50) STMT00212 ( ??? ... 0x34B ) [000981] -A---+----- * ASG int [000980] D----+-N--- +--* LCL_VAR int V65 tmp25 [000978] -----+----- \--* LCL_VAR int V64 tmp24 New refCnts for V65: refCnt = 2, refCntWtd = 1 New refCnts for V64: refCnt = 3, refCntWtd = 1.50 STMT00213 ( ??? ... ??? ) [000984] -A---+----- * ASG int [000983] D----+-N--- +--* LCL_VAR int V66 tmp26 [000979] -----+----- \--* LCL_VAR int V14 loc10 New refCnts for V66: refCnt = 2, refCntWtd = 1 New refCnts for V14: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB85 (weight=0.50) STMT00214 ( ??? ... 0x34E ) [000990] -A---+----- * ASG int [000989] D----+-N--- +--* LCL_VAR int V31 loc27 [000988] -----+----- \--* ADD int [000986] -----+----- +--* LCL_VAR int V65 tmp25 [000987] -----+----- \--* LCL_VAR int V66 tmp26 New refCnts for V31: refCnt = 1, refCntWtd = 0.50 V31 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V65: refCnt = 3, refCntWtd = 1.50 New refCnts for V66: refCnt = 3, refCntWtd = 1.50 STMT00215 ( 0x350[E-] ... 0x353 ) [000994] -----+----- * JTRUE void [000993] J----+-N--- \--* GT int [000991] -----+----- +--* LCL_VAR int V06 loc2 [000992] -----+----- \--* LCL_VAR int V31 loc27 New refCnts for V06: refCnt = 7, refCntWtd = 27 New refCnts for V31: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB86 (weight=0.50) STMT00235 ( 0x355[E-] ... 0x357 ) [001089] -A---+----- * ASG int [001088] D----+-N--- +--* LCL_VAR int V67 tmp27 [001087] -----+----- \--* LCL_VAR int V31 loc27 New refCnts for V67: refCnt = 1, refCntWtd = 0.50 V67 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V31: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB87 (weight=0.50) STMT00216 ( 0x359[E-] ... 0x359 ) [000997] -A---+----- * ASG int [000996] D----+-N--- +--* LCL_VAR int V67 tmp27 [000995] -----+----- \--* LCL_VAR int V06 loc2 New refCnts for V67: refCnt = 2, refCntWtd = 1 New refCnts for V06: refCnt = 8, refCntWtd = 27.50 *** marking local variables in block BB88 (weight=0.50) STMT00217 ( ??? ... 0x35A ) [001001] -A---+----- * ASG int [001000] D----+-N--- +--* LCL_VAR int V32 loc28 [000999] -----+----- \--* LCL_VAR int V67 tmp27 New refCnts for V32: refCnt = 1, refCntWtd = 0.50 V32 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V67: refCnt = 3, refCntWtd = 1.50 STMT00502 ( 0x3C2[E-] ... ??? ) ( 9, 7) [003156] ----------- * JTRUE void ( 7, 5) [003157] J------N--- \--* LE int ( 3, 2) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [003159] ----------- \--* LCL_VAR int V28 loc24 New refCnts for V32: refCnt = 2, refCntWtd = 1 New refCnts for V28: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB89 (weight=4 ) STMT00219 ( 0x35E[E-] ... 0x360 ) [001009] -----+----- * JTRUE void [001008] J----+-N--- \--* EQ int [001006] -----+----- +--* LCL_VAR int V30 loc26 [001007] -----+----- \--* CNS_INT int 0 New refCnts for V30: refCnt = 2, refCntWtd = 4.50 *** marking local variables in block BB90 (weight=4 ) STMT00220 ( 0x362[E-] ... 0x366 ) [001014] -A---+----- * ASG int [001013] D----+-N--- +--* LCL_VAR int V20 loc16 [001012] -----+----- \--* ADD int [001010] -----+----- +--* LCL_VAR int V20 loc16 [001011] -----+----- \--* CNS_INT int 1 New refCnts for V20: refCnt = 2, refCntWtd = 5 New refCnts for V20: refCnt = 3, refCntWtd = 9 STMT00222 ( 0x368[E-] ... ??? ) [001021] -----+----- * JTRUE void [001020] J----+-N--- \--* LT int [001015] -----+----- +--* LCL_VAR int V20 loc16 [001574] -----+----- \--* LCL_VAR int V144 tmp104 New refCnts for V20: refCnt = 4, refCntWtd = 13 New refCnts for V144: refCnt = 2, refCntWtd = 5 *** marking local variables in block BB91 (weight=2 ) STMT00229 ( 0x373[E-] ... ??? ) [001070] -ACXG+----- * ASG ref [001069] D----+-N--- +--* LCL_VAR ref V33 loc29 [001068] --CXG+----- \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 [001067] -----+----- arg1 in x0 +--* CAST long <- int [001066] -----+----- | \--* LSH int [001578] -----+----- | +--* LCL_VAR int V144 tmp104 [001065] -----+----- | \--* CNS_INT int 1 [002672] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn New refCnts for V33: refCnt = 1, refCntWtd = 2 V33 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V144: refCnt = 3, refCntWtd = 7 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] [002679] -A---+----- * COMMA void [002675] -A--------- +--* ASG byref [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 [002674] ----------- | \--* CNS_INT byref 0 [002678] -A--------- \--* ASG int [002676] D------N--- +--* LCL_VAR int V160 tmp120 [002677] ----------- \--* CNS_INT int 0 New refCnts for V159: refCnt = 1, refCntWtd = 2 V159 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V160: refCnt = 1, refCntWtd = 2 V160 needs explicit zero init. Disqualified as a single-def register candidate. STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001590] -----+----- * JTRUE void [001589] J----+-N--- \--* NE int [001073] -----+----- +--* LCL_VAR ref V33 loc29 [001588] -----+----- \--* CNS_INT ref null New refCnts for V33: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB92 (weight=2 ) STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [002686] -A---+----- * COMMA void [002682] -A--------- +--* ASG byref [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 [002681] ----------- | \--* CNS_INT byref 0 [002685] -A--------- \--* ASG int [002683] D------N--- +--* LCL_VAR int V160 tmp120 [002684] ----------- \--* CNS_INT int 0 New refCnts for V159: refCnt = 2, refCntWtd = 4 New refCnts for V160: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB93 (weight=2 ) STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001604] -A-X-+----- * ASG byref [001603] D----+-N--- +--* LCL_VAR byref V159 tmp119 [002692] ---X-+-N--- \--* COMMA byref [002688] ---X-+----- +--* NULLCHECK byte [002687] -----+----- | \--* LCL_VAR ref V33 loc29 [002691] -----+----- \--* ADD byref [002689] -----+----- +--* LCL_VAR ref V33 loc29 [002690] -----+----- \--* CNS_INT long 16 Fseq[] New refCnts for V159: refCnt = 3, refCntWtd = 6 New refCnts for V33: refCnt = 3, refCntWtd = 6 New refCnts for V33: refCnt = 4, refCntWtd = 8 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] [001610] -A-X-+----- * ASG int [001609] D----+-N--- +--* LCL_VAR int V160 tmp120 [001608] ---X-+----- \--* ARR_LENGTH int [001607] -----+----- \--* LCL_VAR ref V33 loc29 New refCnts for V160: refCnt = 3, refCntWtd = 6 New refCnts for V33: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB94 (weight=2 ) STMT00339 ( ??? ... ??? ) [002699] -A---+----- * COMMA void [002695] -A--------- +--* ASG byref [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 [002694] ----------- | \--* LCL_VAR byref V159 tmp119 [002698] -A--------- \--* ASG int [002696] D------N--- +--* LCL_VAR int V162 tmp122 [002697] ----------- \--* LCL_VAR int V160 tmp120 New refCnts for V161: refCnt = 1, refCntWtd = 2 V161 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V159: refCnt = 4, refCntWtd = 8 New refCnts for V162: refCnt = 1, refCntWtd = 2 V162 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V160: refCnt = 4, refCntWtd = 8 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? [001629] -----+----- * JTRUE void [001628] N----+-N-U- \--* GT int [001620] -----+----- +--* LCL_VAR int V144 tmp104 [001647] -----+----- \--* LCL_VAR int V160 tmp120 New refCnts for V144: refCnt = 4, refCntWtd = 9 New refCnts for V160: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB95 (weight=2 ) *** marking local variables in block BB96 (weight=2 ) STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001669] -A---+----- * ASG byref [001668] D----+-N--- +--* LCL_VAR byref V81 tmp41 [001633] -----+----- \--* LCL_VAR byref V161 tmp121 New refCnts for V81: refCnt = 1, refCntWtd = 4 V81 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V161: refCnt = 2, refCntWtd = 4 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001671] -A---+----- * ASG byref [001670] D----+-N--- +--* LCL_VAR byref V82 tmp42 [001636] -----+----- \--* LCL_VAR byref V143 tmp103 New refCnts for V82: refCnt = 1, refCntWtd = 4 V82 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V143: refCnt = 2, refCntWtd = 3 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? [001673] -A---+----- * ASG long [001672] D----+-N--- +--* LCL_VAR long V83 tmp43 [001640] -----+---U- \--* CAST long <- ulong <- uint [001639] -----+----- \--* LCL_VAR int V144 tmp104 New refCnts for V83: refCnt = 1, refCntWtd = 4 V83 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V144: refCnt = 5, refCntWtd = 11 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? [001667] --CXG+----- * CALL r2r_ind void [001666] -----+----- arg3 in x2 +--* LSH long [001663] -----+----- | +--* LCL_VAR long V83 tmp43 [001665] -----+----- | \--* CNS_INT long 2 [001661] -----+----- arg1 in x0 +--* LCL_VAR byref V161 tmp121 [001662] -----+----- arg2 in x1 +--* LCL_VAR byref V143 tmp103 [002700] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn New refCnts for V83: refCnt = 2, refCntWtd = 8 New refCnts for V161: refCnt = 3, refCntWtd = 6 New refCnts for V143: refCnt = 3, refCntWtd = 5 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] [002708] -A---+----- * COMMA void [002704] -A--------- +--* ASG byref [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 [002703] ----------- | \--* CNS_INT byref 0 [002707] -A--------- \--* ASG int [002705] D------N--- +--* LCL_VAR int V164 tmp124 [002706] ----------- \--* CNS_INT int 0 New refCnts for V163: refCnt = 1, refCntWtd = 2 V163 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V164: refCnt = 1, refCntWtd = 2 V164 needs explicit zero init. Disqualified as a single-def register candidate. STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001702] -----+----- * JTRUE void [001701] J----+-N--- \--* NE int [001082] -----+----- +--* LCL_VAR ref V33 loc29 [001700] -----+----- \--* CNS_INT ref null New refCnts for V33: refCnt = 6, refCntWtd = 12 *** marking local variables in block BB97 (weight=2 ) STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [002715] -A---+----- * COMMA void [002711] -A--------- +--* ASG byref [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 [002710] ----------- | \--* CNS_INT byref 0 [002714] -A--------- \--* ASG int [002712] D------N--- +--* LCL_VAR int V164 tmp124 [002713] ----------- \--* CNS_INT int 0 New refCnts for V163: refCnt = 2, refCntWtd = 4 New refCnts for V164: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB98 (weight=2 ) STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001716] -A-X-+----- * ASG byref [001715] D----+-N--- +--* LCL_VAR byref V163 tmp123 [002721] ---X-+-N--- \--* COMMA byref [002717] ---X-+----- +--* NULLCHECK byte [002716] -----+----- | \--* LCL_VAR ref V33 loc29 [002720] -----+----- \--* ADD byref [002718] -----+----- +--* LCL_VAR ref V33 loc29 [002719] -----+----- \--* CNS_INT long 16 Fseq[] New refCnts for V163: refCnt = 3, refCntWtd = 6 New refCnts for V33: refCnt = 7, refCntWtd = 14 New refCnts for V33: refCnt = 8, refCntWtd = 16 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] [001722] -A-X-+----- * ASG int [001721] D----+-N--- +--* LCL_VAR int V164 tmp124 [001720] ---X-+----- \--* ARR_LENGTH int [001719] -----+----- \--* LCL_VAR ref V33 loc29 New refCnts for V164: refCnt = 3, refCntWtd = 6 New refCnts for V33: refCnt = 9, refCntWtd = 18 *** marking local variables in block BB99 (weight=2 ) STMT00234 ( 0x391[E-] ... ??? ) [002728] -A---+----- * COMMA void [002724] -A--------- +--* ASG byref [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 [002723] ----------- | \--* LCL_VAR byref V163 tmp123 [002727] -A--------- \--* ASG int [002725] D------N--- +--* LCL_VAR int V144 tmp104 [002726] ----------- \--* LCL_VAR int V164 tmp124 New refCnts for V143: refCnt = 4, refCntWtd = 7 V143 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V163: refCnt = 4, refCntWtd = 8 New refCnts for V144: refCnt = 6, refCntWtd = 13 New refCnts for V164: refCnt = 4, refCntWtd = 8 *** marking local variables in block BB100 (weight=4 ) STMT00223 ( 0x39A[E-] ... 0x3A5 ) [001038] -A-XG+----- * ASG int [001035] ---XG+-N--- +--* COMMA int [001029] ---X-+----- | +--* BOUNDS_CHECK_Rng void [001024] -----+----- | | +--* LCL_VAR int V20 loc16 [001028] -----+----- | | \--* LCL_VAR int V144 tmp104 [002729] ---XG+-N--- | \--* IND int [001034] -----+----- | \--* ADD byref [001033] -----+----- | +--* LCL_VAR byref V143 tmp103 [001032] -----+----- | \--* LSH long [001030] -----+---U- | +--* CAST long <- uint [001025] -----+----- | | \--* LCL_VAR int V20 loc16 [001031] -----+----- | \--* CNS_INT long 2 [001036] -----+----- \--* LCL_VAR int V28 loc24 New refCnts for V20: refCnt = 5, refCntWtd = 17 New refCnts for V144: refCnt = 7, refCntWtd = 17 New refCnts for V143: refCnt = 5, refCntWtd = 11 New refCnts for V20: refCnt = 6, refCntWtd = 21 New refCnts for V28: refCnt = 5, refCntWtd = 6 STMT00224 ( 0x3A6[E-] ... 0x3AC ) [001044] -----+----- * JTRUE void [001043] J----+-N--- \--* GE int [001039] -----+----- +--* LCL_VAR int V27 loc23 [001042] -----+----- \--* ADD int [001040] -----+----- +--* LCL_VAR int V29 loc25 [001041] -----+----- \--* CNS_INT int -1 New refCnts for V27: refCnt = 4, refCntWtd = 5.50 New refCnts for V29: refCnt = 3, refCntWtd = 5 *** marking local variables in block BB101 (weight=2 ) STMT00226 ( 0x3AE[E-] ... 0x3B2 ) [001054] -A---+----- * ASG int [001053] D----+-N--- +--* LCL_VAR int V27 loc23 [001052] -----+----- \--* ADD int [001050] -----+----- +--* LCL_VAR int V27 loc23 [001051] -----+----- \--* CNS_INT int 1 New refCnts for V27: refCnt = 5, refCntWtd = 7.50 New refCnts for V27: refCnt = 6, refCntWtd = 9.50 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) [001060] -A-XG+----- * ASG int [001059] D----+-N--- +--* LCL_VAR int V30 loc26 [002741] ---XG+----- \--* COMMA int [002733] ---X-+----- +--* BOUNDS_CHECK_Rng void [001056] -----+----- | +--* LCL_VAR int V27 loc23 [002732] ---X-+----- | \--* ARR_LENGTH int [001055] -----+----- | \--* LCL_VAR ref V26 loc22 [002742] n---G+----- \--* IND int [002740] -----+----- \--* ARR_ADDR byref int[] [002739] -----+----- \--* ADD byref [002738] -----+----- +--* ADD byref [002730] -----+----- | +--* LCL_VAR ref V26 loc22 [002737] -----+----- | \--* CNS_INT long 16 [002736] -----+----- \--* LSH long [002734] -----+---U- +--* CAST long <- uint [002731] -----+----- | \--* LCL_VAR int V27 loc23 [002735] -----+-N--- \--* CNS_INT long 2 New refCnts for V30: refCnt = 3, refCntWtd = 6.50 New refCnts for V27: refCnt = 7, refCntWtd = 11.50 New refCnts for V26: refCnt = 5, refCntWtd = 4 New refCnts for V26: refCnt = 6, refCntWtd = 6 New refCnts for V27: refCnt = 8, refCntWtd = 13.50 *** marking local variables in block BB102 (weight=4 ) STMT00225 ( 0x3BB[E-] ... 0x3C0 ) [001049] -A---+----- * ASG int [001048] D----+-N--- +--* LCL_VAR int V28 loc24 [001047] -----+----- \--* ADD int [001045] -----+----- +--* LCL_VAR int V28 loc24 [001046] -----+----- \--* LCL_VAR int V30 loc26 New refCnts for V28: refCnt = 6, refCntWtd = 10 New refCnts for V28: refCnt = 7, refCntWtd = 14 New refCnts for V30: refCnt = 4, refCntWtd = 10.50 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 9, 7) [001005] ----------- * JTRUE void ( 7, 5) [001004] J------N--- \--* GT int ( 3, 2) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 3, 2) [001003] ----------- \--* LCL_VAR int V28 loc24 New refCnts for V32: refCnt = 3, refCntWtd = 5 New refCnts for V28: refCnt = 8, refCntWtd = 18 *** marking local variables in block BB103 (weight=1 ) STMT00047 ( 0x3C8[E-] ... 0x3CE ) [000186] ---XG+----- * JTRUE void [000185] J--XG+-N--- \--* EQ int [000183] ---XG+----- +--* IND bool [002744] -----+----- | \--* ADD byref [000182] -----+----- | +--* LCL_VAR byref V01 arg1 [002743] -----+----- | \--* CNS_INT long 8 [000184] -----+----- \--* CNS_INT int 0 New refCnts for V01: refCnt = 15, refCntWtd = 21.50 *** marking local variables in block BB104 (weight=0.50) STMT00198 ( 0x3D0[E-] ... 0x3D2 ) [000930] -----+----- * JTRUE void [000929] J----+-N--- \--* NE int [000927] -----+----- +--* LCL_VAR int V15 loc11 [000928] -----+----- \--* CNS_INT int 0 New refCnts for V15: refCnt = 6, refCntWtd = 18.50 *** marking local variables in block BB105 (weight=0.50) STMT00199 ( 0x3D4[E-] ... 0x3DA ) [000935] ---XG+----- * JTRUE void [000934] J--XG+-N--- \--* EQ int [000932] ---XG+----- +--* IND int [002746] -----+----- | \--* ADD byref [000931] -----+----- | +--* LCL_VAR byref V01 arg1 [002745] -----+----- | \--* CNS_INT long 4 [000933] -----+----- \--* CNS_INT int 0 New refCnts for V01: refCnt = 16, refCntWtd = 22 *** marking local variables in block BB106 (weight=0.50) STMT00367 ( 0x3DC[E-] ... ??? ) [001783] -A-XG+----- * ASG ref [001782] D----+-N--- +--* LCL_VAR ref V86 tmp46 [001730] ---XG+----- \--* IND ref [002748] -----+----- \--* ADD byref [000937] -----+----- +--* LCL_VAR ref V03 arg3 [002747] -----+----- \--* CNS_INT long 40 Fseq[] New refCnts for V86: refCnt = 1, refCntWtd = 1 Marking EH Var V86 as a register candidate. New refCnts for V03: refCnt = 3, refCntWtd = 1.50 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001735] -----+----- * JTRUE void [001734] J----+-N--- \--* EQ int [001732] -----+----- +--* LCL_VAR ref V86 tmp46 [001733] -----+----- \--* CNS_INT ref null New refCnts for V86: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB107 (weight=0.50) STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001738] -A-XG+----- * ASG int [001737] D----+-N--- +--* LCL_VAR int V87 tmp47 [001736] ---XG+----- \--* IND int [002750] -----+----- \--* ADD byref [000936] -----+----- +--* LCL_VAR byref V00 arg0 [002749] -----+----- \--* CNS_INT long 8 New refCnts for V87: refCnt = 1, refCntWtd = 0.50 V87 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 1, refCntWtd = 0.50 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001743] ---X-+----- * JTRUE void [001742] N--X-+-N-U- \--* NE int [001740] ---X-+----- +--* ARR_LENGTH int [001739] -----+----- | \--* LCL_VAR ref V86 tmp46 [001741] -----+----- \--* CNS_INT int 1 New refCnts for V86: refCnt = 3, refCntWtd = 3 *** marking local variables in block BB108 (weight=0.50) STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001753] ---XG+----- * JTRUE void [001752] N--XG+-N-U- \--* GE int [001747] -----+----- +--* LCL_VAR int V87 tmp47 [001786] ---XG+----- \--* IND int [002754] -----+----- \--* ADD byref [001748] -----+----- +--* LCL_VAR byref V00 arg0 [002753] -----+----- \--* CNS_INT long 24 New refCnts for V87: refCnt = 2, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB109 (weight=0.50) STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001759] -A-XG+----- * ASG byref [001758] D----+-N--- +--* LCL_VAR byref V88 tmp48 [002761] ---X-+-N--- \--* COMMA byref [002757] ---X-+----- +--* NULLCHECK byte [002756] -----+----- | \--* LCL_VAR byref V00 arg0 [002760] -----+----- \--* ADD byref [002758] -----+----- +--* LCL_VAR byref V00 arg0 [002759] -----+----- \--* CNS_INT long 16 New refCnts for V88: refCnt = 1, refCntWtd = 1 Marking EH Var V88 as a register candidate. New refCnts for V00: refCnt = 3, refCntWtd = 1.50 New refCnts for V00: refCnt = 4, refCntWtd = 2 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] [001775] -A-XG+----- * ASG short [001769] ---XG+-N--- +--* COMMA short [001763] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001756] -----+----- | | +--* LCL_VAR int V87 tmp47 [001762] ---XG+----- | | \--* IND int [002763] -----+----- | | \--* ADD byref [001761] -----+----- | | +--* LCL_VAR byref V88 tmp48 [002762] -----+----- | | \--* CNS_INT long 8 [002764] ---XG+-N--- | \--* IND short [001768] ---XG+----- | \--* ADD byref [001767] ---XG+----- | +--* IND byref [001760] -----+----- | | \--* LCL_VAR byref V88 tmp48 [001766] -----+----- | \--* LSH long [001764] -----+---U- | +--* CAST long <- uint [001757] -----+----- | | \--* LCL_VAR int V87 tmp47 [001765] -----+----- | \--* CNS_INT long 1 [002775] ---XG+----- \--* COMMA ushort [002768] ---X-+----- +--* BOUNDS_CHECK_Rng void [001771] -----+----- | +--* CNS_INT int 0 [002767] ---X-+----- | \--* ARR_LENGTH int [001770] -----+----- | \--* LCL_VAR ref V86 tmp46 [002777] n---G+----- \--* IND ushort [002774] -----+----- \--* ARR_ADDR byref ushort[] [002772] -----+----- \--* ADD byref [002765] -----+----- +--* LCL_VAR ref V86 tmp46 [002771] -----+----- \--* CNS_INT long 12 New refCnts for V87: refCnt = 3, refCntWtd = 1.50 New refCnts for V88: refCnt = 2, refCntWtd = 2 New refCnts for V88: refCnt = 3, refCntWtd = 3 New refCnts for V87: refCnt = 4, refCntWtd = 2 New refCnts for V86: refCnt = 4, refCntWtd = 4 New refCnts for V86: refCnt = 5, refCntWtd = 5 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001781] -A-XG+----- * ASG int [001780] ---XG+-N--- +--* IND int [002779] -----+----- | \--* ADD byref [001776] -----+----- | +--* LCL_VAR byref V00 arg0 [002778] -----+----- | \--* CNS_INT long 8 [001779] -----+----- \--* ADD int [001777] -----+----- +--* LCL_VAR int V87 tmp47 [001778] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 5, refCntWtd = 2.50 New refCnts for V87: refCnt = 5, refCntWtd = 2.50 *** marking local variables in block BB110 (weight=0 ) STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? [001630] --CXG+----- * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() [002701] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn *** marking local variables in block BB111 (weight=0.50) STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] [001746] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001744] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001745] -----+----- arg2 in x1 +--* LCL_VAR ref V86 tmp46 [002780] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn New refCnts for V00: refCnt = 6, refCntWtd = 3 New refCnts for V86: refCnt = 6, refCntWtd = 6 *** marking local variables in block BB112 (weight=1 ) STMT00048 ( 0x3E8[E-] ... 0x3E9 ) [000189] -A---+----- * ASG int [000188] D----+-N--- +--* LCL_VAR int V21 loc17 [002781] -----+----- \--* CNS_INT int 0 New refCnts for V21: refCnt = 1, refCntWtd = 1 V21 needs explicit zero init. Disqualified as a single-def register candidate. STMT00369 ( 0x3EB[E-] ... ??? ) [002788] -A---+----- * COMMA void [002784] -A--------- +--* ASG byref [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] [002787] -A--------- \--* ASG int [002785] D------N--- +--* LCL_VAR int V166 tmp126 [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V165: refCnt = 1, refCntWtd = 1 Marking EH Var V165 as a register candidate. New refCnts for V02: refCnt = 13, refCntWtd = 243 New refCnts for V166: refCnt = 1, refCntWtd = 1 V166 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V02: refCnt = 14, refCntWtd = 244 STMT00050 ( 0x3EB[E-] ... ??? ) [000196] -A---+----- * ASG byref [000195] D----+-N--- +--* LCL_VAR byref V35 loc31 [001792] -----+----- \--* LCL_VAR byref V165 tmp125 New refCnts for V35: refCnt = 1, refCntWtd = 1 Marking EH Var V35 as a register candidate. New refCnts for V165: refCnt = 2, refCntWtd = 2 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) [000200] -A---+----- * ASG long [000199] D----+-N--- +--* LCL_VAR long V34 loc30 [002793] -A---+----- \--* COMMA long [002790] -A---+----- +--* ASG long [002789] D----+-N--- | +--* LCL_VAR long V169 tmp129 [000197] -----+----- | \--* LCL_VAR byref V165 tmp125 [002791] -----+----- \--* LCL_VAR long V169 tmp129 New refCnts for V34: refCnt = 1, refCntWtd = 1 V34 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V169: refCnt = 1, refCntWtd = 2 V169 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V165: refCnt = 3, refCntWtd = 3 New refCnts for V169: refCnt = 2, refCntWtd = 4 STMT00052 ( 0x3F8[E-] ... 0x3FA ) [000203] -A---+----- * ASG long [000202] D----+-N--- +--* LCL_VAR long V36 loc32 [000201] -----+----- \--* LCL_VAR long V17 loc13 New refCnts for V36: refCnt = 1, refCntWtd = 1 V36 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V17: refCnt = 4, refCntWtd = 14 *** marking local variables in block BB113 (weight=2 ) STMT00070 ( 0x401[E-] ... 0x404 ) [000274] -----+----- * JTRUE void [000273] J----+-N--- \--* LE int [000271] -----+----- +--* LCL_VAR int V14 loc10 [000272] -----+----- \--* CNS_INT int 0 New refCnts for V14: refCnt = 5, refCntWtd = 4 *** marking local variables in block BB114 (weight=2 ) STMT00176 ( 0x406[E-] ... 0x40A ) [000824] -----+----- * JTRUE void [000823] J----+-N--- \--* EQ int [000821] -----+----- +--* LCL_VAR int V18 loc14 [000822] -----+----- \--* CNS_INT int 35 New refCnts for V18: refCnt = 11, refCntWtd = 154 *** marking local variables in block BB115 (weight=2 ) STMT00196 ( 0x40C[E-] ... 0x410 ) [000922] -----+----- * JTRUE void [000921] J----+-N--- \--* EQ int [000919] -----+----- +--* LCL_VAR int V18 loc14 [000920] -----+----- \--* CNS_INT int 46 New refCnts for V18: refCnt = 12, refCntWtd = 156 *** marking local variables in block BB116 (weight=2 ) STMT00197 ( 0x412[E-] ... 0x416 ) [000926] -----+----- * JTRUE void [000925] J----+-N--- \--* EQ int [000923] -----+----- +--* LCL_VAR int V18 loc14 [000924] -----+----- \--* CNS_INT int 48 New refCnts for V18: refCnt = 13, refCntWtd = 158 *** marking local variables in block BB117 (weight=2 ) *** marking local variables in block BB118 (weight=8 ) STMT00179 ( ??? ... 0x41E ) [000836] -A---+----- * ASG byref [000835] D----+-N--- +--* LCL_VAR byref V60 tmp20 [000829] -----+----- \--* LCL_VAR byref V00 arg0 New refCnts for V60: refCnt = 1, refCntWtd = 8 V60 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 7, refCntWtd = 11 STMT00178 ( 0x41A[E-] ... 0x41E ) [000834] ---XG+----- * JTRUE void [000833] J--XG+-N--- \--* NE int [000831] ---XG+----- +--* IND ubyte [000830] -----+----- | \--* LCL_VAR long V36 loc32 [000832] -----+----- \--* CNS_INT int 0 New refCnts for V36: refCnt = 2, refCntWtd = 9 *** marking local variables in block BB119 (weight=8 ) STMT00194 ( ??? ... 0x422 ) [000914] -A---+----- * ASG byref [000913] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000838] -----+----- \--* LCL_VAR byref V60 tmp20 New refCnts for V62: refCnt = 1, refCntWtd = 8 V62 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V60: refCnt = 2, refCntWtd = 16 STMT00195 ( ??? ... ??? ) [000917] -A---+----- * ASG int [000916] D----+-N--- +--* LCL_VAR int V63 tmp23 [000912] -----+----- \--* CNS_INT int 48 New refCnts for V63: refCnt = 1, refCntWtd = 8 V63 needs explicit zero init. Disqualified as a single-def register candidate. *** marking local variables in block BB120 (weight=8 ) STMT00181 ( ??? ... 0x429 ) [000848] -A---+----- * ASG long [000847] D----+-N--- +--* LCL_VAR long V61 tmp21 [000840] -----+----- \--* LCL_VAR long V36 loc32 New refCnts for V61: refCnt = 1, refCntWtd = 16 V61 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V36: refCnt = 3, refCntWtd = 17 STMT00180 ( ??? ... ??? ) [000846] -A---+----- * ASG long [000845] D----+-N--- +--* LCL_VAR long V36 loc32 [000844] -----+----- \--* ADD long [000841] -----+----- +--* LCL_VAR long V36 loc32 [000843] -----+----- \--* CNS_INT long 1 New refCnts for V36: refCnt = 4, refCntWtd = 25 New refCnts for V36: refCnt = 5, refCntWtd = 33 STMT00182 ( ??? ... 0x42B ) [000852] -A---+----- * ASG byref [000851] D----+-N--- +--* LCL_VAR byref V62 tmp22 [000839] -----+----- \--* LCL_VAR byref V60 tmp20 New refCnts for V62: refCnt = 2, refCntWtd = 16 New refCnts for V60: refCnt = 3, refCntWtd = 24 STMT00183 ( ??? ... ??? ) [000855] -A-XG+----- * ASG int [000854] D----+-N--- +--* LCL_VAR int V63 tmp23 [000850] ---XG+----- \--* IND ubyte [000849] -----+----- \--* LCL_VAR long V61 tmp21 New refCnts for V63: refCnt = 2, refCntWtd = 16 New refCnts for V61: refCnt = 2, refCntWtd = 32 *** marking local variables in block BB121 (weight=8 ) STMT00377 ( ??? ... ??? ) [001836] -A---+----- * ASG ushort [001835] D----+-N--- +--* LCL_VAR int V92 tmp52 [001796] -----+----- \--* CAST int <- ushort <- int [000858] -----+----- \--* LCL_VAR int V63 tmp23 New refCnts for V92: refCnt = 1, refCntWtd = 16 V92 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V63: refCnt = 3, refCntWtd = 24 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [001799] -A-XG+----- * ASG int [001798] D----+-N--- +--* LCL_VAR int V91 tmp51 [001797] ---XG+----- \--* IND int [002795] -----+----- \--* ADD byref [000857] -----+----- +--* LCL_VAR byref V62 tmp22 [002794] -----+----- \--* CNS_INT long 8 New refCnts for V91: refCnt = 1, refCntWtd = 8 V91 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V62: refCnt = 3, refCntWtd = 24 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [001806] ---XG+----- * JTRUE void [001805] N--XG+-N-U- \--* GE int [001800] -----+----- +--* LCL_VAR int V91 tmp51 [001839] ---XG+----- \--* IND int [002799] -----+----- \--* ADD byref [001801] -----+----- +--* LCL_VAR byref V62 tmp22 [002798] -----+----- \--* CNS_INT long 24 New refCnts for V91: refCnt = 2, refCntWtd = 16 New refCnts for V62: refCnt = 4, refCntWtd = 32 *** marking local variables in block BB122 (weight=8 ) STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [001815] -A-XG+----- * ASG byref [001814] D----+-N--- +--* LCL_VAR byref V93 tmp53 [002806] ---X-+-N--- \--* COMMA byref [002802] ---X-+----- +--* NULLCHECK byte [002801] -----+----- | \--* LCL_VAR byref V62 tmp22 [002805] -----+----- \--* ADD byref [002803] -----+----- +--* LCL_VAR byref V62 tmp22 [002804] -----+----- \--* CNS_INT long 16 New refCnts for V93: refCnt = 1, refCntWtd = 16 V93 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V62: refCnt = 5, refCntWtd = 40 New refCnts for V62: refCnt = 6, refCntWtd = 48 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? [001828] -A-XG+----- * ASG short [001825] ---XG+-N--- +--* COMMA short [001819] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001812] -----+----- | | +--* LCL_VAR int V91 tmp51 [001818] ---XG+----- | | \--* IND int [002808] -----+----- | | \--* ADD byref [001817] -----+----- | | +--* LCL_VAR byref V93 tmp53 [002807] -----+----- | | \--* CNS_INT long 8 [002809] ---XG+-N--- | \--* IND short [001824] ---XG+----- | \--* ADD byref [001823] ---XG+----- | +--* IND byref [001816] -----+----- | | \--* LCL_VAR byref V93 tmp53 [001822] -----+----- | \--* LSH long [001820] -----+---U- | +--* CAST long <- uint [001813] -----+----- | | \--* LCL_VAR int V91 tmp51 [001821] -----+----- | \--* CNS_INT long 1 [001826] -----+----- \--* LCL_VAR int V92 tmp52 New refCnts for V91: refCnt = 3, refCntWtd = 24 New refCnts for V93: refCnt = 2, refCntWtd = 32 New refCnts for V93: refCnt = 3, refCntWtd = 48 New refCnts for V91: refCnt = 4, refCntWtd = 32 New refCnts for V92: refCnt = 2, refCntWtd = 32 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [001834] -A-XG+----- * ASG int [001833] ---XG+-N--- +--* IND int [002811] -----+----- | \--* ADD byref [001829] -----+----- | +--* LCL_VAR byref V62 tmp22 [002810] -----+----- | \--* CNS_INT long 8 [001832] -----+----- \--* ADD int [001830] -----+----- +--* LCL_VAR int V91 tmp51 [001831] -----+----- \--* CNS_INT int 1 New refCnts for V62: refCnt = 7, refCntWtd = 56 New refCnts for V91: refCnt = 5, refCntWtd = 40 *** marking local variables in block BB123 (weight=8 ) STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [001809] --CXG+----- * CALL r2r_ind void [001807] -----+----- this in x0 +--* LCL_VAR byref V62 tmp22 [001808] -----+----- arg2 in x1 +--* LCL_VAR int V92 tmp52 [002812] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn New refCnts for V62: refCnt = 8, refCntWtd = 64 New refCnts for V92: refCnt = 3, refCntWtd = 48 *** marking local variables in block BB124 (weight=8 ) STMT00185 ( 0x431[E-] ... ??? ) [000863] -----+----- * JTRUE void [000862] J----+-N--- \--* EQ int [000860] -----+----- +--* LCL_VAR int V12 loc8 [000861] -----+----- \--* CNS_INT int 0 New refCnts for V12: refCnt = 5, refCntWtd = 27 *** marking local variables in block BB125 (weight=8 ) STMT00188 ( 0x435[E-] ... 0x438 ) [000877] -----+----- * JTRUE void [000876] J----+-N--- \--* LE int [000874] -----+----- +--* LCL_VAR int V08 loc4 [000875] -----+----- \--* CNS_INT int 1 New refCnts for V08: refCnt = 4, refCntWtd = 9.50 *** marking local variables in block BB126 (weight=8 ) STMT00189 ( 0x43A[E-] ... 0x43D ) [000881] -----+----- * JTRUE void [000880] J----+-N--- \--* LT int [000878] -----+----- +--* LCL_VAR int V20 loc16 [000879] -----+----- \--* CNS_INT int 0 New refCnts for V20: refCnt = 7, refCntWtd = 29 *** marking local variables in block BB127 (weight=8 ) STMT00190 ( 0x43F[E-] ... 0x44D ) [000901] ---XG+----- * JTRUE void [000900] N--XG+-N-U- \--* NE int [000882] -----+----- +--* LCL_VAR int V08 loc4 [000899] ---XG+----- \--* ADD int [000896] ---XG+----- +--* COMMA int [000890] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000885] -----+----- | | +--* LCL_VAR int V20 loc16 [000889] -----+----- | | \--* LCL_VAR int V144 tmp104 [002813] ---XG+----- | \--* IND int [000895] -----+----- | \--* ADD byref [000894] -----+----- | +--* LCL_VAR byref V143 tmp103 [000893] -----+----- | \--* LSH long [000891] -----+---U- | +--* CAST long <- uint [000886] -----+----- | | \--* LCL_VAR int V20 loc16 [000892] -----+----- | \--* CNS_INT long 2 [000898] -----+----- \--* CNS_INT int 1 New refCnts for V08: refCnt = 5, refCntWtd = 17.50 New refCnts for V20: refCnt = 8, refCntWtd = 37 New refCnts for V144: refCnt = 8, refCntWtd = 25 New refCnts for V143: refCnt = 6, refCntWtd = 19 New refCnts for V20: refCnt = 9, refCntWtd = 45 *** marking local variables in block BB128 (weight=8 ) STMT00388 ( 0x44F[E-] ... ??? ) [001896] -A-XG+----- * ASG ref [001895] D----+-N--- +--* LCL_VAR ref V95 tmp55 [001843] ---XG+----- \--* IND ref [002815] -----+----- \--* ADD byref [000903] -----+----- +--* LCL_VAR ref V03 arg3 [002814] -----+----- \--* CNS_INT long 56 Fseq[] New refCnts for V95: refCnt = 1, refCntWtd = 16 V95 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V03: refCnt = 4, refCntWtd = 9.50 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001848] -----+----- * JTRUE void [001847] J----+-N--- \--* EQ int [001845] -----+----- +--* LCL_VAR ref V95 tmp55 [001846] -----+----- \--* CNS_INT ref null New refCnts for V95: refCnt = 2, refCntWtd = 32 *** marking local variables in block BB129 (weight=8 ) STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001851] -A-XG+----- * ASG int [001850] D----+-N--- +--* LCL_VAR int V96 tmp56 [001849] ---XG+----- \--* IND int [002817] -----+----- \--* ADD byref [000902] -----+----- +--* LCL_VAR byref V00 arg0 [002816] -----+----- \--* CNS_INT long 8 New refCnts for V96: refCnt = 1, refCntWtd = 8 V96 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 8, refCntWtd = 19 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001856] ---X-+----- * JTRUE void [001855] N--X-+-N-U- \--* NE int [001853] ---X-+----- +--* ARR_LENGTH int [001852] -----+----- | \--* LCL_VAR ref V95 tmp55 [001854] -----+----- \--* CNS_INT int 1 New refCnts for V95: refCnt = 3, refCntWtd = 48 *** marking local variables in block BB130 (weight=8 ) STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001866] ---XG+----- * JTRUE void [001865] N--XG+-N-U- \--* GE int [001860] -----+----- +--* LCL_VAR int V96 tmp56 [001899] ---XG+----- \--* IND int [002821] -----+----- \--* ADD byref [001861] -----+----- +--* LCL_VAR byref V00 arg0 [002820] -----+----- \--* CNS_INT long 24 New refCnts for V96: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 9, refCntWtd = 27 *** marking local variables in block BB131 (weight=8 ) STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001872] -A-XG+----- * ASG byref [001871] D----+-N--- +--* LCL_VAR byref V97 tmp57 [002828] ---X-+-N--- \--* COMMA byref [002824] ---X-+----- +--* NULLCHECK byte [002823] -----+----- | \--* LCL_VAR byref V00 arg0 [002827] -----+----- \--* ADD byref [002825] -----+----- +--* LCL_VAR byref V00 arg0 [002826] -----+----- \--* CNS_INT long 16 New refCnts for V97: refCnt = 1, refCntWtd = 16 V97 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 10, refCntWtd = 35 New refCnts for V00: refCnt = 11, refCntWtd = 43 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] [001888] -A-XG+----- * ASG short [001882] ---XG+-N--- +--* COMMA short [001876] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001869] -----+----- | | +--* LCL_VAR int V96 tmp56 [001875] ---XG+----- | | \--* IND int [002830] -----+----- | | \--* ADD byref [001874] -----+----- | | +--* LCL_VAR byref V97 tmp57 [002829] -----+----- | | \--* CNS_INT long 8 [002831] ---XG+-N--- | \--* IND short [001881] ---XG+----- | \--* ADD byref [001880] ---XG+----- | +--* IND byref [001873] -----+----- | | \--* LCL_VAR byref V97 tmp57 [001879] -----+----- | \--* LSH long [001877] -----+---U- | +--* CAST long <- uint [001870] -----+----- | | \--* LCL_VAR int V96 tmp56 [001878] -----+----- | \--* CNS_INT long 1 [002842] ---XG+----- \--* COMMA ushort [002835] ---X-+----- +--* BOUNDS_CHECK_Rng void [001884] -----+----- | +--* CNS_INT int 0 [002834] ---X-+----- | \--* ARR_LENGTH int [001883] -----+----- | \--* LCL_VAR ref V95 tmp55 [002844] n---G+----- \--* IND ushort [002841] -----+----- \--* ARR_ADDR byref ushort[] [002839] -----+----- \--* ADD byref [002832] -----+----- +--* LCL_VAR ref V95 tmp55 [002838] -----+----- \--* CNS_INT long 12 New refCnts for V96: refCnt = 3, refCntWtd = 24 New refCnts for V97: refCnt = 2, refCntWtd = 32 New refCnts for V97: refCnt = 3, refCntWtd = 48 New refCnts for V96: refCnt = 4, refCntWtd = 32 New refCnts for V95: refCnt = 4, refCntWtd = 64 New refCnts for V95: refCnt = 5, refCntWtd = 80 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001894] -A-XG+----- * ASG int [001893] ---XG+-N--- +--* IND int [002846] -----+----- | \--* ADD byref [001889] -----+----- | +--* LCL_VAR byref V00 arg0 [002845] -----+----- | \--* CNS_INT long 8 [001892] -----+----- \--* ADD int [001890] -----+----- +--* LCL_VAR int V96 tmp56 [001891] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 12, refCntWtd = 51 New refCnts for V96: refCnt = 5, refCntWtd = 40 *** marking local variables in block BB132 (weight=8 ) STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] [001859] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001857] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001858] -----+----- arg2 in x1 +--* LCL_VAR ref V95 tmp55 [002847] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn New refCnts for V00: refCnt = 13, refCntWtd = 59 New refCnts for V95: refCnt = 6, refCntWtd = 96 *** marking local variables in block BB133 (weight=8 ) STMT00193 ( 0x45B[E-] ... ??? ) [000911] -A---+----- * ASG int [000910] D----+-N--- +--* LCL_VAR int V20 loc16 [000909] -----+----- \--* ADD int [000907] -----+----- +--* LCL_VAR int V20 loc16 [000908] -----+----- \--* CNS_INT int -1 New refCnts for V20: refCnt = 10, refCntWtd = 53 New refCnts for V20: refCnt = 11, refCntWtd = 61 *** marking local variables in block BB134 (weight=8 ) STMT00186 ( 0x461[E-] ... 0x465 ) [000868] -A---+----- * ASG int [000867] D----+-N--- +--* LCL_VAR int V08 loc4 [000866] -----+----- \--* ADD int [000864] -----+----- +--* LCL_VAR int V08 loc4 [000865] -----+----- \--* CNS_INT int -1 New refCnts for V08: refCnt = 6, refCntWtd = 25.50 New refCnts for V08: refCnt = 7, refCntWtd = 33.50 STMT00187 ( 0x467[E-] ... 0x46B ) [000873] -A---+----- * ASG int [000872] D----+-N--- +--* LCL_VAR int V14 loc10 [000871] -----+----- \--* ADD int [000869] -----+----- +--* LCL_VAR int V14 loc10 [000870] -----+----- \--* CNS_INT int -1 New refCnts for V14: refCnt = 6, refCntWtd = 12 New refCnts for V14: refCnt = 7, refCntWtd = 20 *** marking local variables in block BB135 (weight=16 ) STMT00177 ( 0x46D[E-] ... 0x470 ) [000828] -----+----- * JTRUE void [000827] J----+-N--- \--* GT int [000825] -----+----- +--* LCL_VAR int V14 loc10 [000826] -----+----- \--* CNS_INT int 0 New refCnts for V14: refCnt = 8, refCntWtd = 36 *** marking local variables in block BB136 (weight=2 ) STMT00071 ( 0x472[E-] ... 0x476 ) [000278] -----+----- * JTRUE void [000277] N----+-N-U- \--* GT int [000275] -----+----- +--* LCL_VAR int V18 loc14 [000276] -----+----- \--* CNS_INT int 69 New refCnts for V18: refCnt = 14, refCntWtd = 160 *** marking local variables in block BB137 (weight=2 ) STMT00129 ( 0x478[E-] ... 0x47D ) [000596] -----+----- * SWITCH void [000595] -----+----- \--* ADD int [000593] -----+----- +--* LCL_VAR int V18 loc14 [000594] -----+----- \--* CNS_INT int -34 New refCnts for V18: refCnt = 15, refCntWtd = 162 *** marking local variables in block BB138 (weight=2 ) STMT00130 ( 0x49A[E-] ... 0x49F ) [000600] -----+----- * SWITCH void [000599] -----+----- \--* ADD int [000597] -----+----- +--* LCL_VAR int V18 loc14 [000598] -----+----- \--* CNS_INT int -44 New refCnts for V18: refCnt = 16, refCntWtd = 164 *** marking local variables in block BB139 (weight=2 ) STMT00131 ( 0x4B8[E-] ... 0x4BC ) [000604] -----+----- * JTRUE void [000603] J----+-N--- \--* EQ int [000601] -----+----- +--* LCL_VAR int V18 loc14 [000602] -----+----- \--* CNS_INT int 69 New refCnts for V18: refCnt = 17, refCntWtd = 166 *** marking local variables in block BB140 (weight=2 ) *** marking local variables in block BB141 (weight=2 ) STMT00072 ( 0x4C6[E-] ... 0x4CA ) [000282] -----+----- * JTRUE void [000281] J----+-N--- \--* EQ int [000279] -----+----- +--* LCL_VAR int V18 loc14 [000280] -----+----- \--* CNS_INT int 92 New refCnts for V18: refCnt = 18, refCntWtd = 168 *** marking local variables in block BB142 (weight=2 ) STMT00079 ( 0x4CF[E-] ... 0x4D3 ) [000322] -----+----- * JTRUE void [000321] J----+-N--- \--* EQ int [000319] -----+----- +--* LCL_VAR int V18 loc14 [000320] -----+----- \--* CNS_INT int 101 New refCnts for V18: refCnt = 19, refCntWtd = 170 *** marking local variables in block BB143 (weight=2 ) STMT00125 ( 0x4D8[E-] ... 0x4DF ) [000584] -----+----- * JTRUE void [000583] J----+-N--- \--* NE int [000581] -----+----- +--* LCL_VAR int V18 loc14 [000582] -----+----- \--* CNS_INT int 0x2030 New refCnts for V18: refCnt = 20, refCntWtd = 172 *** marking local variables in block BB144 (weight=2 ) STMT00429 ( 0x598[E-] ... ??? ) [002119] -A-XG+----- * ASG ref [002118] D----+-N--- +--* LCL_VAR ref V110 tmp70 [002066] ---XG+----- \--* IND ref [002849] -----+----- \--* ADD byref [000586] -----+----- +--* LCL_VAR ref V03 arg3 [002848] -----+----- \--* CNS_INT long 136 Fseq[] New refCnts for V110: refCnt = 1, refCntWtd = 4 V110 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V03: refCnt = 5, refCntWtd = 11.50 *** marking local variables in block BB145 (weight=2 ) STMT00141 ( 0x4E9[E-] ... 0x4EC ) [000642] -----+----- * JTRUE void [000641] J----+-N--- \--* GE int [000639] -----+----- +--* LCL_VAR int V14 loc10 [000640] -----+----- \--* CNS_INT int 0 New refCnts for V14: refCnt = 9, refCntWtd = 38 *** marking local variables in block BB146 (weight=2 ) STMT00160 ( 0x4EE[E-] ... 0x4F2 ) [000735] -A---+----- * ASG int [000734] D----+-N--- +--* LCL_VAR int V14 loc10 [000733] -----+----- \--* ADD int [000731] -----+----- +--* LCL_VAR int V14 loc10 [000732] -----+----- \--* CNS_INT int 1 New refCnts for V14: refCnt = 10, refCntWtd = 40 New refCnts for V14: refCnt = 11, refCntWtd = 42 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) [000739] -----+----- * JTRUE void [000738] J----+-N--- \--* LE int [000736] -----+----- +--* LCL_VAR int V08 loc4 [000737] -----+----- \--* LCL_VAR int V06 loc2 New refCnts for V08: refCnt = 8, refCntWtd = 35.50 New refCnts for V06: refCnt = 9, refCntWtd = 29.50 *** marking local variables in block BB147 (weight=2 ) STMT00164 ( 0x4F9[E-] ... 0x4FA ) [000749] -A---+----- * ASG int [000748] D----+-N--- +--* LCL_VAR int V58 tmp18 [000747] -----+----- \--* CNS_INT int 0 New refCnts for V58: refCnt = 1, refCntWtd = 2 V58 needs explicit zero init. Disqualified as a single-def register candidate. *** marking local variables in block BB148 (weight=2 ) STMT00162 ( 0x4FC[E-] ... 0x4FC ) [000742] -A---+----- * ASG int [000741] D----+-N--- +--* LCL_VAR int V58 tmp18 [000740] -----+----- \--* CNS_INT int 48 New refCnts for V58: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB149 (weight=2 ) STMT00163 ( ??? ... 0x4FE ) [000746] -A---+----- * ASG int [000745] D----+-N--- +--* LCL_VAR int V18 loc14 [002850] -----+----- \--* CAST int <- ushort <- int [000744] -----+----- \--* LCL_VAR int V58 tmp18 New refCnts for V18: refCnt = 21, refCntWtd = 174 New refCnts for V58: refCnt = 3, refCntWtd = 6 *** marking local variables in block BB150 (weight=2 ) STMT00142 ( 0x502[E-] ... 0x505 ) [000647] ---XG+----- * JTRUE void [000646] J--XG+-N--- \--* NE int [000644] ---XG+----- +--* IND ubyte [000643] -----+----- | \--* LCL_VAR long V36 loc32 [000645] -----+----- \--* CNS_INT int 0 New refCnts for V36: refCnt = 6, refCntWtd = 35 *** marking local variables in block BB151 (weight=2 ) STMT00157 ( 0x507[E-] ... 0x50A ) [000722] -----+----- * JTRUE void [000721] J----+-N--- \--* GT int [000719] -----+----- +--* LCL_VAR int V08 loc4 [000720] -----+----- \--* LCL_VAR int V07 loc3 New refCnts for V08: refCnt = 9, refCntWtd = 37.50 New refCnts for V07: refCnt = 6, refCntWtd = 20.50 *** marking local variables in block BB152 (weight=2 ) STMT00159 ( 0x50C[E-] ... 0x50D ) [000729] -A---+----- * ASG int [000728] D----+-N--- +--* LCL_VAR int V57 tmp17 [000727] -----+----- \--* CNS_INT int 0 New refCnts for V57: refCnt = 1, refCntWtd = 2 V57 needs explicit zero init. Disqualified as a single-def register candidate. *** marking local variables in block BB153 (weight=2 ) STMT00158 ( 0x50F[E-] ... 0x511 ) [000725] -A---+----- * ASG int [000724] D----+-N--- +--* LCL_VAR int V57 tmp17 [000723] -----+----- \--* CNS_INT int 48 New refCnts for V57: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB154 (weight=2 ) STMT00144 ( 0x513[E-] ... 0x518 ) [000656] -A---+----- * ASG long [000655] D----+-N--- +--* LCL_VAR long V56 tmp16 [000648] -----+----- \--* LCL_VAR long V36 loc32 New refCnts for V56: refCnt = 1, refCntWtd = 4 V56 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V36: refCnt = 7, refCntWtd = 37 STMT00143 ( 0x513[E-] ... ??? ) [000654] -A---+----- * ASG long [000653] D----+-N--- +--* LCL_VAR long V36 loc32 [000652] -----+----- \--* ADD long [000649] -----+----- +--* LCL_VAR long V36 loc32 [000651] -----+----- \--* CNS_INT long 1 New refCnts for V36: refCnt = 8, refCntWtd = 39 New refCnts for V36: refCnt = 9, refCntWtd = 41 STMT00145 ( ??? ... 0x51A ) [000660] -A-XG+----- * ASG int [000659] D----+-N--- +--* LCL_VAR int V57 tmp17 [000658] ---XG+----- \--* IND ubyte [000657] -----+----- \--* LCL_VAR long V56 tmp16 New refCnts for V57: refCnt = 3, refCntWtd = 6 New refCnts for V56: refCnt = 2, refCntWtd = 8 *** marking local variables in block BB155 (weight=2 ) STMT00146 ( ??? ... 0x51B ) [000664] -A---+----- * ASG int [000663] D----+-N--- +--* LCL_VAR int V18 loc14 [002851] -----+----- \--* CAST int <- ushort <- int [000662] -----+----- \--* LCL_VAR int V57 tmp17 New refCnts for V18: refCnt = 22, refCntWtd = 176 New refCnts for V57: refCnt = 4, refCntWtd = 8 *** marking local variables in block BB156 (weight=2 ) STMT00147 ( 0x51D[E-] ... 0x51F ) [000668] -----+----- * JTRUE void [000667] J----+-N--- \--* EQ int [000665] -----+----- +--* LCL_VAR int V18 loc14 [000666] -----+----- \--* CNS_INT int 0 New refCnts for V18: refCnt = 23, refCntWtd = 178 *** marking local variables in block BB157 (weight=2 ) STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] [001905] -A-XG+----- * ASG int [001904] D----+-N--- +--* LCL_VAR int V99 tmp59 [001903] ---XG+----- \--* IND int [002853] -----+----- \--* ADD byref [000674] -----+----- +--* LCL_VAR byref V00 arg0 [002852] -----+----- \--* CNS_INT long 8 New refCnts for V99: refCnt = 1, refCntWtd = 2 V99 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 14, refCntWtd = 61 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] [001912] ---XG+----- * JTRUE void [001911] N--XG+-N-U- \--* GE int [001906] -----+----- +--* LCL_VAR int V99 tmp59 [001942] ---XG+----- \--* IND int [002857] -----+----- \--* ADD byref [001907] -----+----- +--* LCL_VAR byref V00 arg0 [002856] -----+----- \--* CNS_INT long 24 New refCnts for V99: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 15, refCntWtd = 63 *** marking local variables in block BB158 (weight=2 ) STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] [001920] -A-XG+----- * ASG byref [001919] D----+-N--- +--* LCL_VAR byref V100 tmp60 [002864] ---X-+-N--- \--* COMMA byref [002860] ---X-+----- +--* NULLCHECK byte [002859] -----+----- | \--* LCL_VAR byref V00 arg0 [002863] -----+----- \--* ADD byref [002861] -----+----- +--* LCL_VAR byref V00 arg0 [002862] -----+----- \--* CNS_INT long 16 New refCnts for V100: refCnt = 1, refCntWtd = 4 V100 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 16, refCntWtd = 65 New refCnts for V00: refCnt = 17, refCntWtd = 67 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] [001933] -A-XG+----- * ASG short [001930] ---XG+-N--- +--* COMMA short [001924] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001917] -----+----- | | +--* LCL_VAR int V99 tmp59 [001923] ---XG+----- | | \--* IND int [002866] -----+----- | | \--* ADD byref [001922] -----+----- | | +--* LCL_VAR byref V100 tmp60 [002865] -----+----- | | \--* CNS_INT long 8 [002867] ---XG+-N--- | \--* IND short [001929] ---XG+----- | \--* ADD byref [001928] ---XG+----- | +--* IND byref [001921] -----+----- | | \--* LCL_VAR byref V100 tmp60 [001927] -----+----- | \--* LSH long [001925] -----+---U- | +--* CAST long <- uint [001918] -----+----- | | \--* LCL_VAR int V99 tmp59 [001926] -----+----- | \--* CNS_INT long 1 [001931] -----+----- \--* LCL_VAR int V18 loc14 New refCnts for V99: refCnt = 3, refCntWtd = 6 New refCnts for V100: refCnt = 2, refCntWtd = 8 New refCnts for V100: refCnt = 3, refCntWtd = 12 New refCnts for V99: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 24, refCntWtd = 180 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] [001939] -A-XG+----- * ASG int [001938] ---XG+-N--- +--* IND int [002869] -----+----- | \--* ADD byref [001934] -----+----- | +--* LCL_VAR byref V00 arg0 [002868] -----+----- | \--* CNS_INT long 8 [001937] -----+----- \--* ADD int [001935] -----+----- +--* LCL_VAR int V99 tmp59 [001936] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 18, refCntWtd = 69 New refCnts for V99: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB159 (weight=2 ) STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] [001914] --CXG+----- * CALL r2r_ind void [001913] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000675] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [002870] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn New refCnts for V00: refCnt = 19, refCntWtd = 71 New refCnts for V18: refCnt = 25, refCntWtd = 182 *** marking local variables in block BB160 (weight=2 ) STMT00150 ( 0x529[E-] ... ??? ) [000680] -----+----- * JTRUE void [000679] J----+-N--- \--* EQ int [000677] -----+----- +--* LCL_VAR int V12 loc8 [000678] -----+----- \--* CNS_INT int 0 New refCnts for V12: refCnt = 6, refCntWtd = 29 *** marking local variables in block BB161 (weight=2 ) STMT00151 ( 0x52D[E-] ... 0x530 ) [000684] -----+----- * JTRUE void [000683] J----+-N--- \--* LE int [000681] -----+----- +--* LCL_VAR int V08 loc4 [000682] -----+----- \--* CNS_INT int 1 New refCnts for V08: refCnt = 10, refCntWtd = 39.50 *** marking local variables in block BB162 (weight=2 ) STMT00152 ( 0x532[E-] ... 0x535 ) [000688] -----+----- * JTRUE void [000687] J----+-N--- \--* LT int [000685] -----+----- +--* LCL_VAR int V20 loc16 [000686] -----+----- \--* CNS_INT int 0 New refCnts for V20: refCnt = 12, refCntWtd = 63 *** marking local variables in block BB163 (weight=2 ) STMT00153 ( 0x537[E-] ... 0x545 ) [000708] ---XG+----- * JTRUE void [000707] N--XG+-N-U- \--* NE int [000689] -----+----- +--* LCL_VAR int V08 loc4 [000706] ---XG+----- \--* ADD int [000703] ---XG+----- +--* COMMA int [000697] ---X-+----- | +--* BOUNDS_CHECK_Rng void [000692] -----+----- | | +--* LCL_VAR int V20 loc16 [000696] -----+----- | | \--* LCL_VAR int V144 tmp104 [002871] ---XG+----- | \--* IND int [000702] -----+----- | \--* ADD byref [000701] -----+----- | +--* LCL_VAR byref V143 tmp103 [000700] -----+----- | \--* LSH long [000698] -----+---U- | +--* CAST long <- uint [000693] -----+----- | | \--* LCL_VAR int V20 loc16 [000699] -----+----- | \--* CNS_INT long 2 [000705] -----+----- \--* CNS_INT int 1 New refCnts for V08: refCnt = 11, refCntWtd = 41.50 New refCnts for V20: refCnt = 13, refCntWtd = 65 New refCnts for V144: refCnt = 9, refCntWtd = 27 New refCnts for V143: refCnt = 7, refCntWtd = 21 New refCnts for V20: refCnt = 14, refCntWtd = 67 *** marking local variables in block BB164 (weight=2 ) STMT00407 ( 0x547[E-] ... ??? ) [001999] -A-XG+----- * ASG ref [001998] D----+-N--- +--* LCL_VAR ref V102 tmp62 [001946] ---XG+----- \--* IND ref [002873] -----+----- \--* ADD byref [000710] -----+----- +--* LCL_VAR ref V03 arg3 [002872] -----+----- \--* CNS_INT long 56 Fseq[] New refCnts for V102: refCnt = 1, refCntWtd = 4 V102 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V03: refCnt = 6, refCntWtd = 13.50 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] [001951] -----+----- * JTRUE void [001950] J----+-N--- \--* EQ int [001948] -----+----- +--* LCL_VAR ref V102 tmp62 [001949] -----+----- \--* CNS_INT ref null New refCnts for V102: refCnt = 2, refCntWtd = 8 *** marking local variables in block BB165 (weight=2 ) STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] [001954] -A-XG+----- * ASG int [001953] D----+-N--- +--* LCL_VAR int V103 tmp63 [001952] ---XG+----- \--* IND int [002875] -----+----- \--* ADD byref [000709] -----+----- +--* LCL_VAR byref V00 arg0 [002874] -----+----- \--* CNS_INT long 8 New refCnts for V103: refCnt = 1, refCntWtd = 2 V103 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 20, refCntWtd = 73 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] [001959] ---X-+----- * JTRUE void [001958] N--X-+-N-U- \--* NE int [001956] ---X-+----- +--* ARR_LENGTH int [001955] -----+----- | \--* LCL_VAR ref V102 tmp62 [001957] -----+----- \--* CNS_INT int 1 New refCnts for V102: refCnt = 3, refCntWtd = 12 *** marking local variables in block BB166 (weight=2 ) STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] [001969] ---XG+----- * JTRUE void [001968] N--XG+-N-U- \--* GE int [001963] -----+----- +--* LCL_VAR int V103 tmp63 [002002] ---XG+----- \--* IND int [002879] -----+----- \--* ADD byref [001964] -----+----- +--* LCL_VAR byref V00 arg0 [002878] -----+----- \--* CNS_INT long 24 New refCnts for V103: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 21, refCntWtd = 75 *** marking local variables in block BB167 (weight=2 ) STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] [001975] -A-XG+----- * ASG byref [001974] D----+-N--- +--* LCL_VAR byref V104 tmp64 [002886] ---X-+-N--- \--* COMMA byref [002882] ---X-+----- +--* NULLCHECK byte [002881] -----+----- | \--* LCL_VAR byref V00 arg0 [002885] -----+----- \--* ADD byref [002883] -----+----- +--* LCL_VAR byref V00 arg0 [002884] -----+----- \--* CNS_INT long 16 New refCnts for V104: refCnt = 1, refCntWtd = 4 V104 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 22, refCntWtd = 77 New refCnts for V00: refCnt = 23, refCntWtd = 79 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] [001991] -A-XG+----- * ASG short [001985] ---XG+-N--- +--* COMMA short [001979] ---XG+----- | +--* BOUNDS_CHECK_Rng void [001972] -----+----- | | +--* LCL_VAR int V103 tmp63 [001978] ---XG+----- | | \--* IND int [002888] -----+----- | | \--* ADD byref [001977] -----+----- | | +--* LCL_VAR byref V104 tmp64 [002887] -----+----- | | \--* CNS_INT long 8 [002889] ---XG+-N--- | \--* IND short [001984] ---XG+----- | \--* ADD byref [001983] ---XG+----- | +--* IND byref [001976] -----+----- | | \--* LCL_VAR byref V104 tmp64 [001982] -----+----- | \--* LSH long [001980] -----+---U- | +--* CAST long <- uint [001973] -----+----- | | \--* LCL_VAR int V103 tmp63 [001981] -----+----- | \--* CNS_INT long 1 [002900] ---XG+----- \--* COMMA ushort [002893] ---X-+----- +--* BOUNDS_CHECK_Rng void [001987] -----+----- | +--* CNS_INT int 0 [002892] ---X-+----- | \--* ARR_LENGTH int [001986] -----+----- | \--* LCL_VAR ref V102 tmp62 [002902] n---G+----- \--* IND ushort [002899] -----+----- \--* ARR_ADDR byref ushort[] [002897] -----+----- \--* ADD byref [002890] -----+----- +--* LCL_VAR ref V102 tmp62 [002896] -----+----- \--* CNS_INT long 12 New refCnts for V103: refCnt = 3, refCntWtd = 6 New refCnts for V104: refCnt = 2, refCntWtd = 8 New refCnts for V104: refCnt = 3, refCntWtd = 12 New refCnts for V103: refCnt = 4, refCntWtd = 8 New refCnts for V102: refCnt = 4, refCntWtd = 16 New refCnts for V102: refCnt = 5, refCntWtd = 20 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] [001997] -A-XG+----- * ASG int [001996] ---XG+-N--- +--* IND int [002904] -----+----- | \--* ADD byref [001992] -----+----- | +--* LCL_VAR byref V00 arg0 [002903] -----+----- | \--* CNS_INT long 8 [001995] -----+----- \--* ADD int [001993] -----+----- +--* LCL_VAR int V103 tmp63 [001994] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 24, refCntWtd = 81 New refCnts for V103: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB168 (weight=2 ) STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] [001962] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [001960] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [001961] -----+----- arg2 in x1 +--* LCL_VAR ref V102 tmp62 [002905] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn New refCnts for V00: refCnt = 25, refCntWtd = 83 New refCnts for V102: refCnt = 6, refCntWtd = 24 *** marking local variables in block BB169 (weight=2 ) STMT00156 ( 0x553[E-] ... ??? ) [000718] -A---+----- * ASG int [000717] D----+-N--- +--* LCL_VAR int V20 loc16 [000716] -----+----- \--* ADD int [000714] -----+----- +--* LCL_VAR int V20 loc16 [000715] -----+----- \--* CNS_INT int -1 New refCnts for V20: refCnt = 15, refCntWtd = 69 New refCnts for V20: refCnt = 16, refCntWtd = 71 *** marking local variables in block BB170 (weight=2 ) STMT00148 ( 0x559[E-] ... 0x55D ) [000673] -A---+----- * ASG int [000672] D----+-N--- +--* LCL_VAR int V08 loc4 [000671] -----+----- \--* ADD int [000669] -----+----- +--* LCL_VAR int V08 loc4 [000670] -----+----- \--* CNS_INT int -1 New refCnts for V08: refCnt = 12, refCntWtd = 43.50 New refCnts for V08: refCnt = 13, refCntWtd = 45.50 *** marking local variables in block BB171 (weight=2 ) STMT00132 ( 0x564[E-] ... 0x56C ) [000612] -----+----- * JTRUE void [000611] J----+-N--- \--* NE int [000609] -----+----- +--* OR int [000607] -----+----- | +--* NE int [000605] -----+----- | | +--* LCL_VAR int V08 loc4 [000606] -----+----- | | \--* CNS_INT int 0 [000608] -----+----- | \--* LCL_VAR int V21 loc17 [000610] -----+----- \--* CNS_INT int 0 New refCnts for V08: refCnt = 14, refCntWtd = 47.50 New refCnts for V21: refCnt = 2, refCntWtd = 3 *** marking local variables in block BB172 (weight=2 ) STMT00133 ( 0x571[E-] ... 0x573 ) [000616] -----+----- * JTRUE void [000615] J----+-N--- \--* LT int [000613] -----+----- +--* LCL_VAR int V07 loc3 [000614] -----+----- \--* CNS_INT int 0 New refCnts for V07: refCnt = 7, refCntWtd = 22.50 *** marking local variables in block BB173 (weight=2 ) STMT00137 ( 0x575[E-] ... 0x577 ) [000628] -----+----- * JTRUE void [000627] J----+-N--- \--* GE int [000625] -----+----- +--* LCL_VAR int V05 loc1 [000626] -----+----- \--* LCL_VAR int V04 loc0 New refCnts for V05: refCnt = 17, refCntWtd = 53 New refCnts for V04: refCnt = 15, refCntWtd = 96 *** marking local variables in block BB174 (weight=2 ) STMT00138 ( 0x57C[E-] ... 0x57F ) [000633] ---XG+----- * JTRUE void [000632] J--XG+-N--- \--* EQ int [000630] ---XG+----- +--* IND ubyte [000629] -----+----- | \--* LCL_VAR long V36 loc32 [000631] -----+----- \--* CNS_INT int 0 New refCnts for V36: refCnt = 10, refCntWtd = 43 *** marking local variables in block BB175 (weight=2 ) STMT00418 ( 0x584[E-] ... ??? ) [002059] -A-XG+----- * ASG ref [002058] D----+-N--- +--* LCL_VAR ref V106 tmp66 [002006] ---XG+----- \--* IND ref [002907] -----+----- \--* ADD byref [000618] -----+----- +--* LCL_VAR ref V03 arg3 [002906] -----+----- \--* CNS_INT long 48 Fseq[] New refCnts for V106: refCnt = 1, refCntWtd = 4 V106 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V03: refCnt = 7, refCntWtd = 15.50 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] [002011] -----+----- * JTRUE void [002010] J----+-N--- \--* EQ int [002008] -----+----- +--* LCL_VAR ref V106 tmp66 [002009] -----+----- \--* CNS_INT ref null New refCnts for V106: refCnt = 2, refCntWtd = 8 *** marking local variables in block BB176 (weight=2 ) STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] [002014] -A-XG+----- * ASG int [002013] D----+-N--- +--* LCL_VAR int V107 tmp67 [002012] ---XG+----- \--* IND int [002909] -----+----- \--* ADD byref [000617] -----+----- +--* LCL_VAR byref V00 arg0 [002908] -----+----- \--* CNS_INT long 8 New refCnts for V107: refCnt = 1, refCntWtd = 2 V107 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 26, refCntWtd = 85 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] [002019] ---X-+----- * JTRUE void [002018] N--X-+-N-U- \--* NE int [002016] ---X-+----- +--* ARR_LENGTH int [002015] -----+----- | \--* LCL_VAR ref V106 tmp66 [002017] -----+----- \--* CNS_INT int 1 New refCnts for V106: refCnt = 3, refCntWtd = 12 *** marking local variables in block BB177 (weight=2 ) STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] [002029] ---XG+----- * JTRUE void [002028] N--XG+-N-U- \--* GE int [002023] -----+----- +--* LCL_VAR int V107 tmp67 [002062] ---XG+----- \--* IND int [002913] -----+----- \--* ADD byref [002024] -----+----- +--* LCL_VAR byref V00 arg0 [002912] -----+----- \--* CNS_INT long 24 New refCnts for V107: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 27, refCntWtd = 87 *** marking local variables in block BB178 (weight=2 ) STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] [002035] -A-XG+----- * ASG byref [002034] D----+-N--- +--* LCL_VAR byref V108 tmp68 [002920] ---X-+-N--- \--* COMMA byref [002916] ---X-+----- +--* NULLCHECK byte [002915] -----+----- | \--* LCL_VAR byref V00 arg0 [002919] -----+----- \--* ADD byref [002917] -----+----- +--* LCL_VAR byref V00 arg0 [002918] -----+----- \--* CNS_INT long 16 New refCnts for V108: refCnt = 1, refCntWtd = 4 V108 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 28, refCntWtd = 89 New refCnts for V00: refCnt = 29, refCntWtd = 91 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] [002051] -A-XG+----- * ASG short [002045] ---XG+-N--- +--* COMMA short [002039] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002032] -----+----- | | +--* LCL_VAR int V107 tmp67 [002038] ---XG+----- | | \--* IND int [002922] -----+----- | | \--* ADD byref [002037] -----+----- | | +--* LCL_VAR byref V108 tmp68 [002921] -----+----- | | \--* CNS_INT long 8 [002923] ---XG+-N--- | \--* IND short [002044] ---XG+----- | \--* ADD byref [002043] ---XG+----- | +--* IND byref [002036] -----+----- | | \--* LCL_VAR byref V108 tmp68 [002042] -----+----- | \--* LSH long [002040] -----+---U- | +--* CAST long <- uint [002033] -----+----- | | \--* LCL_VAR int V107 tmp67 [002041] -----+----- | \--* CNS_INT long 1 [002934] ---XG+----- \--* COMMA ushort [002927] ---X-+----- +--* BOUNDS_CHECK_Rng void [002047] -----+----- | +--* CNS_INT int 0 [002926] ---X-+----- | \--* ARR_LENGTH int [002046] -----+----- | \--* LCL_VAR ref V106 tmp66 [002936] n---G+----- \--* IND ushort [002933] -----+----- \--* ARR_ADDR byref ushort[] [002931] -----+----- \--* ADD byref [002924] -----+----- +--* LCL_VAR ref V106 tmp66 [002930] -----+----- \--* CNS_INT long 12 New refCnts for V107: refCnt = 3, refCntWtd = 6 New refCnts for V108: refCnt = 2, refCntWtd = 8 New refCnts for V108: refCnt = 3, refCntWtd = 12 New refCnts for V107: refCnt = 4, refCntWtd = 8 New refCnts for V106: refCnt = 4, refCntWtd = 16 New refCnts for V106: refCnt = 5, refCntWtd = 20 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] [002057] -A-XG+----- * ASG int [002056] ---XG+-N--- +--* IND int [002938] -----+----- | \--* ADD byref [002052] -----+----- | +--* LCL_VAR byref V00 arg0 [002937] -----+----- | \--* CNS_INT long 8 [002055] -----+----- \--* ADD int [002053] -----+----- +--* LCL_VAR int V107 tmp67 [002054] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 30, refCntWtd = 93 New refCnts for V107: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB179 (weight=2 ) STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] [002022] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002020] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002021] -----+----- arg2 in x1 +--* LCL_VAR ref V106 tmp66 [002939] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn New refCnts for V00: refCnt = 31, refCntWtd = 95 New refCnts for V106: refCnt = 6, refCntWtd = 24 *** marking local variables in block BB180 (weight=2 ) STMT00136 ( 0x590[E-] ... ??? ) [000624] -A---+----- * ASG int [000623] D----+-N--- +--* LCL_VAR int V21 loc17 [002940] -----+----- \--* CNS_INT int 1 New refCnts for V21: refCnt = 3, refCntWtd = 5 *** marking local variables in block BB181 (weight=2 ) STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] [002071] -----+----- * JTRUE void [002070] J----+-N--- \--* EQ int [002068] -----+----- +--* LCL_VAR ref V110 tmp70 [002069] -----+----- \--* CNS_INT ref null New refCnts for V110: refCnt = 2, refCntWtd = 8 *** marking local variables in block BB182 (weight=2 ) STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] [002074] -A-XG+----- * ASG int [002073] D----+-N--- +--* LCL_VAR int V111 tmp71 [002072] ---XG+----- \--* IND int [002942] -----+----- \--* ADD byref [000585] -----+----- +--* LCL_VAR byref V00 arg0 [002941] -----+----- \--* CNS_INT long 8 New refCnts for V111: refCnt = 1, refCntWtd = 2 V111 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 32, refCntWtd = 97 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] [002079] ---X-+----- * JTRUE void [002078] N--X-+-N-U- \--* NE int [002076] ---X-+----- +--* ARR_LENGTH int [002075] -----+----- | \--* LCL_VAR ref V110 tmp70 [002077] -----+----- \--* CNS_INT int 1 New refCnts for V110: refCnt = 3, refCntWtd = 12 *** marking local variables in block BB183 (weight=2 ) STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] [002089] ---XG+----- * JTRUE void [002088] N--XG+-N-U- \--* GE int [002083] -----+----- +--* LCL_VAR int V111 tmp71 [002122] ---XG+----- \--* IND int [002946] -----+----- \--* ADD byref [002084] -----+----- +--* LCL_VAR byref V00 arg0 [002945] -----+----- \--* CNS_INT long 24 New refCnts for V111: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 33, refCntWtd = 99 *** marking local variables in block BB184 (weight=2 ) STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] [002095] -A-XG+----- * ASG byref [002094] D----+-N--- +--* LCL_VAR byref V112 tmp72 [002953] ---X-+-N--- \--* COMMA byref [002949] ---X-+----- +--* NULLCHECK byte [002948] -----+----- | \--* LCL_VAR byref V00 arg0 [002952] -----+----- \--* ADD byref [002950] -----+----- +--* LCL_VAR byref V00 arg0 [002951] -----+----- \--* CNS_INT long 16 New refCnts for V112: refCnt = 1, refCntWtd = 4 V112 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 34, refCntWtd = 101 New refCnts for V00: refCnt = 35, refCntWtd = 103 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] [002111] -A-XG+----- * ASG short [002105] ---XG+-N--- +--* COMMA short [002099] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002092] -----+----- | | +--* LCL_VAR int V111 tmp71 [002098] ---XG+----- | | \--* IND int [002955] -----+----- | | \--* ADD byref [002097] -----+----- | | +--* LCL_VAR byref V112 tmp72 [002954] -----+----- | | \--* CNS_INT long 8 [002956] ---XG+-N--- | \--* IND short [002104] ---XG+----- | \--* ADD byref [002103] ---XG+----- | +--* IND byref [002096] -----+----- | | \--* LCL_VAR byref V112 tmp72 [002102] -----+----- | \--* LSH long [002100] -----+---U- | +--* CAST long <- uint [002093] -----+----- | | \--* LCL_VAR int V111 tmp71 [002101] -----+----- | \--* CNS_INT long 1 [002967] ---XG+----- \--* COMMA ushort [002960] ---X-+----- +--* BOUNDS_CHECK_Rng void [002107] -----+----- | +--* CNS_INT int 0 [002959] ---X-+----- | \--* ARR_LENGTH int [002106] -----+----- | \--* LCL_VAR ref V110 tmp70 [002969] n---G+----- \--* IND ushort [002966] -----+----- \--* ARR_ADDR byref ushort[] [002964] -----+----- \--* ADD byref [002957] -----+----- +--* LCL_VAR ref V110 tmp70 [002963] -----+----- \--* CNS_INT long 12 New refCnts for V111: refCnt = 3, refCntWtd = 6 New refCnts for V112: refCnt = 2, refCntWtd = 8 New refCnts for V112: refCnt = 3, refCntWtd = 12 New refCnts for V111: refCnt = 4, refCntWtd = 8 New refCnts for V110: refCnt = 4, refCntWtd = 16 New refCnts for V110: refCnt = 5, refCntWtd = 20 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] [002117] -A-XG+----- * ASG int [002116] ---XG+-N--- +--* IND int [002971] -----+----- | \--* ADD byref [002112] -----+----- | +--* LCL_VAR byref V00 arg0 [002970] -----+----- | \--* CNS_INT long 8 [002115] -----+----- \--* ADD int [002113] -----+----- +--* LCL_VAR int V111 tmp71 [002114] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 36, refCntWtd = 105 New refCnts for V111: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB185 (weight=2 ) STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] [002082] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002080] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002081] -----+----- arg2 in x1 +--* LCL_VAR ref V110 tmp70 [002972] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn New refCnts for V00: refCnt = 37, refCntWtd = 107 New refCnts for V110: refCnt = 6, refCntWtd = 24 *** marking local variables in block BB186 (weight=2 ) STMT00440 ( 0x5A9[E-] ... ??? ) [002179] -A-XG+----- * ASG ref [002178] D----+-N--- +--* LCL_VAR ref V114 tmp74 [002126] ---XG+----- \--* IND ref [002974] -----+----- \--* ADD byref [000635] -----+----- +--* LCL_VAR ref V03 arg3 [002973] -----+----- \--* CNS_INT long 128 Fseq[] New refCnts for V114: refCnt = 1, refCntWtd = 4 V114 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V03: refCnt = 8, refCntWtd = 17.50 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002131] -----+----- * JTRUE void [002130] J----+-N--- \--* EQ int [002128] -----+----- +--* LCL_VAR ref V114 tmp74 [002129] -----+----- \--* CNS_INT ref null New refCnts for V114: refCnt = 2, refCntWtd = 8 *** marking local variables in block BB187 (weight=2 ) STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002134] -A-XG+----- * ASG int [002133] D----+-N--- +--* LCL_VAR int V115 tmp75 [002132] ---XG+----- \--* IND int [002976] -----+----- \--* ADD byref [000634] -----+----- +--* LCL_VAR byref V00 arg0 [002975] -----+----- \--* CNS_INT long 8 New refCnts for V115: refCnt = 1, refCntWtd = 2 V115 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 38, refCntWtd = 109 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002139] ---X-+----- * JTRUE void [002138] N--X-+-N-U- \--* NE int [002136] ---X-+----- +--* ARR_LENGTH int [002135] -----+----- | \--* LCL_VAR ref V114 tmp74 [002137] -----+----- \--* CNS_INT int 1 New refCnts for V114: refCnt = 3, refCntWtd = 12 *** marking local variables in block BB188 (weight=2 ) STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002149] ---XG+----- * JTRUE void [002148] N--XG+-N-U- \--* GE int [002143] -----+----- +--* LCL_VAR int V115 tmp75 [002182] ---XG+----- \--* IND int [002980] -----+----- \--* ADD byref [002144] -----+----- +--* LCL_VAR byref V00 arg0 [002979] -----+----- \--* CNS_INT long 24 New refCnts for V115: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 39, refCntWtd = 111 *** marking local variables in block BB189 (weight=2 ) STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002155] -A-XG+----- * ASG byref [002154] D----+-N--- +--* LCL_VAR byref V116 tmp76 [002987] ---X-+-N--- \--* COMMA byref [002983] ---X-+----- +--* NULLCHECK byte [002982] -----+----- | \--* LCL_VAR byref V00 arg0 [002986] -----+----- \--* ADD byref [002984] -----+----- +--* LCL_VAR byref V00 arg0 [002985] -----+----- \--* CNS_INT long 16 New refCnts for V116: refCnt = 1, refCntWtd = 4 V116 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 40, refCntWtd = 113 New refCnts for V00: refCnt = 41, refCntWtd = 115 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] [002171] -A-XG+----- * ASG short [002165] ---XG+-N--- +--* COMMA short [002159] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002152] -----+----- | | +--* LCL_VAR int V115 tmp75 [002158] ---XG+----- | | \--* IND int [002989] -----+----- | | \--* ADD byref [002157] -----+----- | | +--* LCL_VAR byref V116 tmp76 [002988] -----+----- | | \--* CNS_INT long 8 [002990] ---XG+-N--- | \--* IND short [002164] ---XG+----- | \--* ADD byref [002163] ---XG+----- | +--* IND byref [002156] -----+----- | | \--* LCL_VAR byref V116 tmp76 [002162] -----+----- | \--* LSH long [002160] -----+---U- | +--* CAST long <- uint [002153] -----+----- | | \--* LCL_VAR int V115 tmp75 [002161] -----+----- | \--* CNS_INT long 1 [003001] ---XG+----- \--* COMMA ushort [002994] ---X-+----- +--* BOUNDS_CHECK_Rng void [002167] -----+----- | +--* CNS_INT int 0 [002993] ---X-+----- | \--* ARR_LENGTH int [002166] -----+----- | \--* LCL_VAR ref V114 tmp74 [003003] n---G+----- \--* IND ushort [003000] -----+----- \--* ARR_ADDR byref ushort[] [002998] -----+----- \--* ADD byref [002991] -----+----- +--* LCL_VAR ref V114 tmp74 [002997] -----+----- \--* CNS_INT long 12 New refCnts for V115: refCnt = 3, refCntWtd = 6 New refCnts for V116: refCnt = 2, refCntWtd = 8 New refCnts for V116: refCnt = 3, refCntWtd = 12 New refCnts for V115: refCnt = 4, refCntWtd = 8 New refCnts for V114: refCnt = 4, refCntWtd = 16 New refCnts for V114: refCnt = 5, refCntWtd = 20 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002177] -A-XG+----- * ASG int [002176] ---XG+-N--- +--* IND int [003005] -----+----- | \--* ADD byref [002172] -----+----- | +--* LCL_VAR byref V00 arg0 [003004] -----+----- | \--* CNS_INT long 8 [002175] -----+----- \--* ADD int [002173] -----+----- +--* LCL_VAR int V115 tmp75 [002174] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 42, refCntWtd = 117 New refCnts for V115: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB190 (weight=2 ) STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] [002142] --CXG+----- * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this [002140] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002141] -----+----- arg2 in x1 +--* LCL_VAR ref V114 tmp74 [003006] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn New refCnts for V00: refCnt = 43, refCntWtd = 119 New refCnts for V114: refCnt = 6, refCntWtd = 24 *** marking local variables in block BB191 (weight=8 ) STMT00174 ( 0x5BA[E-] ... 0x5C2 ) [000812] -A---+----- * ASG int [000811] D----+-N--- +--* LCL_VAR int V59 tmp19 [000805] -----+----- \--* LCL_VAR int V16 loc12 New refCnts for V59: refCnt = 1, refCntWtd = 16 V59 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 28, refCntWtd = 733 STMT00173 ( 0x5BA[E-] ... ??? ) [000810] -A---+----- * ASG int [000809] D----+-N--- +--* LCL_VAR int V16 loc12 [000808] -----+----- \--* ADD int [000806] -----+----- +--* LCL_VAR int V16 loc12 [000807] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 29, refCntWtd = 741 New refCnts for V16: refCnt = 30, refCntWtd = 749 STMT00449 ( ??? ... ??? ) [002225] -A-XG+----- * ASG ushort [002224] D----+-N--- +--* LCL_VAR int V119 tmp79 [000819] ---XG+----- \--* IND ushort [000818] -----+----- \--* ADD long [000804] -----+----- +--* LCL_VAR long V34 loc30 [000817] -----+----- \--* LSH long [000814] -----+----- +--* CAST long <- int [000813] -----+----- | \--* LCL_VAR int V59 tmp19 [000816] -----+----- \--* CNS_INT long 1 New refCnts for V119: refCnt = 1, refCntWtd = 16 V119 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V34: refCnt = 2, refCntWtd = 9 New refCnts for V59: refCnt = 2, refCntWtd = 32 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002188] -A-XG+----- * ASG int [002187] D----+-N--- +--* LCL_VAR int V118 tmp78 [002186] ---XG+----- \--* IND int [003008] -----+----- \--* ADD byref [000803] -----+----- +--* LCL_VAR byref V00 arg0 [003007] -----+----- \--* CNS_INT long 8 New refCnts for V118: refCnt = 1, refCntWtd = 8 V118 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 44, refCntWtd = 127 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002195] ---XG+----- * JTRUE void [002194] N--XG+-N-U- \--* GE int [002189] -----+----- +--* LCL_VAR int V118 tmp78 [002228] ---XG+----- \--* IND int [003012] -----+----- \--* ADD byref [002190] -----+----- +--* LCL_VAR byref V00 arg0 [003011] -----+----- \--* CNS_INT long 24 New refCnts for V118: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 45, refCntWtd = 135 *** marking local variables in block BB192 (weight=8 ) STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002204] -A-XG+----- * ASG byref [002203] D----+-N--- +--* LCL_VAR byref V120 tmp80 [003019] ---X-+-N--- \--* COMMA byref [003015] ---X-+----- +--* NULLCHECK byte [003014] -----+----- | \--* LCL_VAR byref V00 arg0 [003018] -----+----- \--* ADD byref [003016] -----+----- +--* LCL_VAR byref V00 arg0 [003017] -----+----- \--* CNS_INT long 16 New refCnts for V120: refCnt = 1, refCntWtd = 16 V120 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 46, refCntWtd = 143 New refCnts for V00: refCnt = 47, refCntWtd = 151 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? [002217] -A-XG+----- * ASG short [002214] ---XG+-N--- +--* COMMA short [002208] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002201] -----+----- | | +--* LCL_VAR int V118 tmp78 [002207] ---XG+----- | | \--* IND int [003021] -----+----- | | \--* ADD byref [002206] -----+----- | | +--* LCL_VAR byref V120 tmp80 [003020] -----+----- | | \--* CNS_INT long 8 [003022] ---XG+-N--- | \--* IND short [002213] ---XG+----- | \--* ADD byref [002212] ---XG+----- | +--* IND byref [002205] -----+----- | | \--* LCL_VAR byref V120 tmp80 [002211] -----+----- | \--* LSH long [002209] -----+---U- | +--* CAST long <- uint [002202] -----+----- | | \--* LCL_VAR int V118 tmp78 [002210] -----+----- | \--* CNS_INT long 1 [002215] -----+----- \--* LCL_VAR int V119 tmp79 New refCnts for V118: refCnt = 3, refCntWtd = 24 New refCnts for V120: refCnt = 2, refCntWtd = 32 New refCnts for V120: refCnt = 3, refCntWtd = 48 New refCnts for V118: refCnt = 4, refCntWtd = 32 New refCnts for V119: refCnt = 2, refCntWtd = 32 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002223] -A-XG+----- * ASG int [002222] ---XG+-N--- +--* IND int [003024] -----+----- | \--* ADD byref [002218] -----+----- | +--* LCL_VAR byref V00 arg0 [003023] -----+----- | \--* CNS_INT long 8 [002221] -----+----- \--* ADD int [002219] -----+----- +--* LCL_VAR int V118 tmp78 [002220] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 48, refCntWtd = 159 New refCnts for V118: refCnt = 5, refCntWtd = 40 *** marking local variables in block BB193 (weight=8 ) STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002198] --CXG+----- * CALL r2r_ind void [002196] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002197] -----+----- arg2 in x1 +--* LCL_VAR int V119 tmp79 [003025] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn New refCnts for V00: refCnt = 49, refCntWtd = 167 New refCnts for V119: refCnt = 3, refCntWtd = 48 *** marking local variables in block BB194 (weight=16 ) STMT00166 ( 0x5CE[E-] ... ??? ) [000757] -----+----- * JTRUE void [000756] J----+-N--- \--* GE int [000751] -----+----- +--* LCL_VAR int V16 loc12 [002234] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 31, refCntWtd = 765 New refCnts for V02: refCnt = 15, refCntWtd = 260 *** marking local variables in block BB195 (weight=16 ) STMT00171 ( 0x5D9[E-] ... 0x5E2 ) [000791] ---XG+----- * JTRUE void [000790] J--XG+-N--- \--* EQ int [000788] ---XG+----- +--* IND ushort [000787] -----+----- | \--* ADD long [000781] -----+----- | +--* LCL_VAR long V34 loc30 [000786] -----+----- | \--* LSH long [000783] -----+----- | +--* CAST long <- int [000782] -----+----- | | \--* LCL_VAR int V16 loc12 [000785] -----+----- | \--* CNS_INT long 1 [000789] -----+----- \--* CNS_INT int 0 New refCnts for V34: refCnt = 3, refCntWtd = 25 New refCnts for V16: refCnt = 32, refCntWtd = 781 *** marking local variables in block BB196 (weight=16 ) STMT00172 ( 0x5E4[E-] ... 0x5EF ) [000802] ---XG+----- * JTRUE void [000801] N--XG+-N-U- \--* NE int [000799] ---XG+----- +--* IND ushort [000798] -----+----- | \--* ADD long [000792] -----+----- | +--* LCL_VAR long V34 loc30 [000797] -----+----- | \--* LSH long [000794] -----+----- | +--* CAST long <- int [000793] -----+----- | | \--* LCL_VAR int V16 loc12 [000796] -----+----- | \--* CNS_INT long 1 [000800] -----+----- \--* LCL_VAR int V18 loc14 New refCnts for V34: refCnt = 4, refCntWtd = 41 New refCnts for V16: refCnt = 33, refCntWtd = 797 New refCnts for V18: refCnt = 26, refCntWtd = 198 *** marking local variables in block BB197 (weight=2 ) STMT00168 ( 0x5F1[E-] ... ??? ) [000764] -----+----- * JTRUE void [000763] J----+-N--- \--* GE int [000758] -----+----- +--* LCL_VAR int V16 loc12 [002238] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 34, refCntWtd = 799 New refCnts for V02: refCnt = 16, refCntWtd = 262 *** marking local variables in block BB198 (weight=2 ) STMT00169 ( 0x5FF[E-] ... 0x608 ) [000775] ---XG+----- * JTRUE void [000774] J--XG+-N--- \--* EQ int [000772] ---XG+----- +--* IND ushort [000771] -----+----- | \--* ADD long [000765] -----+----- | +--* LCL_VAR long V34 loc30 [000770] -----+----- | \--* LSH long [000767] -----+----- | +--* CAST long <- int [000766] -----+----- | | \--* LCL_VAR int V16 loc12 [000769] -----+----- | \--* CNS_INT long 1 [000773] -----+----- \--* CNS_INT int 0 New refCnts for V34: refCnt = 5, refCntWtd = 43 New refCnts for V16: refCnt = 35, refCntWtd = 801 *** marking local variables in block BB199 (weight=2 ) STMT00170 ( 0x60D[E-] ... 0x611 ) [000780] -A---+----- * ASG int [000779] D----+-N--- +--* LCL_VAR int V16 loc12 [000778] -----+----- \--* ADD int [000776] -----+----- +--* LCL_VAR int V16 loc12 [000777] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 36, refCntWtd = 803 New refCnts for V16: refCnt = 37, refCntWtd = 805 *** marking local variables in block BB200 (weight=2 ) STMT00074 ( 0x618[E-] ... ??? ) [000289] -----+----- * JTRUE void [000288] J----+-N--- \--* GE int [000283] -----+----- +--* LCL_VAR int V16 loc12 [002242] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 38, refCntWtd = 807 New refCnts for V02: refCnt = 17, refCntWtd = 264 *** marking local variables in block BB201 (weight=2 ) STMT00075 ( 0x626[E-] ... 0x62F ) [000300] ---XG+----- * JTRUE void [000299] J--XG+-N--- \--* EQ int [000297] ---XG+----- +--* IND ushort [000296] -----+----- | \--* ADD long [000290] -----+----- | +--* LCL_VAR long V34 loc30 [000295] -----+----- | \--* LSH long [000292] -----+----- | +--* CAST long <- int [000291] -----+----- | | \--* LCL_VAR int V16 loc12 [000294] -----+----- | \--* CNS_INT long 1 [000298] -----+----- \--* CNS_INT int 0 New refCnts for V34: refCnt = 6, refCntWtd = 45 New refCnts for V16: refCnt = 39, refCntWtd = 809 *** marking local variables in block BB202 (weight=2 ) STMT00077 ( 0x634[E-] ... 0x63C ) [000310] -A---+----- * ASG int [000309] D----+-N--- +--* LCL_VAR int V51 tmp11 [000303] -----+----- \--* LCL_VAR int V16 loc12 New refCnts for V51: refCnt = 1, refCntWtd = 4 V51 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 40, refCntWtd = 811 STMT00076 ( 0x634[E-] ... ??? ) [000308] -A---+----- * ASG int [000307] D----+-N--- +--* LCL_VAR int V16 loc12 [000306] -----+----- \--* ADD int [000304] -----+----- +--* LCL_VAR int V16 loc12 [000305] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 41, refCntWtd = 813 New refCnts for V16: refCnt = 42, refCntWtd = 815 STMT00458 ( ??? ... ??? ) [002283] -A-XG+----- * ASG ushort [002282] D----+-N--- +--* LCL_VAR int V123 tmp83 [000317] ---XG+----- \--* IND ushort [000316] -----+----- \--* ADD long [000302] -----+----- +--* LCL_VAR long V34 loc30 [000315] -----+----- \--* LSH long [000312] -----+----- +--* CAST long <- int [000311] -----+----- | \--* LCL_VAR int V51 tmp11 [000314] -----+----- \--* CNS_INT long 1 New refCnts for V123: refCnt = 1, refCntWtd = 4 V123 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V34: refCnt = 7, refCntWtd = 47 New refCnts for V51: refCnt = 2, refCntWtd = 8 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002246] -A-XG+----- * ASG int [002245] D----+-N--- +--* LCL_VAR int V122 tmp82 [002244] ---XG+----- \--* IND int [003027] -----+----- \--* ADD byref [000301] -----+----- +--* LCL_VAR byref V00 arg0 [003026] -----+----- \--* CNS_INT long 8 New refCnts for V122: refCnt = 1, refCntWtd = 2 V122 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 50, refCntWtd = 169 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002253] ---XG+----- * JTRUE void [002252] N--XG+-N-U- \--* GE int [002247] -----+----- +--* LCL_VAR int V122 tmp82 [002286] ---XG+----- \--* IND int [003031] -----+----- \--* ADD byref [002248] -----+----- +--* LCL_VAR byref V00 arg0 [003030] -----+----- \--* CNS_INT long 24 New refCnts for V122: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 51, refCntWtd = 171 *** marking local variables in block BB203 (weight=2 ) STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002262] -A-XG+----- * ASG byref [002261] D----+-N--- +--* LCL_VAR byref V124 tmp84 [003038] ---X-+-N--- \--* COMMA byref [003034] ---X-+----- +--* NULLCHECK byte [003033] -----+----- | \--* LCL_VAR byref V00 arg0 [003037] -----+----- \--* ADD byref [003035] -----+----- +--* LCL_VAR byref V00 arg0 [003036] -----+----- \--* CNS_INT long 16 New refCnts for V124: refCnt = 1, refCntWtd = 4 V124 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 52, refCntWtd = 173 New refCnts for V00: refCnt = 53, refCntWtd = 175 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? [002275] -A-XG+----- * ASG short [002272] ---XG+-N--- +--* COMMA short [002266] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002259] -----+----- | | +--* LCL_VAR int V122 tmp82 [002265] ---XG+----- | | \--* IND int [003040] -----+----- | | \--* ADD byref [002264] -----+----- | | +--* LCL_VAR byref V124 tmp84 [003039] -----+----- | | \--* CNS_INT long 8 [003041] ---XG+-N--- | \--* IND short [002271] ---XG+----- | \--* ADD byref [002270] ---XG+----- | +--* IND byref [002263] -----+----- | | \--* LCL_VAR byref V124 tmp84 [002269] -----+----- | \--* LSH long [002267] -----+---U- | +--* CAST long <- uint [002260] -----+----- | | \--* LCL_VAR int V122 tmp82 [002268] -----+----- | \--* CNS_INT long 1 [002273] -----+----- \--* LCL_VAR int V123 tmp83 New refCnts for V122: refCnt = 3, refCntWtd = 6 New refCnts for V124: refCnt = 2, refCntWtd = 8 New refCnts for V124: refCnt = 3, refCntWtd = 12 New refCnts for V122: refCnt = 4, refCntWtd = 8 New refCnts for V123: refCnt = 2, refCntWtd = 8 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002281] -A-XG+----- * ASG int [002280] ---XG+-N--- +--* IND int [003043] -----+----- | \--* ADD byref [002276] -----+----- | +--* LCL_VAR byref V00 arg0 [003042] -----+----- | \--* CNS_INT long 8 [002279] -----+----- \--* ADD int [002277] -----+----- +--* LCL_VAR int V122 tmp82 [002278] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 54, refCntWtd = 177 New refCnts for V122: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB204 (weight=2 ) STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002256] --CXG+----- * CALL r2r_ind void [002254] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002255] -----+----- arg2 in x1 +--* LCL_VAR int V123 tmp83 [003044] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn New refCnts for V00: refCnt = 55, refCntWtd = 179 New refCnts for V123: refCnt = 3, refCntWtd = 12 *** marking local variables in block BB205 (weight=2 ) STMT00080 ( 0x64D[E-] ... 0x64E ) [000325] -A---+----- * ASG int [000324] D----+-N--- +--* LCL_VAR int V37 loc33 [003045] -----+----- \--* CNS_INT int 0 New refCnts for V37: refCnt = 1, refCntWtd = 2 V37 needs explicit zero init. Disqualified as a single-def register candidate. STMT00081 ( 0x650[E-] ... 0x651 ) [000328] -A---+----- * ASG int [000327] D----+-N--- +--* LCL_VAR int V38 loc34 [000326] -----+----- \--* CNS_INT int 0 New refCnts for V38: refCnt = 1, refCntWtd = 2 V38 needs explicit zero init. Disqualified as a single-def register candidate. STMT00082 ( 0x653[E-] ... 0x655 ) [000332] -----+----- * JTRUE void [000331] J----+-N--- \--* EQ int [000329] -----+----- +--* LCL_VAR int V09 loc5 [000330] -----+----- \--* CNS_INT int 0 New refCnts for V09: refCnt = 5, refCntWtd = 23 *** marking local variables in block BB206 (weight=2 ) STMT00098 ( 0x65A[E-] ... ??? ) [000425] -----+----- * JTRUE void [000424] J----+-N--- \--* GE int [000419] -----+----- +--* LCL_VAR int V16 loc12 [002292] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 43, refCntWtd = 817 New refCnts for V02: refCnt = 18, refCntWtd = 266 *** marking local variables in block BB207 (weight=2 ) STMT00123 ( 0x665[E-] ... 0x670 ) [000575] ---XG+----- * JTRUE void [000574] N--XG+-N-U- \--* EQ int [000572] ---XG+----- +--* IND ushort [000571] -----+----- | \--* ADD long [000565] -----+----- | +--* LCL_VAR long V34 loc30 [000570] -----+----- | \--* LSH long [000567] -----+----- | +--* CAST long <- int [000566] -----+----- | | \--* LCL_VAR int V16 loc12 [000569] -----+----- | \--* CNS_INT long 1 [000573] -----+----- \--* CNS_INT int 48 New refCnts for V34: refCnt = 8, refCntWtd = 49 New refCnts for V16: refCnt = 44, refCntWtd = 819 *** marking local variables in block BB208 (weight=2 ) STMT00100 ( 0x67A[E-] ... ??? ) [000434] -----+----- * JTRUE void [000433] J----+-N--- \--* GE int [000428] -----+----- +--* ADD int [000426] -----+----- | +--* LCL_VAR int V16 loc12 [000427] -----+----- | \--* CNS_INT int 1 [002296] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 45, refCntWtd = 821 New refCnts for V02: refCnt = 19, refCntWtd = 268 *** marking local variables in block BB209 (weight=2 ) STMT00120 ( 0x687[E-] ... 0x692 ) [000548] ---XG+----- * JTRUE void [000547] N--XG+-N-U- \--* NE int [000545] ---XG+----- +--* IND ushort [000544] -----+----- | \--* ADD long [000538] -----+----- | +--* LCL_VAR long V34 loc30 [000543] -----+----- | \--* LSH long [000540] -----+----- | +--* CAST long <- int [000539] -----+----- | | \--* LCL_VAR int V16 loc12 [000542] -----+----- | \--* CNS_INT long 1 [000546] -----+----- \--* CNS_INT int 43 New refCnts for V34: refCnt = 9, refCntWtd = 51 New refCnts for V16: refCnt = 46, refCntWtd = 823 *** marking local variables in block BB210 (weight=2 ) STMT00121 ( 0x694[E-] ... 0x6A1 ) [000561] ---XG+----- * JTRUE void [000560] N--XG+-N-U- \--* NE int [000558] ---XG+----- +--* IND ushort [000557] -----+----- | \--* ADD long [000549] -----+----- | +--* LCL_VAR long V34 loc30 [000556] -----+----- | \--* LSH long [000553] -----+----- | +--* CAST long <- int [000552] -----+----- | | \--* ADD int [000550] -----+----- | | +--* LCL_VAR int V16 loc12 [000551] -----+----- | | \--* CNS_INT int 1 [000555] -----+----- | \--* CNS_INT long 1 [000559] -----+----- \--* CNS_INT int 48 New refCnts for V34: refCnt = 10, refCntWtd = 53 New refCnts for V16: refCnt = 47, refCntWtd = 825 *** marking local variables in block BB211 (weight=2 ) STMT00122 ( 0x6A3[E-] ... 0x6A4 ) [000564] -A---+----- * ASG int [000563] D----+-N--- +--* LCL_VAR int V37 loc33 [003046] -----+----- \--* CNS_INT int 1 New refCnts for V37: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB212 (weight=2 ) STMT00102 ( 0x6A8[E-] ... ??? ) [000443] -----+----- * JTRUE void [000442] J----+-N--- \--* GE int [000437] -----+----- +--* ADD int [000435] -----+----- | +--* LCL_VAR int V16 loc12 [000436] -----+----- | \--* CNS_INT int 1 [002300] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 48, refCntWtd = 827 New refCnts for V02: refCnt = 20, refCntWtd = 270 *** marking local variables in block BB213 (weight=2 ) STMT00104 ( 0x6B5[E-] ... 0x6C0 ) [000457] ---XG+----- * JTRUE void [000456] N--XG+-N-U- \--* NE int [000454] ---XG+----- +--* IND ushort [000453] -----+----- | \--* ADD long [000447] -----+----- | +--* LCL_VAR long V34 loc30 [000452] -----+----- | \--* LSH long [000449] -----+----- | +--* CAST long <- int [000448] -----+----- | | \--* LCL_VAR int V16 loc12 [000451] -----+----- | \--* CNS_INT long 1 [000455] -----+----- \--* CNS_INT int 45 New refCnts for V34: refCnt = 11, refCntWtd = 55 New refCnts for V16: refCnt = 49, refCntWtd = 829 *** marking local variables in block BB214 (weight=2 ) STMT00105 ( 0x6C2[E-] ... 0x6CF ) [000470] ---XG+----- * JTRUE void [000469] J--XG+-N--- \--* EQ int [000467] ---XG+----- +--* IND ushort [000466] -----+----- | \--* ADD long [000458] -----+----- | +--* LCL_VAR long V34 loc30 [000465] -----+----- | \--* LSH long [000462] -----+----- | +--* CAST long <- int [000461] -----+----- | | \--* ADD int [000459] -----+----- | | +--* LCL_VAR int V16 loc12 [000460] -----+----- | | \--* CNS_INT int 1 [000464] -----+----- | \--* CNS_INT long 1 [000468] -----+----- \--* CNS_INT int 48 New refCnts for V34: refCnt = 12, refCntWtd = 57 New refCnts for V16: refCnt = 50, refCntWtd = 831 *** marking local variables in block BB215 (weight=2 ) STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002304] -A-XG+----- * ASG int [002303] D----+-N--- +--* LCL_VAR int V126 tmp86 [002302] ---XG+----- \--* IND int [003048] -----+----- \--* ADD byref [000444] -----+----- +--* LCL_VAR byref V00 arg0 [003047] -----+----- \--* CNS_INT long 8 New refCnts for V126: refCnt = 1, refCntWtd = 2 V126 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 56, refCntWtd = 181 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002311] ---XG+----- * JTRUE void [002310] N--XG+-N-U- \--* GE int [002305] -----+----- +--* LCL_VAR int V126 tmp86 [002341] ---XG+----- \--* IND int [003052] -----+----- \--* ADD byref [002306] -----+----- +--* LCL_VAR byref V00 arg0 [003051] -----+----- \--* CNS_INT long 24 New refCnts for V126: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 57, refCntWtd = 183 *** marking local variables in block BB216 (weight=2 ) STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002319] -A-XG+----- * ASG byref [002318] D----+-N--- +--* LCL_VAR byref V127 tmp87 [003059] ---X-+-N--- \--* COMMA byref [003055] ---X-+----- +--* NULLCHECK byte [003054] -----+----- | \--* LCL_VAR byref V00 arg0 [003058] -----+----- \--* ADD byref [003056] -----+----- +--* LCL_VAR byref V00 arg0 [003057] -----+----- \--* CNS_INT long 16 New refCnts for V127: refCnt = 1, refCntWtd = 4 V127 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 58, refCntWtd = 185 New refCnts for V00: refCnt = 59, refCntWtd = 187 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] [002332] -A-XG+----- * ASG short [002329] ---XG+-N--- +--* COMMA short [002323] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002316] -----+----- | | +--* LCL_VAR int V126 tmp86 [002322] ---XG+----- | | \--* IND int [003061] -----+----- | | \--* ADD byref [002321] -----+----- | | +--* LCL_VAR byref V127 tmp87 [003060] -----+----- | | \--* CNS_INT long 8 [003062] ---XG+-N--- | \--* IND short [002328] ---XG+----- | \--* ADD byref [002327] ---XG+----- | +--* IND byref [002320] -----+----- | | \--* LCL_VAR byref V127 tmp87 [002326] -----+----- | \--* LSH long [002324] -----+---U- | +--* CAST long <- uint [002317] -----+----- | | \--* LCL_VAR int V126 tmp86 [002325] -----+----- | \--* CNS_INT long 1 [002330] -----+----- \--* LCL_VAR int V18 loc14 New refCnts for V126: refCnt = 3, refCntWtd = 6 New refCnts for V127: refCnt = 2, refCntWtd = 8 New refCnts for V127: refCnt = 3, refCntWtd = 12 New refCnts for V126: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 27, refCntWtd = 200 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] [002338] -A-XG+----- * ASG int [002337] ---XG+-N--- +--* IND int [003064] -----+----- | \--* ADD byref [002333] -----+----- | +--* LCL_VAR byref V00 arg0 [003063] -----+----- | \--* CNS_INT long 8 [002336] -----+----- \--* ADD int [002334] -----+----- +--* LCL_VAR int V126 tmp86 [002335] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 60, refCntWtd = 189 New refCnts for V126: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB217 (weight=2 ) *** marking local variables in block BB218 (weight=8 ) STMT00119 ( 0x6DE[E-] ... 0x6E2 ) [000537] -A---+----- * ASG int [000536] D----+-N--- +--* LCL_VAR int V38 loc34 [000535] -----+----- \--* ADD int [000533] -----+----- +--* LCL_VAR int V38 loc34 [000534] -----+----- \--* CNS_INT int 1 New refCnts for V38: refCnt = 2, refCntWtd = 10 New refCnts for V38: refCnt = 3, refCntWtd = 18 *** marking local variables in block BB219 (weight=16 ) STMT00106 ( 0x6E4[E-] ... 0x6E9 ) [000475] -A---+----- * ASG int [000474] D----+-N--- +--* LCL_VAR int V54 tmp14 [000473] -----+----- \--* ADD int [000471] -----+----- +--* LCL_VAR int V16 loc12 [000472] -----+----- \--* CNS_INT int 1 New refCnts for V54: refCnt = 1, refCntWtd = 32 V54 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 51, refCntWtd = 847 STMT00107 ( ??? ... ??? ) [000479] -A---+----- * ASG int [000478] D----+-N--- +--* LCL_VAR int V16 loc12 [000477] -----+----- \--* LCL_VAR int V54 tmp14 New refCnts for V16: refCnt = 52, refCntWtd = 863 New refCnts for V54: refCnt = 2, refCntWtd = 64 STMT00109 ( ??? ... ??? ) [000485] -----+----- * JTRUE void [000484] J----+-N--- \--* GE int [000476] -----+----- +--* LCL_VAR int V54 tmp14 [002347] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V54: refCnt = 3, refCntWtd = 96 New refCnts for V02: refCnt = 21, refCntWtd = 286 *** marking local variables in block BB220 (weight=16 ) STMT00118 ( 0x6F4[E-] ... 0x6FF ) [000532] ---XG+----- * JTRUE void [000531] J--XG+-N--- \--* EQ int [000529] ---XG+----- +--* IND ushort [000528] -----+----- | \--* ADD long [000522] -----+----- | +--* LCL_VAR long V34 loc30 [000527] -----+----- | \--* LSH long [000524] -----+----- | +--* CAST long <- int [000523] -----+----- | | \--* LCL_VAR int V16 loc12 [000526] -----+----- | \--* CNS_INT long 1 [000530] -----+----- \--* CNS_INT int 48 New refCnts for V34: refCnt = 13, refCntWtd = 73 New refCnts for V16: refCnt = 53, refCntWtd = 879 *** marking local variables in block BB221 (weight=2 ) STMT00110 ( 0x701[E-] ... 0x705 ) [000489] -----+----- * JTRUE void [000488] J----+-N--- \--* LE int [000486] -----+----- +--* LCL_VAR int V38 loc34 [000487] -----+----- \--* CNS_INT int 10 New refCnts for V38: refCnt = 4, refCntWtd = 20 *** marking local variables in block BB222 (weight=2 ) STMT00117 ( 0x707[E-] ... 0x709 ) [000521] -A---+----- * ASG int [000520] D----+-N--- +--* LCL_VAR int V38 loc34 [000519] -----+----- \--* CNS_INT int 10 New refCnts for V38: refCnt = 5, refCntWtd = 22 *** marking local variables in block BB223 (weight=2 ) STMT00111 ( 0x70B[E-] ... 0x70E ) [000494] ---XG+----- * JTRUE void [000493] J--XG+-N--- \--* EQ int [000491] ---XG+----- +--* IND ubyte [000490] -----+----- | \--* LCL_VAR long V17 loc13 [000492] -----+----- \--* CNS_INT int 0 New refCnts for V17: refCnt = 5, refCntWtd = 16 *** marking local variables in block BB224 (weight=2 ) STMT00116 ( 0x710[E-] ... 0x718 ) [000517] -A-XG+----- * ASG int [000516] D----+-N--- +--* LCL_VAR int V55 tmp15 [000515] ---XG+----- \--* SUB int [000513] ---XG+----- +--* IND int [003067] -----+----- | \--* ADD byref [000512] -----+----- | +--* LCL_VAR byref V01 arg1 [003066] -----+----- | \--* CNS_INT long 4 [000514] -----+----- \--* LCL_VAR int V05 loc1 New refCnts for V55: refCnt = 1, refCntWtd = 2 V55 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V01: refCnt = 17, refCntWtd = 24 New refCnts for V05: refCnt = 18, refCntWtd = 55 *** marking local variables in block BB225 (weight=2 ) STMT00112 ( 0x71A[E-] ... 0x71A ) [000497] -A---+----- * ASG int [000496] D----+-N--- +--* LCL_VAR int V55 tmp15 [000495] -----+----- \--* CNS_INT int 0 New refCnts for V55: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB226 (weight=2 ) STMT00114 ( 0x71D[E-] ... 0x72D ) [000508] --CXG+----- * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) [000507] -----+----- arg6 in x5 +--* LCL_VAR int V37 loc33 [000502] -----+----- arg1 in x0 +--* LCL_VAR byref V00 arg0 [000503] -----+----- arg2 in x1 +--* LCL_VAR ref V03 arg3 [000499] -----+----- arg3 in x2 +--* LCL_VAR int V55 tmp15 [000505] -----+----- arg4 in x3 +--* LCL_VAR int V18 loc14 [000506] -----+----- arg5 in x4 +--* LCL_VAR int V38 loc34 [003068] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn New refCnts for V37: refCnt = 3, refCntWtd = 6 New refCnts for V00: refCnt = 61, refCntWtd = 191 New refCnts for V03: refCnt = 9, refCntWtd = 19.50 New refCnts for V55: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 28, refCntWtd = 202 New refCnts for V38: refCnt = 6, refCntWtd = 24 STMT00115 ( 0x72C[E-] ... ??? ) [000511] -A---+----- * ASG int [000510] D----+-N--- +--* LCL_VAR int V09 loc5 [003069] -----+----- \--* CNS_INT int 0 New refCnts for V09: refCnt = 6, refCntWtd = 25 *** marking local variables in block BB227 (weight=2 ) STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] [002351] -A-XG+----- * ASG int [002350] D----+-N--- +--* LCL_VAR int V129 tmp89 [002349] ---XG+----- \--* IND int [003071] -----+----- \--* ADD byref [000333] -----+----- +--* LCL_VAR byref V00 arg0 [003070] -----+----- \--* CNS_INT long 8 New refCnts for V129: refCnt = 1, refCntWtd = 2 V129 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 62, refCntWtd = 193 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] [002358] ---XG+----- * JTRUE void [002357] N--XG+-N-U- \--* GE int [002352] -----+----- +--* LCL_VAR int V129 tmp89 [002388] ---XG+----- \--* IND int [003075] -----+----- \--* ADD byref [002353] -----+----- +--* LCL_VAR byref V00 arg0 [003074] -----+----- \--* CNS_INT long 24 New refCnts for V129: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 63, refCntWtd = 195 *** marking local variables in block BB228 (weight=2 ) STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] [002366] -A-XG+----- * ASG byref [002365] D----+-N--- +--* LCL_VAR byref V130 tmp90 [003082] ---X-+-N--- \--* COMMA byref [003078] ---X-+----- +--* NULLCHECK byte [003077] -----+----- | \--* LCL_VAR byref V00 arg0 [003081] -----+----- \--* ADD byref [003079] -----+----- +--* LCL_VAR byref V00 arg0 [003080] -----+----- \--* CNS_INT long 16 New refCnts for V130: refCnt = 1, refCntWtd = 4 V130 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 64, refCntWtd = 197 New refCnts for V00: refCnt = 65, refCntWtd = 199 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] [002379] -A-XG+----- * ASG short [002376] ---XG+-N--- +--* COMMA short [002370] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002363] -----+----- | | +--* LCL_VAR int V129 tmp89 [002369] ---XG+----- | | \--* IND int [003084] -----+----- | | \--* ADD byref [002368] -----+----- | | +--* LCL_VAR byref V130 tmp90 [003083] -----+----- | | \--* CNS_INT long 8 [003085] ---XG+-N--- | \--* IND short [002375] ---XG+----- | \--* ADD byref [002374] ---XG+----- | +--* IND byref [002367] -----+----- | | \--* LCL_VAR byref V130 tmp90 [002373] -----+----- | \--* LSH long [002371] -----+---U- | +--* CAST long <- uint [002364] -----+----- | | \--* LCL_VAR int V129 tmp89 [002372] -----+----- | \--* CNS_INT long 1 [002377] -----+----- \--* LCL_VAR int V18 loc14 New refCnts for V129: refCnt = 3, refCntWtd = 6 New refCnts for V130: refCnt = 2, refCntWtd = 8 New refCnts for V130: refCnt = 3, refCntWtd = 12 New refCnts for V129: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 29, refCntWtd = 204 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] [002385] -A-XG+----- * ASG int [002384] ---XG+-N--- +--* IND int [003087] -----+----- | \--* ADD byref [002380] -----+----- | +--* LCL_VAR byref V00 arg0 [003086] -----+----- | \--* CNS_INT long 8 [002383] -----+----- \--* ADD int [002381] -----+----- +--* LCL_VAR int V129 tmp89 [002382] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 66, refCntWtd = 201 New refCnts for V129: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB229 (weight=2 ) STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] [002360] --CXG+----- * CALL r2r_ind void [002359] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000334] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003088] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn New refCnts for V00: refCnt = 67, refCntWtd = 203 New refCnts for V18: refCnt = 30, refCntWtd = 206 *** marking local variables in block BB230 (weight=2 ) STMT00085 ( 0x739[E-] ... ??? ) [000342] -----+----- * JTRUE void [000341] J----+-N--- \--* GE int [000336] -----+----- +--* LCL_VAR int V16 loc12 [002394] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 54, refCntWtd = 881 New refCnts for V02: refCnt = 22, refCntWtd = 288 *** marking local variables in block BB231 (weight=2 ) STMT00086 ( 0x744[E-] ... 0x74F ) [000353] ---XG+----- * JTRUE void [000352] J--XG+-N--- \--* EQ int [000350] ---XG+----- +--* IND ushort [000349] -----+----- | \--* ADD long [000343] -----+----- | +--* LCL_VAR long V34 loc30 [000348] -----+----- | \--* LSH long [000345] -----+----- | +--* CAST long <- int [000344] -----+----- | | \--* LCL_VAR int V16 loc12 [000347] -----+----- | \--* CNS_INT long 1 [000351] -----+----- \--* CNS_INT int 43 New refCnts for V34: refCnt = 14, refCntWtd = 75 New refCnts for V16: refCnt = 55, refCntWtd = 883 *** marking local variables in block BB232 (weight=2 ) STMT00096 ( 0x751[E-] ... 0x75C ) [000418] ---XG+----- * JTRUE void [000417] N--XG+-N-U- \--* NE int [000415] ---XG+----- +--* IND ushort [000414] -----+----- | \--* ADD long [000408] -----+----- | +--* LCL_VAR long V34 loc30 [000413] -----+----- | \--* LSH long [000410] -----+----- | +--* CAST long <- int [000409] -----+----- | | \--* LCL_VAR int V16 loc12 [000412] -----+----- | \--* CNS_INT long 1 [000416] -----+----- \--* CNS_INT int 45 New refCnts for V34: refCnt = 15, refCntWtd = 77 New refCnts for V16: refCnt = 56, refCntWtd = 885 *** marking local variables in block BB233 (weight=2 ) STMT00088 ( 0x75E[E-] ... 0x766 ) [000363] -A---+----- * ASG int [000362] D----+-N--- +--* LCL_VAR int V52 tmp12 [000356] -----+----- \--* LCL_VAR int V16 loc12 New refCnts for V52: refCnt = 1, refCntWtd = 4 V52 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 57, refCntWtd = 887 STMT00087 ( 0x75E[E-] ... ??? ) [000361] -A---+----- * ASG int [000360] D----+-N--- +--* LCL_VAR int V16 loc12 [000359] -----+----- \--* ADD int [000357] -----+----- +--* LCL_VAR int V16 loc12 [000358] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 58, refCntWtd = 889 New refCnts for V16: refCnt = 59, refCntWtd = 891 STMT00483 ( ??? ... ??? ) [002435] -A-XG+----- * ASG ushort [002434] D----+-N--- +--* LCL_VAR int V133 tmp93 [000370] ---XG+----- \--* IND ushort [000369] -----+----- \--* ADD long [000355] -----+----- +--* LCL_VAR long V34 loc30 [000368] -----+----- \--* LSH long [000365] -----+----- +--* CAST long <- int [000364] -----+----- | \--* LCL_VAR int V52 tmp12 [000367] -----+----- \--* CNS_INT long 1 New refCnts for V133: refCnt = 1, refCntWtd = 4 V133 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V34: refCnt = 16, refCntWtd = 79 New refCnts for V52: refCnt = 2, refCntWtd = 8 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002398] -A-XG+----- * ASG int [002397] D----+-N--- +--* LCL_VAR int V132 tmp92 [002396] ---XG+----- \--* IND int [003090] -----+----- \--* ADD byref [000354] -----+----- +--* LCL_VAR byref V00 arg0 [003089] -----+----- \--* CNS_INT long 8 New refCnts for V132: refCnt = 1, refCntWtd = 2 V132 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 68, refCntWtd = 205 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002405] ---XG+----- * JTRUE void [002404] N--XG+-N-U- \--* GE int [002399] -----+----- +--* LCL_VAR int V132 tmp92 [002438] ---XG+----- \--* IND int [003094] -----+----- \--* ADD byref [002400] -----+----- +--* LCL_VAR byref V00 arg0 [003093] -----+----- \--* CNS_INT long 24 New refCnts for V132: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 69, refCntWtd = 207 *** marking local variables in block BB234 (weight=2 ) STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002414] -A-XG+----- * ASG byref [002413] D----+-N--- +--* LCL_VAR byref V134 tmp94 [003101] ---X-+-N--- \--* COMMA byref [003097] ---X-+----- +--* NULLCHECK byte [003096] -----+----- | \--* LCL_VAR byref V00 arg0 [003100] -----+----- \--* ADD byref [003098] -----+----- +--* LCL_VAR byref V00 arg0 [003099] -----+----- \--* CNS_INT long 16 New refCnts for V134: refCnt = 1, refCntWtd = 4 V134 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 70, refCntWtd = 209 New refCnts for V00: refCnt = 71, refCntWtd = 211 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? [002427] -A-XG+----- * ASG short [002424] ---XG+-N--- +--* COMMA short [002418] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002411] -----+----- | | +--* LCL_VAR int V132 tmp92 [002417] ---XG+----- | | \--* IND int [003103] -----+----- | | \--* ADD byref [002416] -----+----- | | +--* LCL_VAR byref V134 tmp94 [003102] -----+----- | | \--* CNS_INT long 8 [003104] ---XG+-N--- | \--* IND short [002423] ---XG+----- | \--* ADD byref [002422] ---XG+----- | +--* IND byref [002415] -----+----- | | \--* LCL_VAR byref V134 tmp94 [002421] -----+----- | \--* LSH long [002419] -----+---U- | +--* CAST long <- uint [002412] -----+----- | | \--* LCL_VAR int V132 tmp92 [002420] -----+----- | \--* CNS_INT long 1 [002425] -----+----- \--* LCL_VAR int V133 tmp93 New refCnts for V132: refCnt = 3, refCntWtd = 6 New refCnts for V134: refCnt = 2, refCntWtd = 8 New refCnts for V134: refCnt = 3, refCntWtd = 12 New refCnts for V132: refCnt = 4, refCntWtd = 8 New refCnts for V133: refCnt = 2, refCntWtd = 8 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002433] -A-XG+----- * ASG int [002432] ---XG+-N--- +--* IND int [003106] -----+----- | \--* ADD byref [002428] -----+----- | +--* LCL_VAR byref V00 arg0 [003105] -----+----- | \--* CNS_INT long 8 [002431] -----+----- \--* ADD int [002429] -----+----- +--* LCL_VAR int V132 tmp92 [002430] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 72, refCntWtd = 213 New refCnts for V132: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB235 (weight=2 ) STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002408] --CXG+----- * CALL r2r_ind void [002406] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002407] -----+----- arg2 in x1 +--* LCL_VAR int V133 tmp93 [003107] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn New refCnts for V00: refCnt = 73, refCntWtd = 215 New refCnts for V133: refCnt = 3, refCntWtd = 12 *** marking local variables in block BB236 (weight=8 ) STMT00094 ( 0x774[E-] ... 0x77C ) [000399] -A---+----- * ASG int [000398] D----+-N--- +--* LCL_VAR int V53 tmp13 [000392] -----+----- \--* LCL_VAR int V16 loc12 New refCnts for V53: refCnt = 1, refCntWtd = 16 V53 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 60, refCntWtd = 899 STMT00093 ( 0x774[E-] ... ??? ) [000397] -A---+----- * ASG int [000396] D----+-N--- +--* LCL_VAR int V16 loc12 [000395] -----+----- \--* ADD int [000393] -----+----- +--* LCL_VAR int V16 loc12 [000394] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 61, refCntWtd = 907 New refCnts for V16: refCnt = 62, refCntWtd = 915 STMT00492 ( ??? ... ??? ) [002481] -A-XG+----- * ASG ushort [002480] D----+-N--- +--* LCL_VAR int V137 tmp97 [000406] ---XG+----- \--* IND ushort [000405] -----+----- \--* ADD long [000391] -----+----- +--* LCL_VAR long V34 loc30 [000404] -----+----- \--* LSH long [000401] -----+----- +--* CAST long <- int [000400] -----+----- | \--* LCL_VAR int V53 tmp13 [000403] -----+----- \--* CNS_INT long 1 New refCnts for V137: refCnt = 1, refCntWtd = 16 V137 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V34: refCnt = 17, refCntWtd = 87 New refCnts for V53: refCnt = 2, refCntWtd = 32 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? [002444] -A-XG+----- * ASG int [002443] D----+-N--- +--* LCL_VAR int V136 tmp96 [002442] ---XG+----- \--* IND int [003109] -----+----- \--* ADD byref [000390] -----+----- +--* LCL_VAR byref V00 arg0 [003108] -----+----- \--* CNS_INT long 8 New refCnts for V136: refCnt = 1, refCntWtd = 8 V136 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 74, refCntWtd = 223 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? [002451] ---XG+----- * JTRUE void [002450] N--XG+-N-U- \--* GE int [002445] -----+----- +--* LCL_VAR int V136 tmp96 [002484] ---XG+----- \--* IND int [003113] -----+----- \--* ADD byref [002446] -----+----- +--* LCL_VAR byref V00 arg0 [003112] -----+----- \--* CNS_INT long 24 New refCnts for V136: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 75, refCntWtd = 231 *** marking local variables in block BB237 (weight=8 ) STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? [002460] -A-XG+----- * ASG byref [002459] D----+-N--- +--* LCL_VAR byref V138 tmp98 [003120] ---X-+-N--- \--* COMMA byref [003116] ---X-+----- +--* NULLCHECK byte [003115] -----+----- | \--* LCL_VAR byref V00 arg0 [003119] -----+----- \--* ADD byref [003117] -----+----- +--* LCL_VAR byref V00 arg0 [003118] -----+----- \--* CNS_INT long 16 New refCnts for V138: refCnt = 1, refCntWtd = 16 V138 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 76, refCntWtd = 239 New refCnts for V00: refCnt = 77, refCntWtd = 247 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? [002473] -A-XG+----- * ASG short [002470] ---XG+-N--- +--* COMMA short [002464] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002457] -----+----- | | +--* LCL_VAR int V136 tmp96 [002463] ---XG+----- | | \--* IND int [003122] -----+----- | | \--* ADD byref [002462] -----+----- | | +--* LCL_VAR byref V138 tmp98 [003121] -----+----- | | \--* CNS_INT long 8 [003123] ---XG+-N--- | \--* IND short [002469] ---XG+----- | \--* ADD byref [002468] ---XG+----- | +--* IND byref [002461] -----+----- | | \--* LCL_VAR byref V138 tmp98 [002467] -----+----- | \--* LSH long [002465] -----+---U- | +--* CAST long <- uint [002458] -----+----- | | \--* LCL_VAR int V136 tmp96 [002466] -----+----- | \--* CNS_INT long 1 [002471] -----+----- \--* LCL_VAR int V137 tmp97 New refCnts for V136: refCnt = 3, refCntWtd = 24 New refCnts for V138: refCnt = 2, refCntWtd = 32 New refCnts for V138: refCnt = 3, refCntWtd = 48 New refCnts for V136: refCnt = 4, refCntWtd = 32 New refCnts for V137: refCnt = 2, refCntWtd = 32 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? [002479] -A-XG+----- * ASG int [002478] ---XG+-N--- +--* IND int [003125] -----+----- | \--* ADD byref [002474] -----+----- | +--* LCL_VAR byref V00 arg0 [003124] -----+----- | \--* CNS_INT long 8 [002477] -----+----- \--* ADD int [002475] -----+----- +--* LCL_VAR int V136 tmp96 [002476] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 78, refCntWtd = 255 New refCnts for V136: refCnt = 5, refCntWtd = 40 *** marking local variables in block BB238 (weight=8 ) STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? [002454] --CXG+----- * CALL r2r_ind void [002452] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [002453] -----+----- arg2 in x1 +--* LCL_VAR int V137 tmp97 [003126] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn New refCnts for V00: refCnt = 79, refCntWtd = 263 New refCnts for V137: refCnt = 3, refCntWtd = 48 *** marking local variables in block BB239 (weight=16 ) STMT00091 ( 0x788[E-] ... ??? ) [000378] -----+----- * JTRUE void [000377] J----+-N--- \--* GE int [000372] -----+----- +--* LCL_VAR int V16 loc12 [002490] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 63, refCntWtd = 931 New refCnts for V02: refCnt = 23, refCntWtd = 304 *** marking local variables in block BB240 (weight=16 ) STMT00092 ( 0x793[E-] ... 0x79E ) [000389] ---XG+----- * JTRUE void [000388] J--XG+-N--- \--* EQ int [000386] ---XG+----- +--* IND ushort [000385] -----+----- | \--* ADD long [000379] -----+----- | +--* LCL_VAR long V34 loc30 [000384] -----+----- | \--* LSH long [000381] -----+----- | +--* CAST long <- int [000380] -----+----- | | \--* LCL_VAR int V16 loc12 [000383] -----+----- | \--* CNS_INT long 1 [000387] -----+----- \--* CNS_INT int 48 New refCnts for V34: refCnt = 18, refCntWtd = 103 New refCnts for V16: refCnt = 64, refCntWtd = 947 *** marking local variables in block BB241 (weight=2 ) *** marking local variables in block BB242 (weight=2 ) STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002494] -A-XG+----- * ASG int [002493] D----+-N--- +--* LCL_VAR int V140 tmp100 [002492] ---XG+----- \--* IND int [003128] -----+----- \--* ADD byref [000590] -----+----- +--* LCL_VAR byref V00 arg0 [003127] -----+----- \--* CNS_INT long 8 New refCnts for V140: refCnt = 1, refCntWtd = 2 V140 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 80, refCntWtd = 265 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002501] ---XG+----- * JTRUE void [002500] N--XG+-N-U- \--* GE int [002495] -----+----- +--* LCL_VAR int V140 tmp100 [002531] ---XG+----- \--* IND int [003132] -----+----- \--* ADD byref [002496] -----+----- +--* LCL_VAR byref V00 arg0 [003131] -----+----- \--* CNS_INT long 24 New refCnts for V140: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 81, refCntWtd = 267 *** marking local variables in block BB243 (weight=2 ) STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002509] -A-XG+----- * ASG byref [002508] D----+-N--- +--* LCL_VAR byref V141 tmp101 [003139] ---X-+-N--- \--* COMMA byref [003135] ---X-+----- +--* NULLCHECK byte [003134] -----+----- | \--* LCL_VAR byref V00 arg0 [003138] -----+----- \--* ADD byref [003136] -----+----- +--* LCL_VAR byref V00 arg0 [003137] -----+----- \--* CNS_INT long 16 New refCnts for V141: refCnt = 1, refCntWtd = 4 V141 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V00: refCnt = 82, refCntWtd = 269 New refCnts for V00: refCnt = 83, refCntWtd = 271 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] [002522] -A-XG+----- * ASG short [002519] ---XG+-N--- +--* COMMA short [002513] ---XG+----- | +--* BOUNDS_CHECK_Rng void [002506] -----+----- | | +--* LCL_VAR int V140 tmp100 [002512] ---XG+----- | | \--* IND int [003141] -----+----- | | \--* ADD byref [002511] -----+----- | | +--* LCL_VAR byref V141 tmp101 [003140] -----+----- | | \--* CNS_INT long 8 [003142] ---XG+-N--- | \--* IND short [002518] ---XG+----- | \--* ADD byref [002517] ---XG+----- | +--* IND byref [002510] -----+----- | | \--* LCL_VAR byref V141 tmp101 [002516] -----+----- | \--* LSH long [002514] -----+---U- | +--* CAST long <- uint [002507] -----+----- | | \--* LCL_VAR int V140 tmp100 [002515] -----+----- | \--* CNS_INT long 1 [002520] -----+----- \--* LCL_VAR int V18 loc14 New refCnts for V140: refCnt = 3, refCntWtd = 6 New refCnts for V141: refCnt = 2, refCntWtd = 8 New refCnts for V141: refCnt = 3, refCntWtd = 12 New refCnts for V140: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 31, refCntWtd = 208 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002528] -A-XG+----- * ASG int [002527] ---XG+-N--- +--* IND int [003144] -----+----- | \--* ADD byref [002523] -----+----- | +--* LCL_VAR byref V00 arg0 [003143] -----+----- | \--* CNS_INT long 8 [002526] -----+----- \--* ADD int [002524] -----+----- +--* LCL_VAR int V140 tmp100 [002525] -----+----- \--* CNS_INT int 1 New refCnts for V00: refCnt = 84, refCntWtd = 273 New refCnts for V140: refCnt = 5, refCntWtd = 10 *** marking local variables in block BB244 (weight=2 ) STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] [002503] --CXG+----- * CALL r2r_ind void [002502] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [000591] -----+----- arg2 in x1 +--* LCL_VAR int V18 loc14 [003145] H----+----- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn New refCnts for V00: refCnt = 85, refCntWtd = 275 New refCnts for V18: refCnt = 32, refCntWtd = 210 *** marking local variables in block BB245 (weight=8 ) STMT00054 ( 0x7AA[E-] ... ??? ) [000210] -----+----- * JTRUE void [000209] J----+-N--- \--* GE int [000204] -----+----- +--* LCL_VAR int V16 loc12 [002537] -----+----- \--* LCL_FLD int V02 arg2 [+8] New refCnts for V16: refCnt = 65, refCntWtd = 955 New refCnts for V02: refCnt = 24, refCntWtd = 312 *** marking local variables in block BB246 (weight=4 ) STMT00065 ( 0x7B5[E-] ... 0x7BC ) [000250] -A---+----- * ASG int [000249] D----+-N--- +--* LCL_VAR int V49 tmp9 [000243] -----+----- \--* LCL_VAR int V16 loc12 New refCnts for V49: refCnt = 1, refCntWtd = 8 V49 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V16: refCnt = 66, refCntWtd = 959 STMT00064 ( 0x7B5[E-] ... ??? ) [000248] -A---+----- * ASG int [000247] D----+-N--- +--* LCL_VAR int V16 loc12 [000246] -----+----- \--* ADD int [000244] -----+----- +--* LCL_VAR int V16 loc12 [000245] -----+----- \--* CNS_INT int 1 New refCnts for V16: refCnt = 67, refCntWtd = 963 New refCnts for V16: refCnt = 68, refCntWtd = 967 STMT00066 ( ??? ... 0x7C4 ) [000259] -A-XG+----- * ASG int [000258] D----+-N--- +--* LCL_VAR int V50 tmp10 [000257] ---XG+----- \--* IND ushort [000256] -----+----- \--* ADD long [000242] -----+----- +--* LCL_VAR long V34 loc30 [000255] -----+----- \--* LSH long [000252] -----+----- +--* CAST long <- int [000251] -----+----- | \--* LCL_VAR int V49 tmp9 [000254] -----+----- \--* CNS_INT long 1 New refCnts for V50: refCnt = 1, refCntWtd = 8 V50 needs explicit zero init. Disqualified as a single-def register candidate. New refCnts for V34: refCnt = 19, refCntWtd = 107 New refCnts for V49: refCnt = 2, refCntWtd = 16 STMT00067 ( ??? ... ??? ) [000263] -A---+----- * ASG int [000262] D----+-N--- +--* LCL_VAR int V18 loc14 [000261] -----+----- \--* LCL_VAR int V50 tmp10 New refCnts for V18: refCnt = 33, refCntWtd = 214 New refCnts for V50: refCnt = 2, refCntWtd = 16 STMT00068 ( ??? ... 0x7C6 ) [000266] -----+----- * JTRUE void [000265] J----+-N--- \--* EQ int [000260] -----+----- +--* LCL_VAR int V50 tmp10 [000264] -----+----- \--* CNS_INT int 0 New refCnts for V50: refCnt = 3, refCntWtd = 24 *** marking local variables in block BB247 (weight=4 ) STMT00069 ( 0x7C8[E-] ... 0x7CC ) [000270] -----+----- * JTRUE void [000269] N----+-N-U- \--* NE int [000267] -----+----- +--* LCL_VAR int V18 loc14 [000268] -----+----- \--* CNS_INT int 59 New refCnts for V18: refCnt = 34, refCntWtd = 218 *** marking local variables in block BB248 (weight=1 ) STMT00055 ( 0x7D1[E-] ... 0x7D3 ) [000214] -A---+----- * ASG byref [000213] D----+-N--- +--* LCL_VAR byref V35 loc31 [000212] -----+----- \--* CNS_INT long 0 New refCnts for V35: refCnt = 2, refCntWtd = 2 V35 has multiple definitions. Disqualified as a single-def register candidate. STMT00056 ( 0x7D5[E-] ... 0x7DB ) [000219] ---XG+----- * JTRUE void [000218] J--XG+-N--- \--* EQ int [000216] ---XG+----- +--* IND bool [003148] -----+----- | \--* ADD byref [000215] -----+----- | +--* LCL_VAR byref V01 arg1 [003147] -----+----- | \--* CNS_INT long 8 [000217] -----+----- \--* CNS_INT int 0 New refCnts for V01: refCnt = 18, refCntWtd = 25 *** marking local variables in block BB249 (weight=0.50) STMT00058 ( 0x7DD[E-] ... 0x7DF ) [000224] -----+----- * JTRUE void [000223] J----+-N--- \--* NE int [000221] -----+----- +--* LCL_VAR int V15 loc11 [000222] -----+----- \--* CNS_INT int 0 New refCnts for V15: refCnt = 7, refCntWtd = 19 *** marking local variables in block BB250 (weight=0.50) STMT00059 ( 0x7E1[E-] ... 0x7E7 ) [000229] ---XG+----- * JTRUE void [000228] J--XG+-N--- \--* NE int [000226] ---XG+----- +--* IND int [003150] -----+----- | \--* ADD byref [000225] -----+----- | +--* LCL_VAR byref V01 arg1 [003149] -----+----- | \--* CNS_INT long 4 [000227] -----+----- \--* CNS_INT int 0 New refCnts for V01: refCnt = 19, refCntWtd = 25.50 *** marking local variables in block BB251 (weight=0.50) STMT00061 ( 0x7E9[E-] ... ??? ) [000235] ---XG+----- * JTRUE void [000234] J--XG+-N--- \--* LE int [002539] ---XG+----- +--* IND int [003152] -----+----- | \--* ADD byref [000230] -----+----- | +--* LCL_VAR byref V00 arg0 [003151] -----+----- | \--* CNS_INT long 8 [000233] -----+----- \--* CNS_INT int 0 New refCnts for V00: refCnt = 86, refCntWtd = 275.50 *** marking local variables in block BB252 (weight=0.50) STMT00063 ( 0x7F2[E-] ... ??? ) [000241] --CXG+----- * CALL r2r_ind void [002541] ---XG+----- arg3 in x2 +--* IND ref [003155] -----+----- | \--* ADD byref [000238] -----+----- | +--* LCL_VAR ref V03 arg3 [003154] -----+----- | \--* CNS_INT long 40 Fseq[] [000236] -----+----- this in x0 +--* LCL_VAR byref V00 arg0 [003153] H----+----- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn [000237] -----+----- arg2 in x1 \--* CNS_INT int 0 New refCnts for V03: refCnt = 10, refCntWtd = 20 New refCnts for V00: refCnt = 87, refCntWtd = 276 *** marking local variables in block BB253 (weight=1 ) STMT00057 ( 0x7FF[E-] ... 0x7FF ) [000220] -----+----- * RETURN void *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 88, refCntWtd = 277 New refCnts for V00: refCnt = 89, refCntWtd = 278 New refCnts for V01: refCnt = 20, refCntWtd = 26.50 New refCnts for V01: refCnt = 21, refCntWtd = 27.50 New refCnts for V02: refCnt = 25, refCntWtd = 313 New refCnts for V02: refCnt = 26, refCntWtd = 314 New refCnts for V03: refCnt = 11, refCntWtd = 21 New refCnts for V03: refCnt = 12, refCntWtd = 22 *************** Finishing PHASE Mark local vars [no changes] *************** Starting PHASE Opt add copies *************** In optAddCopies() *************** Finishing PHASE Opt add copies [no changes] *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order Trees after Find oper order ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) ( 17, 13) [000001] --CXG------ * CALL r2r_ind void ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) ( 1, 3) [000004] -A------R-- * ASG int ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] ( 5, 6) [001500] -A-XGO--R-- * ASG byref ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 ( 5, 6) [002549] ---X-O-N--- \--* COMMA byref ( 2, 2) [002545] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002544] ----------- | \--* LCL_VAR byref V01 arg1 ( 3, 4) [002548] -----O----- \--* ADD byref ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) ( 13, 15) [000009] -A-XGO--R-- * ASG long ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 ( 13, 15) [002554] -A-XGO----- \--* COMMA long ( 12, 14) [002551] -A-XGO--R-- +--* ASG long ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 ( 4, 3) [001503] ---XG------ | | \--* IND int ( 3, 4) [002556] -------N--- | | \--* ADD byref ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 ( 3, 2) [001505] ---XG------ | \--* IND byref ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) ( 14, 14) [002563] -A--------- * COMMA void ( 7, 7) [002559] -A------R-- +--* ASG byref ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] ( 7, 7) [002562] -A------R-- \--* ASG int ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) ( 8, 8) [000015] ---XG------ * JTRUE void ( 6, 6) [000014] J--XG--N--- \--* EQ int ( 4, 3) [000012] ---XG------ +--* IND ubyte ( 1, 1) [000011] ----------- | \--* LCL_VAR long V167 tmp127 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) ( 14, 10) [002570] -A--------- * COMMA void ( 7, 5) [002566] -A------R-- +--* ASG byref ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 ( 7, 5) [002569] -A------R-- \--* ASG int ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) ( 9, 9) [001476] ---XG------ * JTRUE void ( 7, 7) [001475] J--XG--N--- \--* NE int ( 5, 4) [001473] ---XG------ +--* IND bool ( 3, 4) [002572] -------N--- | \--* ADD byref ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) ( 14, 10) [002579] -A--------- * COMMA void ( 7, 5) [002575] -A------R-- +--* ASG byref ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 ( 7, 5) [002578] -A------R-- \--* ASG int ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) ( 5, 5) [001494] -A------R-- * ASG int ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) ( 14, 10) [002586] -A--------- * COMMA void ( 7, 5) [002582] -A------R-- +--* ASG byref ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 ( 7, 5) [002585] -A------R-- \--* ASG int ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) ( 5, 5) [001487] -A------R-- * ASG int ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) ( 14, 10) [002593] -A--------- * COMMA void ( 7, 5) [002589] -A------R-- +--* ASG byref ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 ( 7, 5) [002592] -A------R-- \--* ASG int ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) ( 5, 5) [000026] -A------R-- * ASG int ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) ( 25, 19) [000034] -ACXG---R-- * ASG int ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) ( 1, 3) [000037] -A------R-- * ASG int ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) ( 1, 3) [000040] -A------R-- * ASG int ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) ( 1, 4) [000043] -A------R-- * ASG int ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) ( 1, 3) [000046] -A------R-- * ASG int ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) ( 1, 3) [000049] -A------R-- * ASG int ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) ( 1, 3) [000052] -A------R-- * ASG int ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) ( 1, 3) [000055] -A------R-- * ASG int ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) ( 1, 3) [000058] -A------R-- * ASG int ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) ( 1, 3) [000061] -A------R-- * ASG int ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) ( 6, 8) [002606] -A--------- * COMMA void ( 3, 4) [002602] -A------R-- +--* ASG byref ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] ( 3, 4) [002605] -A------R-- \--* ASG int ( 1, 1) [002603] D------N--- +--* LCL_VAR int V158 tmp118 ( 3, 4) [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) ( 1, 3) [000068] -A------R-- * ASG byref ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) ( 2, 4) [000072] -A------R-- * ASG long ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 ( 2, 4) [002611] -A--------- \--* COMMA long ( 1, 3) [002608] -A------R-- +--* ASG long ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) ( 5, 6) [001229] ----------- * JTRUE void ( 3, 4) [001228] N------N-U- \--* GT int ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) ( 13, 9) [001364] ----------- * SWITCH void ( 3, 4) [001363] ----------- \--* ADD int ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) ( 13, 9) [001368] ----------- * SWITCH void ( 3, 4) [001367] ----------- \--* ADD int ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) ( 5, 6) [001372] ----------- * JTRUE void ( 3, 4) [001371] J------N--- \--* EQ int ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) ( 5, 6) [001233] ----------- * JTRUE void ( 3, 4) [001232] J------N--- \--* EQ int ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) ( 5, 6) [001260] ----------- * JTRUE void ( 3, 4) [001259] J------N--- \--* EQ int ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) ( 5, 8) [001355] ----------- * JTRUE void ( 3, 6) [001354] J------N--- \--* NE int ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) ( 3, 4) [001360] -A------R-- * ASG int ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 ( 3, 4) [001358] ----------- \--* ADD int ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) ( 3, 4) [001434] -A------R-- * ASG int ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 ( 3, 4) [001432] ----------- \--* ADD int ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) ( 5, 8) [001376] ----------- * JTRUE void ( 3, 6) [001375] N------N-U- \--* NE int ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) ( 1, 3) [001387] -A------R-- * ASG int ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) ( 3, 4) [001381] -A------R-- * ASG int ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 ( 3, 4) [001379] ----------- \--* ADD int ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) ( 1, 3) [001384] -A------R-- * ASG int ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) ( 5, 6) [001391] ----------- * JTRUE void ( 3, 4) [001390] J------N--- \--* GE int ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) ( 1, 3) [001394] -A------R-- * ASG int ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) ( 5, 6) [001398] ----------- * JTRUE void ( 3, 4) [001397] J------N--- \--* LE int ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) ( 5, 6) [001402] ----------- * JTRUE void ( 3, 4) [001401] J------N--- \--* GE int ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) ( 5, 6) [001406] ----------- * JTRUE void ( 3, 4) [001405] J------N--- \--* LT int ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) ( 5, 5) [001416] ----------- * JTRUE void ( 3, 3) [001415] N------N-U- \--* NE int ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) ( 3, 4) [001424] -A------R-- * ASG int ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 ( 3, 4) [001422] ----------- \--* ADD int ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) ( 1, 3) [001419] -A------R-- * ASG int ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) ( 1, 3) [001409] -A------R-- * ASG int ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) ( 1, 3) [001412] -A------R-- * ASG int ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) ( 3, 4) [001429] -A------R-- * ASG int ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 ( 3, 4) [001427] ----------- \--* ADD int ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) ( 7, 8) [001441] ----------- * JTRUE void ( 5, 6) [001440] J------N--- \--* GE int ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) ( 13, 15) [001452] ---XG------ * JTRUE void ( 11, 13) [001451] J--XG--N--- \--* EQ int ( 9, 10) [001449] ---XG------ +--* IND ushort ( 6, 8) [001448] -------N--- | \--* ADD long ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 ( 4, 6) [001447] ----------- | \--* LSH long ( 2, 3) [001444] ----------- | +--* CAST long <- int ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) ( 1, 3) [001461] -A------R-- * ASG int ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) ( 3, 4) [001459] -A------R-- * ASG int ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [001457] ----------- \--* ADD int ( 1, 1) [001455] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) ( 13, 14) [001471] ---XG------ * JTRUE void ( 11, 12) [001470] N--XG--N-U- \--* NE int ( 9, 10) [001468] ---XG------ +--* IND ushort ( 6, 8) [001467] -------N--- | \--* ADD long ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 ( 4, 6) [001466] ----------- | \--* LSH long ( 2, 3) [001463] ----------- | +--* CAST long <- int ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) ( 7, 8) [001240] ----------- * JTRUE void ( 5, 6) [001239] J------N--- \--* GE int ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) ( 13, 15) [001251] ---XG------ * JTRUE void ( 11, 13) [001250] J--XG--N--- \--* EQ int ( 9, 10) [001248] ---XG------ +--* IND ushort ( 6, 8) [001247] -------N--- | \--* ADD long ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 ( 4, 6) [001246] ----------- | \--* LSH long ( 2, 3) [001243] ----------- | +--* CAST long <- int ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) ( 3, 4) [001256] -A------R-- * ASG int ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [001254] ----------- \--* ADD int ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) ( 7, 8) [001267] ----------- * JTRUE void ( 5, 6) [001266] J------N--- \--* GE int ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) ( 13, 15) [001351] ---XG------ * JTRUE void ( 11, 13) [001350] J--XG--N--- \--* EQ int ( 9, 10) [001348] ---XG------ +--* IND ushort ( 6, 8) [001347] -------N--- | \--* ADD long ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 ( 4, 6) [001346] ----------- | \--* LSH long ( 2, 3) [001343] ----------- | +--* CAST long <- int ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) ( 9, 11) [001276] ----------- * JTRUE void ( 7, 9) [001275] J------N--- \--* GE int ( 3, 4) [001270] ----------- +--* ADD int ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) ( 13, 15) [001287] ---XG------ * JTRUE void ( 11, 13) [001286] J--XG--N--- \--* EQ int ( 9, 10) [001284] ---XG------ +--* IND ushort ( 6, 8) [001283] -------N--- | \--* ADD long ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 ( 4, 6) [001282] ----------- | \--* LSH long ( 2, 3) [001279] ----------- | +--* CAST long <- int ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) ( 13, 15) [001340] ---XG------ * JTRUE void ( 11, 13) [001339] N--XG--N-U- \--* NE int ( 9, 10) [001337] ---XG------ +--* IND ushort ( 6, 8) [001336] -------N--- | \--* ADD long ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 ( 4, 6) [001335] ----------- | \--* LSH long ( 2, 3) [001332] ----------- | +--* CAST long <- int ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) ( 15, 18) [001300] ---XG------ * JTRUE void ( 13, 16) [001299] N--XG--N-U- \--* NE int ( 11, 13) [001297] ---XG------ +--* IND ushort ( 8, 11) [001296] -------N--- | \--* ADD long ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 ( 6, 9) [001295] ----------- | \--* LSH long ( 4, 6) [001292] ----------- | +--* CAST long <- int ( 3, 4) [001291] ----------- | | \--* ADD int ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) ( 3, 4) [001305] -A------R-- * ASG int ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 ( 3, 4) [001303] ----------- \--* ADD int ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) ( 1, 3) [001309] -A------R-- * ASG int ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB44 STMT00282 ( ??? ... ??? ) ( 7, 8) [001315] ----------- * JTRUE void ( 5, 6) [001314] J------N--- \--* GE int ( 1, 1) [001306] ----------- +--* LCL_VAR int V73 tmp33 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) ( 13, 15) [001329] ---XG------ * JTRUE void ( 11, 13) [001328] J--XG--N--- \--* EQ int ( 9, 10) [001326] ---XG------ +--* IND ushort ( 6, 8) [001325] -------N--- | \--* ADD long ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 ( 4, 6) [001324] ----------- | \--* LSH long ( 2, 3) [001321] ----------- | +--* CAST long <- int ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) ( 1, 3) [001318] -A------R-- * ASG int ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) ( 7, 8) [000079] ----------- * JTRUE void ( 5, 6) [000078] J------N--- \--* GE int ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) ( 1, 3) [001205] -A------R-- * ASG int ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) ( 3, 4) [001203] -A------R-- * ASG int ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [001201] ----------- \--* ADD int ( 1, 1) [001199] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) ( 9, 10) [001214] -A-XG---R-- * ASG int ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 ( 9, 10) [001212] ---XG------ \--* IND ushort ( 6, 8) [001211] -------N--- \--* ADD long ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 ( 4, 6) [001210] ----------- \--* LSH long ( 2, 3) [001207] ----------- +--* CAST long <- int ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) ( 1, 3) [001218] -A------R-- * ASG int ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB48 STMT00264 ( ??? ... 0x220 ) ( 5, 6) [001221] ----------- * JTRUE void ( 3, 4) [001220] J------N--- \--* EQ int ( 1, 1) [001215] ----------- +--* LCL_VAR int V72 tmp32 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) ( 5, 6) [001225] ----------- * JTRUE void ( 3, 4) [001224] N------N-U- \--* NE int ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) ( 1, 3) [000083] -A------R-- * ASG byref ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) ( 5, 6) [000087] ----------- * JTRUE void ( 3, 4) [000086] J------N--- \--* GE int ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) ( 1, 3) [001196] -A------R-- * ASG int ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) ( 5, 6) [000091] ----------- * JTRUE void ( 3, 4) [000090] J------N--- \--* LT int ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) ( 5, 5) [001183] ----------- * JTRUE void ( 3, 3) [001182] N------N-U- \--* NE int ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) ( 8, 8) [001193] -A------R-- * ASG int ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 ( 8, 8) [001191] ----------- \--* SUB int ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 ( 6, 6) [001190] ----------- \--* MUL int ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) ( 1, 3) [001186] -A------R-- * ASG int ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) ( 8, 8) [000096] ---XG------ * JTRUE void ( 6, 6) [000095] J--XG--N--- \--* EQ int ( 4, 3) [000093] ---XG------ +--* IND ubyte ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) ( 5, 6) [001129] -A-XGO--R-- * ASG byref ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 ( 5, 6) [002621] ---X-O-N--- \--* COMMA byref ( 2, 2) [002617] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002616] ----------- | \--* LCL_VAR byref V01 arg1 ( 3, 4) [002620] -----O----- \--* ADD byref ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) ( 9, 7) [001136] -A-XG---R-- * ASG int ( 3, 2) [001135] ---XG--N--- +--* IND int ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 ( 5, 4) [001134] ---XG------ \--* ADD int ( 3, 2) [001132] ---XG------ +--* IND int ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) ( 5, 6) [001140] ----------- * JTRUE void ( 3, 4) [001139] J------N--- \--* NE int ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) ( 8, 7) [001178] -A-XG---R-- * ASG int ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 ( 8, 7) [001176] ---XG------ \--* SUB int ( 6, 5) [001174] ---XG------ +--* ADD int ( 4, 3) [001172] ---XG------ | +--* IND int ( 3, 4) [002623] -------N--- | | \--* ADD byref ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) ( 1, 3) [001143] -A------R-- * ASG int ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) ( 19, 18) [001151] --CXG------ * CALL r2r_ind void ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) ( 8, 8) [001156] ---XG------ * JTRUE void ( 6, 6) [001155] J--XG--N--- \--* NE int ( 4, 3) [001153] ---XG------ +--* IND ubyte ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) ( 23, 23) [001163] -ACXG---R-- * ASG int ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) ( 5, 5) [001167] ----------- * JTRUE void ( 3, 3) [001166] J------N--- \--* EQ int ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) ( 1, 3) [001170] -A------R-- * ASG int ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) ( 9, 9) [000101] ---XG------ * JTRUE void ( 7, 7) [000100] J--XG--N--- \--* EQ int ( 5, 4) [000098] ---XG------ +--* IND ubyte ( 3, 4) [002630] -------N--- | \--* ADD byref ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) ( 7, 7) [001125] -A-XG------ * ASG bool ( 5, 4) [001124] ---XG--N--- +--* IND bool ( 3, 4) [002632] -------N--- | \--* ADD byref ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) ( 6, 6) [000105] -A-XG------ * ASG int ( 4, 3) [000104] ---XG--N--- +--* IND int ( 3, 4) [002634] -------N--- | \--* ADD byref ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) ( 5, 5) [000109] ----------- * JTRUE void ( 3, 3) [000108] J------N--- \--* LT int ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) ( 5, 5) [001120] -A------R-- * ASG int ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) ( 7, 6) [000114] -A------R-- * ASG int ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 ( 3, 3) [000112] ----------- \--* SUB int ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00031 ( ??? ... 0x2B8 ) ( 3, 3) [000118] -A------R-- * ASG int ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) ( 5, 5) [000122] ----------- * JTRUE void ( 3, 3) [000121] J------N--- \--* GT int ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) ( 5, 5) [001116] -A------R-- * ASG int ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) ( 7, 6) [000127] -A------R-- * ASG int ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 ( 3, 3) [000125] ----------- \--* SUB int ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00034 ( ??? ... 0x2C3 ) ( 3, 3) [000131] -A------R-- * ASG int ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) ( 5, 6) [000135] ----------- * JTRUE void ( 3, 4) [000134] J------N--- \--* EQ int ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) ( 1, 3) [001110] -A------R-- * ASG int ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) ( 1, 3) [001113] -A------R-- * ASG int ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) ( 8, 7) [000140] ---XG------ * JTRUE void ( 6, 5) [000139] J--XG--N--- \--* GT int ( 4, 3) [000137] ---XG------ +--* IND int ( 3, 4) [002636] -------N--- | \--* ADD byref ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) ( 5, 4) [001106] -A------R-- * ASG int ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) ( 8, 6) [000144] -A-XG---R-- * ASG int ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 ( 4, 3) [000142] ---XG------ \--* IND int ( 3, 4) [002638] -------N--- \--* ADD byref ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00038 ( ??? ... 0x2E2 ) ( 3, 3) [000148] -A------R-- * ASG int ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) ( 6, 5) [000154] -A-XG---R-- * ASG int ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 ( 6, 5) [000152] ---XG------ \--* SUB int ( 4, 3) [000150] ---XG------ +--* IND int ( 3, 4) [002640] -------N--- | \--* ADD byref ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) ( 1, 3) [000157] -A------R-- * ASG int ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) ( 2, 6) [002647] -A--------- * COMMA void ( 1, 3) [002643] -A------R-- +--* ASG byref ( 1, 1) [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 ( 1, 2) [002642] ----------- | \--* CNS_INT byref 0 ( 1, 3) [002646] -A------R-- \--* ASG int ( 1, 1) [002644] D------N--- +--* LCL_VAR int V152 tmp112 ( 1, 2) [002645] ----------- \--* CNS_INT int 0 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? ( 3, 3) [001553] -A------R-- * ASG byref ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? ( 1, 3) [001558] -A------R-- * ASG int ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) ( 2, 6) [002654] -A--------- * COMMA void ( 1, 3) [002650] -A------R-- +--* ASG byref ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 ( 1, 3) [002653] -A------R-- \--* ASG int ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) ( 1, 3) [000177] -A------R-- * ASG int ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) ( 5, 6) [000181] ----------- * JTRUE void ( 3, 4) [000180] J------N--- \--* EQ int ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) ( 10, 10) [000947] ---XG------ * JTRUE void ( 8, 8) [000946] J--XG--N--- \--* LE int ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int ( 4, 3) [001570] ---XG------ | \--* IND ref ( 3, 4) [002656] -------N--- | \--* ADD byref ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] ( 1, 2) [000945] ----------- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) ( 4, 3) [000951] -A-XG---R-- * ASG ref ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 ( 4, 3) [000949] ---XG------ \--* IND ref ( 3, 4) [002658] -------N--- \--* ADD byref ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) ( 1, 3) [000954] -A------R-- * ASG int ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) ( 1, 3) [000957] -A------R-- * ASG int ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) ( 3, 3) [000961] -A-X----R-- * ASG int ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) ( 5, 6) [000965] ----------- * JTRUE void ( 3, 4) [000964] J------N--- \--* EQ int ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) ( 18, 23) [001103] -A-XGO--R-- * ASG int ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 ( 18, 23) [002670] ---XGO----- \--* COMMA int ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 ( 10, 12) [002671] n---GO----- \--* IND int ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] ( 7, 10) [002668] -------N--- \--* ADD byref ( 3, 4) [002667] ----------- +--* ADD byref ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 ( 4, 6) [002665] ----------- \--* LSH long ( 2, 3) [002663] ---------U- +--* CAST long <- uint ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) ( 1, 3) [000968] -A------R-- * ASG int ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB82 STMT00211 ( ??? ... 0x346 ) ( 5, 4) [000975] -A------R-- * ASG int ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) ( 5, 6) [000973] ----------- * JTRUE void ( 3, 4) [000972] J------N--- \--* LT int ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) ( 7, 5) [001093] -A------R-- * ASG int ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB83 STMT00237 ( ??? ... ??? ) ( 5, 5) [001096] -A------R-- * ASG int ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) ( 7, 5) [000981] -A------R-- * ASG int ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00213 ( ??? ... ??? ) ( 5, 4) [000984] -A------R-- * ASG int ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00214 ( ??? ... 0x34E ) ( 11, 8) [000990] -A------R-- * ASG int ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 ( 7, 5) [000988] ----------- \--* ADD int ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) ( 7, 6) [000994] ----------- * JTRUE void ( 5, 4) [000993] J------N--- \--* GT int ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) ( 7, 5) [001089] -A------R-- * ASG int ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) ( 5, 4) [000997] -A------R-- * ASG int ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00217 ( ??? ... 0x35A ) ( 3, 3) [001001] -A------R-- * ASG int ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) ( 5, 5) [003156] ----------- * JTRUE void ( 3, 3) [003157] J------N--- \--* LE int ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 ( 1, 1) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) ( 5, 6) [001009] ----------- * JTRUE void ( 3, 4) [001008] J------N--- \--* EQ int ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) ( 3, 4) [001014] -A------R-- * ASG int ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 ( 3, 4) [001012] ----------- \--* ADD int ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) ( 5, 5) [001021] ----------- * JTRUE void ( 3, 3) [001020] J------N--- \--* LT int ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) ( 20, 18) [001070] -ACXG---R-- * ASG ref ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int ( 3, 4) [001066] ----------- | \--* LSH int ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] ( 2, 6) [002679] -A--------- * COMMA void ( 1, 3) [002675] -A------R-- +--* ASG byref ( 1, 1) [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 ( 1, 2) [002674] ----------- | \--* CNS_INT byref 0 ( 1, 3) [002678] -A------R-- \--* ASG int ( 1, 1) [002676] D------N--- +--* LCL_VAR int V160 tmp120 ( 1, 2) [002677] ----------- \--* CNS_INT int 0 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] ( 5, 6) [001590] ----------- * JTRUE void ( 3, 4) [001589] J------N--- \--* NE int ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 ( 1, 2) [001588] ----------- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] ( 2, 6) [002686] -A--------- * COMMA void ( 1, 3) [002682] -A------R-- +--* ASG byref ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 ( 1, 3) [002685] -A------R-- \--* ASG int ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] ( 5, 6) [001604] -A-X-O--R-- * ASG byref ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 ( 5, 6) [002692] ---X-O-N--- \--* COMMA byref ( 2, 2) [002688] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002687] ----------- | \--* LCL_VAR ref V33 loc29 ( 3, 4) [002691] -----O----- \--* ADD byref ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] ( 3, 3) [001610] -A-X----R-- * ASG int ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00339 ( ??? ... ??? ) ( 6, 7) [002699] -A--------- * COMMA void ( 1, 3) [002695] -A------R-- +--* ASG byref ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 ( 5, 4) [002698] -A------R-- \--* ASG int ( 3, 2) [002696] D------N--- +--* LCL_VAR int V162 tmp122 ( 1, 1) [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? ( 5, 5) [001629] ----------- * JTRUE void ( 3, 3) [001628] N------N-U- \--* GT int ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? ( 1, 3) [001669] -A------R-- * ASG byref ( 1, 1) [001668] D------N--- +--* LCL_VAR byref V81 tmp41 ( 1, 1) [001633] ----------- \--* LCL_VAR byref V161 tmp121 ***** BB96 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? ( 1, 3) [001671] -A------R-- * ASG byref ( 1, 1) [001670] D------N--- +--* LCL_VAR byref V82 tmp42 ( 1, 1) [001636] ----------- \--* LCL_VAR byref V143 tmp103 ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? ( 2, 3) [001673] -A------R-- * ASG long ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? ( 21, 20) [001667] --CXG------ * CALL r2r_ind void ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] ( 2, 6) [002708] -A--------- * COMMA void ( 1, 3) [002704] -A------R-- +--* ASG byref ( 1, 1) [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 ( 1, 2) [002703] ----------- | \--* CNS_INT byref 0 ( 1, 3) [002707] -A------R-- \--* ASG int ( 1, 1) [002705] D------N--- +--* LCL_VAR int V164 tmp124 ( 1, 2) [002706] ----------- \--* CNS_INT int 0 ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] ( 5, 6) [001702] ----------- * JTRUE void ( 3, 4) [001701] J------N--- \--* NE int ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 ( 1, 2) [001700] ----------- \--* CNS_INT ref null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] ( 2, 6) [002715] -A--------- * COMMA void ( 1, 3) [002711] -A------R-- +--* ASG byref ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 ( 1, 3) [002714] -A------R-- \--* ASG int ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] ( 5, 6) [001716] -A-X-O--R-- * ASG byref ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 ( 5, 6) [002721] ---X-O-N--- \--* COMMA byref ( 2, 2) [002717] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002716] ----------- | \--* LCL_VAR ref V33 loc29 ( 3, 4) [002720] -----O----- \--* ADD byref ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] ( 3, 3) [001722] -A-X----R-- * ASG int ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) ( 2, 6) [002728] -A--------- * COMMA void ( 1, 3) [002724] -A------R-- +--* ASG byref ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 ( 1, 3) [002727] -A------R-- \--* ASG int ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) ( 16, 20) [001038] -A-XGO----- * ASG int ( 14, 18) [001035] ---XGO-N--- +--* COMMA int ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 ( 8, 9) [002729] ---XGO-N--- | \--* IND int ( 6, 8) [001034] -----O-N--- | \--* ADD byref ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 ( 4, 6) [001032] ----------- | \--* LSH long ( 2, 3) [001030] ---------U- | +--* CAST long <- uint ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) ( 7, 8) [001044] ----------- * JTRUE void ( 5, 6) [001043] J------N--- \--* GE int ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 ( 3, 4) [001042] ----------- \--* ADD int ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) ( 3, 4) [001054] -A------R-- * ASG int ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 ( 3, 4) [001052] ----------- \--* ADD int ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) ( 18, 23) [001060] -A-XGO--R-- * ASG int ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 ( 18, 23) [002741] ---XGO----- \--* COMMA int ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 ( 10, 12) [002742] n---GO----- \--* IND int ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] ( 7, 10) [002739] -------N--- \--* ADD byref ( 3, 4) [002738] ----------- +--* ADD byref ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 ( 4, 6) [002736] ----------- \--* LSH long ( 2, 3) [002734] ---------U- +--* CAST long <- uint ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) ( 3, 3) [001049] -A------R-- * ASG int ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 ( 3, 3) [001047] ----------- \--* ADD int ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) ( 5, 5) [001005] ----------- * JTRUE void ( 3, 3) [001004] J------N--- \--* GT int ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) ( 9, 9) [000186] ---XG------ * JTRUE void ( 7, 7) [000185] J--XG--N--- \--* EQ int ( 5, 4) [000183] ---XG------ +--* IND bool ( 3, 4) [002744] -------N--- | \--* ADD byref ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) ( 5, 6) [000930] ----------- * JTRUE void ( 3, 4) [000929] J------N--- \--* NE int ( 1, 1) [000927] ----------- +--* LCL_VAR int V15 loc11 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) ( 8, 8) [000935] ---XG------ * JTRUE void ( 6, 6) [000934] J--XG--N--- \--* EQ int ( 4, 3) [000932] ---XG------ +--* IND int ( 3, 4) [002746] -------N--- | \--* ADD byref ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) ( 4, 3) [001783] -A-XG---R-- * ASG ref ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 ( 4, 3) [001730] ---XG------ \--* IND ref ( 3, 4) [002748] -------N--- \--* ADD byref ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] ( 5, 6) [001735] ----------- * JTRUE void ( 3, 4) [001734] J------N--- \--* EQ int ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 ( 1, 2) [001733] ----------- \--* CNS_INT ref null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] ( 8, 6) [001738] -A-XG---R-- * ASG int ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 ( 4, 3) [001736] ---XG------ \--* IND int ( 3, 4) [002750] -------N--- \--* ADD byref ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] ( 7, 8) [001743] ---X------- * JTRUE void ( 5, 6) [001742] N--X---N-U- \--* NE int ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] ( 10, 8) [001753] ---XG------ * JTRUE void ( 8, 6) [001752] N--XG--N-U- \--* GE int ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 ( 4, 3) [001786] ---XG------ \--* IND int ( 3, 4) [002754] -------N--- \--* ADD byref ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] ( 5, 6) [001759] -A-XGO--R-- * ASG byref ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 ( 5, 6) [002761] ---X-O-N--- \--* COMMA byref ( 2, 2) [002757] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002756] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [002760] -----O----- \--* ADD byref ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] ( 38, 41) [001775] -A-XGO----- * ASG short ( 24, 24) [001769] ---XGO-N--- +--* COMMA short ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 ( 4, 3) [001762] ---XG------ | | \--* IND int ( 3, 4) [002763] -------N--- | | \--* ADD byref ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 ( 13, 12) [002764] ---XGO-N--- | \--* IND short ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref ( 3, 2) [001767] ---XG------ | +--* IND byref ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 ( 6, 7) [001766] ----------- | \--* LSH long ( 4, 4) [001764] ---------U- | +--* CAST long <- uint ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 ( 5, 4) [002777] n---GO----- \--* IND ushort ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] ( 1, 1) [002772] -------N--- \--* ADD byref ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] ( 10, 9) [001781] -A-XG---R-- * ASG int ( 4, 3) [001780] ---XG--N--- +--* IND int ( 3, 4) [002779] -------N--- | \--* ADD byref ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 ( 5, 5) [001779] ----------- \--* ADD int ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) ( 1, 3) [000189] -A------R-- * ASG int ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) ( 10, 11) [002788] -A--------- * COMMA void ( 3, 4) [002784] -A------R-- +--* ASG byref ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] ( 7, 7) [002787] -A------R-- \--* ASG int ( 3, 2) [002785] D------N--- +--* LCL_VAR int V166 tmp126 ( 3, 4) [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) ( 5, 4) [000196] -A------R-- * ASG byref ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) ( 2, 4) [000200] -A------R-- * ASG long ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 ( 2, 4) [002793] -A--------- \--* COMMA long ( 1, 3) [002790] -A------R-- +--* ASG long ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) ( 1, 3) [000203] -A------R-- * ASG long ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) ( 5, 6) [000274] ----------- * JTRUE void ( 3, 4) [000273] J------N--- \--* LE int ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) ( 5, 6) [000824] ----------- * JTRUE void ( 3, 4) [000823] J------N--- \--* EQ int ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) ( 5, 6) [000922] ----------- * JTRUE void ( 3, 4) [000921] J------N--- \--* EQ int ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) ( 5, 6) [000926] ----------- * JTRUE void ( 3, 4) [000925] J------N--- \--* EQ int ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) ( 1, 3) [000836] -A------R-- * ASG byref ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) ( 8, 8) [000834] ---XG------ * JTRUE void ( 6, 6) [000833] J--XG--N--- \--* NE int ( 4, 3) [000831] ---XG------ +--* IND ubyte ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) ( 1, 3) [000914] -A------R-- * ASG byref ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB119 STMT00195 ( ??? ... ??? ) ( 1, 3) [000917] -A------R-- * ASG int ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) ( 1, 3) [000848] -A------R-- * ASG long ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB120 STMT00180 ( ??? ... ??? ) ( 3, 4) [000846] -A------R-- * ASG long ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 ( 3, 4) [000844] ----------- \--* ADD long ( 1, 1) [000841] ----------- +--* LCL_VAR long V36 loc32 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) ( 1, 3) [000852] -A------R-- * ASG byref ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB120 STMT00183 ( ??? ... ??? ) ( 4, 3) [000855] -A-XG---R-- * ASG int ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 ( 4, 3) [000850] ---XG------ \--* IND ubyte ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00377 ( ??? ... ??? ) ( 2, 3) [001836] -A------R-- * ASG ushort ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? ( 4, 3) [001799] -A-XG---R-- * ASG int ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 ( 4, 3) [001797] ---XG------ \--* IND int ( 3, 4) [002795] -------N--- \--* ADD byref ( 1, 1) [000857] ----------- +--* LCL_VAR byref V62 tmp22 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? ( 8, 7) [001806] ---XG------ * JTRUE void ( 6, 5) [001805] N--XG--N-U- \--* GE int ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 ( 4, 3) [001839] ---XG------ \--* IND int ( 3, 4) [002799] -------N--- \--* ADD byref ( 1, 1) [001801] ----------- +--* LCL_VAR byref V62 tmp22 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? ( 5, 6) [001815] -A-XGO--R-- * ASG byref ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 ( 5, 6) [002806] ---X-O-N--- \--* COMMA byref ( 2, 2) [002802] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002801] ----------- | \--* LCL_VAR byref V62 tmp22 ( 3, 4) [002805] -----O----- \--* ADD byref ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? ( 22, 24) [001828] -A-XGO----- * ASG short ( 20, 22) [001825] ---XGO-N--- +--* COMMA short ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 ( 4, 3) [001818] ---XG------ | | \--* IND int ( 3, 4) [002808] -------N--- | | \--* ADD byref ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 ( 11, 11) [002809] ---XGO-N--- | \--* IND short ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref ( 3, 2) [001823] ---XG------ | +--* IND byref ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 ( 4, 6) [001822] ----------- | \--* LSH long ( 2, 3) [001820] ---------U- | +--* CAST long <- uint ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? ( 8, 8) [001834] -A-XG---R-- * ASG int ( 4, 3) [001833] ---XG--N--- +--* IND int ( 3, 4) [002811] -------N--- | \--* ADD byref ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V62 tmp22 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 ( 3, 4) [001832] ----------- \--* ADD int ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? ( 18, 15) [001809] --CXG------ * CALL r2r_ind void ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V62 tmp22 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) ( 5, 6) [000863] ----------- * JTRUE void ( 3, 4) [000862] J------N--- \--* EQ int ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) ( 5, 6) [000877] ----------- * JTRUE void ( 3, 4) [000876] J------N--- \--* LE int ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) ( 5, 6) [000881] ----------- * JTRUE void ( 3, 4) [000880] J------N--- \--* LT int ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) ( 20, 25) [000901] ---XGO----- * JTRUE void ( 18, 23) [000900] N--XGO-N-U- \--* NE int ( 16, 21) [000899] ---XGO----- +--* ADD int ( 14, 18) [000896] ---XGO----- | +--* COMMA int ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 ( 8, 9) [002813] ---XGO----- | | \--* IND int ( 6, 8) [000895] -----O-N--- | | \--* ADD byref ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 ( 4, 6) [000893] ----------- | | \--* LSH long ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) ( 4, 3) [001896] -A-XG---R-- * ASG ref ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 ( 4, 3) [001843] ---XG------ \--* IND ref ( 3, 4) [002815] -------N--- \--* ADD byref ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] ( 5, 6) [001848] ----------- * JTRUE void ( 3, 4) [001847] J------N--- \--* EQ int ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 ( 1, 2) [001846] ----------- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] ( 4, 3) [001851] -A-XG---R-- * ASG int ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 ( 4, 3) [001849] ---XG------ \--* IND int ( 3, 4) [002817] -------N--- \--* ADD byref ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] ( 7, 8) [001856] ---X------- * JTRUE void ( 5, 6) [001855] N--X---N-U- \--* NE int ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] ( 8, 7) [001866] ---XG------ * JTRUE void ( 6, 5) [001865] N--XG--N-U- \--* GE int ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 ( 4, 3) [001899] ---XG------ \--* IND int ( 3, 4) [002821] -------N--- \--* ADD byref ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] ( 5, 6) [001872] -A-XGO--R-- * ASG byref ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 ( 5, 6) [002828] ---X-O-N--- \--* COMMA byref ( 2, 2) [002824] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002823] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [002827] -----O----- \--* ADD byref ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] ( 34, 39) [001888] -A-XGO----- * ASG short ( 20, 22) [001882] ---XGO-N--- +--* COMMA short ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 ( 4, 3) [001875] ---XG------ | | \--* IND int ( 3, 4) [002830] -------N--- | | \--* ADD byref ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 ( 11, 11) [002831] ---XGO-N--- | \--* IND short ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref ( 3, 2) [001880] ---XG------ | +--* IND byref ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 ( 4, 6) [001879] ----------- | \--* LSH long ( 2, 3) [001877] ---------U- | +--* CAST long <- uint ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 ( 5, 4) [002844] n---GO----- \--* IND ushort ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] ( 1, 1) [002839] -------N--- \--* ADD byref ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] ( 8, 8) [001894] -A-XG---R-- * ASG int ( 4, 3) [001893] ---XG--N--- +--* IND int ( 3, 4) [002846] -------N--- | \--* ADD byref ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 ( 3, 4) [001892] ----------- \--* ADD int ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) ( 3, 4) [000911] -A------R-- * ASG int ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 ( 3, 4) [000909] ----------- \--* ADD int ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) ( 3, 4) [000868] -A------R-- * ASG int ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 ( 3, 4) [000866] ----------- \--* ADD int ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) ( 3, 4) [000873] -A------R-- * ASG int ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 ( 3, 4) [000871] ----------- \--* ADD int ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) ( 5, 6) [000828] ----------- * JTRUE void ( 3, 4) [000827] J------N--- \--* GT int ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) ( 5, 6) [000278] ----------- * JTRUE void ( 3, 4) [000277] N------N-U- \--* GT int ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) ( 13, 9) [000596] ----------- * SWITCH void ( 3, 4) [000595] ----------- \--* ADD int ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) ( 13, 9) [000600] ----------- * SWITCH void ( 3, 4) [000599] ----------- \--* ADD int ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) ( 5, 6) [000604] ----------- * JTRUE void ( 3, 4) [000603] J------N--- \--* EQ int ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) ( 5, 6) [000282] ----------- * JTRUE void ( 3, 4) [000281] J------N--- \--* EQ int ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) ( 5, 6) [000322] ----------- * JTRUE void ( 3, 4) [000321] J------N--- \--* EQ int ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) ( 5, 8) [000584] ----------- * JTRUE void ( 3, 6) [000583] J------N--- \--* NE int ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) ( 4, 3) [002119] -A-XG---R-- * ASG ref ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 ( 4, 3) [002066] ---XG------ \--* IND ref ( 3, 4) [002849] -------N--- \--* ADD byref ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) ( 5, 6) [000642] ----------- * JTRUE void ( 3, 4) [000641] J------N--- \--* GE int ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) ( 3, 4) [000735] -A------R-- * ASG int ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 ( 3, 4) [000733] ----------- \--* ADD int ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) ( 5, 5) [000739] ----------- * JTRUE void ( 3, 3) [000738] J------N--- \--* LE int ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) ( 1, 3) [000749] -A------R-- * ASG int ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) ( 1, 3) [000742] -A------R-- * ASG int ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00163 ( ??? ... 0x4FE ) ( 2, 3) [000746] -A------R-- * ASG int ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) ( 8, 8) [000647] ---XG------ * JTRUE void ( 6, 6) [000646] J--XG--N--- \--* NE int ( 4, 3) [000644] ---XG------ +--* IND ubyte ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) ( 5, 5) [000722] ----------- * JTRUE void ( 3, 3) [000721] J------N--- \--* GT int ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) ( 1, 3) [000729] -A------R-- * ASG int ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) ( 1, 3) [000725] -A------R-- * ASG int ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) ( 1, 3) [000656] -A------R-- * ASG long ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) ( 3, 4) [000654] -A------R-- * ASG long ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 ( 3, 4) [000652] ----------- \--* ADD long ( 1, 1) [000649] ----------- +--* LCL_VAR long V36 loc32 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) ( 4, 3) [000660] -A-XG---R-- * ASG int ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 ( 4, 3) [000658] ---XG------ \--* IND ubyte ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00146 ( ??? ... 0x51B ) ( 2, 3) [000664] -A------R-- * ASG int ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) ( 5, 6) [000668] ----------- * JTRUE void ( 3, 4) [000667] J------N--- \--* EQ int ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] ( 4, 3) [001905] -A-XG---R-- * ASG int ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 ( 4, 3) [001903] ---XG------ \--* IND int ( 3, 4) [002853] -------N--- \--* ADD byref ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] ( 8, 7) [001912] ---XG------ * JTRUE void ( 6, 5) [001911] N--XG--N-U- \--* GE int ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 ( 4, 3) [001942] ---XG------ \--* IND int ( 3, 4) [002857] -------N--- \--* ADD byref ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] ( 5, 6) [001920] -A-XGO--R-- * ASG byref ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 ( 5, 6) [002864] ---X-O-N--- \--* COMMA byref ( 2, 2) [002860] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002859] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [002863] -----O----- \--* ADD byref ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] ( 22, 24) [001933] -A-XGO----- * ASG short ( 20, 22) [001930] ---XGO-N--- +--* COMMA short ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 ( 4, 3) [001923] ---XG------ | | \--* IND int ( 3, 4) [002866] -------N--- | | \--* ADD byref ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 ( 11, 11) [002867] ---XGO-N--- | \--* IND short ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref ( 3, 2) [001928] ---XG------ | +--* IND byref ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 ( 4, 6) [001927] ----------- | \--* LSH long ( 2, 3) [001925] ---------U- | +--* CAST long <- uint ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] ( 8, 8) [001939] -A-XG---R-- * ASG int ( 4, 3) [001938] ---XG--N--- +--* IND int ( 3, 4) [002869] -------N--- | \--* ADD byref ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 ( 3, 4) [001937] ----------- \--* ADD int ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] ( 18, 15) [001914] --CXG------ * CALL r2r_ind void ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) ( 5, 6) [000680] ----------- * JTRUE void ( 3, 4) [000679] J------N--- \--* EQ int ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) ( 5, 6) [000684] ----------- * JTRUE void ( 3, 4) [000683] J------N--- \--* LE int ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) ( 5, 6) [000688] ----------- * JTRUE void ( 3, 4) [000687] J------N--- \--* LT int ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) ( 20, 25) [000708] ---XGO----- * JTRUE void ( 18, 23) [000707] N--XGO-N-U- \--* NE int ( 16, 21) [000706] ---XGO----- +--* ADD int ( 14, 18) [000703] ---XGO----- | +--* COMMA int ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 ( 8, 9) [002871] ---XGO----- | | \--* IND int ( 6, 8) [000702] -----O-N--- | | \--* ADD byref ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 ( 4, 6) [000700] ----------- | | \--* LSH long ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) ( 4, 3) [001999] -A-XG---R-- * ASG ref ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 ( 4, 3) [001946] ---XG------ \--* IND ref ( 3, 4) [002873] -------N--- \--* ADD byref ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] ( 5, 6) [001951] ----------- * JTRUE void ( 3, 4) [001950] J------N--- \--* EQ int ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 ( 1, 2) [001949] ----------- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] ( 4, 3) [001954] -A-XG---R-- * ASG int ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 ( 4, 3) [001952] ---XG------ \--* IND int ( 3, 4) [002875] -------N--- \--* ADD byref ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] ( 7, 8) [001959] ---X------- * JTRUE void ( 5, 6) [001958] N--X---N-U- \--* NE int ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] ( 8, 7) [001969] ---XG------ * JTRUE void ( 6, 5) [001968] N--XG--N-U- \--* GE int ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 ( 4, 3) [002002] ---XG------ \--* IND int ( 3, 4) [002879] -------N--- \--* ADD byref ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] ( 5, 6) [001975] -A-XGO--R-- * ASG byref ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 ( 5, 6) [002886] ---X-O-N--- \--* COMMA byref ( 2, 2) [002882] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002881] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [002885] -----O----- \--* ADD byref ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] ( 34, 39) [001991] -A-XGO----- * ASG short ( 20, 22) [001985] ---XGO-N--- +--* COMMA short ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 ( 4, 3) [001978] ---XG------ | | \--* IND int ( 3, 4) [002888] -------N--- | | \--* ADD byref ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 ( 11, 11) [002889] ---XGO-N--- | \--* IND short ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref ( 3, 2) [001983] ---XG------ | +--* IND byref ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 ( 4, 6) [001982] ----------- | \--* LSH long ( 2, 3) [001980] ---------U- | +--* CAST long <- uint ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 ( 5, 4) [002902] n---GO----- \--* IND ushort ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] ( 1, 1) [002897] -------N--- \--* ADD byref ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] ( 8, 8) [001997] -A-XG---R-- * ASG int ( 4, 3) [001996] ---XG--N--- +--* IND int ( 3, 4) [002904] -------N--- | \--* ADD byref ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 ( 3, 4) [001995] ----------- \--* ADD int ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) ( 3, 4) [000718] -A------R-- * ASG int ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 ( 3, 4) [000716] ----------- \--* ADD int ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) ( 3, 4) [000673] -A------R-- * ASG int ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 ( 3, 4) [000671] ----------- \--* ADD int ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) ( 12, 11) [000612] ----------- * JTRUE void ( 10, 9) [000611] J------N--- \--* NE int ( 8, 6) [000609] ----------- +--* OR int ( 6, 4) [000607] ----------- | +--* NE int ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) ( 5, 6) [000616] ----------- * JTRUE void ( 3, 4) [000615] J------N--- \--* LT int ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) ( 5, 5) [000628] ----------- * JTRUE void ( 3, 3) [000627] J------N--- \--* GE int ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) ( 8, 8) [000633] ---XG------ * JTRUE void ( 6, 6) [000632] J--XG--N--- \--* EQ int ( 4, 3) [000630] ---XG------ +--* IND ubyte ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) ( 4, 3) [002059] -A-XG---R-- * ASG ref ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 ( 4, 3) [002006] ---XG------ \--* IND ref ( 3, 4) [002907] -------N--- \--* ADD byref ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] ( 5, 6) [002011] ----------- * JTRUE void ( 3, 4) [002010] J------N--- \--* EQ int ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 ( 1, 2) [002009] ----------- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] ( 4, 3) [002014] -A-XG---R-- * ASG int ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 ( 4, 3) [002012] ---XG------ \--* IND int ( 3, 4) [002909] -------N--- \--* ADD byref ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] ( 7, 8) [002019] ---X------- * JTRUE void ( 5, 6) [002018] N--X---N-U- \--* NE int ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] ( 8, 7) [002029] ---XG------ * JTRUE void ( 6, 5) [002028] N--XG--N-U- \--* GE int ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 ( 4, 3) [002062] ---XG------ \--* IND int ( 3, 4) [002913] -------N--- \--* ADD byref ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] ( 5, 6) [002035] -A-XGO--R-- * ASG byref ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 ( 5, 6) [002920] ---X-O-N--- \--* COMMA byref ( 2, 2) [002916] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002915] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [002919] -----O----- \--* ADD byref ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] ( 34, 39) [002051] -A-XGO----- * ASG short ( 20, 22) [002045] ---XGO-N--- +--* COMMA short ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 ( 4, 3) [002038] ---XG------ | | \--* IND int ( 3, 4) [002922] -------N--- | | \--* ADD byref ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 ( 11, 11) [002923] ---XGO-N--- | \--* IND short ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref ( 3, 2) [002043] ---XG------ | +--* IND byref ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 ( 4, 6) [002042] ----------- | \--* LSH long ( 2, 3) [002040] ---------U- | +--* CAST long <- uint ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 ( 5, 4) [002936] n---GO----- \--* IND ushort ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] ( 1, 1) [002931] -------N--- \--* ADD byref ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] ( 8, 8) [002057] -A-XG---R-- * ASG int ( 4, 3) [002056] ---XG--N--- +--* IND int ( 3, 4) [002938] -------N--- | \--* ADD byref ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 ( 3, 4) [002055] ----------- \--* ADD int ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) ( 1, 3) [000624] -A------R-- * ASG int ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] ( 5, 6) [002071] ----------- * JTRUE void ( 3, 4) [002070] J------N--- \--* EQ int ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 ( 1, 2) [002069] ----------- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] ( 4, 3) [002074] -A-XG---R-- * ASG int ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 ( 4, 3) [002072] ---XG------ \--* IND int ( 3, 4) [002942] -------N--- \--* ADD byref ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] ( 7, 8) [002079] ---X------- * JTRUE void ( 5, 6) [002078] N--X---N-U- \--* NE int ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] ( 8, 7) [002089] ---XG------ * JTRUE void ( 6, 5) [002088] N--XG--N-U- \--* GE int ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 ( 4, 3) [002122] ---XG------ \--* IND int ( 3, 4) [002946] -------N--- \--* ADD byref ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] ( 5, 6) [002095] -A-XGO--R-- * ASG byref ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 ( 5, 6) [002953] ---X-O-N--- \--* COMMA byref ( 2, 2) [002949] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002948] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [002952] -----O----- \--* ADD byref ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] ( 34, 39) [002111] -A-XGO----- * ASG short ( 20, 22) [002105] ---XGO-N--- +--* COMMA short ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 ( 4, 3) [002098] ---XG------ | | \--* IND int ( 3, 4) [002955] -------N--- | | \--* ADD byref ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 ( 11, 11) [002956] ---XGO-N--- | \--* IND short ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref ( 3, 2) [002103] ---XG------ | +--* IND byref ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 ( 4, 6) [002102] ----------- | \--* LSH long ( 2, 3) [002100] ---------U- | +--* CAST long <- uint ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 ( 5, 4) [002969] n---GO----- \--* IND ushort ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] ( 1, 1) [002964] -------N--- \--* ADD byref ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] ( 8, 8) [002117] -A-XG---R-- * ASG int ( 4, 3) [002116] ---XG--N--- +--* IND int ( 3, 4) [002971] -------N--- | \--* ADD byref ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 ( 3, 4) [002115] ----------- \--* ADD int ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) ( 4, 3) [002179] -A-XG---R-- * ASG ref ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 ( 4, 3) [002126] ---XG------ \--* IND ref ( 3, 4) [002974] -------N--- \--* ADD byref ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] ( 5, 6) [002131] ----------- * JTRUE void ( 3, 4) [002130] J------N--- \--* EQ int ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 ( 1, 2) [002129] ----------- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] ( 4, 3) [002134] -A-XG---R-- * ASG int ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 ( 4, 3) [002132] ---XG------ \--* IND int ( 3, 4) [002976] -------N--- \--* ADD byref ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] ( 7, 8) [002139] ---X------- * JTRUE void ( 5, 6) [002138] N--X---N-U- \--* NE int ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] ( 8, 7) [002149] ---XG------ * JTRUE void ( 6, 5) [002148] N--XG--N-U- \--* GE int ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 ( 4, 3) [002182] ---XG------ \--* IND int ( 3, 4) [002980] -------N--- \--* ADD byref ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] ( 5, 6) [002155] -A-XGO--R-- * ASG byref ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 ( 5, 6) [002987] ---X-O-N--- \--* COMMA byref ( 2, 2) [002983] ---X-O----- +--* NULLCHECK byte ( 1, 1) [002982] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [002986] -----O----- \--* ADD byref ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] ( 34, 39) [002171] -A-XGO----- * ASG short ( 20, 22) [002165] ---XGO-N--- +--* COMMA short ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 ( 4, 3) [002158] ---XG------ | | \--* IND int ( 3, 4) [002989] -------N--- | | \--* ADD byref ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 ( 11, 11) [002990] ---XGO-N--- | \--* IND short ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref ( 3, 2) [002163] ---XG------ | +--* IND byref ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 ( 4, 6) [002162] ----------- | \--* LSH long ( 2, 3) [002160] ---------U- | +--* CAST long <- uint ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 ( 5, 4) [003003] n---GO----- \--* IND ushort ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] ( 1, 1) [002998] -------N--- \--* ADD byref ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] ( 8, 8) [002177] -A-XG---R-- * ASG int ( 4, 3) [002176] ---XG--N--- +--* IND int ( 3, 4) [003005] -------N--- | \--* ADD byref ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 ( 3, 4) [002175] ----------- \--* ADD int ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) ( 1, 3) [000812] -A------R-- * ASG int ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) ( 3, 4) [000810] -A------R-- * ASG int ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [000808] ----------- \--* ADD int ( 1, 1) [000806] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) ( 9, 10) [002225] -A-XG---R-- * ASG ushort ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 ( 9, 10) [000819] ---XG------ \--* IND ushort ( 6, 8) [000818] -------N--- \--* ADD long ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 ( 4, 6) [000817] ----------- \--* LSH long ( 2, 3) [000814] ----------- +--* CAST long <- int ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? ( 4, 3) [002188] -A-XG---R-- * ASG int ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 ( 4, 3) [002186] ---XG------ \--* IND int ( 3, 4) [003008] -------N--- \--* ADD byref ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? ( 8, 7) [002195] ---XG------ * JTRUE void ( 6, 5) [002194] N--XG--N-U- \--* GE int ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 ( 4, 3) [002228] ---XG------ \--* IND int ( 3, 4) [003012] -------N--- \--* ADD byref ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? ( 5, 6) [002204] -A-XGO--R-- * ASG byref ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 ( 5, 6) [003019] ---X-O-N--- \--* COMMA byref ( 2, 2) [003015] ---X-O----- +--* NULLCHECK byte ( 1, 1) [003014] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [003018] -----O----- \--* ADD byref ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? ( 22, 24) [002217] -A-XGO----- * ASG short ( 20, 22) [002214] ---XGO-N--- +--* COMMA short ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 ( 4, 3) [002207] ---XG------ | | \--* IND int ( 3, 4) [003021] -------N--- | | \--* ADD byref ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 ( 11, 11) [003022] ---XGO-N--- | \--* IND short ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref ( 3, 2) [002212] ---XG------ | +--* IND byref ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 ( 4, 6) [002211] ----------- | \--* LSH long ( 2, 3) [002209] ---------U- | +--* CAST long <- uint ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? ( 8, 8) [002223] -A-XG---R-- * ASG int ( 4, 3) [002222] ---XG--N--- +--* IND int ( 3, 4) [003024] -------N--- | \--* ADD byref ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 ( 3, 4) [002221] ----------- \--* ADD int ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? ( 18, 15) [002198] --CXG------ * CALL r2r_ind void ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) ( 7, 8) [000757] ----------- * JTRUE void ( 5, 6) [000756] J------N--- \--* GE int ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) ( 13, 15) [000791] ---XG------ * JTRUE void ( 11, 13) [000790] J--XG--N--- \--* EQ int ( 9, 10) [000788] ---XG------ +--* IND ushort ( 6, 8) [000787] -------N--- | \--* ADD long ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000786] ----------- | \--* LSH long ( 2, 3) [000783] ----------- | +--* CAST long <- int ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) ( 13, 14) [000802] ---XG------ * JTRUE void ( 11, 12) [000801] N--XG--N-U- \--* NE int ( 9, 10) [000799] ---XG------ +--* IND ushort ( 6, 8) [000798] -------N--- | \--* ADD long ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000797] ----------- | \--* LSH long ( 2, 3) [000794] ----------- | +--* CAST long <- int ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) ( 7, 8) [000764] ----------- * JTRUE void ( 5, 6) [000763] J------N--- \--* GE int ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) ( 13, 15) [000775] ---XG------ * JTRUE void ( 11, 13) [000774] J--XG--N--- \--* EQ int ( 9, 10) [000772] ---XG------ +--* IND ushort ( 6, 8) [000771] -------N--- | \--* ADD long ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000770] ----------- | \--* LSH long ( 2, 3) [000767] ----------- | +--* CAST long <- int ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) ( 3, 4) [000780] -A------R-- * ASG int ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [000778] ----------- \--* ADD int ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) ( 7, 8) [000289] ----------- * JTRUE void ( 5, 6) [000288] J------N--- \--* GE int ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) ( 13, 15) [000300] ---XG------ * JTRUE void ( 11, 13) [000299] J--XG--N--- \--* EQ int ( 9, 10) [000297] ---XG------ +--* IND ushort ( 6, 8) [000296] -------N--- | \--* ADD long ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000295] ----------- | \--* LSH long ( 2, 3) [000292] ----------- | +--* CAST long <- int ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) ( 1, 3) [000310] -A------R-- * ASG int ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) ( 3, 4) [000308] -A------R-- * ASG int ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [000306] ----------- \--* ADD int ( 1, 1) [000304] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) ( 9, 10) [002283] -A-XG---R-- * ASG ushort ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 ( 9, 10) [000317] ---XG------ \--* IND ushort ( 6, 8) [000316] -------N--- \--* ADD long ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 ( 4, 6) [000315] ----------- \--* LSH long ( 2, 3) [000312] ----------- +--* CAST long <- int ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? ( 4, 3) [002246] -A-XG---R-- * ASG int ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 ( 4, 3) [002244] ---XG------ \--* IND int ( 3, 4) [003027] -------N--- \--* ADD byref ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? ( 8, 7) [002253] ---XG------ * JTRUE void ( 6, 5) [002252] N--XG--N-U- \--* GE int ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 ( 4, 3) [002286] ---XG------ \--* IND int ( 3, 4) [003031] -------N--- \--* ADD byref ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? ( 5, 6) [002262] -A-XGO--R-- * ASG byref ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 ( 5, 6) [003038] ---X-O-N--- \--* COMMA byref ( 2, 2) [003034] ---X-O----- +--* NULLCHECK byte ( 1, 1) [003033] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [003037] -----O----- \--* ADD byref ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? ( 22, 24) [002275] -A-XGO----- * ASG short ( 20, 22) [002272] ---XGO-N--- +--* COMMA short ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 ( 4, 3) [002265] ---XG------ | | \--* IND int ( 3, 4) [003040] -------N--- | | \--* ADD byref ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 ( 11, 11) [003041] ---XGO-N--- | \--* IND short ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref ( 3, 2) [002270] ---XG------ | +--* IND byref ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 ( 4, 6) [002269] ----------- | \--* LSH long ( 2, 3) [002267] ---------U- | +--* CAST long <- uint ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? ( 8, 8) [002281] -A-XG---R-- * ASG int ( 4, 3) [002280] ---XG--N--- +--* IND int ( 3, 4) [003043] -------N--- | \--* ADD byref ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 ( 3, 4) [002279] ----------- \--* ADD int ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? ( 18, 15) [002256] --CXG------ * CALL r2r_ind void ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) ( 1, 3) [000325] -A------R-- * ASG int ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) ( 1, 3) [000328] -A------R-- * ASG int ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) ( 5, 6) [000332] ----------- * JTRUE void ( 3, 4) [000331] J------N--- \--* EQ int ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) ( 7, 8) [000425] ----------- * JTRUE void ( 5, 6) [000424] J------N--- \--* GE int ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) ( 13, 15) [000575] ---XG------ * JTRUE void ( 11, 13) [000574] N--XG--N-U- \--* EQ int ( 9, 10) [000572] ---XG------ +--* IND ushort ( 6, 8) [000571] -------N--- | \--* ADD long ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000570] ----------- | \--* LSH long ( 2, 3) [000567] ----------- | +--* CAST long <- int ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) ( 9, 11) [000434] ----------- * JTRUE void ( 7, 9) [000433] J------N--- \--* GE int ( 3, 4) [000428] ----------- +--* ADD int ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) ( 13, 15) [000548] ---XG------ * JTRUE void ( 11, 13) [000547] N--XG--N-U- \--* NE int ( 9, 10) [000545] ---XG------ +--* IND ushort ( 6, 8) [000544] -------N--- | \--* ADD long ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000543] ----------- | \--* LSH long ( 2, 3) [000540] ----------- | +--* CAST long <- int ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) ( 15, 18) [000561] ---XG------ * JTRUE void ( 13, 16) [000560] N--XG--N-U- \--* NE int ( 11, 13) [000558] ---XG------ +--* IND ushort ( 8, 11) [000557] -------N--- | \--* ADD long ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 ( 6, 9) [000556] ----------- | \--* LSH long ( 4, 6) [000553] ----------- | +--* CAST long <- int ( 3, 4) [000552] ----------- | | \--* ADD int ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) ( 1, 3) [000564] -A------R-- * ASG int ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) ( 9, 11) [000443] ----------- * JTRUE void ( 7, 9) [000442] J------N--- \--* GE int ( 3, 4) [000437] ----------- +--* ADD int ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) ( 13, 15) [000457] ---XG------ * JTRUE void ( 11, 13) [000456] N--XG--N-U- \--* NE int ( 9, 10) [000454] ---XG------ +--* IND ushort ( 6, 8) [000453] -------N--- | \--* ADD long ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000452] ----------- | \--* LSH long ( 2, 3) [000449] ----------- | +--* CAST long <- int ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) ( 15, 18) [000470] ---XG------ * JTRUE void ( 13, 16) [000469] J--XG--N--- \--* EQ int ( 11, 13) [000467] ---XG------ +--* IND ushort ( 8, 11) [000466] -------N--- | \--* ADD long ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 ( 6, 9) [000465] ----------- | \--* LSH long ( 4, 6) [000462] ----------- | +--* CAST long <- int ( 3, 4) [000461] ----------- | | \--* ADD int ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] ( 4, 3) [002304] -A-XG---R-- * ASG int ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 ( 4, 3) [002302] ---XG------ \--* IND int ( 3, 4) [003048] -------N--- \--* ADD byref ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] ( 8, 7) [002311] ---XG------ * JTRUE void ( 6, 5) [002310] N--XG--N-U- \--* GE int ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 ( 4, 3) [002341] ---XG------ \--* IND int ( 3, 4) [003052] -------N--- \--* ADD byref ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] ( 5, 6) [002319] -A-XGO--R-- * ASG byref ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 ( 5, 6) [003059] ---X-O-N--- \--* COMMA byref ( 2, 2) [003055] ---X-O----- +--* NULLCHECK byte ( 1, 1) [003054] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [003058] -----O----- \--* ADD byref ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] ( 22, 24) [002332] -A-XGO----- * ASG short ( 20, 22) [002329] ---XGO-N--- +--* COMMA short ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 ( 4, 3) [002322] ---XG------ | | \--* IND int ( 3, 4) [003061] -------N--- | | \--* ADD byref ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 ( 11, 11) [003062] ---XGO-N--- | \--* IND short ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref ( 3, 2) [002327] ---XG------ | +--* IND byref ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 ( 4, 6) [002326] ----------- | \--* LSH long ( 2, 3) [002324] ---------U- | +--* CAST long <- uint ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] ( 8, 8) [002338] -A-XG---R-- * ASG int ( 4, 3) [002337] ---XG--N--- +--* IND int ( 3, 4) [003064] -------N--- | \--* ADD byref ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 ( 3, 4) [002336] ----------- \--* ADD int ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) ( 3, 4) [000537] -A------R-- * ASG int ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 ( 3, 4) [000535] ----------- \--* ADD int ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) ( 3, 4) [000475] -A------R-- * ASG int ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 ( 3, 4) [000473] ----------- \--* ADD int ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) ( 1, 3) [000479] -A------R-- * ASG int ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB219 STMT00109 ( ??? ... ??? ) ( 7, 8) [000485] ----------- * JTRUE void ( 5, 6) [000484] J------N--- \--* GE int ( 1, 1) [000476] ----------- +--* LCL_VAR int V54 tmp14 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) ( 13, 15) [000532] ---XG------ * JTRUE void ( 11, 13) [000531] J--XG--N--- \--* EQ int ( 9, 10) [000529] ---XG------ +--* IND ushort ( 6, 8) [000528] -------N--- | \--* ADD long ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000527] ----------- | \--* LSH long ( 2, 3) [000524] ----------- | +--* CAST long <- int ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) ( 5, 6) [000489] ----------- * JTRUE void ( 3, 4) [000488] J------N--- \--* LE int ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) ( 1, 3) [000521] -A------R-- * ASG int ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) ( 8, 8) [000494] ---XG------ * JTRUE void ( 6, 6) [000493] J--XG--N--- \--* EQ int ( 4, 3) [000491] ---XG------ +--* IND ubyte ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) ( 6, 5) [000517] -A-XG---R-- * ASG int ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 ( 6, 5) [000515] ---XG------ \--* SUB int ( 4, 3) [000513] ---XG------ +--* IND int ( 3, 4) [003067] -------N--- | \--* ADD byref ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) ( 1, 3) [000497] -A------R-- * ASG int ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) ( 1, 3) [000511] -A------R-- * ASG int ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] ( 4, 3) [002351] -A-XG---R-- * ASG int ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 ( 4, 3) [002349] ---XG------ \--* IND int ( 3, 4) [003071] -------N--- \--* ADD byref ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] ( 8, 7) [002358] ---XG------ * JTRUE void ( 6, 5) [002357] N--XG--N-U- \--* GE int ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 ( 4, 3) [002388] ---XG------ \--* IND int ( 3, 4) [003075] -------N--- \--* ADD byref ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] ( 5, 6) [002366] -A-XGO--R-- * ASG byref ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 ( 5, 6) [003082] ---X-O-N--- \--* COMMA byref ( 2, 2) [003078] ---X-O----- +--* NULLCHECK byte ( 1, 1) [003077] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [003081] -----O----- \--* ADD byref ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] ( 22, 24) [002379] -A-XGO----- * ASG short ( 20, 22) [002376] ---XGO-N--- +--* COMMA short ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 ( 4, 3) [002369] ---XG------ | | \--* IND int ( 3, 4) [003084] -------N--- | | \--* ADD byref ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 ( 11, 11) [003085] ---XGO-N--- | \--* IND short ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref ( 3, 2) [002374] ---XG------ | +--* IND byref ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 ( 4, 6) [002373] ----------- | \--* LSH long ( 2, 3) [002371] ---------U- | +--* CAST long <- uint ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] ( 8, 8) [002385] -A-XG---R-- * ASG int ( 4, 3) [002384] ---XG--N--- +--* IND int ( 3, 4) [003087] -------N--- | \--* ADD byref ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 ( 3, 4) [002383] ----------- \--* ADD int ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] ( 18, 15) [002360] --CXG------ * CALL r2r_ind void ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) ( 7, 8) [000342] ----------- * JTRUE void ( 5, 6) [000341] J------N--- \--* GE int ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) ( 13, 15) [000353] ---XG------ * JTRUE void ( 11, 13) [000352] J--XG--N--- \--* EQ int ( 9, 10) [000350] ---XG------ +--* IND ushort ( 6, 8) [000349] -------N--- | \--* ADD long ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000348] ----------- | \--* LSH long ( 2, 3) [000345] ----------- | +--* CAST long <- int ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) ( 13, 15) [000418] ---XG------ * JTRUE void ( 11, 13) [000417] N--XG--N-U- \--* NE int ( 9, 10) [000415] ---XG------ +--* IND ushort ( 6, 8) [000414] -------N--- | \--* ADD long ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000413] ----------- | \--* LSH long ( 2, 3) [000410] ----------- | +--* CAST long <- int ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) ( 1, 3) [000363] -A------R-- * ASG int ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) ( 3, 4) [000361] -A------R-- * ASG int ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [000359] ----------- \--* ADD int ( 1, 1) [000357] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) ( 9, 10) [002435] -A-XG---R-- * ASG ushort ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 ( 9, 10) [000370] ---XG------ \--* IND ushort ( 6, 8) [000369] -------N--- \--* ADD long ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 ( 4, 6) [000368] ----------- \--* LSH long ( 2, 3) [000365] ----------- +--* CAST long <- int ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? ( 4, 3) [002398] -A-XG---R-- * ASG int ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 ( 4, 3) [002396] ---XG------ \--* IND int ( 3, 4) [003090] -------N--- \--* ADD byref ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? ( 8, 7) [002405] ---XG------ * JTRUE void ( 6, 5) [002404] N--XG--N-U- \--* GE int ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 ( 4, 3) [002438] ---XG------ \--* IND int ( 3, 4) [003094] -------N--- \--* ADD byref ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? ( 5, 6) [002414] -A-XGO--R-- * ASG byref ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 ( 5, 6) [003101] ---X-O-N--- \--* COMMA byref ( 2, 2) [003097] ---X-O----- +--* NULLCHECK byte ( 1, 1) [003096] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [003100] -----O----- \--* ADD byref ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? ( 22, 24) [002427] -A-XGO----- * ASG short ( 20, 22) [002424] ---XGO-N--- +--* COMMA short ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 ( 4, 3) [002417] ---XG------ | | \--* IND int ( 3, 4) [003103] -------N--- | | \--* ADD byref ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 ( 11, 11) [003104] ---XGO-N--- | \--* IND short ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref ( 3, 2) [002422] ---XG------ | +--* IND byref ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 ( 4, 6) [002421] ----------- | \--* LSH long ( 2, 3) [002419] ---------U- | +--* CAST long <- uint ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? ( 8, 8) [002433] -A-XG---R-- * ASG int ( 4, 3) [002432] ---XG--N--- +--* IND int ( 3, 4) [003106] -------N--- | \--* ADD byref ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 ( 3, 4) [002431] ----------- \--* ADD int ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? ( 18, 15) [002408] --CXG------ * CALL r2r_ind void ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) ( 1, 3) [000399] -A------R-- * ASG int ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) ( 3, 4) [000397] -A------R-- * ASG int ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [000395] ----------- \--* ADD int ( 1, 1) [000393] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) ( 9, 10) [002481] -A-XG---R-- * ASG ushort ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 ( 9, 10) [000406] ---XG------ \--* IND ushort ( 6, 8) [000405] -------N--- \--* ADD long ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 ( 4, 6) [000404] ----------- \--* LSH long ( 2, 3) [000401] ----------- +--* CAST long <- int ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? ( 4, 3) [002444] -A-XG---R-- * ASG int ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 ( 4, 3) [002442] ---XG------ \--* IND int ( 3, 4) [003109] -------N--- \--* ADD byref ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? ( 8, 7) [002451] ---XG------ * JTRUE void ( 6, 5) [002450] N--XG--N-U- \--* GE int ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 ( 4, 3) [002484] ---XG------ \--* IND int ( 3, 4) [003113] -------N--- \--* ADD byref ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? ( 5, 6) [002460] -A-XGO--R-- * ASG byref ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 ( 5, 6) [003120] ---X-O-N--- \--* COMMA byref ( 2, 2) [003116] ---X-O----- +--* NULLCHECK byte ( 1, 1) [003115] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [003119] -----O----- \--* ADD byref ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? ( 22, 24) [002473] -A-XGO----- * ASG short ( 20, 22) [002470] ---XGO-N--- +--* COMMA short ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 ( 4, 3) [002463] ---XG------ | | \--* IND int ( 3, 4) [003122] -------N--- | | \--* ADD byref ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 ( 11, 11) [003123] ---XGO-N--- | \--* IND short ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref ( 3, 2) [002468] ---XG------ | +--* IND byref ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 ( 4, 6) [002467] ----------- | \--* LSH long ( 2, 3) [002465] ---------U- | +--* CAST long <- uint ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? ( 8, 8) [002479] -A-XG---R-- * ASG int ( 4, 3) [002478] ---XG--N--- +--* IND int ( 3, 4) [003125] -------N--- | \--* ADD byref ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 ( 3, 4) [002477] ----------- \--* ADD int ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? ( 18, 15) [002454] --CXG------ * CALL r2r_ind void ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) ( 7, 8) [000378] ----------- * JTRUE void ( 5, 6) [000377] J------N--- \--* GE int ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) ( 13, 15) [000389] ---XG------ * JTRUE void ( 11, 13) [000388] J--XG--N--- \--* EQ int ( 9, 10) [000386] ---XG------ +--* IND ushort ( 6, 8) [000385] -------N--- | \--* ADD long ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 ( 4, 6) [000384] ----------- | \--* LSH long ( 2, 3) [000381] ----------- | +--* CAST long <- int ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] ( 4, 3) [002494] -A-XG---R-- * ASG int ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 ( 4, 3) [002492] ---XG------ \--* IND int ( 3, 4) [003128] -------N--- \--* ADD byref ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] ( 8, 7) [002501] ---XG------ * JTRUE void ( 6, 5) [002500] N--XG--N-U- \--* GE int ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 ( 4, 3) [002531] ---XG------ \--* IND int ( 3, 4) [003132] -------N--- \--* ADD byref ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] ( 5, 6) [002509] -A-XGO--R-- * ASG byref ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 ( 5, 6) [003139] ---X-O-N--- \--* COMMA byref ( 2, 2) [003135] ---X-O----- +--* NULLCHECK byte ( 1, 1) [003134] ----------- | \--* LCL_VAR byref V00 arg0 ( 3, 4) [003138] -----O----- \--* ADD byref ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] ( 22, 24) [002522] -A-XGO----- * ASG short ( 20, 22) [002519] ---XGO-N--- +--* COMMA short ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 ( 4, 3) [002512] ---XG------ | | \--* IND int ( 3, 4) [003141] -------N--- | | \--* ADD byref ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 ( 11, 11) [003142] ---XGO-N--- | \--* IND short ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref ( 3, 2) [002517] ---XG------ | +--* IND byref ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 ( 4, 6) [002516] ----------- | \--* LSH long ( 2, 3) [002514] ---------U- | +--* CAST long <- uint ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] ( 8, 8) [002528] -A-XG---R-- * ASG int ( 4, 3) [002527] ---XG--N--- +--* IND int ( 3, 4) [003144] -------N--- | \--* ADD byref ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 ( 3, 4) [002526] ----------- \--* ADD int ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] ( 18, 15) [002503] --CXG------ * CALL r2r_ind void ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) ( 7, 8) [000210] ----------- * JTRUE void ( 5, 6) [000209] J------N--- \--* GE int ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) ( 1, 3) [000250] -A------R-- * ASG int ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) ( 3, 4) [000248] -A------R-- * ASG int ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 ( 3, 4) [000246] ----------- \--* ADD int ( 1, 1) [000244] ----------- +--* LCL_VAR int V16 loc12 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) ( 9, 10) [000259] -A-XG---R-- * ASG int ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 ( 9, 10) [000257] ---XG------ \--* IND ushort ( 6, 8) [000256] -------N--- \--* ADD long ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 ( 4, 6) [000255] ----------- \--* LSH long ( 2, 3) [000252] ----------- +--* CAST long <- int ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) ( 1, 3) [000263] -A------R-- * ASG int ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) ( 5, 6) [000266] ----------- * JTRUE void ( 3, 4) [000265] J------N--- \--* EQ int ( 1, 1) [000260] ----------- +--* LCL_VAR int V50 tmp10 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) ( 5, 6) [000270] ----------- * JTRUE void ( 3, 4) [000269] N------N-U- \--* NE int ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) ( 5, 5) [000214] -A------R-- * ASG byref ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) ( 9, 9) [000219] ---XG------ * JTRUE void ( 7, 7) [000218] J--XG--N--- \--* EQ int ( 5, 4) [000216] ---XG------ +--* IND bool ( 3, 4) [003148] -------N--- | \--* ADD byref ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) ( 5, 6) [000224] ----------- * JTRUE void ( 3, 4) [000223] J------N--- \--* NE int ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) ( 8, 8) [000229] ---XG------ * JTRUE void ( 6, 6) [000228] J--XG--N--- \--* NE int ( 4, 3) [000226] ---XG------ +--* IND int ( 3, 4) [003150] -------N--- | \--* ADD byref ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) ( 8, 8) [000235] ---XG------ * JTRUE void ( 6, 6) [000234] J--XG--N--- \--* LE int ( 4, 3) [002539] ---XG------ +--* IND int ( 3, 4) [003152] -------N--- | \--* ADD byref ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) ( 22, 20) [000241] --CXG------ * CALL r2r_ind void ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref ( 3, 4) [003155] -------N--- | \--* ADD byref ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) ( 0, 0) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Set block order *************** In fgSetBlockOrder() fgMarkLoopHead: Checking loop head block BB07: this block will execute a call fgMarkLoopHead: Checking loop head block BB08: no guaranteed callsite exits, marking method as fully interruptible fgMarkLoopHead: Checking loop head block BB31: method is already fully interruptible fgMarkLoopHead: Checking loop head block BB44: method is already fully interruptible fgMarkLoopHead: Checking loop head block BB89: method is already fully interruptible fgMarkLoopHead: Checking loop head block BB113: method is already fully interruptible fgMarkLoopHead: Checking loop head block BB118: method is already fully interruptible fgMarkLoopHead: Checking loop head block BB191: method is already fully interruptible fgMarkLoopHead: Checking loop head block BB218: method is already fully interruptible fgMarkLoopHead: Checking loop head block BB236: method is already fully interruptible The biggest BB has 26 tree nodes *************** Finishing PHASE Set block order Trees after Set block order ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N008 ( 5, 6) [001500] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 N006 ( 5, 6) [002549] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002545] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002544] ----------- | \--* LCL_VAR byref V01 arg1 N005 ( 3, 4) [002548] -----O----- \--* ADD byref N003 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 N004 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 ***** BB01 STMT00005 ( ??? ... 0x015 ) N007 ( 14, 14) [002563] -A--------- * COMMA void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 [+0] N006 ( 7, 7) [002562] -A------R-- \--* ASG int N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V167 tmp127 N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 N006 ( 7, 5) [002569] -A------R-- \--* ASG int N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 N006 ( 7, 5) [002578] -A------R-- \--* ASG int N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 N006 ( 7, 5) [002585] -A------R-- \--* ASG int N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 N006 ( 7, 5) [002592] -A------R-- \--* ASG int N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N007 ( 6, 8) [002606] -A--------- * COMMA void N003 ( 3, 4) [002602] -A------R-- +--* ASG byref N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] N006 ( 3, 4) [002605] -A------R-- \--* ASG int N005 ( 1, 1) [002603] D------N--- +--* LCL_VAR int V158 tmp118 N004 ( 3, 4) [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 N005 ( 2, 4) [002611] -A--------- \--* COMMA long N003 ( 1, 3) [002608] -A------R-- +--* ASG long N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 N003 ( 3, 4) [001358] ----------- \--* ADD int N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 N003 ( 3, 4) [001432] ----------- \--* ADD int N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void N003 ( 3, 6) [001375] N------N-U- \--* NE int N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 N003 ( 3, 4) [001379] ----------- \--* ADD int N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void N003 ( 3, 4) [001390] J------N--- \--* GE int N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void N003 ( 3, 4) [001397] J------N--- \--* LE int N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void N003 ( 3, 4) [001401] J------N--- \--* GE int N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void N003 ( 3, 4) [001405] J------N--- \--* LT int N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void N003 ( 3, 3) [001415] N------N-U- \--* NE int N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 N003 ( 3, 4) [001422] ----------- \--* ADD int N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 N003 ( 3, 4) [001427] ----------- \--* ADD int N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 7, 8) [001441] ----------- * JTRUE void N003 ( 5, 6) [001440] J------N--- \--* GE int N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N010 ( 13, 15) [001452] ---XG------ * JTRUE void N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 N005 ( 4, 6) [001447] ----------- | \--* LSH long N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [001457] ----------- \--* ADD int N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N010 ( 13, 14) [001471] ---XG------ * JTRUE void N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 N005 ( 4, 6) [001466] ----------- | \--* LSH long N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 7, 8) [001240] ----------- * JTRUE void N003 ( 5, 6) [001239] J------N--- \--* GE int N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N010 ( 13, 15) [001251] ---XG------ * JTRUE void N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 N005 ( 4, 6) [001246] ----------- | \--* LSH long N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [001254] ----------- \--* ADD int N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 7, 8) [001267] ----------- * JTRUE void N003 ( 5, 6) [001266] J------N--- \--* GE int N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N010 ( 13, 15) [001351] ---XG------ * JTRUE void N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 N005 ( 4, 6) [001346] ----------- | \--* LSH long N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 9, 11) [001276] ----------- * JTRUE void N005 ( 7, 9) [001275] J------N--- \--* GE int N003 ( 3, 4) [001270] ----------- +--* ADD int N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N010 ( 13, 15) [001287] ---XG------ * JTRUE void N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 N005 ( 4, 6) [001282] ----------- | \--* LSH long N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N010 ( 13, 15) [001340] ---XG------ * JTRUE void N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 N005 ( 4, 6) [001335] ----------- | \--* LSH long N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 N007 ( 6, 9) [001295] ----------- | \--* LSH long N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int N004 ( 3, 4) [001291] ----------- | | \--* ADD int N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 N003 ( 3, 4) [001303] ----------- \--* ADD int N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 7, 8) [001315] ----------- * JTRUE void N003 ( 5, 6) [001314] J------N--- \--* GE int N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V73 tmp33 N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 N005 ( 4, 6) [001324] ----------- | \--* LSH long N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 7, 8) [000079] ----------- * JTRUE void N003 ( 5, 6) [000078] J------N--- \--* GE int N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [001201] ----------- \--* ADD int N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 N005 ( 4, 6) [001210] ----------- \--* LSH long N003 ( 2, 3) [001207] ----------- +--* CAST long <- int N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V72 tmp32 N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void N003 ( 3, 4) [000086] J------N--- \--* GE int N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void N003 ( 3, 4) [000090] J------N--- \--* LT int N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void N003 ( 3, 3) [001182] N------N-U- \--* NE int N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 N005 ( 8, 8) [001191] ----------- \--* SUB int N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 N004 ( 6, 6) [001190] ----------- \--* MUL int N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N008 ( 5, 6) [001129] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 N006 ( 5, 6) [002621] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002617] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002616] ----------- | \--* LCL_VAR byref V01 arg1 N005 ( 3, 4) [002620] -----O----- \--* ADD byref N003 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 N004 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int N006 ( 3, 2) [001135] ---XG--N--- +--* IND int N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void N003 ( 3, 4) [001139] J------N--- \--* NE int N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 [+0] N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 [+8] N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void N003 ( 3, 3) [001166] J------N--- \--* EQ int N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool N004 ( 5, 4) [001124] ---XG--N--- +--* IND bool N003 ( 3, 4) [002632] -------N--- | \--* ADD byref N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int N004 ( 4, 3) [000104] ---XG--N--- +--* IND int N003 ( 3, 4) [002634] -------N--- | \--* ADD byref N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void N003 ( 3, 3) [000108] J------N--- \--* LT int N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 N003 ( 3, 3) [000112] ----------- \--* SUB int N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void N003 ( 3, 3) [000121] J------N--- \--* GT int N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 N003 ( 3, 3) [000125] ----------- \--* SUB int N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void N003 ( 3, 4) [000134] J------N--- \--* EQ int N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N007 ( 8, 7) [000140] ---XG------ * JTRUE void N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N007 ( 2, 6) [002647] -A--------- * COMMA void N003 ( 1, 3) [002643] -A------R-- +--* ASG byref N002 ( 1, 1) [002641] D------N--- | +--* LCL_VAR byref V151 tmp111 N001 ( 1, 2) [002642] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002646] -A------R-- \--* ASG int N005 ( 1, 1) [002644] D------N--- +--* LCL_VAR int V152 tmp112 N004 ( 1, 2) [002645] ----------- \--* CNS_INT int 0 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 N006 ( 1, 3) [002653] -A------R-- \--* ASG int N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void N003 ( 3, 4) [000180] J------N--- \--* EQ int N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 N011 ( 4, 6) [002665] ----------- \--* LSH long N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void N003 ( 3, 4) [000972] J------N--- \--* LT int N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 N003 ( 7, 5) [000988] ----------- \--* ADD int N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void N003 ( 5, 4) [000993] J------N--- \--* GT int N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void N003 ( 3, 3) [003157] J------N--- \--* LE int N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V28 loc24 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void N003 ( 3, 4) [001008] J------N--- \--* EQ int N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 N003 ( 3, 4) [001012] ----------- \--* ADD int N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void N003 ( 3, 3) [001020] J------N--- \--* LT int N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int N003 ( 3, 4) [001066] ----------- | \--* LSH int N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N007 ( 2, 6) [002679] -A--------- * COMMA void N003 ( 1, 3) [002675] -A------R-- +--* ASG byref N002 ( 1, 1) [002673] D------N--- | +--* LCL_VAR byref V159 tmp119 N001 ( 1, 2) [002674] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002678] -A------R-- \--* ASG int N005 ( 1, 1) [002676] D------N--- +--* LCL_VAR int V160 tmp120 N004 ( 1, 2) [002677] ----------- \--* CNS_INT int 0 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 5, 6) [001590] ----------- * JTRUE void N003 ( 3, 4) [001589] J------N--- \--* NE int N001 ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 N002 ( 1, 2) [001588] ----------- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002685] -A------R-- \--* ASG int N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N008 ( 5, 6) [001604] -A-X-O--R-- * ASG byref N007 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 N006 ( 5, 6) [002692] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002688] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002687] ----------- | \--* LCL_VAR ref V33 loc29 N005 ( 3, 4) [002691] -----O----- \--* ADD byref N003 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 N004 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00339 ( ??? ... ??? ) N007 ( 6, 7) [002699] -A--------- * COMMA void N003 ( 1, 3) [002695] -A------R-- +--* ASG byref N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 N006 ( 5, 4) [002698] -A------R-- \--* ASG int N005 ( 3, 2) [002696] D------N--- +--* LCL_VAR int V162 tmp122 N004 ( 1, 1) [002697] ----------- \--* LCL_VAR int V160 tmp120 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void N003 ( 3, 3) [001628] N------N-U- \--* GT int N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001669] -A------R-- * ASG byref N002 ( 1, 1) [001668] D------N--- +--* LCL_VAR byref V81 tmp41 N001 ( 1, 1) [001633] ----------- \--* LCL_VAR byref V161 tmp121 ***** BB96 STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001671] -A------R-- * ASG byref N002 ( 1, 1) [001670] D------N--- +--* LCL_VAR byref V82 tmp42 N001 ( 1, 1) [001636] ----------- \--* LCL_VAR byref V143 tmp103 ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N007 ( 2, 6) [002708] -A--------- * COMMA void N003 ( 1, 3) [002704] -A------R-- +--* ASG byref N002 ( 1, 1) [002702] D------N--- | +--* LCL_VAR byref V163 tmp123 N001 ( 1, 2) [002703] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002707] -A------R-- \--* ASG int N005 ( 1, 1) [002705] D------N--- +--* LCL_VAR int V164 tmp124 N004 ( 1, 2) [002706] ----------- \--* CNS_INT int 0 ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 5, 6) [001702] ----------- * JTRUE void N003 ( 3, 4) [001701] J------N--- \--* NE int N001 ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 N002 ( 1, 2) [001700] ----------- \--* CNS_INT ref null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002714] -A------R-- \--* ASG int N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N008 ( 5, 6) [001716] -A-X-O--R-- * ASG byref N007 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 N006 ( 5, 6) [002721] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002717] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002716] ----------- | \--* LCL_VAR ref V33 loc29 N005 ( 3, 4) [002720] -----O----- \--* ADD byref N003 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 N004 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 N006 ( 1, 3) [002727] -A------R-- \--* ASG int N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 N010 ( 8, 9) [002729] ---XGO-N--- | \--* IND int N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 N008 ( 4, 6) [001032] ----------- | \--* LSH long N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 N003 ( 3, 4) [001052] ----------- \--* ADD int N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 N011 ( 4, 6) [002736] ----------- \--* LSH long N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 N003 ( 3, 3) [001047] ----------- \--* ADD int N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void N003 ( 3, 3) [001004] J------N--- \--* GT int N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void N003 ( 3, 4) [000929] J------N--- \--* NE int N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V15 loc11 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 5, 6) [001759] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 N006 ( 5, 6) [002761] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002757] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002756] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [002760] -----O----- \--* ADD byref N003 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 N014 ( 13, 12) [002764] ---XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int N007 ( 4, 3) [001780] ---XG--N--- +--* IND int N006 ( 3, 4) [002779] -------N--- | \--* ADD byref N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N007 ( 10, 11) [002788] -A--------- * COMMA void N003 ( 3, 4) [002784] -A------R-- +--* ASG byref N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] N006 ( 7, 7) [002787] -A------R-- \--* ASG int N005 ( 3, 2) [002785] D------N--- +--* LCL_VAR int V166 tmp126 N004 ( 3, 4) [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 N005 ( 2, 4) [002793] -A--------- \--* COMMA long N003 ( 1, 3) [002790] -A------R-- +--* ASG long N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void N003 ( 3, 4) [000273] J------N--- \--* LE int N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N005 ( 8, 8) [000834] ---XG------ * JTRUE void N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 N003 ( 3, 4) [000844] ----------- \--* ADD long N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V36 loc32 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V60 tmp20 ***** BB120 STMT00183 ( ??? ... ??? ) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V62 tmp22 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V62 tmp22 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [001815] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 N006 ( 5, 6) [002806] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002802] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002801] ----------- | \--* LCL_VAR byref V62 tmp22 N005 ( 3, 4) [002805] -----O----- \--* ADD byref N003 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 N004 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002809] ---XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int N007 ( 4, 3) [001833] ---XG--N--- +--* IND int N006 ( 3, 4) [002811] -------N--- | \--* ADD byref N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V62 tmp22 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V62 tmp22 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void N003 ( 3, 4) [000862] J------N--- \--* EQ int N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void N003 ( 3, 4) [000876] J------N--- \--* LE int N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void N003 ( 3, 4) [000880] J------N--- \--* LT int N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 N008 ( 4, 6) [000893] ----------- | | \--* LSH long N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 5, 6) [001872] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 N006 ( 5, 6) [002828] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002824] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002823] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [002827] -----O----- \--* ADD byref N003 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002831] ---XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int N007 ( 4, 3) [001893] ---XG--N--- +--* IND int N006 ( 3, 4) [002846] -------N--- | \--* ADD byref N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 N003 ( 3, 4) [000909] ----------- \--* ADD int N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 N003 ( 3, 4) [000866] ----------- \--* ADD int N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 N003 ( 3, 4) [000871] ----------- \--* ADD int N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void N003 ( 3, 4) [000827] J------N--- \--* GT int N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void N003 ( 3, 4) [000641] J------N--- \--* GE int N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 N003 ( 3, 4) [000733] ----------- \--* ADD int N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void N003 ( 3, 3) [000738] J------N--- \--* LE int N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void N003 ( 3, 3) [000721] J------N--- \--* GT int N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 N003 ( 3, 4) [000652] ----------- \--* ADD long N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V36 loc32 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void N003 ( 3, 4) [000667] J------N--- \--* EQ int N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 5, 6) [001920] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 N006 ( 5, 6) [002864] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002860] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002859] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [002863] -----O----- \--* ADD byref N003 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002867] ---XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int N007 ( 4, 3) [001938] ---XG--N--- +--* IND int N006 ( 3, 4) [002869] -------N--- | \--* ADD byref N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void N003 ( 3, 4) [000679] J------N--- \--* EQ int N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void N003 ( 3, 4) [000683] J------N--- \--* LE int N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void N003 ( 3, 4) [000687] J------N--- \--* LT int N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 N008 ( 4, 6) [000700] ----------- | | \--* LSH long N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 5, 6) [001975] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 N006 ( 5, 6) [002886] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002882] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002881] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [002885] -----O----- \--* ADD byref N003 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002889] ---XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int N007 ( 4, 3) [001996] ---XG--N--- +--* IND int N006 ( 3, 4) [002904] -------N--- | \--* ADD byref N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 N003 ( 3, 4) [000716] ----------- \--* ADD int N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 N003 ( 3, 4) [000671] ----------- \--* ADD int N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void N007 ( 10, 9) [000611] J------N--- \--* NE int N005 ( 8, 6) [000609] ----------- +--* OR int N003 ( 6, 4) [000607] ----------- | +--* NE int N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void N003 ( 3, 4) [000615] J------N--- \--* LT int N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void N003 ( 3, 3) [000627] J------N--- \--* GE int N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 5, 6) [002035] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 N006 ( 5, 6) [002920] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002916] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002915] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [002919] -----O----- \--* ADD byref N003 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002923] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int N007 ( 4, 3) [002056] ---XG--N--- +--* IND int N006 ( 3, 4) [002938] -------N--- | \--* ADD byref N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 5, 6) [002095] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 N006 ( 5, 6) [002953] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002949] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002948] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [002952] -----O----- \--* ADD byref N003 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002956] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int N007 ( 4, 3) [002116] ---XG--N--- +--* IND int N006 ( 3, 4) [002971] -------N--- | \--* ADD byref N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 5, 6) [002155] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 N006 ( 5, 6) [002987] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002983] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002982] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [002986] -----O----- \--* ADD byref N003 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002990] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int N007 ( 4, 3) [002176] ---XG--N--- +--* IND int N006 ( 3, 4) [003005] -------N--- | \--* ADD byref N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [000808] ----------- \--* ADD int N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000817] ----------- \--* LSH long N003 ( 2, 3) [000814] ----------- +--* CAST long <- int N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [002204] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 N006 ( 5, 6) [003019] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003015] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003014] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [003018] -----O----- \--* ADD byref N003 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003022] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int N007 ( 4, 3) [002222] ---XG--N--- +--* IND int N006 ( 3, 4) [003024] -------N--- | \--* ADD byref N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 7, 8) [000757] ----------- * JTRUE void N003 ( 5, 6) [000756] J------N--- \--* GE int N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N010 ( 13, 15) [000791] ---XG------ * JTRUE void N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000786] ----------- | \--* LSH long N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N010 ( 13, 14) [000802] ---XG------ * JTRUE void N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000797] ----------- | \--* LSH long N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 7, 8) [000764] ----------- * JTRUE void N003 ( 5, 6) [000763] J------N--- \--* GE int N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N010 ( 13, 15) [000775] ---XG------ * JTRUE void N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000770] ----------- | \--* LSH long N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [000778] ----------- \--* ADD int N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 7, 8) [000289] ----------- * JTRUE void N003 ( 5, 6) [000288] J------N--- \--* GE int N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N010 ( 13, 15) [000300] ---XG------ * JTRUE void N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000295] ----------- | \--* LSH long N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [000306] ----------- \--* ADD int N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000315] ----------- \--* LSH long N003 ( 2, 3) [000312] ----------- +--* CAST long <- int N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [002262] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 N006 ( 5, 6) [003038] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003034] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003033] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [003037] -----O----- \--* ADD byref N003 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003041] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int N007 ( 4, 3) [002280] ---XG--N--- +--* IND int N006 ( 3, 4) [003043] -------N--- | \--* ADD byref N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void N003 ( 3, 4) [000331] J------N--- \--* EQ int N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 7, 8) [000425] ----------- * JTRUE void N003 ( 5, 6) [000424] J------N--- \--* GE int N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N010 ( 13, 15) [000575] ---XG------ * JTRUE void N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000570] ----------- | \--* LSH long N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 9, 11) [000434] ----------- * JTRUE void N005 ( 7, 9) [000433] J------N--- \--* GE int N003 ( 3, 4) [000428] ----------- +--* ADD int N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N010 ( 13, 15) [000548] ---XG------ * JTRUE void N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000543] ----------- | \--* LSH long N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 N007 ( 6, 9) [000556] ----------- | \--* LSH long N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int N004 ( 3, 4) [000552] ----------- | | \--* ADD int N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) N006 ( 9, 11) [000443] ----------- * JTRUE void N005 ( 7, 9) [000442] J------N--- \--* GE int N003 ( 3, 4) [000437] ----------- +--* ADD int N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N010 ( 13, 15) [000457] ---XG------ * JTRUE void N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000452] ----------- | \--* LSH long N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 N007 ( 6, 9) [000465] ----------- | \--* LSH long N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int N004 ( 3, 4) [000461] ----------- | | \--* ADD int N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 5, 6) [002319] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 N006 ( 5, 6) [003059] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003055] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003054] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [003058] -----O----- \--* ADD byref N003 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003062] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int N007 ( 4, 3) [002337] ---XG--N--- +--* IND int N006 ( 3, 4) [003064] -------N--- | \--* ADD byref N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 N003 ( 3, 4) [000535] ----------- \--* ADD int N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 N003 ( 3, 4) [000473] ----------- \--* ADD int N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 7, 8) [000485] ----------- * JTRUE void N003 ( 5, 6) [000484] J------N--- \--* GE int N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V54 tmp14 N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000527] ----------- | \--* LSH long N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void N003 ( 3, 4) [000488] J------N--- \--* LE int N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 5, 6) [002366] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 N006 ( 5, 6) [003082] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003078] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003077] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [003081] -----O----- \--* ADD byref N003 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003085] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int N007 ( 4, 3) [002384] ---XG--N--- +--* IND int N006 ( 3, 4) [003087] -------N--- | \--* ADD byref N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 7, 8) [000342] ----------- * JTRUE void N003 ( 5, 6) [000341] J------N--- \--* GE int N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N010 ( 13, 15) [000353] ---XG------ * JTRUE void N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000348] ----------- | \--* LSH long N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N010 ( 13, 15) [000418] ---XG------ * JTRUE void N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000413] ----------- | \--* LSH long N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [000359] ----------- \--* ADD int N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000368] ----------- \--* LSH long N003 ( 2, 3) [000365] ----------- +--* CAST long <- int N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [002414] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 N006 ( 5, 6) [003101] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003097] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003096] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [003100] -----O----- \--* ADD byref N003 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003104] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int N007 ( 4, 3) [002432] ---XG--N--- +--* IND int N006 ( 3, 4) [003106] -------N--- | \--* ADD byref N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [000395] ----------- \--* ADD int N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000404] ----------- \--* LSH long N003 ( 2, 3) [000401] ----------- +--* CAST long <- int N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [002460] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 N006 ( 5, 6) [003120] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003116] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003115] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [003119] -----O----- \--* ADD byref N003 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003123] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int N007 ( 4, 3) [002478] ---XG--N--- +--* IND int N006 ( 3, 4) [003125] -------N--- | \--* ADD byref N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 7, 8) [000378] ----------- * JTRUE void N003 ( 5, 6) [000377] J------N--- \--* GE int N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N010 ( 13, 15) [000389] ---XG------ * JTRUE void N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000384] ----------- | \--* LSH long N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 5, 6) [002509] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 N006 ( 5, 6) [003139] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003135] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003134] ----------- | \--* LCL_VAR byref V00 arg0 N005 ( 3, 4) [003138] -----O----- \--* ADD byref N003 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 N004 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003142] ---XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int N007 ( 4, 3) [002527] ---XG--N--- +--* IND int N006 ( 3, 4) [003144] -------N--- | \--* ADD byref N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 7, 8) [000210] ----------- * JTRUE void N003 ( 5, 6) [000209] J------N--- \--* GE int N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 [+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 N003 ( 3, 4) [000246] ----------- \--* ADD int N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V16 loc12 N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 N005 ( 4, 6) [000255] ----------- \--* LSH long N003 ( 2, 3) [000252] ----------- +--* CAST long <- int N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V50 tmp10 N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void N003 ( 3, 4) [000223] J------N--- \--* NE int N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 254. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB06 BB05 BB02 BB02 : BB04 BB03 BB06 : BB07 BB07 : BB47 BB08 : BB38 BB13 BB09 BB09 : BB31 BB30 BB17 BB10 BB10 : BB23 BB21 BB18 BB11 BB11 : BB12 BB13 : BB35 BB14 BB14 : BB15 BB15 : BB16 BB18 : BB20 BB19 BB21 : BB22 BB23 : BB24 BB24 : BB25 BB25 : BB29 BB26 BB26 : BB28 BB27 BB31 : BB32 BB32 : BB33 BB33 : BB34 BB35 : BB36 BB36 : BB37 BB38 : BB44 BB40 BB39 BB40 : BB41 BB41 : BB43 BB42 BB44 : BB46 BB45 BB47 : BB50 BB48 BB48 : BB49 BB49 : BB08 BB50 : BB52 BB51 BB52 : BB56 BB53 BB53 : BB55 BB54 BB56 : BB66 BB63 BB57 BB57 : BB60 BB59 BB58 BB60 : BB61 BB61 : BB62 BB63 : BB65 BB64 BB66 : BB69 BB68 BB67 BB69 : BB72 BB71 BB70 BB72 : BB78 BB74 BB73 BB74 : BB77 BB76 BB75 BB78 : BB103 BB79 BB79 : BB80 BB80 : BB82 BB81 BB82 : BB85 BB84 BB83 BB85 : BB88 BB87 BB86 BB88 : BB89 BB89 : BB90 BB90 : BB100 BB91 BB91 : BB94 BB93 BB92 BB94 : BB110 BB95 BB95 : BB96 BB96 : BB99 BB98 BB97 BB100 : BB102 BB101 BB103 : BB112 BB104 BB104 : BB105 BB105 : BB106 BB106 : BB107 BB107 : BB111 BB108 BB108 : BB109 BB112 : BB245 BB113 : BB136 BB114 BB114 : BB135 BB115 BB115 : BB116 BB116 : BB117 BB118 : BB121 BB120 BB119 BB121 : BB124 BB123 BB122 BB124 : BB134 BB125 BB125 : BB126 BB126 : BB127 BB127 : BB128 BB128 : BB133 BB129 BB129 : BB132 BB130 BB130 : BB131 BB135 : BB118 BB136 : BB244 BB242 BB205 BB141 BB137 BB137 : BB194 BB186 BB145 BB138 BB138 : BB171 BB139 BB139 : BB140 BB141 : BB200 BB142 BB142 : BB143 BB143 : BB144 BB144 : BB181 BB145 : BB156 BB150 BB146 BB146 : BB149 BB148 BB147 BB150 : BB155 BB154 BB151 BB151 : BB153 BB152 BB156 : BB170 BB157 BB157 : BB160 BB159 BB158 BB160 : BB161 BB161 : BB162 BB162 : BB163 BB163 : BB164 BB164 : BB169 BB165 BB165 : BB168 BB166 BB166 : BB167 BB171 : BB172 BB172 : BB175 BB173 BB173 : BB174 BB175 : BB180 BB176 BB176 : BB179 BB177 BB177 : BB178 BB181 : BB182 BB182 : BB185 BB183 BB183 : BB184 BB186 : BB187 BB187 : BB190 BB188 BB188 : BB189 BB191 : BB193 BB192 BB194 : BB197 BB195 BB195 : BB196 BB196 : BB191 BB197 : BB198 BB198 : BB199 BB200 : BB201 BB201 : BB202 BB202 : BB204 BB203 BB205 : BB227 BB206 BB206 : BB219 BB218 BB208 BB207 BB208 : BB212 BB209 BB209 : BB210 BB210 : BB211 BB212 : BB215 BB213 BB213 : BB214 BB215 : BB217 BB216 BB219 : BB221 BB220 BB221 : BB223 BB222 BB223 : BB226 BB225 BB224 BB227 : BB230 BB229 BB228 BB230 : BB231 BB231 : BB239 BB233 BB232 BB233 : BB235 BB234 BB236 : BB238 BB237 BB239 : BB240 BB240 : BB241 BB236 BB242 : BB243 BB245 : BB248 BB246 BB246 : BB247 BB247 : BB113 BB248 : BB253 BB249 BB249 : BB250 BB250 : BB251 BB251 : BB252 *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Local V02 should not be enregistered because: struct size does not match reg size Tracked variable (131 out of 171) table: V16 loc12 [ int]: refCnt = 68, refCntWtd = 967 V73 tmp33 [ int]: refCnt = 3, refCntWtd = 384 V02 arg2 [struct]: refCnt = 26, refCntWtd = 314 V00 arg0 [ byref]: refCnt = 89, refCntWtd = 278 V22 loc18 [ long]: refCnt = 10, refCntWtd = 256 V74 tmp34 [ int]: refCnt = 2, refCntWtd = 256 V18 loc14 [ushort]: refCnt = 34, refCntWtd = 218 V34 loc30 [ long]: refCnt = 19, refCntWtd = 107 V04 loc0 [ int]: refCnt = 15, refCntWtd = 96 V95 tmp55 [ ref]: refCnt = 6, refCntWtd = 96 V54 tmp14 [ int]: refCnt = 3, refCntWtd = 96 V72 tmp32 [ int]: refCnt = 3, refCntWtd = 96 V20 loc16 [ int]: refCnt = 16, refCntWtd = 71 V62 tmp22 [ byref]: refCnt = 8, refCntWtd = 64 V71 tmp31 [ int]: refCnt = 2, refCntWtd = 64 V05 loc1 [ int]: refCnt = 18, refCntWtd = 55 V13 loc9 [ int]: refCnt = 8, refCntWtd = 48 V93 tmp53 [ byref]: refCnt = 3, refCntWtd = 48 V97 tmp57 [ byref]: refCnt = 3, refCntWtd = 48 V120 tmp80 [ byref]: refCnt = 3, refCntWtd = 48 V138 tmp98 [ byref]: refCnt = 3, refCntWtd = 48 V92 tmp52 [ushort]: refCnt = 3, refCntWtd = 48 V119 tmp79 [ushort]: refCnt = 3, refCntWtd = 48 V137 tmp97 [ushort]: refCnt = 3, refCntWtd = 48 V08 loc4 [ int]: refCnt = 14, refCntWtd = 47.50 V36 loc32 [ long]: refCnt = 10, refCntWtd = 43 V14 loc10 [ int]: refCnt = 11, refCntWtd = 42 V10 loc6 [ int]: refCnt = 6, refCntWtd = 42 V91 tmp51 [ int]: refCnt = 5, refCntWtd = 40 V96 tmp56 [ int]: refCnt = 5, refCntWtd = 40 V118 tmp78 [ int]: refCnt = 5, refCntWtd = 40 V136 tmp96 [ int]: refCnt = 5, refCntWtd = 40 V53 tmp13 [ int]: refCnt = 2, refCntWtd = 32 V59 tmp19 [ int]: refCnt = 2, refCntWtd = 32 V61 tmp21 [ long]: refCnt = 2, refCntWtd = 32 V168 tmp128 [ long]: refCnt = 2, refCntWtd = 32 V01 arg1 [ byref]: refCnt = 21, refCntWtd = 27.50 V06 loc2 [ int]: refCnt = 9, refCntWtd = 29.50 V12 loc8 [ bool]: refCnt = 6, refCntWtd = 29 V144 tmp104 [ int]: refCnt = 9, refCntWtd = 27 V11 loc7 [ int]: refCnt = 5, refCntWtd = 27 V09 loc5 [ bool]: refCnt = 6, refCntWtd = 25 V03 arg3 [ ref]: refCnt = 12, refCntWtd = 22 V102 tmp62 [ ref]: refCnt = 6, refCntWtd = 24 V106 tmp66 [ ref]: refCnt = 6, refCntWtd = 24 V110 tmp70 [ ref]: refCnt = 6, refCntWtd = 24 V114 tmp74 [ ref]: refCnt = 6, refCntWtd = 24 V38 loc34 [ int]: refCnt = 6, refCntWtd = 24 V60 tmp20 [ byref]: refCnt = 3, refCntWtd = 24 V69 tmp29 [ byref]: refCnt = 3, refCntWtd = 24 V157 tmp117 [ byref]: refCnt = 3, refCntWtd = 24 V50 tmp10 [ int]: refCnt = 3, refCntWtd = 24 V63 tmp23 [ int]: refCnt = 3, refCntWtd = 24 V07 loc3 [ int]: refCnt = 7, refCntWtd = 22.50 V143 tmp103 [ byref]: refCnt = 7, refCntWtd = 21 V15 loc11 [ int]: refCnt = 7, refCntWtd = 19 V33 loc29 [ ref]: refCnt = 9, refCntWtd = 18 V28 loc24 [ int]: refCnt = 8, refCntWtd = 18 V17 loc13 [ long]: refCnt = 5, refCntWtd = 16 V49 tmp9 [ int]: refCnt = 2, refCntWtd = 16 V27 loc23 [ int]: refCnt = 8, refCntWtd = 13.50 V100 tmp60 [ byref]: refCnt = 3, refCntWtd = 12 V104 tmp64 [ byref]: refCnt = 3, refCntWtd = 12 V108 tmp68 [ byref]: refCnt = 3, refCntWtd = 12 V112 tmp72 [ byref]: refCnt = 3, refCntWtd = 12 V116 tmp76 [ byref]: refCnt = 3, refCntWtd = 12 V124 tmp84 [ byref]: refCnt = 3, refCntWtd = 12 V127 tmp87 [ byref]: refCnt = 3, refCntWtd = 12 V130 tmp90 [ byref]: refCnt = 3, refCntWtd = 12 V134 tmp94 [ byref]: refCnt = 3, refCntWtd = 12 V141 tmp101 [ byref]: refCnt = 3, refCntWtd = 12 V123 tmp83 [ushort]: refCnt = 3, refCntWtd = 12 V133 tmp93 [ushort]: refCnt = 3, refCntWtd = 12 V30 loc26 [ int]: refCnt = 4, refCntWtd = 10.50 V99 tmp59 [ int]: refCnt = 5, refCntWtd = 10 V103 tmp63 [ int]: refCnt = 5, refCntWtd = 10 V107 tmp67 [ int]: refCnt = 5, refCntWtd = 10 V111 tmp71 [ int]: refCnt = 5, refCntWtd = 10 V115 tmp75 [ int]: refCnt = 5, refCntWtd = 10 V122 tmp82 [ int]: refCnt = 5, refCntWtd = 10 V126 tmp86 [ int]: refCnt = 5, refCntWtd = 10 V129 tmp89 [ int]: refCnt = 5, refCntWtd = 10 V132 tmp92 [ int]: refCnt = 5, refCntWtd = 10 V140 tmp100 [ int]: refCnt = 5, refCntWtd = 10 V160 tmp120 [ int]: refCnt = 5, refCntWtd = 10 V159 tmp119 [ byref]: refCnt = 4, refCntWtd = 8 V163 tmp123 [ byref]: refCnt = 4, refCntWtd = 8 V57 tmp17 [ int]: refCnt = 4, refCntWtd = 8 V164 tmp124 [ int]: refCnt = 4, refCntWtd = 8 V70 tmp30 [ int]: refCnt = 3, refCntWtd = 8 V51 tmp11 [ int]: refCnt = 2, refCntWtd = 8 V52 tmp12 [ int]: refCnt = 2, refCntWtd = 8 V56 tmp16 [ long]: refCnt = 2, refCntWtd = 8 V83 tmp43 [ long]: refCnt = 2, refCntWtd = 8 V158 tmp118 [ int]: refCnt = 1, refCntWtd = 8 V26 loc22 [ ref]: refCnt = 6, refCntWtd = 6 V86 tmp46 [ ref]: refCnt = 6, refCntWtd = 6 V76 tmp36 [ byref]: refCnt = 3, refCntWtd = 6 V161 tmp121 [ byref]: refCnt = 3, refCntWtd = 6 V37 loc33 [ bool]: refCnt = 3, refCntWtd = 6 V55 tmp15 [ int]: refCnt = 3, refCntWtd = 6 V58 tmp18 [ int]: refCnt = 3, refCntWtd = 6 V167 tmp127 [ long]: refCnt = 3, refCntWtd = 6 V21 loc17 [ bool]: refCnt = 3, refCntWtd = 5 V29 loc25 [ int]: refCnt = 3, refCntWtd = 5 V32 loc28 [ int]: refCnt = 3, refCntWtd = 5 V169 tmp129 [ long]: refCnt = 2, refCntWtd = 4 V81 tmp41 [ byref]: refCnt = 1, refCntWtd = 4 V82 tmp42 [ byref]: refCnt = 1, refCntWtd = 4 V88 tmp48 [ byref]: refCnt = 3, refCntWtd = 3 V151 tmp111 [ byref]: refCnt = 3, refCntWtd = 3 V165 tmp125 [ byref]: refCnt = 3, refCntWtd = 3 V152 tmp112 [ int]: refCnt = 3, refCntWtd = 3 V87 tmp47 [ int]: refCnt = 5, refCntWtd = 2.50 V149 tmp109 [ byref]: refCnt = 4, refCntWtd = 2.50 V43 tmp3 [ int]: refCnt = 4, refCntWtd = 2.50 V150 tmp110 [ int]: refCnt = 4, refCntWtd = 2.50 V147 tmp107 [ byref]: refCnt = 3, refCntWtd = 2 V44 tmp4 [ int]: refCnt = 3, refCntWtd = 2 V45 tmp5 [ int]: refCnt = 3, refCntWtd = 2 V148 tmp108 [ int]: refCnt = 3, refCntWtd = 2 V162 tmp122 [ int]: refCnt = 1, refCntWtd = 2 V155 tmp115 [ byref]: refCnt = 3, refCntWtd = 1.50 V31 loc27 [ int]: refCnt = 3, refCntWtd = 1.50 V46 tmp6 [ int]: refCnt = 3, refCntWtd = 1.50 V64 tmp24 [ int]: refCnt = 3, refCntWtd = 1.50 V65 tmp25 [ int]: refCnt = 3, refCntWtd = 1.50 V66 tmp26 [ int]: refCnt = 3, refCntWtd = 1.50 V67 tmp27 [ int]: refCnt = 3, refCntWtd = 1.50 V156 tmp116 [ int]: refCnt = 3, refCntWtd = 1.50 V166 tmp126 [ int]: refCnt = 1, refCntWtd = 1 *************** In fgPerBlockLocalVarLiveness() BB01 USE(2)={V02 V01 } + ByrefExposed + GcHeap DEF(6)={ V11 V17 V76 V167 V147 V148} + ByrefExposed* + GcHeap* BB02 USE(3)={V01 V147 V148 } + ByrefExposed + GcHeap DEF(2)={ V155 V156} BB03 USE(2)={ V155 V156} DEF(3)={V149 V43 V150 } BB04 USE(2)={ V155 V156} DEF(3)={V149 V43 V150 } BB05 USE(2)={ V147 V148} DEF(3)={V149 V43 V150 } BB06 USE(3)={ V149 V43 V150} + ByrefExposed + GcHeap DEF(1)={V15 } + ByrefExposed* + GcHeap* BB07 USE(2)={ V02 V15 } DEF(13)={V16 V22 V04 V05 V13 V10 V168 V06 V12 V09 V157 V07 V158} BB08 USE(1)={V18} DEF(0)={ } BB09 USE(1)={V18} DEF(0)={ } BB10 USE(1)={V18} DEF(0)={ } BB11 USE(1)={V18} DEF(0)={ } BB12 USE(0)={} DEF(0)={} BB13 USE(1)={V18} DEF(0)={ } BB14 USE(1)={V18} DEF(0)={ } BB15 USE(1)={V18} DEF(0)={ } BB16 USE(1)={V13} DEF(1)={V13} BB17 USE(1)={V04} DEF(1)={V04} BB18 USE(1)={V06} DEF(0)={ } BB19 USE(1)={V04 } DEF(1)={ V06} BB20 USE(1)={V04 } DEF(2)={V04 V07} BB21 USE(1)={V05} DEF(0)={ } BB22 USE(1)={V04 } DEF(1)={ V05} BB23 USE(1)={V04} DEF(0)={ } BB24 USE(1)={V05} DEF(0)={ } BB25 USE(1)={V10} DEF(0)={ } BB26 USE(2)={V04 V10} DEF(0)={ } BB27 USE(1)={V11} DEF(1)={V11} BB28 USE(0)={ } DEF(1)={V12} BB29 USE(1)={V04 } DEF(2)={ V10 V11} BB30 USE(1)={V13} DEF(1)={V13} BB31 USE(2)={V16 V02} DEF(0)={ } BB32 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB33 USE(3)={V16 V22 V18} + ByrefExposed + GcHeap DEF(2)={V16 V74 } BB34 USE(0)={} DEF(0)={} BB35 USE(2)={V16 V02} DEF(0)={ } BB36 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB37 USE(1)={V16} DEF(1)={V16} BB38 USE(2)={V16 V02} DEF(0)={ } BB39 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB40 USE(2)={V16 V02} DEF(0)={ } BB41 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB42 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB43 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB44 USE(2)={V16 V02} DEF(2)={V16 V73 } BB45 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB46 USE(0)={ } DEF(1)={V09} BB47 USE(2)={V16 V02} DEF(0)={ } BB48 USE(2)={V16 V22 } + ByrefExposed + GcHeap DEF(4)={V16 V18 V72 V71} BB49 USE(1)={V18} DEF(0)={ } BB50 USE(1)={V05} DEF(0)={ } BB51 USE(1)={V04 } DEF(1)={ V05} BB52 USE(1)={V10} DEF(0)={ } BB53 USE(2)={V05 V10} DEF(0)={ } BB54 USE(2)={V13 V11} DEF(1)={V13 } BB55 USE(0)={ } DEF(1)={V12} BB56 USE(1)={V17} + ByrefExposed + GcHeap DEF(0)={ } BB57 USE(3)={V13 V01 V09 } + ByrefExposed + GcHeap DEF(1)={ V69} + ByrefExposed + GcHeap BB58 USE(3)={V04 V05 V01 } + ByrefExposed + GcHeap DEF(1)={ V70} BB59 USE(1)={V04 } DEF(1)={ V70} BB60 USE(3)={V01 V17 V70} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB61 USE(2)={ V02 V15} + ByrefExposed + GcHeap DEF(1)={V16 } + ByrefExposed* + GcHeap* BB62 USE(1)={V16 } DEF(1)={ V15} BB63 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } BB64 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed + GcHeap BB65 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed + GcHeap BB66 USE(2)={V05 V06} DEF(0)={ } BB67 USE(0)={ } DEF(1)={V44} BB68 USE(2)={V05 V06 } DEF(1)={ V44} BB69 USE(3)={V05 V07 V44} DEF(1)={ V06 } BB70 USE(0)={ } DEF(1)={V45} BB71 USE(2)={V05 V07 } DEF(1)={ V45} BB72 USE(2)={V09 V45} DEF(1)={ V07 } BB73 USE(1)={V05 } DEF(2)={ V08 V14} BB74 USE(2)={V05 V01} + ByrefExposed + GcHeap DEF(0)={ } BB75 USE(1)={V05 } DEF(1)={ V46} BB76 USE(1)={V01 } + ByrefExposed + GcHeap DEF(1)={ V46} BB77 USE(3)={V05 V01 V46} + ByrefExposed + GcHeap DEF(2)={ V08 V14 } BB78 USE(2)={ V12 V15 } + ByrefExposed DEF(6)={V16 V20 V144 V143 V151 V152} BB79 USE(1)={V03} + ByrefExposed + GcHeap DEF(0)={ } BB80 USE(1)={V03 } + ByrefExposed + GcHeap DEF(4)={ V28 V27 V26 V29} BB81 USE(2)={ V27 V26} + ByrefExposed + GcHeap DEF(1)={V28 } BB82 USE(3)={V08 V14 V28 } DEF(2)={ V30 V64} BB83 USE(1)={V64 } DEF(2)={ V65 V66} BB84 USE(2)={V14 V64 } DEF(2)={ V65 V66} BB85 USE(3)={V06 V65 V66} DEF(1)={ V31 } BB86 USE(1)={V31 } DEF(1)={ V67} BB87 USE(1)={V06 } DEF(1)={ V67} BB88 USE(2)={V28 V67} DEF(1)={ V32 } BB89 USE(1)={V30} DEF(0)={ } BB90 USE(2)={V20 V144} DEF(1)={V20 } BB91 USE(1)={V144 } DEF(3)={ V33 V160 V159} BB92 USE(0)={ } DEF(2)={V160 V159} BB93 USE(1)={V33 } DEF(2)={ V160 V159} BB94 USE(3)={V144 V160 V159 } DEF(2)={ V161 V162} BB95 USE(0)={} DEF(0)={} BB96 USE(4)={V144 V143 V33 V161 } + ByrefExposed + GcHeap DEF(5)={ V163 V164 V83 V81 V82} + ByrefExposed* + GcHeap* BB97 USE(0)={ } DEF(2)={V163 V164} BB98 USE(1)={V33 } DEF(2)={ V163 V164} BB99 USE(2)={ V163 V164} DEF(2)={V144 V143 } BB100 USE(6)={V20 V144 V143 V28 V27 V29} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed + GcHeap BB101 USE(2)={V27 V26} + ByrefExposed + GcHeap DEF(2)={V27 V30 } BB102 USE(3)={V28 V30 V32} DEF(1)={V28 } BB103 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } BB104 USE(1)={V15} DEF(0)={ } BB105 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } BB106 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V86} BB107 USE(2)={V00 V86 } + ByrefExposed + GcHeap DEF(1)={ V87} BB108 USE(2)={V00 V87} + ByrefExposed + GcHeap DEF(0)={ } BB109 USE(3)={V00 V86 V87} + ByrefExposed + GcHeap DEF(1)={ V88 } + ByrefExposed + GcHeap BB110 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB111 USE(2)={V00 V86} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB112 USE(2)={V02 V17 } DEF(6)={ V34 V36 V21 V169 V165 V166} BB113 USE(1)={V14} DEF(0)={ } BB114 USE(1)={V18} DEF(0)={ } BB115 USE(1)={V18} DEF(0)={ } BB116 USE(1)={V18} DEF(0)={ } BB117 USE(0)={} DEF(0)={} BB118 USE(2)={V00 V36 } + ByrefExposed + GcHeap DEF(1)={ V60} BB119 USE(1)={ V60 } DEF(2)={V62 V63} BB120 USE(2)={ V36 V60 } + ByrefExposed + GcHeap DEF(4)={V62 V36 V61 V63} BB121 USE(2)={V62 V63} + ByrefExposed + GcHeap DEF(2)={ V92 V91 } BB122 USE(3)={V62 V92 V91} + ByrefExposed + GcHeap DEF(1)={ V93 } + ByrefExposed + GcHeap BB123 USE(2)={V62 V92} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB124 USE(1)={V12} DEF(0)={ } BB125 USE(1)={V08} DEF(0)={ } BB126 USE(1)={V20} DEF(0)={ } BB127 USE(4)={V20 V08 V144 V143} + ByrefExposed + GcHeap DEF(0)={ } BB128 USE(1)={ V03} + ByrefExposed + GcHeap DEF(1)={V95 } BB129 USE(2)={V00 V95 } + ByrefExposed + GcHeap DEF(1)={ V96} BB130 USE(2)={V00 V96} + ByrefExposed + GcHeap DEF(0)={ } BB131 USE(3)={V00 V95 V96} + ByrefExposed + GcHeap DEF(1)={ V97 } + ByrefExposed + GcHeap BB132 USE(2)={V00 V95} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB133 USE(1)={V20} DEF(1)={V20} BB134 USE(2)={V08 V14} DEF(2)={V08 V14} BB135 USE(1)={V14} DEF(0)={ } BB136 USE(1)={V18} DEF(0)={ } BB137 USE(1)={V18} DEF(0)={ } BB138 USE(1)={V18} DEF(0)={ } BB139 USE(1)={V18} DEF(0)={ } BB140 USE(0)={} DEF(0)={} BB141 USE(1)={V18} DEF(0)={ } BB142 USE(1)={V18} DEF(0)={ } BB143 USE(1)={V18} DEF(0)={ } BB144 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V110} BB145 USE(1)={V14} DEF(0)={ } BB146 USE(3)={V08 V14 V06} DEF(1)={ V14 } BB147 USE(0)={ } DEF(1)={V58} BB148 USE(0)={ } DEF(1)={V58} BB149 USE(1)={ V58} DEF(1)={V18 } BB150 USE(1)={V36} + ByrefExposed + GcHeap DEF(0)={ } BB151 USE(2)={V08 V07} DEF(0)={ } BB152 USE(0)={ } DEF(1)={V57} BB153 USE(0)={ } DEF(1)={V57} BB154 USE(1)={V36 } + ByrefExposed + GcHeap DEF(3)={V36 V57 V56} BB155 USE(1)={ V57} DEF(1)={V18 } BB156 USE(1)={V18} DEF(0)={ } BB157 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V99} BB158 USE(3)={V00 V18 V99} + ByrefExposed + GcHeap DEF(1)={ V100 } + ByrefExposed + GcHeap BB159 USE(2)={V00 V18} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB160 USE(1)={V12} DEF(0)={ } BB161 USE(1)={V08} DEF(0)={ } BB162 USE(1)={V20} DEF(0)={ } BB163 USE(4)={V20 V08 V144 V143} + ByrefExposed + GcHeap DEF(0)={ } BB164 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V102} BB165 USE(2)={V00 V102 } + ByrefExposed + GcHeap DEF(1)={ V103} BB166 USE(2)={V00 V103} + ByrefExposed + GcHeap DEF(0)={ } BB167 USE(3)={V00 V102 V103} + ByrefExposed + GcHeap DEF(1)={ V104 } + ByrefExposed + GcHeap BB168 USE(2)={V00 V102} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB169 USE(1)={V20} DEF(1)={V20} BB170 USE(1)={V08} DEF(1)={V08} BB171 USE(2)={V08 V21} DEF(0)={ } BB172 USE(1)={V07} DEF(0)={ } BB173 USE(2)={V04 V05} DEF(0)={ } BB174 USE(1)={V36} + ByrefExposed + GcHeap DEF(0)={ } BB175 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V106} BB176 USE(2)={V00 V106 } + ByrefExposed + GcHeap DEF(1)={ V107} BB177 USE(2)={V00 V107} + ByrefExposed + GcHeap DEF(0)={ } BB178 USE(3)={V00 V106 V107} + ByrefExposed + GcHeap DEF(1)={ V108 } + ByrefExposed + GcHeap BB179 USE(2)={V00 V106} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB180 USE(0)={ } DEF(1)={V21} BB181 USE(1)={V110} DEF(0)={ } BB182 USE(2)={V00 V110 } + ByrefExposed + GcHeap DEF(1)={ V111} BB183 USE(2)={V00 V111} + ByrefExposed + GcHeap DEF(0)={ } BB184 USE(3)={V00 V110 V111} + ByrefExposed + GcHeap DEF(1)={ V112 } + ByrefExposed + GcHeap BB185 USE(2)={V00 V110} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB186 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V114} BB187 USE(2)={V00 V114 } + ByrefExposed + GcHeap DEF(1)={ V115} BB188 USE(2)={V00 V115} + ByrefExposed + GcHeap DEF(0)={ } BB189 USE(3)={V00 V114 V115} + ByrefExposed + GcHeap DEF(1)={ V116 } + ByrefExposed + GcHeap BB190 USE(2)={V00 V114} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB191 USE(3)={V16 V00 V34 } + ByrefExposed + GcHeap DEF(4)={V16 V119 V118 V59} BB192 USE(3)={V00 V119 V118} + ByrefExposed + GcHeap DEF(1)={ V120 } + ByrefExposed + GcHeap BB193 USE(2)={V00 V119} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB194 USE(2)={V16 V02} DEF(0)={ } BB195 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB196 USE(3)={V16 V18 V34} + ByrefExposed + GcHeap DEF(0)={ } BB197 USE(2)={V16 V02} DEF(0)={ } BB198 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB199 USE(1)={V16} DEF(1)={V16} BB200 USE(2)={V16 V02} DEF(0)={ } BB201 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB202 USE(3)={V16 V00 V34 } + ByrefExposed + GcHeap DEF(4)={V16 V123 V122 V51} BB203 USE(3)={V00 V123 V122} + ByrefExposed + GcHeap DEF(1)={ V124 } + ByrefExposed + GcHeap BB204 USE(2)={V00 V123} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB205 USE(1)={V09 } DEF(2)={ V38 V37} BB206 USE(2)={V16 V02} DEF(0)={ } BB207 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB208 USE(2)={V16 V02} DEF(0)={ } BB209 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB210 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB211 USE(0)={ } DEF(1)={V37} BB212 USE(2)={V16 V02} DEF(0)={ } BB213 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB214 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB215 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V126} BB216 USE(3)={V00 V18 V126} + ByrefExposed + GcHeap DEF(1)={ V127 } + ByrefExposed + GcHeap BB217 USE(0)={} DEF(0)={} BB218 USE(1)={V38} DEF(1)={V38} BB219 USE(2)={V16 V02 } DEF(2)={V16 V54} BB220 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB221 USE(1)={V38} DEF(0)={ } BB222 USE(0)={ } DEF(1)={V38} BB223 USE(1)={V17} + ByrefExposed + GcHeap DEF(0)={ } BB224 USE(2)={V05 V01 } + ByrefExposed + GcHeap DEF(1)={ V55} BB225 USE(0)={ } DEF(1)={V55} BB226 USE(6)={V00 V18 V03 V38 V37 V55} + ByrefExposed + GcHeap DEF(1)={ V09 } + ByrefExposed* + GcHeap* BB227 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V129} BB228 USE(3)={V00 V18 V129} + ByrefExposed + GcHeap DEF(1)={ V130 } + ByrefExposed + GcHeap BB229 USE(2)={V00 V18} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB230 USE(2)={V16 V02} DEF(0)={ } BB231 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB232 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB233 USE(3)={V16 V00 V34 } + ByrefExposed + GcHeap DEF(4)={V16 V133 V132 V52} BB234 USE(3)={V00 V133 V132} + ByrefExposed + GcHeap DEF(1)={ V134 } + ByrefExposed + GcHeap BB235 USE(2)={V00 V133} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB236 USE(3)={V16 V00 V34 } + ByrefExposed + GcHeap DEF(4)={V16 V137 V136 V53} BB237 USE(3)={V00 V137 V136} + ByrefExposed + GcHeap DEF(1)={ V138 } + ByrefExposed + GcHeap BB238 USE(2)={V00 V137} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB239 USE(2)={V16 V02} DEF(0)={ } BB240 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB241 USE(0)={} DEF(0)={} BB242 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V140} BB243 USE(3)={V00 V18 V140} + ByrefExposed + GcHeap DEF(1)={ V141 } + ByrefExposed + GcHeap BB244 USE(2)={V00 V18} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB245 USE(2)={V16 V02} DEF(0)={ } BB246 USE(2)={V16 V34 } + ByrefExposed + GcHeap DEF(4)={V16 V18 V50 V49} BB247 USE(1)={V18} DEF(0)={ } BB248 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } BB249 USE(1)={V15} DEF(0)={ } BB250 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } BB251 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } BB252 USE(2)={V00 V03} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB253 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (4)={V02 V00 V01 V03 } + ByrefExposed + GcHeap OUT(8)={V02 V00 V01 V11 V03 V17 V147 V148} + ByrefExposed + GcHeap BB02 IN (8)={V02 V00 V01 V11 V03 V17 V147 V148 } + ByrefExposed + GcHeap OUT(8)={V02 V00 V01 V11 V03 V17 V155 V156} + ByrefExposed + GcHeap BB03 IN (8)={V02 V00 V01 V11 V03 V17 V155 V156} + ByrefExposed + GcHeap OUT(9)={V02 V00 V01 V11 V03 V17 V149 V43 V150 } + ByrefExposed + GcHeap BB04 IN (8)={V02 V00 V01 V11 V03 V17 V155 V156} + ByrefExposed + GcHeap OUT(9)={V02 V00 V01 V11 V03 V17 V149 V43 V150 } + ByrefExposed + GcHeap BB05 IN (8)={V02 V00 V01 V11 V03 V17 V147 V148} + ByrefExposed + GcHeap OUT(9)={V02 V00 V01 V11 V03 V17 V149 V43 V150 } + ByrefExposed + GcHeap BB06 IN (9)={V02 V00 V01 V11 V03 V17 V149 V43 V150} + ByrefExposed + GcHeap OUT(7)={V02 V00 V01 V11 V03 V15 V17 } + ByrefExposed + GcHeap BB07 IN (7)={ V02 V00 V01 V11 V03 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB08 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB09 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB10 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB11 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB12 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB13 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB14 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB15 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB16 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB17 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB18 IN (16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V15 V17} + ByrefExposed + GcHeap OUT(16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V15 V17} + ByrefExposed + GcHeap BB19 IN (15)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V12 V11 V09 V03 V15 V17} + ByrefExposed + GcHeap OUT(16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V15 V17} + ByrefExposed + GcHeap BB20 IN (16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB21 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB22 IN (16)={V16 V02 V00 V22 V04 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB23 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB24 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB25 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB26 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB27 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB28 IN (14)={V16 V02 V00 V22 V04 V05 V13 V01 V06 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(15)={V16 V02 V00 V22 V04 V05 V13 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB29 IN (15)={V16 V02 V00 V22 V04 V05 V13 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB30 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB31 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB32 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB33 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB34 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB35 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB36 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB37 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB38 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB39 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB40 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB41 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB42 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB43 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB44 IN (16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V03 V07 V15 V17} + ByrefExposed + GcHeap BB45 IN (16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V03 V07 V15 V17} + ByrefExposed + GcHeap BB46 IN (16)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB47 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB48 IN (17)={V16 V02 V00 V22 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB49 IN (18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V22 V18 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB50 IN (15)={V02 V00 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(15)={V02 V00 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB51 IN (14)={V02 V00 V04 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(15)={V02 V00 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB52 IN (15)={V02 V00 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(15)={V02 V00 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB53 IN (15)={V02 V00 V04 V05 V13 V10 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(14)={V02 V00 V04 V05 V13 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB54 IN (14)={V02 V00 V04 V05 V13 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(14)={V02 V00 V04 V05 V13 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB55 IN (13)={V02 V00 V04 V05 V13 V01 V06 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(14)={V02 V00 V04 V05 V13 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB56 IN (14)={V02 V00 V04 V05 V13 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(14)={V02 V00 V04 V05 V13 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB57 IN (14)={V02 V00 V04 V05 V13 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(13)={V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB58 IN (13)={V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap OUT(14)={V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17 V70} + ByrefExposed + GcHeap BB59 IN (13)={V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap OUT(14)={V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17 V70} + ByrefExposed + GcHeap BB60 IN (14)={V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17 V70} + ByrefExposed + GcHeap OUT(13)={V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap BB61 IN (13)={ V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(14)={V16 V02 V00 V04 V05 V01 V06 V12 V11 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB62 IN (7)={V16 V02 V00 V01 V11 V03 V17} + ByrefExposed + GcHeap OUT(7)={ V02 V00 V01 V11 V03 V15 V17} + ByrefExposed + GcHeap BB63 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB64 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB65 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB66 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB67 IN (11)={V02 V00 V04 V05 V01 V12 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V12 V09 V03 V07 V15 V17 V44} + ByrefExposed + GcHeap BB68 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V12 V09 V03 V07 V15 V17 V44} + ByrefExposed + GcHeap BB69 IN (12)={V02 V00 V04 V05 V01 V12 V09 V03 V07 V15 V17 V44} + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap BB70 IN (11)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V15 V17 } + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V15 V17 V45} + ByrefExposed + GcHeap BB71 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V15 V17 V45} + ByrefExposed + GcHeap BB72 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V15 V17 V45} + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap BB73 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(14)={V02 V00 V04 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB74 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap BB75 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap OUT(13)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 V46} + ByrefExposed + GcHeap BB76 IN (12)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap OUT(13)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 V46} + ByrefExposed + GcHeap BB77 IN (13)={V02 V00 V04 V05 V01 V06 V12 V09 V03 V07 V15 V17 V46} + ByrefExposed + GcHeap OUT(14)={V02 V00 V04 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V17 } + ByrefExposed + GcHeap BB78 IN (14)={ V02 V00 V04 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap BB79 IN (18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap BB80 IN (18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 } + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V26 V29} + ByrefExposed + GcHeap BB81 IN (21)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V27 V26 V29} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V26 V29} + ByrefExposed + GcHeap BB82 IN (22)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V26 V29 } + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V64} + ByrefExposed + GcHeap BB83 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V64 } + ByrefExposed + GcHeap OUT(25)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V65 V66} + ByrefExposed + GcHeap BB84 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V64 } + ByrefExposed + GcHeap OUT(25)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V65 V66} + ByrefExposed + GcHeap BB85 IN (25)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V65 V66} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V31 } + ByrefExposed + GcHeap BB86 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V31 } + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V67} + ByrefExposed + GcHeap BB87 IN (23)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 } + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V67} + ByrefExposed + GcHeap BB88 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V67} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32 } + ByrefExposed + GcHeap BB89 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB90 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB91 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(25)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB92 IN (25)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(27)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V160 V159 V26 V29 V32} + ByrefExposed + GcHeap BB93 IN (25)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(27)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V160 V159 V26 V29 V32} + ByrefExposed + GcHeap BB94 IN (27)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V160 V159 V26 V29 V32} + ByrefExposed + GcHeap OUT(26)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V26 V161 V29 V32} + ByrefExposed + GcHeap BB95 IN (26)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V26 V161 V29 V32} + ByrefExposed + GcHeap OUT(26)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V26 V161 V29 V32} + ByrefExposed + GcHeap BB96 IN (26)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V33 V28 V17 V27 V30 V26 V161 V29 V32} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V33 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB97 IN (22)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V28 V17 V27 V30 V163 V164 V26 V29 V32} + ByrefExposed + GcHeap BB98 IN (23)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V33 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V28 V17 V27 V30 V163 V164 V26 V29 V32} + ByrefExposed + GcHeap BB99 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V09 V03 V07 V15 V28 V17 V27 V30 V163 V164 V26 V29 V32} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB100 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB101 IN (23)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V26 V29 V32} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB102 IN (24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V28 V17 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB103 IN (18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap BB104 IN (18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap BB105 IN (18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap BB106 IN (18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 } + ByrefExposed + GcHeap OUT(19)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V86} + ByrefExposed + GcHeap BB107 IN (19)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V86 } + ByrefExposed + GcHeap OUT(20)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V86 V87} + ByrefExposed + GcHeap BB108 IN (20)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V86 V87} + ByrefExposed + GcHeap OUT(20)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V86 V87} + ByrefExposed + GcHeap BB109 IN (20)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V86 V87} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 } + ByrefExposed + GcHeap BB110 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB111 IN (19)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V86} + ByrefExposed + GcHeap OUT(18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 } + ByrefExposed + GcHeap BB112 IN (18)={V16 V02 V00 V04 V20 V05 V08 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 } + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB113 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB114 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB115 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB116 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB117 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB118 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V60 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB119 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V60 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V62 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V63 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB120 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V60 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V62 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V63 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB121 IN (24)={V16 V02 V00 V18 V34 V04 V20 V62 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V63 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(25)={V16 V02 V00 V18 V34 V04 V20 V62 V05 V92 V08 V36 V14 V91 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB122 IN (25)={V16 V02 V00 V18 V34 V04 V20 V62 V05 V92 V08 V36 V14 V91 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB123 IN (24)={V16 V02 V00 V18 V34 V04 V20 V62 V05 V92 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB124 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB125 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB126 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB127 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB128 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V95 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB129 IN (23)={V16 V02 V00 V18 V34 V04 V95 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V95 V20 V05 V08 V36 V14 V96 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB130 IN (24)={V16 V02 V00 V18 V34 V04 V95 V20 V05 V08 V36 V14 V96 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V95 V20 V05 V08 V36 V14 V96 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB131 IN (24)={V16 V02 V00 V18 V34 V04 V95 V20 V05 V08 V36 V14 V96 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB132 IN (23)={V16 V02 V00 V18 V34 V04 V95 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB133 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB134 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB135 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB136 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB137 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB138 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB139 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB140 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB141 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB142 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB143 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB144 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB145 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB146 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB147 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V58 V21} + ByrefExposed + GcHeap BB148 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V58 V21} + ByrefExposed + GcHeap BB149 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V58 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB150 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB151 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB152 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V57 V21} + ByrefExposed + GcHeap BB153 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V57 V21} + ByrefExposed + GcHeap BB154 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V57 V21} + ByrefExposed + GcHeap BB155 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V57 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB156 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB157 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V99 V21} + ByrefExposed + GcHeap BB158 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V99 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB159 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB160 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB161 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB162 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB163 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB164 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V102 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB165 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V102 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V102 V07 V143 V15 V17 V103 V21} + ByrefExposed + GcHeap BB166 IN (23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V102 V07 V143 V15 V17 V103 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V102 V07 V143 V15 V17 V103 V21} + ByrefExposed + GcHeap BB167 IN (23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V102 V07 V143 V15 V17 V103 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB168 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V102 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB169 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB170 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB171 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB172 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB173 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB174 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB175 IN (20)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V106 V07 V143 V15 V17} + ByrefExposed + GcHeap BB176 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V106 V07 V143 V15 V17 } + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V106 V07 V143 V15 V17 V107} + ByrefExposed + GcHeap BB177 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V106 V07 V143 V15 V17 V107} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V106 V07 V143 V15 V17 V107} + ByrefExposed + GcHeap BB178 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V106 V07 V143 V15 V17 V107} + ByrefExposed + GcHeap OUT(20)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 } + ByrefExposed + GcHeap BB179 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V106 V07 V143 V15 V17} + ByrefExposed + GcHeap OUT(20)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17} + ByrefExposed + GcHeap BB180 IN (20)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 } + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB181 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB182 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V111 V21} + ByrefExposed + GcHeap BB183 IN (23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V111 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V111 V21} + ByrefExposed + GcHeap BB184 IN (23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V111 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB185 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V110 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB186 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V114 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB187 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V114 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V114 V07 V143 V15 V17 V115 V21} + ByrefExposed + GcHeap BB188 IN (23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V114 V07 V143 V15 V17 V115 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V114 V07 V143 V15 V17 V115 V21} + ByrefExposed + GcHeap BB189 IN (23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V114 V07 V143 V15 V17 V115 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB190 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V114 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB191 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V119 V08 V36 V14 V118 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB192 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V119 V08 V36 V14 V118 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB193 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V119 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB194 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB195 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB196 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB197 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB198 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB199 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB200 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB201 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB202 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V123 V122 V21} + ByrefExposed + GcHeap BB203 IN (23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V123 V122 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB204 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V123 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB205 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB206 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB207 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB208 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB209 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB210 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB211 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB212 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB213 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB214 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB215 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V126 V21} + ByrefExposed + GcHeap BB216 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V126 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB217 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB218 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB219 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB220 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB221 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB222 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB223 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB224 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V55 V21} + ByrefExposed + GcHeap BB225 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V55 V21} + ByrefExposed + GcHeap BB226 IN (24)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V03 V38 V07 V143 V15 V17 V37 V55 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB227 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V129 V21} + ByrefExposed + GcHeap BB228 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V129 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB229 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB230 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB231 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB232 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB233 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V133 V132 V21} + ByrefExposed + GcHeap BB234 IN (23)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V133 V132 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB235 IN (22)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V133 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB236 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V34 V04 V20 V05 V137 V08 V36 V14 V136 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB237 IN (23)={V16 V02 V00 V34 V04 V20 V05 V137 V08 V36 V14 V136 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB238 IN (22)={V16 V02 V00 V34 V04 V20 V05 V137 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB239 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB240 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB241 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB242 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V140 V21} + ByrefExposed + GcHeap BB243 IN (23)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V140 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB244 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB245 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB246 IN (21)={V16 V02 V00 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB247 IN (22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V02 V00 V18 V34 V04 V20 V05 V08 V36 V14 V01 V06 V12 V144 V09 V03 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB248 IN (4)={V00 V01 V03 V15} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V15} + ByrefExposed + GcHeap BB249 IN (4)={V00 V01 V03 V15} + ByrefExposed + GcHeap OUT(3)={V00 V01 V03 } + ByrefExposed + GcHeap BB250 IN (3)={V00 V01 V03} + ByrefExposed + GcHeap OUT(2)={V00 V03} + ByrefExposed + GcHeap BB251 IN (2)={V00 V03} + ByrefExposed + GcHeap OUT(2)={V00 V03} + ByrefExposed + GcHeap BB252 IN (2)={V00 V03} + ByrefExposed + GcHeap OUT(0)={ } BB253 IN (0)={} OUT(0)={} Removing tree [002605] in BB07 as useless N006 ( 3, 4) [002605] -A------R-- * ASG int N005 ( 1, 1) [002603] D------N--- +--* LCL_VAR int V158 tmp118 N004 ( 3, 4) [002604] ----------- \--* LCL_FLD int V02 arg2 [+8] fgComputeLife modified tree: N005 ( 3, 4) [002606] -A--------- * COMMA void N003 ( 3, 4) [002602] -A------R-- +--* ASG byref N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 [+0] N004 ( 0, 0) [002605] ----------- \--* NOP void Removing tree [002646] in BB78 as useless N006 ( 1, 3) [002646] -A------R-- * ASG int N005 ( 1, 1) [002644] D------N--- +--* LCL_VAR int V152 tmp112 N004 ( 1, 2) [002645] ----------- \--* CNS_INT int 0 Removing tree [002643] in BB78 as useless N003 ( 1, 3) [002643] -A------R-- * ASG byref N002 ( 1, 1) [002641] D------N--- +--* LCL_VAR byref V151 tmp111 N001 ( 1, 2) [002642] ----------- \--* CNS_INT byref 0 fgComputeLife modified tree: N003 ( 0, 0) [002647] ----------- * COMMA void N001 ( 0, 0) [002643] ----------- +--* NOP void N002 ( 0, 0) [002646] ----------- \--* NOP void Removing tree [002678] in BB91 as useless N006 ( 1, 3) [002678] -A------R-- * ASG int N005 ( 1, 1) [002676] D------N--- +--* LCL_VAR int V160 tmp120 N004 ( 1, 2) [002677] ----------- \--* CNS_INT int 0 Removing tree [002675] in BB91 as useless N003 ( 1, 3) [002675] -A------R-- * ASG byref N002 ( 1, 1) [002673] D------N--- +--* LCL_VAR byref V159 tmp119 N001 ( 1, 2) [002674] ----------- \--* CNS_INT byref 0 fgComputeLife modified tree: N003 ( 0, 0) [002679] ----------- * COMMA void N001 ( 0, 0) [002675] ----------- +--* NOP void N002 ( 0, 0) [002678] ----------- \--* NOP void Removing tree [002698] in BB94 as useless N006 ( 5, 4) [002698] -A------R-- * ASG int N005 ( 3, 2) [002696] D------N--- +--* LCL_VAR int V162 tmp122 N004 ( 1, 1) [002697] ----------- \--* LCL_VAR int V160 tmp120 fgComputeLife modified tree: N005 ( 1, 3) [002699] -A--------- * COMMA void N003 ( 1, 3) [002695] -A------R-- +--* ASG byref N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 N004 ( 0, 0) [002698] ----------- \--* NOP void Removing tree [002707] in BB96 as useless N006 ( 1, 3) [002707] -A------R-- * ASG int N005 ( 1, 1) [002705] D------N--- +--* LCL_VAR int V164 tmp124 N004 ( 1, 2) [002706] ----------- \--* CNS_INT int 0 Removing tree [002704] in BB96 as useless N003 ( 1, 3) [002704] -A------R-- * ASG byref N002 ( 1, 1) [002702] D------N--- +--* LCL_VAR byref V163 tmp123 N001 ( 1, 2) [002703] ----------- \--* CNS_INT byref 0 fgComputeLife modified tree: N003 ( 0, 0) [002708] ----------- * COMMA void N001 ( 0, 0) [002704] ----------- +--* NOP void N002 ( 0, 0) [002707] ----------- \--* NOP void top level assign removing stmt with no side effects removing useless STMT00345 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001671] -A------R-- * ASG byref N002 ( 1, 1) [001670] D------N--- +--* LCL_VAR byref V82 tmp42 N001 ( 1, 1) [001636] ----------- \--* LCL_VAR byref V143 tmp103 from BB96 top level assign removing stmt with no side effects removing useless STMT00344 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001669] -A------R-- * ASG byref N002 ( 1, 1) [001668] D------N--- +--* LCL_VAR byref V81 tmp41 N001 ( 1, 1) [001633] ----------- \--* LCL_VAR byref V161 tmp121 from BB96 Removing tree [002787] in BB112 as useless N006 ( 7, 7) [002787] -A------R-- * ASG int N005 ( 3, 2) [002785] D------N--- +--* LCL_VAR int V166 tmp126 N004 ( 3, 4) [002786] ----------- \--* LCL_FLD int V02 arg2 [+8] fgComputeLife modified tree: N005 ( 3, 4) [002788] -A--------- * COMMA void N003 ( 3, 4) [002784] -A------R-- +--* ASG byref N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 [+0] N004 ( 0, 0) [002787] ----------- \--* NOP void *************** In optRemoveRedundantZeroInits() Marking V11 as having an explicit init Marking V167 as having an explicit init Marking V17 as having an explicit init Marking V148 as having an explicit init *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: Added PHI definition for V15 at start of BB07. Added PHI definition for V16 at start of BB245. Inserting phi definition for ByrefExposed at start of BB194. Inserting phi definition for ByrefExposed at start of BB245. Added PHI definition for V16 at start of BB194. Added PHI definition for V08 at start of BB245. Added PHI definition for V20 at start of BB170. Added PHI definition for V20 at start of BB245. Inserting phi definition for ByrefExposed at start of BB169. Inserting phi definition for ByrefExposed at start of BB170. Inserting phi definition for ByrefExposed at start of BB160. Added PHI definition for V18 at start of BB156. Added PHI definition for V58 at start of BB149. Added PHI definition for V14 at start of BB156. Added PHI definition for V14 at start of BB245. Added PHI definition for V57 at start of BB155. Added PHI definition for V36 at start of BB155. Added PHI definition for V36 at start of BB156. Added PHI definition for V36 at start of BB245. Added PHI definition for V21 at start of BB245. Inserting phi definition for ByrefExposed at start of BB180. Added PHI definition for V09 at start of BB245. Added PHI definition for V55 at start of BB226. Added PHI definition for V38 at start of BB223. Added PHI definition for V38 at start of BB219. Added PHI definition for V38 at start of BB218. Added PHI definition for V16 at start of BB218. Added PHI definition for V16 at start of BB219. Added PHI definition for V37 at start of BB219. Added PHI definition for V37 at start of BB218. Inserting phi definition for ByrefExposed at start of BB239. Added PHI definition for V16 at start of BB239. Inserting phi definition for ByrefExposed at start of BB230. Added PHI definition for V08 at start of BB135. Added PHI definition for V08 at start of BB136. Added PHI definition for V14 at start of BB135. Added PHI definition for V14 at start of BB136. Added PHI definition for V20 at start of BB134. Added PHI definition for V20 at start of BB135. Added PHI definition for V20 at start of BB136. Inserting phi definition for ByrefExposed at start of BB133. Inserting phi definition for ByrefExposed at start of BB134. Inserting phi definition for ByrefExposed at start of BB135. Inserting phi definition for ByrefExposed at start of BB136. Inserting phi definition for ByrefExposed at start of BB124. Added PHI definition for V62 at start of BB121. Added PHI definition for V63 at start of BB121. Added PHI definition for V36 at start of BB121. Added PHI definition for V36 at start of BB135. Added PHI definition for V36 at start of BB136. Inserting phi definition for ByrefExposed at start of BB112. Added PHI definition for V28 at start of BB89. Added PHI definition for V27 at start of BB102. Added PHI definition for V27 at start of BB89. Added PHI definition for V30 at start of BB102. Added PHI definition for V30 at start of BB89. Inserting phi definition for ByrefExposed at start of BB103. Inserting phi definition for ByrefExposed at start of BB89. Added PHI definition for V144 at start of BB100. Added PHI definition for V144 at start of BB103. Added PHI definition for V144 at start of BB89. Added PHI definition for V143 at start of BB100. Added PHI definition for V143 at start of BB103. Added PHI definition for V143 at start of BB89. Added PHI definition for V163 at start of BB99. Added PHI definition for V164 at start of BB99. Inserting phi definition for ByrefExposed at start of BB100. Added PHI definition for V160 at start of BB94. Added PHI definition for V159 at start of BB94. Added PHI definition for V20 at start of BB103. Added PHI definition for V20 at start of BB89. Added PHI definition for V67 at start of BB88. Added PHI definition for V65 at start of BB85. Added PHI definition for V66 at start of BB85. Added PHI definition for V28 at start of BB82. Added PHI definition for V08 at start of BB78. Added PHI definition for V14 at start of BB78. Added PHI definition for V46 at start of BB77. Added PHI definition for V45 at start of BB72. Added PHI definition for V44 at start of BB69. Inserting phi definition for ByrefExposed at start of BB66. Inserting phi definition for ByrefExposed at start of BB07. Added PHI definition for V70 at start of BB60. Inserting phi definition for ByrefExposed at start of BB65. Added PHI definition for V13 at start of BB56. Added PHI definition for V12 at start of BB56. Added PHI definition for V05 at start of BB52. Added PHI definition for V16 at start of BB31. Added PHI definition for V16 at start of BB47. Added PHI definition for V04 at start of BB47. Added PHI definition for V13 at start of BB47. Added PHI definition for V11 at start of BB47. Added PHI definition for V11 at start of BB07. Added PHI definition for V10 at start of BB47. Added PHI definition for V12 at start of BB29. Added PHI definition for V12 at start of BB47. Added PHI definition for V05 at start of BB47. Added PHI definition for V07 at start of BB47. Added PHI definition for V06 at start of BB20. Added PHI definition for V06 at start of BB47. Added PHI definition for V09 at start of BB47. Added PHI definition for V16 at start of BB44. Added PHI definition for V149 at start of BB06. Added PHI definition for V43 at start of BB06. Added PHI definition for V150 at start of BB06. *************** In SsaBuilder::RenameVariables() V00.1: defined in BB00 87 uses (global) V01.1: defined in BB00 19 uses (global) V02.1: defined in BB00 22 uses (global) V03.1: defined in BB00 10 uses (global) V04.1: defined in BB07 1 uses (global), has phi uses V04.2: defined in BB47 12 uses (global), has phi uses V04.3: defined in BB17 1 uses (global), has phi uses V04.4: defined in BB20 2 uses (global), has phi uses V05.1: defined in BB07 1 uses (global), has phi uses V05.2: defined in BB47 5 uses (global), has phi uses V05.3: defined in BB52 12 uses (global) V05.4: defined in BB51 1 uses (global), has phi uses V05.5: defined in BB22 1 uses (global), has phi uses V06.1: defined in BB07 1 uses (global), has phi uses V06.2: defined in BB47 5 uses (global), has phi uses V06.3: defined in BB69 3 uses (global) V06.4: defined in BB20 1 uses (global), has phi uses V06.5: defined in BB19 1 uses (global), has phi uses V07.1: defined in BB07 1 uses (global), has phi uses V07.2: defined in BB47 3 uses (global), has phi uses V07.3: defined in BB72 2 uses (global) V07.4: defined in BB20 1 uses (global), has phi uses V08.1: defined in BB78 2 uses (global), has phi uses V08.2: defined in BB245 2 uses (global), has phi uses V08.3: defined in BB136 7 uses (global), has phi uses V08.4: defined in BB170 1 uses (global), has phi uses V08.5: defined in BB135 4 uses (global), has phi uses V08.6: defined in BB134 1 uses (global), has phi uses V08.7: defined in BB77 1 uses (global), has phi uses V08.8: defined in BB73 1 uses (global), has phi uses V09.1: defined in BB07 1 uses (global), has phi uses V09.2: defined in BB47 4 uses (global), has phi uses V09.3: defined in BB245 2 uses (global), has phi uses V09.4: defined in BB226 1 uses (global), has phi uses V09.5: defined in BB46 1 uses (global), has phi uses V10.1: defined in BB07 1 uses (global), has phi uses V10.2: defined in BB47 5 uses (global), has phi uses V10.3: defined in BB29 1 uses (global), has phi uses V11.1: defined in BB01 1 uses (global), has phi uses V11.2: defined in BB07 1 uses (global), has phi uses V11.3: defined in BB47 4 uses (global), has phi uses V11.4: defined in BB29 1 uses (global), has phi uses V11.5: defined in BB27 1 uses (global), has phi uses V12.1: defined in BB07 1 uses (global), has phi uses V12.2: defined in BB47 3 uses (global), has phi uses V12.3: defined in BB56 3 uses (global) V12.4: defined in BB55 1 uses (global), has phi uses V12.5: defined in BB29 1 uses (global), has phi uses V12.6: defined in BB28 1 uses (global), has phi uses V13.1: defined in BB07 1 uses (global), has phi uses V13.2: defined in BB47 5 uses (global), has phi uses V13.3: defined in BB56 1 uses (global) V13.4: defined in BB54 1 uses (global), has phi uses V13.5: defined in BB16 1 uses (global), has phi uses V13.6: defined in BB30 1 uses (global), has phi uses V14.1: defined in BB78 3 uses (global), has phi uses V14.2: defined in BB245 3 uses (global), has phi uses V14.3: defined in BB136 4 uses (global), has phi uses V14.4: defined in BB156 1 uses (global), has phi uses V14.5: defined in BB146 1 uses (global), has phi uses V14.6: defined in BB135 3 uses (global), has phi uses V14.7: defined in BB134 1 uses (global), has phi uses V14.8: defined in BB77 1 uses (global), has phi uses V14.9: defined in BB73 1 uses (global), has phi uses V15.1: defined in BB06 1 uses (global), has phi uses V15.2: defined in BB07 5 uses (global) V15.3: defined in BB62 1 uses (global), has phi uses V16.1: defined in BB07 1 uses (global), has phi uses V16.2: defined in BB47 3 uses (global) V16.3: defined in BB78 1 uses (global), has phi uses V16.4: defined in BB245 3 uses (global) V16.5: defined in BB246 22 uses (global), has phi uses V16.6: defined in BB239 5 uses (global), has phi uses V16.7: defined in BB236 1 uses (global), has phi uses V16.8: defined in BB233 1 uses (global), has phi uses V16.9: defined in BB219 1 uses (local) V16.10: defined in BB219 3 uses (global), has phi uses V16.11: defined in BB218 1 uses (global), has phi uses V16.12: defined in BB202 1 uses (global), has phi uses V16.13: defined in BB194 9 uses (global), has phi uses V16.14: defined in BB199 1 uses (global), has phi uses V16.15: defined in BB191 1 uses (global), has phi uses V16.16: defined in BB61 2 uses (global) V16.17: defined in BB48 12 uses (global), has phi uses V16.18: defined in BB44 1 uses (local) V16.19: defined in BB44 3 uses (global), has phi uses V16.20: defined in BB37 1 uses (global), has phi uses V16.21: defined in BB31 5 uses (global), has phi uses V16.22: defined in BB33 2 uses (global), has phi uses V17.1: defined in BB01 4 uses (global) V18.1: defined in BB246 18 uses (global) V18.2: defined in BB156 3 uses (global) V18.3: defined in BB155 1 uses (global), has phi uses V18.4: defined in BB149 1 uses (global), has phi uses V18.5: defined in BB48 9 uses (global) V20.1: defined in BB78 2 uses (global), has phi uses V20.2: defined in BB103 1 uses (global), has phi uses V20.3: defined in BB245 2 uses (global), has phi uses V20.4: defined in BB136 6 uses (global), has phi uses V20.5: defined in BB170 1 uses (global), has phi uses V20.6: defined in BB169 1 uses (global), has phi uses V20.7: defined in BB135 6 uses (global), has phi uses V20.8: defined in BB134 1 uses (global), has phi uses V20.9: defined in BB133 1 uses (global), has phi uses V20.10: defined in BB89 2 uses (global), has phi uses V20.11: defined in BB90 5 uses (global), has phi uses V21.1: defined in BB112 1 uses (global), has phi uses V21.2: defined in BB245 2 uses (global), has phi uses V21.3: defined in BB180 1 uses (global), has phi uses V22.1: defined in BB07 9 uses (global) V26.1: defined in BB80 5 uses (global) V27.1: defined in BB80 3 uses (global), has phi uses V27.2: defined in BB89 3 uses (global), has phi uses V27.3: defined in BB102 1 uses (global), has phi uses V27.4: defined in BB101 3 uses (global), has phi uses V28.1: defined in BB80 1 uses (global), has phi uses V28.2: defined in BB82 3 uses (global), has phi uses V28.3: defined in BB89 2 uses (global) V28.4: defined in BB102 2 uses (global), has phi uses V28.5: defined in BB81 1 uses (global), has phi uses V29.1: defined in BB80 2 uses (global) V30.1: defined in BB82 1 uses (global), has phi uses V30.2: defined in BB89 2 uses (global), has phi uses V30.3: defined in BB102 2 uses (global), has phi uses V30.4: defined in BB101 1 uses (global), has phi uses V31.1: defined in BB85 2 uses (global) V32.1: defined in BB88 2 uses (global) V33.1: defined in BB91 8 uses (global) V34.1: defined in BB112 18 uses (global) V36.1: defined in BB112 1 uses (global), has phi uses V36.2: defined in BB245 2 uses (global), has phi uses V36.3: defined in BB136 7 uses (global), has phi uses V36.4: defined in BB156 1 uses (global), has phi uses V36.5: defined in BB155 1 uses (global), has phi uses V36.6: defined in BB154 1 uses (global), has phi uses V36.7: defined in BB135 5 uses (global), has phi uses V36.8: defined in BB121 1 uses (global), has phi uses V36.9: defined in BB120 1 uses (global), has phi uses V37.1: defined in BB205 2 uses (global), has phi uses V37.2: defined in BB219 2 uses (global), has phi uses V37.3: defined in BB218 1 uses (global), has phi uses V37.4: defined in BB211 1 uses (global), has phi uses V38.1: defined in BB205 2 uses (global), has phi uses V38.2: defined in BB219 3 uses (global), has phi uses V38.3: defined in BB223 1 uses (global) V38.4: defined in BB222 1 uses (global), has phi uses V38.5: defined in BB218 1 uses (local) V38.6: defined in BB218 1 uses (global), has phi uses V43.1: defined in BB06 1 uses (local) V43.2: defined in BB05 1 uses (global), has phi uses V43.3: defined in BB04 1 uses (global), has phi uses V43.4: defined in BB03 1 uses (global), has phi uses V44.1: defined in BB69 1 uses (local) V44.2: defined in BB68 1 uses (global), has phi uses V44.3: defined in BB67 1 uses (global), has phi uses V45.1: defined in BB72 1 uses (local) V45.2: defined in BB71 1 uses (global), has phi uses V45.3: defined in BB70 1 uses (global), has phi uses V46.1: defined in BB77 1 uses (local) V46.2: defined in BB76 1 uses (global), has phi uses V46.3: defined in BB75 1 uses (global), has phi uses V49.1: defined in BB246 1 uses (local) V50.1: defined in BB246 2 uses (local) V51.1: defined in BB202 1 uses (local) V52.1: defined in BB233 1 uses (local) V53.1: defined in BB236 1 uses (local) V54.1: defined in BB219 2 uses (local) V55.1: defined in BB226 1 uses (local) V55.2: defined in BB225 1 uses (global), has phi uses V55.3: defined in BB224 1 uses (global), has phi uses V56.1: defined in BB154 1 uses (local) V57.1: defined in BB155 1 uses (local) V57.2: defined in BB154 1 uses (global), has phi uses V57.3: defined in BB153 1 uses (global), has phi uses V57.4: defined in BB152 1 uses (global), has phi uses V58.1: defined in BB149 1 uses (local) V58.2: defined in BB148 1 uses (global), has phi uses V58.3: defined in BB147 1 uses (global), has phi uses V59.1: defined in BB191 1 uses (local) V60.1: defined in BB118 2 uses (global) V61.1: defined in BB120 1 uses (local) V62.1: defined in BB121 6 uses (global) V62.2: defined in BB120 1 uses (global), has phi uses V62.3: defined in BB119 1 uses (global), has phi uses V63.1: defined in BB121 1 uses (local) V63.2: defined in BB120 1 uses (global), has phi uses V63.3: defined in BB119 1 uses (global), has phi uses V64.1: defined in BB82 2 uses (global) V65.1: defined in BB85 1 uses (local) V65.2: defined in BB84 1 uses (global), has phi uses V65.3: defined in BB83 1 uses (global), has phi uses V66.1: defined in BB85 1 uses (local) V66.2: defined in BB84 1 uses (global), has phi uses V66.3: defined in BB83 1 uses (global), has phi uses V67.1: defined in BB88 1 uses (local) V67.2: defined in BB87 1 uses (global), has phi uses V67.3: defined in BB86 1 uses (global), has phi uses V69.1: defined in BB57 2 uses (local) V70.1: defined in BB60 1 uses (local) V70.2: defined in BB59 1 uses (global), has phi uses V70.3: defined in BB58 1 uses (global), has phi uses V71.1: defined in BB48 1 uses (local) V72.1: defined in BB48 2 uses (local) V73.1: defined in BB44 2 uses (local) V74.1: defined in BB33 1 uses (local) V76.1: defined in BB01 2 uses (local) V2198648256: in SSA but no defs V2198648256: in SSA but no defs V83.1: defined in BB96 1 uses (local) V86.1: defined in BB106 5 uses (global) V87.1: defined in BB107 4 uses (global) V88.1: defined in BB109 2 uses (local) V91.1: defined in BB121 4 uses (global) V92.1: defined in BB121 2 uses (global) V93.1: defined in BB122 2 uses (local) V95.1: defined in BB128 5 uses (global) V96.1: defined in BB129 4 uses (global) V97.1: defined in BB131 2 uses (local) V99.1: defined in BB157 4 uses (global) V100.1: defined in BB158 2 uses (local) V102.1: defined in BB164 5 uses (global) V103.1: defined in BB165 4 uses (global) V104.1: defined in BB167 2 uses (local) V106.1: defined in BB175 5 uses (global) V107.1: defined in BB176 4 uses (global) V108.1: defined in BB178 2 uses (local) V110.1: defined in BB144 5 uses (global) V111.1: defined in BB182 4 uses (global) V112.1: defined in BB184 2 uses (local) V114.1: defined in BB186 5 uses (global) V115.1: defined in BB187 4 uses (global) V116.1: defined in BB189 2 uses (local) V118.1: defined in BB191 4 uses (global) V119.1: defined in BB191 2 uses (global) V120.1: defined in BB192 2 uses (local) V122.1: defined in BB202 4 uses (global) V123.1: defined in BB202 2 uses (global) V124.1: defined in BB203 2 uses (local) V126.1: defined in BB215 4 uses (global) V127.1: defined in BB216 2 uses (local) V129.1: defined in BB227 4 uses (global) V130.1: defined in BB228 2 uses (local) V132.1: defined in BB233 4 uses (global) V133.1: defined in BB233 2 uses (global) V134.1: defined in BB234 2 uses (local) V136.1: defined in BB236 4 uses (global) V137.1: defined in BB236 2 uses (global) V138.1: defined in BB237 2 uses (local) V140.1: defined in BB242 4 uses (global) V141.1: defined in BB243 2 uses (local) V143.1: defined in BB78 2 uses (global), has phi uses V143.2: defined in BB103 2 uses (global) V143.3: defined in BB89 3 uses (global), has phi uses V143.4: defined in BB100 3 uses (global), has phi uses V143.5: defined in BB99 1 uses (global), has phi uses V144.1: defined in BB78 2 uses (global), has phi uses V144.2: defined in BB103 2 uses (global) V144.3: defined in BB89 6 uses (global), has phi uses V144.4: defined in BB100 3 uses (global), has phi uses V144.5: defined in BB99 1 uses (global), has phi uses V147.1: defined in BB01 2 uses (global) V148.1: defined in BB01 2 uses (global) V149.1: defined in BB06 1 uses (local) V149.2: defined in BB05 1 uses (global), has phi uses V149.3: defined in BB04 1 uses (global), has phi uses V149.4: defined in BB03 1 uses (global), has phi uses V150.1: defined in BB06 1 uses (local) V150.2: defined in BB05 1 uses (global), has phi uses V150.3: defined in BB04 1 uses (global), has phi uses V150.4: defined in BB03 1 uses (global), has phi uses V151.1: defined in BB78 1 uses (local) V152.1: defined in BB78 1 uses (local) V155.1: defined in BB02 2 uses (global) V156.1: defined in BB02 2 uses (global) V157.1: defined in BB07 2 uses (local) V2198648256: in SSA but no defs V159.1: defined in BB94 1 uses (local) V159.2: defined in BB93 1 uses (global), has phi uses V159.3: defined in BB92 1 uses (global), has phi uses V160.1: defined in BB94 1 uses (local) V160.2: defined in BB93 1 uses (global), has phi uses V160.3: defined in BB92 1 uses (global), has phi uses V161.1: defined in BB94 1 uses (global) V2198648256: in SSA but no defs V163.1: defined in BB99 1 uses (local) V163.2: defined in BB98 1 uses (global), has phi uses V163.3: defined in BB97 1 uses (global), has phi uses V164.1: defined in BB99 1 uses (local) V164.2: defined in BB98 1 uses (global), has phi uses V164.3: defined in BB97 1 uses (global), has phi uses V165.1: defined in BB112 2 uses (local) V2198648256: in SSA but no defs V167.1: defined in BB01 2 uses (local) V168.1: defined in BB07 1 uses (local) V169.1: defined in BB112 1 uses (local) *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N008 ( 5, 6) [001500] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 N006 ( 5, 6) [002549] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002545] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002544] ----------- | \--* LCL_VAR byref V01 arg1 u:1 N005 ( 3, 4) [002548] -----O----- \--* ADD byref N003 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 N004 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N007 ( 14, 14) [002563] -A--------- * COMMA void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N006 ( 7, 7) [002562] -A------R-- \--* ASG int N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V167 tmp127 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) N006 ( 7, 5) [002569] -A------R-- \--* ASG int N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) N006 ( 7, 5) [002578] -A------R-- \--* ASG int N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) N006 ( 7, 5) [002585] -A------R-- \--* ASG int N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) N006 ( 7, 5) [002592] -A------R-- \--* ASG int N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 N004 ( 0, 0) [003413] ----------- \--* PHI int N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 N004 ( 0, 0) [003410] ----------- \--* PHI int N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 N004 ( 0, 0) [003407] ----------- \--* PHI byref N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 N003 ( 0, 0) [003377] ----------- \--* PHI int N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 N003 ( 0, 0) [003161] ----------- \--* PHI int N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 3, 4) [002606] -A--------- * COMMA void N003 ( 3, 4) [002602] -A------R-- +--* ASG byref N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N004 ( 0, 0) [002605] ----------- \--* NOP void ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 N005 ( 2, 4) [002611] -A--------- \--* COMMA long N003 ( 1, 3) [002608] -A------R-- +--* ASG long N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 N003 ( 3, 4) [001358] ----------- \--* ADD int N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 N003 ( 3, 4) [001432] ----------- \--* ADD int N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void N003 ( 3, 6) [001375] N------N-U- \--* NE int N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 N003 ( 0, 0) [003395] ----------- \--* PHI int N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 N003 ( 3, 4) [001379] ----------- \--* ADD int N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void N003 ( 3, 4) [001390] J------N--- \--* GE int N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void N003 ( 3, 4) [001397] J------N--- \--* LE int N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void N003 ( 3, 4) [001401] J------N--- \--* GE int N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void N003 ( 3, 4) [001405] J------N--- \--* LT int N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void N003 ( 3, 3) [001415] N------N-U- \--* NE int N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 N003 ( 3, 4) [001422] ----------- \--* ADD int N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 N003 ( 0, 0) [003383] ----------- \--* PHI bool N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 N003 ( 3, 4) [001427] ----------- \--* ADD int N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 N003 ( 0, 0) [003362] ----------- \--* PHI int N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 7, 8) [001441] ----------- * JTRUE void N003 ( 5, 6) [001440] J------N--- \--* GE int N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N010 ( 13, 15) [001452] ---XG------ * JTRUE void N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001447] ----------- | \--* LSH long N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 N003 ( 3, 4) [001457] ----------- \--* ADD int N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V16 loc12 u:21 (last use) N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N010 ( 13, 14) [001471] ---XG------ * JTRUE void N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001466] ----------- | \--* LSH long N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 7, 8) [001240] ----------- * JTRUE void N003 ( 5, 6) [001239] J------N--- \--* GE int N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N010 ( 13, 15) [001251] ---XG------ * JTRUE void N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001246] ----------- | \--* LSH long N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 N003 ( 3, 4) [001254] ----------- \--* ADD int N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 7, 8) [001267] ----------- * JTRUE void N003 ( 5, 6) [001266] J------N--- \--* GE int N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N010 ( 13, 15) [001351] ---XG------ * JTRUE void N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001346] ----------- | \--* LSH long N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 9, 11) [001276] ----------- * JTRUE void N005 ( 7, 9) [001275] J------N--- \--* GE int N003 ( 3, 4) [001270] ----------- +--* ADD int N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N010 ( 13, 15) [001287] ---XG------ * JTRUE void N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001282] ----------- | \--* LSH long N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N010 ( 13, 15) [001340] ---XG------ * JTRUE void N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001335] ----------- | \--* LSH long N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 N007 ( 6, 9) [001295] ----------- | \--* LSH long N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int N004 ( 3, 4) [001291] ----------- | | \--* ADD int N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 N003 ( 0, 0) [003404] ----------- \--* PHI int N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 N003 ( 3, 4) [001303] ----------- \--* ADD int N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 7, 8) [001315] ----------- * JTRUE void N003 ( 5, 6) [001314] J------N--- \--* GE int N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V73 tmp33 u:1 (last use) N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001324] ----------- | \--* LSH long N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 N004 ( 0, 0) [003401] ----------- \--* PHI bool N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 N004 ( 0, 0) [003398] ----------- \--* PHI int N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 N004 ( 0, 0) [003392] ----------- \--* PHI int N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 N004 ( 0, 0) [003389] ----------- \--* PHI int N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 N004 ( 0, 0) [003386] ----------- \--* PHI bool N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 N004 ( 0, 0) [003380] ----------- \--* PHI int N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 N005 ( 0, 0) [003374] ----------- \--* PHI int N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 N005 ( 0, 0) [003371] ----------- \--* PHI int N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 N005 ( 0, 0) [003368] ----------- \--* PHI int N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 N007 ( 0, 0) [003365] ----------- \--* PHI int N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 7, 8) [000079] ----------- * JTRUE void N003 ( 5, 6) [000078] J------N--- \--* GE int N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 N003 ( 3, 4) [001201] ----------- \--* ADD int N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V16 loc12 u:2 (last use) N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001210] ----------- \--* LSH long N003 ( 2, 3) [001207] ----------- +--* CAST long <- int N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V72 tmp32 u:1 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void N003 ( 3, 4) [000086] J------N--- \--* GE int N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 N003 ( 0, 0) [003359] ----------- \--* PHI int N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void N003 ( 3, 4) [000090] J------N--- \--* LT int N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void N003 ( 3, 3) [001182] N------N-U- \--* NE int N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 N005 ( 8, 8) [001191] ----------- \--* SUB int N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N004 ( 6, 6) [001190] ----------- \--* MUL int N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 N003 ( 0, 0) [003356] ----------- \--* PHI bool N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 N003 ( 0, 0) [003353] ----------- \--* PHI int N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N008 ( 5, 6) [001129] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 N006 ( 5, 6) [002621] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002617] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002616] ----------- | \--* LCL_VAR byref V01 arg1 u:1 N005 ( 3, 4) [002620] -----O----- \--* ADD byref N003 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 N004 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int N006 ( 3, 2) [001135] D--XG--N--- +--* IND int N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void N003 ( 3, 4) [001139] J------N--- \--* NE int N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 N003 ( 0, 0) [003350] ----------- \--* PHI int N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void N003 ( 3, 3) [001166] J------N--- \--* EQ int N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool N003 ( 3, 4) [002632] -------N--- | \--* ADD byref N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int N004 ( 4, 3) [000104] D--XG--N--- +--* IND int N003 ( 3, 4) [002634] -------N--- | \--* ADD byref N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void N003 ( 3, 3) [000108] J------N--- \--* LT int N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 N003 ( 3, 3) [000112] ----------- \--* SUB int N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 N003 ( 0, 0) [003347] ----------- \--* PHI int N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void N003 ( 3, 3) [000121] J------N--- \--* GT int N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 N003 ( 3, 3) [000125] ----------- \--* SUB int N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 N003 ( 0, 0) [003344] ----------- \--* PHI int N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void N003 ( 3, 4) [000134] J------N--- \--* EQ int N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N007 ( 8, 7) [000140] ---XG------ * JTRUE void N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 N003 ( 0, 0) [003341] ----------- \--* PHI int N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 N003 ( 0, 0) [003338] ----------- \--* PHI int N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 N003 ( 0, 0) [003335] ----------- \--* PHI int N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void N001 ( 0, 0) [002643] ----------- +--* NOP void N002 ( 0, 0) [002646] ----------- \--* NOP void ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) N006 ( 1, 3) [002653] -A------R-- \--* ASG int N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void N003 ( 3, 4) [000180] J------N--- \--* EQ int N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 N011 ( 4, 6) [002665] ----------- \--* LSH long N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 N003 ( 0, 0) [003332] ----------- \--* PHI int N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void N003 ( 3, 4) [000972] J------N--- \--* LT int N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 N003 ( 0, 0) [003329] ----------- \--* PHI int N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 N003 ( 0, 0) [003326] ----------- \--* PHI int N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 N003 ( 7, 5) [000988] ----------- \--* ADD int N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void N003 ( 5, 4) [000993] J------N--- \--* GT int N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 N003 ( 0, 0) [003323] ----------- \--* PHI int N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void N003 ( 3, 3) [003157] J------N--- \--* LE int N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V28 loc24 u:2 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 N003 ( 0, 0) [003320] ----------- \--* PHI int N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 N003 ( 0, 0) [003302] ----------- \--* PHI byref N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 N003 ( 0, 0) [003293] ----------- \--* PHI int N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 N003 ( 0, 0) [003284] ----------- \--* PHI int N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 N003 ( 0, 0) [003278] ----------- \--* PHI int N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 N003 ( 0, 0) [003272] ----------- \--* PHI int N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void N003 ( 3, 4) [001008] J------N--- \--* EQ int N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 N003 ( 3, 4) [001012] ----------- \--* ADD int N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void N003 ( 3, 3) [001020] J------N--- \--* LT int N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int N003 ( 3, 4) [001066] ----------- | \--* LSH int N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void N001 ( 0, 0) [002675] ----------- +--* NOP void N002 ( 0, 0) [002678] ----------- \--* NOP void ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 5, 6) [001590] ----------- * JTRUE void N003 ( 3, 4) [001589] J------N--- \--* NE int N001 ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [001588] ----------- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002685] -A------R-- \--* ASG int N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N008 ( 5, 6) [001604] -A-X-O--R-- * ASG byref N007 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 N006 ( 5, 6) [002692] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002688] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002687] ----------- | \--* LCL_VAR ref V33 loc29 u:1 N005 ( 3, 4) [002691] -----O----- \--* ADD byref N003 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 N004 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 N003 ( 0, 0) [003314] ----------- \--* PHI byref N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 N003 ( 0, 0) [003311] ----------- \--* PHI int N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void N003 ( 1, 3) [002695] -A------R-- +--* ASG byref N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) N004 ( 0, 0) [002698] ----------- \--* NOP void ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void N003 ( 3, 3) [001628] N------N-U- \--* GT int N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void N001 ( 0, 0) [002704] ----------- +--* NOP void N002 ( 0, 0) [002707] ----------- \--* NOP void ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 5, 6) [001702] ----------- * JTRUE void N003 ( 3, 4) [001701] J------N--- \--* NE int N001 ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [001700] ----------- \--* CNS_INT ref null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002714] -A------R-- \--* ASG int N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N008 ( 5, 6) [001716] -A-X-O--R-- * ASG byref N007 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 N006 ( 5, 6) [002721] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002717] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002716] ----------- | \--* LCL_VAR ref V33 loc29 u:1 N005 ( 3, 4) [002720] -----O----- \--* ADD byref N003 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 N004 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 N003 ( 0, 0) [003308] ----------- \--* PHI int N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 N003 ( 0, 0) [003305] ----------- \--* PHI byref N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) N006 ( 1, 3) [002727] -A------R-- \--* ASG int N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 N003 ( 0, 0) [003296] ----------- \--* PHI byref N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 N003 ( 0, 0) [003287] ----------- \--* PHI int N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 N008 ( 4, 6) [001032] ----------- | \--* LSH long N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 N003 ( 3, 4) [001052] ----------- \--* ADD int N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 N011 ( 4, 6) [002736] ----------- \--* LSH long N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 N003 ( 0, 0) [003281] ----------- \--* PHI int N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 N003 ( 0, 0) [003275] ----------- \--* PHI int N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 N003 ( 3, 3) [001047] ----------- \--* ADD int N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void N003 ( 3, 3) [001004] J------N--- \--* GT int N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 N004 ( 0, 0) [003317] ----------- \--* PHI int N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 N004 ( 0, 0) [003299] ----------- \--* PHI byref N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 N004 ( 0, 0) [003290] ----------- \--* PHI int N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void N003 ( 3, 4) [000929] J------N--- \--* NE int N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V15 loc11 u:2 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 5, 6) [001759] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 N006 ( 5, 6) [002761] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002757] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002756] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [002760] -----O----- \--* ADD byref N003 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int N007 ( 4, 3) [001780] D--XG--N--- +--* IND int N006 ( 3, 4) [002779] -------N--- | \--* ADD byref N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 3, 4) [002788] -A--------- * COMMA void N003 ( 3, 4) [002784] -A------R-- +--* ASG byref N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N004 ( 0, 0) [002787] ----------- \--* NOP void ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 N005 ( 2, 4) [002793] -A--------- \--* COMMA long N003 ( 1, 3) [002790] -A------R-- +--* ASG long N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void N003 ( 3, 4) [000273] J------N--- \--* LE int N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N005 ( 8, 8) [000834] ---XG------ * JTRUE void N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 N003 ( 3, 4) [000844] ----------- \--* ADD long N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V36 loc32 u:7 (last use) N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) ***** BB120 STMT00183 ( ??? ... ??? ) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 N003 ( 0, 0) [003263] ----------- \--* PHI long N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 N003 ( 0, 0) [003260] ----------- \--* PHI int N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 N003 ( 0, 0) [003257] ----------- \--* PHI byref N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V62 tmp22 u:1 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V62 tmp22 u:1 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [001815] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 N006 ( 5, 6) [002806] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002802] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002801] ----------- | \--* LCL_VAR byref V62 tmp22 u:1 N005 ( 3, 4) [002805] -----O----- \--* ADD byref N003 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 u:1 N004 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int N007 ( 4, 3) [001833] D--XG--N--- +--* IND int N006 ( 3, 4) [002811] -------N--- | \--* ADD byref N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V62 tmp22 u:1 (last use) N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V62 tmp22 u:1 (last use) N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void N003 ( 3, 4) [000862] J------N--- \--* EQ int N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void N003 ( 3, 4) [000876] J------N--- \--* LE int N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void N003 ( 3, 4) [000880] J------N--- \--* LT int N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 N008 ( 4, 6) [000893] ----------- | | \--* LSH long N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 5, 6) [001872] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 N006 ( 5, 6) [002828] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002824] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002823] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [002827] -----O----- \--* ADD byref N003 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int N007 ( 4, 3) [001893] D--XG--N--- +--* IND int N006 ( 3, 4) [002846] -------N--- | \--* ADD byref N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 N003 ( 3, 4) [000909] ----------- \--* ADD int N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 N003 ( 0, 0) [003248] ----------- \--* PHI int N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 N003 ( 3, 4) [000866] ----------- \--* ADD int N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 N003 ( 3, 4) [000871] ----------- \--* ADD int N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 N003 ( 0, 0) [003266] ----------- \--* PHI long N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 N003 ( 0, 0) [003251] ----------- \--* PHI int N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 N003 ( 0, 0) [003242] ----------- \--* PHI int N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 N003 ( 0, 0) [003236] ----------- \--* PHI int N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void N003 ( 3, 4) [000827] J------N--- \--* GT int N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 N003 ( 0, 0) [003269] ----------- \--* PHI long N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 N003 ( 0, 0) [003254] ----------- \--* PHI int N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 N003 ( 0, 0) [003245] ----------- \--* PHI int N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 N003 ( 0, 0) [003239] ----------- \--* PHI int N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void N003 ( 3, 4) [000641] J------N--- \--* GE int N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 N003 ( 3, 4) [000733] ----------- \--* ADD int N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void N003 ( 3, 3) [000738] J------N--- \--* LE int N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 N003 ( 0, 0) [003182] ----------- \--* PHI int N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void N003 ( 3, 3) [000721] J------N--- \--* GT int N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 N003 ( 3, 4) [000652] ----------- \--* ADD long N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V36 loc32 u:3 (last use) N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 N003 ( 0, 0) [003194] ----------- \--* PHI long N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 N004 ( 0, 0) [003191] ----------- \--* PHI int N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 N003 ( 0, 0) [003197] ----------- \--* PHI long N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 N003 ( 0, 0) [003185] ----------- \--* PHI int N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 N003 ( 0, 0) [003179] ----------- \--* PHI ushort N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void N003 ( 3, 4) [000667] J------N--- \--* EQ int N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 5, 6) [001920] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 N006 ( 5, 6) [002864] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002860] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002859] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [002863] -----O----- \--* ADD byref N003 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int N007 ( 4, 3) [001938] D--XG--N--- +--* IND int N006 ( 3, 4) [002869] -------N--- | \--* ADD byref N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void N003 ( 3, 4) [000679] J------N--- \--* EQ int N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void N003 ( 3, 4) [000683] J------N--- \--* LE int N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void N003 ( 3, 4) [000687] J------N--- \--* LT int N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 N008 ( 4, 6) [000700] ----------- | | \--* LSH long N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 5, 6) [001975] -A-XGO--R-- * ASG byref N007 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 N006 ( 5, 6) [002886] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002882] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002881] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [002885] -----O----- \--* ADD byref N003 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int N007 ( 4, 3) [001996] D--XG--N--- +--* IND int N006 ( 3, 4) [002904] -------N--- | \--* ADD byref N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 N003 ( 3, 4) [000716] ----------- \--* ADD int N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 N003 ( 0, 0) [003173] ----------- \--* PHI int N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 N003 ( 3, 4) [000671] ----------- \--* ADD int N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void N007 ( 10, 9) [000611] J------N--- \--* NE int N005 ( 8, 6) [000609] ----------- +--* OR int N003 ( 6, 4) [000607] ----------- | +--* NE int N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void N003 ( 3, 4) [000615] J------N--- \--* LT int N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void N003 ( 3, 3) [000627] J------N--- \--* GE int N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 5, 6) [002035] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 N006 ( 5, 6) [002920] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002916] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002915] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [002919] -----O----- \--* ADD byref N003 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int N007 ( 4, 3) [002056] D--XG--N--- +--* IND int N006 ( 3, 4) [002938] -------N--- | \--* ADD byref N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 5, 6) [002095] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 N006 ( 5, 6) [002953] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002949] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002948] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [002952] -----O----- \--* ADD byref N003 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int N007 ( 4, 3) [002116] D--XG--N--- +--* IND int N006 ( 3, 4) [002971] -------N--- | \--* ADD byref N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 5, 6) [002155] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 N006 ( 5, 6) [002987] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [002983] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [002982] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [002986] -----O----- \--* ADD byref N003 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int N007 ( 4, 3) [002176] D--XG--N--- +--* IND int N006 ( 3, 4) [003005] -------N--- | \--* ADD byref N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 N003 ( 3, 4) [000808] ----------- \--* ADD int N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000817] ----------- \--* LSH long N003 ( 2, 3) [000814] ----------- +--* CAST long <- int N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [002204] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 N006 ( 5, 6) [003019] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003015] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003014] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [003018] -----O----- \--* ADD byref N003 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int N007 ( 4, 3) [002222] D--XG--N--- +--* IND int N006 ( 3, 4) [003024] -------N--- | \--* ADD byref N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 N003 ( 0, 0) [003167] ----------- \--* PHI int N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 7, 8) [000757] ----------- * JTRUE void N003 ( 5, 6) [000756] J------N--- \--* GE int N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N010 ( 13, 15) [000791] ---XG------ * JTRUE void N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000786] ----------- | \--* LSH long N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N010 ( 13, 14) [000802] ---XG------ * JTRUE void N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000797] ----------- | \--* LSH long N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 7, 8) [000764] ----------- * JTRUE void N003 ( 5, 6) [000763] J------N--- \--* GE int N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N010 ( 13, 15) [000775] ---XG------ * JTRUE void N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000770] ----------- | \--* LSH long N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 N003 ( 3, 4) [000778] ----------- \--* ADD int N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 7, 8) [000289] ----------- * JTRUE void N003 ( 5, 6) [000288] J------N--- \--* GE int N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N010 ( 13, 15) [000300] ---XG------ * JTRUE void N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000295] ----------- | \--* LSH long N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 N003 ( 3, 4) [000306] ----------- \--* ADD int N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000315] ----------- \--* LSH long N003 ( 2, 3) [000312] ----------- +--* CAST long <- int N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [002262] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 N006 ( 5, 6) [003038] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003034] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003033] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [003037] -----O----- \--* ADD byref N003 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int N007 ( 4, 3) [002280] D--XG--N--- +--* IND int N006 ( 3, 4) [003043] -------N--- | \--* ADD byref N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void N003 ( 3, 4) [000331] J------N--- \--* EQ int N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 7, 8) [000425] ----------- * JTRUE void N003 ( 5, 6) [000424] J------N--- \--* GE int N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N010 ( 13, 15) [000575] ---XG------ * JTRUE void N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000570] ----------- | \--* LSH long N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 9, 11) [000434] ----------- * JTRUE void N005 ( 7, 9) [000433] J------N--- \--* GE int N003 ( 3, 4) [000428] ----------- +--* ADD int N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N010 ( 13, 15) [000548] ---XG------ * JTRUE void N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000543] ----------- | \--* LSH long N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 N007 ( 6, 9) [000556] ----------- | \--* LSH long N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int N004 ( 3, 4) [000552] ----------- | | \--* ADD int N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) N006 ( 9, 11) [000443] ----------- * JTRUE void N005 ( 7, 9) [000442] J------N--- \--* GE int N003 ( 3, 4) [000437] ----------- +--* ADD int N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N010 ( 13, 15) [000457] ---XG------ * JTRUE void N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000452] ----------- | \--* LSH long N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 N007 ( 6, 9) [000465] ----------- | \--* LSH long N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int N004 ( 3, 4) [000461] ----------- | | \--* ADD int N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 5, 6) [002319] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 N006 ( 5, 6) [003059] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003055] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003054] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [003058] -----O----- \--* ADD byref N003 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int N007 ( 4, 3) [002337] D--XG--N--- +--* IND int N006 ( 3, 4) [003064] -------N--- | \--* ADD byref N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 N003 ( 0, 0) [003230] ----------- \--* PHI bool N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 N003 ( 0, 0) [003221] ----------- \--* PHI int N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 N003 ( 0, 0) [003218] ----------- \--* PHI int N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 N003 ( 3, 4) [000535] ----------- \--* ADD int N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 N004 ( 0, 0) [003227] ----------- \--* PHI bool N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 N003 ( 0, 0) [003224] ----------- \--* PHI int N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 N003 ( 0, 0) [003215] ----------- \--* PHI int N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 N003 ( 3, 4) [000473] ----------- \--* ADD int N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 7, 8) [000485] ----------- * JTRUE void N003 ( 5, 6) [000484] J------N--- \--* GE int N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V54 tmp14 u:1 (last use) N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000527] ----------- | \--* LSH long N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void N003 ( 3, 4) [000488] J------N--- \--* LE int N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 N003 ( 0, 0) [003212] ----------- \--* PHI int N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 N003 ( 0, 0) [003209] ----------- \--* PHI int N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 5, 6) [002366] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 N006 ( 5, 6) [003082] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003078] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003077] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [003081] -----O----- \--* ADD byref N003 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int N007 ( 4, 3) [002384] D--XG--N--- +--* IND int N006 ( 3, 4) [003087] -------N--- | \--* ADD byref N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 7, 8) [000342] ----------- * JTRUE void N003 ( 5, 6) [000341] J------N--- \--* GE int N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N010 ( 13, 15) [000353] ---XG------ * JTRUE void N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000348] ----------- | \--* LSH long N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N010 ( 13, 15) [000418] ---XG------ * JTRUE void N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000413] ----------- | \--* LSH long N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 N003 ( 3, 4) [000359] ----------- \--* ADD int N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000368] ----------- \--* LSH long N003 ( 2, 3) [000365] ----------- +--* CAST long <- int N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [002414] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 N006 ( 5, 6) [003101] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003097] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003096] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [003100] -----O----- \--* ADD byref N003 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int N007 ( 4, 3) [002432] D--XG--N--- +--* IND int N006 ( 3, 4) [003106] -------N--- | \--* ADD byref N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 N003 ( 3, 4) [000395] ----------- \--* ADD int N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V16 loc12 u:6 (last use) N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000404] ----------- \--* LSH long N003 ( 2, 3) [000401] ----------- +--* CAST long <- int N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N008 ( 5, 6) [002460] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 N006 ( 5, 6) [003120] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003116] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003115] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [003119] -----O----- \--* ADD byref N003 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int N007 ( 4, 3) [002478] D--XG--N--- +--* IND int N006 ( 3, 4) [003125] -------N--- | \--* ADD byref N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 N004 ( 0, 0) [003233] ----------- \--* PHI int N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 7, 8) [000378] ----------- * JTRUE void N003 ( 5, 6) [000377] J------N--- \--* GE int N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N010 ( 13, 15) [000389] ---XG------ * JTRUE void N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000384] ----------- | \--* LSH long N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 5, 6) [002509] -A-XGO--R-- * ASG byref N007 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 N006 ( 5, 6) [003139] ---X-O-N--- \--* COMMA byref N002 ( 2, 2) [003135] ---X-O----- +--* NULLCHECK byte N001 ( 1, 1) [003134] ----------- | \--* LCL_VAR byref V00 arg0 u:1 N005 ( 3, 4) [003138] -----O----- \--* ADD byref N003 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N004 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int N007 ( 4, 3) [002527] D--XG--N--- +--* IND int N006 ( 3, 4) [003144] -------N--- | \--* ADD byref N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 N004 ( 0, 0) [003206] ----------- \--* PHI bool N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 N004 ( 0, 0) [003203] ----------- \--* PHI bool N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 N004 ( 0, 0) [003200] ----------- \--* PHI long N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 N004 ( 0, 0) [003188] ----------- \--* PHI int N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 N004 ( 0, 0) [003176] ----------- \--* PHI int N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 N004 ( 0, 0) [003170] ----------- \--* PHI int N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 N008 ( 0, 0) [003164] ----------- \--* PHI int N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 7, 8) [000210] ----------- * JTRUE void N003 ( 5, 6) [000209] J------N--- \--* GE int N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 N003 ( 3, 4) [000246] ----------- \--* ADD int N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V16 loc12 u:4 (last use) N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000255] ----------- \--* LSH long N003 ( 2, 3) [000252] ----------- +--* CAST long <- int N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V50 tmp10 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void N003 ( 3, 4) [000223] J------N--- \--* NE int N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist SSA checks completed successfully *************** In fgDebugCheckLoopTable *************** Starting PHASE Early Value Propagation optEarlyProp Marking a null check for removal N002 ( 2, 2) [002545] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002544] ----------- \--* LCL_VAR byref V01 arg1 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 N003 ( 3, 4) [002548] -----O----- \--* ADD byref N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002617] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002616] ----------- \--* LCL_VAR byref V01 arg1 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 N003 ( 3, 4) [002620] -----O----- \--* ADD byref N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002688] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002687] ----------- \--* LCL_VAR ref V33 loc29 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001604] -A---O--R-- * ASG byref N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 N003 ( 3, 4) [002691] -----O----- \--* ADD byref N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] optEarlyProp Marking a null check for removal N002 ( 2, 2) [002717] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002716] ----------- \--* LCL_VAR ref V33 loc29 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001716] -A---O--R-- * ASG byref N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 N003 ( 3, 4) [002720] -----O----- \--* ADD byref N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] optEarlyProp Marking a null check for removal N002 ( 2, 2) [002757] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002756] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 N003 ( 3, 4) [002760] -----O----- \--* ADD byref N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002802] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002801] ----------- \--* LCL_VAR byref V62 tmp22 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 N003 ( 3, 4) [002805] -----O----- \--* ADD byref N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 u:1 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002824] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002823] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 N003 ( 3, 4) [002827] -----O----- \--* ADD byref N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002860] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002859] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 N003 ( 3, 4) [002863] -----O----- \--* ADD byref N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002882] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002881] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 N003 ( 3, 4) [002885] -----O----- \--* ADD byref N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002916] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002915] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 N003 ( 3, 4) [002919] -----O----- \--* ADD byref N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002949] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002948] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 N003 ( 3, 4) [002952] -----O----- \--* ADD byref N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [002983] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [002982] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 N003 ( 3, 4) [002986] -----O----- \--* ADD byref N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [003015] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [003014] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 N003 ( 3, 4) [003018] -----O----- \--* ADD byref N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [003034] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [003033] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 N003 ( 3, 4) [003037] -----O----- \--* ADD byref N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [003055] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [003054] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 N003 ( 3, 4) [003058] -----O----- \--* ADD byref N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [003078] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [003077] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 N003 ( 3, 4) [003081] -----O----- \--* ADD byref N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [003097] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [003096] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 N003 ( 3, 4) [003100] -----O----- \--* ADD byref N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [003116] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [003115] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 N003 ( 3, 4) [003119] -----O----- \--* ADD byref N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 optEarlyProp Marking a null check for removal N002 ( 2, 2) [003135] ---X-O----- * NULLCHECK byte N001 ( 1, 1) [003134] ----------- \--* LCL_VAR byref V00 arg0 u:1 optFoldNullCheck morphed tree: N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 N003 ( 3, 4) [003138] -----O----- \--* ADD byref N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 Optimized 17 trees *************** Finishing PHASE Early Value Propagation Trees after Early Value Propagation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 N003 ( 3, 4) [002548] -----O----- \--* ADD byref N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N007 ( 14, 14) [002563] -A--------- * COMMA void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N006 ( 7, 7) [002562] -A------R-- \--* ASG int N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V167 tmp127 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) N006 ( 7, 5) [002569] -A------R-- \--* ASG int N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) N006 ( 7, 5) [002578] -A------R-- \--* ASG int N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) N006 ( 7, 5) [002585] -A------R-- \--* ASG int N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) N006 ( 7, 5) [002592] -A------R-- \--* ASG int N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 N004 ( 0, 0) [003413] ----------- \--* PHI int N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 N004 ( 0, 0) [003410] ----------- \--* PHI int N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 N004 ( 0, 0) [003407] ----------- \--* PHI byref N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 N003 ( 0, 0) [003377] ----------- \--* PHI int N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 N003 ( 0, 0) [003161] ----------- \--* PHI int N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 3, 4) [002606] -A--------- * COMMA void N003 ( 3, 4) [002602] -A------R-- +--* ASG byref N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N004 ( 0, 0) [002605] ----------- \--* NOP void ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 N005 ( 2, 4) [002611] -A--------- \--* COMMA long N003 ( 1, 3) [002608] -A------R-- +--* ASG long N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 N003 ( 3, 4) [001358] ----------- \--* ADD int N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 N003 ( 3, 4) [001432] ----------- \--* ADD int N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void N003 ( 3, 6) [001375] N------N-U- \--* NE int N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 N003 ( 0, 0) [003395] ----------- \--* PHI int N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 N003 ( 3, 4) [001379] ----------- \--* ADD int N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void N003 ( 3, 4) [001390] J------N--- \--* GE int N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void N003 ( 3, 4) [001397] J------N--- \--* LE int N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void N003 ( 3, 4) [001401] J------N--- \--* GE int N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void N003 ( 3, 4) [001405] J------N--- \--* LT int N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void N003 ( 3, 3) [001415] N------N-U- \--* NE int N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 N003 ( 3, 4) [001422] ----------- \--* ADD int N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 N003 ( 0, 0) [003383] ----------- \--* PHI bool N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 N003 ( 3, 4) [001427] ----------- \--* ADD int N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 N003 ( 0, 0) [003362] ----------- \--* PHI int N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 7, 8) [001441] ----------- * JTRUE void N003 ( 5, 6) [001440] J------N--- \--* GE int N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N010 ( 13, 15) [001452] ---XG------ * JTRUE void N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001447] ----------- | \--* LSH long N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 N003 ( 3, 4) [001457] ----------- \--* ADD int N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V16 loc12 u:21 (last use) N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N010 ( 13, 14) [001471] ---XG------ * JTRUE void N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001466] ----------- | \--* LSH long N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 7, 8) [001240] ----------- * JTRUE void N003 ( 5, 6) [001239] J------N--- \--* GE int N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N010 ( 13, 15) [001251] ---XG------ * JTRUE void N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001246] ----------- | \--* LSH long N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 N003 ( 3, 4) [001254] ----------- \--* ADD int N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 7, 8) [001267] ----------- * JTRUE void N003 ( 5, 6) [001266] J------N--- \--* GE int N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N010 ( 13, 15) [001351] ---XG------ * JTRUE void N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001346] ----------- | \--* LSH long N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 9, 11) [001276] ----------- * JTRUE void N005 ( 7, 9) [001275] J------N--- \--* GE int N003 ( 3, 4) [001270] ----------- +--* ADD int N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N010 ( 13, 15) [001287] ---XG------ * JTRUE void N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001282] ----------- | \--* LSH long N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N010 ( 13, 15) [001340] ---XG------ * JTRUE void N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001335] ----------- | \--* LSH long N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 N007 ( 6, 9) [001295] ----------- | \--* LSH long N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int N004 ( 3, 4) [001291] ----------- | | \--* ADD int N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 N003 ( 0, 0) [003404] ----------- \--* PHI int N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 N003 ( 3, 4) [001303] ----------- \--* ADD int N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 7, 8) [001315] ----------- * JTRUE void N003 ( 5, 6) [001314] J------N--- \--* GE int N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V73 tmp33 u:1 (last use) N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001324] ----------- | \--* LSH long N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 N004 ( 0, 0) [003401] ----------- \--* PHI bool N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 N004 ( 0, 0) [003398] ----------- \--* PHI int N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 N004 ( 0, 0) [003392] ----------- \--* PHI int N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 N004 ( 0, 0) [003389] ----------- \--* PHI int N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 N004 ( 0, 0) [003386] ----------- \--* PHI bool N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 N004 ( 0, 0) [003380] ----------- \--* PHI int N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 N005 ( 0, 0) [003374] ----------- \--* PHI int N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 N005 ( 0, 0) [003371] ----------- \--* PHI int N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 N005 ( 0, 0) [003368] ----------- \--* PHI int N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 N007 ( 0, 0) [003365] ----------- \--* PHI int N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 7, 8) [000079] ----------- * JTRUE void N003 ( 5, 6) [000078] J------N--- \--* GE int N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 N003 ( 3, 4) [001201] ----------- \--* ADD int N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V16 loc12 u:2 (last use) N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001210] ----------- \--* LSH long N003 ( 2, 3) [001207] ----------- +--* CAST long <- int N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V72 tmp32 u:1 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void N003 ( 3, 4) [000086] J------N--- \--* GE int N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 N003 ( 0, 0) [003359] ----------- \--* PHI int N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void N003 ( 3, 4) [000090] J------N--- \--* LT int N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void N003 ( 3, 3) [001182] N------N-U- \--* NE int N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 N005 ( 8, 8) [001191] ----------- \--* SUB int N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N004 ( 6, 6) [001190] ----------- \--* MUL int N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 N003 ( 0, 0) [003356] ----------- \--* PHI bool N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 N003 ( 0, 0) [003353] ----------- \--* PHI int N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 N003 ( 3, 4) [002620] -----O----- \--* ADD byref N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int N006 ( 3, 2) [001135] D--XG--N--- +--* IND int N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void N003 ( 3, 4) [001139] J------N--- \--* NE int N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 N003 ( 0, 0) [003350] ----------- \--* PHI int N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void N003 ( 3, 3) [001166] J------N--- \--* EQ int N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool N003 ( 3, 4) [002632] -------N--- | \--* ADD byref N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int N004 ( 4, 3) [000104] D--XG--N--- +--* IND int N003 ( 3, 4) [002634] -------N--- | \--* ADD byref N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void N003 ( 3, 3) [000108] J------N--- \--* LT int N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 N003 ( 3, 3) [000112] ----------- \--* SUB int N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 N003 ( 0, 0) [003347] ----------- \--* PHI int N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void N003 ( 3, 3) [000121] J------N--- \--* GT int N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 N003 ( 3, 3) [000125] ----------- \--* SUB int N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 N003 ( 0, 0) [003344] ----------- \--* PHI int N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void N003 ( 3, 4) [000134] J------N--- \--* EQ int N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N007 ( 8, 7) [000140] ---XG------ * JTRUE void N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 N003 ( 0, 0) [003341] ----------- \--* PHI int N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 N003 ( 0, 0) [003338] ----------- \--* PHI int N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 N003 ( 0, 0) [003335] ----------- \--* PHI int N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void N001 ( 0, 0) [002643] ----------- +--* NOP void N002 ( 0, 0) [002646] ----------- \--* NOP void ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) N006 ( 1, 3) [002653] -A------R-- \--* ASG int N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void N003 ( 3, 4) [000180] J------N--- \--* EQ int N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 N011 ( 4, 6) [002665] ----------- \--* LSH long N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 N003 ( 0, 0) [003332] ----------- \--* PHI int N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void N003 ( 3, 4) [000972] J------N--- \--* LT int N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 N003 ( 0, 0) [003329] ----------- \--* PHI int N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 N003 ( 0, 0) [003326] ----------- \--* PHI int N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 N003 ( 7, 5) [000988] ----------- \--* ADD int N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void N003 ( 5, 4) [000993] J------N--- \--* GT int N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 N003 ( 0, 0) [003323] ----------- \--* PHI int N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void N003 ( 3, 3) [003157] J------N--- \--* LE int N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V28 loc24 u:2 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 N003 ( 0, 0) [003320] ----------- \--* PHI int N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 N003 ( 0, 0) [003302] ----------- \--* PHI byref N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 N003 ( 0, 0) [003293] ----------- \--* PHI int N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 N003 ( 0, 0) [003284] ----------- \--* PHI int N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 N003 ( 0, 0) [003278] ----------- \--* PHI int N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 N003 ( 0, 0) [003272] ----------- \--* PHI int N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void N003 ( 3, 4) [001008] J------N--- \--* EQ int N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 N003 ( 3, 4) [001012] ----------- \--* ADD int N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void N003 ( 3, 3) [001020] J------N--- \--* LT int N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int N003 ( 3, 4) [001066] ----------- | \--* LSH int N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void N001 ( 0, 0) [002675] ----------- +--* NOP void N002 ( 0, 0) [002678] ----------- \--* NOP void ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 5, 6) [001590] ----------- * JTRUE void N003 ( 3, 4) [001589] J------N--- \--* NE int N001 ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [001588] ----------- \--* CNS_INT ref null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002685] -A------R-- \--* ASG int N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 N003 ( 3, 4) [002691] -----O----- \--* ADD byref N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 N003 ( 0, 0) [003314] ----------- \--* PHI byref N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 N003 ( 0, 0) [003311] ----------- \--* PHI int N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void N003 ( 1, 3) [002695] -A------R-- +--* ASG byref N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) N004 ( 0, 0) [002698] ----------- \--* NOP void ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void N003 ( 3, 3) [001628] N------N-U- \--* GT int N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void N001 ( 0, 0) [002704] ----------- +--* NOP void N002 ( 0, 0) [002707] ----------- \--* NOP void ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 5, 6) [001702] ----------- * JTRUE void N003 ( 3, 4) [001701] J------N--- \--* NE int N001 ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [001700] ----------- \--* CNS_INT ref null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002714] -A------R-- \--* ASG int N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 N003 ( 3, 4) [002720] -----O----- \--* ADD byref N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 N003 ( 0, 0) [003308] ----------- \--* PHI int N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 N003 ( 0, 0) [003305] ----------- \--* PHI byref N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) N006 ( 1, 3) [002727] -A------R-- \--* ASG int N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 N003 ( 0, 0) [003296] ----------- \--* PHI byref N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 N003 ( 0, 0) [003287] ----------- \--* PHI int N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 N008 ( 4, 6) [001032] ----------- | \--* LSH long N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 N003 ( 3, 4) [001052] ----------- \--* ADD int N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 N011 ( 4, 6) [002736] ----------- \--* LSH long N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 N003 ( 0, 0) [003281] ----------- \--* PHI int N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 N003 ( 0, 0) [003275] ----------- \--* PHI int N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 N003 ( 3, 3) [001047] ----------- \--* ADD int N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void N003 ( 3, 3) [001004] J------N--- \--* GT int N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 N004 ( 0, 0) [003317] ----------- \--* PHI int N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 N004 ( 0, 0) [003299] ----------- \--* PHI byref N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 N004 ( 0, 0) [003290] ----------- \--* PHI int N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void N003 ( 3, 4) [000929] J------N--- \--* NE int N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V15 loc11 u:2 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 N003 ( 3, 4) [002760] -----O----- \--* ADD byref N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int N007 ( 4, 3) [001780] D--XG--N--- +--* IND int N006 ( 3, 4) [002779] -------N--- | \--* ADD byref N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 3, 4) [002788] -A--------- * COMMA void N003 ( 3, 4) [002784] -A------R-- +--* ASG byref N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N004 ( 0, 0) [002787] ----------- \--* NOP void ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 N005 ( 2, 4) [002793] -A--------- \--* COMMA long N003 ( 1, 3) [002790] -A------R-- +--* ASG long N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void N003 ( 3, 4) [000273] J------N--- \--* LE int N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N005 ( 8, 8) [000834] ---XG------ * JTRUE void N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 N003 ( 3, 4) [000844] ----------- \--* ADD long N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V36 loc32 u:7 (last use) N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) ***** BB120 STMT00183 ( ??? ... ??? ) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 N003 ( 0, 0) [003263] ----------- \--* PHI long N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 N003 ( 0, 0) [003260] ----------- \--* PHI int N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 N003 ( 0, 0) [003257] ----------- \--* PHI byref N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V62 tmp22 u:1 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V62 tmp22 u:1 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 N003 ( 3, 4) [002805] -----O----- \--* ADD byref N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 u:1 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int N007 ( 4, 3) [001833] D--XG--N--- +--* IND int N006 ( 3, 4) [002811] -------N--- | \--* ADD byref N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V62 tmp22 u:1 (last use) N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V62 tmp22 u:1 (last use) N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void N003 ( 3, 4) [000862] J------N--- \--* EQ int N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void N003 ( 3, 4) [000876] J------N--- \--* LE int N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void N003 ( 3, 4) [000880] J------N--- \--* LT int N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 N008 ( 4, 6) [000893] ----------- | | \--* LSH long N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 N003 ( 3, 4) [002827] -----O----- \--* ADD byref N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int N007 ( 4, 3) [001893] D--XG--N--- +--* IND int N006 ( 3, 4) [002846] -------N--- | \--* ADD byref N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 N003 ( 3, 4) [000909] ----------- \--* ADD int N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 N003 ( 0, 0) [003248] ----------- \--* PHI int N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 N003 ( 3, 4) [000866] ----------- \--* ADD int N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 N003 ( 3, 4) [000871] ----------- \--* ADD int N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 N003 ( 0, 0) [003266] ----------- \--* PHI long N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 N003 ( 0, 0) [003251] ----------- \--* PHI int N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 N003 ( 0, 0) [003242] ----------- \--* PHI int N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 N003 ( 0, 0) [003236] ----------- \--* PHI int N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void N003 ( 3, 4) [000827] J------N--- \--* GT int N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 N003 ( 0, 0) [003269] ----------- \--* PHI long N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 N003 ( 0, 0) [003254] ----------- \--* PHI int N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 N003 ( 0, 0) [003245] ----------- \--* PHI int N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 N003 ( 0, 0) [003239] ----------- \--* PHI int N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void N003 ( 3, 4) [000641] J------N--- \--* GE int N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 N003 ( 3, 4) [000733] ----------- \--* ADD int N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void N003 ( 3, 3) [000738] J------N--- \--* LE int N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 N003 ( 0, 0) [003182] ----------- \--* PHI int N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void N003 ( 3, 3) [000721] J------N--- \--* GT int N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 N003 ( 3, 4) [000652] ----------- \--* ADD long N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V36 loc32 u:3 (last use) N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 N003 ( 0, 0) [003194] ----------- \--* PHI long N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 N004 ( 0, 0) [003191] ----------- \--* PHI int N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 N003 ( 0, 0) [003197] ----------- \--* PHI long N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 N003 ( 0, 0) [003185] ----------- \--* PHI int N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 N003 ( 0, 0) [003179] ----------- \--* PHI ushort N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void N003 ( 3, 4) [000667] J------N--- \--* EQ int N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 N003 ( 3, 4) [002863] -----O----- \--* ADD byref N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int N007 ( 4, 3) [001938] D--XG--N--- +--* IND int N006 ( 3, 4) [002869] -------N--- | \--* ADD byref N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void N003 ( 3, 4) [000679] J------N--- \--* EQ int N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void N003 ( 3, 4) [000683] J------N--- \--* LE int N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void N003 ( 3, 4) [000687] J------N--- \--* LT int N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 N008 ( 4, 6) [000700] ----------- | | \--* LSH long N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 N003 ( 3, 4) [002885] -----O----- \--* ADD byref N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int N007 ( 4, 3) [001996] D--XG--N--- +--* IND int N006 ( 3, 4) [002904] -------N--- | \--* ADD byref N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 N003 ( 3, 4) [000716] ----------- \--* ADD int N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 N003 ( 0, 0) [003173] ----------- \--* PHI int N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 N003 ( 3, 4) [000671] ----------- \--* ADD int N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void N007 ( 10, 9) [000611] J------N--- \--* NE int N005 ( 8, 6) [000609] ----------- +--* OR int N003 ( 6, 4) [000607] ----------- | +--* NE int N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void N003 ( 3, 4) [000615] J------N--- \--* LT int N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void N003 ( 3, 3) [000627] J------N--- \--* GE int N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 N003 ( 3, 4) [002919] -----O----- \--* ADD byref N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int N007 ( 4, 3) [002056] D--XG--N--- +--* IND int N006 ( 3, 4) [002938] -------N--- | \--* ADD byref N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 N003 ( 3, 4) [002952] -----O----- \--* ADD byref N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int N007 ( 4, 3) [002116] D--XG--N--- +--* IND int N006 ( 3, 4) [002971] -------N--- | \--* ADD byref N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 N003 ( 3, 4) [002986] -----O----- \--* ADD byref N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int N007 ( 4, 3) [002176] D--XG--N--- +--* IND int N006 ( 3, 4) [003005] -------N--- | \--* ADD byref N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 N003 ( 3, 4) [000808] ----------- \--* ADD int N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 ***** BB191 STMT00449 ( ??? ... ??? ) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000817] ----------- \--* LSH long N003 ( 2, 3) [000814] ----------- +--* CAST long <- int N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 N003 ( 3, 4) [003018] -----O----- \--* ADD byref N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int N007 ( 4, 3) [002222] D--XG--N--- +--* IND int N006 ( 3, 4) [003024] -------N--- | \--* ADD byref N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 N003 ( 0, 0) [003167] ----------- \--* PHI int N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 7, 8) [000757] ----------- * JTRUE void N003 ( 5, 6) [000756] J------N--- \--* GE int N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N010 ( 13, 15) [000791] ---XG------ * JTRUE void N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000786] ----------- | \--* LSH long N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N010 ( 13, 14) [000802] ---XG------ * JTRUE void N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000797] ----------- | \--* LSH long N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 7, 8) [000764] ----------- * JTRUE void N003 ( 5, 6) [000763] J------N--- \--* GE int N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N010 ( 13, 15) [000775] ---XG------ * JTRUE void N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000770] ----------- | \--* LSH long N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 N003 ( 3, 4) [000778] ----------- \--* ADD int N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 7, 8) [000289] ----------- * JTRUE void N003 ( 5, 6) [000288] J------N--- \--* GE int N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N010 ( 13, 15) [000300] ---XG------ * JTRUE void N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000295] ----------- | \--* LSH long N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 N003 ( 3, 4) [000306] ----------- \--* ADD int N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 ***** BB202 STMT00458 ( ??? ... ??? ) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000315] ----------- \--* LSH long N003 ( 2, 3) [000312] ----------- +--* CAST long <- int N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 N003 ( 3, 4) [003037] -----O----- \--* ADD byref N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int N007 ( 4, 3) [002280] D--XG--N--- +--* IND int N006 ( 3, 4) [003043] -------N--- | \--* ADD byref N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void N003 ( 3, 4) [000331] J------N--- \--* EQ int N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 7, 8) [000425] ----------- * JTRUE void N003 ( 5, 6) [000424] J------N--- \--* GE int N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N010 ( 13, 15) [000575] ---XG------ * JTRUE void N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000570] ----------- | \--* LSH long N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 9, 11) [000434] ----------- * JTRUE void N005 ( 7, 9) [000433] J------N--- \--* GE int N003 ( 3, 4) [000428] ----------- +--* ADD int N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N010 ( 13, 15) [000548] ---XG------ * JTRUE void N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000543] ----------- | \--* LSH long N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 N007 ( 6, 9) [000556] ----------- | \--* LSH long N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int N004 ( 3, 4) [000552] ----------- | | \--* ADD int N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) N006 ( 9, 11) [000443] ----------- * JTRUE void N005 ( 7, 9) [000442] J------N--- \--* GE int N003 ( 3, 4) [000437] ----------- +--* ADD int N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N010 ( 13, 15) [000457] ---XG------ * JTRUE void N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000452] ----------- | \--* LSH long N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 N007 ( 6, 9) [000465] ----------- | \--* LSH long N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int N004 ( 3, 4) [000461] ----------- | | \--* ADD int N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 N003 ( 3, 4) [003058] -----O----- \--* ADD byref N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int N007 ( 4, 3) [002337] D--XG--N--- +--* IND int N006 ( 3, 4) [003064] -------N--- | \--* ADD byref N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 N003 ( 0, 0) [003230] ----------- \--* PHI bool N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 N003 ( 0, 0) [003221] ----------- \--* PHI int N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 N003 ( 0, 0) [003218] ----------- \--* PHI int N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 N003 ( 3, 4) [000535] ----------- \--* ADD int N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 N004 ( 0, 0) [003227] ----------- \--* PHI bool N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 N003 ( 0, 0) [003224] ----------- \--* PHI int N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 N003 ( 0, 0) [003215] ----------- \--* PHI int N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 N003 ( 3, 4) [000473] ----------- \--* ADD int N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 7, 8) [000485] ----------- * JTRUE void N003 ( 5, 6) [000484] J------N--- \--* GE int N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V54 tmp14 u:1 (last use) N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000527] ----------- | \--* LSH long N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void N003 ( 3, 4) [000488] J------N--- \--* LE int N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 N003 ( 0, 0) [003212] ----------- \--* PHI int N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 N003 ( 0, 0) [003209] ----------- \--* PHI int N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 N003 ( 3, 4) [003081] -----O----- \--* ADD byref N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int N007 ( 4, 3) [002384] D--XG--N--- +--* IND int N006 ( 3, 4) [003087] -------N--- | \--* ADD byref N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 7, 8) [000342] ----------- * JTRUE void N003 ( 5, 6) [000341] J------N--- \--* GE int N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N010 ( 13, 15) [000353] ---XG------ * JTRUE void N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000348] ----------- | \--* LSH long N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N010 ( 13, 15) [000418] ---XG------ * JTRUE void N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000413] ----------- | \--* LSH long N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 N003 ( 3, 4) [000359] ----------- \--* ADD int N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 ***** BB233 STMT00483 ( ??? ... ??? ) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000368] ----------- \--* LSH long N003 ( 2, 3) [000365] ----------- +--* CAST long <- int N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 N003 ( 3, 4) [003100] -----O----- \--* ADD byref N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int N007 ( 4, 3) [002432] D--XG--N--- +--* IND int N006 ( 3, 4) [003106] -------N--- | \--* ADD byref N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 N003 ( 3, 4) [000395] ----------- \--* ADD int N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V16 loc12 u:6 (last use) N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 ***** BB236 STMT00492 ( ??? ... ??? ) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000404] ----------- \--* LSH long N003 ( 2, 3) [000401] ----------- +--* CAST long <- int N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 N003 ( 3, 4) [003119] -----O----- \--* ADD byref N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int N007 ( 4, 3) [002478] D--XG--N--- +--* IND int N006 ( 3, 4) [003125] -------N--- | \--* ADD byref N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 N004 ( 0, 0) [003233] ----------- \--* PHI int N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 7, 8) [000378] ----------- * JTRUE void N003 ( 5, 6) [000377] J------N--- \--* GE int N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N010 ( 13, 15) [000389] ---XG------ * JTRUE void N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000384] ----------- | \--* LSH long N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 N003 ( 3, 4) [003138] -----O----- \--* ADD byref N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int N007 ( 4, 3) [002527] D--XG--N--- +--* IND int N006 ( 3, 4) [003144] -------N--- | \--* ADD byref N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 N004 ( 0, 0) [003206] ----------- \--* PHI bool N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 N004 ( 0, 0) [003203] ----------- \--* PHI bool N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 N004 ( 0, 0) [003200] ----------- \--* PHI long N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 N004 ( 0, 0) [003188] ----------- \--* PHI int N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 N004 ( 0, 0) [003176] ----------- \--* PHI int N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 N004 ( 0, 0) [003170] ----------- \--* PHI int N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 N008 ( 0, 0) [003164] ----------- \--* PHI int N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 7, 8) [000210] ----------- * JTRUE void N003 ( 5, 6) [000209] J------N--- \--* GE int N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 N003 ( 3, 4) [000246] ----------- \--* ADD int N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V16 loc12 u:4 (last use) N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000255] ----------- \--* LSH long N003 ( 2, 3) [000252] ----------- +--* CAST long <- int N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V50 tmp10 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void N003 ( 3, 4) [000223] J------N--- \--* NE int N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [info] NumUses overestimated for V00.1: IR 73 SSA 101 [info] NumUses overestimated for V01.1: IR 17 SSA 21 [info] NumUses overestimated for V33.1: IR 6 SSA 10 [info] NumUses overestimated for V62.1: IR 5 SSA 7 SSA checks completed successfully *************** In fgDebugCheckLoopTable *************** Starting PHASE Do value numbering *************** In fgValueNumber() optComputeLoopNestSideEffects for L00 optComputeLoopSideEffectsOfBlock BB07, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB08, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB09, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB10, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB11, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB12, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB13, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB14, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB15, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB16, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB17, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB18, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB19, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB20, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB21, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB22, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB23, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB24, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB25, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB26, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB27, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB28, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB29, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB30, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB31, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB32, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB33, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB34, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB35, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB36, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB37, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB38, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB39, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB40, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB41, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB42, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB43, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB44, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB45, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB46, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB47, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB48, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB49, mostNestedLoop 1 optComputeLoopSideEffectsOfBlock BB50, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB51, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB52, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB53, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB54, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB55, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB56, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB57, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB58, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB59, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB60, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB61, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB62, mostNestedLoop 0 optComputeLoopNestSideEffects for L02 optComputeLoopSideEffectsOfBlock BB89, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB90, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB91, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB92, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB93, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB94, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB95, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB96, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB97, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB98, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB99, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB100, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB101, mostNestedLoop 2 optComputeLoopSideEffectsOfBlock BB102, mostNestedLoop 2 optComputeLoopNestSideEffects for L03 optComputeLoopSideEffectsOfBlock BB113, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB114, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB115, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB116, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB117, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB118, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB119, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB120, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB121, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB122, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB123, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB124, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB125, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB126, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB127, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB128, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB129, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB130, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB131, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB132, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB133, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB134, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB135, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB136, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB137, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB138, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB139, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB140, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB141, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB142, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB143, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB144, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB145, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB146, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB147, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB148, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB149, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB150, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB151, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB152, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB153, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB154, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB155, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB156, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB157, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB158, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB159, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB160, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB161, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB162, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB163, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB164, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB165, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB166, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB167, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB168, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB169, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB170, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB171, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB172, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB173, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB174, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB175, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB176, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB177, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB178, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB179, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB180, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB181, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB182, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB183, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB184, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB185, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB186, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB187, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB188, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB189, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB190, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB191, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB192, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB193, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB194, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB195, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB196, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB197, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB198, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB199, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB200, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB201, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB202, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB203, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB204, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB205, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB206, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB207, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB208, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB209, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB210, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB211, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB212, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB213, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB214, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB215, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB216, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB217, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB218, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB219, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB220, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB221, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB222, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB223, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB224, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB225, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB226, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB227, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB228, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB229, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB230, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB231, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB232, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB233, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB234, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB235, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB236, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB237, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB238, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB239, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB240, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB241, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB242, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB243, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB244, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB245, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB246, mostNestedLoop 3 optComputeLoopSideEffectsOfBlock BB247, mostNestedLoop 3 Memory Initial Value in BB01 is: $1c0 The SSA definition for ByrefExposed (#1) at start of BB01 is $1c0 {InitVal($c4)} The SSA definition for GcHeap (#1) at start of BB01 is $1c0 {InitVal($c4)} ***** BB01, STMT00000(before) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn N001 [000000] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002543] CNS_INT(h) 0x400000000046ac80 ftn => $42 {Hnd const: 0x400000000046AC80} fgCurMemoryVN[GcHeap] assigned for CALL at [000001] to VN: $1c1. N003 [000001] CALL r2r_ind => $VN.Void ***** BB01, STMT00000(after) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 --------- ***** BB01, STMT00001(before) N003 ( 1, 3) [000004] -A------R-- * ASG int N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 N001 [000002] CNS_INT 0 => $c0 {IntCns 0} N002 [000003] LCL_VAR V11 loc7 d:1 => $VN.Void Tree [000004] assigned VN to local var V11/1: $c0 {IntCns 0} N003 [000004] ASG => $VN.Void ***** BB01, STMT00001(after) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB01, STMT00320(before) N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 N003 ( 3, 4) [002548] -----O----- \--* ADD byref N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 N001 [002546] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002547] CNS_INT 16 => $200 {LngCns: 16} N003 [002548] ADD => $240 {ADD($101, $200)} N004 [001499] LCL_VAR V76 tmp36 d:1 => $VN.Void Tree [001500] assigned VN to local var V76/1: $240 {ADD($101, $200)} N005 [001500] ASG => $VN.Void ***** BB01, STMT00320(after) N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 --------- ***** BB01, STMT00003(before) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 N001 [001497] CNS_INT 0 => $c0 {IntCns 0} N002 [001502] LCL_VAR V76 tmp36 u:1 => $240 {ADD($101, $200)} N003 [002555] CNS_INT 8 => $201 {LngCns: 8} N004 [002556] ADD => $241 {ADD($201, $240)} N005 [001503] IND => N006 [001504] BOUNDS_CHECK_Rng => N007 [001501] LCL_VAR V76 tmp36 u:1 (last use) => $240 {ADD($101, $200)} N008 [001505] IND => N009 [001507] COMMA => N010 [002550] LCL_VAR V167 tmp127 d:1 => $VN.Void Tree [002551] assigned VN to local var V167/1: N011 [002551] ASG => N012 [002552] LCL_VAR V167 tmp127 u:1 => N013 [002554] COMMA => N014 [000008] LCL_VAR V17 loc13 d:1 => $VN.Void Tree [000009] assigned VN to local var V17/1: N015 [000009] ASG => ***** BB01, STMT00003(after) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 --------- ***** BB01, STMT00005(before) N007 ( 14, 14) [002563] -A--------- * COMMA void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N006 ( 7, 7) [002562] -A------R-- \--* ASG int N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] VNForLoad: VNForMapPhysicalSelect($140, [0:7]):byref returns $246 {$140[$202]} VNForLoad: VNForMapPhysicalSelect($140, [0:7]):byref returns $246 {$140[$202]} N001 [002558] LCL_FLD V02 arg2 u:1[+0] => $246 {$140[$202]} N002 [002557] LCL_VAR V147 tmp107 d:1 => $VN.Void Tree [002559] assigned VN to local var V147/1: $246 {$140[$202]} N003 [002559] ASG => $VN.Void VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N004 [002561] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N005 [002560] LCL_VAR V148 tmp108 d:1 => $VN.Void Tree [002562] assigned VN to local var V148/1: $342 {$140[$203]} N006 [002562] ASG => $VN.Void N007 [002563] COMMA => $VN.Void ***** BB01, STMT00005(after) N007 ( 14, 14) [002563] -A--------- * COMMA void $VN.Void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N006 ( 7, 7) [002562] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 --------- ***** BB01, STMT00004(before) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V167 tmp127 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 N001 [000011] LCL_VAR V167 tmp127 u:1 (last use) => N002 [000012] IND => N003 [000013] CNS_INT 0 => $c0 {IntCns 0} N004 [000014] EQ => N005 [000015] JTRUE => ***** BB01, STMT00004(after) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V167 tmp127 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. Succ(BB05). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB05 is $1c1 {MemOpaque:NotInLoop} The SSA definition for GcHeap (#2) at start of BB05 is $1c1 {MemOpaque:NotInLoop} ***** BB05, STMT00006(before) N007 ( 14, 10) [002593] -A--------- * COMMA void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) N006 ( 7, 5) [002592] -A------R-- \--* ASG int N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) N001 [002588] LCL_VAR V147 tmp107 u:1 (last use) => $246 {$140[$202]} N002 [002587] LCL_VAR V149 tmp109 d:2 => $VN.Void Tree [002589] assigned VN to local var V149/2: $246 {$140[$202]} N003 [002589] ASG => $VN.Void N004 [002591] LCL_VAR V148 tmp108 u:1 (last use) => $342 {$140[$203]} N005 [002590] LCL_VAR V150 tmp110 d:2 => $VN.Void Tree [002592] assigned VN to local var V150/2: $342 {$140[$203]} N006 [002592] ASG => $VN.Void N007 [002593] COMMA => $VN.Void ***** BB05, STMT00006(after) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 --------- ***** BB05, STMT00007(before) N003 ( 5, 5) [000026] -A------R-- * ASG int N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 N001 [000021] CNS_INT 2 => $c2 {IntCns 2} N002 [000025] LCL_VAR V43 tmp3 d:2 => $VN.Void Tree [000026] assigned VN to local var V43/2: $c2 {IntCns 2} N003 [000026] ASG => $VN.Void ***** BB05, STMT00007(after) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 finish(BB05). Succ(BB06). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#2) at start of BB02 is $1c1 {MemOpaque:NotInLoop} The SSA definition for GcHeap (#2) at start of BB02 is $1c1 {MemOpaque:NotInLoop} ***** BB02, STMT00315(before) N007 ( 14, 10) [002570] -A--------- * COMMA void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) N006 ( 7, 5) [002569] -A------R-- \--* ASG int N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) N001 [002565] LCL_VAR V147 tmp107 u:1 (last use) => $246 {$140[$202]} N002 [002564] LCL_VAR V155 tmp115 d:1 => $VN.Void Tree [002566] assigned VN to local var V155/1: $246 {$140[$202]} N003 [002566] ASG => $VN.Void N004 [002568] LCL_VAR V148 tmp108 u:1 (last use) => $342 {$140[$203]} N005 [002567] LCL_VAR V156 tmp116 d:1 => $VN.Void Tree [002569] assigned VN to local var V156/1: $342 {$140[$203]} N006 [002569] ASG => $VN.Void N007 [002570] COMMA => $VN.Void ***** BB02, STMT00315(after) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 --------- ***** BB02, STMT00314(before) N007 ( 9, 9) [001476] ---XG------ * JTRUE void N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 N001 [001472] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002571] CNS_INT 8 => $201 {LngCns: 8} N003 [002572] ADD => $247 {ADD($101, $201)} N004 [001473] IND => N005 [001474] CNS_INT 0 => $c0 {IntCns 0} N006 [001475] NE => N007 [001476] JTRUE => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB02, STMT00314(after) N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 finish(BB02). Succ(BB03). Not yet completed. All preds complete, adding to allDone. Succ(BB04). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB04 is $1c1 {MemOpaque:NotInLoop} The SSA definition for GcHeap (#2) at start of BB04 is $1c1 {MemOpaque:NotInLoop} ***** BB04, STMT00316(before) N007 ( 14, 10) [002586] -A--------- * COMMA void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) N006 ( 7, 5) [002585] -A------R-- \--* ASG int N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) N001 [002581] LCL_VAR V155 tmp115 u:1 (last use) => $246 {$140[$202]} N002 [002580] LCL_VAR V149 tmp109 d:3 => $VN.Void Tree [002582] assigned VN to local var V149/3: $246 {$140[$202]} N003 [002582] ASG => $VN.Void N004 [002584] LCL_VAR V156 tmp116 u:1 (last use) => $342 {$140[$203]} N005 [002583] LCL_VAR V150 tmp110 d:3 => $VN.Void Tree [002585] assigned VN to local var V150/3: $342 {$140[$203]} N006 [002585] ASG => $VN.Void N007 [002586] COMMA => $VN.Void ***** BB04, STMT00316(after) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 --------- ***** BB04, STMT00317(before) N003 ( 5, 5) [001487] -A------R-- * ASG int N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 N001 [001482] CNS_INT 1 => $c1 {IntCns 1} N002 [001486] LCL_VAR V43 tmp3 d:3 => $VN.Void Tree [001487] assigned VN to local var V43/3: $c1 {IntCns 1} N003 [001487] ASG => $VN.Void ***** BB04, STMT00317(after) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 finish(BB04). Succ(BB06). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#2) at start of BB03 is $1c1 {MemOpaque:NotInLoop} The SSA definition for GcHeap (#2) at start of BB03 is $1c1 {MemOpaque:NotInLoop} ***** BB03, STMT00318(before) N007 ( 14, 10) [002579] -A--------- * COMMA void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) N006 ( 7, 5) [002578] -A------R-- \--* ASG int N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) N001 [002574] LCL_VAR V155 tmp115 u:1 (last use) => $246 {$140[$202]} N002 [002573] LCL_VAR V149 tmp109 d:4 => $VN.Void Tree [002575] assigned VN to local var V149/4: $246 {$140[$202]} N003 [002575] ASG => $VN.Void N004 [002577] LCL_VAR V156 tmp116 u:1 (last use) => $342 {$140[$203]} N005 [002576] LCL_VAR V150 tmp110 d:4 => $VN.Void Tree [002578] assigned VN to local var V150/4: $342 {$140[$203]} N006 [002578] ASG => $VN.Void N007 [002579] COMMA => $VN.Void ***** BB03, STMT00318(after) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 --------- ***** BB03, STMT00319(before) N003 ( 5, 5) [001494] -A------R-- * ASG int N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 N001 [001489] CNS_INT 0 => $c0 {IntCns 0} N002 [001493] LCL_VAR V43 tmp3 d:4 => $VN.Void Tree [001494] assigned VN to local var V43/4: $c0 {IntCns 0} N003 [001494] ASG => $VN.Void ***** BB03, STMT00319(after) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 finish(BB03). Succ(BB06). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 150/1 to $342 {$140[$203]} (all same). SSA PHI definition: set VN of local 43/1 to $281 {PhiDef($2b, $1, $34c)} . SSA PHI definition: set VN of local 149/1 to $246 {$140[$202]} (all same). The SSA definition for ByrefExposed (#2) at start of BB06 is $1c1 {MemOpaque:NotInLoop} The SSA definition for GcHeap (#2) at start of BB06 is $1c1 {MemOpaque:NotInLoop} ***** BB06, STMT00008(before) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn N001 [002596] LCL_VAR V149 tmp109 u:1 (last use) => $246 {$140[$202]} N002 [002597] LCL_VAR V150 tmp110 u:1 (last use) => $342 {$140[$203]} N003 [002595] FIELD_LIST => $141 {MemOpaque:NotInLoop} N004 [000029] LCL_VAR V43 tmp3 u:1 (last use) => $281 {PhiDef($2b, $1, $34c)} N005 [002594] CNS_INT(h) 0x40000000005401e8 ftn => $43 {Hnd const: 0x40000000005401E8} fgCurMemoryVN[GcHeap] assigned for CALL at [000030] to VN: $1c2. N006 [000030] CALL r2r_ind => $2c1 {MemOpaque:NotInLoop} N007 [000033] LCL_VAR V15 loc11 d:1 => $VN.Void Tree [000034] assigned VN to local var V15/1: $2c1 {MemOpaque:NotInLoop} N008 [000034] ASG => $VN.Void ***** BB06, STMT00008(after) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 finish(BB06). Succ(BB07). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. SSA PHI definition: set VN of local 11/2 to $282 {PhiDef($b, $2, $34d)} . SSA PHI definition: set VN of local 15/2 to $283 {PhiDef($f, $2, $34d)} . Computing GcHeap state for block BB07, entry block for loops 0 to 0: Loop 0 has memory havoc effect; heap state is new unique $1c3. The SSA definition for GcHeap (#4) at start of BB07 is $1c3 {MemOpaque:L00} ***** BB07, STMT00009(before) N003 ( 1, 3) [000037] -A------R-- * ASG int N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 N001 [000035] CNS_INT 0 => $c0 {IntCns 0} N002 [000036] LCL_VAR V04 loc0 d:1 => $VN.Void Tree [000037] assigned VN to local var V04/1: $c0 {IntCns 0} N003 [000037] ASG => $VN.Void ***** BB07, STMT00009(after) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB07, STMT00010(before) N003 ( 1, 3) [000040] -A------R-- * ASG int N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 N001 [000038] CNS_INT -1 => $c4 {IntCns 4294967295} N002 [000039] LCL_VAR V05 loc1 d:1 => $VN.Void Tree [000040] assigned VN to local var V05/1: $c4 {IntCns 4294967295} N003 [000040] ASG => $VN.Void ***** BB07, STMT00010(after) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 --------- ***** BB07, STMT00011(before) N003 ( 1, 4) [000043] -A------R-- * ASG int N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF N001 [000041] CNS_INT 0x7FFFFFFF => $c9 {IntCns 0x7FFFFFFF} N002 [000042] LCL_VAR V06 loc2 d:1 => $VN.Void Tree [000043] assigned VN to local var V06/1: $c9 {IntCns 0x7FFFFFFF} N003 [000043] ASG => $VN.Void ***** BB07, STMT00011(after) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 --------- ***** BB07, STMT00012(before) N003 ( 1, 3) [000046] -A------R-- * ASG int N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 N001 [000044] CNS_INT 0 => $c0 {IntCns 0} N002 [000045] LCL_VAR V07 loc3 d:1 => $VN.Void Tree [000046] assigned VN to local var V07/1: $c0 {IntCns 0} N003 [000046] ASG => $VN.Void ***** BB07, STMT00012(after) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB07, STMT00013(before) N003 ( 1, 3) [000049] -A------R-- * ASG int N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 N001 [002598] CNS_INT 0 => $c0 {IntCns 0} N002 [000048] LCL_VAR V09 loc5 d:1 => $VN.Void Tree [000049] assigned VN to local var V09/1: $c0 {IntCns 0} N003 [000049] ASG => $VN.Void ***** BB07, STMT00013(after) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB07, STMT00014(before) N003 ( 1, 3) [000052] -A------R-- * ASG int N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 N001 [000050] CNS_INT -1 => $c4 {IntCns 4294967295} N002 [000051] LCL_VAR V10 loc6 d:1 => $VN.Void Tree [000052] assigned VN to local var V10/1: $c4 {IntCns 4294967295} N003 [000052] ASG => $VN.Void ***** BB07, STMT00014(after) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 --------- ***** BB07, STMT00015(before) N003 ( 1, 3) [000055] -A------R-- * ASG int N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 N001 [002599] CNS_INT 0 => $c0 {IntCns 0} N002 [000054] LCL_VAR V12 loc8 d:1 => $VN.Void Tree [000055] assigned VN to local var V12/1: $c0 {IntCns 0} N003 [000055] ASG => $VN.Void ***** BB07, STMT00015(after) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB07, STMT00016(before) N003 ( 1, 3) [000058] -A------R-- * ASG int N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 N001 [000056] CNS_INT 0 => $c0 {IntCns 0} N002 [000057] LCL_VAR V13 loc9 d:1 => $VN.Void Tree [000058] assigned VN to local var V13/1: $c0 {IntCns 0} N003 [000058] ASG => $VN.Void ***** BB07, STMT00016(after) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB07, STMT00017(before) N003 ( 1, 3) [000061] -A------R-- * ASG int N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 N001 [000059] LCL_VAR V15 loc11 u:2 => $283 {PhiDef($f, $2, $34d)} N002 [000060] LCL_VAR V16 loc12 d:1 => $VN.Void Tree [000061] assigned VN to local var V16/1: $283 {PhiDef($f, $2, $34d)} N003 [000061] ASG => $VN.Void ***** BB07, STMT00017(after) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 --------- ***** BB07, STMT00321(before) N005 ( 3, 4) [002606] -A--------- * COMMA void N003 ( 3, 4) [002602] -A------R-- +--* ASG byref N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N004 ( 0, 0) [002605] ----------- \--* NOP void VNForLoad: VNForMapPhysicalSelect($140, [0:7]):byref returns $246 {$140[$202]} VNForLoad: VNForMapPhysicalSelect($140, [0:7]):byref returns $246 {$140[$202]} N001 [002601] LCL_FLD V02 arg2 u:1[+0] => $246 {$140[$202]} N002 [002600] LCL_VAR V157 tmp117 d:1 => $VN.Void Tree [002602] assigned VN to local var V157/1: $246 {$140[$202]} N003 [002602] ASG => $VN.Void N004 [002605] NOP => $580 {MemOpaque:L00} N005 [002606] COMMA => $580 {MemOpaque:L00} ***** BB07, STMT00321(after) N005 ( 3, 4) [002606] -A--------- * COMMA void $580 N003 ( 3, 4) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 --------- ***** BB07, STMT00019(before) N003 ( 1, 3) [000068] -A------R-- * ASG byref N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 N001 [001512] LCL_VAR V157 tmp117 u:1 => $246 {$140[$202]} N002 [000067] LCL_VAR V23 loc19 => $VN.Void Tree [000068] assigns to non-address-taken local V23; excluded from SSA, so value not tracked N003 [000068] ASG => $VN.Void ***** BB07, STMT00019(after) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 --------- ***** BB07, STMT00020(before) N007 ( 2, 4) [000072] -A------R-- * ASG long N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 N005 ( 2, 4) [002611] -A--------- \--* COMMA long N003 ( 1, 3) [002608] -A------R-- +--* ASG long N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) N001 [000069] LCL_VAR V157 tmp117 u:1 (last use) => $246 {$140[$202]} N002 [002607] LCL_VAR V168 tmp128 d:1 => $VN.Void Tree [002608] assigned VN to local var V168/1: $3c4 {$246, long <- byref} N003 [002608] ASG => $VN.Void N004 [002609] LCL_VAR V168 tmp128 u:1 (last use) => $3c4 {$246, long <- byref} N005 [002611] COMMA => $3c4 {$246, long <- byref} N006 [000071] LCL_VAR V22 loc18 d:1 => $VN.Void Tree [000072] assigned VN to local var V22/1: $3c4 {$246, long <- byref} N007 [000072] ASG => $VN.Void ***** BB07, STMT00020(after) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 finish(BB07). Succ(BB47). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. SSA PHI definition: set VN of local 9/2 to $4c1 {PhiDef($9, $2, $543)} . SSA PHI definition: set VN of local 6/2 to $284 {PhiDef($6, $2, $34f)} . SSA PHI definition: set VN of local 7/2 to $285 {PhiDef($7, $2, $34f)} . SSA PHI definition: set VN of local 5/2 to $286 {PhiDef($5, $2, $351)} . SSA PHI definition: set VN of local 12/2 to $4c2 {PhiDef($c, $2, $351)} . SSA PHI definition: set VN of local 10/2 to $287 {PhiDef($a, $2, $353)} . SSA PHI definition: set VN of local 11/3 to $288 {PhiDef($b, $3, $356)} . SSA PHI definition: set VN of local 13/2 to $289 {PhiDef($d, $2, $359)} . SSA PHI definition: set VN of local 4/2 to $28a {PhiDef($4, $2, $35a)} . SSA PHI definition: set VN of local 16/2 to $28b {PhiDef($10, $2, $35f)} . The SSA definition for ByrefExposed (#4) at start of BB47 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB47 is $1c3 {MemOpaque:L00} ***** BB47, STMT00022(before) N004 ( 7, 8) [000079] ----------- * JTRUE void N003 ( 5, 6) [000078] J------N--- \--* GE int N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000073] LCL_VAR V16 loc12 u:2 => $28b {PhiDef($10, $2, $35f)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [001538] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000078] GE => $360 {GE($28b, $342)} N004 [000079] JTRUE => $VN.Void ***** BB47, STMT00022(after) N004 ( 7, 8) [000079] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB47). Succ(BB48). Not yet completed. All preds complete, adding to allDone. Succ(BB50). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB48 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB48 is $1c3 {MemOpaque:L00} ***** BB48, STMT00261(before) N003 ( 1, 3) [001205] -A------R-- * ASG int N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 N001 [001198] LCL_VAR V16 loc12 u:2 => $28b {PhiDef($10, $2, $35f)} N002 [001204] LCL_VAR V71 tmp31 d:1 => $VN.Void Tree [001205] assigned VN to local var V71/1: $28b {PhiDef($10, $2, $35f)} N003 [001205] ASG => $VN.Void ***** BB48, STMT00261(after) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b --------- ***** BB48, STMT00260(before) N005 ( 3, 4) [001203] -A------R-- * ASG int N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 N003 ( 3, 4) [001201] ----------- \--* ADD int N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V16 loc12 u:2 (last use) N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 N001 [001199] LCL_VAR V16 loc12 u:2 (last use) => $28b {PhiDef($10, $2, $35f)} N002 [001200] CNS_INT 1 => $c1 {IntCns 1} N003 [001201] ADD => $361 {ADD($c1, $28b)} N004 [001202] LCL_VAR V16 loc12 d:17 => $VN.Void Tree [001203] assigned VN to local var V16/17: $361 {ADD($c1, $28b)} N005 [001203] ASG => $VN.Void ***** BB48, STMT00260(after) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V16 loc12 u:2 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB48, STMT00262(before) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001210] ----------- \--* LSH long N003 ( 2, 3) [001207] ----------- +--* CAST long <- int N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 N001 [001197] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001206] LCL_VAR V71 tmp31 u:1 (last use) => $28b {PhiDef($10, $2, $35f)} N003 [001207] CAST => $3c5 {$28b, long <- int} N004 [001209] CNS_INT 1 => $204 {LngCns: 1} N005 [001210] LSH => $3c6 {LSH($3c5, $204)} N006 [001211] ADD => $3c7 {ADD($3c4, $3c6)} N007 [001212] IND => N008 [001213] LCL_VAR V72 tmp32 d:1 => $VN.Void Tree [001214] assigned VN to local var V72/1: N009 [001214] ASG => $30f {norm=$VN.Void, exc=$30e {NullPtrExc($3c7)}} ***** BB48, STMT00262(after) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 --------- ***** BB48, STMT00263(before) N003 ( 1, 3) [001218] -A------R-- * ASG int N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 N001 [001216] LCL_VAR V72 tmp32 u:1 => N002 [001217] LCL_VAR V18 loc14 d:5 => $VN.Void Tree [001218] assigned VN to local var V18/5: N003 [001218] ASG => $VN.Void ***** BB48, STMT00263(after) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 --------- ***** BB48, STMT00264(before) N004 ( 5, 6) [001221] ----------- * JTRUE void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V72 tmp32 u:1 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 N001 [001215] LCL_VAR V72 tmp32 u:1 (last use) => N002 [001219] CNS_INT 0 => $c0 {IntCns 0} N003 [001220] EQ => N004 [001221] JTRUE => $VN.Void ***** BB48, STMT00264(after) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V72 tmp32 u:1 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 finish(BB48). Succ(BB49). Not yet completed. All preds complete, adding to allDone. Succ(BB50). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#4) at start of BB49 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB49 is $1c3 {MemOpaque:L00} ***** BB49, STMT00265(before) N004 ( 5, 6) [001225] ----------- * JTRUE void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 N001 [001222] LCL_VAR V18 loc14 u:5 => N002 [001223] CNS_INT 59 => $d1 {IntCns 59} N003 [001224] NE => N004 [001225] JTRUE => $VN.Void ***** BB49, STMT00265(after) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 finish(BB49). Succ(BB50). Not yet completed. All preds complete, adding to allDone. Succ(BB08). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB08 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB08 is $1c3 {MemOpaque:L00} ***** BB08, STMT00266(before) N004 ( 5, 6) [001229] ----------- * JTRUE void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 N001 [001226] LCL_VAR V18 loc14 u:5 => N002 [001227] CNS_INT 69 => $d2 {IntCns 69} N003 [001228] GT => N004 [001229] JTRUE => $VN.Void ***** BB08, STMT00266(after) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 finish(BB08). Succ(BB09). Not yet completed. All preds complete, adding to allDone. Succ(BB13). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB13 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB13 is $1c3 {MemOpaque:L00} ***** BB13, STMT00267(before) N004 ( 5, 6) [001233] ----------- * JTRUE void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 N001 [001230] LCL_VAR V18 loc14 u:5 => N002 [001231] CNS_INT 92 => $d3 {IntCns 92} N003 [001232] EQ => N004 [001233] JTRUE => $VN.Void ***** BB13, STMT00267(after) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 finish(BB13). Succ(BB14). Not yet completed. All preds complete, adding to allDone. Succ(BB35). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB35 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB35 is $1c3 {MemOpaque:L00} ***** BB35, STMT00269(before) N004 ( 7, 8) [001240] ----------- * JTRUE void N003 ( 5, 6) [001239] J------N--- \--* GE int N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [001234] LCL_VAR V16 loc12 u:17 => $361 {ADD($c1, $28b)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [001522] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [001239] GE => $36c {GE($361, $342)} N004 [001240] JTRUE => $VN.Void ***** BB35, STMT00269(after) N004 ( 7, 8) [001240] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB35). Succ(BB36). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB36 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB36 is $1c3 {MemOpaque:L00} ***** BB36, STMT00270(before) N010 ( 13, 15) [001251] ---XG------ * JTRUE void N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001246] ----------- | \--* LSH long N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 N001 [001241] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001242] LCL_VAR V16 loc12 u:17 => $361 {ADD($c1, $28b)} N003 [001243] CAST => $3c8 {$361, long <- int} N004 [001245] CNS_INT 1 => $204 {LngCns: 1} N005 [001246] LSH => $3c9 {LSH($3c8, $204)} N006 [001247] ADD => $3ca {ADD($3c4, $3c9)} N007 [001248] IND => N008 [001249] CNS_INT 0 => $c0 {IntCns 0} N009 [001250] EQ => N010 [001251] JTRUE => $311 {norm=$VN.Void, exc=$310 {NullPtrExc($3ca)}} ***** BB36, STMT00270(after) N010 ( 13, 15) [001251] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 finish(BB36). Succ(BB37). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB37 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB37 is $1c3 {MemOpaque:L00} ***** BB37, STMT00271(before) N005 ( 3, 4) [001256] -A------R-- * ASG int N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 N003 ( 3, 4) [001254] ----------- \--* ADD int N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 N001 [001252] LCL_VAR V16 loc12 u:17 (last use) => $361 {ADD($c1, $28b)} N002 [001253] CNS_INT 1 => $c1 {IntCns 1} N003 [001254] ADD => $371 {ADD($c1, $361)} N004 [001255] LCL_VAR V16 loc12 d:20 => $VN.Void Tree [001256] assigned VN to local var V16/20: $371 {ADD($c1, $361)} N005 [001256] ASG => $VN.Void ***** BB37, STMT00271(after) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 finish(BB37). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB14 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB14 is $1c3 {MemOpaque:L00} ***** BB14, STMT00272(before) N004 ( 5, 6) [001260] ----------- * JTRUE void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 N001 [001257] LCL_VAR V18 loc14 u:5 => N002 [001258] CNS_INT 101 => $d4 {IntCns 101} N003 [001259] EQ => N004 [001260] JTRUE => $VN.Void ***** BB14, STMT00272(after) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 finish(BB14). Succ(BB15). Not yet completed. All preds complete, adding to allDone. Succ(BB38). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB15 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB15 is $1c3 {MemOpaque:L00} ***** BB15, STMT00287(before) N004 ( 5, 8) [001355] ----------- * JTRUE void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 N001 [001352] LCL_VAR V18 loc14 u:5 (last use) => N002 [001353] CNS_INT 0x2030 => $d5 {IntCns 0x2030} N003 [001354] NE => N004 [001355] JTRUE => $VN.Void ***** BB15, STMT00287(after) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 finish(BB15). Succ(BB16). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB16 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB16 is $1c3 {MemOpaque:L00} ***** BB16, STMT00288(before) N005 ( 3, 4) [001360] -A------R-- * ASG int N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 N003 ( 3, 4) [001358] ----------- \--* ADD int N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 N001 [001356] LCL_VAR V13 loc9 u:2 (last use) => $289 {PhiDef($d, $2, $359)} N002 [001357] CNS_INT 3 => $c3 {IntCns 3} N003 [001358] ADD => $376 {ADD($c3, $289)} N004 [001359] LCL_VAR V13 loc9 d:5 => $VN.Void Tree [001360] assigned VN to local var V13/5: $376 {ADD($c3, $289)} N005 [001360] ASG => $VN.Void ***** BB16, STMT00288(after) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 finish(BB16). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB09 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB09 is $1c3 {MemOpaque:L00} ***** BB09, STMT00289(before) N004 ( 13, 9) [001364] ----------- * SWITCH void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 N001 [001361] LCL_VAR V18 loc14 u:5 => N002 [001362] CNS_INT -34 => $d6 {IntCns 4294967262} N003 [001363] ADD => N004 [001364] SWITCH => $VN.Void ***** BB09, STMT00289(after) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 finish(BB09). Succ(BB31). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB17). Not yet completed. All preds complete, adding to allDone. Succ(BB47). Succ(BB30). Not yet completed. All preds complete, adding to allDone. Succ(BB10). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB10 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB10 is $1c3 {MemOpaque:L00} ***** BB10, STMT00290(before) N004 ( 13, 9) [001368] ----------- * SWITCH void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 N001 [001365] LCL_VAR V18 loc14 u:5 => N002 [001366] CNS_INT -44 => $d7 {IntCns 4294967252} N003 [001367] ADD => N004 [001368] SWITCH => $VN.Void ***** BB10, STMT00290(after) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 finish(BB10). Succ(BB23). Not yet completed. All preds complete, adding to allDone. Succ(BB47). Succ(BB21). Not yet completed. All preds complete, adding to allDone. Succ(BB18). Not yet completed. All preds complete, adding to allDone. Succ(BB11). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB11 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB11 is $1c3 {MemOpaque:L00} ***** BB11, STMT00291(before) N004 ( 5, 6) [001372] ----------- * JTRUE void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 N001 [001369] LCL_VAR V18 loc14 u:5 (last use) => N002 [001370] CNS_INT 69 => $d2 {IntCns 69} N003 [001371] EQ => N004 [001372] JTRUE => $VN.Void ***** BB11, STMT00291(after) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 finish(BB11). Succ(BB12). Not yet completed. All preds complete, adding to allDone. Succ(BB38). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB38 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB38 is $1c3 {MemOpaque:L00} ***** BB38, STMT00274(before) N004 ( 7, 8) [001267] ----------- * JTRUE void N003 ( 5, 6) [001266] J------N--- \--* GE int N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [001261] LCL_VAR V16 loc12 u:17 => $361 {ADD($c1, $28b)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [001526] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [001266] GE => $36c {GE($361, $342)} N004 [001267] JTRUE => $VN.Void ***** BB38, STMT00274(after) N004 ( 7, 8) [001267] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB38). Succ(BB39). Not yet completed. All preds complete, adding to allDone. Succ(BB40). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB39 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB39 is $1c3 {MemOpaque:L00} ***** BB39, STMT00286(before) N010 ( 13, 15) [001351] ---XG------ * JTRUE void N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001346] ----------- | \--* LSH long N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 N001 [001341] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001342] LCL_VAR V16 loc12 u:17 => $361 {ADD($c1, $28b)} N003 [001343] CAST => $3c8 {$361, long <- int} N004 [001345] CNS_INT 1 => $204 {LngCns: 1} N005 [001346] LSH => $3c9 {LSH($3c8, $204)} N006 [001347] ADD => $3ca {ADD($3c4, $3c9)} N007 [001348] IND => N008 [001349] CNS_INT 48 => $d8 {IntCns 48} N009 [001350] EQ => N010 [001351] JTRUE => $311 {norm=$VN.Void, exc=$310 {NullPtrExc($3ca)}} ***** BB39, STMT00286(after) N010 ( 13, 15) [001351] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 finish(BB39). Succ(BB40). Not yet completed. All preds complete, adding to allDone. Succ(BB44). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB40 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB40 is $1c3 {MemOpaque:L00} ***** BB40, STMT00276(before) N006 ( 9, 11) [001276] ----------- * JTRUE void N005 ( 7, 9) [001275] J------N--- \--* GE int N003 ( 3, 4) [001270] ----------- +--* ADD int N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [001268] LCL_VAR V16 loc12 u:17 => $361 {ADD($c1, $28b)} N002 [001269] CNS_INT 1 => $c1 {IntCns 1} N003 [001270] ADD => $371 {ADD($c1, $361)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N004 [001530] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N005 [001275] GE => $681 {GE($371, $342)} N006 [001276] JTRUE => $VN.Void ***** BB40, STMT00276(after) N006 ( 9, 11) [001276] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB40). Succ(BB41). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB41 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB41 is $1c3 {MemOpaque:L00} ***** BB41, STMT00277(before) N010 ( 13, 15) [001287] ---XG------ * JTRUE void N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001282] ----------- | \--* LSH long N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 N001 [001277] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001278] LCL_VAR V16 loc12 u:17 => $361 {ADD($c1, $28b)} N003 [001279] CAST => $3c8 {$361, long <- int} N004 [001281] CNS_INT 1 => $204 {LngCns: 1} N005 [001282] LSH => $3c9 {LSH($3c8, $204)} N006 [001283] ADD => $3ca {ADD($3c4, $3c9)} N007 [001284] IND => N008 [001285] CNS_INT 43 => $d9 {IntCns 43} N009 [001286] EQ => N010 [001287] JTRUE => $311 {norm=$VN.Void, exc=$310 {NullPtrExc($3ca)}} ***** BB41, STMT00277(after) N010 ( 13, 15) [001287] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 finish(BB41). Succ(BB42). Not yet completed. All preds complete, adding to allDone. Succ(BB43). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB42 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB42 is $1c3 {MemOpaque:L00} ***** BB42, STMT00285(before) N010 ( 13, 15) [001340] ---XG------ * JTRUE void N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001335] ----------- | \--* LSH long N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 N001 [001330] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001331] LCL_VAR V16 loc12 u:17 => $361 {ADD($c1, $28b)} N003 [001332] CAST => $3c8 {$361, long <- int} N004 [001334] CNS_INT 1 => $204 {LngCns: 1} N005 [001335] LSH => $3c9 {LSH($3c8, $204)} N006 [001336] ADD => $3ca {ADD($3c4, $3c9)} N007 [001337] IND => N008 [001338] CNS_INT 45 => $da {IntCns 45} N009 [001339] NE => N010 [001340] JTRUE => $311 {norm=$VN.Void, exc=$310 {NullPtrExc($3ca)}} ***** BB42, STMT00285(after) N010 ( 13, 15) [001340] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001335] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da finish(BB42). Succ(BB43). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB43 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB43 is $1c3 {MemOpaque:L00} ***** BB43, STMT00278(before) N012 ( 15, 18) [001300] ---XG------ * JTRUE void N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 N007 ( 6, 9) [001295] ----------- | \--* LSH long N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int N004 ( 3, 4) [001291] ----------- | | \--* ADD int N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 N001 [001288] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001289] LCL_VAR V16 loc12 u:17 => $361 {ADD($c1, $28b)} N003 [001290] CNS_INT 1 => $c1 {IntCns 1} N004 [001291] ADD => $371 {ADD($c1, $361)} N005 [001292] CAST => $3cb {$371, long <- int} N006 [001294] CNS_INT 1 => $204 {LngCns: 1} N007 [001295] LSH => $3cc {LSH($3cb, $204)} N008 [001296] ADD => $3cd {ADD($3c4, $3cc)} N009 [001297] IND => N010 [001298] CNS_INT 48 => $d8 {IntCns 48} N011 [001299] NE => N012 [001300] JTRUE => $313 {norm=$VN.Void, exc=$312 {NullPtrExc($3cd)}} ***** BB43, STMT00278(after) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 finish(BB43). Succ(BB44). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB12 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB12 is $1c3 {MemOpaque:L00} finish(BB12). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB18 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB18 is $1c3 {MemOpaque:L00} ***** BB18, STMT00292(before) N004 ( 5, 8) [001376] ----------- * JTRUE void N003 ( 3, 6) [001375] N------N-U- \--* NE int N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF N001 [001373] LCL_VAR V06 loc2 u:2 => $284 {PhiDef($6, $2, $34f)} N002 [001374] CNS_INT 0x7FFFFFFF => $c9 {IntCns 0x7FFFFFFF} N003 [001375] NE => $68e {NE($284, $c9)} N004 [001376] JTRUE => $VN.Void ***** BB18, STMT00292(after) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 finish(BB18). Succ(BB19). Not yet completed. All preds complete, adding to allDone. Succ(BB20). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB19 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB19 is $1c3 {MemOpaque:L00} ***** BB19, STMT00295(before) N003 ( 1, 3) [001387] -A------R-- * ASG int N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 N001 [001385] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N002 [001386] LCL_VAR V06 loc2 d:5 => $VN.Void Tree [001387] assigned VN to local var V06/5: $28a {PhiDef($4, $2, $35a)} N003 [001387] ASG => $VN.Void ***** BB19, STMT00295(after) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a finish(BB19). Succ(BB20). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 6/4 to $28c {PhiDef($6, $4, $350)} . The SSA definition for ByrefExposed (#4) at start of BB20 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB20 is $1c3 {MemOpaque:L00} ***** BB20, STMT00293(before) N005 ( 3, 4) [001381] -A------R-- * ASG int N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 N003 ( 3, 4) [001379] ----------- \--* ADD int N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 N001 [001377] LCL_VAR V04 loc0 u:2 (last use) => $28a {PhiDef($4, $2, $35a)} N002 [001378] CNS_INT 1 => $c1 {IntCns 1} N003 [001379] ADD => $68f {ADD($c1, $28a)} N004 [001380] LCL_VAR V04 loc0 d:4 => $VN.Void Tree [001381] assigned VN to local var V04/4: $68f {ADD($c1, $28a)} N005 [001381] ASG => $VN.Void ***** BB20, STMT00293(after) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB20, STMT00294(before) N003 ( 1, 3) [001384] -A------R-- * ASG int N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 N001 [001382] LCL_VAR V04 loc0 u:4 => $68f {ADD($c1, $28a)} N002 [001383] LCL_VAR V07 loc3 d:4 => $VN.Void Tree [001384] assigned VN to local var V07/4: $68f {ADD($c1, $28a)} N003 [001384] ASG => $VN.Void ***** BB20, STMT00294(after) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f finish(BB20). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB21 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB21 is $1c3 {MemOpaque:L00} ***** BB21, STMT00296(before) N004 ( 5, 6) [001391] ----------- * JTRUE void N003 ( 3, 4) [001390] J------N--- \--* GE int N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 N001 [001388] LCL_VAR V05 loc1 u:2 => $286 {PhiDef($5, $2, $351)} N002 [001389] CNS_INT 0 => $c0 {IntCns 0} N003 [001390] GE => $690 {GE($286, $c0)} N004 [001391] JTRUE => $VN.Void ***** BB21, STMT00296(after) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 finish(BB21). Succ(BB22). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB22 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB22 is $1c3 {MemOpaque:L00} ***** BB22, STMT00297(before) N003 ( 1, 3) [001394] -A------R-- * ASG int N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 N001 [001392] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N002 [001393] LCL_VAR V05 loc1 d:5 => $VN.Void Tree [001394] assigned VN to local var V05/5: $28a {PhiDef($4, $2, $35a)} N003 [001394] ASG => $VN.Void ***** BB22, STMT00297(after) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a finish(BB22). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB23 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB23 is $1c3 {MemOpaque:L00} ***** BB23, STMT00298(before) N004 ( 5, 6) [001398] ----------- * JTRUE void N003 ( 3, 4) [001397] J------N--- \--* LE int N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 N001 [001395] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N002 [001396] CNS_INT 0 => $c0 {IntCns 0} N003 [001397] LE => $691 {LE($28a, $c0)} N004 [001398] JTRUE => $VN.Void ***** BB23, STMT00298(after) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 finish(BB23). Succ(BB24). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB24 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB24 is $1c3 {MemOpaque:L00} ***** BB24, STMT00299(before) N004 ( 5, 6) [001402] ----------- * JTRUE void N003 ( 3, 4) [001401] J------N--- \--* GE int N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 N001 [001399] LCL_VAR V05 loc1 u:2 => $286 {PhiDef($5, $2, $351)} N002 [001400] CNS_INT 0 => $c0 {IntCns 0} N003 [001401] GE => $690 {GE($286, $c0)} N004 [001402] JTRUE => $VN.Void ***** BB24, STMT00299(after) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 finish(BB24). Succ(BB25). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB25 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB25 is $1c3 {MemOpaque:L00} ***** BB25, STMT00300(before) N004 ( 5, 6) [001406] ----------- * JTRUE void N003 ( 3, 4) [001405] J------N--- \--* LT int N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 N001 [001403] LCL_VAR V10 loc6 u:2 => $287 {PhiDef($a, $2, $353)} N002 [001404] CNS_INT 0 => $c0 {IntCns 0} N003 [001405] LT => $692 {LT($287, $c0)} N004 [001406] JTRUE => $VN.Void ***** BB25, STMT00300(after) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 finish(BB25). Succ(BB26). Not yet completed. All preds complete, adding to allDone. Succ(BB29). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB26 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB26 is $1c3 {MemOpaque:L00} ***** BB26, STMT00303(before) N004 ( 5, 5) [001416] ----------- * JTRUE void N003 ( 3, 3) [001415] N------N-U- \--* NE int N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 N001 [001413] LCL_VAR V10 loc6 u:2 => $287 {PhiDef($a, $2, $353)} N002 [001414] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N003 [001415] NE => $693 {NE($287, $28a)} N004 [001416] JTRUE => $VN.Void ***** BB26, STMT00303(after) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a finish(BB26). Succ(BB27). Not yet completed. All preds complete, adding to allDone. Succ(BB28). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB28 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB28 is $1c3 {MemOpaque:L00} ***** BB28, STMT00304(before) N003 ( 1, 3) [001419] -A------R-- * ASG int N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 N001 [002612] CNS_INT 1 => $c1 {IntCns 1} N002 [001418] LCL_VAR V12 loc8 d:6 => $VN.Void Tree [001419] assigned VN to local var V12/6: $c1 {IntCns 1} N003 [001419] ASG => $VN.Void ***** BB28, STMT00304(after) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 finish(BB28). Succ(BB29). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 12/5 to $4c3 {PhiDef($c, $5, $544)} . The SSA definition for ByrefExposed (#4) at start of BB29 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB29 is $1c3 {MemOpaque:L00} ***** BB29, STMT00301(before) N003 ( 1, 3) [001409] -A------R-- * ASG int N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 N001 [001407] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N002 [001408] LCL_VAR V10 loc6 d:3 => $VN.Void Tree [001409] assigned VN to local var V10/3: $28a {PhiDef($4, $2, $35a)} N003 [001409] ASG => $VN.Void ***** BB29, STMT00301(after) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a --------- ***** BB29, STMT00302(before) N003 ( 1, 3) [001412] -A------R-- * ASG int N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 N001 [001410] CNS_INT 1 => $c1 {IntCns 1} N002 [001411] LCL_VAR V11 loc7 d:4 => $VN.Void Tree [001412] assigned VN to local var V11/4: $c1 {IntCns 1} N003 [001412] ASG => $VN.Void ***** BB29, STMT00302(after) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 finish(BB29). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB27 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB27 is $1c3 {MemOpaque:L00} ***** BB27, STMT00305(before) N005 ( 3, 4) [001424] -A------R-- * ASG int N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 N003 ( 3, 4) [001422] ----------- \--* ADD int N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 N001 [001420] LCL_VAR V11 loc7 u:3 (last use) => $288 {PhiDef($b, $3, $356)} N002 [001421] CNS_INT 1 => $c1 {IntCns 1} N003 [001422] ADD => $694 {ADD($c1, $288)} N004 [001423] LCL_VAR V11 loc7 d:5 => $VN.Void Tree [001424] assigned VN to local var V11/5: $694 {ADD($c1, $288)} N005 [001424] ASG => $VN.Void ***** BB27, STMT00305(after) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 finish(BB27). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB30 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB30 is $1c3 {MemOpaque:L00} ***** BB30, STMT00306(before) N005 ( 3, 4) [001429] -A------R-- * ASG int N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 N003 ( 3, 4) [001427] ----------- \--* ADD int N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 N001 [001425] LCL_VAR V13 loc9 u:2 (last use) => $289 {PhiDef($d, $2, $359)} N002 [001426] CNS_INT 2 => $c2 {IntCns 2} N003 [001427] ADD => $695 {ADD($c2, $289)} N004 [001428] LCL_VAR V13 loc9 d:6 => $VN.Void Tree [001429] assigned VN to local var V13/6: $695 {ADD($c2, $289)} N005 [001429] ASG => $VN.Void ***** BB30, STMT00306(after) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 finish(BB30). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB17 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB17 is $1c3 {MemOpaque:L00} ***** BB17, STMT00307(before) N005 ( 3, 4) [001434] -A------R-- * ASG int N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 N003 ( 3, 4) [001432] ----------- \--* ADD int N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 N001 [001430] LCL_VAR V04 loc0 u:2 (last use) => $28a {PhiDef($4, $2, $35a)} N002 [001431] CNS_INT 1 => $c1 {IntCns 1} N003 [001432] ADD => $68f {ADD($c1, $28a)} N004 [001433] LCL_VAR V04 loc0 d:3 => $VN.Void Tree [001434] assigned VN to local var V04/3: $68f {ADD($c1, $28a)} N005 [001434] ASG => $VN.Void ***** BB17, STMT00307(after) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 finish(BB17). Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB50 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB50 is $1c3 {MemOpaque:L00} ***** BB50, STMT00023(before) N003 ( 1, 3) [000083] -A------R-- * ASG byref N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 N001 [000081] CNS_INT 0 => $205 {LngCns: 0} N002 [000082] LCL_VAR V23 loc19 => $VN.Void Tree [000083] assigns to non-address-taken local V23; excluded from SSA, so value not tracked N003 [000083] ASG => $VN.Void ***** BB50, STMT00023(after) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 --------- ***** BB50, STMT00024(before) N004 ( 5, 6) [000087] ----------- * JTRUE void N003 ( 3, 4) [000086] J------N--- \--* GE int N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 N001 [000084] LCL_VAR V05 loc1 u:2 => $286 {PhiDef($5, $2, $351)} N002 [000085] CNS_INT 0 => $c0 {IntCns 0} N003 [000086] GE => $690 {GE($286, $c0)} N004 [000087] JTRUE => $VN.Void ***** BB50, STMT00024(after) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 finish(BB50). Succ(BB51). Not yet completed. All preds complete, adding to allDone. Succ(BB52). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB51 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB51 is $1c3 {MemOpaque:L00} ***** BB51, STMT00259(before) N003 ( 1, 3) [001196] -A------R-- * ASG int N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 N001 [001194] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N002 [001195] LCL_VAR V05 loc1 d:4 => $VN.Void Tree [001196] assigned VN to local var V05/4: $28a {PhiDef($4, $2, $35a)} N003 [001196] ASG => $VN.Void ***** BB51, STMT00259(after) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a finish(BB51). Succ(BB52). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 5/3 to $28d {PhiDef($5, $3, $34e)} . The SSA definition for ByrefExposed (#4) at start of BB52 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB52 is $1c3 {MemOpaque:L00} ***** BB52, STMT00025(before) N004 ( 5, 6) [000091] ----------- * JTRUE void N003 ( 3, 4) [000090] J------N--- \--* LT int N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 N001 [000088] LCL_VAR V10 loc6 u:2 => $287 {PhiDef($a, $2, $353)} N002 [000089] CNS_INT 0 => $c0 {IntCns 0} N003 [000090] LT => $692 {LT($287, $c0)} N004 [000091] JTRUE => $VN.Void ***** BB52, STMT00025(after) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 finish(BB52). Succ(BB53). Not yet completed. All preds complete, adding to allDone. Succ(BB56). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB53 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB53 is $1c3 {MemOpaque:L00} ***** BB53, STMT00256(before) N004 ( 5, 5) [001183] ----------- * JTRUE void N003 ( 3, 3) [001182] N------N-U- \--* NE int N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [001180] LCL_VAR V10 loc6 u:2 (last use) => $287 {PhiDef($a, $2, $353)} N002 [001181] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N003 [001182] NE => $696 {NE($287, $28d)} N004 [001183] JTRUE => $VN.Void ***** BB53, STMT00256(after) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d finish(BB53). Succ(BB54). Not yet completed. All preds complete, adding to allDone. Succ(BB55). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB55 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB55 is $1c3 {MemOpaque:L00} ***** BB55, STMT00257(before) N003 ( 1, 3) [001186] -A------R-- * ASG int N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 N001 [002615] CNS_INT 1 => $c1 {IntCns 1} N002 [001185] LCL_VAR V12 loc8 d:4 => $VN.Void Tree [001186] assigned VN to local var V12/4: $c1 {IntCns 1} N003 [001186] ASG => $VN.Void ***** BB55, STMT00257(after) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 finish(BB55). Succ(BB56). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#4) at start of BB54 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB54 is $1c3 {MemOpaque:L00} ***** BB54, STMT00258(before) N007 ( 8, 8) [001193] -A------R-- * ASG int N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 N005 ( 8, 8) [001191] ----------- \--* SUB int N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) N004 ( 6, 6) [001190] ----------- \--* MUL int N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 N001 [001187] LCL_VAR V13 loc9 u:2 (last use) => $289 {PhiDef($d, $2, $359)} N002 [001188] LCL_VAR V11 loc7 u:3 => $288 {PhiDef($b, $3, $356)} N003 [001189] CNS_INT 3 => $c3 {IntCns 3} N004 [001190] MUL => $697 {MUL($c3, $288)} N005 [001191] SUB => $698 {SUB($289, $697)} N006 [001192] LCL_VAR V13 loc9 d:4 => $VN.Void Tree [001193] assigned VN to local var V13/4: $698 {SUB($289, $697)} N007 [001193] ASG => $VN.Void ***** BB54, STMT00258(after) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 finish(BB54). Succ(BB56). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 12/3 to $4c4 {PhiDef($c, $3, $34e)} . SSA PHI definition: set VN of local 13/3 to $28e {PhiDef($d, $3, $34e)} . The SSA definition for ByrefExposed (#4) at start of BB56 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB56 is $1c3 {MemOpaque:L00} ***** BB56, STMT00026(before) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 N001 [000092] LCL_VAR V17 loc13 u:1 => N002 [000093] IND => N003 [000094] CNS_INT 0 => $c0 {IntCns 0} N004 [000095] EQ => N005 [000096] JTRUE => ***** BB56, STMT00026(after) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 finish(BB56). Succ(BB57). Not yet completed. All preds complete, adding to allDone. Succ(BB63). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB63 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB63 is $1c3 {MemOpaque:L00} ***** BB63, STMT00027(before) N007 ( 9, 9) [000101] ---XG------ * JTRUE void N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 N001 [000097] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002629] CNS_INT 10 => $206 {LngCns: 10} N003 [002630] ADD => $249 {ADD($101, $206)} N004 [000098] IND => N005 [000099] CNS_INT 3 => $c3 {IntCns 3} N006 [000100] EQ => N007 [000101] JTRUE => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB63, STMT00027(after) N007 ( 9, 9) [000101] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 finish(BB63). Succ(BB64). Not yet completed. All preds complete, adding to allDone. Succ(BB65). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB64 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB64 is $1c3 {MemOpaque:L00} ***** BB64, STMT00244(before) N006 ( 7, 7) [001125] -A-XG------ * ASG bool N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool N003 ( 3, 4) [002632] -------N--- | \--* ADD byref N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 N001 [001122] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002631] CNS_INT 8 => $201 {LngCns: 8} N003 [002632] ADD => $247 {ADD($101, $201)} N004 [001124] IND => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} N005 [001123] CNS_INT 0 => $c0 {IntCns 0} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001125] to VN: $1c4. N006 [001125] ASG => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB64, STMT00244(after) N006 ( 7, 7) [001125] -A-XG------ * ASG bool $301 N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 finish(BB64). Succ(BB65). Not yet completed. All preds complete, adding to allDone. Building phi application: $d1 = SSA# 59. Building phi application: $c8 = SSA# 4. Building phi application: $6c0 = phi($c8, $d1). The SSA definition for GcHeap (#57) at start of BB65 is $6c1 {PhiMemoryDef($44, $6c0)} ***** BB65, STMT00028(before) N006 ( 6, 6) [000105] -A-XG------ * ASG int N004 ( 4, 3) [000104] D--XG--N--- +--* IND int N003 ( 3, 4) [002634] -------N--- | \--* ADD byref N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 N001 [000102] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002633] CNS_INT 4 => $207 {LngCns: 4} N003 [002634] ADD => $24a {ADD($101, $207)} N004 [000104] IND => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} N005 [000103] CNS_INT 0 => $c0 {IntCns 0} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000105] to VN: $1c5. N006 [000105] ASG => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB65, STMT00028(after) N006 ( 6, 6) [000105] -A-XG------ * ASG int $301 N004 ( 4, 3) [000104] D--XG--N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 finish(BB65). Succ(BB66). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB57 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB57 is $1c3 {MemOpaque:L00} ***** BB57, STMT00245(before) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 N003 ( 3, 4) [002620] -----O----- \--* ADD byref N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 N001 [002618] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002619] CNS_INT 4 => $207 {LngCns: 4} N003 [002620] ADD => $24a {ADD($101, $207)} N004 [001128] LCL_VAR V69 tmp29 d:1 => $VN.Void Tree [001129] assigned VN to local var V69/1: $24a {ADD($101, $207)} N005 [001129] ASG => $VN.Void ***** BB57, STMT00245(after) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 --------- ***** BB57, STMT00246(before) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int N006 ( 3, 2) [001135] D--XG--N--- +--* IND int N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) N001 [001131] LCL_VAR V69 tmp29 u:1 => $24a {ADD($101, $207)} N002 [001132] IND => N003 [001133] LCL_VAR V13 loc9 u:3 (last use) => $28e {PhiDef($d, $3, $34e)} N004 [001134] ADD => N005 [001130] LCL_VAR V69 tmp29 u:1 (last use) => $24a {ADD($101, $207)} N006 [001135] IND => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001136] to VN: $1c6. N007 [001136] ASG => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB57, STMT00246(after) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] D--XG--N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e --------- ***** BB57, STMT00247(before) N004 ( 5, 6) [001140] ----------- * JTRUE void N003 ( 3, 4) [001139] J------N--- \--* NE int N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 N001 [001137] LCL_VAR V09 loc5 u:2 => $4c1 {PhiDef($9, $2, $543)} N002 [001138] CNS_INT 0 => $c0 {IntCns 0} N003 [001139] NE => $6a7 {NE($4c1, $c0)} N004 [001140] JTRUE => $VN.Void ***** BB57, STMT00247(after) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 finish(BB57). Succ(BB58). Not yet completed. All preds complete, adding to allDone. Succ(BB59). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#60) at start of BB59 is $1c6 {MemOpaque:L00} The SSA definition for GcHeap (#60) at start of BB59 is $1c6 {MemOpaque:L00} ***** BB59, STMT00248(before) N003 ( 1, 3) [001143] -A------R-- * ASG int N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 N001 [001141] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N002 [001142] LCL_VAR V70 tmp30 d:2 => $VN.Void Tree [001143] assigned VN to local var V70/2: $28a {PhiDef($4, $2, $35a)} N003 [001143] ASG => $VN.Void ***** BB59, STMT00248(after) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a finish(BB59). Succ(BB60). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#60) at start of BB58 is $1c6 {MemOpaque:L00} The SSA definition for GcHeap (#60) at start of BB58 is $1c6 {MemOpaque:L00} ***** BB58, STMT00255(before) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [001171] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002622] CNS_INT 4 => $207 {LngCns: 4} N003 [002623] ADD => $24a {ADD($101, $207)} N004 [001172] IND => N005 [001173] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N006 [001174] ADD => N007 [001175] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N008 [001176] SUB => N009 [001177] LCL_VAR V70 tmp30 d:3 => $VN.Void Tree [001178] assigned VN to local var V70/3: N010 [001178] ASG => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB58, STMT00255(after) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d finish(BB58). Succ(BB60). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 70/1 to $291 {PhiDef($46, $1, $352)} . The SSA definition for ByrefExposed (#60) at start of BB60 is $1c6 {MemOpaque:L00} The SSA definition for GcHeap (#60) at start of BB60 is $1c6 {MemOpaque:L00} ***** BB60, STMT00250(before) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 N001 [001145] LCL_VAR V70 tmp30 u:1 (last use) => $291 {PhiDef($46, $1, $352)} N002 [001148] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N003 [002624] CNS_INT(h) 0x400000000046acb8 ftn => $45 {Hnd const: 0x400000000046ACB8} N004 [001150] CNS_INT 0 => $c0 {IntCns 0} fgCurMemoryVN[GcHeap] assigned for CALL at [001151] to VN: $1c7. N005 [001151] CALL r2r_ind => $VN.Void ***** BB60, STMT00250(after) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 --------- ***** BB60, STMT00251(before) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 N001 [001152] LCL_VAR V17 loc13 u:1 => N002 [001153] IND => N003 [001154] CNS_INT 0 => $c0 {IntCns 0} N004 [001155] NE => N005 [001156] JTRUE => ***** BB60, STMT00251(after) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 finish(BB60). Succ(BB61). Not yet completed. All preds complete, adding to allDone. Succ(BB66). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#61) at start of BB61 is $1c7 {MemOpaque:L00} The SSA definition for GcHeap (#61) at start of BB61 is $1c7 {MemOpaque:L00} ***** BB61, STMT00252(before) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 VNForLoad: VNForMapPhysicalSelect($140, [0:7]):byref returns $246 {$140[$202]} VNForLoad: VNForMapPhysicalSelect($140, [0:7]):byref returns $246 {$140[$202]} N001 [002627] LCL_FLD V02 arg2 u:1[+0] => $246 {$140[$202]} VNForLoad: VNForMapPhysicalSelect($140, [8:15]):long returns $3ce {$140[$208]} VNForLoad: VNForMapPhysicalSelect($140, [8:15]):long returns $3ce {$140[$208]} N002 [002628] LCL_FLD V02 arg2 u:1[+8] => $3ce {$140[$208]} N003 [002626] FIELD_LIST => $142 {MemOpaque:L00} N004 [002625] CNS_INT(h) 0x40000000005401e8 ftn => $43 {Hnd const: 0x40000000005401E8} N005 [001158] CNS_INT 2 => $c2 {IntCns 2} fgCurMemoryVN[GcHeap] assigned for CALL at [001159] to VN: $1c8. N006 [001159] CALL r2r_ind => $2c4 {MemOpaque:L00} N007 [001162] LCL_VAR V16 loc12 d:16 => $VN.Void Tree [001163] assigned VN to local var V16/16: $2c4 {MemOpaque:L00} N008 [001163] ASG => $VN.Void ***** BB61, STMT00252(after) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 --------- ***** BB61, STMT00253(before) N004 ( 5, 5) [001167] ----------- * JTRUE void N003 ( 3, 3) [001166] J------N--- \--* EQ int N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 N001 [001164] LCL_VAR V16 loc12 u:16 => $2c4 {MemOpaque:L00} N002 [001165] LCL_VAR V15 loc11 u:2 => $283 {PhiDef($f, $2, $34d)} N003 [001166] EQ => $6b6 {EQ($2c4, $283)} N004 [001167] JTRUE => $VN.Void ***** BB61, STMT00253(after) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 finish(BB61). Succ(BB62). Not yet completed. All preds complete, adding to allDone. Succ(BB66). Not yet completed. All preds complete, adding to allDone. Building phi application: $dc = SSA# 62. Building phi application: $dd = SSA# 61. Building phi application: $6c2 = phi($dd, $dc). Building phi application: $de = SSA# 58. Building phi application: $6c3 = phi($de, $6c2). The SSA definition for GcHeap (#5) at start of BB66 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB66, STMT00029(before) N004 ( 5, 5) [000109] ----------- * JTRUE void N003 ( 3, 3) [000108] J------N--- \--* LT int N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [000106] LCL_VAR V06 loc2 u:2 => $284 {PhiDef($6, $2, $34f)} N002 [000107] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N003 [000108] LT => $6b7 {LT($284, $28d)} N004 [000109] JTRUE => $VN.Void ***** BB66, STMT00029(after) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d finish(BB66). Succ(BB67). Not yet completed. All preds complete, adding to allDone. Succ(BB68). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#5) at start of BB68 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB68 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB68, STMT00030(before) N005 ( 7, 6) [000114] -A------R-- * ASG int N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 N003 ( 3, 3) [000112] ----------- \--* SUB int N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) N001 [000110] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N002 [000111] LCL_VAR V06 loc2 u:2 (last use) => $284 {PhiDef($6, $2, $34f)} N003 [000112] SUB => $6b8 {SUB($28d, $284)} N004 [000113] LCL_VAR V44 tmp4 d:2 => $VN.Void Tree [000114] assigned VN to local var V44/2: $6b8 {SUB($28d, $284)} N005 [000114] ASG => $VN.Void ***** BB68, STMT00030(after) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 finish(BB68). Succ(BB69). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB67 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB67 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB67, STMT00243(before) N003 ( 5, 5) [001120] -A------R-- * ASG int N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 N001 [001118] CNS_INT 0 => $c0 {IntCns 0} N002 [001119] LCL_VAR V44 tmp4 d:3 => $VN.Void Tree [001120] assigned VN to local var V44/3: $c0 {IntCns 0} N003 [001120] ASG => $VN.Void ***** BB67, STMT00243(after) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 finish(BB67). Succ(BB69). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 44/1 to $292 {PhiDef($2c, $1, $352)} . The SSA definition for ByrefExposed (#5) at start of BB69 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB69 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB69, STMT00031(before) N003 ( 3, 3) [000118] -A------R-- * ASG int N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) N001 [000116] LCL_VAR V44 tmp4 u:1 (last use) => $292 {PhiDef($2c, $1, $352)} N002 [000117] LCL_VAR V06 loc2 d:3 => $VN.Void Tree [000118] assigned VN to local var V06/3: $292 {PhiDef($2c, $1, $352)} N003 [000118] ASG => $VN.Void ***** BB69, STMT00031(after) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 --------- ***** BB69, STMT00032(before) N004 ( 5, 5) [000122] ----------- * JTRUE void N003 ( 3, 3) [000121] J------N--- \--* GT int N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [000119] LCL_VAR V07 loc3 u:2 => $285 {PhiDef($7, $2, $34f)} N002 [000120] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N003 [000121] GT => $6b9 {GT($285, $28d)} N004 [000122] JTRUE => $VN.Void ***** BB69, STMT00032(after) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d finish(BB69). Succ(BB70). Not yet completed. All preds complete, adding to allDone. Succ(BB71). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#5) at start of BB71 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB71 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB71, STMT00033(before) N005 ( 7, 6) [000127] -A------R-- * ASG int N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 N003 ( 3, 3) [000125] ----------- \--* SUB int N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) N001 [000123] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N002 [000124] LCL_VAR V07 loc3 u:2 (last use) => $285 {PhiDef($7, $2, $34f)} N003 [000125] SUB => $6ba {SUB($28d, $285)} N004 [000126] LCL_VAR V45 tmp5 d:2 => $VN.Void Tree [000127] assigned VN to local var V45/2: $6ba {SUB($28d, $285)} N005 [000127] ASG => $VN.Void ***** BB71, STMT00033(after) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 finish(BB71). Succ(BB72). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB70 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB70 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB70, STMT00242(before) N003 ( 5, 5) [001116] -A------R-- * ASG int N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 N001 [001114] CNS_INT 0 => $c0 {IntCns 0} N002 [001115] LCL_VAR V45 tmp5 d:3 => $VN.Void Tree [001116] assigned VN to local var V45/3: $c0 {IntCns 0} N003 [001116] ASG => $VN.Void ***** BB70, STMT00242(after) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 finish(BB70). Succ(BB72). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 45/1 to $293 {PhiDef($2d, $1, $352)} . The SSA definition for ByrefExposed (#5) at start of BB72 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB72 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB72, STMT00034(before) N003 ( 3, 3) [000131] -A------R-- * ASG int N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) N001 [000129] LCL_VAR V45 tmp5 u:1 (last use) => $293 {PhiDef($2d, $1, $352)} N002 [000130] LCL_VAR V07 loc3 d:3 => $VN.Void Tree [000131] assigned VN to local var V07/3: $293 {PhiDef($2d, $1, $352)} N003 [000131] ASG => $VN.Void ***** BB72, STMT00034(after) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 --------- ***** BB72, STMT00035(before) N004 ( 5, 6) [000135] ----------- * JTRUE void N003 ( 3, 4) [000134] J------N--- \--* EQ int N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 N001 [000132] LCL_VAR V09 loc5 u:2 => $4c1 {PhiDef($9, $2, $543)} N002 [000133] CNS_INT 0 => $c0 {IntCns 0} N003 [000134] EQ => $6bb {EQ($4c1, $c0)} N004 [000135] JTRUE => $VN.Void ***** BB72, STMT00035(after) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 finish(BB72). Succ(BB73). Not yet completed. All preds complete, adding to allDone. Succ(BB74). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#5) at start of BB74 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB74 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB74, STMT00036(before) N007 ( 8, 7) [000140] ---XG------ * JTRUE void N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [000136] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002635] CNS_INT 4 => $207 {LngCns: 4} N003 [002636] ADD => $24a {ADD($101, $207)} N004 [000137] IND => N005 [000138] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N006 [000139] GT => N007 [000140] JTRUE => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB74, STMT00036(after) N007 ( 8, 7) [000140] ---XG------ * JTRUE void $301 N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d finish(BB74). Succ(BB75). Not yet completed. All preds complete, adding to allDone. Succ(BB76). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#5) at start of BB76 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB76 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB76, STMT00037(before) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 N001 [000141] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002637] CNS_INT 4 => $207 {LngCns: 4} N003 [002638] ADD => $24a {ADD($101, $207)} N004 [000142] IND => N005 [000143] LCL_VAR V46 tmp6 d:2 => $VN.Void Tree [000144] assigned VN to local var V46/2: N006 [000144] ASG => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB76, STMT00037(after) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int $301 N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref $24a N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 $207 finish(BB76). Succ(BB77). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB75 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB75 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB75, STMT00239(before) N003 ( 5, 4) [001106] -A------R-- * ASG int N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [001104] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N002 [001105] LCL_VAR V46 tmp6 d:3 => $VN.Void Tree [001106] assigned VN to local var V46/3: $28d {PhiDef($5, $3, $34e)} N003 [001106] ASG => $VN.Void ***** BB75, STMT00239(after) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d finish(BB75). Succ(BB77). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 46/1 to $295 {PhiDef($2e, $1, $352)} . The SSA definition for ByrefExposed (#5) at start of BB77 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB77 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB77, STMT00038(before) N003 ( 3, 3) [000148] -A------R-- * ASG int N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) N001 [000146] LCL_VAR V46 tmp6 u:1 (last use) => $295 {PhiDef($2e, $1, $352)} N002 [000147] LCL_VAR V08 loc4 d:7 => $VN.Void Tree [000148] assigned VN to local var V08/7: $295 {PhiDef($2e, $1, $352)} N003 [000148] ASG => $VN.Void ***** BB77, STMT00038(after) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 --------- ***** BB77, STMT00039(before) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [000149] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002639] CNS_INT 4 => $207 {LngCns: 4} N003 [002640] ADD => $24a {ADD($101, $207)} N004 [000150] IND => N005 [000151] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N006 [000152] SUB => N007 [000153] LCL_VAR V14 loc10 d:8 => $VN.Void Tree [000154] assigned VN to local var V14/8: N008 [000154] ASG => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB77, STMT00039(after) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d finish(BB77). Succ(BB78). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB73 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB73 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB73, STMT00240(before) N003 ( 1, 3) [001110] -A------R-- * ASG int N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [001108] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N002 [001109] LCL_VAR V08 loc4 d:8 => $VN.Void Tree [001110] assigned VN to local var V08/8: $28d {PhiDef($5, $3, $34e)} N003 [001110] ASG => $VN.Void ***** BB73, STMT00240(after) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d --------- ***** BB73, STMT00241(before) N003 ( 1, 3) [001113] -A------R-- * ASG int N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 N001 [001111] CNS_INT 0 => $c0 {IntCns 0} N002 [001112] LCL_VAR V14 loc10 d:9 => $VN.Void Tree [001113] assigned VN to local var V14/9: $c0 {IntCns 0} N003 [001113] ASG => $VN.Void ***** BB73, STMT00241(after) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 finish(BB73). Succ(BB78). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 14/1 to $296 {PhiDef($e, $1, $708)} . SSA PHI definition: set VN of local 8/1 to $297 {PhiDef($8, $1, $709)} . The SSA definition for ByrefExposed (#5) at start of BB78 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB78 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB78, STMT00040(before) N003 ( 1, 3) [000157] -A------R-- * ASG int N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 N001 [000155] LCL_VAR V15 loc11 u:2 => $283 {PhiDef($f, $2, $34d)} N002 [000156] LCL_VAR V16 loc12 d:3 => $VN.Void Tree [000157] assigned VN to local var V16/3: $283 {PhiDef($f, $2, $34d)} N003 [000157] ASG => $VN.Void ***** BB78, STMT00040(after) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 --------- ***** BB78, STMT00041(before) N003 ( 0, 0) [002647] ----------- * COMMA void N001 ( 0, 0) [002643] ----------- +--* NOP void N002 ( 0, 0) [002646] ----------- \--* NOP void N001 [002643] NOP => $581 {MemOpaque:NotInLoop} N002 [002646] NOP => $582 {MemOpaque:NotInLoop} N003 [002647] COMMA => $582 {MemOpaque:NotInLoop} ***** BB78, STMT00041(after) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 --------- ***** BB78, STMT00324(before) N003 ( 3, 3) [001553] -A------R-- * ASG byref N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 N001 [001550] LCL_VAR_ADDR V47 tmp7 => $740 {MemOpaque:NotInLoop} N002 [001552] LCL_VAR V151 tmp111 d:1 => $VN.Void Tree [001553] assigned VN to local var V151/1: $24b {$740, byref <- long} N003 [001553] ASG => $VN.Void ***** BB78, STMT00324(after) N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 --------- ***** BB78, STMT00325(before) N003 ( 1, 3) [001558] -A------R-- * ASG int N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 N001 [001556] CNS_INT 4 => $c8 {IntCns 4} N002 [001557] LCL_VAR V152 tmp112 d:1 => $VN.Void Tree [001558] assigned VN to local var V152/1: $c8 {IntCns 4} N003 [001558] ASG => $VN.Void ***** BB78, STMT00325(after) N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 --------- ***** BB78, STMT00044(before) N007 ( 2, 6) [002654] -A--------- * COMMA void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) N006 ( 1, 3) [002653] -A------R-- \--* ASG int N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) N001 [002649] LCL_VAR V151 tmp111 u:1 (last use) => $24b {$740, byref <- long} N002 [002648] LCL_VAR V143 tmp103 d:1 => $VN.Void Tree [002650] assigned VN to local var V143/1: $24b {$740, byref <- long} N003 [002650] ASG => $VN.Void N004 [002652] LCL_VAR V152 tmp112 u:1 (last use) => $c8 {IntCns 4} N005 [002651] LCL_VAR V144 tmp104 d:1 => $VN.Void Tree [002653] assigned VN to local var V144/1: $c8 {IntCns 4} N006 [002653] ASG => $VN.Void N007 [002654] COMMA => $VN.Void ***** BB78, STMT00044(after) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) $c8 --------- ***** BB78, STMT00045(before) N003 ( 1, 3) [000177] -A------R-- * ASG int N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 N001 [000175] CNS_INT -1 => $c4 {IntCns 4294967295} N002 [000176] LCL_VAR V20 loc16 d:1 => $VN.Void Tree [000177] assigned VN to local var V20/1: $c4 {IntCns 4294967295} N003 [000177] ASG => $VN.Void ***** BB78, STMT00045(after) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 --------- ***** BB78, STMT00046(before) N004 ( 5, 6) [000181] ----------- * JTRUE void N003 ( 3, 4) [000180] J------N--- \--* EQ int N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 N001 [000178] LCL_VAR V12 loc8 u:3 => $4c4 {PhiDef($c, $3, $34e)} N002 [000179] CNS_INT 0 => $c0 {IntCns 0} N003 [000180] EQ => $70a {EQ($4c4, $c0)} N004 [000181] JTRUE => $VN.Void ***** BB78, STMT00046(after) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 finish(BB78). Succ(BB79). Not yet completed. All preds complete, adding to allDone. Succ(BB103). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB79 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB79 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB79, STMT00203(before) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 N001 [000941] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N002 [002655] CNS_INT 56 Fseq[] => $209 {LngCns: 56} N003 [002656] ADD => $24c {ADD($180, $209)} VNForHandle() is $47, fieldType is ref, size = 8 VNForMapSelect($6c4, $47):mem returns $782 {$6c4[$47]} VNForMapSelect($782, $180):ref returns $314 {$782[$180]} N004 [001570] IND => N005 [000944] ARR_LENGTH => N006 [000945] CNS_INT 0 => $c0 {IntCns 0} N007 [000946] LE => N008 [000947] JTRUE => ***** BB79, STMT00203(after) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 finish(BB79). Succ(BB80). Not yet completed. All preds complete, adding to allDone. Succ(BB103). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#5) at start of BB80 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB80 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB80, STMT00204(before) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] N001 [000948] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N002 [002657] CNS_INT 8 Fseq[] => $201 {LngCns: 8} N003 [002658] ADD => $24d {ADD($180, $201)} VNForHandle() is $48, fieldType is ref, size = 8 VNForMapSelect($6c4, $48):mem returns $785 {$6c4[$48]} VNForMapSelect($785, $180):ref returns $31e {$785[$180]} N004 [000949] IND => N005 [000950] LCL_VAR V26 loc22 d:1 => $VN.Void Tree [000951] assigned VN to local var V26/1: N006 [000951] ASG => $321 {norm=$VN.Void, exc=$315 {NullPtrExc($180)}} ***** BB80, STMT00204(after) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 --------- ***** BB80, STMT00205(before) N003 ( 1, 3) [000954] -A------R-- * ASG int N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 N001 [000952] CNS_INT 0 => $c0 {IntCns 0} N002 [000953] LCL_VAR V27 loc23 d:1 => $VN.Void Tree [000954] assigned VN to local var V27/1: $c0 {IntCns 0} N003 [000954] ASG => $VN.Void ***** BB80, STMT00205(after) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB80, STMT00206(before) N003 ( 1, 3) [000957] -A------R-- * ASG int N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 N001 [000955] CNS_INT 0 => $c0 {IntCns 0} N002 [000956] LCL_VAR V28 loc24 d:1 => $VN.Void Tree [000957] assigned VN to local var V28/1: $c0 {IntCns 0} N003 [000957] ASG => $VN.Void ***** BB80, STMT00206(after) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB80, STMT00207(before) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 N001 [000958] LCL_VAR V26 loc22 u:1 => N002 [000959] ARR_LENGTH => N003 [000960] LCL_VAR V29 loc25 d:1 => $VN.Void Tree [000961] assigned VN to local var V29/1: N004 [000961] ASG => ***** BB80, STMT00207(after) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 --------- ***** BB80, STMT00208(before) N004 ( 5, 6) [000965] ----------- * JTRUE void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 N001 [000962] LCL_VAR V29 loc25 u:1 => N002 [000963] CNS_INT 0 => $c0 {IntCns 0} N003 [000964] EQ => N004 [000965] JTRUE => $VN.Void ***** BB80, STMT00208(after) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 finish(BB80). Succ(BB81). Not yet completed. All preds complete, adding to allDone. Succ(BB82). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB81 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB81 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB81, STMT00238(before) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 N011 ( 4, 6) [002665] ----------- \--* LSH long N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 N001 [001099] LCL_VAR V27 loc23 u:1 => $c0 {IntCns 0} N002 [001098] LCL_VAR V26 loc22 u:1 => N003 [002661] ARR_LENGTH => N004 [002662] BOUNDS_CHECK_Rng => N005 [002659] LCL_VAR V26 loc22 u:1 => N006 [002666] CNS_INT 16 => $200 {LngCns: 16} N007 [002667] ADD => N008 [002660] LCL_VAR V27 loc23 u:1 => $c0 {IntCns 0} N009 [002663] CAST => $205 {LngCns: 0} N010 [002664] CNS_INT 2 => $20a {LngCns: 2} N011 [002665] LSH => $205 {LngCns: 0} N012 [002668] ADD => VNForHandle(arrElemType: int) is $40 N013 [002669] ARR_ADDR => $82 {PtrToArrElem($40, $31e, $205, $205)} Array element load: elemTypeEq is $40 for int[] VNForMapSelect($6c4, $40):mem returns $788 {$6c4[$40]} GcHeap[elemTypeEq: $40] is $788 VNForMapSelect($788, $31e):mem returns $789 {$788[$31e]} GcHeap[elemTypeEq][array: $31e] is $789 VNForMapSelect($789, $205):int returns $715 {$789[$205]} GcHeap[elemTypeEq][array][index: $205] is $715 N014 [002671] IND => N015 [002670] COMMA => N016 [001102] LCL_VAR V28 loc24 d:5 => $VN.Void Tree [001103] assigned VN to local var V28/5: N017 [001103] ASG => ***** BB81, STMT00238(after) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a finish(BB81). Succ(BB82). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 28/2 to $298 {PhiDef($1c, $2, $718)} . The SSA definition for ByrefExposed (#5) at start of BB82 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB82 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB82, STMT00209(before) N003 ( 1, 3) [000968] -A------R-- * ASG int N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 N001 [000966] LCL_VAR V28 loc24 u:2 => $298 {PhiDef($1c, $2, $718)} N002 [000967] LCL_VAR V30 loc26 d:1 => $VN.Void Tree [000968] assigned VN to local var V30/1: $298 {PhiDef($1c, $2, $718)} N003 [000968] ASG => $VN.Void ***** BB82, STMT00209(after) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 --------- ***** BB82, STMT00211(before) N003 ( 5, 4) [000975] -A------R-- * ASG int N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 N001 [000969] LCL_VAR V08 loc4 u:1 => $297 {PhiDef($8, $1, $709)} N002 [000974] LCL_VAR V64 tmp24 d:1 => $VN.Void Tree [000975] assigned VN to local var V64/1: $297 {PhiDef($8, $1, $709)} N003 [000975] ASG => $VN.Void ***** BB82, STMT00211(after) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 --------- ***** BB82, STMT00210(before) N004 ( 5, 6) [000973] ----------- * JTRUE void N003 ( 3, 4) [000972] J------N--- \--* LT int N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 N001 [000970] LCL_VAR V14 loc10 u:1 => $296 {PhiDef($e, $1, $708)} N002 [000971] CNS_INT 0 => $c0 {IntCns 0} N003 [000972] LT => $719 {LT($296, $c0)} N004 [000973] JTRUE => $VN.Void ***** BB82, STMT00210(after) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 finish(BB82). Succ(BB83). Not yet completed. All preds complete, adding to allDone. Succ(BB84). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#5) at start of BB84 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB84 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB84, STMT00212(before) N003 ( 7, 5) [000981] -A------R-- * ASG int N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) N001 [000978] LCL_VAR V64 tmp24 u:1 (last use) => $297 {PhiDef($8, $1, $709)} N002 [000980] LCL_VAR V65 tmp25 d:2 => $VN.Void Tree [000981] assigned VN to local var V65/2: $297 {PhiDef($8, $1, $709)} N003 [000981] ASG => $VN.Void ***** BB84, STMT00212(after) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 --------- ***** BB84, STMT00213(before) N003 ( 5, 4) [000984] -A------R-- * ASG int N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 N001 [000979] LCL_VAR V14 loc10 u:1 => $296 {PhiDef($e, $1, $708)} N002 [000983] LCL_VAR V66 tmp26 d:2 => $VN.Void Tree [000984] assigned VN to local var V66/2: $296 {PhiDef($e, $1, $708)} N003 [000984] ASG => $VN.Void ***** BB84, STMT00213(after) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 finish(BB84). Succ(BB85). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB83 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB83 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB83, STMT00236(before) N003 ( 7, 5) [001093] -A------R-- * ASG int N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) N001 [000977] LCL_VAR V64 tmp24 u:1 (last use) => $297 {PhiDef($8, $1, $709)} N002 [001092] LCL_VAR V65 tmp25 d:3 => $VN.Void Tree [001093] assigned VN to local var V65/3: $297 {PhiDef($8, $1, $709)} N003 [001093] ASG => $VN.Void ***** BB83, STMT00236(after) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 --------- ***** BB83, STMT00237(before) N003 ( 5, 5) [001096] -A------R-- * ASG int N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 N001 [001091] CNS_INT 0 => $c0 {IntCns 0} N002 [001095] LCL_VAR V66 tmp26 d:3 => $VN.Void Tree [001096] assigned VN to local var V66/3: $c0 {IntCns 0} N003 [001096] ASG => $VN.Void ***** BB83, STMT00237(after) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 finish(BB83). Succ(BB85). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 66/1 to $299 {PhiDef($42, $1, $352)} . SSA PHI definition: set VN of local 65/1 to $297 {PhiDef($8, $1, $709)} (all same). The SSA definition for ByrefExposed (#5) at start of BB85 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB85 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB85, STMT00214(before) N005 ( 11, 8) [000990] -A------R-- * ASG int N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 N003 ( 7, 5) [000988] ----------- \--* ADD int N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) N001 [000986] LCL_VAR V65 tmp25 u:1 (last use) => $297 {PhiDef($8, $1, $709)} N002 [000987] LCL_VAR V66 tmp26 u:1 (last use) => $299 {PhiDef($42, $1, $352)} N003 [000988] ADD => $71a {ADD($297, $299)} N004 [000989] LCL_VAR V31 loc27 d:1 => $VN.Void Tree [000990] assigned VN to local var V31/1: $71a {ADD($297, $299)} N005 [000990] ASG => $VN.Void ***** BB85, STMT00214(after) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 --------- ***** BB85, STMT00215(before) N004 ( 7, 6) [000994] ----------- * JTRUE void N003 ( 5, 4) [000993] J------N--- \--* GT int N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 N001 [000991] LCL_VAR V06 loc2 u:3 => $292 {PhiDef($2c, $1, $352)} N002 [000992] LCL_VAR V31 loc27 u:1 => $71a {ADD($297, $299)} N003 [000993] GT => $71b {GT($292, $71a)} N004 [000994] JTRUE => $VN.Void ***** BB85, STMT00215(after) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a finish(BB85). Succ(BB86). Not yet completed. All preds complete, adding to allDone. Succ(BB87). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#5) at start of BB87 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB87 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB87, STMT00216(before) N003 ( 5, 4) [000997] -A------R-- * ASG int N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 N001 [000995] LCL_VAR V06 loc2 u:3 => $292 {PhiDef($2c, $1, $352)} N002 [000996] LCL_VAR V67 tmp27 d:2 => $VN.Void Tree [000997] assigned VN to local var V67/2: $292 {PhiDef($2c, $1, $352)} N003 [000997] ASG => $VN.Void ***** BB87, STMT00216(after) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 finish(BB87). Succ(BB88). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB86 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB86 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB86, STMT00235(before) N003 ( 7, 5) [001089] -A------R-- * ASG int N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) N001 [001087] LCL_VAR V31 loc27 u:1 (last use) => $71a {ADD($297, $299)} N002 [001088] LCL_VAR V67 tmp27 d:3 => $VN.Void Tree [001089] assigned VN to local var V67/3: $71a {ADD($297, $299)} N003 [001089] ASG => $VN.Void ***** BB86, STMT00235(after) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a finish(BB86). Succ(BB88). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 67/1 to $29a {PhiDef($43, $1, $352)} . The SSA definition for ByrefExposed (#5) at start of BB88 is $6c4 {PhiMemoryDef($46, $6c3)} The SSA definition for GcHeap (#5) at start of BB88 is $6c4 {PhiMemoryDef($46, $6c3)} ***** BB88, STMT00217(before) N003 ( 3, 3) [001001] -A------R-- * ASG int N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) N001 [000999] LCL_VAR V67 tmp27 u:1 (last use) => $29a {PhiDef($43, $1, $352)} N002 [001000] LCL_VAR V32 loc28 d:1 => $VN.Void Tree [001001] assigned VN to local var V32/1: $29a {PhiDef($43, $1, $352)} N003 [001001] ASG => $VN.Void ***** BB88, STMT00217(after) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a --------- ***** BB88, STMT00502(before) N004 ( 5, 5) [003156] ----------- * JTRUE void N003 ( 3, 3) [003157] J------N--- \--* LE int N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V28 loc24 u:2 N001 [003158] LCL_VAR V32 loc28 u:1 => $29a {PhiDef($43, $1, $352)} N002 [003159] LCL_VAR V28 loc24 u:2 => $298 {PhiDef($1c, $2, $718)} N003 [003157] LE => $71c {LE($29a, $298)} N004 [003156] JTRUE => $VN.Void ***** BB88, STMT00502(after) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 finish(BB88). Succ(BB89). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB103). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#62) at start of BB62 is $1c8 {MemOpaque:L00} The SSA definition for GcHeap (#62) at start of BB62 is $1c8 {MemOpaque:L00} ***** BB62, STMT00254(before) N003 ( 1, 3) [001170] -A------R-- * ASG int N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) N001 [001168] LCL_VAR V16 loc12 u:16 (last use) => $2c4 {MemOpaque:L00} N002 [001169] LCL_VAR V15 loc11 d:3 => $VN.Void Tree [001170] assigned VN to local var V15/3: $2c4 {MemOpaque:L00} N003 [001170] ASG => $VN.Void ***** BB62, STMT00254(after) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 finish(BB62). Succ(BB07). SSA PHI definition: set VN of local 20/10 to $29b {PhiDef($14, $a, $71d)} . SSA PHI definition: set VN of local 143/3 to $381 {PhiDef($8f, $3, $252)} . SSA PHI definition: set VN of local 144/3 to $29c {PhiDef($90, $3, $252)} . SSA PHI definition: set VN of local 30/2 to $29d {PhiDef($1e, $2, $34d)} . SSA PHI definition: set VN of local 27/2 to $29e {PhiDef($1b, $2, $34d)} . SSA PHI definition: set VN of local 28/3 to $29f {PhiDef($1c, $3, $34e)} . Computing GcHeap state for block BB89, entry block for loops 2 to 2: Loop 2 has memory havoc effect; heap state is new unique $1c9. The SSA definition for GcHeap (#52) at start of BB89 is $1c9 {MemOpaque:L02} ***** BB89, STMT00219(before) N004 ( 5, 6) [001009] ----------- * JTRUE void N003 ( 3, 4) [001008] J------N--- \--* EQ int N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 N001 [001006] LCL_VAR V30 loc26 u:2 => $29d {PhiDef($1e, $2, $34d)} N002 [001007] CNS_INT 0 => $c0 {IntCns 0} N003 [001008] EQ => $71e {EQ($29d, $c0)} N004 [001009] JTRUE => $VN.Void ***** BB89, STMT00219(after) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 finish(BB89). Succ(BB90). Not yet completed. All preds complete, adding to allDone. Succ(BB103). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#52) at start of BB90 is $1c9 {MemOpaque:L02} The SSA definition for GcHeap (#52) at start of BB90 is $1c9 {MemOpaque:L02} ***** BB90, STMT00220(before) N005 ( 3, 4) [001014] -A------R-- * ASG int N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 N003 ( 3, 4) [001012] ----------- \--* ADD int N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 N001 [001010] LCL_VAR V20 loc16 u:10 (last use) => $29b {PhiDef($14, $a, $71d)} N002 [001011] CNS_INT 1 => $c1 {IntCns 1} N003 [001012] ADD => $71f {ADD($c1, $29b)} N004 [001013] LCL_VAR V20 loc16 d:11 => $VN.Void Tree [001014] assigned VN to local var V20/11: $71f {ADD($c1, $29b)} N005 [001014] ASG => $VN.Void ***** BB90, STMT00220(after) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB90, STMT00222(before) N004 ( 5, 5) [001021] ----------- * JTRUE void N003 ( 3, 3) [001020] J------N--- \--* LT int N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 N001 [001015] LCL_VAR V20 loc16 u:11 => $71f {ADD($c1, $29b)} N002 [001574] LCL_VAR V144 tmp104 u:3 => $29c {PhiDef($90, $3, $252)} N003 [001020] LT => $720 {LT($71f, $29c)} N004 [001021] JTRUE => $VN.Void ***** BB90, STMT00222(after) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c finish(BB90). Succ(BB91). Not yet completed. All preds complete, adding to allDone. Succ(BB100). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#52) at start of BB91 is $1c9 {MemOpaque:L02} The SSA definition for GcHeap (#52) at start of BB91 is $1c9 {MemOpaque:L02} ***** BB91, STMT00229(before) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int N003 ( 3, 4) [001066] ----------- | \--* LSH int N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn N001 [001578] LCL_VAR V144 tmp104 u:3 => $29c {PhiDef($90, $3, $252)} N002 [001065] CNS_INT 1 => $c1 {IntCns 1} N003 [001066] LSH => $721 {LSH($29c, $c1)} N004 [001067] CAST => $3cf {$721, long <- int} N005 [002672] CNS_INT(h) 0x4000000000421858 ftn => $49 {Hnd const: 0x4000000000421858} N006 [001068] CALL help r2r_ind => $330 {norm=$800 {JitReadyToRunNewArr($49, $3cf, $18f)}, exc=$32f {NewArrOverflowExc($49)}} N007 [001069] LCL_VAR V33 loc29 d:1 => $VN.Void Tree [001070] assigned VN to local var V33/1: $800 {JitReadyToRunNewArr($49, $3cf, $18f)} N008 [001070] ASG => $331 {norm=$VN.Void, exc=$32f {NewArrOverflowExc($49)}} ***** BB91, STMT00229(after) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 --------- ***** BB91, STMT00327(before) N003 ( 0, 0) [002679] ----------- * COMMA void N001 ( 0, 0) [002675] ----------- +--* NOP void N002 ( 0, 0) [002678] ----------- \--* NOP void N001 [002675] NOP => $583 {MemOpaque:L02} N002 [002678] NOP => $584 {MemOpaque:L02} N003 [002679] COMMA => $584 {MemOpaque:L02} ***** BB91, STMT00327(after) N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 --------- ***** BB91, STMT00329(before) N004 ( 5, 6) [001590] ----------- * JTRUE void N003 ( 3, 4) [001589] J------N--- \--* NE int N001 ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [001588] ----------- \--* CNS_INT ref null N001 [001073] LCL_VAR V33 loc29 u:1 => $800 {JitReadyToRunNewArr($49, $3cf, $18f)} N002 [001588] CNS_INT null => $VN.Null N003 [001589] NE => $c1 {IntCns 1} N004 [001590] JTRUE => $VN.Void ***** BB91, STMT00329(after) N004 ( 5, 6) [001590] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001589] J------N--- \--* NE int $c1 N001 ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [001588] ----------- \--* CNS_INT ref null $VN.Null finish(BB91). Succ(BB92). Not yet completed. All preds complete, adding to allDone. Succ(BB93). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#52) at start of BB93 is $1c9 {MemOpaque:L02} The SSA definition for GcHeap (#52) at start of BB93 is $1c9 {MemOpaque:L02} ***** BB93, STMT00331(before) N005 ( 3, 4) [001604] -A---O--R-- * ASG byref N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 N003 ( 3, 4) [002691] -----O----- \--* ADD byref N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] N001 [002689] LCL_VAR V33 loc29 u:1 => $800 {JitReadyToRunNewArr($49, $3cf, $18f)} N002 [002690] CNS_INT 16 Fseq[] => $200 {LngCns: 16} N003 [002691] ADD => $253 {ADD($200, $800)} N004 [001603] LCL_VAR V159 tmp119 d:2 => $VN.Void Tree [001604] assigned VN to local var V159/2: $253 {ADD($200, $800)} N005 [001604] ASG => $VN.Void ***** BB93, STMT00331(after) N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 --------- ***** BB93, STMT00332(before) N004 ( 3, 3) [001610] -A-X----R-- * ASG int N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 N001 [001607] LCL_VAR V33 loc29 u:1 => $800 {JitReadyToRunNewArr($49, $3cf, $18f)} N002 [001608] ARR_LENGTH => $2cc {ARR_LENGTH($800)} N003 [001609] LCL_VAR V160 tmp120 d:2 => $VN.Void Tree [001610] assigned VN to local var V160/2: $2cc {ARR_LENGTH($800)} N004 [001610] ASG => $VN.Void ***** BB93, STMT00332(after) N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 finish(BB93). Succ(BB94). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#52) at start of BB92 is $1c9 {MemOpaque:L02} The SSA definition for GcHeap (#52) at start of BB92 is $1c9 {MemOpaque:L02} ***** BB92, STMT00333(before) N007 ( 2, 6) [002686] -A--------- * COMMA void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002685] -A------R-- \--* ASG int N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 N001 [002681] CNS_INT 0 => $VN.Null N002 [002680] LCL_VAR V159 tmp119 d:3 => $VN.Void Tree [002682] assigned VN to local var V159/3: $VN.Null N003 [002682] ASG => $VN.Void N004 [002684] CNS_INT 0 => $c0 {IntCns 0} N005 [002683] LCL_VAR V160 tmp120 d:3 => $VN.Void Tree [002685] assigned VN to local var V160/3: $c0 {IntCns 0} N006 [002685] ASG => $VN.Void N007 [002686] COMMA => $VN.Void ***** BB92, STMT00333(after) N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 finish(BB92). Succ(BB94). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 159/1 to $382 {PhiDef($9f, $1, $352)} . SSA PHI definition: set VN of local 160/1 to $2a0 {PhiDef($a0, $1, $352)} . The SSA definition for ByrefExposed (#52) at start of BB94 is $1c9 {MemOpaque:L02} The SSA definition for GcHeap (#52) at start of BB94 is $1c9 {MemOpaque:L02} ***** BB94, STMT00339(before) N005 ( 1, 3) [002699] -A--------- * COMMA void N003 ( 1, 3) [002695] -A------R-- +--* ASG byref N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) N004 ( 0, 0) [002698] ----------- \--* NOP void N001 [002694] LCL_VAR V159 tmp119 u:1 (last use) => $382 {PhiDef($9f, $1, $352)} N002 [002693] LCL_VAR V161 tmp121 d:1 => $VN.Void Tree [002695] assigned VN to local var V161/1: $382 {PhiDef($9f, $1, $352)} N003 [002695] ASG => $VN.Void N004 [002698] NOP => $585 {MemOpaque:L02} N005 [002699] COMMA => $585 {MemOpaque:L02} ***** BB94, STMT00339(after) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 --------- ***** BB94, STMT00336(before) N004 ( 5, 5) [001629] ----------- * JTRUE void N003 ( 3, 3) [001628] N------N-U- \--* GT int N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) N001 [001620] LCL_VAR V144 tmp104 u:3 => $29c {PhiDef($90, $3, $252)} N002 [001647] LCL_VAR V160 tmp120 u:1 (last use) => $2a0 {PhiDef($a0, $1, $352)} N003 [001628] GT => $722 {GT_UN($29c, $2a0)} N004 [001629] JTRUE => $VN.Void ***** BB94, STMT00336(after) N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 finish(BB94). Succ(BB95). Not yet completed. All preds complete, adding to allDone. Succ(BB110). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#52) at start of BB110 is $1c9 {MemOpaque:L02} The SSA definition for GcHeap (#52) at start of BB110 is $1c9 {MemOpaque:L02} ***** BB110, STMT00337(before) N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn N001 [002701] CNS_INT(h) 0x4000000000424a20 ftn => $4a {Hnd const: 0x4000000000424A20} fgCurMemoryVN[GcHeap] assigned for CALL at [001630] to VN: $1ca. N002 [001630] CALL r2r_ind => $VN.Void ***** BB110, STMT00337(after) N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a finish(BB110). The SSA definition for ByrefExposed (#52) at start of BB95 is $1c9 {MemOpaque:L02} The SSA definition for GcHeap (#52) at start of BB95 is $1c9 {MemOpaque:L02} finish(BB95). Succ(BB96). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#52) at start of BB96 is $1c9 {MemOpaque:L02} The SSA definition for GcHeap (#52) at start of BB96 is $1c9 {MemOpaque:L02} ***** BB96, STMT00346(before) N004 ( 2, 3) [001673] -A------R-- * ASG long N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) N001 [001639] LCL_VAR V144 tmp104 u:3 (last use) => $29c {PhiDef($90, $3, $252)} N002 [001640] CAST => $3d0 {$29c, long <- ulong <- uint} N003 [001672] LCL_VAR V83 tmp43 d:1 => $VN.Void Tree [001673] assigned VN to local var V83/1: $3d0 {$29c, long <- ulong <- uint} N004 [001673] ASG => $VN.Void ***** BB96, STMT00346(after) N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c --------- ***** BB96, STMT00343(before) N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn N001 [001663] LCL_VAR V83 tmp43 u:1 (last use) => $3d0 {$29c, long <- ulong <- uint} N002 [001665] CNS_INT 2 => $20a {LngCns: 2} N003 [001666] LSH => $3d1 {LSH($3d0, $20a)} N004 [001661] LCL_VAR V161 tmp121 u:1 (last use) => $382 {PhiDef($9f, $1, $352)} N005 [001662] LCL_VAR V143 tmp103 u:3 (last use) => $381 {PhiDef($8f, $3, $252)} N006 [002700] CNS_INT(h) 0x4000000000420490 ftn => $4b {Hnd const: 0x4000000000420490} fgCurMemoryVN[GcHeap] assigned for CALL at [001667] to VN: $1cb. N007 [001667] CALL r2r_ind => $VN.Void ***** BB96, STMT00343(after) N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b --------- ***** BB96, STMT00351(before) N003 ( 0, 0) [002708] ----------- * COMMA void N001 ( 0, 0) [002704] ----------- +--* NOP void N002 ( 0, 0) [002707] ----------- \--* NOP void N001 [002704] NOP => $586 {MemOpaque:L02} N002 [002707] NOP => $587 {MemOpaque:L02} N003 [002708] COMMA => $587 {MemOpaque:L02} ***** BB96, STMT00351(after) N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 --------- ***** BB96, STMT00353(before) N004 ( 5, 6) [001702] ----------- * JTRUE void N003 ( 3, 4) [001701] J------N--- \--* NE int N001 ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [001700] ----------- \--* CNS_INT ref null N001 [001082] LCL_VAR V33 loc29 u:1 => $800 {JitReadyToRunNewArr($49, $3cf, $18f)} N002 [001700] CNS_INT null => $VN.Null N003 [001701] NE => $c1 {IntCns 1} N004 [001702] JTRUE => $VN.Void ***** BB96, STMT00353(after) N004 ( 5, 6) [001702] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001701] J------N--- \--* NE int $c1 N001 ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [001700] ----------- \--* CNS_INT ref null $VN.Null finish(BB96). Succ(BB97). Not yet completed. All preds complete, adding to allDone. Succ(BB98). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#56) at start of BB98 is $1cb {MemOpaque:L02} The SSA definition for GcHeap (#56) at start of BB98 is $1cb {MemOpaque:L02} ***** BB98, STMT00355(before) N005 ( 3, 4) [001716] -A---O--R-- * ASG byref N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 N003 ( 3, 4) [002720] -----O----- \--* ADD byref N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] N001 [002718] LCL_VAR V33 loc29 u:1 => $800 {JitReadyToRunNewArr($49, $3cf, $18f)} N002 [002719] CNS_INT 16 Fseq[] => $200 {LngCns: 16} N003 [002720] ADD => $253 {ADD($200, $800)} N004 [001715] LCL_VAR V163 tmp123 d:2 => $VN.Void Tree [001716] assigned VN to local var V163/2: $253 {ADD($200, $800)} N005 [001716] ASG => $VN.Void ***** BB98, STMT00355(after) N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 --------- ***** BB98, STMT00356(before) N004 ( 3, 3) [001722] -A-X----R-- * ASG int N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) N001 [001719] LCL_VAR V33 loc29 u:1 (last use) => $800 {JitReadyToRunNewArr($49, $3cf, $18f)} N002 [001720] ARR_LENGTH => $2cc {ARR_LENGTH($800)} N003 [001721] LCL_VAR V164 tmp124 d:2 => $VN.Void Tree [001722] assigned VN to local var V164/2: $2cc {ARR_LENGTH($800)} N004 [001722] ASG => $VN.Void ***** BB98, STMT00356(after) N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 finish(BB98). Succ(BB99). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#56) at start of BB97 is $1cb {MemOpaque:L02} The SSA definition for GcHeap (#56) at start of BB97 is $1cb {MemOpaque:L02} ***** BB97, STMT00357(before) N007 ( 2, 6) [002715] -A--------- * COMMA void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 N006 ( 1, 3) [002714] -A------R-- \--* ASG int N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 N001 [002710] CNS_INT 0 => $VN.Null N002 [002709] LCL_VAR V163 tmp123 d:3 => $VN.Void Tree [002711] assigned VN to local var V163/3: $VN.Null N003 [002711] ASG => $VN.Void N004 [002713] CNS_INT 0 => $c0 {IntCns 0} N005 [002712] LCL_VAR V164 tmp124 d:3 => $VN.Void Tree [002714] assigned VN to local var V164/3: $c0 {IntCns 0} N006 [002714] ASG => $VN.Void N007 [002715] COMMA => $VN.Void ***** BB97, STMT00357(after) N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 finish(BB97). Succ(BB99). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 164/1 to $2a1 {PhiDef($a4, $1, $352)} . SSA PHI definition: set VN of local 163/1 to $383 {PhiDef($a3, $1, $352)} . The SSA definition for ByrefExposed (#56) at start of BB99 is $1cb {MemOpaque:L02} The SSA definition for GcHeap (#56) at start of BB99 is $1cb {MemOpaque:L02} ***** BB99, STMT00234(before) N007 ( 2, 6) [002728] -A--------- * COMMA void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) N006 ( 1, 3) [002727] -A------R-- \--* ASG int N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) N001 [002723] LCL_VAR V163 tmp123 u:1 (last use) => $383 {PhiDef($a3, $1, $352)} N002 [002722] LCL_VAR V143 tmp103 d:5 => $VN.Void Tree [002724] assigned VN to local var V143/5: $383 {PhiDef($a3, $1, $352)} N003 [002724] ASG => $VN.Void N004 [002726] LCL_VAR V164 tmp124 u:1 (last use) => $2a1 {PhiDef($a4, $1, $352)} N005 [002725] LCL_VAR V144 tmp104 d:5 => $VN.Void Tree [002727] assigned VN to local var V144/5: $2a1 {PhiDef($a4, $1, $352)} N006 [002727] ASG => $VN.Void N007 [002728] COMMA => $VN.Void ***** BB99, STMT00234(after) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 finish(BB99). Succ(BB100). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 143/4 to $384 {PhiDef($8f, $4, $254)} . SSA PHI definition: set VN of local 144/4 to $2a2 {PhiDef($90, $4, $254)} . Building phi application: $e2 = SSA# 56. Building phi application: $e3 = SSA# 52. Building phi application: $6c5 = phi($e3, $e2). The SSA definition for GcHeap (#53) at start of BB100 is $6c6 {PhiMemoryDef($4c, $6c5)} ***** BB100, STMT00223(before) N013 ( 16, 20) [001038] -A-XGO----- * ASG int N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 N008 ( 4, 6) [001032] ----------- | \--* LSH long N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 N001 [001024] LCL_VAR V20 loc16 u:11 => $71f {ADD($c1, $29b)} N002 [001028] LCL_VAR V144 tmp104 u:4 => $2a2 {PhiDef($90, $4, $254)} N003 [001029] BOUNDS_CHECK_Rng => $334 {norm=$VN.Void, exc=$333 {IndexOutOfRangeExc($71f, $2a2)}} N004 [001033] LCL_VAR V143 tmp103 u:4 => $384 {PhiDef($8f, $4, $254)} N005 [001025] LCL_VAR V20 loc16 u:11 => $71f {ADD($c1, $29b)} N006 [001030] CAST => $3d2 {$71f, long <- uint} N007 [001031] CNS_INT 2 => $20a {LngCns: 2} N008 [001032] LSH => $3d3 {LSH($3d2, $20a)} N009 [001034] ADD => $255 {ADD($384, $3d3)} N010 [002729] IND => $336 {norm=$VN.Void, exc=$335 {NullPtrExc($255)}} N011 [001035] COMMA => $338 {norm=$VN.Void, exc=$337( {NullPtrExc($255)}, {IndexOutOfRangeExc($71f, $2a2)})} N012 [001036] LCL_VAR V28 loc24 u:3 => $29f {PhiDef($1c, $3, $34e)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001038] to VN: $1cc. N013 [001038] ASG => $338 {norm=$VN.Void, exc=$337( {NullPtrExc($255)}, {IndexOutOfRangeExc($71f, $2a2)})} ***** BB100, STMT00223(after) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f --------- ***** BB100, STMT00224(before) N006 ( 7, 8) [001044] ----------- * JTRUE void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 N001 [001039] LCL_VAR V27 loc23 u:2 => $29e {PhiDef($1b, $2, $34d)} N002 [001040] LCL_VAR V29 loc25 u:1 => N003 [001041] CNS_INT -1 => $c4 {IntCns 4294967295} N004 [001042] ADD => N005 [001043] GE => N006 [001044] JTRUE => $VN.Void ***** BB100, STMT00224(after) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 finish(BB100). Succ(BB101). Not yet completed. All preds complete, adding to allDone. Succ(BB102). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#54) at start of BB101 is $1cc {MemOpaque:L02} The SSA definition for GcHeap (#54) at start of BB101 is $1cc {MemOpaque:L02} ***** BB101, STMT00226(before) N005 ( 3, 4) [001054] -A------R-- * ASG int N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 N003 ( 3, 4) [001052] ----------- \--* ADD int N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 N001 [001050] LCL_VAR V27 loc23 u:2 (last use) => $29e {PhiDef($1b, $2, $34d)} N002 [001051] CNS_INT 1 => $c1 {IntCns 1} N003 [001052] ADD => $727 {ADD($c1, $29e)} N004 [001053] LCL_VAR V27 loc23 d:4 => $VN.Void Tree [001054] assigned VN to local var V27/4: $727 {ADD($c1, $29e)} N005 [001054] ASG => $VN.Void ***** BB101, STMT00226(after) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB101, STMT00227(before) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $80 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 N011 ( 4, 6) [002736] ----------- \--* LSH long N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 N001 [001056] LCL_VAR V27 loc23 u:4 => $727 {ADD($c1, $29e)} N002 [001055] LCL_VAR V26 loc22 u:1 => N003 [002732] ARR_LENGTH => N004 [002733] BOUNDS_CHECK_Rng => N005 [002730] LCL_VAR V26 loc22 u:1 => N006 [002737] CNS_INT 16 => $200 {LngCns: 16} N007 [002738] ADD => N008 [002731] LCL_VAR V27 loc23 u:4 => $727 {ADD($c1, $29e)} N009 [002734] CAST => $3d4 {$727, long <- uint} N010 [002735] CNS_INT 2 => $20a {LngCns: 2} N011 [002736] LSH => $3d5 {LSH($3d4, $20a)} N012 [002739] ADD => VNForHandle(arrElemType: int) is $40 N013 [002740] ARR_ADDR => $83 {PtrToArrElem($40, $31e, $3d4, $205)} Array element load: elemTypeEq is $40 for int[] VNForMapSelect($1cc, $40):mem returns $78a {$1cc[$40]} GcHeap[elemTypeEq: $40] is $78a VNForMapSelect($78a, $31e):mem returns $78b {$78a[$31e]} GcHeap[elemTypeEq][array: $31e] is $78b VNForMapSelect($78b, $3d4):int returns $728 {$78b[$3d4]} GcHeap[elemTypeEq][array][index: $3d4] is $728 N014 [002742] IND => N015 [002741] COMMA => N016 [001059] LCL_VAR V30 loc26 d:4 => $VN.Void Tree [001060] assigned VN to local var V30/4: N017 [001060] ASG => ***** BB101, STMT00227(after) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a finish(BB101). Succ(BB102). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 30/3 to $2a3 {PhiDef($1e, $3, $34e)} . SSA PHI definition: set VN of local 27/3 to $2a4 {PhiDef($1b, $3, $34e)} . The SSA definition for ByrefExposed (#54) at start of BB102 is $1cc {MemOpaque:L02} The SSA definition for GcHeap (#54) at start of BB102 is $1cc {MemOpaque:L02} ***** BB102, STMT00225(before) N005 ( 3, 3) [001049] -A------R-- * ASG int N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 N003 ( 3, 3) [001047] ----------- \--* ADD int N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 N001 [001045] LCL_VAR V28 loc24 u:3 (last use) => $29f {PhiDef($1c, $3, $34e)} N002 [001046] LCL_VAR V30 loc26 u:3 => $2a3 {PhiDef($1e, $3, $34e)} N003 [001047] ADD => $72b {ADD($29f, $2a3)} N004 [001048] LCL_VAR V28 loc24 d:4 => $VN.Void Tree [001049] assigned VN to local var V28/4: $72b {ADD($29f, $2a3)} N005 [001049] ASG => $VN.Void ***** BB102, STMT00225(after) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 --------- ***** BB102, STMT00218(before) N004 ( 5, 5) [001005] ----------- * JTRUE void N003 ( 3, 3) [001004] J------N--- \--* GT int N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 N001 [001002] LCL_VAR V32 loc28 u:1 => $29a {PhiDef($43, $1, $352)} N002 [001003] LCL_VAR V28 loc24 u:4 => $72b {ADD($29f, $2a3)} N003 [001004] GT => $72c {GT($29a, $72b)} N004 [001005] JTRUE => $VN.Void ***** BB102, STMT00218(after) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b finish(BB102). Succ(BB103). Not yet completed. All preds complete, adding to allDone. Succ(BB89). SSA PHI definition: set VN of local 20/2 to $2a5 {PhiDef($14, $2, $72e)} . SSA PHI definition: set VN of local 143/2 to $385 {PhiDef($8f, $2, $258)} . SSA PHI definition: set VN of local 144/2 to $2a6 {PhiDef($90, $2, $258)} . Building phi application: $e5 = SSA# 54. Building phi application: $e3 = SSA# 52. Building phi application: $6c7 = phi($e3, $e5). Building phi application: $ca = SSA# 5. Building phi application: $6c8 = phi($ca, $6c7). The SSA definition for GcHeap (#6) at start of BB103 is $6c9 {PhiMemoryDef($4d, $6c8)} ***** BB103, STMT00047(before) N007 ( 9, 9) [000186] ---XG------ * JTRUE void N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 N001 [000182] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002743] CNS_INT 8 => $201 {LngCns: 8} N003 [002744] ADD => $247 {ADD($101, $201)} N004 [000183] IND => N005 [000184] CNS_INT 0 => $c0 {IntCns 0} N006 [000185] EQ => N007 [000186] JTRUE => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB103, STMT00047(after) N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 finish(BB103). Succ(BB104). Not yet completed. All preds complete, adding to allDone. Succ(BB112). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#6) at start of BB104 is $6c9 {PhiMemoryDef($4d, $6c8)} The SSA definition for GcHeap (#6) at start of BB104 is $6c9 {PhiMemoryDef($4d, $6c8)} ***** BB104, STMT00198(before) N004 ( 5, 6) [000930] ----------- * JTRUE void N003 ( 3, 4) [000929] J------N--- \--* NE int N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V15 loc11 u:2 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 N001 [000927] LCL_VAR V15 loc11 u:2 => $283 {PhiDef($f, $2, $34d)} N002 [000928] CNS_INT 0 => $c0 {IntCns 0} N003 [000929] NE => $733 {NE($283, $c0)} N004 [000930] JTRUE => $VN.Void ***** BB104, STMT00198(after) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V15 loc11 u:2 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 finish(BB104). Succ(BB105). Not yet completed. All preds complete, adding to allDone. Succ(BB112). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#6) at start of BB105 is $6c9 {PhiMemoryDef($4d, $6c8)} The SSA definition for GcHeap (#6) at start of BB105 is $6c9 {PhiMemoryDef($4d, $6c8)} ***** BB105, STMT00199(before) N007 ( 8, 8) [000935] ---XG------ * JTRUE void N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 N001 [000931] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [002745] CNS_INT 4 => $207 {LngCns: 4} N003 [002746] ADD => $24a {ADD($101, $207)} N004 [000932] IND => N005 [000933] CNS_INT 0 => $c0 {IntCns 0} N006 [000934] EQ => N007 [000935] JTRUE => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB105, STMT00199(after) N007 ( 8, 8) [000935] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 finish(BB105). Succ(BB106). Not yet completed. All preds complete, adding to allDone. Succ(BB112). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#6) at start of BB106 is $6c9 {PhiMemoryDef($4d, $6c8)} The SSA definition for GcHeap (#6) at start of BB106 is $6c9 {PhiMemoryDef($4d, $6c8)} ***** BB106, STMT00367(before) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] N001 [000937] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N002 [002747] CNS_INT 40 Fseq[] => $20b {LngCns: 40} N003 [002748] ADD => $259 {ADD($180, $20b)} VNForHandle() is $4e, fieldType is ref, size = 8 VNForMapSelect($6c9, $4e):mem returns $790 {$6c9[$4e]} VNForMapSelect($790, $180):ref returns $841 {$790[$180]} N004 [001730] IND => N005 [001782] LCL_VAR V86 tmp46 d:1 => $VN.Void Tree [001783] assigned VN to local var V86/1: N006 [001783] ASG => $321 {norm=$VN.Void, exc=$315 {NullPtrExc($180)}} ***** BB106, STMT00367(after) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b --------- ***** BB106, STMT00358(before) N004 ( 5, 6) [001735] ----------- * JTRUE void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null N001 [001732] LCL_VAR V86 tmp46 u:1 => N002 [001733] CNS_INT null => $VN.Null N003 [001734] EQ => N004 [001735] JTRUE => $VN.Void ***** BB106, STMT00358(after) N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null finish(BB106). Succ(BB107). Not yet completed. All preds complete, adding to allDone. Succ(BB112). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#6) at start of BB107 is $6c9 {PhiMemoryDef($4d, $6c8)} The SSA definition for GcHeap (#6) at start of BB107 is $6c9 {PhiMemoryDef($4d, $6c8)} ***** BB107, STMT00359(before) N006 ( 8, 6) [001738] -A-XG---R-- * ASG int N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 N001 [000936] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002749] CNS_INT 8 => $201 {LngCns: 8} N003 [002750] ADD => $25a {ADD($100, $201)} N004 [001736] IND => N005 [001737] LCL_VAR V87 tmp47 d:1 => $VN.Void Tree [001738] assigned VN to local var V87/1: N006 [001738] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB107, STMT00359(after) N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 --------- ***** BB107, STMT00360(before) N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 N001 [001739] LCL_VAR V86 tmp46 u:1 => N002 [001740] ARR_LENGTH => N003 [001741] CNS_INT 1 => $c1 {IntCns 1} N004 [001742] NE => N005 [001743] JTRUE => ***** BB107, STMT00360(after) N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 finish(BB107). Succ(BB108). Not yet completed. All preds complete, adding to allDone. Succ(BB111). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#6) at start of BB108 is $6c9 {PhiMemoryDef($4d, $6c8)} The SSA definition for GcHeap (#6) at start of BB108 is $6c9 {PhiMemoryDef($4d, $6c8)} ***** BB108, STMT00363(before) N007 ( 10, 8) [001753] ---XG------ * JTRUE void N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 N001 [001747] LCL_VAR V87 tmp47 u:1 => N002 [001748] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [002753] CNS_INT 24 => $20c {LngCns: 24} N004 [002754] ADD => $25b {ADD($100, $20c)} N005 [001786] IND => N006 [001752] GE => N007 [001753] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB108, STMT00363(after) N007 ( 10, 8) [001753] ---XG------ * JTRUE void $845 N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c finish(BB108). Succ(BB109). Not yet completed. All preds complete, adding to allDone. Succ(BB111). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#6) at start of BB111 is $6c9 {PhiMemoryDef($4d, $6c8)} The SSA definition for GcHeap (#6) at start of BB111 is $6c9 {PhiMemoryDef($4d, $6c8)} ***** BB111, STMT00361(before) N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn N001 [001744] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [001745] LCL_VAR V86 tmp46 u:1 (last use) => N003 [002780] CNS_INT(h) 0x4000000000431d58 ftn => $4f {Hnd const: 0x4000000000431D58} fgCurMemoryVN[GcHeap] assigned for CALL at [001746] to VN: $1cd. N004 [001746] CALL r2r_ind => $VN.Void ***** BB111, STMT00361(after) N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f finish(BB111). Succ(BB112). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#6) at start of BB109 is $6c9 {PhiMemoryDef($4d, $6c8)} The SSA definition for GcHeap (#6) at start of BB109 is $6c9 {PhiMemoryDef($4d, $6c8)} ***** BB109, STMT00364(before) N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 N003 ( 3, 4) [002760] -----O----- \--* ADD byref N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 N001 [002758] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002759] CNS_INT 16 => $200 {LngCns: 16} N003 [002760] ADD => $25c {ADD($100, $200)} N004 [001758] LCL_VAR V88 tmp48 d:1 => $VN.Void Tree [001759] assigned VN to local var V88/1: $25c {ADD($100, $200)} N005 [001759] ASG => $VN.Void ***** BB109, STMT00364(after) N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 --------- ***** BB109, STMT00365(before) N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 N001 [001756] LCL_VAR V87 tmp47 u:1 => N002 [001761] LCL_VAR V88 tmp48 u:1 => $25c {ADD($100, $200)} N003 [002762] CNS_INT 8 => $201 {LngCns: 8} N004 [002763] ADD => $25d {ADD($201, $25c)} N005 [001762] IND => N006 [001763] BOUNDS_CHECK_Rng => N007 [001760] LCL_VAR V88 tmp48 u:1 (last use) => $25c {ADD($100, $200)} N008 [001767] IND => N009 [001757] LCL_VAR V87 tmp47 u:1 => N010 [001764] CAST => N011 [001765] CNS_INT 1 => $204 {LngCns: 1} N012 [001766] LSH => N013 [001768] ADD => N014 [002764] IND => N015 [001769] COMMA => N016 [001771] CNS_INT 0 => $c0 {IntCns 0} N017 [001770] LCL_VAR V86 tmp46 u:1 => N018 [002767] ARR_LENGTH => N019 [002768] BOUNDS_CHECK_Rng => N020 [002765] LCL_VAR V86 tmp46 u:1 (last use) => N021 [002771] CNS_INT 12 => $20d {LngCns: 12} N022 [002772] ADD => VNForHandle(arrElemType: ushort) is $41 N023 [002774] ARR_ADDR => $84 {PtrToArrElem($41, $841, $205, $205)} Array element load: elemTypeEq is $41 for short[] VNForMapSelect($6c9, $41):mem returns $795 {$6c9[$41]} GcHeap[elemTypeEq: $41] is $795 VNForMapSelect($795, $841):mem returns $796 {$795[$841]} GcHeap[elemTypeEq][array: $841] is $796 VNForMapSelect($796, $205):short returns $8c0 {$796[$205]} GcHeap[elemTypeEq][array][index: $205] is $8c0 VNForLoadStoreBitcast returns $649 {BitCast($8c0)} N024 [002777] IND => ($8c0)}, c:$606 {MemOpaque:NotInLoop}> N025 [002775] COMMA => ($8c0)}, exc=$862( {NullPtrExc($841)}, {IndexOutOfRangeExc($c0, $2d0)})}, c:$64b {norm=$606 {MemOpaque:NotInLoop}, exc=$863( {NullPtrExc($191)}, {IndexOutOfRangeExc($c0, $2d1)})}> fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001775] to VN: $1ce. N026 [001775] ASG => ***** BB109, STMT00365(after) N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d --------- ***** BB109, STMT00366(before) N008 ( 10, 9) [001781] -A-XG---R-- * ASG int N007 ( 4, 3) [001780] D--XG--N--- +--* IND int N006 ( 3, 4) [002779] -------N--- | \--* ADD byref N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 N001 [001777] LCL_VAR V87 tmp47 u:1 (last use) => N002 [001778] CNS_INT 1 => $c1 {IntCns 1} N003 [001779] ADD => N004 [001776] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [002778] CNS_INT 8 => $201 {LngCns: 8} N006 [002779] ADD => $25a {ADD($100, $201)} N007 [001780] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001781] to VN: $1cf. N008 [001781] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB109, STMT00366(after) N008 ( 10, 9) [001781] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001780] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 finish(BB109). Succ(BB112). Not yet completed. All preds complete, adding to allDone. Building phi application: $e6 = SSA# 51. Building phi application: $e7 = SSA# 50. Building phi application: $6ca = phi($e7, $e6). Building phi application: $cb = SSA# 6. Building phi application: $6cb = phi($cb, $6ca). The SSA definition for GcHeap (#7) at start of BB112 is $6cc {PhiMemoryDef($50, $6cb)} ***** BB112, STMT00048(before) N003 ( 1, 3) [000189] -A------R-- * ASG int N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 N001 [002781] CNS_INT 0 => $c0 {IntCns 0} N002 [000188] LCL_VAR V21 loc17 d:1 => $VN.Void Tree [000189] assigned VN to local var V21/1: $c0 {IntCns 0} N003 [000189] ASG => $VN.Void ***** BB112, STMT00048(after) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB112, STMT00369(before) N005 ( 3, 4) [002788] -A--------- * COMMA void N003 ( 3, 4) [002784] -A------R-- +--* ASG byref N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] N004 ( 0, 0) [002787] ----------- \--* NOP void VNForLoad: VNForMapPhysicalSelect($140, [0:7]):byref returns $246 {$140[$202]} VNForLoad: VNForMapPhysicalSelect($140, [0:7]):byref returns $246 {$140[$202]} N001 [002783] LCL_FLD V02 arg2 u:1[+0] => $246 {$140[$202]} N002 [002782] LCL_VAR V165 tmp125 d:1 => $VN.Void Tree [002784] assigned VN to local var V165/1: $246 {$140[$202]} N003 [002784] ASG => $VN.Void N004 [002787] NOP => $588 {MemOpaque:NotInLoop} N005 [002788] COMMA => $588 {MemOpaque:NotInLoop} ***** BB112, STMT00369(after) N005 ( 3, 4) [002788] -A--------- * COMMA void $588 N003 ( 3, 4) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 --------- ***** BB112, STMT00050(before) N003 ( 5, 4) [000196] -A------R-- * ASG byref N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 N001 [001792] LCL_VAR V165 tmp125 u:1 => $246 {$140[$202]} N002 [000195] LCL_VAR V35 loc31 => $VN.Void Tree [000196] assigns to non-address-taken local V35; excluded from SSA, so value not tracked N003 [000196] ASG => $VN.Void ***** BB112, STMT00050(after) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 --------- ***** BB112, STMT00051(before) N007 ( 2, 4) [000200] -A------R-- * ASG long N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 N005 ( 2, 4) [002793] -A--------- \--* COMMA long N003 ( 1, 3) [002790] -A------R-- +--* ASG long N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) N001 [000197] LCL_VAR V165 tmp125 u:1 (last use) => $246 {$140[$202]} N002 [002789] LCL_VAR V169 tmp129 d:1 => $VN.Void Tree [002790] assigned VN to local var V169/1: $3c4 {$246, long <- byref} N003 [002790] ASG => $VN.Void N004 [002791] LCL_VAR V169 tmp129 u:1 (last use) => $3c4 {$246, long <- byref} N005 [002793] COMMA => $3c4 {$246, long <- byref} N006 [000199] LCL_VAR V34 loc30 d:1 => $VN.Void Tree [000200] assigned VN to local var V34/1: $3c4 {$246, long <- byref} N007 [000200] ASG => $VN.Void ***** BB112, STMT00051(after) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 --------- ***** BB112, STMT00052(before) N003 ( 1, 3) [000203] -A------R-- * ASG long N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 N001 [000201] LCL_VAR V17 loc13 u:1 => N002 [000202] LCL_VAR V36 loc32 d:1 => $VN.Void Tree [000203] assigned VN to local var V36/1: N003 [000203] ASG => $VN.Void ***** BB112, STMT00052(after) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 finish(BB112). Succ(BB245). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. SSA PHI definition: set VN of local 9/3 to $4c6 {PhiDef($9, $3, $34c)} . SSA PHI definition: set VN of local 21/2 to $4c7 {PhiDef($15, $2, $353)} . SSA PHI definition: set VN of local 36/2 to $900 {PhiDef($24, $2, $258)} . SSA PHI definition: set VN of local 14/2 to $2ab {PhiDef($e, $2, $258)} . SSA PHI definition: set VN of local 20/3 to $2ac {PhiDef($14, $3, $890)} . SSA PHI definition: set VN of local 8/2 to $2ad {PhiDef($8, $2, $258)} . SSA PHI definition: set VN of local 16/4 to $2ae {PhiDef($10, $4, $896)} . Computing GcHeap state for block BB245, entry block for loops 3 to 3: Loop 3 has memory havoc effect; heap state is new unique $1d0. The SSA definition for GcHeap (#8) at start of BB245 is $1d0 {MemOpaque:L03} ***** BB245, STMT00054(before) N004 ( 7, 8) [000210] ----------- * JTRUE void N003 ( 5, 6) [000209] J------N--- \--* GE int N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000204] LCL_VAR V16 loc12 u:4 => $2ae {PhiDef($10, $4, $896)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [002537] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000209] GE => $897 {GE($2ae, $342)} N004 [000210] JTRUE => $VN.Void ***** BB245, STMT00054(after) N004 ( 7, 8) [000210] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB245). Succ(BB246). Not yet completed. All preds complete, adding to allDone. Succ(BB248). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB246 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB246 is $1d0 {MemOpaque:L03} ***** BB246, STMT00065(before) N003 ( 1, 3) [000250] -A------R-- * ASG int N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 N001 [000243] LCL_VAR V16 loc12 u:4 => $2ae {PhiDef($10, $4, $896)} N002 [000249] LCL_VAR V49 tmp9 d:1 => $VN.Void Tree [000250] assigned VN to local var V49/1: $2ae {PhiDef($10, $4, $896)} N003 [000250] ASG => $VN.Void ***** BB246, STMT00065(after) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae --------- ***** BB246, STMT00064(before) N005 ( 3, 4) [000248] -A------R-- * ASG int N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 N003 ( 3, 4) [000246] ----------- \--* ADD int N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V16 loc12 u:4 (last use) N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 N001 [000244] LCL_VAR V16 loc12 u:4 (last use) => $2ae {PhiDef($10, $4, $896)} N002 [000245] CNS_INT 1 => $c1 {IntCns 1} N003 [000246] ADD => $898 {ADD($c1, $2ae)} N004 [000247] LCL_VAR V16 loc12 d:5 => $VN.Void Tree [000248] assigned VN to local var V16/5: $898 {ADD($c1, $2ae)} N005 [000248] ASG => $VN.Void ***** BB246, STMT00064(after) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V16 loc12 u:4 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB246, STMT00066(before) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000255] ----------- \--* LSH long N003 ( 2, 3) [000252] ----------- +--* CAST long <- int N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 N001 [000242] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000251] LCL_VAR V49 tmp9 u:1 (last use) => $2ae {PhiDef($10, $4, $896)} N003 [000252] CAST => $3db {$2ae, long <- int} N004 [000254] CNS_INT 1 => $204 {LngCns: 1} N005 [000255] LSH => $3dc {LSH($3db, $204)} N006 [000256] ADD => $3dd {ADD($3c4, $3dc)} N007 [000257] IND => N008 [000258] LCL_VAR V50 tmp10 d:1 => $VN.Void Tree [000259] assigned VN to local var V50/1: N009 [000259] ASG => $871 {norm=$VN.Void, exc=$870 {NullPtrExc($3dd)}} ***** BB246, STMT00066(after) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 --------- ***** BB246, STMT00067(before) N003 ( 1, 3) [000263] -A------R-- * ASG int N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 N001 [000261] LCL_VAR V50 tmp10 u:1 => N002 [000262] LCL_VAR V18 loc14 d:1 => $VN.Void Tree [000263] assigned VN to local var V18/1: N003 [000263] ASG => $VN.Void ***** BB246, STMT00067(after) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 --------- ***** BB246, STMT00068(before) N004 ( 5, 6) [000266] ----------- * JTRUE void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V50 tmp10 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 N001 [000260] LCL_VAR V50 tmp10 u:1 (last use) => N002 [000264] CNS_INT 0 => $c0 {IntCns 0} N003 [000265] EQ => N004 [000266] JTRUE => $VN.Void ***** BB246, STMT00068(after) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V50 tmp10 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 finish(BB246). Succ(BB247). Not yet completed. All preds complete, adding to allDone. Succ(BB248). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#8) at start of BB247 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB247 is $1d0 {MemOpaque:L03} ***** BB247, STMT00069(before) N004 ( 5, 6) [000270] ----------- * JTRUE void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 N001 [000267] LCL_VAR V18 loc14 u:1 => N002 [000268] CNS_INT 59 => $d1 {IntCns 59} N003 [000269] NE => N004 [000270] JTRUE => $VN.Void ***** BB247, STMT00069(after) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 finish(BB247). Succ(BB248). Not yet completed. All preds complete, adding to allDone. Succ(BB113). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#8) at start of BB113 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB113 is $1d0 {MemOpaque:L03} ***** BB113, STMT00070(before) N004 ( 5, 6) [000274] ----------- * JTRUE void N003 ( 3, 4) [000273] J------N--- \--* LE int N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 N001 [000271] LCL_VAR V14 loc10 u:2 => $2ab {PhiDef($e, $2, $258)} N002 [000272] CNS_INT 0 => $c0 {IntCns 0} N003 [000273] LE => $89f {LE($2ab, $c0)} N004 [000274] JTRUE => $VN.Void ***** BB113, STMT00070(after) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 finish(BB113). Succ(BB114). Not yet completed. All preds complete, adding to allDone. Succ(BB136). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB114 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB114 is $1d0 {MemOpaque:L03} ***** BB114, STMT00176(before) N004 ( 5, 6) [000824] ----------- * JTRUE void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 N001 [000821] LCL_VAR V18 loc14 u:1 => N002 [000822] CNS_INT 35 => $ea {IntCns 35} N003 [000823] EQ => N004 [000824] JTRUE => $VN.Void ***** BB114, STMT00176(after) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea finish(BB114). Succ(BB115). Not yet completed. All preds complete, adding to allDone. Succ(BB135). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB115 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB115 is $1d0 {MemOpaque:L03} ***** BB115, STMT00196(before) N004 ( 5, 6) [000922] ----------- * JTRUE void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 N001 [000919] LCL_VAR V18 loc14 u:1 => N002 [000920] CNS_INT 46 => $eb {IntCns 46} N003 [000921] EQ => N004 [000922] JTRUE => $VN.Void ***** BB115, STMT00196(after) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb finish(BB115). Succ(BB116). Not yet completed. All preds complete, adding to allDone. Succ(BB135). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#8) at start of BB116 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB116 is $1d0 {MemOpaque:L03} ***** BB116, STMT00197(before) N004 ( 5, 6) [000926] ----------- * JTRUE void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 N001 [000923] LCL_VAR V18 loc14 u:1 => N002 [000924] CNS_INT 48 => $d8 {IntCns 48} N003 [000925] EQ => N004 [000926] JTRUE => $VN.Void ***** BB116, STMT00197(after) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 finish(BB116). Succ(BB117). Not yet completed. All preds complete, adding to allDone. Succ(BB135). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#8) at start of BB117 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB117 is $1d0 {MemOpaque:L03} finish(BB117). Succ(BB136). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#8) at start of BB248 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB248 is $1d0 {MemOpaque:L03} ***** BB248, STMT00055(before) N003 ( 5, 5) [000214] -A------R-- * ASG byref N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 N001 [000212] CNS_INT 0 => $205 {LngCns: 0} N002 [000213] LCL_VAR V35 loc31 => $VN.Void Tree [000214] assigns to non-address-taken local V35; excluded from SSA, so value not tracked N003 [000214] ASG => $VN.Void ***** BB248, STMT00055(after) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 --------- ***** BB248, STMT00056(before) N007 ( 9, 9) [000219] ---XG------ * JTRUE void N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 N001 [000215] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [003147] CNS_INT 8 => $201 {LngCns: 8} N003 [003148] ADD => $247 {ADD($101, $201)} N004 [000216] IND => N005 [000217] CNS_INT 0 => $c0 {IntCns 0} N006 [000218] EQ => N007 [000219] JTRUE => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB248, STMT00056(after) N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 finish(BB248). Succ(BB249). Not yet completed. All preds complete, adding to allDone. Succ(BB253). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB249 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB249 is $1d0 {MemOpaque:L03} ***** BB249, STMT00058(before) N004 ( 5, 6) [000224] ----------- * JTRUE void N003 ( 3, 4) [000223] J------N--- \--* NE int N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 N001 [000221] LCL_VAR V15 loc11 u:2 (last use) => $283 {PhiDef($f, $2, $34d)} N002 [000222] CNS_INT 0 => $c0 {IntCns 0} N003 [000223] NE => $733 {NE($283, $c0)} N004 [000224] JTRUE => $VN.Void ***** BB249, STMT00058(after) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 finish(BB249). Succ(BB250). Not yet completed. All preds complete, adding to allDone. Succ(BB253). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#8) at start of BB250 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB250 is $1d0 {MemOpaque:L03} ***** BB250, STMT00059(before) N007 ( 8, 8) [000229] ---XG------ * JTRUE void N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 N001 [000225] LCL_VAR V01 arg1 u:1 (last use) => $101 {InitVal($c1)} N002 [003149] CNS_INT 4 => $207 {LngCns: 4} N003 [003150] ADD => $24a {ADD($101, $207)} N004 [000226] IND => N005 [000227] CNS_INT 0 => $c0 {IntCns 0} N006 [000228] NE => N007 [000229] JTRUE => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB250, STMT00059(after) N007 ( 8, 8) [000229] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 finish(BB250). Succ(BB251). Not yet completed. All preds complete, adding to allDone. Succ(BB253). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#8) at start of BB251 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB251 is $1d0 {MemOpaque:L03} ***** BB251, STMT00061(before) N007 ( 8, 8) [000235] ---XG------ * JTRUE void N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 N001 [000230] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003151] CNS_INT 8 => $201 {LngCns: 8} N003 [003152] ADD => $25a {ADD($100, $201)} N004 [002539] IND => N005 [000233] CNS_INT 0 => $c0 {IntCns 0} N006 [000234] LE => N007 [000235] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB251, STMT00061(after) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 finish(BB251). Succ(BB252). Not yet completed. All preds complete, adding to allDone. Succ(BB253). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#8) at start of BB252 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB252 is $1d0 {MemOpaque:L03} ***** BB252, STMT00063(before) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 N001 [000238] LCL_VAR V03 arg3 u:1 (last use) => $180 {InitVal($c3)} N002 [003154] CNS_INT 40 Fseq[] => $20b {LngCns: 40} N003 [003155] ADD => $259 {ADD($180, $20b)} VNForHandle() is $4e, fieldType is ref, size = 8 VNForMapSelect($1d0, $4e):mem returns $797 {$1d0[$4e]} VNForMapSelect($797, $180):ref returns $872 {$797[$180]} N004 [002541] IND => N005 [000236] LCL_VAR V00 arg0 u:1 (last use) => $100 {InitVal($c0)} N006 [003153] CNS_INT(h) 0x4000000000540210 ftn => $51 {Hnd const: 0x4000000000540210} N007 [000237] CNS_INT 0 => $c0 {IntCns 0} fgCurMemoryVN[GcHeap] assigned for CALL at [000241] to VN: $1d1. N008 [000241] CALL r2r_ind => $VN.Void ***** BB252, STMT00063(after) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 finish(BB252). Succ(BB253). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#8) at start of BB253 is $1d0 {MemOpaque:L03} The SSA definition for GcHeap (#8) at start of BB253 is $1d0 {MemOpaque:L03} ***** BB253, STMT00057(before) N001 ( 0, 0) [000220] ----------- * RETURN void N001 [000220] RETURN => $VN.Void ***** BB253, STMT00057(after) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void finish(BB253). SSA PHI definition: set VN of local 16/21 to $2b1 {PhiDef($10, $15, $8b6)} . The SSA definition for ByrefExposed (#4) at start of BB31 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB31 is $1c3 {MemOpaque:L00} ***** BB31, STMT00309(before) N004 ( 7, 8) [001441] ----------- * JTRUE void N003 ( 5, 6) [001440] J------N--- \--* GE int N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [001435] LCL_VAR V16 loc12 u:21 => $2b1 {PhiDef($10, $15, $8b6)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [001518] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [001440] GE => $8b7 {GE($2b1, $342)} N004 [001441] JTRUE => $VN.Void ***** BB31, STMT00309(after) N004 ( 7, 8) [001441] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB31). Succ(BB32). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB32 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB32 is $1c3 {MemOpaque:L00} ***** BB32, STMT00310(before) N010 ( 13, 15) [001452] ---XG------ * JTRUE void N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001447] ----------- | \--* LSH long N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 N001 [001442] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001443] LCL_VAR V16 loc12 u:21 => $2b1 {PhiDef($10, $15, $8b6)} N003 [001444] CAST => $3de {$2b1, long <- int} N004 [001446] CNS_INT 1 => $204 {LngCns: 1} N005 [001447] LSH => $3df {LSH($3de, $204)} N006 [001448] ADD => $3e0 {ADD($3c4, $3df)} N007 [001449] IND => N008 [001450] CNS_INT 0 => $c0 {IntCns 0} N009 [001451] EQ => N010 [001452] JTRUE => $876 {norm=$VN.Void, exc=$875 {NullPtrExc($3e0)}} ***** BB32, STMT00310(after) N010 ( 13, 15) [001452] ---XG------ * JTRUE void $876 N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 finish(BB32). Succ(BB33). Not yet completed. All preds complete, adding to allDone. Succ(BB47). The SSA definition for ByrefExposed (#4) at start of BB33 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB33 is $1c3 {MemOpaque:L00} ***** BB33, STMT00312(before) N003 ( 1, 3) [001461] -A------R-- * ASG int N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 N001 [001454] LCL_VAR V16 loc12 u:21 => $2b1 {PhiDef($10, $15, $8b6)} N002 [001460] LCL_VAR V74 tmp34 d:1 => $VN.Void Tree [001461] assigned VN to local var V74/1: $2b1 {PhiDef($10, $15, $8b6)} N003 [001461] ASG => $VN.Void ***** BB33, STMT00312(after) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 --------- ***** BB33, STMT00311(before) N005 ( 3, 4) [001459] -A------R-- * ASG int N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 N003 ( 3, 4) [001457] ----------- \--* ADD int N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V16 loc12 u:21 (last use) N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 N001 [001455] LCL_VAR V16 loc12 u:21 (last use) => $2b1 {PhiDef($10, $15, $8b6)} N002 [001456] CNS_INT 1 => $c1 {IntCns 1} N003 [001457] ADD => $8bc {ADD($c1, $2b1)} N004 [001458] LCL_VAR V16 loc12 d:22 => $VN.Void Tree [001459] assigned VN to local var V16/22: $8bc {ADD($c1, $2b1)} N005 [001459] ASG => $VN.Void ***** BB33, STMT00311(after) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V16 loc12 u:21 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB33, STMT00313(before) N010 ( 13, 14) [001471] ---XG------ * JTRUE void N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001466] ----------- | \--* LSH long N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 N001 [001453] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001462] LCL_VAR V74 tmp34 u:1 (last use) => $2b1 {PhiDef($10, $15, $8b6)} N003 [001463] CAST => $3de {$2b1, long <- int} N004 [001465] CNS_INT 1 => $204 {LngCns: 1} N005 [001466] LSH => $3df {LSH($3de, $204)} N006 [001467] ADD => $3e0 {ADD($3c4, $3df)} N007 [001468] IND => N008 [001469] LCL_VAR V18 loc14 u:5 => N009 [001470] NE => N010 [001471] JTRUE => $876 {norm=$VN.Void, exc=$875 {NullPtrExc($3e0)}} ***** BB33, STMT00313(after) N010 ( 13, 14) [001471] ---XG------ * JTRUE void $876 N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001466] ----------- | \--* LSH long $3df N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 finish(BB33). Succ(BB34). Not yet completed. All preds complete, adding to allDone. Succ(BB31). The SSA definition for ByrefExposed (#4) at start of BB34 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB34 is $1c3 {MemOpaque:L00} finish(BB34). Succ(BB47). SSA PHI definition: set VN of local 16/18 to $2b2 {PhiDef($10, $12, $941)} . The SSA definition for ByrefExposed (#4) at start of BB44 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB44 is $1c3 {MemOpaque:L00} ***** BB44, STMT00279(before) N005 ( 3, 4) [001305] -A------R-- * ASG int N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 N003 ( 3, 4) [001303] ----------- \--* ADD int N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 N001 [001301] LCL_VAR V16 loc12 u:18 (last use) => $2b2 {PhiDef($10, $12, $941)} N002 [001302] CNS_INT 1 => $c1 {IntCns 1} N003 [001303] ADD => $942 {ADD($c1, $2b2)} N004 [001304] LCL_VAR V73 tmp33 d:1 => $VN.Void Tree [001305] assigned VN to local var V73/1: $942 {ADD($c1, $2b2)} N005 [001305] ASG => $VN.Void ***** BB44, STMT00279(after) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB44, STMT00280(before) N003 ( 1, 3) [001309] -A------R-- * ASG int N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 N001 [001307] LCL_VAR V73 tmp33 u:1 => $942 {ADD($c1, $2b2)} N002 [001308] LCL_VAR V16 loc12 d:19 => $VN.Void Tree [001309] assigned VN to local var V16/19: $942 {ADD($c1, $2b2)} N003 [001309] ASG => $VN.Void ***** BB44, STMT00280(after) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 --------- ***** BB44, STMT00282(before) N004 ( 7, 8) [001315] ----------- * JTRUE void N003 ( 5, 6) [001314] J------N--- \--* GE int N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V73 tmp33 u:1 (last use) N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [001306] LCL_VAR V73 tmp33 u:1 (last use) => $942 {ADD($c1, $2b2)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [001534] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [001314] GE => $943 {GE($942, $342)} N004 [001315] JTRUE => $VN.Void ***** BB44, STMT00282(after) N004 ( 7, 8) [001315] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V73 tmp33 u:1 (last use) $942 N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB44). Succ(BB45). Not yet completed. All preds complete, adding to allDone. Succ(BB46). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB45 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB45 is $1c3 {MemOpaque:L00} ***** BB45, STMT00284(before) N010 ( 13, 15) [001329] ---XG------ * JTRUE void N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 N005 ( 4, 6) [001324] ----------- | \--* LSH long N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 N001 [001319] LCL_VAR V22 loc18 u:1 => $3c4 {$246, long <- byref} N002 [001320] LCL_VAR V16 loc12 u:19 => $942 {ADD($c1, $2b2)} N003 [001321] CAST => $3e1 {$942, long <- int} N004 [001323] CNS_INT 1 => $204 {LngCns: 1} N005 [001324] LSH => $3e2 {LSH($3e1, $204)} N006 [001325] ADD => $3e3 {ADD($3c4, $3e2)} N007 [001326] IND => N008 [001327] CNS_INT 48 => $d8 {IntCns 48} N009 [001328] EQ => N010 [001329] JTRUE => $878 {norm=$VN.Void, exc=$877 {NullPtrExc($3e3)}} ***** BB45, STMT00284(after) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 finish(BB45). Succ(BB46). Not yet completed. All preds complete, adding to allDone. Succ(BB44). The SSA definition for ByrefExposed (#4) at start of BB46 is $1c3 {MemOpaque:L00} The SSA definition for GcHeap (#4) at start of BB46 is $1c3 {MemOpaque:L00} ***** BB46, STMT00283(before) N003 ( 1, 3) [001318] -A------R-- * ASG int N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 N001 [002613] CNS_INT 1 => $c1 {IntCns 1} N002 [001317] LCL_VAR V09 loc5 d:5 => $VN.Void Tree [001318] assigned VN to local var V09/5: $c1 {IntCns 1} N003 [001318] ASG => $VN.Void ***** BB46, STMT00283(after) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 finish(BB46). Succ(BB47). SSA PHI definition: set VN of local 36/3 to $901 {PhiDef($24, $3, $3e4)} . SSA PHI definition: set VN of local 20/4 to $2b3 {PhiDef($14, $4, $948)} . SSA PHI definition: set VN of local 14/3 to $2b4 {PhiDef($e, $3, $544)} . SSA PHI definition: set VN of local 8/3 to $2b5 {PhiDef($8, $3, $350)} . Building phi application: $ec = SSA# 42. Building phi application: $e0 = SSA# 8. Building phi application: $6cd = phi($e0, $ec). The SSA definition for GcHeap (#10) at start of BB136 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB136, STMT00071(before) N004 ( 5, 6) [000278] ----------- * JTRUE void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 N001 [000275] LCL_VAR V18 loc14 u:1 => N002 [000276] CNS_INT 69 => $d2 {IntCns 69} N003 [000277] GT => N004 [000278] JTRUE => $VN.Void ***** BB136, STMT00071(after) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 finish(BB136). Succ(BB137). Not yet completed. All preds complete, adding to allDone. Succ(BB141). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB141 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB141 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB141, STMT00072(before) N004 ( 5, 6) [000282] ----------- * JTRUE void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 N001 [000279] LCL_VAR V18 loc14 u:1 => N002 [000280] CNS_INT 92 => $d3 {IntCns 92} N003 [000281] EQ => N004 [000282] JTRUE => $VN.Void ***** BB141, STMT00072(after) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 finish(BB141). Succ(BB142). Not yet completed. All preds complete, adding to allDone. Succ(BB200). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB200 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB200 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB200, STMT00074(before) N004 ( 7, 8) [000289] ----------- * JTRUE void N003 ( 5, 6) [000288] J------N--- \--* GE int N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000283] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [002242] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000288] GE => $94d {GE($898, $342)} N004 [000289] JTRUE => $VN.Void ***** BB200, STMT00074(after) N004 ( 7, 8) [000289] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB200). Succ(BB201). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB201 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB201 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB201, STMT00075(before) N010 ( 13, 15) [000300] ---XG------ * JTRUE void N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000295] ----------- | \--* LSH long N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 N001 [000290] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000291] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N003 [000292] CAST => $3e5 {$898, long <- int} N004 [000294] CNS_INT 1 => $204 {LngCns: 1} N005 [000295] LSH => $3e6 {LSH($3e5, $204)} N006 [000296] ADD => $3e7 {ADD($3c4, $3e6)} N007 [000297] IND => N008 [000298] CNS_INT 0 => $c0 {IntCns 0} N009 [000299] EQ => N010 [000300] JTRUE => $87a {norm=$VN.Void, exc=$879 {NullPtrExc($3e7)}} ***** BB201, STMT00075(after) N010 ( 13, 15) [000300] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 finish(BB201). Succ(BB202). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB202 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB202 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB202, STMT00077(before) N003 ( 1, 3) [000310] -A------R-- * ASG int N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 N001 [000303] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N002 [000309] LCL_VAR V51 tmp11 d:1 => $VN.Void Tree [000310] assigned VN to local var V51/1: $898 {ADD($c1, $2ae)} N003 [000310] ASG => $VN.Void ***** BB202, STMT00077(after) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 --------- ***** BB202, STMT00076(before) N005 ( 3, 4) [000308] -A------R-- * ASG int N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 N003 ( 3, 4) [000306] ----------- \--* ADD int N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 N001 [000304] LCL_VAR V16 loc12 u:5 (last use) => $898 {ADD($c1, $2ae)} N002 [000305] CNS_INT 1 => $c1 {IntCns 1} N003 [000306] ADD => $952 {ADD($c1, $898)} N004 [000307] LCL_VAR V16 loc12 d:12 => $VN.Void Tree [000308] assigned VN to local var V16/12: $952 {ADD($c1, $898)} N005 [000308] ASG => $VN.Void ***** BB202, STMT00076(after) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB202, STMT00458(before) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000315] ----------- \--* LSH long N003 ( 2, 3) [000312] ----------- +--* CAST long <- int N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 N001 [000302] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000311] LCL_VAR V51 tmp11 u:1 (last use) => $898 {ADD($c1, $2ae)} N003 [000312] CAST => $3e5 {$898, long <- int} N004 [000314] CNS_INT 1 => $204 {LngCns: 1} N005 [000315] LSH => $3e6 {LSH($3e5, $204)} N006 [000316] ADD => $3e7 {ADD($3c4, $3e6)} N007 [000317] IND => N008 [002282] LCL_VAR V123 tmp83 d:1 => $VN.Void Tree [002283] assigned VN to local var V123/1: N009 [002283] ASG => $87a {norm=$VN.Void, exc=$879 {NullPtrExc($3e7)}} ***** BB202, STMT00458(after) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000315] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 --------- ***** BB202, STMT00451(before) N006 ( 4, 3) [002246] -A-XG---R-- * ASG int N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 N001 [000301] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003026] CNS_INT 8 => $201 {LngCns: 8} N003 [003027] ADD => $25a {ADD($100, $201)} N004 [002244] IND => N005 [002245] LCL_VAR V122 tmp82 d:1 => $VN.Void Tree [002246] assigned VN to local var V122/1: N006 [002246] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB202, STMT00451(after) N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 --------- ***** BB202, STMT00453(before) N007 ( 8, 7) [002253] ---XG------ * JTRUE void N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 N001 [002247] LCL_VAR V122 tmp82 u:1 => N002 [002248] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [003030] CNS_INT 24 => $20c {LngCns: 24} N004 [003031] ADD => $25b {ADD($100, $20c)} N005 [002286] IND => N006 [002252] GE => N007 [002253] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB202, STMT00453(after) N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c finish(BB202). Succ(BB203). Not yet completed. All preds complete, adding to allDone. Succ(BB204). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB204 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB204 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB204, STMT00454(before) N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn N001 [002254] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002255] LCL_VAR V123 tmp83 u:1 (last use) => N003 [003044] CNS_INT(h) 0x4000000000435c58 ftn => $53 {Hnd const: 0x4000000000435C58} fgCurMemoryVN[GcHeap] assigned for CALL at [002256] to VN: $1d2. N004 [002256] CALL r2r_ind => $VN.Void ***** BB204, STMT00454(after) N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 finish(BB204). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB203 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB203 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB203, STMT00455(before) N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 N003 ( 3, 4) [003037] -----O----- \--* ADD byref N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 N001 [003035] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003036] CNS_INT 16 => $200 {LngCns: 16} N003 [003037] ADD => $25c {ADD($100, $200)} N004 [002261] LCL_VAR V124 tmp84 d:1 => $VN.Void Tree [002262] assigned VN to local var V124/1: $25c {ADD($100, $200)} N005 [002262] ASG => $VN.Void ***** BB203, STMT00455(after) N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 --------- ***** BB203, STMT00456(before) N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) N001 [002259] LCL_VAR V122 tmp82 u:1 => N002 [002264] LCL_VAR V124 tmp84 u:1 => $25c {ADD($100, $200)} N003 [003039] CNS_INT 8 => $201 {LngCns: 8} N004 [003040] ADD => $25d {ADD($201, $25c)} N005 [002265] IND => N006 [002266] BOUNDS_CHECK_Rng => N007 [002263] LCL_VAR V124 tmp84 u:1 (last use) => $25c {ADD($100, $200)} N008 [002270] IND => N009 [002260] LCL_VAR V122 tmp82 u:1 => N010 [002267] CAST => N011 [002268] CNS_INT 1 => $204 {LngCns: 1} N012 [002269] LSH => N013 [002271] ADD => N014 [003041] IND => N015 [002272] COMMA => N016 [002273] LCL_VAR V123 tmp83 u:1 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002275] to VN: $1d3. N017 [002275] ASG => ***** BB203, STMT00456(after) N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) --------- ***** BB203, STMT00457(before) N008 ( 8, 8) [002281] -A-XG---R-- * ASG int N007 ( 4, 3) [002280] D--XG--N--- +--* IND int N006 ( 3, 4) [003043] -------N--- | \--* ADD byref N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 N001 [002277] LCL_VAR V122 tmp82 u:1 (last use) => N002 [002278] CNS_INT 1 => $c1 {IntCns 1} N003 [002279] ADD => N004 [002276] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [003042] CNS_INT 8 => $201 {LngCns: 8} N006 [003043] ADD => $25a {ADD($100, $201)} N007 [002280] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002281] to VN: $1d4. N008 [002281] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB203, STMT00457(after) N008 ( 8, 8) [002281] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002280] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 finish(BB203). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB142 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB142 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB142, STMT00079(before) N004 ( 5, 6) [000322] ----------- * JTRUE void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 N001 [000319] LCL_VAR V18 loc14 u:1 => N002 [000320] CNS_INT 101 => $d4 {IntCns 101} N003 [000321] EQ => N004 [000322] JTRUE => $VN.Void ***** BB142, STMT00079(after) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 finish(BB142). Succ(BB143). Not yet completed. All preds complete, adding to allDone. Succ(BB205). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB143 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB143 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB143, STMT00125(before) N004 ( 5, 8) [000584] ----------- * JTRUE void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 N001 [000581] LCL_VAR V18 loc14 u:1 => N002 [000582] CNS_INT 0x2030 => $d5 {IntCns 0x2030} N003 [000583] NE => N004 [000584] JTRUE => $VN.Void ***** BB143, STMT00125(after) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 finish(BB143). Succ(BB144). Not yet completed. All preds complete, adding to allDone. Succ(BB242). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB144 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB144 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB144, STMT00429(before) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] N001 [000586] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N002 [002848] CNS_INT 136 Fseq[] => $20e {LngCns: 136} N003 [002849] ADD => $26c {ADD($180, $20e)} VNForHandle() is $54, fieldType is ref, size = 8 VNForMapSelect($6ce, $54):mem returns $799 {$6ce[$54]} VNForMapSelect($799, $180):ref returns $98f {$799[$180]} N004 [002066] IND => N005 [002118] LCL_VAR V110 tmp70 d:1 => $VN.Void Tree [002119] assigned VN to local var V110/1: N006 [002119] ASG => $321 {norm=$VN.Void, exc=$315 {NullPtrExc($180)}} ***** BB144, STMT00429(after) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e finish(BB144). Succ(BB181). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB181 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB181 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB181, STMT00420(before) N004 ( 5, 6) [002071] ----------- * JTRUE void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null N001 [002068] LCL_VAR V110 tmp70 u:1 => N002 [002069] CNS_INT null => $VN.Null N003 [002070] EQ => N004 [002071] JTRUE => $VN.Void ***** BB181, STMT00420(after) N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null finish(BB181). Succ(BB182). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB182 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB182 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB182, STMT00421(before) N006 ( 4, 3) [002074] -A-XG---R-- * ASG int N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 N001 [000585] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002941] CNS_INT 8 => $201 {LngCns: 8} N003 [002942] ADD => $25a {ADD($100, $201)} N004 [002072] IND => N005 [002073] LCL_VAR V111 tmp71 d:1 => $VN.Void Tree [002074] assigned VN to local var V111/1: N006 [002074] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB182, STMT00421(after) N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 --------- ***** BB182, STMT00422(before) N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 N001 [002075] LCL_VAR V110 tmp70 u:1 => N002 [002076] ARR_LENGTH => N003 [002077] CNS_INT 1 => $c1 {IntCns 1} N004 [002078] NE => N005 [002079] JTRUE => ***** BB182, STMT00422(after) N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 finish(BB182). Succ(BB183). Not yet completed. All preds complete, adding to allDone. Succ(BB185). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB183 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB183 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB183, STMT00425(before) N007 ( 8, 7) [002089] ---XG------ * JTRUE void N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 N001 [002083] LCL_VAR V111 tmp71 u:1 => N002 [002084] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [002945] CNS_INT 24 => $20c {LngCns: 24} N004 [002946] ADD => $25b {ADD($100, $20c)} N005 [002122] IND => N006 [002088] GE => N007 [002089] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB183, STMT00425(after) N007 ( 8, 7) [002089] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c finish(BB183). Succ(BB184). Not yet completed. All preds complete, adding to allDone. Succ(BB185). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB185 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB185 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB185, STMT00423(before) N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn N001 [002080] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002081] LCL_VAR V110 tmp70 u:1 (last use) => N003 [002972] CNS_INT(h) 0x4000000000431d58 ftn => $4f {Hnd const: 0x4000000000431D58} fgCurMemoryVN[GcHeap] assigned for CALL at [002082] to VN: $1d5. N004 [002082] CALL r2r_ind => $VN.Void ***** BB185, STMT00423(after) N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f finish(BB185). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB184 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB184 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB184, STMT00426(before) N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 N003 ( 3, 4) [002952] -----O----- \--* ADD byref N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 N001 [002950] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002951] CNS_INT 16 => $200 {LngCns: 16} N003 [002952] ADD => $25c {ADD($100, $200)} N004 [002094] LCL_VAR V112 tmp72 d:1 => $VN.Void Tree [002095] assigned VN to local var V112/1: $25c {ADD($100, $200)} N005 [002095] ASG => $VN.Void ***** BB184, STMT00426(after) N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 --------- ***** BB184, STMT00427(before) N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $81 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 N001 [002092] LCL_VAR V111 tmp71 u:1 => N002 [002097] LCL_VAR V112 tmp72 u:1 => $25c {ADD($100, $200)} N003 [002954] CNS_INT 8 => $201 {LngCns: 8} N004 [002955] ADD => $25d {ADD($201, $25c)} N005 [002098] IND => N006 [002099] BOUNDS_CHECK_Rng => N007 [002096] LCL_VAR V112 tmp72 u:1 (last use) => $25c {ADD($100, $200)} N008 [002103] IND => N009 [002093] LCL_VAR V111 tmp71 u:1 => N010 [002100] CAST => N011 [002101] CNS_INT 1 => $204 {LngCns: 1} N012 [002102] LSH => N013 [002104] ADD => N014 [002956] IND => N015 [002105] COMMA => N016 [002107] CNS_INT 0 => $c0 {IntCns 0} N017 [002106] LCL_VAR V110 tmp70 u:1 => N018 [002959] ARR_LENGTH => N019 [002960] BOUNDS_CHECK_Rng => N020 [002957] LCL_VAR V110 tmp70 u:1 (last use) => N021 [002963] CNS_INT 12 => $20d {LngCns: 12} N022 [002964] ADD => VNForHandle(arrElemType: ushort) is $41 N023 [002966] ARR_ADDR => $85 {PtrToArrElem($41, $98f, $205, $205)} Array element load: elemTypeEq is $41 for short[] VNForMapSelect($6ce, $41):mem returns $79b {$6ce[$41]} GcHeap[elemTypeEq: $41] is $79b VNForMapSelect($79b, $98f):mem returns $79c {$79b[$98f]} GcHeap[elemTypeEq][array: $98f] is $79c VNForMapSelect($79c, $205):short returns $8c1 {$79c[$205]} GcHeap[elemTypeEq][array][index: $205] is $8c1 VNForLoadStoreBitcast returns $656 {BitCast($8c1)} N024 [002969] IND => ($8c1)}, c:$60d {MemOpaque:L03}> N025 [002967] COMMA => ($8c1)}, exc=$9a4( {NullPtrExc($98f)}, {IndexOutOfRangeExc($c0, $2da)})}, c:$658 {norm=$60d {MemOpaque:L03}, exc=$9a5( {NullPtrExc($19e)}, {IndexOutOfRangeExc($c0, $2db)})}> fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002111] to VN: $1d6. N026 [002111] ASG => ***** BB184, STMT00427(after) N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d --------- ***** BB184, STMT00428(before) N008 ( 8, 8) [002117] -A-XG---R-- * ASG int N007 ( 4, 3) [002116] D--XG--N--- +--* IND int N006 ( 3, 4) [002971] -------N--- | \--* ADD byref N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 N001 [002113] LCL_VAR V111 tmp71 u:1 (last use) => N002 [002114] CNS_INT 1 => $c1 {IntCns 1} N003 [002115] ADD => N004 [002112] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [002970] CNS_INT 8 => $201 {LngCns: 8} N006 [002971] ADD => $25a {ADD($100, $201)} N007 [002116] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002117] to VN: $1d7. N008 [002117] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB184, STMT00428(after) N008 ( 8, 8) [002117] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002116] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 finish(BB184). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB137 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB137 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB137, STMT00129(before) N004 ( 13, 9) [000596] ----------- * SWITCH void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 N001 [000593] LCL_VAR V18 loc14 u:1 => N002 [000594] CNS_INT -34 => $d6 {IntCns 4294967262} N003 [000595] ADD => N004 [000596] SWITCH => $VN.Void ***** BB137, STMT00129(after) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 finish(BB137). Succ(BB194). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB145). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB242). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Succ(BB186). Not yet completed. All preds complete, adding to allDone. Succ(BB138). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB138 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB138 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB138, STMT00130(before) N004 ( 13, 9) [000600] ----------- * SWITCH void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 N001 [000597] LCL_VAR V18 loc14 u:1 => N002 [000598] CNS_INT -44 => $d7 {IntCns 4294967252} N003 [000599] ADD => N004 [000600] SWITCH => $VN.Void ***** BB138, STMT00130(after) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 finish(BB138). Succ(BB245). Succ(BB242). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Succ(BB171). Not yet completed. All preds complete, adding to allDone. Succ(BB145). Not yet completed. All preds complete, adding to allDone. Succ(BB139). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB139 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB139 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB139, STMT00131(before) N004 ( 5, 6) [000604] ----------- * JTRUE void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 N001 [000601] LCL_VAR V18 loc14 u:1 => N002 [000602] CNS_INT 69 => $d2 {IntCns 69} N003 [000603] EQ => N004 [000604] JTRUE => $VN.Void ***** BB139, STMT00131(after) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 finish(BB139). Succ(BB140). Not yet completed. All preds complete, adding to allDone. Succ(BB205). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB205 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB205 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB205, STMT00080(before) N003 ( 1, 3) [000325] -A------R-- * ASG int N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 N001 [003045] CNS_INT 0 => $c0 {IntCns 0} N002 [000324] LCL_VAR V37 loc33 d:1 => $VN.Void Tree [000325] assigned VN to local var V37/1: $c0 {IntCns 0} N003 [000325] ASG => $VN.Void ***** BB205, STMT00080(after) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB205, STMT00081(before) N003 ( 1, 3) [000328] -A------R-- * ASG int N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 N001 [000326] CNS_INT 0 => $c0 {IntCns 0} N002 [000327] LCL_VAR V38 loc34 d:1 => $VN.Void Tree [000328] assigned VN to local var V38/1: $c0 {IntCns 0} N003 [000328] ASG => $VN.Void ***** BB205, STMT00081(after) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 --------- ***** BB205, STMT00082(before) N004 ( 5, 6) [000332] ----------- * JTRUE void N003 ( 3, 4) [000331] J------N--- \--* EQ int N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 N001 [000329] LCL_VAR V09 loc5 u:3 => $4c6 {PhiDef($9, $3, $34c)} N002 [000330] CNS_INT 0 => $c0 {IntCns 0} N003 [000331] EQ => $97d {EQ($4c6, $c0)} N004 [000332] JTRUE => $VN.Void ***** BB205, STMT00082(after) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 finish(BB205). Succ(BB206). Not yet completed. All preds complete, adding to allDone. Succ(BB227). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB227 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB227 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB227, STMT00468(before) N006 ( 4, 3) [002351] -A-XG---R-- * ASG int N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 N001 [000333] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003070] CNS_INT 8 => $201 {LngCns: 8} N003 [003071] ADD => $25a {ADD($100, $201)} N004 [002349] IND => N005 [002350] LCL_VAR V129 tmp89 d:1 => $VN.Void Tree [002351] assigned VN to local var V129/1: N006 [002351] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB227, STMT00468(after) N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 --------- ***** BB227, STMT00470(before) N007 ( 8, 7) [002358] ---XG------ * JTRUE void N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 N001 [002352] LCL_VAR V129 tmp89 u:1 => N002 [002353] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [003074] CNS_INT 24 => $20c {LngCns: 24} N004 [003075] ADD => $25b {ADD($100, $20c)} N005 [002388] IND => N006 [002357] GE => N007 [002358] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB227, STMT00470(after) N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c finish(BB227). Succ(BB228). Not yet completed. All preds complete, adding to allDone. Succ(BB229). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB229 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB229 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB229, STMT00471(before) N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn N001 [002359] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [000334] LCL_VAR V18 loc14 u:1 (last use) => N003 [003088] CNS_INT(h) 0x4000000000435c58 ftn => $53 {Hnd const: 0x4000000000435C58} fgCurMemoryVN[GcHeap] assigned for CALL at [002360] to VN: $1d8. N004 [002360] CALL r2r_ind => $VN.Void ***** BB229, STMT00471(after) N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 finish(BB229). Succ(BB230). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB228 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB228 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB228, STMT00472(before) N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 N003 ( 3, 4) [003081] -----O----- \--* ADD byref N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 N001 [003079] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003080] CNS_INT 16 => $200 {LngCns: 16} N003 [003081] ADD => $25c {ADD($100, $200)} N004 [002365] LCL_VAR V130 tmp90 d:1 => $VN.Void Tree [002366] assigned VN to local var V130/1: $25c {ADD($100, $200)} N005 [002366] ASG => $VN.Void ***** BB228, STMT00472(after) N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 --------- ***** BB228, STMT00473(before) N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) N001 [002363] LCL_VAR V129 tmp89 u:1 => N002 [002368] LCL_VAR V130 tmp90 u:1 => $25c {ADD($100, $200)} N003 [003083] CNS_INT 8 => $201 {LngCns: 8} N004 [003084] ADD => $25d {ADD($201, $25c)} N005 [002369] IND => N006 [002370] BOUNDS_CHECK_Rng => N007 [002367] LCL_VAR V130 tmp90 u:1 (last use) => $25c {ADD($100, $200)} N008 [002374] IND => N009 [002364] LCL_VAR V129 tmp89 u:1 => N010 [002371] CAST => N011 [002372] CNS_INT 1 => $204 {LngCns: 1} N012 [002373] LSH => N013 [002375] ADD => N014 [003085] IND => N015 [002376] COMMA => N016 [002377] LCL_VAR V18 loc14 u:1 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002379] to VN: $1d9. N017 [002379] ASG => ***** BB228, STMT00473(after) N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) --------- ***** BB228, STMT00474(before) N008 ( 8, 8) [002385] -A-XG---R-- * ASG int N007 ( 4, 3) [002384] D--XG--N--- +--* IND int N006 ( 3, 4) [003087] -------N--- | \--* ADD byref N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 N001 [002381] LCL_VAR V129 tmp89 u:1 (last use) => N002 [002382] CNS_INT 1 => $c1 {IntCns 1} N003 [002383] ADD => N004 [002380] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [003086] CNS_INT 8 => $201 {LngCns: 8} N006 [003087] ADD => $25a {ADD($100, $201)} N007 [002384] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002385] to VN: $1da. N008 [002385] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB228, STMT00474(after) N008 ( 8, 8) [002385] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002384] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 finish(BB228). Succ(BB230). Not yet completed. All preds complete, adding to allDone. Building phi application: $ce = SSA# 20. Building phi application: $d0 = SSA# 19. Building phi application: $6cf = phi($d0, $ce). The SSA definition for GcHeap (#13) at start of BB230 is $6d0 {PhiMemoryDef($55, $6cf)} ***** BB230, STMT00085(before) N004 ( 7, 8) [000342] ----------- * JTRUE void N003 ( 5, 6) [000341] J------N--- \--* GE int N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000336] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [002394] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000341] GE => $94d {GE($898, $342)} N004 [000342] JTRUE => $VN.Void ***** BB230, STMT00085(after) N004 ( 7, 8) [000342] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB230). Succ(BB231). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#13) at start of BB231 is $6d0 {PhiMemoryDef($55, $6cf)} The SSA definition for GcHeap (#13) at start of BB231 is $6d0 {PhiMemoryDef($55, $6cf)} ***** BB231, STMT00086(before) N010 ( 13, 15) [000353] ---XG------ * JTRUE void N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000348] ----------- | \--* LSH long N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 N001 [000343] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000344] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N003 [000345] CAST => $3e5 {$898, long <- int} N004 [000347] CNS_INT 1 => $204 {LngCns: 1} N005 [000348] LSH => $3e6 {LSH($3e5, $204)} N006 [000349] ADD => $3e7 {ADD($3c4, $3e6)} N007 [000350] IND => N008 [000351] CNS_INT 43 => $d9 {IntCns 43} N009 [000352] EQ => N010 [000353] JTRUE => $87a {norm=$VN.Void, exc=$879 {NullPtrExc($3e7)}} ***** BB231, STMT00086(after) N010 ( 13, 15) [000353] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 finish(BB231). Succ(BB232). Not yet completed. All preds complete, adding to allDone. Succ(BB233). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#13) at start of BB232 is $6d0 {PhiMemoryDef($55, $6cf)} The SSA definition for GcHeap (#13) at start of BB232 is $6d0 {PhiMemoryDef($55, $6cf)} ***** BB232, STMT00096(before) N010 ( 13, 15) [000418] ---XG------ * JTRUE void N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000413] ----------- | \--* LSH long N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 N001 [000408] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000409] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N003 [000410] CAST => $3e5 {$898, long <- int} N004 [000412] CNS_INT 1 => $204 {LngCns: 1} N005 [000413] LSH => $3e6 {LSH($3e5, $204)} N006 [000414] ADD => $3e7 {ADD($3c4, $3e6)} N007 [000415] IND => N008 [000416] CNS_INT 45 => $da {IntCns 45} N009 [000417] NE => N010 [000418] JTRUE => $87a {norm=$VN.Void, exc=$879 {NullPtrExc($3e7)}} ***** BB232, STMT00096(after) N010 ( 13, 15) [000418] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000413] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da finish(BB232). Succ(BB233). Not yet completed. All preds complete, adding to allDone. Succ(BB239). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#13) at start of BB233 is $6d0 {PhiMemoryDef($55, $6cf)} The SSA definition for GcHeap (#13) at start of BB233 is $6d0 {PhiMemoryDef($55, $6cf)} ***** BB233, STMT00088(before) N003 ( 1, 3) [000363] -A------R-- * ASG int N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 N001 [000356] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N002 [000362] LCL_VAR V52 tmp12 d:1 => $VN.Void Tree [000363] assigned VN to local var V52/1: $898 {ADD($c1, $2ae)} N003 [000363] ASG => $VN.Void ***** BB233, STMT00088(after) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 --------- ***** BB233, STMT00087(before) N005 ( 3, 4) [000361] -A------R-- * ASG int N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 N003 ( 3, 4) [000359] ----------- \--* ADD int N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 N001 [000357] LCL_VAR V16 loc12 u:5 (last use) => $898 {ADD($c1, $2ae)} N002 [000358] CNS_INT 1 => $c1 {IntCns 1} N003 [000359] ADD => $952 {ADD($c1, $898)} N004 [000360] LCL_VAR V16 loc12 d:8 => $VN.Void Tree [000361] assigned VN to local var V16/8: $952 {ADD($c1, $898)} N005 [000361] ASG => $VN.Void ***** BB233, STMT00087(after) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB233, STMT00483(before) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000368] ----------- \--* LSH long N003 ( 2, 3) [000365] ----------- +--* CAST long <- int N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 N001 [000355] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000364] LCL_VAR V52 tmp12 u:1 (last use) => $898 {ADD($c1, $2ae)} N003 [000365] CAST => $3e5 {$898, long <- int} N004 [000367] CNS_INT 1 => $204 {LngCns: 1} N005 [000368] LSH => $3e6 {LSH($3e5, $204)} N006 [000369] ADD => $3e7 {ADD($3c4, $3e6)} N007 [000370] IND => N008 [002434] LCL_VAR V133 tmp93 d:1 => $VN.Void Tree [002435] assigned VN to local var V133/1: N009 [002435] ASG => $87a {norm=$VN.Void, exc=$879 {NullPtrExc($3e7)}} ***** BB233, STMT00483(after) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000368] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000365] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 $204 --------- ***** BB233, STMT00476(before) N006 ( 4, 3) [002398] -A-XG---R-- * ASG int N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 N001 [000354] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003089] CNS_INT 8 => $201 {LngCns: 8} N003 [003090] ADD => $25a {ADD($100, $201)} N004 [002396] IND => N005 [002397] LCL_VAR V132 tmp92 d:1 => $VN.Void Tree [002398] assigned VN to local var V132/1: N006 [002398] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB233, STMT00476(after) N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 --------- ***** BB233, STMT00478(before) N007 ( 8, 7) [002405] ---XG------ * JTRUE void N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 N001 [002399] LCL_VAR V132 tmp92 u:1 => N002 [002400] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [003093] CNS_INT 24 => $20c {LngCns: 24} N004 [003094] ADD => $25b {ADD($100, $20c)} N005 [002438] IND => N006 [002404] GE => N007 [002405] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB233, STMT00478(after) N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c finish(BB233). Succ(BB234). Not yet completed. All preds complete, adding to allDone. Succ(BB235). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#13) at start of BB235 is $6d0 {PhiMemoryDef($55, $6cf)} The SSA definition for GcHeap (#13) at start of BB235 is $6d0 {PhiMemoryDef($55, $6cf)} ***** BB235, STMT00479(before) N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn N001 [002406] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002407] LCL_VAR V133 tmp93 u:1 (last use) => N003 [003107] CNS_INT(h) 0x4000000000435c58 ftn => $53 {Hnd const: 0x4000000000435C58} fgCurMemoryVN[GcHeap] assigned for CALL at [002408] to VN: $1db. N004 [002408] CALL r2r_ind => $VN.Void ***** BB235, STMT00479(after) N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 finish(BB235). Succ(BB239). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#13) at start of BB234 is $6d0 {PhiMemoryDef($55, $6cf)} The SSA definition for GcHeap (#13) at start of BB234 is $6d0 {PhiMemoryDef($55, $6cf)} ***** BB234, STMT00480(before) N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 N003 ( 3, 4) [003100] -----O----- \--* ADD byref N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 N001 [003098] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003099] CNS_INT 16 => $200 {LngCns: 16} N003 [003100] ADD => $25c {ADD($100, $200)} N004 [002413] LCL_VAR V134 tmp94 d:1 => $VN.Void Tree [002414] assigned VN to local var V134/1: $25c {ADD($100, $200)} N005 [002414] ASG => $VN.Void ***** BB234, STMT00480(after) N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 --------- ***** BB234, STMT00481(before) N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) N001 [002411] LCL_VAR V132 tmp92 u:1 => N002 [002416] LCL_VAR V134 tmp94 u:1 => $25c {ADD($100, $200)} N003 [003102] CNS_INT 8 => $201 {LngCns: 8} N004 [003103] ADD => $25d {ADD($201, $25c)} N005 [002417] IND => N006 [002418] BOUNDS_CHECK_Rng => N007 [002415] LCL_VAR V134 tmp94 u:1 (last use) => $25c {ADD($100, $200)} N008 [002422] IND => N009 [002412] LCL_VAR V132 tmp92 u:1 => N010 [002419] CAST => N011 [002420] CNS_INT 1 => $204 {LngCns: 1} N012 [002421] LSH => N013 [002423] ADD => N014 [003104] IND => N015 [002424] COMMA => N016 [002425] LCL_VAR V133 tmp93 u:1 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002427] to VN: $1dc. N017 [002427] ASG => ***** BB234, STMT00481(after) N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) --------- ***** BB234, STMT00482(before) N008 ( 8, 8) [002433] -A-XG---R-- * ASG int N007 ( 4, 3) [002432] D--XG--N--- +--* IND int N006 ( 3, 4) [003106] -------N--- | \--* ADD byref N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 N001 [002429] LCL_VAR V132 tmp92 u:1 (last use) => N002 [002430] CNS_INT 1 => $c1 {IntCns 1} N003 [002431] ADD => N004 [002428] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [003105] CNS_INT 8 => $201 {LngCns: 8} N006 [003106] ADD => $25a {ADD($100, $201)} N007 [002432] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002433] to VN: $1dd. N008 [002433] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB234, STMT00482(after) N008 ( 8, 8) [002433] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002432] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 finish(BB234). Succ(BB239). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#10) at start of BB206 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB206 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB206, STMT00098(before) N004 ( 7, 8) [000425] ----------- * JTRUE void N003 ( 5, 6) [000424] J------N--- \--* GE int N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000419] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [002292] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000424] GE => $94d {GE($898, $342)} N004 [000425] JTRUE => $VN.Void ***** BB206, STMT00098(after) N004 ( 7, 8) [000425] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB206). Succ(BB207). Not yet completed. All preds complete, adding to allDone. Succ(BB208). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB207 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB207 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB207, STMT00123(before) N010 ( 13, 15) [000575] ---XG------ * JTRUE void N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000570] ----------- | \--* LSH long N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 N001 [000565] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000566] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N003 [000567] CAST => $3e5 {$898, long <- int} N004 [000569] CNS_INT 1 => $204 {LngCns: 1} N005 [000570] LSH => $3e6 {LSH($3e5, $204)} N006 [000571] ADD => $3e7 {ADD($3c4, $3e6)} N007 [000572] IND => N008 [000573] CNS_INT 48 => $d8 {IntCns 48} N009 [000574] EQ => N010 [000575] JTRUE => $87a {norm=$VN.Void, exc=$879 {NullPtrExc($3e7)}} ***** BB207, STMT00123(after) N010 ( 13, 15) [000575] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 finish(BB207). Succ(BB208). Not yet completed. All preds complete, adding to allDone. Succ(BB218). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB208 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB208 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB208, STMT00100(before) N006 ( 9, 11) [000434] ----------- * JTRUE void N005 ( 7, 9) [000433] J------N--- \--* GE int N003 ( 3, 4) [000428] ----------- +--* ADD int N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000426] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N002 [000427] CNS_INT 1 => $c1 {IntCns 1} N003 [000428] ADD => $952 {ADD($c1, $898)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N004 [002296] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N005 [000433] GE => $9e2 {GE($952, $342)} N006 [000434] JTRUE => $VN.Void ***** BB208, STMT00100(after) N006 ( 9, 11) [000434] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB208). Succ(BB209). Not yet completed. All preds complete, adding to allDone. Succ(BB212). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB209 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB209 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB209, STMT00120(before) N010 ( 13, 15) [000548] ---XG------ * JTRUE void N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000543] ----------- | \--* LSH long N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 N001 [000538] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000539] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N003 [000540] CAST => $3e5 {$898, long <- int} N004 [000542] CNS_INT 1 => $204 {LngCns: 1} N005 [000543] LSH => $3e6 {LSH($3e5, $204)} N006 [000544] ADD => $3e7 {ADD($3c4, $3e6)} N007 [000545] IND => N008 [000546] CNS_INT 43 => $d9 {IntCns 43} N009 [000547] NE => N010 [000548] JTRUE => $87a {norm=$VN.Void, exc=$879 {NullPtrExc($3e7)}} ***** BB209, STMT00120(after) N010 ( 13, 15) [000548] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 finish(BB209). Succ(BB210). Not yet completed. All preds complete, adding to allDone. Succ(BB212). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#10) at start of BB210 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB210 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB210, STMT00121(before) N012 ( 15, 18) [000561] ---XG------ * JTRUE void N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 N007 ( 6, 9) [000556] ----------- | \--* LSH long N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int N004 ( 3, 4) [000552] ----------- | | \--* ADD int N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 N001 [000549] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000550] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N003 [000551] CNS_INT 1 => $c1 {IntCns 1} N004 [000552] ADD => $952 {ADD($c1, $898)} N005 [000553] CAST => $3f4 {$952, long <- int} N006 [000555] CNS_INT 1 => $204 {LngCns: 1} N007 [000556] LSH => $3f5 {LSH($3f4, $204)} N008 [000557] ADD => $3f6 {ADD($3c4, $3f5)} N009 [000558] IND => N010 [000559] CNS_INT 48 => $d8 {IntCns 48} N011 [000560] NE => N012 [000561] JTRUE => $a11 {norm=$VN.Void, exc=$a10 {NullPtrExc($3f6)}} ***** BB210, STMT00121(after) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 finish(BB210). Succ(BB211). Not yet completed. All preds complete, adding to allDone. Succ(BB212). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB212 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB212 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB212, STMT00102(before) N006 ( 9, 11) [000443] ----------- * JTRUE void N005 ( 7, 9) [000442] J------N--- \--* GE int N003 ( 3, 4) [000437] ----------- +--* ADD int N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000435] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N002 [000436] CNS_INT 1 => $c1 {IntCns 1} N003 [000437] ADD => $952 {ADD($c1, $898)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N004 [002300] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N005 [000442] GE => $9e2 {GE($952, $342)} N006 [000443] JTRUE => $VN.Void ***** BB212, STMT00102(after) N006 ( 9, 11) [000443] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000442] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000437] ----------- +--* ADD int $952 N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB212). Succ(BB213). Not yet completed. All preds complete, adding to allDone. Succ(BB215). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB213 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB213 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB213, STMT00104(before) N010 ( 13, 15) [000457] ---XG------ * JTRUE void N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000452] ----------- | \--* LSH long N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 N001 [000447] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000448] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N003 [000449] CAST => $3e5 {$898, long <- int} N004 [000451] CNS_INT 1 => $204 {LngCns: 1} N005 [000452] LSH => $3e6 {LSH($3e5, $204)} N006 [000453] ADD => $3e7 {ADD($3c4, $3e6)} N007 [000454] IND => N008 [000455] CNS_INT 45 => $da {IntCns 45} N009 [000456] NE => N010 [000457] JTRUE => $87a {norm=$VN.Void, exc=$879 {NullPtrExc($3e7)}} ***** BB213, STMT00104(after) N010 ( 13, 15) [000457] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000452] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da finish(BB213). Succ(BB214). Not yet completed. All preds complete, adding to allDone. Succ(BB215). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#10) at start of BB214 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB214 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB214, STMT00105(before) N012 ( 15, 18) [000470] ---XG------ * JTRUE void N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 N007 ( 6, 9) [000465] ----------- | \--* LSH long N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int N004 ( 3, 4) [000461] ----------- | | \--* ADD int N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 N001 [000458] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000459] LCL_VAR V16 loc12 u:5 => $898 {ADD($c1, $2ae)} N003 [000460] CNS_INT 1 => $c1 {IntCns 1} N004 [000461] ADD => $952 {ADD($c1, $898)} N005 [000462] CAST => $3f4 {$952, long <- int} N006 [000464] CNS_INT 1 => $204 {LngCns: 1} N007 [000465] LSH => $3f5 {LSH($3f4, $204)} N008 [000466] ADD => $3f6 {ADD($3c4, $3f5)} N009 [000467] IND => N010 [000468] CNS_INT 48 => $d8 {IntCns 48} N011 [000469] EQ => N012 [000470] JTRUE => $a11 {norm=$VN.Void, exc=$a10 {NullPtrExc($3f6)}} ***** BB214, STMT00105(after) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 finish(BB214). Succ(BB215). Not yet completed. All preds complete, adding to allDone. Succ(BB219). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB215 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB215 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB215, STMT00460(before) N006 ( 4, 3) [002304] -A-XG---R-- * ASG int N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 N001 [000444] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003047] CNS_INT 8 => $201 {LngCns: 8} N003 [003048] ADD => $25a {ADD($100, $201)} N004 [002302] IND => N005 [002303] LCL_VAR V126 tmp86 d:1 => $VN.Void Tree [002304] assigned VN to local var V126/1: N006 [002304] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB215, STMT00460(after) N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 --------- ***** BB215, STMT00462(before) N007 ( 8, 7) [002311] ---XG------ * JTRUE void N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 N001 [002305] LCL_VAR V126 tmp86 u:1 => N002 [002306] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [003051] CNS_INT 24 => $20c {LngCns: 24} N004 [003052] ADD => $25b {ADD($100, $20c)} N005 [002341] IND => N006 [002310] GE => N007 [002311] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB215, STMT00462(after) N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c finish(BB215). Succ(BB216). Not yet completed. All preds complete, adding to allDone. Succ(BB217). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB217 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB217 is $6ce {PhiMemoryDef($52, $6cd)} finish(BB217). Succ(BB244). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB216 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB216 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB216, STMT00464(before) N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 N003 ( 3, 4) [003058] -----O----- \--* ADD byref N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 N001 [003056] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003057] CNS_INT 16 => $200 {LngCns: 16} N003 [003058] ADD => $25c {ADD($100, $200)} N004 [002318] LCL_VAR V127 tmp87 d:1 => $VN.Void Tree [002319] assigned VN to local var V127/1: $25c {ADD($100, $200)} N005 [002319] ASG => $VN.Void ***** BB216, STMT00464(after) N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 --------- ***** BB216, STMT00465(before) N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) N001 [002316] LCL_VAR V126 tmp86 u:1 => N002 [002321] LCL_VAR V127 tmp87 u:1 => $25c {ADD($100, $200)} N003 [003060] CNS_INT 8 => $201 {LngCns: 8} N004 [003061] ADD => $25d {ADD($201, $25c)} N005 [002322] IND => N006 [002323] BOUNDS_CHECK_Rng => N007 [002320] LCL_VAR V127 tmp87 u:1 (last use) => $25c {ADD($100, $200)} N008 [002327] IND => N009 [002317] LCL_VAR V126 tmp86 u:1 => N010 [002324] CAST => N011 [002325] CNS_INT 1 => $204 {LngCns: 1} N012 [002326] LSH => N013 [002328] ADD => N014 [003062] IND => N015 [002329] COMMA => N016 [002330] LCL_VAR V18 loc14 u:1 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002332] to VN: $1de. N017 [002332] ASG => ***** BB216, STMT00465(after) N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) --------- ***** BB216, STMT00466(before) N008 ( 8, 8) [002338] -A-XG---R-- * ASG int N007 ( 4, 3) [002337] D--XG--N--- +--* IND int N006 ( 3, 4) [003064] -------N--- | \--* ADD byref N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 N001 [002334] LCL_VAR V126 tmp86 u:1 (last use) => N002 [002335] CNS_INT 1 => $c1 {IntCns 1} N003 [002336] ADD => N004 [002333] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [003063] CNS_INT 8 => $201 {LngCns: 8} N006 [003064] ADD => $25a {ADD($100, $201)} N007 [002337] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002338] to VN: $1df. N008 [002338] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB216, STMT00466(after) N008 ( 8, 8) [002338] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002337] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 finish(BB216). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB211 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB211 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB211, STMT00122(before) N003 ( 1, 3) [000564] -A------R-- * ASG int N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 N001 [003046] CNS_INT 1 => $c1 {IntCns 1} N002 [000563] LCL_VAR V37 loc33 d:4 => $VN.Void Tree [000564] assigned VN to local var V37/4: $c1 {IntCns 1} N003 [000564] ASG => $VN.Void ***** BB211, STMT00122(after) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 finish(BB211). Succ(BB219). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#10) at start of BB140 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB140 is $6ce {PhiMemoryDef($52, $6cd)} finish(BB140). Succ(BB242). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB242 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB242 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB242, STMT00494(before) N006 ( 4, 3) [002494] -A-XG---R-- * ASG int N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 N001 [000590] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003127] CNS_INT 8 => $201 {LngCns: 8} N003 [003128] ADD => $25a {ADD($100, $201)} N004 [002492] IND => N005 [002493] LCL_VAR V140 tmp100 d:1 => $VN.Void Tree [002494] assigned VN to local var V140/1: N006 [002494] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB242, STMT00494(after) N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 --------- ***** BB242, STMT00496(before) N007 ( 8, 7) [002501] ---XG------ * JTRUE void N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 N001 [002495] LCL_VAR V140 tmp100 u:1 => N002 [002496] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [003131] CNS_INT 24 => $20c {LngCns: 24} N004 [003132] ADD => $25b {ADD($100, $20c)} N005 [002531] IND => N006 [002500] GE => N007 [002501] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB242, STMT00496(after) N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c finish(BB242). Succ(BB243). Not yet completed. All preds complete, adding to allDone. Succ(BB244). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB244 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB244 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB244, STMT00497(before) N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn N001 [002502] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [000591] LCL_VAR V18 loc14 u:1 (last use) => N003 [003145] CNS_INT(h) 0x4000000000435c58 ftn => $53 {Hnd const: 0x4000000000435C58} fgCurMemoryVN[GcHeap] assigned for CALL at [002503] to VN: $1e0. N004 [002503] CALL r2r_ind => $VN.Void ***** BB244, STMT00497(after) N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 finish(BB244). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB243 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB243 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB243, STMT00498(before) N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 N003 ( 3, 4) [003138] -----O----- \--* ADD byref N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 N001 [003136] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003137] CNS_INT 16 => $200 {LngCns: 16} N003 [003138] ADD => $25c {ADD($100, $200)} N004 [002508] LCL_VAR V141 tmp101 d:1 => $VN.Void Tree [002509] assigned VN to local var V141/1: $25c {ADD($100, $200)} N005 [002509] ASG => $VN.Void ***** BB243, STMT00498(after) N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 --------- ***** BB243, STMT00499(before) N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) N001 [002506] LCL_VAR V140 tmp100 u:1 => N002 [002511] LCL_VAR V141 tmp101 u:1 => $25c {ADD($100, $200)} N003 [003140] CNS_INT 8 => $201 {LngCns: 8} N004 [003141] ADD => $25d {ADD($201, $25c)} N005 [002512] IND => N006 [002513] BOUNDS_CHECK_Rng => N007 [002510] LCL_VAR V141 tmp101 u:1 (last use) => $25c {ADD($100, $200)} N008 [002517] IND => N009 [002507] LCL_VAR V140 tmp100 u:1 => N010 [002514] CAST => N011 [002515] CNS_INT 1 => $204 {LngCns: 1} N012 [002516] LSH => N013 [002518] ADD => N014 [003142] IND => N015 [002519] COMMA => N016 [002520] LCL_VAR V18 loc14 u:1 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002522] to VN: $1e1. N017 [002522] ASG => ***** BB243, STMT00499(after) N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) --------- ***** BB243, STMT00500(before) N008 ( 8, 8) [002528] -A-XG---R-- * ASG int N007 ( 4, 3) [002527] D--XG--N--- +--* IND int N006 ( 3, 4) [003144] -------N--- | \--* ADD byref N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 N001 [002524] LCL_VAR V140 tmp100 u:1 (last use) => N002 [002525] CNS_INT 1 => $c1 {IntCns 1} N003 [002526] ADD => N004 [002523] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [003143] CNS_INT 8 => $201 {LngCns: 8} N006 [003144] ADD => $25a {ADD($100, $201)} N007 [002527] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002528] to VN: $1e2. N008 [002528] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB243, STMT00500(after) N008 ( 8, 8) [002528] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002527] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 finish(BB243). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB145 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB145 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB145, STMT00141(before) N004 ( 5, 6) [000642] ----------- * JTRUE void N003 ( 3, 4) [000641] J------N--- \--* GE int N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 N001 [000639] LCL_VAR V14 loc10 u:3 => $2b4 {PhiDef($e, $3, $544)} N002 [000640] CNS_INT 0 => $c0 {IntCns 0} N003 [000641] GE => $9ff {GE($2b4, $c0)} N004 [000642] JTRUE => $VN.Void ***** BB145, STMT00141(after) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 finish(BB145). Succ(BB146). Not yet completed. All preds complete, adding to allDone. Succ(BB150). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB150 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB150 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB150, STMT00142(before) N005 ( 8, 8) [000647] ---XG------ * JTRUE void N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 N001 [000643] LCL_VAR V36 loc32 u:3 => $901 {PhiDef($24, $3, $3e4)} N002 [000644] IND => N003 [000645] CNS_INT 0 => $c0 {IntCns 0} N004 [000646] NE => N005 [000647] JTRUE => $a27 {norm=$VN.Void, exc=$a26 {NullPtrExc($901)}} ***** BB150, STMT00142(after) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 finish(BB150). Succ(BB151). Not yet completed. All preds complete, adding to allDone. Succ(BB154). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB154 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB154 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB154, STMT00144(before) N003 ( 1, 3) [000656] -A------R-- * ASG long N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 N001 [000648] LCL_VAR V36 loc32 u:3 => $901 {PhiDef($24, $3, $3e4)} N002 [000655] LCL_VAR V56 tmp16 d:1 => $VN.Void Tree [000656] assigned VN to local var V56/1: $901 {PhiDef($24, $3, $3e4)} N003 [000656] ASG => $VN.Void ***** BB154, STMT00144(after) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 --------- ***** BB154, STMT00143(before) N005 ( 3, 4) [000654] -A------R-- * ASG long N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 N003 ( 3, 4) [000652] ----------- \--* ADD long N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V36 loc32 u:3 (last use) N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 N001 [000649] LCL_VAR V36 loc32 u:3 (last use) => $901 {PhiDef($24, $3, $3e4)} N002 [000651] CNS_INT 1 => $204 {LngCns: 1} N003 [000652] ADD => $3fb {ADD($204, $901)} N004 [000653] LCL_VAR V36 loc32 d:6 => $VN.Void Tree [000654] assigned VN to local var V36/6: $3fb {ADD($204, $901)} N005 [000654] ASG => $VN.Void ***** BB154, STMT00143(after) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V36 loc32 u:3 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 --------- ***** BB154, STMT00145(before) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) N001 [000657] LCL_VAR V56 tmp16 u:1 (last use) => $901 {PhiDef($24, $3, $3e4)} N002 [000658] IND => N003 [000659] LCL_VAR V57 tmp17 d:2 => $VN.Void Tree [000660] assigned VN to local var V57/2: N004 [000660] ASG => $a27 {norm=$VN.Void, exc=$a26 {NullPtrExc($901)}} ***** BB154, STMT00145(after) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 finish(BB154). Succ(BB155). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB151 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB151 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB151, STMT00157(before) N004 ( 5, 5) [000722] ----------- * JTRUE void N003 ( 3, 3) [000721] J------N--- \--* GT int N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 N001 [000719] LCL_VAR V08 loc4 u:3 => $2b5 {PhiDef($8, $3, $350)} N002 [000720] LCL_VAR V07 loc3 u:3 => $293 {PhiDef($2d, $1, $352)} N003 [000721] GT => $a86 {GT($2b5, $293)} N004 [000722] JTRUE => $VN.Void ***** BB151, STMT00157(after) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 finish(BB151). Succ(BB152). Not yet completed. All preds complete, adding to allDone. Succ(BB153). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB153 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB153 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB153, STMT00158(before) N003 ( 1, 3) [000725] -A------R-- * ASG int N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 N001 [000723] CNS_INT 48 => $d8 {IntCns 48} N002 [000724] LCL_VAR V57 tmp17 d:3 => $VN.Void Tree [000725] assigned VN to local var V57/3: $d8 {IntCns 48} N003 [000725] ASG => $VN.Void ***** BB153, STMT00158(after) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 finish(BB153). Succ(BB155). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#10) at start of BB152 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB152 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB152, STMT00159(before) N003 ( 1, 3) [000729] -A------R-- * ASG int N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 N001 [000727] CNS_INT 0 => $c0 {IntCns 0} N002 [000728] LCL_VAR V57 tmp17 d:4 => $VN.Void Tree [000729] assigned VN to local var V57/4: $c0 {IntCns 0} N003 [000729] ASG => $VN.Void ***** BB152, STMT00159(after) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 finish(BB152). Succ(BB155). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 36/5 to $902 {PhiDef($24, $5, $3fc)} . SSA PHI definition: set VN of local 57/1 to $2bc {PhiDef($39, $1, $34c)} . The SSA definition for ByrefExposed (#10) at start of BB155 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB155 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB155, STMT00146(before) N004 ( 2, 3) [000664] -A------R-- * ASG int N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) N001 [000662] LCL_VAR V57 tmp17 u:1 (last use) => $2bc {PhiDef($39, $1, $34c)} N002 [002851] CAST => $a87 {$2bc, int <- ushort <- int} N003 [000663] LCL_VAR V18 loc14 d:3 => $VN.Void Tree [000664] assigned VN to local var V18/3: $a87 {$2bc, int <- ushort <- int} N004 [000664] ASG => $VN.Void ***** BB155, STMT00146(after) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc finish(BB155). Succ(BB156). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB146 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB146 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB146, STMT00160(before) N005 ( 3, 4) [000735] -A------R-- * ASG int N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 N003 ( 3, 4) [000733] ----------- \--* ADD int N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 N001 [000731] LCL_VAR V14 loc10 u:3 (last use) => $2b4 {PhiDef($e, $3, $544)} N002 [000732] CNS_INT 1 => $c1 {IntCns 1} N003 [000733] ADD => $a88 {ADD($c1, $2b4)} N004 [000734] LCL_VAR V14 loc10 d:5 => $VN.Void Tree [000735] assigned VN to local var V14/5: $a88 {ADD($c1, $2b4)} N005 [000735] ASG => $VN.Void ***** BB146, STMT00160(after) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB146, STMT00161(before) N004 ( 5, 5) [000739] ----------- * JTRUE void N003 ( 3, 3) [000738] J------N--- \--* LE int N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 N001 [000736] LCL_VAR V08 loc4 u:3 => $2b5 {PhiDef($8, $3, $350)} N002 [000737] LCL_VAR V06 loc2 u:3 => $292 {PhiDef($2c, $1, $352)} N003 [000738] LE => $a89 {LE($2b5, $292)} N004 [000739] JTRUE => $VN.Void ***** BB146, STMT00161(after) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 finish(BB146). Succ(BB147). Not yet completed. All preds complete, adding to allDone. Succ(BB148). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB148 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB148 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB148, STMT00162(before) N003 ( 1, 3) [000742] -A------R-- * ASG int N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 N001 [000740] CNS_INT 48 => $d8 {IntCns 48} N002 [000741] LCL_VAR V58 tmp18 d:2 => $VN.Void Tree [000742] assigned VN to local var V58/2: $d8 {IntCns 48} N003 [000742] ASG => $VN.Void ***** BB148, STMT00162(after) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 finish(BB148). Succ(BB149). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB147 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB147 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB147, STMT00164(before) N003 ( 1, 3) [000749] -A------R-- * ASG int N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 N001 [000747] CNS_INT 0 => $c0 {IntCns 0} N002 [000748] LCL_VAR V58 tmp18 d:3 => $VN.Void Tree [000749] assigned VN to local var V58/3: $c0 {IntCns 0} N003 [000749] ASG => $VN.Void ***** BB147, STMT00164(after) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 finish(BB147). Succ(BB149). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 58/1 to $2bd {PhiDef($3a, $1, $352)} . The SSA definition for ByrefExposed (#10) at start of BB149 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB149 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB149, STMT00163(before) N004 ( 2, 3) [000746] -A------R-- * ASG int N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) N001 [000744] LCL_VAR V58 tmp18 u:1 (last use) => $2bd {PhiDef($3a, $1, $352)} N002 [002850] CAST => $a8a {$2bd, int <- ushort <- int} N003 [000745] LCL_VAR V18 loc14 d:4 => $VN.Void Tree [000746] assigned VN to local var V18/4: $a8a {$2bd, int <- ushort <- int} N004 [000746] ASG => $VN.Void ***** BB149, STMT00163(after) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd finish(BB149). Succ(BB156). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 36/4 to $903 {PhiDef($24, $4, $3fd)} . SSA PHI definition: set VN of local 14/4 to $2be {PhiDef($e, $4, $254)} . SSA PHI definition: set VN of local 18/2 to $5c9 {PhiDef($12, $2, $34b)} . The SSA definition for ByrefExposed (#10) at start of BB156 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB156 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB156, STMT00147(before) N004 ( 5, 6) [000668] ----------- * JTRUE void N003 ( 3, 4) [000667] J------N--- \--* EQ int N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 N001 [000665] LCL_VAR V18 loc14 u:2 => $5c9 {PhiDef($12, $2, $34b)} N002 [000666] CNS_INT 0 => $c0 {IntCns 0} N003 [000667] EQ => $a8b {EQ($5c9, $c0)} N004 [000668] JTRUE => $VN.Void ***** BB156, STMT00147(after) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 finish(BB156). Succ(BB157). Not yet completed. All preds complete, adding to allDone. Succ(BB170). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB157 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB157 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB157, STMT00390(before) N006 ( 4, 3) [001905] -A-XG---R-- * ASG int N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 N001 [000674] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002852] CNS_INT 8 => $201 {LngCns: 8} N003 [002853] ADD => $25a {ADD($100, $201)} N004 [001903] IND => N005 [001904] LCL_VAR V99 tmp59 d:1 => $VN.Void Tree [001905] assigned VN to local var V99/1: N006 [001905] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB157, STMT00390(after) N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 --------- ***** BB157, STMT00392(before) N007 ( 8, 7) [001912] ---XG------ * JTRUE void N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 N001 [001906] LCL_VAR V99 tmp59 u:1 => N002 [001907] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [002856] CNS_INT 24 => $20c {LngCns: 24} N004 [002857] ADD => $25b {ADD($100, $20c)} N005 [001942] IND => N006 [001911] GE => N007 [001912] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB157, STMT00392(after) N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c finish(BB157). Succ(BB158). Not yet completed. All preds complete, adding to allDone. Succ(BB159). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB159 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB159 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB159, STMT00393(before) N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn N001 [001913] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [000675] LCL_VAR V18 loc14 u:2 (last use) => $5c9 {PhiDef($12, $2, $34b)} N003 [002870] CNS_INT(h) 0x4000000000435c58 ftn => $53 {Hnd const: 0x4000000000435C58} fgCurMemoryVN[GcHeap] assigned for CALL at [001914] to VN: $1e3. N004 [001914] CALL r2r_ind => $VN.Void ***** BB159, STMT00393(after) N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 finish(BB159). Succ(BB160). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB158 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB158 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB158, STMT00394(before) N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 N003 ( 3, 4) [002863] -----O----- \--* ADD byref N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 N001 [002861] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002862] CNS_INT 16 => $200 {LngCns: 16} N003 [002863] ADD => $25c {ADD($100, $200)} N004 [001919] LCL_VAR V100 tmp60 d:1 => $VN.Void Tree [001920] assigned VN to local var V100/1: $25c {ADD($100, $200)} N005 [001920] ASG => $VN.Void ***** BB158, STMT00394(after) N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 --------- ***** BB158, STMT00395(before) N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) N001 [001917] LCL_VAR V99 tmp59 u:1 => N002 [001922] LCL_VAR V100 tmp60 u:1 => $25c {ADD($100, $200)} N003 [002865] CNS_INT 8 => $201 {LngCns: 8} N004 [002866] ADD => $25d {ADD($201, $25c)} N005 [001923] IND => N006 [001924] BOUNDS_CHECK_Rng => N007 [001921] LCL_VAR V100 tmp60 u:1 (last use) => $25c {ADD($100, $200)} N008 [001928] IND => N009 [001918] LCL_VAR V99 tmp59 u:1 => N010 [001925] CAST => N011 [001926] CNS_INT 1 => $204 {LngCns: 1} N012 [001927] LSH => N013 [001929] ADD => N014 [002867] IND => N015 [001930] COMMA => N016 [001931] LCL_VAR V18 loc14 u:2 (last use) => $5c9 {PhiDef($12, $2, $34b)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001933] to VN: $1e4. N017 [001933] ASG => ***** BB158, STMT00395(after) N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 --------- ***** BB158, STMT00396(before) N008 ( 8, 8) [001939] -A-XG---R-- * ASG int N007 ( 4, 3) [001938] D--XG--N--- +--* IND int N006 ( 3, 4) [002869] -------N--- | \--* ADD byref N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 N001 [001935] LCL_VAR V99 tmp59 u:1 (last use) => N002 [001936] CNS_INT 1 => $c1 {IntCns 1} N003 [001937] ADD => N004 [001934] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [002868] CNS_INT 8 => $201 {LngCns: 8} N006 [002869] ADD => $25a {ADD($100, $201)} N007 [001938] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001939] to VN: $1e5. N008 [001939] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB158, STMT00396(after) N008 ( 8, 8) [001939] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001938] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 finish(BB158). Succ(BB160). Not yet completed. All preds complete, adding to allDone. Building phi application: $ed = SSA# 38. Building phi application: $ee = SSA# 37. Building phi application: $6d1 = phi($ee, $ed). The SSA definition for GcHeap (#33) at start of BB160 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB160, STMT00150(before) N004 ( 5, 6) [000680] ----------- * JTRUE void N003 ( 3, 4) [000679] J------N--- \--* EQ int N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 N001 [000677] LCL_VAR V12 loc8 u:3 => $4c4 {PhiDef($c, $3, $34e)} N002 [000678] CNS_INT 0 => $c0 {IntCns 0} N003 [000679] EQ => $70a {EQ($4c4, $c0)} N004 [000680] JTRUE => $VN.Void ***** BB160, STMT00150(after) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 finish(BB160). Succ(BB161). Not yet completed. All preds complete, adding to allDone. Succ(BB170). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#33) at start of BB161 is $6d2 {PhiMemoryDef($56, $6d1)} The SSA definition for GcHeap (#33) at start of BB161 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB161, STMT00151(before) N004 ( 5, 6) [000684] ----------- * JTRUE void N003 ( 3, 4) [000683] J------N--- \--* LE int N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 N001 [000681] LCL_VAR V08 loc4 u:3 => $2b5 {PhiDef($8, $3, $350)} N002 [000682] CNS_INT 1 => $c1 {IntCns 1} N003 [000683] LE => $a93 {LE($2b5, $c1)} N004 [000684] JTRUE => $VN.Void ***** BB161, STMT00151(after) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 finish(BB161). Succ(BB162). Not yet completed. All preds complete, adding to allDone. Succ(BB170). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#33) at start of BB162 is $6d2 {PhiMemoryDef($56, $6d1)} The SSA definition for GcHeap (#33) at start of BB162 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB162, STMT00152(before) N004 ( 5, 6) [000688] ----------- * JTRUE void N003 ( 3, 4) [000687] J------N--- \--* LT int N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 N001 [000685] LCL_VAR V20 loc16 u:4 => $2b3 {PhiDef($14, $4, $948)} N002 [000686] CNS_INT 0 => $c0 {IntCns 0} N003 [000687] LT => $a94 {LT($2b3, $c0)} N004 [000688] JTRUE => $VN.Void ***** BB162, STMT00152(after) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 finish(BB162). Succ(BB163). Not yet completed. All preds complete, adding to allDone. Succ(BB170). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#33) at start of BB163 is $6d2 {PhiMemoryDef($56, $6d1)} The SSA definition for GcHeap (#33) at start of BB163 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB163, STMT00153(before) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 N008 ( 4, 6) [000700] ----------- | | \--* LSH long N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 N001 [000692] LCL_VAR V20 loc16 u:4 => $2b3 {PhiDef($14, $4, $948)} N002 [000696] LCL_VAR V144 tmp104 u:2 => $2a6 {PhiDef($90, $2, $258)} N003 [000697] BOUNDS_CHECK_Rng => $a34 {norm=$VN.Void, exc=$a33 {IndexOutOfRangeExc($2b3, $2a6)}} N004 [000701] LCL_VAR V143 tmp103 u:2 => $385 {PhiDef($8f, $2, $258)} N005 [000693] LCL_VAR V20 loc16 u:4 => $2b3 {PhiDef($14, $4, $948)} N006 [000698] CAST => $ac0 {$2b3, long <- uint} N007 [000699] CNS_INT 2 => $20a {LngCns: 2} N008 [000700] LSH => $ac1 {LSH($ac0, $20a)} N009 [000702] ADD => $a44 {ADD($385, $ac1)} N010 [002871] IND => N011 [000703] COMMA => N012 [000705] CNS_INT 1 => $c1 {IntCns 1} N013 [000706] ADD => N014 [000689] LCL_VAR V08 loc4 u:3 => $2b5 {PhiDef($8, $3, $350)} N015 [000707] NE => N016 [000708] JTRUE => $a37 {norm=$VN.Void, exc=$a36( {NullPtrExc($a44)}, {IndexOutOfRangeExc($2b3, $2a6)})} ***** BB163, STMT00153(after) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 finish(BB163). Succ(BB164). Not yet completed. All preds complete, adding to allDone. Succ(BB170). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#33) at start of BB164 is $6d2 {PhiMemoryDef($56, $6d1)} The SSA definition for GcHeap (#33) at start of BB164 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB164, STMT00407(before) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] N001 [000710] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N002 [002872] CNS_INT 56 Fseq[] => $209 {LngCns: 56} N003 [002873] ADD => $24c {ADD($180, $209)} VNForHandle() is $47, fieldType is ref, size = 8 VNForMapSelect($6d2, $47):mem returns $79f {$6d2[$47]} VNForMapSelect($79f, $180):ref returns $a38 {$79f[$180]} N004 [001946] IND => N005 [001998] LCL_VAR V102 tmp62 d:1 => $VN.Void Tree [001999] assigned VN to local var V102/1: N006 [001999] ASG => $321 {norm=$VN.Void, exc=$315 {NullPtrExc($180)}} ***** BB164, STMT00407(after) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 --------- ***** BB164, STMT00398(before) N004 ( 5, 6) [001951] ----------- * JTRUE void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null N001 [001948] LCL_VAR V102 tmp62 u:1 => N002 [001949] CNS_INT null => $VN.Null N003 [001950] EQ => N004 [001951] JTRUE => $VN.Void ***** BB164, STMT00398(after) N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null finish(BB164). Succ(BB165). Not yet completed. All preds complete, adding to allDone. Succ(BB169). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#33) at start of BB165 is $6d2 {PhiMemoryDef($56, $6d1)} The SSA definition for GcHeap (#33) at start of BB165 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB165, STMT00399(before) N006 ( 4, 3) [001954] -A-XG---R-- * ASG int N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 N001 [000709] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002874] CNS_INT 8 => $201 {LngCns: 8} N003 [002875] ADD => $25a {ADD($100, $201)} N004 [001952] IND => N005 [001953] LCL_VAR V103 tmp63 d:1 => $VN.Void Tree [001954] assigned VN to local var V103/1: N006 [001954] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB165, STMT00399(after) N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 --------- ***** BB165, STMT00400(before) N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 N001 [001955] LCL_VAR V102 tmp62 u:1 => N002 [001956] ARR_LENGTH => N003 [001957] CNS_INT 1 => $c1 {IntCns 1} N004 [001958] NE => N005 [001959] JTRUE => ***** BB165, STMT00400(after) N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 finish(BB165). Succ(BB166). Not yet completed. All preds complete, adding to allDone. Succ(BB168). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#33) at start of BB166 is $6d2 {PhiMemoryDef($56, $6d1)} The SSA definition for GcHeap (#33) at start of BB166 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB166, STMT00403(before) N007 ( 8, 7) [001969] ---XG------ * JTRUE void N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 N001 [001963] LCL_VAR V103 tmp63 u:1 => N002 [001964] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [002878] CNS_INT 24 => $20c {LngCns: 24} N004 [002879] ADD => $25b {ADD($100, $20c)} N005 [002002] IND => N006 [001968] GE => N007 [001969] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB166, STMT00403(after) N007 ( 8, 7) [001969] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c finish(BB166). Succ(BB167). Not yet completed. All preds complete, adding to allDone. Succ(BB168). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#33) at start of BB168 is $6d2 {PhiMemoryDef($56, $6d1)} The SSA definition for GcHeap (#33) at start of BB168 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB168, STMT00401(before) N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn N001 [001960] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [001961] LCL_VAR V102 tmp62 u:1 (last use) => N003 [002905] CNS_INT(h) 0x4000000000431d58 ftn => $4f {Hnd const: 0x4000000000431D58} fgCurMemoryVN[GcHeap] assigned for CALL at [001962] to VN: $1e6. N004 [001962] CALL r2r_ind => $VN.Void ***** BB168, STMT00401(after) N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f finish(BB168). Succ(BB169). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#33) at start of BB167 is $6d2 {PhiMemoryDef($56, $6d1)} The SSA definition for GcHeap (#33) at start of BB167 is $6d2 {PhiMemoryDef($56, $6d1)} ***** BB167, STMT00404(before) N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 N003 ( 3, 4) [002885] -----O----- \--* ADD byref N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 N001 [002883] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002884] CNS_INT 16 => $200 {LngCns: 16} N003 [002885] ADD => $25c {ADD($100, $200)} N004 [001974] LCL_VAR V104 tmp64 d:1 => $VN.Void Tree [001975] assigned VN to local var V104/1: $25c {ADD($100, $200)} N005 [001975] ASG => $VN.Void ***** BB167, STMT00404(after) N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 --------- ***** BB167, STMT00405(before) N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $81 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 N001 [001972] LCL_VAR V103 tmp63 u:1 => N002 [001977] LCL_VAR V104 tmp64 u:1 => $25c {ADD($100, $200)} N003 [002887] CNS_INT 8 => $201 {LngCns: 8} N004 [002888] ADD => $25d {ADD($201, $25c)} N005 [001978] IND => N006 [001979] BOUNDS_CHECK_Rng => N007 [001976] LCL_VAR V104 tmp64 u:1 (last use) => $25c {ADD($100, $200)} N008 [001983] IND => N009 [001973] LCL_VAR V103 tmp63 u:1 => N010 [001980] CAST => N011 [001981] CNS_INT 1 => $204 {LngCns: 1} N012 [001982] LSH => N013 [001984] ADD => N014 [002889] IND => N015 [001985] COMMA => N016 [001987] CNS_INT 0 => $c0 {IntCns 0} N017 [001986] LCL_VAR V102 tmp62 u:1 => N018 [002892] ARR_LENGTH => N019 [002893] BOUNDS_CHECK_Rng => N020 [002890] LCL_VAR V102 tmp62 u:1 (last use) => N021 [002896] CNS_INT 12 => $20d {LngCns: 12} N022 [002897] ADD => VNForHandle(arrElemType: ushort) is $41 N023 [002899] ARR_ADDR => $86 {PtrToArrElem($41, $a38, $205, $205)} Array element load: elemTypeEq is $41 for short[] VNForMapSelect($6d2, $41):mem returns $7a2 {$6d2[$41]} GcHeap[elemTypeEq: $41] is $7a2 VNForMapSelect($7a2, $a38):mem returns $7a3 {$7a2[$a38]} GcHeap[elemTypeEq][array: $a38] is $7a3 VNForMapSelect($7a3, $205):short returns $8c2 {$7a3[$205]} GcHeap[elemTypeEq][array][index: $205] is $8c2 VNForLoadStoreBitcast returns $663 {BitCast($8c2)} N024 [002902] IND => ($8c2)}, c:$616 {MemOpaque:L03}> N025 [002900] COMMA => ($8c2)}, exc=$b57( {NullPtrExc($a38)}, {IndexOutOfRangeExc($c0, $2ef)})}, c:$665 {norm=$616 {MemOpaque:L03}, exc=$b58( {NullPtrExc($1ab)}, {IndexOutOfRangeExc($c0, $2f0)})}> fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001991] to VN: $1e7. N026 [001991] ASG => ***** BB167, STMT00405(after) N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d --------- ***** BB167, STMT00406(before) N008 ( 8, 8) [001997] -A-XG---R-- * ASG int N007 ( 4, 3) [001996] D--XG--N--- +--* IND int N006 ( 3, 4) [002904] -------N--- | \--* ADD byref N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 N001 [001993] LCL_VAR V103 tmp63 u:1 (last use) => N002 [001994] CNS_INT 1 => $c1 {IntCns 1} N003 [001995] ADD => N004 [001992] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [002903] CNS_INT 8 => $201 {LngCns: 8} N006 [002904] ADD => $25a {ADD($100, $201)} N007 [001996] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001997] to VN: $1e8. N008 [001997] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB167, STMT00406(after) N008 ( 8, 8) [001997] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001996] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 finish(BB167). Succ(BB169). Not yet completed. All preds complete, adding to allDone. Building phi application: $ef = SSA# 36. Building phi application: $ea = SSA# 35. Building phi application: $6d3 = phi($ea, $ef). Building phi application: $f0 = SSA# 33. Building phi application: $6d4 = phi($f0, $6d3). The SSA definition for GcHeap (#34) at start of BB169 is $6d5 {PhiMemoryDef($57, $6d4)} ***** BB169, STMT00156(before) N005 ( 3, 4) [000718] -A------R-- * ASG int N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 N003 ( 3, 4) [000716] ----------- \--* ADD int N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 N001 [000714] LCL_VAR V20 loc16 u:4 (last use) => $2b3 {PhiDef($14, $4, $948)} N002 [000715] CNS_INT -1 => $c4 {IntCns 4294967295} N003 [000716] ADD => $ab7 {ADD($c4, $2b3)} N004 [000717] LCL_VAR V20 loc16 d:6 => $VN.Void Tree [000718] assigned VN to local var V20/6: $ab7 {ADD($c4, $2b3)} N005 [000718] ASG => $VN.Void ***** BB169, STMT00156(after) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 finish(BB169). Succ(BB170). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 20/5 to $b03 {PhiDef($14, $5, $ab8)} . Building phi application: $f1 = SSA# 34. Building phi application: $f0 = SSA# 33. Building phi application: $6d6 = phi($f0, $f1). Building phi application: $e4 = SSA# 10. Building phi application: $6d7 = phi($e4, $6d6). The SSA definition for GcHeap (#32) at start of BB170 is $6d8 {PhiMemoryDef($58, $6d7)} ***** BB170, STMT00148(before) N005 ( 3, 4) [000673] -A------R-- * ASG int N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 N003 ( 3, 4) [000671] ----------- \--* ADD int N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 N001 [000669] LCL_VAR V08 loc4 u:3 (last use) => $2b5 {PhiDef($8, $3, $350)} N002 [000670] CNS_INT -1 => $c4 {IntCns 4294967295} N003 [000671] ADD => $ab9 {ADD($c4, $2b5)} N004 [000672] LCL_VAR V08 loc4 d:4 => $VN.Void Tree [000673] assigned VN to local var V08/4: $ab9 {ADD($c4, $2b5)} N005 [000673] ASG => $VN.Void ***** BB170, STMT00148(after) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 finish(BB170). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB171 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB171 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB171, STMT00132(before) N008 ( 12, 11) [000612] ----------- * JTRUE void N007 ( 10, 9) [000611] J------N--- \--* NE int N005 ( 8, 6) [000609] ----------- +--* OR int N003 ( 6, 4) [000607] ----------- | +--* NE int N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 N001 [000605] LCL_VAR V08 loc4 u:3 => $2b5 {PhiDef($8, $3, $350)} N002 [000606] CNS_INT 0 => $c0 {IntCns 0} N003 [000607] NE => $aba {NE($2b5, $c0)} N004 [000608] LCL_VAR V21 loc17 u:2 => $4c7 {PhiDef($15, $2, $353)} N005 [000609] OR => $abb {OR($4c7, $aba)} N006 [000610] CNS_INT 0 => $c0 {IntCns 0} N007 [000611] NE => $abc {NE($abb, $c0)} N008 [000612] JTRUE => $VN.Void ***** BB171, STMT00132(after) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 finish(BB171). Succ(BB172). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB172 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB172 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB172, STMT00133(before) N004 ( 5, 6) [000616] ----------- * JTRUE void N003 ( 3, 4) [000615] J------N--- \--* LT int N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 N001 [000613] LCL_VAR V07 loc3 u:3 => $293 {PhiDef($2d, $1, $352)} N002 [000614] CNS_INT 0 => $c0 {IntCns 0} N003 [000615] LT => $abd {LT($293, $c0)} N004 [000616] JTRUE => $VN.Void ***** BB172, STMT00133(after) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 finish(BB172). Succ(BB173). Not yet completed. All preds complete, adding to allDone. Succ(BB175). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB173 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB173 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB173, STMT00137(before) N004 ( 5, 5) [000628] ----------- * JTRUE void N003 ( 3, 3) [000627] J------N--- \--* GE int N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 N001 [000625] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N002 [000626] LCL_VAR V04 loc0 u:2 => $28a {PhiDef($4, $2, $35a)} N003 [000627] GE => $abe {GE($28d, $28a)} N004 [000628] JTRUE => $VN.Void ***** BB173, STMT00137(after) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a finish(BB173). Succ(BB174). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB174 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB174 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB174, STMT00138(before) N005 ( 8, 8) [000633] ---XG------ * JTRUE void N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 N001 [000629] LCL_VAR V36 loc32 u:3 => $901 {PhiDef($24, $3, $3e4)} N002 [000630] IND => N003 [000631] CNS_INT 0 => $c0 {IntCns 0} N004 [000632] EQ => N005 [000633] JTRUE => $a27 {norm=$VN.Void, exc=$a26 {NullPtrExc($901)}} ***** BB174, STMT00138(after) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 finish(BB174). Succ(BB175). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB175 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB175 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB175, STMT00418(before) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] N001 [000618] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N002 [002906] CNS_INT 48 Fseq[] => $20f {LngCns: 48} N003 [002907] ADD => $a4d {ADD($180, $20f)} VNForHandle() is $59, fieldType is ref, size = 8 VNForMapSelect($6ce, $59):mem returns $7a5 {$6ce[$59]} VNForMapSelect($7a5, $180):ref returns $b65 {$7a5[$180]} N004 [002006] IND => N005 [002058] LCL_VAR V106 tmp66 d:1 => $VN.Void Tree [002059] assigned VN to local var V106/1: N006 [002059] ASG => $321 {norm=$VN.Void, exc=$315 {NullPtrExc($180)}} ***** BB175, STMT00418(after) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f --------- ***** BB175, STMT00409(before) N004 ( 5, 6) [002011] ----------- * JTRUE void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null N001 [002008] LCL_VAR V106 tmp66 u:1 => N002 [002009] CNS_INT null => $VN.Null N003 [002010] EQ => N004 [002011] JTRUE => $VN.Void ***** BB175, STMT00409(after) N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null finish(BB175). Succ(BB176). Not yet completed. All preds complete, adding to allDone. Succ(BB180). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB176 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB176 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB176, STMT00410(before) N006 ( 4, 3) [002014] -A-XG---R-- * ASG int N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 N001 [000617] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002908] CNS_INT 8 => $201 {LngCns: 8} N003 [002909] ADD => $25a {ADD($100, $201)} N004 [002012] IND => N005 [002013] LCL_VAR V107 tmp67 d:1 => $VN.Void Tree [002014] assigned VN to local var V107/1: N006 [002014] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB176, STMT00410(after) N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 --------- ***** BB176, STMT00411(before) N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 N001 [002015] LCL_VAR V106 tmp66 u:1 => N002 [002016] ARR_LENGTH => N003 [002017] CNS_INT 1 => $c1 {IntCns 1} N004 [002018] NE => N005 [002019] JTRUE => ***** BB176, STMT00411(after) N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 finish(BB176). Succ(BB177). Not yet completed. All preds complete, adding to allDone. Succ(BB179). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB177 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB177 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB177, STMT00414(before) N007 ( 8, 7) [002029] ---XG------ * JTRUE void N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 N001 [002023] LCL_VAR V107 tmp67 u:1 => N002 [002024] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [002912] CNS_INT 24 => $20c {LngCns: 24} N004 [002913] ADD => $25b {ADD($100, $20c)} N005 [002062] IND => N006 [002028] GE => N007 [002029] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB177, STMT00414(after) N007 ( 8, 7) [002029] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c finish(BB177). Succ(BB178). Not yet completed. All preds complete, adding to allDone. Succ(BB179). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB179 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB179 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB179, STMT00412(before) N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn N001 [002020] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002021] LCL_VAR V106 tmp66 u:1 (last use) => N003 [002939] CNS_INT(h) 0x4000000000431d58 ftn => $4f {Hnd const: 0x4000000000431D58} fgCurMemoryVN[GcHeap] assigned for CALL at [002022] to VN: $1e9. N004 [002022] CALL r2r_ind => $VN.Void ***** BB179, STMT00412(after) N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f finish(BB179). Succ(BB180). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#10) at start of BB178 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB178 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB178, STMT00415(before) N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 N003 ( 3, 4) [002919] -----O----- \--* ADD byref N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 N001 [002917] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002918] CNS_INT 16 => $200 {LngCns: 16} N003 [002919] ADD => $25c {ADD($100, $200)} N004 [002034] LCL_VAR V108 tmp68 d:1 => $VN.Void Tree [002035] assigned VN to local var V108/1: $25c {ADD($100, $200)} N005 [002035] ASG => $VN.Void ***** BB178, STMT00415(after) N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 --------- ***** BB178, STMT00416(before) N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $81 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 N001 [002032] LCL_VAR V107 tmp67 u:1 => N002 [002037] LCL_VAR V108 tmp68 u:1 => $25c {ADD($100, $200)} N003 [002921] CNS_INT 8 => $201 {LngCns: 8} N004 [002922] ADD => $25d {ADD($201, $25c)} N005 [002038] IND => N006 [002039] BOUNDS_CHECK_Rng => N007 [002036] LCL_VAR V108 tmp68 u:1 (last use) => $25c {ADD($100, $200)} N008 [002043] IND => N009 [002033] LCL_VAR V107 tmp67 u:1 => N010 [002040] CAST => N011 [002041] CNS_INT 1 => $204 {LngCns: 1} N012 [002042] LSH => N013 [002044] ADD => N014 [002923] IND => N015 [002045] COMMA => N016 [002047] CNS_INT 0 => $c0 {IntCns 0} N017 [002046] LCL_VAR V106 tmp66 u:1 => N018 [002926] ARR_LENGTH => N019 [002927] BOUNDS_CHECK_Rng => N020 [002924] LCL_VAR V106 tmp66 u:1 (last use) => N021 [002930] CNS_INT 12 => $20d {LngCns: 12} N022 [002931] ADD => VNForHandle(arrElemType: ushort) is $41 N023 [002933] ARR_ADDR => $87 {PtrToArrElem($41, $b65, $205, $205)} Array element load: elemTypeEq is $41 for short[] VNForMapSelect($6ce, $41):mem returns $79b {$6ce[$41]} GcHeap[elemTypeEq: $41] is $79b VNForMapSelect($79b, $b65):mem returns $7a6 {$79b[$b65]} GcHeap[elemTypeEq][array: $b65] is $7a6 VNForMapSelect($7a6, $205):short returns $8c3 {$7a6[$205]} GcHeap[elemTypeEq][array][index: $205] is $8c3 VNForLoadStoreBitcast returns $666 {BitCast($8c3)} N024 [002936] IND => ($8c3)}, c:$617 {MemOpaque:L03}> N025 [002934] COMMA => ($8c3)}, exc=$b7a( {NullPtrExc($b65)}, {IndexOutOfRangeExc($c0, $2f4)})}, c:$668 {norm=$617 {MemOpaque:L03}, exc=$b7b( {NullPtrExc($1b0)}, {IndexOutOfRangeExc($c0, $2f5)})}> fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002051] to VN: $1ea. N026 [002051] ASG => ***** BB178, STMT00416(after) N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d --------- ***** BB178, STMT00417(before) N008 ( 8, 8) [002057] -A-XG---R-- * ASG int N007 ( 4, 3) [002056] D--XG--N--- +--* IND int N006 ( 3, 4) [002938] -------N--- | \--* ADD byref N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 N001 [002053] LCL_VAR V107 tmp67 u:1 (last use) => N002 [002054] CNS_INT 1 => $c1 {IntCns 1} N003 [002055] ADD => N004 [002052] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [002937] CNS_INT 8 => $201 {LngCns: 8} N006 [002938] ADD => $25a {ADD($100, $201)} N007 [002056] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002057] to VN: $1eb. N008 [002057] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB178, STMT00417(after) N008 ( 8, 8) [002057] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002056] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 finish(BB178). Succ(BB180). Not yet completed. All preds complete, adding to allDone. Building phi application: $f2 = SSA# 41. Building phi application: $f3 = SSA# 40. Building phi application: $6d9 = phi($f3, $f2). Building phi application: $e4 = SSA# 10. Building phi application: $6da = phi($e4, $6d9). The SSA definition for GcHeap (#39) at start of BB180 is $6db {PhiMemoryDef($5a, $6da)} ***** BB180, STMT00136(before) N003 ( 1, 3) [000624] -A------R-- * ASG int N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 N001 [002940] CNS_INT 1 => $c1 {IntCns 1} N002 [000623] LCL_VAR V21 loc17 d:3 => $VN.Void Tree [000624] assigned VN to local var V21/3: $c1 {IntCns 1} N003 [000624] ASG => $VN.Void ***** BB180, STMT00136(after) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 finish(BB180). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB186 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB186 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB186, STMT00440(before) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] N001 [000635] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N002 [002973] CNS_INT 128 Fseq[] => $210 {LngCns: 128} N003 [002974] ADD => $a53 {ADD($180, $210)} VNForHandle() is $5b, fieldType is ref, size = 8 VNForMapSelect($6ce, $5b):mem returns $7a8 {$6ce[$5b]} VNForMapSelect($7a8, $180):ref returns $bc8 {$7a8[$180]} N004 [002126] IND => N005 [002178] LCL_VAR V114 tmp74 d:1 => $VN.Void Tree [002179] assigned VN to local var V114/1: N006 [002179] ASG => $321 {norm=$VN.Void, exc=$315 {NullPtrExc($180)}} ***** BB186, STMT00440(after) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 --------- ***** BB186, STMT00431(before) N004 ( 5, 6) [002131] ----------- * JTRUE void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null N001 [002128] LCL_VAR V114 tmp74 u:1 => N002 [002129] CNS_INT null => $VN.Null N003 [002130] EQ => N004 [002131] JTRUE => $VN.Void ***** BB186, STMT00431(after) N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null finish(BB186). Succ(BB187). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB187 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB187 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB187, STMT00432(before) N006 ( 4, 3) [002134] -A-XG---R-- * ASG int N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 N001 [000634] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002975] CNS_INT 8 => $201 {LngCns: 8} N003 [002976] ADD => $25a {ADD($100, $201)} N004 [002132] IND => N005 [002133] LCL_VAR V115 tmp75 d:1 => $VN.Void Tree [002134] assigned VN to local var V115/1: N006 [002134] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB187, STMT00432(after) N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 --------- ***** BB187, STMT00433(before) N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 N001 [002135] LCL_VAR V114 tmp74 u:1 => N002 [002136] ARR_LENGTH => N003 [002137] CNS_INT 1 => $c1 {IntCns 1} N004 [002138] NE => N005 [002139] JTRUE => ***** BB187, STMT00433(after) N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 finish(BB187). Succ(BB188). Not yet completed. All preds complete, adding to allDone. Succ(BB190). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB188 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB188 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB188, STMT00436(before) N007 ( 8, 7) [002149] ---XG------ * JTRUE void N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 N001 [002143] LCL_VAR V115 tmp75 u:1 => N002 [002144] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [002979] CNS_INT 24 => $20c {LngCns: 24} N004 [002980] ADD => $25b {ADD($100, $20c)} N005 [002182] IND => N006 [002148] GE => N007 [002149] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB188, STMT00436(after) N007 ( 8, 7) [002149] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c finish(BB188). Succ(BB189). Not yet completed. All preds complete, adding to allDone. Succ(BB190). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB190 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB190 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB190, STMT00434(before) N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn N001 [002140] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002141] LCL_VAR V114 tmp74 u:1 (last use) => N003 [003006] CNS_INT(h) 0x4000000000431d58 ftn => $4f {Hnd const: 0x4000000000431D58} fgCurMemoryVN[GcHeap] assigned for CALL at [002142] to VN: $1ec. N004 [002142] CALL r2r_ind => $VN.Void ***** BB190, STMT00434(after) N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f finish(BB190). Succ(BB245). The SSA definition for ByrefExposed (#10) at start of BB189 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB189 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB189, STMT00437(before) N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 N003 ( 3, 4) [002986] -----O----- \--* ADD byref N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 N001 [002984] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002985] CNS_INT 16 => $200 {LngCns: 16} N003 [002986] ADD => $25c {ADD($100, $200)} N004 [002154] LCL_VAR V116 tmp76 d:1 => $VN.Void Tree [002155] assigned VN to local var V116/1: $25c {ADD($100, $200)} N005 [002155] ASG => $VN.Void ***** BB189, STMT00437(after) N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 --------- ***** BB189, STMT00438(before) N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $81 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 N001 [002152] LCL_VAR V115 tmp75 u:1 => N002 [002157] LCL_VAR V116 tmp76 u:1 => $25c {ADD($100, $200)} N003 [002988] CNS_INT 8 => $201 {LngCns: 8} N004 [002989] ADD => $25d {ADD($201, $25c)} N005 [002158] IND => N006 [002159] BOUNDS_CHECK_Rng => N007 [002156] LCL_VAR V116 tmp76 u:1 (last use) => $25c {ADD($100, $200)} N008 [002163] IND => N009 [002153] LCL_VAR V115 tmp75 u:1 => N010 [002160] CAST => N011 [002161] CNS_INT 1 => $204 {LngCns: 1} N012 [002162] LSH => N013 [002164] ADD => N014 [002990] IND => N015 [002165] COMMA => N016 [002167] CNS_INT 0 => $c0 {IntCns 0} N017 [002166] LCL_VAR V114 tmp74 u:1 => N018 [002993] ARR_LENGTH => N019 [002994] BOUNDS_CHECK_Rng => N020 [002991] LCL_VAR V114 tmp74 u:1 (last use) => N021 [002997] CNS_INT 12 => $20d {LngCns: 12} N022 [002998] ADD => VNForHandle(arrElemType: ushort) is $41 N023 [003000] ARR_ADDR => $88 {PtrToArrElem($41, $bc8, $205, $205)} Array element load: elemTypeEq is $41 for short[] VNForMapSelect($6ce, $41):mem returns $79b {$6ce[$41]} GcHeap[elemTypeEq: $41] is $79b VNForMapSelect($79b, $bc8):mem returns $7a9 {$79b[$bc8]} GcHeap[elemTypeEq][array: $bc8] is $7a9 VNForMapSelect($7a9, $205):short returns $8c4 {$7a9[$205]} GcHeap[elemTypeEq][array][index: $205] is $8c4 VNForLoadStoreBitcast returns $669 {BitCast($8c4)} N024 [003003] IND => ($8c4)}, c:$618 {MemOpaque:L03}> N025 [003001] COMMA => ($8c4)}, exc=$bdd( {NullPtrExc($bc8)}, {IndexOutOfRangeExc($c0, $2f9)})}, c:$66b {norm=$618 {MemOpaque:L03}, exc=$bde( {NullPtrExc($1b4)}, {IndexOutOfRangeExc($c0, $2fa)})}> fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002171] to VN: $1ed. N026 [002171] ASG => ***** BB189, STMT00438(after) N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d --------- ***** BB189, STMT00439(before) N008 ( 8, 8) [002177] -A-XG---R-- * ASG int N007 ( 4, 3) [002176] D--XG--N--- +--* IND int N006 ( 3, 4) [003005] -------N--- | \--* ADD byref N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 N001 [002173] LCL_VAR V115 tmp75 u:1 (last use) => N002 [002174] CNS_INT 1 => $c1 {IntCns 1} N003 [002175] ADD => N004 [002172] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [003004] CNS_INT 8 => $201 {LngCns: 8} N006 [003005] ADD => $25a {ADD($100, $201)} N007 [002176] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002177] to VN: $1ee. N008 [002177] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB189, STMT00439(after) N008 ( 8, 8) [002177] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002176] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 finish(BB189). Succ(BB245). SSA PHI definition: set VN of local 16/13 to $b04 {PhiDef($10, $d, $ba3)} . Building phi application: $f5 = SSA# 29. Building phi application: $db = SSA# 28. Building phi application: $6dc = phi($db, $f5). Building phi application: $e4 = SSA# 10. Building phi application: $6dd = phi($e4, $6dc). The SSA definition for GcHeap (#27) at start of BB194 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB194, STMT00166(before) N004 ( 7, 8) [000757] ----------- * JTRUE void N003 ( 5, 6) [000756] J------N--- \--* GE int N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000751] LCL_VAR V16 loc12 u:13 => $b04 {PhiDef($10, $d, $ba3)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [002234] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000756] GE => $ba4 {GE($b04, $342)} N004 [000757] JTRUE => $VN.Void ***** BB194, STMT00166(after) N004 ( 7, 8) [000757] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB194). Succ(BB195). Not yet completed. All preds complete, adding to allDone. Succ(BB197). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#27) at start of BB195 is $6de {PhiMemoryDef($5c, $6dd)} The SSA definition for GcHeap (#27) at start of BB195 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB195, STMT00171(before) N010 ( 13, 15) [000791] ---XG------ * JTRUE void N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000786] ----------- | \--* LSH long N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 N001 [000781] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000782] LCL_VAR V16 loc12 u:13 => $b04 {PhiDef($10, $d, $ba3)} N003 [000783] CAST => $aca {$b04, long <- int} N004 [000785] CNS_INT 1 => $204 {LngCns: 1} N005 [000786] LSH => $acb {LSH($aca, $204)} N006 [000787] ADD => $acc {ADD($3c4, $acb)} N007 [000788] IND => N008 [000789] CNS_INT 0 => $c0 {IntCns 0} N009 [000790] EQ => N010 [000791] JTRUE => $bec {norm=$VN.Void, exc=$beb {NullPtrExc($acc)}} ***** BB195, STMT00171(after) N010 ( 13, 15) [000791] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 finish(BB195). Succ(BB196). Not yet completed. All preds complete, adding to allDone. Succ(BB197). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#27) at start of BB196 is $6de {PhiMemoryDef($5c, $6dd)} The SSA definition for GcHeap (#27) at start of BB196 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB196, STMT00172(before) N010 ( 13, 14) [000802] ---XG------ * JTRUE void N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000797] ----------- | \--* LSH long N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 N001 [000792] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000793] LCL_VAR V16 loc12 u:13 => $b04 {PhiDef($10, $d, $ba3)} N003 [000794] CAST => $aca {$b04, long <- int} N004 [000796] CNS_INT 1 => $204 {LngCns: 1} N005 [000797] LSH => $acb {LSH($aca, $204)} N006 [000798] ADD => $acc {ADD($3c4, $acb)} N007 [000799] IND => N008 [000800] LCL_VAR V18 loc14 u:1 => N009 [000801] NE => N010 [000802] JTRUE => $bec {norm=$VN.Void, exc=$beb {NullPtrExc($acc)}} ***** BB196, STMT00172(after) N010 ( 13, 14) [000802] ---XG------ * JTRUE void $bec N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000797] ----------- | \--* LSH long $acb N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 finish(BB196). Succ(BB197). Not yet completed. All preds complete, adding to allDone. Succ(BB191). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#27) at start of BB191 is $6de {PhiMemoryDef($5c, $6dd)} The SSA definition for GcHeap (#27) at start of BB191 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB191, STMT00174(before) N003 ( 1, 3) [000812] -A------R-- * ASG int N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 N001 [000805] LCL_VAR V16 loc12 u:13 => $b04 {PhiDef($10, $d, $ba3)} N002 [000811] LCL_VAR V59 tmp19 d:1 => $VN.Void Tree [000812] assigned VN to local var V59/1: $b04 {PhiDef($10, $d, $ba3)} N003 [000812] ASG => $VN.Void ***** BB191, STMT00174(after) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 --------- ***** BB191, STMT00173(before) N005 ( 3, 4) [000810] -A------R-- * ASG int N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 N003 ( 3, 4) [000808] ----------- \--* ADD int N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 N001 [000806] LCL_VAR V16 loc12 u:13 (last use) => $b04 {PhiDef($10, $d, $ba3)} N002 [000807] CNS_INT 1 => $c1 {IntCns 1} N003 [000808] ADD => $bad {ADD($c1, $b04)} N004 [000809] LCL_VAR V16 loc12 d:15 => $VN.Void Tree [000810] assigned VN to local var V16/15: $bad {ADD($c1, $b04)} N005 [000810] ASG => $VN.Void ***** BB191, STMT00173(after) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB191, STMT00449(before) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000817] ----------- \--* LSH long N003 ( 2, 3) [000814] ----------- +--* CAST long <- int N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 N001 [000804] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000813] LCL_VAR V59 tmp19 u:1 (last use) => $b04 {PhiDef($10, $d, $ba3)} N003 [000814] CAST => $aca {$b04, long <- int} N004 [000816] CNS_INT 1 => $204 {LngCns: 1} N005 [000817] LSH => $acb {LSH($aca, $204)} N006 [000818] ADD => $acc {ADD($3c4, $acb)} N007 [000819] IND => N008 [002224] LCL_VAR V119 tmp79 d:1 => $VN.Void Tree [002225] assigned VN to local var V119/1: N009 [002225] ASG => $bec {norm=$VN.Void, exc=$beb {NullPtrExc($acc)}} ***** BB191, STMT00449(after) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort $bec N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long $acc N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000817] ----------- \--* LSH long $acb N003 ( 2, 3) [000814] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 $204 --------- ***** BB191, STMT00442(before) N006 ( 4, 3) [002188] -A-XG---R-- * ASG int N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 N001 [000803] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003007] CNS_INT 8 => $201 {LngCns: 8} N003 [003008] ADD => $25a {ADD($100, $201)} N004 [002186] IND => N005 [002187] LCL_VAR V118 tmp78 d:1 => $VN.Void Tree [002188] assigned VN to local var V118/1: N006 [002188] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB191, STMT00442(after) N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 --------- ***** BB191, STMT00444(before) N007 ( 8, 7) [002195] ---XG------ * JTRUE void N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 N001 [002189] LCL_VAR V118 tmp78 u:1 => N002 [002190] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [003011] CNS_INT 24 => $20c {LngCns: 24} N004 [003012] ADD => $25b {ADD($100, $20c)} N005 [002228] IND => N006 [002194] GE => N007 [002195] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB191, STMT00444(after) N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c finish(BB191). Succ(BB192). Not yet completed. All preds complete, adding to allDone. Succ(BB193). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#27) at start of BB193 is $6de {PhiMemoryDef($5c, $6dd)} The SSA definition for GcHeap (#27) at start of BB193 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB193, STMT00445(before) N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn N001 [002196] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002197] LCL_VAR V119 tmp79 u:1 (last use) => N003 [003025] CNS_INT(h) 0x4000000000435c58 ftn => $53 {Hnd const: 0x4000000000435C58} fgCurMemoryVN[GcHeap] assigned for CALL at [002198] to VN: $1ef. N004 [002198] CALL r2r_ind => $VN.Void ***** BB193, STMT00445(after) N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 finish(BB193). Succ(BB194). The SSA definition for ByrefExposed (#27) at start of BB192 is $6de {PhiMemoryDef($5c, $6dd)} The SSA definition for GcHeap (#27) at start of BB192 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB192, STMT00446(before) N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 N003 ( 3, 4) [003018] -----O----- \--* ADD byref N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 N001 [003016] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003017] CNS_INT 16 => $200 {LngCns: 16} N003 [003018] ADD => $25c {ADD($100, $200)} N004 [002203] LCL_VAR V120 tmp80 d:1 => $VN.Void Tree [002204] assigned VN to local var V120/1: $25c {ADD($100, $200)} N005 [002204] ASG => $VN.Void ***** BB192, STMT00446(after) N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 --------- ***** BB192, STMT00447(before) N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) N001 [002201] LCL_VAR V118 tmp78 u:1 => N002 [002206] LCL_VAR V120 tmp80 u:1 => $25c {ADD($100, $200)} N003 [003020] CNS_INT 8 => $201 {LngCns: 8} N004 [003021] ADD => $25d {ADD($201, $25c)} N005 [002207] IND => N006 [002208] BOUNDS_CHECK_Rng => N007 [002205] LCL_VAR V120 tmp80 u:1 (last use) => $25c {ADD($100, $200)} N008 [002212] IND => N009 [002202] LCL_VAR V118 tmp78 u:1 => N010 [002209] CAST => N011 [002210] CNS_INT 1 => $204 {LngCns: 1} N012 [002211] LSH => N013 [002213] ADD => N014 [003022] IND => N015 [002214] COMMA => N016 [002215] LCL_VAR V119 tmp79 u:1 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002217] to VN: $1f0. N017 [002217] ASG => ***** BB192, STMT00447(after) N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) --------- ***** BB192, STMT00448(before) N008 ( 8, 8) [002223] -A-XG---R-- * ASG int N007 ( 4, 3) [002222] D--XG--N--- +--* IND int N006 ( 3, 4) [003024] -------N--- | \--* ADD byref N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 N001 [002219] LCL_VAR V118 tmp78 u:1 (last use) => N002 [002220] CNS_INT 1 => $c1 {IntCns 1} N003 [002221] ADD => N004 [002218] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [003023] CNS_INT 8 => $201 {LngCns: 8} N006 [003024] ADD => $25a {ADD($100, $201)} N007 [002222] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002223] to VN: $1f1. N008 [002223] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB192, STMT00448(after) N008 ( 8, 8) [002223] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002222] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 finish(BB192). Succ(BB194). The SSA definition for ByrefExposed (#27) at start of BB197 is $6de {PhiMemoryDef($5c, $6dd)} The SSA definition for GcHeap (#27) at start of BB197 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB197, STMT00168(before) N004 ( 7, 8) [000764] ----------- * JTRUE void N003 ( 5, 6) [000763] J------N--- \--* GE int N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000758] LCL_VAR V16 loc12 u:13 => $b04 {PhiDef($10, $d, $ba3)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [002238] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000763] GE => $ba4 {GE($b04, $342)} N004 [000764] JTRUE => $VN.Void ***** BB197, STMT00168(after) N004 ( 7, 8) [000764] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB197). Succ(BB198). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#27) at start of BB198 is $6de {PhiMemoryDef($5c, $6dd)} The SSA definition for GcHeap (#27) at start of BB198 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB198, STMT00169(before) N010 ( 13, 15) [000775] ---XG------ * JTRUE void N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000770] ----------- | \--* LSH long N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 N001 [000765] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000766] LCL_VAR V16 loc12 u:13 => $b04 {PhiDef($10, $d, $ba3)} N003 [000767] CAST => $aca {$b04, long <- int} N004 [000769] CNS_INT 1 => $204 {LngCns: 1} N005 [000770] LSH => $acb {LSH($aca, $204)} N006 [000771] ADD => $acc {ADD($3c4, $acb)} N007 [000772] IND => N008 [000773] CNS_INT 0 => $c0 {IntCns 0} N009 [000774] EQ => N010 [000775] JTRUE => $bec {norm=$VN.Void, exc=$beb {NullPtrExc($acc)}} ***** BB198, STMT00169(after) N010 ( 13, 15) [000775] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 finish(BB198). Succ(BB199). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#27) at start of BB199 is $6de {PhiMemoryDef($5c, $6dd)} The SSA definition for GcHeap (#27) at start of BB199 is $6de {PhiMemoryDef($5c, $6dd)} ***** BB199, STMT00170(before) N005 ( 3, 4) [000780] -A------R-- * ASG int N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 N003 ( 3, 4) [000778] ----------- \--* ADD int N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 N001 [000776] LCL_VAR V16 loc12 u:13 (last use) => $b04 {PhiDef($10, $d, $ba3)} N002 [000777] CNS_INT 1 => $c1 {IntCns 1} N003 [000778] ADD => $bad {ADD($c1, $b04)} N004 [000779] LCL_VAR V16 loc12 d:14 => $VN.Void Tree [000780] assigned VN to local var V16/14: $bad {ADD($c1, $b04)} N005 [000780] ASG => $VN.Void ***** BB199, STMT00170(after) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 finish(BB199). Succ(BB245). SSA PHI definition: set VN of local 16/6 to $b08 {PhiDef($10, $6, $c41)} . Building phi application: $e8 = SSA# 13. Building phi application: $c7 = SSA# 18. Building phi application: $6df = phi($c7, $e8). Building phi application: $cf = SSA# 17. Building phi application: $6e0 = phi($cf, $6df). Building phi application: $f6 = SSA# 16. Building phi application: $6e1 = phi($f6, $6e0). Building phi application: $f4 = SSA# 15. Building phi application: $6e2 = phi($f4, $6e1). The SSA definition for GcHeap (#14) at start of BB239 is $6e3 {PhiMemoryDef($5d, $6e2)} ***** BB239, STMT00091(before) N004 ( 7, 8) [000378] ----------- * JTRUE void N003 ( 5, 6) [000377] J------N--- \--* GE int N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000372] LCL_VAR V16 loc12 u:6 => $b08 {PhiDef($10, $6, $c41)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [002490] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000377] GE => $c42 {GE($b08, $342)} N004 [000378] JTRUE => $VN.Void ***** BB239, STMT00091(after) N004 ( 7, 8) [000378] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB239). Succ(BB240). Not yet completed. All preds complete, adding to allDone. Succ(BB245). The SSA definition for ByrefExposed (#14) at start of BB240 is $6e3 {PhiMemoryDef($5d, $6e2)} The SSA definition for GcHeap (#14) at start of BB240 is $6e3 {PhiMemoryDef($5d, $6e2)} ***** BB240, STMT00092(before) N010 ( 13, 15) [000389] ---XG------ * JTRUE void N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000384] ----------- | \--* LSH long N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 N001 [000379] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000380] LCL_VAR V16 loc12 u:6 => $b08 {PhiDef($10, $6, $c41)} N003 [000381] CAST => $ad1 {$b08, long <- int} N004 [000383] CNS_INT 1 => $204 {LngCns: 1} N005 [000384] LSH => $ad2 {LSH($ad1, $204)} N006 [000385] ADD => $ad3 {ADD($3c4, $ad2)} N007 [000386] IND => N008 [000387] CNS_INT 48 => $d8 {IntCns 48} N009 [000388] EQ => N010 [000389] JTRUE => $c02 {norm=$VN.Void, exc=$c01 {NullPtrExc($ad3)}} ***** BB240, STMT00092(after) N010 ( 13, 15) [000389] ---XG------ * JTRUE void $c02 N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 finish(BB240). Succ(BB241). Not yet completed. All preds complete, adding to allDone. Succ(BB236). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#14) at start of BB236 is $6e3 {PhiMemoryDef($5d, $6e2)} The SSA definition for GcHeap (#14) at start of BB236 is $6e3 {PhiMemoryDef($5d, $6e2)} ***** BB236, STMT00094(before) N003 ( 1, 3) [000399] -A------R-- * ASG int N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 N001 [000392] LCL_VAR V16 loc12 u:6 => $b08 {PhiDef($10, $6, $c41)} N002 [000398] LCL_VAR V53 tmp13 d:1 => $VN.Void Tree [000399] assigned VN to local var V53/1: $b08 {PhiDef($10, $6, $c41)} N003 [000399] ASG => $VN.Void ***** BB236, STMT00094(after) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 --------- ***** BB236, STMT00093(before) N005 ( 3, 4) [000397] -A------R-- * ASG int N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 N003 ( 3, 4) [000395] ----------- \--* ADD int N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V16 loc12 u:6 (last use) N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 N001 [000393] LCL_VAR V16 loc12 u:6 (last use) => $b08 {PhiDef($10, $6, $c41)} N002 [000394] CNS_INT 1 => $c1 {IntCns 1} N003 [000395] ADD => $c47 {ADD($c1, $b08)} N004 [000396] LCL_VAR V16 loc12 d:7 => $VN.Void Tree [000397] assigned VN to local var V16/7: $c47 {ADD($c1, $b08)} N005 [000397] ASG => $VN.Void ***** BB236, STMT00093(after) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V16 loc12 u:6 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB236, STMT00492(before) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000404] ----------- \--* LSH long N003 ( 2, 3) [000401] ----------- +--* CAST long <- int N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 N001 [000391] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000400] LCL_VAR V53 tmp13 u:1 (last use) => $b08 {PhiDef($10, $6, $c41)} N003 [000401] CAST => $ad1 {$b08, long <- int} N004 [000403] CNS_INT 1 => $204 {LngCns: 1} N005 [000404] LSH => $ad2 {LSH($ad1, $204)} N006 [000405] ADD => $ad3 {ADD($3c4, $ad2)} N007 [000406] IND => N008 [002480] LCL_VAR V137 tmp97 d:1 => $VN.Void Tree [002481] assigned VN to local var V137/1: N009 [002481] ASG => $c02 {norm=$VN.Void, exc=$c01 {NullPtrExc($ad3)}} ***** BB236, STMT00492(after) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort $c02 N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000404] ----------- \--* LSH long $ad2 N003 ( 2, 3) [000401] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 $204 --------- ***** BB236, STMT00485(before) N006 ( 4, 3) [002444] -A-XG---R-- * ASG int N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 N001 [000390] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003108] CNS_INT 8 => $201 {LngCns: 8} N003 [003109] ADD => $25a {ADD($100, $201)} N004 [002442] IND => N005 [002443] LCL_VAR V136 tmp96 d:1 => $VN.Void Tree [002444] assigned VN to local var V136/1: N006 [002444] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB236, STMT00485(after) N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 --------- ***** BB236, STMT00487(before) N007 ( 8, 7) [002451] ---XG------ * JTRUE void N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 N001 [002445] LCL_VAR V136 tmp96 u:1 => N002 [002446] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [003112] CNS_INT 24 => $20c {LngCns: 24} N004 [003113] ADD => $25b {ADD($100, $20c)} N005 [002484] IND => N006 [002450] GE => N007 [002451] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB236, STMT00487(after) N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c finish(BB236). Succ(BB237). Not yet completed. All preds complete, adding to allDone. Succ(BB238). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#14) at start of BB238 is $6e3 {PhiMemoryDef($5d, $6e2)} The SSA definition for GcHeap (#14) at start of BB238 is $6e3 {PhiMemoryDef($5d, $6e2)} ***** BB238, STMT00488(before) N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn N001 [002452] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002453] LCL_VAR V137 tmp97 u:1 (last use) => N003 [003126] CNS_INT(h) 0x4000000000435c58 ftn => $53 {Hnd const: 0x4000000000435C58} fgCurMemoryVN[GcHeap] assigned for CALL at [002454] to VN: $1f2. N004 [002454] CALL r2r_ind => $VN.Void ***** BB238, STMT00488(after) N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 finish(BB238). Succ(BB239). The SSA definition for ByrefExposed (#14) at start of BB237 is $6e3 {PhiMemoryDef($5d, $6e2)} The SSA definition for GcHeap (#14) at start of BB237 is $6e3 {PhiMemoryDef($5d, $6e2)} ***** BB237, STMT00489(before) N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 N003 ( 3, 4) [003119] -----O----- \--* ADD byref N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 N001 [003117] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [003118] CNS_INT 16 => $200 {LngCns: 16} N003 [003119] ADD => $25c {ADD($100, $200)} N004 [002459] LCL_VAR V138 tmp98 d:1 => $VN.Void Tree [002460] assigned VN to local var V138/1: $25c {ADD($100, $200)} N005 [002460] ASG => $VN.Void ***** BB237, STMT00489(after) N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 --------- ***** BB237, STMT00490(before) N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) N001 [002457] LCL_VAR V136 tmp96 u:1 => N002 [002462] LCL_VAR V138 tmp98 u:1 => $25c {ADD($100, $200)} N003 [003121] CNS_INT 8 => $201 {LngCns: 8} N004 [003122] ADD => $25d {ADD($201, $25c)} N005 [002463] IND => N006 [002464] BOUNDS_CHECK_Rng => N007 [002461] LCL_VAR V138 tmp98 u:1 (last use) => $25c {ADD($100, $200)} N008 [002468] IND => N009 [002458] LCL_VAR V136 tmp96 u:1 => N010 [002465] CAST => N011 [002466] CNS_INT 1 => $204 {LngCns: 1} N012 [002467] LSH => N013 [002469] ADD => N014 [003123] IND => N015 [002470] COMMA => N016 [002471] LCL_VAR V137 tmp97 u:1 (last use) => fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002473] to VN: $1f3. N017 [002473] ASG => ***** BB237, STMT00490(after) N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) --------- ***** BB237, STMT00491(before) N008 ( 8, 8) [002479] -A-XG---R-- * ASG int N007 ( 4, 3) [002478] D--XG--N--- +--* IND int N006 ( 3, 4) [003125] -------N--- | \--* ADD byref N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 N001 [002475] LCL_VAR V136 tmp96 u:1 (last use) => N002 [002476] CNS_INT 1 => $c1 {IntCns 1} N003 [002477] ADD => N004 [002474] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [003124] CNS_INT 8 => $201 {LngCns: 8} N006 [003125] ADD => $25a {ADD($100, $201)} N007 [002478] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [002479] to VN: $1f4. N008 [002479] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB237, STMT00491(after) N008 ( 8, 8) [002479] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002478] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 finish(BB237). Succ(BB239). The SSA definition for ByrefExposed (#14) at start of BB241 is $6e3 {PhiMemoryDef($5d, $6e2)} The SSA definition for GcHeap (#14) at start of BB241 is $6e3 {PhiMemoryDef($5d, $6e2)} finish(BB241). Succ(BB245). SSA PHI definition: set VN of local 37/3 to $4c9 {PhiDef($25, $3, $549)} . SSA PHI definition: set VN of local 16/11 to $b0c {PhiDef($10, $b, $c58)} . SSA PHI definition: set VN of local 38/5 to $b0d {PhiDef($26, $5, $549)} . The SSA definition for ByrefExposed (#10) at start of BB218 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB218 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB218, STMT00119(before) N005 ( 3, 4) [000537] -A------R-- * ASG int N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 N003 ( 3, 4) [000535] ----------- \--* ADD int N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 N001 [000533] LCL_VAR V38 loc34 u:5 (last use) => $b0d {PhiDef($26, $5, $549)} N002 [000534] CNS_INT 1 => $c1 {IntCns 1} N003 [000535] ADD => $c59 {ADD($c1, $b0d)} N004 [000536] LCL_VAR V38 loc34 d:6 => $VN.Void Tree [000537] assigned VN to local var V38/6: $c59 {ADD($c1, $b0d)} N005 [000537] ASG => $VN.Void ***** BB218, STMT00119(after) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 finish(BB218). Succ(BB219). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 37/2 to $4ca {PhiDef($25, $2, $54a)} . SSA PHI definition: set VN of local 16/9 to $b0e {PhiDef($10, $9, $c5a)} . SSA PHI definition: set VN of local 38/2 to $b0f {PhiDef($26, $2, $c5b)} . The SSA definition for ByrefExposed (#10) at start of BB219 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB219 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB219, STMT00106(before) N005 ( 3, 4) [000475] -A------R-- * ASG int N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 N003 ( 3, 4) [000473] ----------- \--* ADD int N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 N001 [000471] LCL_VAR V16 loc12 u:9 (last use) => $b0e {PhiDef($10, $9, $c5a)} N002 [000472] CNS_INT 1 => $c1 {IntCns 1} N003 [000473] ADD => $c5c {ADD($c1, $b0e)} N004 [000474] LCL_VAR V54 tmp14 d:1 => $VN.Void Tree [000475] assigned VN to local var V54/1: $c5c {ADD($c1, $b0e)} N005 [000475] ASG => $VN.Void ***** BB219, STMT00106(after) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 --------- ***** BB219, STMT00107(before) N003 ( 1, 3) [000479] -A------R-- * ASG int N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 N001 [000477] LCL_VAR V54 tmp14 u:1 => $c5c {ADD($c1, $b0e)} N002 [000478] LCL_VAR V16 loc12 d:10 => $VN.Void Tree [000479] assigned VN to local var V16/10: $c5c {ADD($c1, $b0e)} N003 [000479] ASG => $VN.Void ***** BB219, STMT00107(after) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c --------- ***** BB219, STMT00109(before) N004 ( 7, 8) [000485] ----------- * JTRUE void N003 ( 5, 6) [000484] J------N--- \--* GE int N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V54 tmp14 u:1 (last use) N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] N001 [000476] LCL_VAR V54 tmp14 u:1 (last use) => $c5c {ADD($c1, $b0e)} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} VNForLoad: VNForMapPhysicalSelect($140, [8:11]):int returns $342 {$140[$203]} N002 [002347] LCL_FLD V02 arg2 u:1[+8] => $342 {$140[$203]} N003 [000484] GE => $c5d {GE($c5c, $342)} N004 [000485] JTRUE => $VN.Void ***** BB219, STMT00109(after) N004 ( 7, 8) [000485] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V54 tmp14 u:1 (last use) $c5c N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 finish(BB219). Succ(BB220). Not yet completed. All preds complete, adding to allDone. Succ(BB221). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB220 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB220 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB220, STMT00118(before) N010 ( 13, 15) [000532] ---XG------ * JTRUE void N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 N005 ( 4, 6) [000527] ----------- | \--* LSH long N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 N001 [000522] LCL_VAR V34 loc30 u:1 => $3c4 {$246, long <- byref} N002 [000523] LCL_VAR V16 loc12 u:10 => $c5c {ADD($c1, $b0e)} N003 [000524] CAST => $ad8 {$c5c, long <- int} N004 [000526] CNS_INT 1 => $204 {LngCns: 1} N005 [000527] LSH => $ad9 {LSH($ad8, $204)} N006 [000528] ADD => $ada {ADD($3c4, $ad9)} N007 [000529] IND => N008 [000530] CNS_INT 48 => $d8 {IntCns 48} N009 [000531] EQ => N010 [000532] JTRUE => $c18 {norm=$VN.Void, exc=$c17 {NullPtrExc($ada)}} ***** BB220, STMT00118(after) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 finish(BB220). Succ(BB221). Not yet completed. All preds complete, adding to allDone. Succ(BB218). The SSA definition for ByrefExposed (#10) at start of BB221 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB221 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB221, STMT00110(before) N004 ( 5, 6) [000489] ----------- * JTRUE void N003 ( 3, 4) [000488] J------N--- \--* LE int N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 N001 [000486] LCL_VAR V38 loc34 u:2 => $b0f {PhiDef($26, $2, $c5b)} N002 [000487] CNS_INT 10 => $e4 {IntCns 10} N003 [000488] LE => $c62 {LE($b0f, $e4)} N004 [000489] JTRUE => $VN.Void ***** BB221, STMT00110(after) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 finish(BB221). Succ(BB222). Not yet completed. All preds complete, adding to allDone. Succ(BB223). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB222 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB222 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB222, STMT00117(before) N003 ( 1, 3) [000521] -A------R-- * ASG int N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 N001 [000519] CNS_INT 10 => $e4 {IntCns 10} N002 [000520] LCL_VAR V38 loc34 d:4 => $VN.Void Tree [000521] assigned VN to local var V38/4: $e4 {IntCns 10} N003 [000521] ASG => $VN.Void ***** BB222, STMT00117(after) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 finish(BB222). Succ(BB223). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 38/3 to $b10 {PhiDef($26, $3, $34e)} . The SSA definition for ByrefExposed (#10) at start of BB223 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB223 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB223, STMT00111(before) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 N001 [000490] LCL_VAR V17 loc13 u:1 => N002 [000491] IND => N003 [000492] CNS_INT 0 => $c0 {IntCns 0} N004 [000493] EQ => N005 [000494] JTRUE => ***** BB223, STMT00111(after) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 finish(BB223). Succ(BB224). Not yet completed. All preds complete, adding to allDone. Succ(BB225). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#10) at start of BB225 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB225 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB225, STMT00112(before) N003 ( 1, 3) [000497] -A------R-- * ASG int N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 N001 [000495] CNS_INT 0 => $c0 {IntCns 0} N002 [000496] LCL_VAR V55 tmp15 d:2 => $VN.Void Tree [000497] assigned VN to local var V55/2: $c0 {IntCns 0} N003 [000497] ASG => $VN.Void ***** BB225, STMT00112(after) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 finish(BB225). Succ(BB226). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#10) at start of BB224 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB224 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB224, STMT00116(before) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 N001 [000512] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [003066] CNS_INT 4 => $207 {LngCns: 4} N003 [003067] ADD => $24a {ADD($101, $207)} N004 [000513] IND => N005 [000514] LCL_VAR V05 loc1 u:3 => $28d {PhiDef($5, $3, $34e)} N006 [000515] SUB => N007 [000516] LCL_VAR V55 tmp15 d:3 => $VN.Void Tree [000517] assigned VN to local var V55/3: N008 [000517] ASG => $301 {norm=$VN.Void, exc=$300 {NullPtrExc($101)}} ***** BB224, STMT00116(after) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d finish(BB224). Succ(BB226). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 55/1 to $b12 {PhiDef($37, $1, $352)} . The SSA definition for ByrefExposed (#10) at start of BB226 is $6ce {PhiMemoryDef($52, $6cd)} The SSA definition for GcHeap (#10) at start of BB226 is $6ce {PhiMemoryDef($52, $6cd)} ***** BB226, STMT00114(before) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn N001 [000507] LCL_VAR V37 loc33 u:2 (last use) => $4ca {PhiDef($25, $2, $54a)} N002 [000502] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [000503] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N004 [000499] LCL_VAR V55 tmp15 u:1 (last use) => $b12 {PhiDef($37, $1, $352)} N005 [000505] LCL_VAR V18 loc14 u:1 (last use) => N006 [000506] LCL_VAR V38 loc34 u:3 (last use) => $b10 {PhiDef($26, $3, $34e)} N007 [003068] CNS_INT(h) 0x4000000000540240 ftn => $5e {Hnd const: 0x4000000000540240} fgCurMemoryVN[GcHeap] assigned for CALL at [000508] to VN: $1f5. N008 [000508] CALL r2r_ind => $VN.Void ***** BB226, STMT00114(after) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e --------- ***** BB226, STMT00115(before) N003 ( 1, 3) [000511] -A------R-- * ASG int N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 N001 [003069] CNS_INT 0 => $c0 {IntCns 0} N002 [000510] LCL_VAR V09 loc5 d:4 => $VN.Void Tree [000511] assigned VN to local var V09/4: $c0 {IntCns 0} N003 [000511] ASG => $VN.Void ***** BB226, STMT00115(after) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 finish(BB226). Succ(BB245). SSA PHI definition: set VN of local 36/7 to $904 {PhiDef($24, $7, $adb)} . SSA PHI definition: set VN of local 20/7 to $b13 {PhiDef($14, $7, $c6d)} . SSA PHI definition: set VN of local 14/6 to $b14 {PhiDef($e, $6, $3e4)} . SSA PHI definition: set VN of local 8/5 to $b15 {PhiDef($8, $5, $544)} . Building phi application: $f7 = SSA# 44. Building phi application: $e0 = SSA# 8. Building phi application: $6e4 = phi($e0, $f7). The SSA definition for GcHeap (#42) at start of BB135 is $6e5 {PhiMemoryDef($5f, $6e4)} ***** BB135, STMT00177(before) N004 ( 5, 6) [000828] ----------- * JTRUE void N003 ( 3, 4) [000827] J------N--- \--* GT int N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 N001 [000825] LCL_VAR V14 loc10 u:6 => $b14 {PhiDef($e, $6, $3e4)} N002 [000826] CNS_INT 0 => $c0 {IntCns 0} N003 [000827] GT => $c6e {GT($b14, $c0)} N004 [000828] JTRUE => $VN.Void ***** BB135, STMT00177(after) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 finish(BB135). Succ(BB136). Succ(BB118). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#42) at start of BB118 is $6e5 {PhiMemoryDef($5f, $6e4)} The SSA definition for GcHeap (#42) at start of BB118 is $6e5 {PhiMemoryDef($5f, $6e4)} ***** BB118, STMT00179(before) N003 ( 1, 3) [000836] -A------R-- * ASG byref N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 N001 [000829] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [000835] LCL_VAR V60 tmp20 d:1 => $VN.Void Tree [000836] assigned VN to local var V60/1: $100 {InitVal($c0)} N003 [000836] ASG => $VN.Void ***** BB118, STMT00179(after) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 --------- ***** BB118, STMT00178(before) N005 ( 8, 8) [000834] ---XG------ * JTRUE void N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 N001 [000830] LCL_VAR V36 loc32 u:7 => $904 {PhiDef($24, $7, $adb)} N002 [000831] IND => N003 [000832] CNS_INT 0 => $c0 {IntCns 0} N004 [000833] NE => N005 [000834] JTRUE => $c1a {norm=$VN.Void, exc=$c19 {NullPtrExc($904)}} ***** BB118, STMT00178(after) N005 ( 8, 8) [000834] ---XG------ * JTRUE void $c1a N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 $904 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 finish(BB118). Succ(BB119). Not yet completed. All preds complete, adding to allDone. Succ(BB120). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#42) at start of BB120 is $6e5 {PhiMemoryDef($5f, $6e4)} The SSA definition for GcHeap (#42) at start of BB120 is $6e5 {PhiMemoryDef($5f, $6e4)} ***** BB120, STMT00181(before) N003 ( 1, 3) [000848] -A------R-- * ASG long N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 N001 [000840] LCL_VAR V36 loc32 u:7 => $904 {PhiDef($24, $7, $adb)} N002 [000847] LCL_VAR V61 tmp21 d:1 => $VN.Void Tree [000848] assigned VN to local var V61/1: $904 {PhiDef($24, $7, $adb)} N003 [000848] ASG => $VN.Void ***** BB120, STMT00181(after) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 --------- ***** BB120, STMT00180(before) N005 ( 3, 4) [000846] -A------R-- * ASG long N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 N003 ( 3, 4) [000844] ----------- \--* ADD long N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V36 loc32 u:7 (last use) N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 N001 [000841] LCL_VAR V36 loc32 u:7 (last use) => $904 {PhiDef($24, $7, $adb)} N002 [000843] CNS_INT 1 => $204 {LngCns: 1} N003 [000844] ADD => $adc {ADD($204, $904)} N004 [000845] LCL_VAR V36 loc32 d:9 => $VN.Void Tree [000846] assigned VN to local var V36/9: $adc {ADD($204, $904)} N005 [000846] ASG => $VN.Void ***** BB120, STMT00180(after) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V36 loc32 u:7 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 --------- ***** BB120, STMT00182(before) N003 ( 1, 3) [000852] -A------R-- * ASG byref N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) N001 [000839] LCL_VAR V60 tmp20 u:1 (last use) => $100 {InitVal($c0)} N002 [000851] LCL_VAR V62 tmp22 d:2 => $VN.Void Tree [000852] assigned VN to local var V62/2: $100 {InitVal($c0)} N003 [000852] ASG => $VN.Void ***** BB120, STMT00182(after) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) $100 --------- ***** BB120, STMT00183(before) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) N001 [000849] LCL_VAR V61 tmp21 u:1 (last use) => $904 {PhiDef($24, $7, $adb)} N002 [000850] IND => N003 [000854] LCL_VAR V63 tmp23 d:2 => $VN.Void Tree [000855] assigned VN to local var V63/2: N004 [000855] ASG => $c1a {norm=$VN.Void, exc=$c19 {NullPtrExc($904)}} ***** BB120, STMT00183(after) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int $c1a N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) $904 finish(BB120). Succ(BB121). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#42) at start of BB119 is $6e5 {PhiMemoryDef($5f, $6e4)} The SSA definition for GcHeap (#42) at start of BB119 is $6e5 {PhiMemoryDef($5f, $6e4)} ***** BB119, STMT00194(before) N003 ( 1, 3) [000914] -A------R-- * ASG byref N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) N001 [000838] LCL_VAR V60 tmp20 u:1 (last use) => $100 {InitVal($c0)} N002 [000913] LCL_VAR V62 tmp22 d:3 => $VN.Void Tree [000914] assigned VN to local var V62/3: $100 {InitVal($c0)} N003 [000914] ASG => $VN.Void ***** BB119, STMT00194(after) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) $100 --------- ***** BB119, STMT00195(before) N003 ( 1, 3) [000917] -A------R-- * ASG int N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 N001 [000912] CNS_INT 48 => $d8 {IntCns 48} N002 [000916] LCL_VAR V63 tmp23 d:3 => $VN.Void Tree [000917] assigned VN to local var V63/3: $d8 {IntCns 48} N003 [000917] ASG => $VN.Void ***** BB119, STMT00195(after) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 finish(BB119). Succ(BB121). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 36/8 to $905 {PhiDef($24, $8, $add)} . SSA PHI definition: set VN of local 63/1 to $b16 {PhiDef($3f, $1, $352)} . SSA PHI definition: set VN of local 62/1 to $100 {InitVal($c0)} (all same). The SSA definition for ByrefExposed (#42) at start of BB121 is $6e5 {PhiMemoryDef($5f, $6e4)} The SSA definition for GcHeap (#42) at start of BB121 is $6e5 {PhiMemoryDef($5f, $6e4)} ***** BB121, STMT00377(before) N004 ( 2, 3) [001836] -A------R-- * ASG ushort N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) N001 [000858] LCL_VAR V63 tmp23 u:1 (last use) => $b16 {PhiDef($3f, $1, $352)} N002 [001796] CAST => $c75 {$b16, int <- ushort <- int} N003 [001835] LCL_VAR V92 tmp52 d:1 => $VN.Void Tree [001836] assigned VN to local var V92/1: $c75 {$b16, int <- ushort <- int} N004 [001836] ASG => $VN.Void ***** BB121, STMT00377(after) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 --------- ***** BB121, STMT00370(before) N006 ( 4, 3) [001799] -A-XG---R-- * ASG int N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V62 tmp22 u:1 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 N001 [000857] LCL_VAR V62 tmp22 u:1 => $100 {InitVal($c0)} N002 [002794] CNS_INT 8 => $201 {LngCns: 8} N003 [002795] ADD => $25a {ADD($100, $201)} N004 [001797] IND => N005 [001798] LCL_VAR V91 tmp51 d:1 => $VN.Void Tree [001799] assigned VN to local var V91/1: N006 [001799] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB121, STMT00370(after) N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V62 tmp22 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 --------- ***** BB121, STMT00372(before) N007 ( 8, 7) [001806] ---XG------ * JTRUE void N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V62 tmp22 u:1 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 N001 [001800] LCL_VAR V91 tmp51 u:1 => N002 [001801] LCL_VAR V62 tmp22 u:1 => $100 {InitVal($c0)} N003 [002798] CNS_INT 24 => $20c {LngCns: 24} N004 [002799] ADD => $25b {ADD($100, $20c)} N005 [001839] IND => N006 [001805] GE => N007 [001806] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB121, STMT00372(after) N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V62 tmp22 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c finish(BB121). Succ(BB122). Not yet completed. All preds complete, adding to allDone. Succ(BB123). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#42) at start of BB123 is $6e5 {PhiMemoryDef($5f, $6e4)} The SSA definition for GcHeap (#42) at start of BB123 is $6e5 {PhiMemoryDef($5f, $6e4)} ***** BB123, STMT00373(before) N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V62 tmp22 u:1 (last use) N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn N001 [001807] LCL_VAR V62 tmp22 u:1 (last use) => $100 {InitVal($c0)} N002 [001808] LCL_VAR V92 tmp52 u:1 (last use) => $c75 {$b16, int <- ushort <- int} N003 [002812] CNS_INT(h) 0x4000000000435c58 ftn => $53 {Hnd const: 0x4000000000435C58} fgCurMemoryVN[GcHeap] assigned for CALL at [001809] to VN: $1f6. N004 [001809] CALL r2r_ind => $VN.Void ***** BB123, STMT00373(after) N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V62 tmp22 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 finish(BB123). Succ(BB124). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#42) at start of BB122 is $6e5 {PhiMemoryDef($5f, $6e4)} The SSA definition for GcHeap (#42) at start of BB122 is $6e5 {PhiMemoryDef($5f, $6e4)} ***** BB122, STMT00374(before) N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 N003 ( 3, 4) [002805] -----O----- \--* ADD byref N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 u:1 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 N001 [002803] LCL_VAR V62 tmp22 u:1 => $100 {InitVal($c0)} N002 [002804] CNS_INT 16 => $200 {LngCns: 16} N003 [002805] ADD => $25c {ADD($100, $200)} N004 [001814] LCL_VAR V93 tmp53 d:1 => $VN.Void Tree [001815] assigned VN to local var V93/1: $25c {ADD($100, $200)} N005 [001815] ASG => $VN.Void ***** BB122, STMT00374(after) N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 --------- ***** BB122, STMT00375(before) N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) N001 [001812] LCL_VAR V91 tmp51 u:1 => N002 [001817] LCL_VAR V93 tmp53 u:1 => $25c {ADD($100, $200)} N003 [002807] CNS_INT 8 => $201 {LngCns: 8} N004 [002808] ADD => $25d {ADD($201, $25c)} N005 [001818] IND => N006 [001819] BOUNDS_CHECK_Rng => N007 [001816] LCL_VAR V93 tmp53 u:1 (last use) => $25c {ADD($100, $200)} N008 [001823] IND => N009 [001813] LCL_VAR V91 tmp51 u:1 => N010 [001820] CAST => N011 [001821] CNS_INT 1 => $204 {LngCns: 1} N012 [001822] LSH => N013 [001824] ADD => N014 [002809] IND => N015 [001825] COMMA => N016 [001826] LCL_VAR V92 tmp52 u:1 (last use) => $c75 {$b16, int <- ushort <- int} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001828] to VN: $1f7. N017 [001828] ASG => ***** BB122, STMT00375(after) N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 --------- ***** BB122, STMT00376(before) N008 ( 8, 8) [001834] -A-XG---R-- * ASG int N007 ( 4, 3) [001833] D--XG--N--- +--* IND int N006 ( 3, 4) [002811] -------N--- | \--* ADD byref N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V62 tmp22 u:1 (last use) N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 N001 [001830] LCL_VAR V91 tmp51 u:1 (last use) => N002 [001831] CNS_INT 1 => $c1 {IntCns 1} N003 [001832] ADD => N004 [001829] LCL_VAR V62 tmp22 u:1 (last use) => $100 {InitVal($c0)} N005 [002810] CNS_INT 8 => $201 {LngCns: 8} N006 [002811] ADD => $25a {ADD($100, $201)} N007 [001833] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001834] to VN: $1f8. N008 [001834] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB122, STMT00376(after) N008 ( 8, 8) [001834] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001833] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V62 tmp22 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 finish(BB122). Succ(BB124). Not yet completed. All preds complete, adding to allDone. Building phi application: $f8 = SSA# 49. Building phi application: $d8 = SSA# 48. Building phi application: $6e6 = phi($d8, $f8). The SSA definition for GcHeap (#43) at start of BB124 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB124, STMT00185(before) N004 ( 5, 6) [000863] ----------- * JTRUE void N003 ( 3, 4) [000862] J------N--- \--* EQ int N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 N001 [000860] LCL_VAR V12 loc8 u:3 => $4c4 {PhiDef($c, $3, $34e)} N002 [000861] CNS_INT 0 => $c0 {IntCns 0} N003 [000862] EQ => $70a {EQ($4c4, $c0)} N004 [000863] JTRUE => $VN.Void ***** BB124, STMT00185(after) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 finish(BB124). Succ(BB125). Not yet completed. All preds complete, adding to allDone. Succ(BB134). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#43) at start of BB125 is $6e7 {PhiMemoryDef($60, $6e6)} The SSA definition for GcHeap (#43) at start of BB125 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB125, STMT00188(before) N004 ( 5, 6) [000877] ----------- * JTRUE void N003 ( 3, 4) [000876] J------N--- \--* LE int N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 N001 [000874] LCL_VAR V08 loc4 u:5 => $b15 {PhiDef($8, $5, $544)} N002 [000875] CNS_INT 1 => $c1 {IntCns 1} N003 [000876] LE => $d03 {LE($b15, $c1)} N004 [000877] JTRUE => $VN.Void ***** BB125, STMT00188(after) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 finish(BB125). Succ(BB126). Not yet completed. All preds complete, adding to allDone. Succ(BB134). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#43) at start of BB126 is $6e7 {PhiMemoryDef($60, $6e6)} The SSA definition for GcHeap (#43) at start of BB126 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB126, STMT00189(before) N004 ( 5, 6) [000881] ----------- * JTRUE void N003 ( 3, 4) [000880] J------N--- \--* LT int N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 N001 [000878] LCL_VAR V20 loc16 u:7 => $b13 {PhiDef($14, $7, $c6d)} N002 [000879] CNS_INT 0 => $c0 {IntCns 0} N003 [000880] LT => $d04 {LT($b13, $c0)} N004 [000881] JTRUE => $VN.Void ***** BB126, STMT00189(after) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 finish(BB126). Succ(BB127). Not yet completed. All preds complete, adding to allDone. Succ(BB134). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#43) at start of BB127 is $6e7 {PhiMemoryDef($60, $6e6)} The SSA definition for GcHeap (#43) at start of BB127 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB127, STMT00190(before) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 N008 ( 4, 6) [000893] ----------- | | \--* LSH long N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 N001 [000885] LCL_VAR V20 loc16 u:7 => $b13 {PhiDef($14, $7, $c6d)} N002 [000889] LCL_VAR V144 tmp104 u:2 => $2a6 {PhiDef($90, $2, $258)} N003 [000890] BOUNDS_CHECK_Rng => $c31 {norm=$VN.Void, exc=$c30 {IndexOutOfRangeExc($b13, $2a6)}} N004 [000894] LCL_VAR V143 tmp103 u:2 => $385 {PhiDef($8f, $2, $258)} N005 [000886] LCL_VAR V20 loc16 u:7 => $b13 {PhiDef($14, $7, $c6d)} N006 [000891] CAST => $ae2 {$b13, long <- uint} N007 [000892] CNS_INT 2 => $20a {LngCns: 2} N008 [000893] LSH => $ae3 {LSH($ae2, $20a)} N009 [000895] ADD => $a6b {ADD($385, $ae3)} N010 [002813] IND => N011 [000896] COMMA => N012 [000898] CNS_INT 1 => $c1 {IntCns 1} N013 [000899] ADD => N014 [000882] LCL_VAR V08 loc4 u:5 => $b15 {PhiDef($8, $5, $544)} N015 [000900] NE => N016 [000901] JTRUE => $c34 {norm=$VN.Void, exc=$c33( {IndexOutOfRangeExc($b13, $2a6)}, {NullPtrExc($a6b)})} ***** BB127, STMT00190(after) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 finish(BB127). Succ(BB128). Not yet completed. All preds complete, adding to allDone. Succ(BB134). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#43) at start of BB128 is $6e7 {PhiMemoryDef($60, $6e6)} The SSA definition for GcHeap (#43) at start of BB128 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB128, STMT00388(before) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] N001 [000903] LCL_VAR V03 arg3 u:1 => $180 {InitVal($c3)} N002 [002814] CNS_INT 56 Fseq[] => $209 {LngCns: 56} N003 [002815] ADD => $24c {ADD($180, $209)} VNForHandle() is $47, fieldType is ref, size = 8 VNForMapSelect($6e7, $47):mem returns $7ac {$6e7[$47]} VNForMapSelect($7ac, $180):ref returns $c35 {$7ac[$180]} N004 [001843] IND => N005 [001895] LCL_VAR V95 tmp55 d:1 => $VN.Void Tree [001896] assigned VN to local var V95/1: N006 [001896] ASG => $321 {norm=$VN.Void, exc=$315 {NullPtrExc($180)}} ***** BB128, STMT00388(after) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 --------- ***** BB128, STMT00379(before) N004 ( 5, 6) [001848] ----------- * JTRUE void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null N001 [001845] LCL_VAR V95 tmp55 u:1 => N002 [001846] CNS_INT null => $VN.Null N003 [001847] EQ => N004 [001848] JTRUE => $VN.Void ***** BB128, STMT00379(after) N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null finish(BB128). Succ(BB129). Not yet completed. All preds complete, adding to allDone. Succ(BB133). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#43) at start of BB129 is $6e7 {PhiMemoryDef($60, $6e6)} The SSA definition for GcHeap (#43) at start of BB129 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB129, STMT00380(before) N006 ( 4, 3) [001851] -A-XG---R-- * ASG int N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 N001 [000902] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002816] CNS_INT 8 => $201 {LngCns: 8} N003 [002817] ADD => $25a {ADD($100, $201)} N004 [001849] IND => N005 [001850] LCL_VAR V96 tmp56 d:1 => $VN.Void Tree [001851] assigned VN to local var V96/1: N006 [001851] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB129, STMT00380(after) N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 --------- ***** BB129, STMT00381(before) N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 N001 [001852] LCL_VAR V95 tmp55 u:1 => N002 [001853] ARR_LENGTH => N003 [001854] CNS_INT 1 => $c1 {IntCns 1} N004 [001855] NE => N005 [001856] JTRUE => ***** BB129, STMT00381(after) N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 finish(BB129). Succ(BB130). Not yet completed. All preds complete, adding to allDone. Succ(BB132). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#43) at start of BB130 is $6e7 {PhiMemoryDef($60, $6e6)} The SSA definition for GcHeap (#43) at start of BB130 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB130, STMT00384(before) N007 ( 8, 7) [001866] ---XG------ * JTRUE void N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 N001 [001860] LCL_VAR V96 tmp56 u:1 => N002 [001861] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N003 [002820] CNS_INT 24 => $20c {LngCns: 24} N004 [002821] ADD => $25b {ADD($100, $20c)} N005 [001899] IND => N006 [001865] GE => N007 [001866] JTRUE => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB130, STMT00384(after) N007 ( 8, 7) [001866] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c finish(BB130). Succ(BB131). Not yet completed. All preds complete, adding to allDone. Succ(BB132). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#43) at start of BB132 is $6e7 {PhiMemoryDef($60, $6e6)} The SSA definition for GcHeap (#43) at start of BB132 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB132, STMT00382(before) N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn N001 [001857] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [001858] LCL_VAR V95 tmp55 u:1 (last use) => N003 [002847] CNS_INT(h) 0x4000000000431d58 ftn => $4f {Hnd const: 0x4000000000431D58} fgCurMemoryVN[GcHeap] assigned for CALL at [001859] to VN: $1f9. N004 [001859] CALL r2r_ind => $VN.Void ***** BB132, STMT00382(after) N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f finish(BB132). Succ(BB133). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#43) at start of BB131 is $6e7 {PhiMemoryDef($60, $6e6)} The SSA definition for GcHeap (#43) at start of BB131 is $6e7 {PhiMemoryDef($60, $6e6)} ***** BB131, STMT00385(before) N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 N003 ( 3, 4) [002827] -----O----- \--* ADD byref N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 N001 [002825] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N002 [002826] CNS_INT 16 => $200 {LngCns: 16} N003 [002827] ADD => $25c {ADD($100, $200)} N004 [001871] LCL_VAR V97 tmp57 d:1 => $VN.Void Tree [001872] assigned VN to local var V97/1: $25c {ADD($100, $200)} N005 [001872] ASG => $VN.Void ***** BB131, STMT00385(after) N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 --------- ***** BB131, STMT00386(before) N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $81 N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 N001 [001869] LCL_VAR V96 tmp56 u:1 => N002 [001874] LCL_VAR V97 tmp57 u:1 => $25c {ADD($100, $200)} N003 [002829] CNS_INT 8 => $201 {LngCns: 8} N004 [002830] ADD => $25d {ADD($201, $25c)} N005 [001875] IND => N006 [001876] BOUNDS_CHECK_Rng => N007 [001873] LCL_VAR V97 tmp57 u:1 (last use) => $25c {ADD($100, $200)} N008 [001880] IND => N009 [001870] LCL_VAR V96 tmp56 u:1 => N010 [001877] CAST => N011 [001878] CNS_INT 1 => $204 {LngCns: 1} N012 [001879] LSH => N013 [001881] ADD => N014 [002831] IND => N015 [001882] COMMA => N016 [001884] CNS_INT 0 => $c0 {IntCns 0} N017 [001883] LCL_VAR V95 tmp55 u:1 => N018 [002834] ARR_LENGTH => N019 [002835] BOUNDS_CHECK_Rng => N020 [002832] LCL_VAR V95 tmp55 u:1 (last use) => N021 [002838] CNS_INT 12 => $20d {LngCns: 12} N022 [002839] ADD => VNForHandle(arrElemType: ushort) is $41 N023 [002841] ARR_ADDR => $89 {PtrToArrElem($41, $c35, $205, $205)} Array element load: elemTypeEq is $41 for short[] VNForMapSelect($6e7, $41):mem returns $7af {$6e7[$41]} GcHeap[elemTypeEq: $41] is $7af VNForMapSelect($7af, $c35):mem returns $7b0 {$7af[$c35]} GcHeap[elemTypeEq][array: $c35] is $7b0 VNForMapSelect($7b0, $205):short returns $8c5 {$7b0[$205]} GcHeap[elemTypeEq][array][index: $205] is $8c5 VNForLoadStoreBitcast returns $676 {BitCast($8c5)} N024 [002844] IND => ($8c5)}, c:$620 {MemOpaque:L03}> N025 [002842] COMMA => ($8c5)}, exc=$d54( {NullPtrExc($c35)}, {IndexOutOfRangeExc($c0, $c89)})}, c:$678 {norm=$620 {MemOpaque:L03}, exc=$d55( {NullPtrExc($cc3)}, {IndexOutOfRangeExc($c0, $c8a)})}> fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001888] to VN: $1fa. N026 [001888] ASG => ***** BB131, STMT00386(after) N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d --------- ***** BB131, STMT00387(before) N008 ( 8, 8) [001894] -A-XG---R-- * ASG int N007 ( 4, 3) [001893] D--XG--N--- +--* IND int N006 ( 3, 4) [002846] -------N--- | \--* ADD byref N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 N001 [001890] LCL_VAR V96 tmp56 u:1 (last use) => N002 [001891] CNS_INT 1 => $c1 {IntCns 1} N003 [001892] ADD => N004 [001889] LCL_VAR V00 arg0 u:1 => $100 {InitVal($c0)} N005 [002845] CNS_INT 8 => $201 {LngCns: 8} N006 [002846] ADD => $25a {ADD($100, $201)} N007 [001893] IND => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [001894] to VN: $1fb. N008 [001894] ASG => $845 {norm=$VN.Void, exc=$844 {NullPtrExc($100)}} ***** BB131, STMT00387(after) N008 ( 8, 8) [001894] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001893] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 finish(BB131). Succ(BB133). Not yet completed. All preds complete, adding to allDone. Building phi application: $f9 = SSA# 47. Building phi application: $eb = SSA# 46. Building phi application: $6e8 = phi($eb, $f9). Building phi application: $d9 = SSA# 43. Building phi application: $6e9 = phi($d9, $6e8). The SSA definition for GcHeap (#45) at start of BB133 is $6ea {PhiMemoryDef($61, $6e9)} ***** BB133, STMT00193(before) N005 ( 3, 4) [000911] -A------R-- * ASG int N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 N003 ( 3, 4) [000909] ----------- \--* ADD int N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 N001 [000907] LCL_VAR V20 loc16 u:7 (last use) => $b13 {PhiDef($14, $7, $c6d)} N002 [000908] CNS_INT -1 => $c4 {IntCns 4294967295} N003 [000909] ADD => $d27 {ADD($c4, $b13)} N004 [000910] LCL_VAR V20 loc16 d:9 => $VN.Void Tree [000911] assigned VN to local var V20/9: $d27 {ADD($c4, $b13)} N005 [000911] ASG => $VN.Void ***** BB133, STMT00193(after) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 finish(BB133). Succ(BB134). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 20/8 to $b1e {PhiDef($14, $8, $d28)} . Building phi application: $da = SSA# 45. Building phi application: $d9 = SSA# 43. Building phi application: $6eb = phi($d9, $da). The SSA definition for GcHeap (#44) at start of BB134 is $6ec {PhiMemoryDef($62, $6eb)} ***** BB134, STMT00186(before) N005 ( 3, 4) [000868] -A------R-- * ASG int N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 N003 ( 3, 4) [000866] ----------- \--* ADD int N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 N001 [000864] LCL_VAR V08 loc4 u:5 (last use) => $b15 {PhiDef($8, $5, $544)} N002 [000865] CNS_INT -1 => $c4 {IntCns 4294967295} N003 [000866] ADD => $d29 {ADD($c4, $b15)} N004 [000867] LCL_VAR V08 loc4 d:6 => $VN.Void Tree [000868] assigned VN to local var V08/6: $d29 {ADD($c4, $b15)} N005 [000868] ASG => $VN.Void ***** BB134, STMT00186(after) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 --------- ***** BB134, STMT00187(before) N005 ( 3, 4) [000873] -A------R-- * ASG int N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 N003 ( 3, 4) [000871] ----------- \--* ADD int N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 N001 [000869] LCL_VAR V14 loc10 u:6 (last use) => $b14 {PhiDef($e, $6, $3e4)} N002 [000870] CNS_INT -1 => $c4 {IntCns 4294967295} N003 [000871] ADD => $d2a {ADD($c4, $b14)} N004 [000872] LCL_VAR V14 loc10 d:7 => $VN.Void Tree [000873] assigned VN to local var V14/7: $d2a {ADD($c4, $b14)} N005 [000873] ASG => $VN.Void ***** BB134, STMT00187(after) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 finish(BB134). Succ(BB135). *************** Finishing PHASE Do value numbering Trees after Do value numbering ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N007 ( 14, 14) [002563] -A--------- * COMMA void $VN.Void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N006 ( 7, 7) [002562] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V167 tmp127 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 3, 4) [002606] -A--------- * COMMA void $580 N003 ( 3, 4) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 7, 8) [001441] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N010 ( 13, 15) [001452] ---XG------ * JTRUE void $876 N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V16 loc12 u:21 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N010 ( 13, 14) [001471] ---XG------ * JTRUE void $876 N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001466] ----------- | \--* LSH long $3df N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 7, 8) [001240] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N010 ( 13, 15) [001251] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 7, 8) [001267] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N010 ( 13, 15) [001351] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 9, 11) [001276] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N010 ( 13, 15) [001287] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N010 ( 13, 15) [001340] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001335] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 7, 8) [001315] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V73 tmp33 u:1 (last use) $942 N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 7, 8) [000079] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V16 loc12 u:2 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V72 tmp32 u:1 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] D--XG--N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool $301 N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int $301 N004 ( 4, 3) [000104] D--XG--N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N007 ( 8, 7) [000140] ---XG------ * JTRUE void $301 N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int $301 N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref $24a N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 $207 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 5, 6) [001590] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001589] J------N--- \--* NE int $c1 N001 ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [001588] ----------- \--* CNS_INT ref null $VN.Null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 5, 6) [001702] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001701] J------N--- \--* NE int $c1 N001 ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [001700] ----------- \--* CNS_INT ref null $VN.Null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V15 loc11 u:2 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void $845 N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001780] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 3, 4) [002788] -A--------- * COMMA void $588 N003 ( 3, 4) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N005 ( 8, 8) [000834] ---XG------ * JTRUE void $c1a N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 $904 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V36 loc32 u:7 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int $c1a N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) $904 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V62 tmp22 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V62 tmp22 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001833] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V62 tmp22 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V62 tmp22 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001893] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V36 loc32 u:3 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001938] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001996] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002056] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002116] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002176] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort $bec N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long $acc N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000817] ----------- \--* LSH long $acb N003 ( 2, 3) [000814] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 $204 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002222] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 7, 8) [000757] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N010 ( 13, 15) [000791] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N010 ( 13, 14) [000802] ---XG------ * JTRUE void $bec N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000797] ----------- | \--* LSH long $acb N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 7, 8) [000764] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N010 ( 13, 15) [000775] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 7, 8) [000289] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N010 ( 13, 15) [000300] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000315] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002280] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 7, 8) [000425] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N010 ( 13, 15) [000575] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 9, 11) [000434] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N010 ( 13, 15) [000548] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) N006 ( 9, 11) [000443] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000442] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000437] ----------- +--* ADD int $952 N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N010 ( 13, 15) [000457] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000452] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002337] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 7, 8) [000485] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V54 tmp14 u:1 (last use) $c5c N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002384] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 7, 8) [000342] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N010 ( 13, 15) [000353] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N010 ( 13, 15) [000418] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000413] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000368] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000365] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 $204 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002432] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V16 loc12 u:6 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort $c02 N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000404] ----------- \--* LSH long $ad2 N003 ( 2, 3) [000401] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 $204 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002478] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 7, 8) [000378] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N010 ( 13, 15) [000389] ---XG------ * JTRUE void $c02 N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002527] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 7, 8) [000210] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V16 loc12 u:4 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V50 tmp10 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [info] NumUses overestimated for V00.1: IR 73 SSA 101 [info] NumUses overestimated for V01.1: IR 17 SSA 21 [info] NumUses overestimated for V33.1: IR 6 SSA 10 [info] NumUses overestimated for V62.1: IR 5 SSA 7 SSA checks completed successfully *************** In fgDebugCheckLoopTable *************** Starting PHASE Hoist loop code *************** In optHoistLoopCode() *************** Exception Handling table is empty *************** Natural loop table L00, from BB07 to BB62 (Head=BB06, Entry=BB07, ExitCnt=3), child loop = L01 call L01, from BB08 to BB49 (Head=BB07, Entry=BB47, ExitCnt=3, parent=L00) L02, from BB89 to BB102 (Head=BB88, Entry=BB89, ExitCnt=3) call L03, from BB113 to BB247 (Head=BB112, Entry=BB245, ExitCnt=3) call Loop Nest L00 Nested Loop L01 optHoistThisLoop for loop L01 : Loop body does not contain a call Loop has multiple exits USEDEF (17)={V02 V04 V05 V06 V07 V09 V10 V11 V12 V13 V16 V18 V22 V71 V72 V73 V74} INOUT (18)={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22} LOOPVARS(13)={V02 V04 V05 V06 V07 V09 V10 V11 V12 V13 V16 V18 V22} Considering hoisting in entry block BB47 because L01 has more than one exit -- BB47 (entry block) optHoistLoopBlocks BB47 (weight= 64 ) of loop L01 ----- PreOrderVisit for [000079] JTRUE ----- PreOrderVisit for [000078] GE ----- PreOrderVisit for [000073] LCL_VAR ----- PostOrderVisit for [000073] LCL_VAR [000073] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [001538] LCL_FLD ----- PostOrderVisit for [001538] LCL_FLD [001538] LCL_FLD: hoistable: unset ----- PostOrderVisit for [000078] GE [000079] not invariant: unset [000078] not hoistable : current node [000073] not invariant: local, not rvalue / not in SSA / defined within current loop [001538] hoistable *************** In fgCreateLoopPreHeader for L01 converting existing header BB07 into pre-header *************** In fgDebugCheckLoopTable Hoisting a copy of [001538] $342 from BB47 into PreHeader BB07 for loop L01 : N002 ( 3, 4) [001538] ----------- * LCL_FLD int V02 arg2 u:1[+8] $342 This hoisted copy placed in PreHeader (BB07): [003623] ----------- * COMMA void ( 3, 4) [003621] -------H--- +--* LCL_FLD int V02 arg2 u:1[+8] $342 [003622] ----------- \--* NOP void ----- PostOrderVisit for [000079] JTRUE [000079] not invariant: variant child Resetting m_pHoistedInCurLoop PREHEADER: BB07 optHoistThisLoop for loop L00 : Loop body contains a call Loop has multiple exits USEDEF (25)={V01 V02 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V69 V70 V71 V72 V73 V74 V157 V158 V168} INOUT (19)={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V70} LOOPVARS(17)={V01 V02 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V70} Considering hoisting in entry block BB07 because L00 has more than one exit -- BB07 (preheader of L01) -- BB07 (entry block) optHoistLoopBlocks BB07 (weight= 8 ) of loop L00 ----- PreOrderVisit for [000037] ASG ----- PreOrderVisit for [000035] CNS_INT ----- PostOrderVisit for [000035] CNS_INT ----- PreOrderVisit for [000036] LCL_VAR ----- PostOrderVisit for [000036] LCL_VAR [000036] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000037] ASG [000037] not invariant: variant child ----- PreOrderVisit for [000040] ASG ----- PreOrderVisit for [000038] CNS_INT ----- PostOrderVisit for [000038] CNS_INT ----- PreOrderVisit for [000039] LCL_VAR ----- PostOrderVisit for [000039] LCL_VAR [000039] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000040] ASG [000040] not invariant: variant child ----- PreOrderVisit for [000043] ASG ----- PreOrderVisit for [000041] CNS_INT ----- PostOrderVisit for [000041] CNS_INT ----- PreOrderVisit for [000042] LCL_VAR ----- PostOrderVisit for [000042] LCL_VAR [000042] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000043] ASG [000043] not invariant: variant child ----- PreOrderVisit for [000046] ASG ----- PreOrderVisit for [000044] CNS_INT ----- PostOrderVisit for [000044] CNS_INT ----- PreOrderVisit for [000045] LCL_VAR ----- PostOrderVisit for [000045] LCL_VAR [000045] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000046] ASG [000046] not invariant: variant child ----- PreOrderVisit for [000049] ASG ----- PreOrderVisit for [002598] CNS_INT ----- PostOrderVisit for [002598] CNS_INT ----- PreOrderVisit for [000048] LCL_VAR ----- PostOrderVisit for [000048] LCL_VAR [000048] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000049] ASG [000049] not invariant: variant child ----- PreOrderVisit for [000052] ASG ----- PreOrderVisit for [000050] CNS_INT ----- PostOrderVisit for [000050] CNS_INT ----- PreOrderVisit for [000051] LCL_VAR ----- PostOrderVisit for [000051] LCL_VAR [000051] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000052] ASG [000052] not invariant: variant child ----- PreOrderVisit for [000055] ASG ----- PreOrderVisit for [002599] CNS_INT ----- PostOrderVisit for [002599] CNS_INT ----- PreOrderVisit for [000054] LCL_VAR ----- PostOrderVisit for [000054] LCL_VAR [000054] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000055] ASG [000055] not invariant: variant child ----- PreOrderVisit for [000058] ASG ----- PreOrderVisit for [000056] CNS_INT ----- PostOrderVisit for [000056] CNS_INT ----- PreOrderVisit for [000057] LCL_VAR ----- PostOrderVisit for [000057] LCL_VAR [000057] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000058] ASG [000058] not invariant: variant child ----- PreOrderVisit for [000061] ASG ----- PreOrderVisit for [000059] LCL_VAR ----- PostOrderVisit for [000059] LCL_VAR [000059] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [000060] LCL_VAR ----- PostOrderVisit for [000060] LCL_VAR [000060] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000061] ASG [000061] not invariant: variant child ----- PreOrderVisit for [002606] COMMA ----- PreOrderVisit for [002602] ASG ----- PreOrderVisit for [002601] LCL_FLD ----- PostOrderVisit for [002601] LCL_FLD [002601] LCL_FLD: hoistable: unset ----- PreOrderVisit for [002600] LCL_VAR ----- PostOrderVisit for [002600] LCL_VAR [002600] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [002602] ASG [002606] not invariant: unset [002602] not hoistable : current node [002601] hoistable tree cost too low: 3 < 6 (loopVarCount 17 >= availableRegCount 10) ... not profitable to hoist [002600] not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [002605] NOP ----- PostOrderVisit for [002605] NOP ----- PostOrderVisit for [002606] COMMA [002606] not invariant: variant child ----- PreOrderVisit for [000068] ASG ----- PreOrderVisit for [001512] LCL_VAR ----- PostOrderVisit for [001512] LCL_VAR [001512] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [000067] LCL_VAR ----- PostOrderVisit for [000067] LCL_VAR [000067] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000068] ASG [000068] not invariant: variant child ----- PreOrderVisit for [000072] ASG ----- PreOrderVisit for [002611] COMMA ----- PreOrderVisit for [002608] ASG ----- PreOrderVisit for [000069] LCL_VAR ----- PostOrderVisit for [000069] LCL_VAR [000069] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [002607] LCL_VAR ----- PostOrderVisit for [002607] LCL_VAR [002607] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [002608] ASG ----- PreOrderVisit for [002609] LCL_VAR ----- PostOrderVisit for [002609] LCL_VAR [002609] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [002611] COMMA ----- PreOrderVisit for [000071] LCL_VAR ----- PostOrderVisit for [000071] LCL_VAR [000071] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000072] ASG [000072] not invariant: variant child ----- PreOrderVisit for [003623] COMMA ----- PreOrderVisit for [003621] LCL_FLD ----- PostOrderVisit for [003621] LCL_FLD [003621] LCL_FLD: hoistable: unset ----- PreOrderVisit for [003622] NOP ----- PostOrderVisit for [003622] NOP ----- PostOrderVisit for [003623] COMMA [003623] not hoistable : current node [003621] hoistable tree cost too low: 3 < 6 (loopVarCount 17 >= availableRegCount 10) ... not profitable to hoist [003622] not invariant: tree VN is loop variant [003623] not invariant: variant child optHoistLoopBlocks BB07 (weight= 8 ) of loop L00 ----- PreOrderVisit for [000037] ASG ----- PreOrderVisit for [000035] CNS_INT ----- PostOrderVisit for [000035] CNS_INT ----- PreOrderVisit for [000036] LCL_VAR ----- PostOrderVisit for [000036] LCL_VAR [000036] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000037] ASG [000037] not invariant: variant child ----- PreOrderVisit for [000040] ASG ----- PreOrderVisit for [000038] CNS_INT ----- PostOrderVisit for [000038] CNS_INT ----- PreOrderVisit for [000039] LCL_VAR ----- PostOrderVisit for [000039] LCL_VAR [000039] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000040] ASG [000040] not invariant: variant child ----- PreOrderVisit for [000043] ASG ----- PreOrderVisit for [000041] CNS_INT ----- PostOrderVisit for [000041] CNS_INT ----- PreOrderVisit for [000042] LCL_VAR ----- PostOrderVisit for [000042] LCL_VAR [000042] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000043] ASG [000043] not invariant: variant child ----- PreOrderVisit for [000046] ASG ----- PreOrderVisit for [000044] CNS_INT ----- PostOrderVisit for [000044] CNS_INT ----- PreOrderVisit for [000045] LCL_VAR ----- PostOrderVisit for [000045] LCL_VAR [000045] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000046] ASG [000046] not invariant: variant child ----- PreOrderVisit for [000049] ASG ----- PreOrderVisit for [002598] CNS_INT ----- PostOrderVisit for [002598] CNS_INT ----- PreOrderVisit for [000048] LCL_VAR ----- PostOrderVisit for [000048] LCL_VAR [000048] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000049] ASG [000049] not invariant: variant child ----- PreOrderVisit for [000052] ASG ----- PreOrderVisit for [000050] CNS_INT ----- PostOrderVisit for [000050] CNS_INT ----- PreOrderVisit for [000051] LCL_VAR ----- PostOrderVisit for [000051] LCL_VAR [000051] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000052] ASG [000052] not invariant: variant child ----- PreOrderVisit for [000055] ASG ----- PreOrderVisit for [002599] CNS_INT ----- PostOrderVisit for [002599] CNS_INT ----- PreOrderVisit for [000054] LCL_VAR ----- PostOrderVisit for [000054] LCL_VAR [000054] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000055] ASG [000055] not invariant: variant child ----- PreOrderVisit for [000058] ASG ----- PreOrderVisit for [000056] CNS_INT ----- PostOrderVisit for [000056] CNS_INT ----- PreOrderVisit for [000057] LCL_VAR ----- PostOrderVisit for [000057] LCL_VAR [000057] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000058] ASG [000058] not invariant: variant child ----- PreOrderVisit for [000061] ASG ----- PreOrderVisit for [000059] LCL_VAR ----- PostOrderVisit for [000059] LCL_VAR [000059] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [000060] LCL_VAR ----- PostOrderVisit for [000060] LCL_VAR [000060] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000061] ASG [000061] not invariant: variant child ----- PreOrderVisit for [002606] COMMA ----- PreOrderVisit for [002602] ASG ----- PreOrderVisit for [002601] LCL_FLD ----- PostOrderVisit for [002601] LCL_FLD [002601] LCL_FLD: hoistable: unset ----- PreOrderVisit for [002600] LCL_VAR ----- PostOrderVisit for [002600] LCL_VAR [002600] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [002602] ASG [002606] not invariant: unset [002602] not hoistable : current node [002601] hoistable tree cost too low: 3 < 6 (loopVarCount 17 >= availableRegCount 10) ... not profitable to hoist [002600] not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [002605] NOP ----- PostOrderVisit for [002605] NOP ----- PostOrderVisit for [002606] COMMA [002606] not invariant: variant child ----- PreOrderVisit for [000068] ASG ----- PreOrderVisit for [001512] LCL_VAR ----- PostOrderVisit for [001512] LCL_VAR [001512] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [000067] LCL_VAR ----- PostOrderVisit for [000067] LCL_VAR [000067] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000068] ASG [000068] not invariant: variant child ----- PreOrderVisit for [000072] ASG ----- PreOrderVisit for [002611] COMMA ----- PreOrderVisit for [002608] ASG ----- PreOrderVisit for [000069] LCL_VAR ----- PostOrderVisit for [000069] LCL_VAR [000069] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [002607] LCL_VAR ----- PostOrderVisit for [002607] LCL_VAR [002607] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [002608] ASG ----- PreOrderVisit for [002609] LCL_VAR ----- PostOrderVisit for [002609] LCL_VAR [002609] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [002611] COMMA ----- PreOrderVisit for [000071] LCL_VAR ----- PostOrderVisit for [000071] LCL_VAR [000071] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PostOrderVisit for [000072] ASG [000072] not invariant: variant child ----- PreOrderVisit for [003623] COMMA ----- PreOrderVisit for [003621] LCL_FLD ----- PostOrderVisit for [003621] LCL_FLD [003621] LCL_FLD: hoistable: unset ----- PreOrderVisit for [003622] NOP ----- PostOrderVisit for [003622] NOP ----- PostOrderVisit for [003623] COMMA [003623] not hoistable : current node [003621] hoistable tree cost too low: 3 < 6 (loopVarCount 17 >= availableRegCount 10) ... not profitable to hoist [003622] not invariant: tree VN is loop variant [003623] not invariant: variant child Resetting m_pHoistedInCurLoop Loop Nest L02 optHoistThisLoop for loop L02 : Loop body contains a call Loop has multiple exits USEDEF (19)={V20 V26 V27 V28 V29 V30 V32 V33 V81 V82 V83 V143 V144 V159 V160 V161 V162 V163 V164} INOUT (30)={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159 V160 V161 V163 V164} LOOPVARS(15)={V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159 V160 V161 V163 V164} Considering hoisting in entry block BB89 because L02 has more than one exit -- BB89 (entry block) optHoistLoopBlocks BB89 (weight= 4 ) of loop L02 ----- PreOrderVisit for [001009] JTRUE ----- PreOrderVisit for [001008] EQ ----- PreOrderVisit for [001006] LCL_VAR ----- PostOrderVisit for [001006] LCL_VAR [001006] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [001007] CNS_INT ----- PostOrderVisit for [001007] CNS_INT ----- PostOrderVisit for [001008] EQ ----- PostOrderVisit for [001009] JTRUE [001009] not invariant: variant child Resetting m_pHoistedInCurLoop Loop Nest L03 optHoistThisLoop for loop L03 : Loop body contains a call Loop has multiple exits USEDEF (76)={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V16 V17 V18 V20 V21 V34 V36 V37 V38 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 V91 V92 V93 V95 V96 V97 V99 V100 V102 V103 V104 V106 V107 V108 V110 V111 V112 V114 V115 V116 V118 V119 V120 V122 V123 V124 V126 V127 V129 V130 V132 V133 V134 V136 V137 V138 V140 V141 V143 V144} INOUT (54)={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V57 V58 V60 V62 V63 V91 V92 V95 V96 V99 V102 V103 V106 V107 V110 V111 V114 V115 V118 V119 V122 V123 V126 V129 V132 V133 V136 V137 V140 V143 V144} LOOPVARS(53)={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V57 V58 V60 V62 V63 V91 V92 V95 V96 V99 V102 V103 V106 V107 V110 V111 V114 V115 V118 V119 V122 V123 V126 V129 V132 V133 V136 V137 V140 V143 V144} Considering hoisting in entry block BB245 because L03 has more than one exit -- BB245 (entry block) optHoistLoopBlocks BB245 (weight= 8 ) of loop L03 ----- PreOrderVisit for [000210] JTRUE ----- PreOrderVisit for [000209] GE ----- PreOrderVisit for [000204] LCL_VAR ----- PostOrderVisit for [000204] LCL_VAR [000204] LCL_VAR: not invariant: local, not rvalue / not in SSA / defined within current loop ----- PreOrderVisit for [002537] LCL_FLD ----- PostOrderVisit for [002537] LCL_FLD [002537] LCL_FLD: hoistable: unset ----- PostOrderVisit for [000209] GE [000210] not invariant: unset [000209] not hoistable : current node [000204] not invariant: local, not rvalue / not in SSA / defined within current loop [002537] hoistable tree cost too low: 3 < 6 (loopVarCount 53 >= availableRegCount 10) ... not profitable to hoist ----- PostOrderVisit for [000210] JTRUE [000210] not invariant: variant child Resetting m_pHoistedInCurLoop *************** Finishing PHASE Hoist loop code Trees after Hoist loop code ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N007 ( 14, 14) [002563] -A--------- * COMMA void $VN.Void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N006 ( 7, 7) [002562] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V167 tmp127 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 3, 4) [002606] -A--------- * COMMA void $580 N003 ( 3, 4) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 3, 4) [003623] ----------- * COMMA void N001 ( 3, 4) [003621] -------H--- +--* LCL_FLD int V02 arg2 u:1[+8] $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 7, 8) [001441] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N010 ( 13, 15) [001452] ---XG------ * JTRUE void $876 N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V16 loc12 u:21 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N010 ( 13, 14) [001471] ---XG------ * JTRUE void $876 N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001466] ----------- | \--* LSH long $3df N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 7, 8) [001240] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N010 ( 13, 15) [001251] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 7, 8) [001267] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N010 ( 13, 15) [001351] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 9, 11) [001276] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N010 ( 13, 15) [001287] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N010 ( 13, 15) [001340] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001335] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 7, 8) [001315] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V73 tmp33 u:1 (last use) $942 N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 7, 8) [000079] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V16 loc12 u:2 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V72 tmp32 u:1 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] D--XG--N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool $301 N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int $301 N004 ( 4, 3) [000104] D--XG--N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N007 ( 8, 7) [000140] ---XG------ * JTRUE void $301 N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int $301 N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref $24a N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 $207 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 5, 6) [001590] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001589] J------N--- \--* NE int $c1 N001 ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [001588] ----------- \--* CNS_INT ref null $VN.Null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 5, 6) [001702] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001701] J------N--- \--* NE int $c1 N001 ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [001700] ----------- \--* CNS_INT ref null $VN.Null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V15 loc11 u:2 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void $845 N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001780] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 3, 4) [002788] -A--------- * COMMA void $588 N003 ( 3, 4) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N005 ( 8, 8) [000834] ---XG------ * JTRUE void $c1a N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 $904 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V36 loc32 u:7 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V60 tmp20 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int $c1a N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) $904 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V62 tmp22 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V62 tmp22 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V62 tmp22 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001833] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V62 tmp22 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V62 tmp22 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001893] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V36 loc32 u:3 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001938] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001996] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002056] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002116] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002176] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort $bec N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long $acc N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000817] ----------- \--* LSH long $acb N003 ( 2, 3) [000814] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 $204 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002222] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 7, 8) [000757] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N010 ( 13, 15) [000791] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N010 ( 13, 14) [000802] ---XG------ * JTRUE void $bec N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000797] ----------- | \--* LSH long $acb N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 7, 8) [000764] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N010 ( 13, 15) [000775] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 7, 8) [000289] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N010 ( 13, 15) [000300] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000315] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002280] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 7, 8) [000425] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N010 ( 13, 15) [000575] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 9, 11) [000434] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N010 ( 13, 15) [000548] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) N006 ( 9, 11) [000443] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000442] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000437] ----------- +--* ADD int $952 N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N010 ( 13, 15) [000457] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000452] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002337] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 7, 8) [000485] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V54 tmp14 u:1 (last use) $c5c N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002384] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 7, 8) [000342] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N010 ( 13, 15) [000353] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N010 ( 13, 15) [000418] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000413] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V16 loc12 u:5 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000368] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000365] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 $204 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002432] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V16 loc12 u:6 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort $c02 N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000404] ----------- \--* LSH long $ad2 N003 ( 2, 3) [000401] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 $204 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002478] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 7, 8) [000378] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N010 ( 13, 15) [000389] ---XG------ * JTRUE void $c02 N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002527] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 7, 8) [000210] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V16 loc12 u:4 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V50 tmp10 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [info] NumUses overestimated for V00.1: IR 73 SSA 101 [info] NumUses overestimated for V01.1: IR 17 SSA 21 [info] NumUses overestimated for V33.1: IR 6 SSA 10 [info] NumUses overestimated for V62.1: IR 5 SSA 7 SSA checks completed successfully *************** In fgDebugCheckLoopTable *************** Starting PHASE VN based copy prop Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00 V01 V02 V03} => {V00 V01 V02 V03 V11} Live vars: {V00 V01 V02 V03 V11} => {V00 V01 V02 V03 V11 V76} Live vars: {V00 V01 V02 V03 V11 V76} => {V00 V01 V02 V03 V11} Live vars: {V00 V01 V02 V03 V11} => {V00 V01 V02 V03 V11 V167} Live vars: {V00 V01 V02 V03 V11 V167} => {V00 V01 V02 V03 V11 V17 V167} Live vars: {V00 V01 V02 V03 V11 V17 V167} => {V00 V01 V02 V03 V11 V17 V147 V167} Live vars: {V00 V01 V02 V03 V11 V17 V147 V167} => {V00 V01 V02 V03 V11 V17 V147 V148 V167} Live vars: {V00 V01 V02 V03 V11 V17 V147 V148 V167} => {V00 V01 V02 V03 V11 V17 V147 V148} VN based copy assertion for [000011] V167 $3c1 by [000008] V17 $3c1. N001 ( 1, 1) [000011] ----------- * LCL_VAR long V167 tmp127 u:1 (last use) copy propagated to: N001 ( 1, 1) [000011] ----------- * LCL_VAR long V17 loc13 u:1 (last use) Copy Assertion for BB06 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [002550]:V167/1 [001499]:V76/1 [002557]:V147/1 [002560]:V148/1 [000003]:V11/1 [000008]:V17/1 } Live vars: {V00 V01 V02 V03 V11 V17 V43 V149 V150} => {V00 V01 V02 V03 V11 V17 V43 V150} Live vars: {V00 V01 V02 V03 V11 V17 V43 V150} => {V00 V01 V02 V03 V11 V17 V43} Live vars: {V00 V01 V02 V03 V11 V17 V43} => {V00 V01 V02 V03 V11 V17} Live vars: {V00 V01 V02 V03 V11 V17} => {V00 V01 V02 V03 V11 V15 V17} Copy Assertion for BB07 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [002550]:V167/1 [001499]:V76/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [000003]:V11/1 [003412]:V150/NA [000033]:V15/1 [000008]:V17/1 [003409]:V43/NA } Live vars: {V00 V01 V02 V03 V11 V15 V17} => {V00 V01 V02 V03 V04 V11 V15 V17} Live vars: {V00 V01 V02 V03 V04 V11 V15 V17} => {V00 V01 V02 V03 V04 V05 V11 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V11 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V11 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V11 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V11 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V11 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V157} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V157} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V168} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V168} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB47 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [000036]:V04/1 [000039]:V05/1 [000042]:V06/1 [000045]:V07/1 [000048]:V09/1 [000051]:V10/1 [003376]:V11/NA [000054]:V12/1 [000057]:V13/1 [003160]:V15/NA [000060]:V16/1 [000008]:V17/1 [001499]:V76/1 [000071]:V22/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [002600]:V157/1 [003409]:V43/NA [002550]:V167/1 [002607]:V168/1 } Copy Assertion for BB50 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [003364]:V16/NA [000008]:V17/1 [001499]:V76/1 [000071]:V22/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [002600]:V157/1 [003409]:V43/NA [002550]:V167/1 [002607]:V168/1 } Copy Assertion for BB52 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [003364]:V16/NA [000008]:V17/1 [001499]:V76/1 [000071]:V22/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [002600]:V157/1 [003409]:V43/NA [002550]:V167/1 [002607]:V168/1 } Copy Assertion for BB56 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [003364]:V16/NA [000008]:V17/1 [001499]:V76/1 [000071]:V22/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [002600]:V157/1 [003409]:V43/NA [002550]:V167/1 [002607]:V168/1 } Copy Assertion for BB66 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [003364]:V16/NA [000008]:V17/1 [001499]:V76/1 [000071]:V22/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [002600]:V157/1 [003409]:V43/NA [002550]:V167/1 [002607]:V168/1 } Copy Assertion for BB69 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [003364]:V16/NA [000008]:V17/1 [001499]:V76/1 [000071]:V22/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [002600]:V157/1 [003409]:V43/NA [002550]:V167/1 [002607]:V168/1 } Live vars: {V00 V01 V02 V03 V04 V05 V07 V09 V12 V15 V17 V44} => {V00 V01 V02 V03 V04 V05 V07 V09 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} Copy Assertion for BB72 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [003364]:V16/NA [000008]:V17/1 [001499]:V76/1 [000071]:V22/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [002550]:V167/1 [002607]:V168/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V12 V15 V17 V45} => {V00 V01 V02 V03 V04 V05 V06 V09 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} Copy Assertion for BB78 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [003364]:V16/NA [000008]:V17/1 [001499]:V76/1 [000071]:V22/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002550]:V167/1 [002607]:V168/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V151} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V151} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V151 V152} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V151 V152} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V152} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V152} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V143 V152} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V143 V152} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V143} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V143} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144} Copy Assertion for BB103 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [000156]:V16/3 [000008]:V17/1 [001499]:V76/1 [000176]:V20/1 [000071]:V22/1 [002648]:V143/1 [002651]:V144/1 [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001557]:V152/1 [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002550]:V167/1 [002607]:V168/1 } Copy Assertion for BB112 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [000156]:V16/3 [000008]:V17/1 [001499]:V76/1 [003316]:V20/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001557]:V152/1 [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002550]:V167/1 [002607]:V168/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144 V165} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144 V165} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144 V169} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144 V169} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB245 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [000156]:V16/3 [000008]:V17/1 [001499]:V76/1 [003316]:V20/NA [000188]:V21/1 [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [000202]:V36/1 [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [002550]:V167/1 [002607]:V168/1 [002789]:V169/1 } Copy Assertion for BB248 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [003163]:V16/NA [000008]:V17/1 [001499]:V76/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [002550]:V167/1 [002607]:V168/1 [002789]:V169/1 } Copy Assertion for BB253 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [003163]:V16/NA [000008]:V17/1 [001499]:V76/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [002550]:V167/1 [002607]:V168/1 [002789]:V169/1 } Copy Assertion for BB249 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [003163]:V16/NA [000008]:V17/1 [001499]:V76/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [002550]:V167/1 [002607]:V168/1 [002789]:V169/1 } Live vars: {V00 V01 V03 V15} => {V00 V01 V03} Copy Assertion for BB250 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [003163]:V16/NA [000008]:V17/1 [001499]:V76/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [002550]:V167/1 [002607]:V168/1 [002789]:V169/1 } Live vars: {V00 V01 V03} => {V00 V03} Copy Assertion for BB251 curSsaName stack: { [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [003163]:V16/NA [000008]:V17/1 [001499]:V76/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [002550]:V167/1 [002607]:V168/1 [002789]:V169/1 } Copy Assertion for BB252 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [003163]:V16/NA [000008]:V17/1 [001499]:V76/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [002550]:V167/1 [002607]:V168/1 [002789]:V169/1 } Live vars: {V00 V03} => {V00} Live vars: {V00} => {} Copy Assertion for BB246 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [003163]:V16/NA [000008]:V17/1 [001499]:V76/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [002550]:V167/1 [002607]:V168/1 [002789]:V169/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V49 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V49 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V49 V143 V144} VN based copy assertion for [000244] V16 $2ae by [000249] V49 $2ae. N001 ( 1, 1) [000244] ----------- * LCL_VAR int V16 loc12 u:4 (last use) $2ae copy propagated to: N001 ( 1, 1) [000244] ----------- * LCL_VAR int V49 tmp9 u:1 (last use) $2ae Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V49 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V49 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V49 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V50 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V50 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V50 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V50 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} VN based copy assertion for [000260] V50 $89a by [000262] V18 $89a. N001 ( 1, 1) [000260] ----------- * LCL_VAR int V50 tmp10 u:1 (last use) copy propagated to: N001 ( 1, 1) [000260] ----------- * LCL_VAR int V18 loc14 u:1 (last use) Copy Assertion for BB247 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [000247]:V16/5 [000008]:V17/1 [001499]:V76/1 [000262]:V18/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [000249]:V49/1 [002550]:V167/1 [000258]:V50/1 [002607]:V168/1 [002789]:V169/1 } Copy Assertion for BB113 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [000247]:V16/5 [000008]:V17/1 [001499]:V76/1 [000262]:V18/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [000249]:V49/1 [002550]:V167/1 [000258]:V50/1 [002607]:V168/1 [002789]:V169/1 } Copy Assertion for BB136 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [000247]:V16/5 [000008]:V17/1 [001499]:V76/1 [000262]:V18/1 [003175]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003199]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [000249]:V49/1 [002550]:V167/1 [000258]:V50/1 [002607]:V168/1 [002789]:V169/1 } Copy Assertion for BB244 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [000247]:V16/5 [000008]:V17/1 [001499]:V76/1 [000262]:V18/1 [003253]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003268]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [000249]:V49/1 [002550]:V167/1 [000258]:V50/1 [002607]:V168/1 [002789]:V169/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB242 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [000247]:V16/5 [000008]:V17/1 [001499]:V76/1 [000262]:V18/1 [003253]:V20/NA [003202]:V21/NA [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003268]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [000249]:V49/1 [002550]:V167/1 [000258]:V50/1 [002607]:V168/1 [002789]:V169/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144} Copy Assertion for BB243 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [000247]:V16/5 [000008]:V17/1 [001499]:V76/1 [000262]:V18/1 [003253]:V20/NA [003202]:V21/NA [002493]:V140/1 [000071]:V22/1 [003298]:V143/NA [003289]:V144/NA [002557]:V147/1 [002560]:V148/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000199]:V34/1 [001557]:V152/1 [003268]:V36/NA [002600]:V157/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [002782]:V165/1 [000249]:V49/1 [002550]:V167/1 [000258]:V50/1 [002607]:V168/1 [002789]:V169/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V141 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V141 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V140 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V140 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB205 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} Copy Assertion for BB227 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144} Copy Assertion for BB230 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Copy Assertion for BB231 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Copy Assertion for BB239 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Copy Assertion for BB240 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003232]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Copy Assertion for BB241 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003232]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Copy Assertion for BB236 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003232]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V53 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V53 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V53 V143 V144} VN based copy assertion for [000393] V16 $b08 by [000398] V53 $b08. N001 ( 1, 1) [000393] ----------- * LCL_VAR int V16 loc12 u:6 (last use) $b08 copy propagated to: N001 ( 1, 1) [000393] ----------- * LCL_VAR int V53 tmp13 u:1 (last use) $b08 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V53 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V53 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V53 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V137 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V137 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144} Copy Assertion for BB238 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [002443]:V136/1 [003358]:V05/NA [002480]:V137/1 [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000396]:V16/7 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000398]:V53/1 [001499]:V76/1 [002350]:V129/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V137 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB237 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [002443]:V136/1 [003358]:V05/NA [002480]:V137/1 [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000396]:V16/7 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000398]:V53/1 [001499]:V76/1 [002350]:V129/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V138 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V138 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB233 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V52 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V52 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V52 V143 V144} VN based copy assertion for [000357] V16 $898 by [000362] V52 $898. N001 ( 1, 1) [000357] ----------- * LCL_VAR int V16 loc12 u:5 (last use) $898 copy propagated to: N001 ( 1, 1) [000357] ----------- * LCL_VAR int V52 tmp12 u:1 (last use) $898 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V52 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V52 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V52 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V133 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V133 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144} Copy Assertion for BB235 curSsaName stack: { [000230]:V00/1 [002397]:V132/1 [000000]:V01/1 [002434]:V133/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000360]:V16/8 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000362]:V52/1 [001499]:V76/1 [002350]:V129/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V133 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB234 curSsaName stack: { [000230]:V00/1 [002397]:V132/1 [000000]:V01/1 [002434]:V133/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000360]:V16/8 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000362]:V52/1 [001499]:V76/1 [002350]:V129/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V134 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V134 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB232 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Copy Assertion for BB229 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB228 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002350]:V129/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V130 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V130 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V129 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V129 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB206 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB219 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V17 V18 V20 V21 V34 V36 V37 V38 V54 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V17 V18 V20 V21 V34 V36 V37 V38 V54 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V54 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V54 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} VN based copy assertion for [000476] V54 $c5c by [000478] V16 $c5c. N001 ( 1, 1) [000476] ----------- * LCL_VAR int V54 tmp14 u:1 (last use) $c5c copy propagated to: N001 ( 1, 1) [000476] ----------- * LCL_VAR int V16 loc12 u:10 (last use) $c5c Copy Assertion for BB221 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000478]:V16/10 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [003226]:V37/NA [002607]:V168/1 [003214]:V38/NA [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000474]:V54/1 [001499]:V76/1 } Copy Assertion for BB223 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000478]:V16/10 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [003226]:V37/NA [002607]:V168/1 [003214]:V38/NA [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000474]:V54/1 [001499]:V76/1 } Copy Assertion for BB226 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000478]:V16/10 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [003226]:V37/NA [002607]:V168/1 [003211]:V38/NA [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000474]:V54/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V38 V55 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V38 V55 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V38 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V38 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V20 V21 V34 V36 V38 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V20 V21 V34 V36 V38 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB225 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000478]:V16/10 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [003226]:V37/NA [002607]:V168/1 [003211]:V38/NA [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000474]:V54/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144} Copy Assertion for BB224 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000478]:V16/10 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [003226]:V37/NA [002607]:V168/1 [003211]:V38/NA [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000474]:V54/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144} Copy Assertion for BB222 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000478]:V16/10 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [003226]:V37/NA [002607]:V168/1 [003214]:V38/NA [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000474]:V54/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} Copy Assertion for BB220 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000478]:V16/10 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [003226]:V37/NA [002607]:V168/1 [003214]:V38/NA [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000474]:V54/1 [001499]:V76/1 } Copy Assertion for BB218 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} Copy Assertion for BB208 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB212 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB215 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144} Copy Assertion for BB217 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002303]:V126/1 } Copy Assertion for BB216 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002303]:V126/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V127 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V127 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V126 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V126 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB213 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB214 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB209 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB210 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB211 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V38 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144} Copy Assertion for BB207 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [000324]:V37/1 [002607]:V168/1 [000327]:V38/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB141 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB200 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB201 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB202 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V51 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V51 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V51 V143 V144} VN based copy assertion for [000304] V16 $898 by [000309] V51 $898. N001 ( 1, 1) [000304] ----------- * LCL_VAR int V16 loc12 u:5 (last use) $898 copy propagated to: N001 ( 1, 1) [000304] ----------- * LCL_VAR int V51 tmp11 u:1 (last use) $898 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V51 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V51 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V51 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V123 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V123 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144} Copy Assertion for BB204 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000307]:V16/12 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000309]:V51/1 [001499]:V76/1 [002245]:V122/1 [002282]:V123/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V123 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB203 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000307]:V16/12 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000309]:V51/1 [001499]:V76/1 [002245]:V122/1 [002282]:V123/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V124 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V124 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB142 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB143 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB144 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144} Copy Assertion for BB181 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002118]:V110/1 } Copy Assertion for BB182 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002118]:V110/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144} Copy Assertion for BB185 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002118]:V110/1 [002073]:V111/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB183 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002118]:V110/1 [002073]:V111/1 } Copy Assertion for BB184 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002118]:V110/1 [002073]:V111/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V112 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V112 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V111 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V111 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB137 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB194 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB197 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003166]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB198 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003166]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB199 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003166]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB195 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003166]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB196 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003166]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB191 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [003166]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V59 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V59 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V18 V20 V21 V34 V36 V59 V143 V144} VN based copy assertion for [000806] V16 $b04 by [000811] V59 $b04. N001 ( 1, 1) [000806] ----------- * LCL_VAR int V16 loc12 u:13 (last use) $b04 copy propagated to: N001 ( 1, 1) [000806] ----------- * LCL_VAR int V59 tmp19 u:1 (last use) $b04 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V18 V20 V21 V34 V36 V59 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V59 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V59 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V119 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V119 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144} Copy Assertion for BB193 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000809]:V16/15 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000811]:V59/1 [001499]:V76/1 [002187]:V118/1 [002224]:V119/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V119 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB192 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000809]:V16/15 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000811]:V59/1 [001499]:V76/1 [002187]:V118/1 [002224]:V119/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V120 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V120 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB186 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144} Copy Assertion for BB187 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002178]:V114/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144} Copy Assertion for BB190 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002178]:V114/1 [002133]:V115/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB188 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002178]:V114/1 [002133]:V115/1 } Copy Assertion for BB189 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002178]:V114/1 [002133]:V115/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V116 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V116 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V115 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V115 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB145 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB156 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB170 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB157 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144} Copy Assertion for BB160 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 } Copy Assertion for BB161 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 } Copy Assertion for BB162 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 } Copy Assertion for BB163 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 } Copy Assertion for BB164 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144} Copy Assertion for BB169 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 [001998]:V102/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB165 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 [001998]:V102/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144} Copy Assertion for BB168 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 [001998]:V102/1 [001953]:V103/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB166 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 [001998]:V102/1 [001953]:V103/1 } Copy Assertion for BB167 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 [001998]:V102/1 [001953]:V103/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V104 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V104 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V103 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V103 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB159 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB158 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003184]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003178]:V18/NA [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003196]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [001904]:V99/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V100 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V100 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V99 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V99 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB150 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB155 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB154 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V56 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V56 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V56 V143 V144} VN based copy assertion for [000649] V36 $901 by [000655] V56 $901. N001 ( 1, 1) [000649] ----------- * LCL_VAR long V36 loc32 u:3 (last use) $901 copy propagated to: N001 ( 1, 1) [000649] ----------- * LCL_VAR long V56 tmp16 u:1 (last use) $901 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V56 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V56 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V56 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144} Copy Assertion for BB151 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB153 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144} Copy Assertion for BB152 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144} Copy Assertion for BB146 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB149 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [000734]:V14/5 [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB148 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [000734]:V14/5 [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144} Copy Assertion for BB147 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [000734]:V14/5 [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144} Copy Assertion for BB138 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB171 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB172 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB175 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144} Copy Assertion for BB180 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002058]:V106/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144} Copy Assertion for BB176 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002058]:V106/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144} Copy Assertion for BB179 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002058]:V106/1 [002013]:V107/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144} Copy Assertion for BB177 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002058]:V106/1 [002013]:V107/1 } Copy Assertion for BB178 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 [002058]:V106/1 [002013]:V107/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V108 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V108 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V107 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V107 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144} Copy Assertion for BB173 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB174 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB139 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB140 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003238]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003244]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003253]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003268]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB114 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003175]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003199]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB135 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003175]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003199]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB118 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003265]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V60 V143 V144} Copy Assertion for BB121 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003265]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V63 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V92 V143 V144} VN based copy assertion for [000857] V62 $100 by [000230] V00 $100. N001 ( 1, 1) [000857] ----------- * LCL_VAR byref V62 tmp22 u:1 $100 copy propagated to: N001 ( 1, 1) [000857] ----------- * LCL_VAR byref V00 arg0 u:1 $100 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V92 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V91 V92 V143 V144} VN based copy assertion for [001801] V62 $100 by [000230] V00 $100. N002 ( 1, 1) [001801] ----------- * LCL_VAR byref V62 tmp22 u:1 $100 copy propagated to: N002 ( 1, 1) [001801] ----------- * LCL_VAR byref V00 arg0 u:1 $100 Copy Assertion for BB124 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 } Copy Assertion for BB134 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB125 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 } Copy Assertion for BB126 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 } Copy Assertion for BB127 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 } Copy Assertion for BB128 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144} Copy Assertion for BB133 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 [001895]:V95/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V21 V34 V36 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB129 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 [001895]:V95/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144} Copy Assertion for BB132 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 [001895]:V95/1 [001850]:V96/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB130 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 [001895]:V95/1 [001850]:V96/1 } Copy Assertion for BB131 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 [001895]:V95/1 [001850]:V96/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V97 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V97 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V96 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V96 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB123 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V92 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V92 V143 V144} VN based copy assertion for [001807] V62 $100 by [000230] V00 $100. N001 ( 1, 1) [001807] ----------- * LCL_VAR byref V62 tmp22 u:1 (last use) $100 copy propagated to: N001 ( 1, 1) [001807] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V92 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} Copy Assertion for BB122 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003262]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [003256]:V62/NA [003259]:V63/NA [001499]:V76/1 [001798]:V91/1 [001835]:V92/1 } VN based copy assertion for [002803] V62 $100 by [000230] V00 $100. N001 ( 1, 1) [002803] -----O----- * LCL_VAR byref V62 tmp22 u:1 $100 copy propagated to: N001 ( 1, 1) [002803] -----O----- * LCL_VAR byref V00 arg0 u:1 $100 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V91 V92 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V91 V92 V93 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V91 V92 V93 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V91 V92 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V91 V92 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V91 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V91 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} VN based copy assertion for [001829] V62 $100 by [000230] V00 $100. N004 ( 1, 1) [001829] ----------- * LCL_VAR byref V62 tmp22 u:1 (last use) $100 copy propagated to: N004 ( 1, 1) [001829] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 Copy Assertion for BB120 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003265]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V60 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V60 V61 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V60 V61 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V60 V61 V143 V144} VN based copy assertion for [000841] V36 $904 by [000847] V61 $904. N001 ( 1, 1) [000841] ----------- * LCL_VAR long V36 loc32 u:7 (last use) $904 copy propagated to: N001 ( 1, 1) [000841] ----------- * LCL_VAR long V61 tmp21 u:1 (last use) $904 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V60 V61 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V60 V61 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V60 V61 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V61 V143 V144} VN based copy assertion for [000839] V60 $100 by [000230] V00 $100. N001 ( 1, 1) [000839] ----------- * LCL_VAR byref V60 tmp20 u:1 (last use) $100 copy propagated to: N001 ( 1, 1) [000839] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V61 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V61 V62 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V61 V62 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V63 V143 V144} Copy Assertion for BB119 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003235]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003241]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003250]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003265]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [000835]:V60/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V60 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} VN based copy assertion for [000838] V60 $100 by [000230] V00 $100. N001 ( 1, 1) [000838] ----------- * LCL_VAR byref V60 tmp20 u:1 (last use) $100 copy propagated to: N001 ( 1, 1) [000838] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V62 V63 V143 V144} Copy Assertion for BB115 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003175]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003199]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB116 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003175]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003199]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB117 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003169]:V08/NA [003205]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003187]:V14/NA [003160]:V15/NA [002557]:V147/1 [000247]:V16/5 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [000262]:V18/1 [003412]:V150/NA [001552]:V151/1 [003175]:V20/NA [001557]:V152/1 [003202]:V21/NA [000071]:V22/1 [002600]:V157/1 [002782]:V165/1 [000199]:V34/1 [002550]:V167/1 [003199]:V36/NA [002607]:V168/1 [002789]:V169/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000249]:V49/1 [000258]:V50/1 [001499]:V76/1 } Copy Assertion for BB104 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [003316]:V20/NA [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } VN based copy assertion for [000927] V15 $283 by [000156] V16 $283. N001 ( 1, 1) [000927] ----------- * LCL_VAR int V15 loc11 u:2 $283 copy propagated to: N001 ( 1, 1) [000927] ----------- * LCL_VAR int V16 loc12 u:3 $283 Copy Assertion for BB105 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [003316]:V20/NA [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Copy Assertion for BB106 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [003316]:V20/NA [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144} Copy Assertion for BB107 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [003316]:V20/NA [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 [001782]:V86/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144} Copy Assertion for BB111 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [003316]:V20/NA [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 [001782]:V86/1 [001737]:V87/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144} Copy Assertion for BB108 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [003316]:V20/NA [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 [001782]:V86/1 [001737]:V87/1 } Copy Assertion for BB109 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003298]:V143/NA [003355]:V12/NA [003289]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [003316]:V20/NA [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 [001782]:V86/1 [001737]:V87/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V88 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V88 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V87 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V87 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144} Copy Assertion for BB79 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Copy Assertion for BB80 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144} Copy Assertion for BB82 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [000956]:V28/1 [000960]:V29/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144} Copy Assertion for BB85 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [003331]:V28/NA [000960]:V29/1 [000967]:V30/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V66 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V66 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V31 V143 V144} Copy Assertion for BB88 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [003331]:V28/NA [000960]:V29/1 [000967]:V30/1 [000989]:V31/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V67 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144} VN based copy assertion for [003159] V28 $298 by [000967] V30 $298. N002 ( 1, 1) [003159] ----------- * LCL_VAR int V28 loc24 u:2 $298 copy propagated to: N002 ( 1, 1) [003159] ----------- * LCL_VAR int V30 loc26 u:1 $298 Copy Assertion for BB89 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [003331]:V28/NA [000960]:V29/1 [000967]:V30/1 [000989]:V31/1 [001000]:V32/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Copy Assertion for BB90 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [003319]:V20/NA [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003271]:V28/NA [000960]:V29/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V26 V27 V28 V29 V30 V32 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V26 V27 V28 V29 V30 V32 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144} Copy Assertion for BB100 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003271]:V28/NA [000960]:V29/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Copy Assertion for BB102 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003295]:V143/NA [003355]:V12/NA [003286]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003271]:V28/NA [000960]:V29/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V29 V30 V32 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V29 V30 V32 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144} Copy Assertion for BB101 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003295]:V143/NA [003355]:V12/NA [003286]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003271]:V28/NA [000960]:V29/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V32 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V28 V29 V32 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V28 V29 V32 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V32 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V32 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144} Copy Assertion for BB91 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003271]:V28/NA [000960]:V29/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144} Copy Assertion for BB94 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003271]:V28/NA [000960]:V29/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159 V160} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V160} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V160} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V160 V161} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V160 V161} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V161} Copy Assertion for BB110 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003313]:V159/NA [003271]:V28/NA [003310]:V160/NA [000960]:V29/1 [002693]:V161/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Copy Assertion for BB95 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003313]:V159/NA [003271]:V28/NA [003310]:V160/NA [000960]:V29/1 [002693]:V161/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Copy Assertion for BB96 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003313]:V159/NA [003271]:V28/NA [003310]:V160/NA [000960]:V29/1 [002693]:V161/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V161} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V161} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V161} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V83 V143 V161} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V83 V143 V161} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V161} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V161} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33} Copy Assertion for BB99 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003313]:V159/NA [003271]:V28/NA [003310]:V160/NA [000960]:V29/1 [002693]:V161/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 [001672]:V83/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V163 V164} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V164} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V164} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V164} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V164} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144} Copy Assertion for BB98 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003313]:V159/NA [003271]:V28/NA [003310]:V160/NA [000960]:V29/1 [002693]:V161/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 [001672]:V83/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V163} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V163} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V163} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V163} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V163 V164} Copy Assertion for BB97 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003313]:V159/NA [003271]:V28/NA [003310]:V160/NA [000960]:V29/1 [002693]:V161/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 [001672]:V83/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V163} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V163} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V163 V164} Copy Assertion for BB93 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003271]:V28/NA [000960]:V29/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159 V160} Copy Assertion for BB92 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003301]:V143/NA [003355]:V12/NA [003292]:V144/NA [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [001013]:V20/11 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [003277]:V27/NA [003271]:V28/NA [000960]:V29/1 [003283]:V30/NA [000989]:V31/1 [001000]:V32/1 [001069]:V33/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [003322]:V67/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V159 V160} Copy Assertion for BB87 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [003331]:V28/NA [000960]:V29/1 [000967]:V30/1 [000989]:V31/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V67 V143 V144} Copy Assertion for BB86 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [003331]:V28/NA [000960]:V29/1 [000967]:V30/1 [000989]:V31/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [003325]:V65/NA [003328]:V66/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V31 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V67 V143 V144} Copy Assertion for BB84 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [003331]:V28/NA [000960]:V29/1 [000967]:V30/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144} Copy Assertion for BB83 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [003331]:V28/NA [000960]:V29/1 [000967]:V30/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [000974]:V64/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V143 V144} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144} Copy Assertion for BB81 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003334]:V08/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [002648]:V143/1 [003355]:V12/NA [002651]:V144/1 [003352]:V13/NA [003337]:V14/NA [003160]:V15/NA [002557]:V147/1 [000156]:V16/3 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [001552]:V151/1 [000176]:V20/1 [001557]:V152/1 [000071]:V22/1 [000950]:V26/1 [002600]:V157/1 [000953]:V27/1 [000956]:V28/1 [000960]:V29/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V29 V143 V144} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144} Copy Assertion for BB74 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Copy Assertion for BB77 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17 V46} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17} Copy Assertion for BB76 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17 V46} Copy Assertion for BB75 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17 V46} Copy Assertion for BB73 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [000130]:V07/3 [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [003343]:V45/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17} Copy Assertion for BB71 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V09 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V09 V12 V15 V17 V45} Copy Assertion for BB70 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [000117]:V06/3 [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [003346]:V44/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V09 V12 V15 V17 V45} Copy Assertion for BB68 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V07 V09 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V07 V09 V12 V15 V17 V44} Copy Assertion for BB67 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V07 V09 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V07 V09 V12 V15 V17 V44} Copy Assertion for BB63 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Copy Assertion for BB65 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Copy Assertion for BB64 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Copy Assertion for BB57 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V69} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V69} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V69} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V69} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17} Copy Assertion for BB60 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001128]:V69/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17} Copy Assertion for BB61 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001128]:V69/1 [003349]:V70/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V16 V17} Copy Assertion for BB62 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [001162]:V16/16 [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001128]:V69/1 [003349]:V70/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V11 V16 V17} => {V00 V01 V02 V03 V11 V17} Live vars: {V00 V01 V02 V03 V11 V17} => {V00 V01 V02 V03 V11 V15 V17} Copy Assertion for BB59 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001128]:V69/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70} Copy Assertion for BB58 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003355]:V12/NA [003352]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001128]:V69/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70} Copy Assertion for BB53 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17} Copy Assertion for BB55 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V13 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17} Copy Assertion for BB54 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003358]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17} Copy Assertion for BB51 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V06 V07 V09 V10 V11 V12 V13 V15 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17} Copy Assertion for BB48 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [003364]:V16/NA [002560]:V148/1 [000008]:V17/1 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V71} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V71} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V22 V71} VN based copy assertion for [001199] V16 $28b by [001204] V71 $28b. N001 ( 1, 1) [001199] ----------- * LCL_VAR int V16 loc12 u:2 (last use) $28b copy propagated to: N001 ( 1, 1) [001199] ----------- * LCL_VAR int V71 tmp31 u:1 (last use) $28b Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V22 V71} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V71} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V71} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V72} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V72} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V72} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V72} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22} VN based copy assertion for [001215] V72 $363 by [001217] V18 $363. N001 ( 1, 1) [001215] ----------- * LCL_VAR int V72 tmp32 u:1 (last use) copy propagated to: N001 ( 1, 1) [001215] ----------- * LCL_VAR int V18 loc14 u:5 (last use) Copy Assertion for BB49 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB08 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB38 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB44 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V17 V22} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V17 V22 V73} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V17 V22 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V73} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22} VN based copy assertion for [001306] V73 $942 by [001308] V16 $942. N001 ( 1, 1) [001306] ----------- * LCL_VAR int V73 tmp33 u:1 (last use) $942 copy propagated to: N001 ( 1, 1) [001306] ----------- * LCL_VAR int V16 loc12 u:19 (last use) $942 Copy Assertion for BB46 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001308]:V16/19 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001304]:V73/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB45 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001308]:V16/19 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001304]:V73/1 [001499]:V76/1 } Copy Assertion for BB40 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB41 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB43 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB42 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB39 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB13 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB35 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB36 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB37 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V22} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB14 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB15 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB16 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V16 V17 V22} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB09 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB31 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB32 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [003361]:V16/NA [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB33 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [003361]:V16/NA [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V74} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V74} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V18 V22 V74} VN based copy assertion for [001455] V16 $2b1 by [001460] V74 $2b1. N001 ( 1, 1) [001455] ----------- * LCL_VAR int V16 loc12 u:21 (last use) $2b1 copy propagated to: N001 ( 1, 1) [001455] ----------- * LCL_VAR int V74 tmp34 u:1 (last use) $2b1 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V18 V22 V74} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V74} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V74} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22} Copy Assertion for BB34 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001458]:V16/22 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001460]:V74/1 [001499]:V76/1 } Copy Assertion for BB30 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V16 V17 V22} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB17 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Live vars: {V00 V01 V02 V03 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB10 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB23 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB24 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB25 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB29 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V12 V13 V15 V16 V17 V22} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB26 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB28 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22} Copy Assertion for BB27 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V12 V13 V15 V16 V17 V22} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB21 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB22 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB18 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB20 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22} Live vars: {V00 V01 V02 V03 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22} Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB19 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V09 V10 V11 V12 V13 V15 V16 V17 V22} => {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB11 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22} Copy Assertion for BB12 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [003367]:V04/NA [003388]:V05/NA [003397]:V06/NA [003391]:V07/NA [003400]:V09/NA [003379]:V10/NA [003373]:V11/NA [003385]:V12/NA [003370]:V13/NA [003160]:V15/NA [002557]:V147/1 [001202]:V16/17 [002560]:V148/1 [000008]:V17/1 [001217]:V18/5 [003406]:V149/NA [003412]:V150/NA [000071]:V22/1 [002600]:V157/1 [002550]:V167/1 [002607]:V168/1 [003409]:V43/NA [001204]:V71/1 [001213]:V72/1 [001499]:V76/1 } Copy Assertion for BB05 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [000003]:V11/1 [002557]:V147/1 [002560]:V148/1 [000008]:V17/1 [002550]:V167/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V11 V17 V147 V148} => {V00 V01 V02 V03 V11 V17 V148} Live vars: {V00 V01 V02 V03 V11 V17 V148} => {V00 V01 V02 V03 V11 V17 V148 V149} Live vars: {V00 V01 V02 V03 V11 V17 V148 V149} => {V00 V01 V02 V03 V11 V17 V149} Live vars: {V00 V01 V02 V03 V11 V17 V149} => {V00 V01 V02 V03 V11 V17 V149 V150} Live vars: {V00 V01 V02 V03 V11 V17 V149 V150} => {V00 V01 V02 V03 V11 V17 V43 V149 V150} Copy Assertion for BB02 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [000003]:V11/1 [002557]:V147/1 [002560]:V148/1 [000008]:V17/1 [002550]:V167/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V11 V17 V147 V148} => {V00 V01 V02 V03 V11 V17 V148} Live vars: {V00 V01 V02 V03 V11 V17 V148} => {V00 V01 V02 V03 V11 V17 V148 V155} Live vars: {V00 V01 V02 V03 V11 V17 V148 V155} => {V00 V01 V02 V03 V11 V17 V155} Live vars: {V00 V01 V02 V03 V11 V17 V155} => {V00 V01 V02 V03 V11 V17 V155 V156} Copy Assertion for BB04 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [000003]:V11/1 [002557]:V147/1 [002560]:V148/1 [000008]:V17/1 [002564]:V155/1 [002567]:V156/1 [002550]:V167/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V11 V17 V155 V156} => {V00 V01 V02 V03 V11 V17 V156} Live vars: {V00 V01 V02 V03 V11 V17 V156} => {V00 V01 V02 V03 V11 V17 V149 V156} Live vars: {V00 V01 V02 V03 V11 V17 V149 V156} => {V00 V01 V02 V03 V11 V17 V149} Live vars: {V00 V01 V02 V03 V11 V17 V149} => {V00 V01 V02 V03 V11 V17 V149 V150} Live vars: {V00 V01 V02 V03 V11 V17 V149 V150} => {V00 V01 V02 V03 V11 V17 V43 V149 V150} Copy Assertion for BB03 curSsaName stack: { [000230]:V00/1 [000000]:V01/1 [002558]:V02/1 [000238]:V03/1 [000003]:V11/1 [002557]:V147/1 [002560]:V148/1 [000008]:V17/1 [002564]:V155/1 [002567]:V156/1 [002550]:V167/1 [001499]:V76/1 } Live vars: {V00 V01 V02 V03 V11 V17 V155 V156} => {V00 V01 V02 V03 V11 V17 V156} Live vars: {V00 V01 V02 V03 V11 V17 V156} => {V00 V01 V02 V03 V11 V17 V149 V156} Live vars: {V00 V01 V02 V03 V11 V17 V149 V156} => {V00 V01 V02 V03 V11 V17 V149} Live vars: {V00 V01 V02 V03 V11 V17 V149} => {V00 V01 V02 V03 V11 V17 V149 V150} Live vars: {V00 V01 V02 V03 V11 V17 V149 V150} => {V00 V01 V02 V03 V11 V17 V43 V149 V150} *************** Finishing PHASE VN based copy prop Trees after VN based copy prop ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N007 ( 14, 14) [002563] -A--------- * COMMA void $VN.Void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N006 ( 7, 7) [002562] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 3, 4) [002606] -A--------- * COMMA void $580 N003 ( 3, 4) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 3, 4) [003623] ----------- * COMMA void N001 ( 3, 4) [003621] -------H--- +--* LCL_FLD int V02 arg2 u:1[+8] $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 7, 8) [001441] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N010 ( 13, 15) [001452] ---XG------ * JTRUE void $876 N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N010 ( 13, 14) [001471] ---XG------ * JTRUE void $876 N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001466] ----------- | \--* LSH long $3df N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 7, 8) [001240] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N010 ( 13, 15) [001251] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 7, 8) [001267] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N010 ( 13, 15) [001351] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 9, 11) [001276] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N010 ( 13, 15) [001287] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N010 ( 13, 15) [001340] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001335] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 7, 8) [001315] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 7, 8) [000079] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] D--XG--N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool $301 N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int $301 N004 ( 4, 3) [000104] D--XG--N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N007 ( 8, 7) [000140] ---XG------ * JTRUE void $301 N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int $301 N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref $24a N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 $207 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [373..39A) -> BB93 (cond), preds={BB90} succs={BB92,BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ***** BB91 STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 5, 6) [001590] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001589] J------N--- \--* NE int $c1 N001 ( 1, 1) [001073] ----------- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [001588] ----------- \--* CNS_INT ref null $VN.Null ------------ BB92 [383..384) -> BB94 (always), preds={BB91} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (cond), preds={BB95} succs={BB97,BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ***** BB96 STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 5, 6) [001702] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001701] J------N--- \--* NE int $c1 N001 ( 1, 1) [001082] ----------- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [001700] ----------- \--* CNS_INT ref null $VN.Null ------------ BB97 [391..392) -> BB99 (always), preds={BB96} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void $845 N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001780] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 3, 4) [002788] -A--------- * COMMA void $588 N003 ( 3, 4) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N005 ( 8, 8) [000834] ---XG------ * JTRUE void $c1a N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 $904 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int $c1a N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) $904 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001833] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001893] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001938] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001996] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002056] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002116] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002176] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort $bec N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long $acc N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000817] ----------- \--* LSH long $acb N003 ( 2, 3) [000814] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 $204 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002222] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 7, 8) [000757] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB195 [5D9..5E4) -> BB197 (cond), preds={BB194} succs={BB196,BB197} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N010 ( 13, 15) [000791] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N010 ( 13, 14) [000802] ---XG------ * JTRUE void $bec N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000797] ----------- | \--* LSH long $acb N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB195,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 7, 8) [000764] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N010 ( 13, 15) [000775] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 7, 8) [000289] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N010 ( 13, 15) [000300] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000315] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002280] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 7, 8) [000425] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N010 ( 13, 15) [000575] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 9, 11) [000434] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB209 [687..694) -> BB212 (cond), preds={BB208} succs={BB210,BB212} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N010 ( 13, 15) [000548] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB212 (cond), preds={BB209} succs={BB211,BB212} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB212 [6A8..6B5) -> BB215 (cond), preds={BB208,BB209,BB210} succs={BB213,BB215} ***** BB212 STMT00102 ( 0x6A8[E-] ... ??? ) N006 ( 9, 11) [000443] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000442] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000437] ----------- +--* ADD int $952 N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB212} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N010 ( 13, 15) [000457] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000452] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002337] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 7, 8) [000485] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002384] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 7, 8) [000342] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N010 ( 13, 15) [000353] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N010 ( 13, 15) [000418] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000413] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000368] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000365] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 $204 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002432] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort $c02 N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000404] ----------- \--* LSH long $ad2 N003 ( 2, 3) [000401] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 $204 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002478] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 7, 8) [000378] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N010 ( 13, 15) [000389] ---XG------ * JTRUE void $c02 N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002527] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 7, 8) [000210] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [info] NumUses overestimated for V00.1: IR 80 SSA 108 [info] NumUses overestimated for V01.1: IR 17 SSA 21 [info] NumUses overestimated for V15.2: IR 4 SSA 5 [info] NumUses overestimated for V16.2: IR 2 SSA 3 [info] NumUses overestimated for V16.4: IR 2 SSA 3 [info] NumUses overestimated for V16.5: IR 20 SSA 22 [info] NumUses overestimated for V16.6: IR 4 SSA 5 [info] NumUses overestimated for V16.13: IR 8 SSA 9 [info] NumUses overestimated for V16.21: IR 4 SSA 5 [info] NumUses overestimated for V28.2: IR 2 SSA 3 [info] NumUses overestimated for V33.1: IR 6 SSA 10 [info] NumUses overestimated for V36.3: IR 6 SSA 7 [info] NumUses overestimated for V36.7: IR 4 SSA 5 [info] NumUses overestimated for V50.1: IR 1 SSA 2 [info] NumUses overestimated for V54.1: IR 1 SSA 2 [info] NumUses overestimated for V60.1: IR 0 SSA 2 [info] HasGlobalUse overestimated for V60.1 [info] NumUses overestimated for V62.1: IR 0 SSA 7 [info] HasGlobalUse overestimated for V62.1 [info] NumUses overestimated for V72.1: IR 1 SSA 2 [info] NumUses overestimated for V73.1: IR 1 SSA 2 [info] NumUses overestimated for V167.1: IR 1 SSA 2 SSA checks completed successfully *************** In fgDebugCheckLoopTable *************** Starting PHASE Redundant branch opts ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 ( cond ) i hascall bwd BB92 [0219] 1 BB91 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 ( cond ) i gcsafe bwd BB97 [0242] 1 BB96 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB197 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 3 BB194,BB195,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 1 BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB212 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB212 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 3 BB208,BB209,BB210 2 3 [6A8..6B5)-> BB215 ( cond ) i bwd BB213 [0169] 1 BB212 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- --- Trying RBO in BB251 --- Relop [000234] BB251 value unknown, trying inference BB251 has side effects; no threading --- Trying RBO in BB250 --- Relop [000228] BB250 value unknown, trying inference BB250 has side effects; no threading --- Trying RBO in BB249 --- Relop [000223] BB249 value unknown, trying inference ... JT-PHI [interestingVN] in BB249 relop first operand VN is PhiDef for V15:2 $34d N003 ( 3, 4) [000223] J------N--- * NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs optRedundantRelop in BB248; jump tree is N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 -- prev tree defs untracked V35 --- Trying RBO in BB248 --- Relop [000218] BB248 value unknown, trying inference BB248 has side effects; no threading optRedundantRelop in BB242; jump tree is N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB242 --- Relop [002500] BB242 value unknown, trying inference BB242 has side effects; no threading optRedundantRelop in BB236; jump tree is N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related ... checking previous tree N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort $c02 N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000404] ----------- \--* LSH long $ad2 N003 ( 2, 3) [000401] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 $204 -- prev tree VN is not related ... checking previous tree N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 -- prev tree VN is not related --- Trying RBO in BB236 --- Relop [002450] BB236 value unknown, trying inference BB236 has side effects; no threading --- Trying RBO in BB240 --- Relop [000388] BB240 value unknown, trying inference BB240 has side effects; no threading optRedundantRelop in BB239; jump tree is N004 ( 7, 8) [000378] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ... checking previous tree N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 -- prev tree is a phi --- Trying RBO in BB239 --- Relop [000377] BB239 value unknown, trying inference BB239 has global phi for V16.6; no phi-based threading optRedundantRelop in BB233; jump tree is N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related ... checking previous tree N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000368] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000365] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 $204 -- prev tree VN is not related ... checking previous tree N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 -- prev tree VN is not related --- Trying RBO in BB233 --- Relop [002404] BB233 value unknown, trying inference BB233 has side effects; no threading --- Trying RBO in BB232 --- Relop [000417] BB232 value unknown, trying inference BB232 has side effects; no threading --- Trying RBO in BB231 --- Relop [000352] BB231 value unknown, trying inference BB231 has side effects; no threading --- Trying RBO in BB230 --- Relop [000341] BB230 value unknown, trying inference No usable PhiDef VNs optRedundantRelop in BB227; jump tree is N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB227 --- Relop [002357] BB227 value unknown, trying inference BB227 has side effects; no threading optRedundantRelop in BB223; jump tree is N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f -- prev tree is a phi --- Trying RBO in BB223 --- Relop [000493] BB223 value unknown, trying inference BB223 has global phi for V38.3; no phi-based threading --- Trying RBO in BB221 --- Relop [000488] BB221 value unknown, trying inference ... JT-PHI [interestingVN] in BB221 relop first operand VN is PhiDef for V38:2 $c5b N003 ( 3, 4) [000488] J------N--- * LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 No usable PhiDef VNs --- Trying RBO in BB220 --- Relop [000531] BB220 value unknown, trying inference BB220 has side effects; no threading optRedundantRelop in BB219; jump tree is N004 ( 7, 8) [000485] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ... checking previous tree N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c -- prev tree VN is not related ... checking previous tree N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 -- prev tree is a phi --- Trying RBO in BB219 --- Relop [000484] BB219 value unknown, trying inference BB219 has global phi for V37.2; no phi-based threading optRedundantRelop in BB215; jump tree is N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB215 --- Relop [002310] BB215 value unknown, trying inference BB215 has side effects; no threading --- Trying RBO in BB214 --- Relop [000469] BB214 value unknown, trying inference BB214 has side effects; no threading --- Trying RBO in BB213 --- Relop [000456] BB213 value unknown, trying inference BB213 has side effects; no threading --- Trying RBO in BB212 --- Relop [000442] BB212 value unknown, trying inference Dominator BB208 of BB212 has relop with same liberal VN N005 ( 7, 9) [000433] J------N--- * GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 Redundant compare; current relop: N005 ( 7, 9) [000442] J------N--- * GE int $9e2 N003 ( 3, 4) [000437] ----------- +--* ADD int $952 N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 Both successors of idom BB208 reach BB212 -- attempting jump threading BB208 is an ambiguous pred BB209 is a false pred BB210 is a false pred Optimizing via jump threading Jump flow from pred BB209 -> BB212 implies predicate false; we can safely redirect flow to be BB209 -> BB213 Setting edge weights for BB209 -> BB213 to [0 .. 3.402823e+38] Jump flow from pred BB210 -> BB212 implies predicate false; we can safely redirect flow to be BB210 -> BB213 Setting edge weights for BB210 -> BB213 to [0 .. 3.402823e+38] Will retry RBO in BB212 after partial optimization --- Trying RBO in BB212 --- Relop [000442] BB212 value unknown, trying inference Dominator BB208 of BB212 has relop with same liberal VN N005 ( 7, 9) [000433] J------N--- * GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 Redundant compare; current relop: N005 ( 7, 9) [000442] J------N--- * GE int $9e2 N003 ( 3, 4) [000437] ----------- +--* ADD int $952 N001 ( 1, 1) [000435] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000436] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002300] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 Jump successor BB212 of BB208 reaches, relop [000442] must be true Redundant branch opt in BB212: removing useless STMT00102 ( 0x6A8[E-] ... ??? ) N006 ( 9, 11) [000443] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000442] ----------- \--* CNS_INT int 1 from BB212 BB212 becomes empty Conditional folded at BB212 BB212 becomes a BBJ_ALWAYS to BB215 optRedundantBranch removed tree: N006 ( 9, 11) [000443] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000442] ----------- \--* CNS_INT int 1 --- Trying RBO in BB210 --- Relop [000560] BB210 value unknown, trying inference BB210 has side effects; no threading --- Trying RBO in BB209 --- Relop [000547] BB209 value unknown, trying inference BB209 has side effects; no threading --- Trying RBO in BB208 --- Relop [000433] BB208 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB207 --- Relop [000574] BB207 value unknown, trying inference BB207 has side effects; no threading --- Trying RBO in BB206 --- Relop [000424] BB206 value unknown, trying inference No usable PhiDef VNs optRedundantRelop in BB205; jump tree is N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 -- prev tree VN is not related --- Trying RBO in BB205 --- Relop [000331] BB205 value unknown, trying inference BB205 has side effects; no threading optRedundantRelop in BB202; jump tree is N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related ... checking previous tree N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000315] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 -- prev tree VN is not related ... checking previous tree N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 -- prev tree VN is not related --- Trying RBO in BB202 --- Relop [002252] BB202 value unknown, trying inference BB202 has side effects; no threading --- Trying RBO in BB201 --- Relop [000299] BB201 value unknown, trying inference BB201 has side effects; no threading --- Trying RBO in BB200 --- Relop [000288] BB200 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB183 --- Relop [002088] BB183 value unknown, trying inference BB183 has side effects; no threading optRedundantRelop in BB182; jump tree is N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ... checking previous tree N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB182 --- Relop [002078] BB182 value unknown, trying inference BB182 has side effects; no threading --- Trying RBO in BB181 --- Relop [002070] BB181 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB143 --- Relop [000583] BB143 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB142 --- Relop [000321] BB142 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB141 --- Relop [000281] BB141 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB198 --- Relop [000774] BB198 value unknown, trying inference BB198 has side effects; no threading --- Trying RBO in BB197 --- Relop [000763] BB197 value unknown, trying inference Dominator BB194 of BB197 has relop with same liberal VN N003 ( 5, 6) [000756] J------N--- * GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 Redundant compare; current relop: N003 ( 5, 6) [000763] J------N--- * GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 Both successors of idom BB194 reach BB197 -- attempting jump threading BB194 is an ambiguous pred BB195 is a false pred BB196 is a false pred BB196 is the fall-through pred BB197 has both ambiguous preds and a fall through pred Treating fall through pred BB196 as an ambiguous pred Optimizing via jump threading Jump flow from pred BB195 -> BB197 implies predicate false; we can safely redirect flow to be BB195 -> BB198 Setting edge weights for BB195 -> BB198 to [0 .. 3.402823e+38] Will retry RBO in BB197 after partial optimization --- Trying RBO in BB197 --- Relop [000763] BB197 value unknown, trying inference Dominator BB194 of BB197 has relop with same liberal VN N003 ( 5, 6) [000756] J------N--- * GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 Redundant compare; current relop: N003 ( 5, 6) [000763] J------N--- * GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 Both successors of idom BB194 reach BB197 -- attempting jump threading BB194 is an ambiguous pred BB196 is a false pred BB196 is the fall-through pred BB197 has both ambiguous preds and a fall through pred Treating fall through pred BB196 as an ambiguous pred BB197 now only has ambiguous preds, not jump threading ... JT-PHI [interestingVN] in BB197 relop first operand VN is PhiDef for V16:13 $ba3 N003 ( 5, 6) [000763] J------N--- * GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 No usable PhiDef VNs optRedundantRelop in BB191; jump tree is N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related ... checking previous tree N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort $bec N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long $acc N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000817] ----------- \--* LSH long $acb N003 ( 2, 3) [000814] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 $204 -- prev tree VN is not related ... checking previous tree N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 -- prev tree VN is not related --- Trying RBO in BB191 --- Relop [002194] BB191 value unknown, trying inference BB191 has side effects; no threading --- Trying RBO in BB196 --- Relop [000801] BB196 value unknown, trying inference BB196 has side effects; no threading --- Trying RBO in BB195 --- Relop [000790] BB195 value unknown, trying inference BB195 has side effects; no threading optRedundantRelop in BB194; jump tree is N004 ( 7, 8) [000757] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ... checking previous tree N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 -- prev tree is a phi --- Trying RBO in BB194 --- Relop [000756] BB194 value unknown, trying inference BB194 has global phi for V16.13; no phi-based threading --- Trying RBO in BB188 --- Relop [002148] BB188 value unknown, trying inference BB188 has side effects; no threading optRedundantRelop in BB187; jump tree is N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ... checking previous tree N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB187 --- Relop [002138] BB187 value unknown, trying inference BB187 has side effects; no threading optRedundantRelop in BB186; jump tree is N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ... checking previous tree N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 -- prev tree VN is not related --- Trying RBO in BB186 --- Relop [002130] BB186 value unknown, trying inference BB186 has side effects; no threading --- Trying RBO in BB166 --- Relop [001968] BB166 value unknown, trying inference BB166 has side effects; no threading optRedundantRelop in BB165; jump tree is N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ... checking previous tree N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB165 --- Relop [001958] BB165 value unknown, trying inference BB165 has side effects; no threading optRedundantRelop in BB164; jump tree is N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ... checking previous tree N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 -- prev tree VN is not related --- Trying RBO in BB164 --- Relop [001950] BB164 value unknown, trying inference BB164 has side effects; no threading --- Trying RBO in BB163 --- Relop [000707] BB163 value unknown, trying inference BB163 has side effects; no threading --- Trying RBO in BB162 --- Relop [000687] BB162 value unknown, trying inference ... JT-PHI [interestingVN] in BB162 relop first operand VN is PhiDef for V20:4 $948 N003 ( 3, 4) [000687] J------N--- * LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB161 --- Relop [000683] BB161 value unknown, trying inference ... JT-PHI [interestingVN] in BB161 relop first operand VN is PhiDef for V08:3 $350 N003 ( 3, 4) [000683] J------N--- * LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 No usable PhiDef VNs --- Trying RBO in BB160 --- Relop [000679] BB160 value unknown, trying inference Dominator BB78 of BB160 has relop with same liberal VN N003 ( 3, 4) [000180] J------N--- * EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 Redundant compare; current relop: N003 ( 3, 4) [000679] J------N--- * EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 -- BB157 not closest branching dom, so no threading ... JT-PHI [interestingVN] in BB160 relop first operand VN is PhiDef for V12:3 $34e N003 ( 3, 4) [000679] J------N--- * EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs optRedundantRelop in BB157; jump tree is N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB157 --- Relop [001911] BB157 value unknown, trying inference BB157 has side effects; no threading optRedundantRelop in BB156; jump tree is N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 -- prev tree is a phi --- Trying RBO in BB156 --- Relop [000667] BB156 value unknown, trying inference BB156 has global phi for V36.4; no phi-based threading --- Trying RBO in BB151 --- Relop [000721] BB151 value unknown, trying inference ... JT-PHI [interestingVN] in BB151 relop first operand VN is PhiDef for V08:3 $350 N003 ( 3, 3) [000721] J------N--- * GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ... JT-PHI [interestingVN] in BB151 relop second operand VN is PhiDef for V45:1 $352 N003 ( 3, 3) [000721] J------N--- * GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 No usable PhiDef VNs --- Trying RBO in BB150 --- Relop [000646] BB150 value unknown, trying inference BB150 has side effects; no threading optRedundantRelop in BB146; jump tree is N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ... checking previous tree N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related --- Trying RBO in BB146 --- Relop [000738] BB146 value unknown, trying inference BB146 has side effects; no threading --- Trying RBO in BB145 --- Relop [000641] BB145 value unknown, trying inference ... JT-PHI [interestingVN] in BB145 relop first operand VN is PhiDef for V14:3 $544 N003 ( 3, 4) [000641] J------N--- * GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB177 --- Relop [002028] BB177 value unknown, trying inference BB177 has side effects; no threading optRedundantRelop in BB176; jump tree is N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ... checking previous tree N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB176 --- Relop [002018] BB176 value unknown, trying inference BB176 has side effects; no threading optRedundantRelop in BB175; jump tree is N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ... checking previous tree N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f -- prev tree VN is not related --- Trying RBO in BB175 --- Relop [002010] BB175 value unknown, trying inference BB175 has side effects; no threading --- Trying RBO in BB174 --- Relop [000632] BB174 value unknown, trying inference BB174 has side effects; no threading --- Trying RBO in BB173 --- Relop [000627] BB173 value unknown, trying inference ... JT-PHI [interestingVN] in BB173 relop first operand VN is PhiDef for V05:3 $34e N003 ( 3, 3) [000627] J------N--- * GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ... JT-PHI [interestingVN] in BB173 relop second operand VN is PhiDef for V04:2 $35a N003 ( 3, 3) [000627] J------N--- * GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a No usable PhiDef VNs --- Trying RBO in BB172 --- Relop [000615] BB172 value unknown, trying inference ... JT-PHI [interestingVN] in BB172 relop first operand VN is PhiDef for V45:1 $352 N003 ( 3, 4) [000615] J------N--- * LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB171 --- Relop [000611] BB171 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB139 --- Relop [000603] BB139 value unknown, trying inference Can infer EQ from [true] dominating GT_UN Dominator BB136 of BB139 has same VN operands but different relop N003 ( 3, 4) [000277] N------N-U- * GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 Redundant compare; current relop: N003 ( 3, 4) [000603] J------N--- * EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 inference failed -- will keep looking higher No usable PhiDef VNs optRedundantRelop in BB136; jump tree is N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ... checking previous tree N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad -- prev tree is a phi --- Trying RBO in BB136 --- Relop [000277] BB136 value unknown, trying inference BB136 has global phi for V36.3; no phi-based threading --- Trying RBO in BB130 --- Relop [001865] BB130 value unknown, trying inference BB130 has side effects; no threading optRedundantRelop in BB129; jump tree is N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ... checking previous tree N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB129 --- Relop [001855] BB129 value unknown, trying inference BB129 has side effects; no threading optRedundantRelop in BB128; jump tree is N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ... checking previous tree N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 -- prev tree VN is not related --- Trying RBO in BB128 --- Relop [001847] BB128 value unknown, trying inference BB128 has side effects; no threading --- Trying RBO in BB127 --- Relop [000900] BB127 value unknown, trying inference BB127 has side effects; no threading --- Trying RBO in BB126 --- Relop [000880] BB126 value unknown, trying inference ... JT-PHI [interestingVN] in BB126 relop first operand VN is PhiDef for V20:7 $c6d N003 ( 3, 4) [000880] J------N--- * LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB125 --- Relop [000876] BB125 value unknown, trying inference ... JT-PHI [interestingVN] in BB125 relop first operand VN is PhiDef for V08:5 $544 N003 ( 3, 4) [000876] J------N--- * LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 No usable PhiDef VNs --- Trying RBO in BB124 --- Relop [000862] BB124 value unknown, trying inference Dominator BB78 of BB124 has relop with same liberal VN N003 ( 3, 4) [000180] J------N--- * EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 Redundant compare; current relop: N003 ( 3, 4) [000862] J------N--- * EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 -- BB121 not closest branching dom, so no threading ... JT-PHI [interestingVN] in BB124 relop first operand VN is PhiDef for V12:3 $34e N003 ( 3, 4) [000862] J------N--- * EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs optRedundantRelop in BB121; jump tree is N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ... checking previous tree N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related ... checking previous tree N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 -- prev tree is a phi --- Trying RBO in BB121 --- Relop [001805] BB121 value unknown, trying inference BB121 has global phi for V36.8; no phi-based threading optRedundantRelop in BB118; jump tree is N005 ( 8, 8) [000834] ---XG------ * JTRUE void $c1a N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 $904 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 -- prev tree VN is not related --- Trying RBO in BB118 --- Relop [000833] BB118 value unknown, trying inference BB118 has side effects; no threading optRedundantRelop in BB135; jump tree is N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad -- prev tree is a phi --- Trying RBO in BB135 --- Relop [000827] BB135 value unknown, trying inference BB135 has global phi for V36.7; no phi-based threading --- Trying RBO in BB116 --- Relop [000925] BB116 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB115 --- Relop [000921] BB115 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB114 --- Relop [000823] BB114 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB113 --- Relop [000273] BB113 value unknown, trying inference ... JT-PHI [interestingVN] in BB113 relop first operand VN is PhiDef for V14:2 $258 N003 ( 3, 4) [000273] J------N--- * LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB247 --- Relop [000269] BB247 value unknown, trying inference No usable PhiDef VNs optRedundantRelop in BB246; jump tree is N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 -- prev tree VN is not related ... checking previous tree N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 -- prev tree VN is not related ... checking previous tree N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae -- prev tree VN is not related --- Trying RBO in BB246 --- Relop [000265] BB246 value unknown, trying inference BB246 has side effects; no threading optRedundantRelop in BB245; jump tree is N004 ( 7, 8) [000210] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ... checking previous tree N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 -- prev tree is a phi --- Trying RBO in BB245 --- Relop [000209] BB245 value unknown, trying inference BB245 is the entry for L03; no threading --- Trying RBO in BB108 --- Relop [001752] BB108 value unknown, trying inference BB108 has side effects; no threading optRedundantRelop in BB107; jump tree is N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ... checking previous tree N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 -- prev tree VN is not related --- Trying RBO in BB107 --- Relop [001742] BB107 value unknown, trying inference BB107 has side effects; no threading optRedundantRelop in BB106; jump tree is N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ... checking previous tree N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b -- prev tree VN is not related --- Trying RBO in BB106 --- Relop [001734] BB106 value unknown, trying inference BB106 has side effects; no threading --- Trying RBO in BB105 --- Relop [000934] BB105 value unknown, trying inference BB105 has side effects; no threading --- Trying RBO in BB104 --- Relop [000929] BB104 value unknown, trying inference ... JT-PHI [interestingVN] in BB104 relop first operand VN is PhiDef for V15:2 $34d N003 ( 3, 4) [000929] J------N--- * NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs optRedundantRelop in BB103; jump tree is N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 -- prev tree is a phi --- Trying RBO in BB103 --- Relop [000185] BB103 value unknown, trying inference BB103 has global phi for V20.2; no phi-based threading optRedundantRelop in BB102; jump tree is N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ... checking previous tree N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e -- prev tree is a phi --- Trying RBO in BB102 --- Relop [001004] BB102 value unknown, trying inference BB102 has global phi for V30.3; no phi-based threading optRedundantRelop in BB100; jump tree is N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ... checking previous tree N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f -- prev tree has side effects, allowing as prev tree is immediately before jumpTree -- prev tree not ASG(LCL...) --- Trying RBO in BB100 --- Relop [001043] BB100 value unknown, trying inference BB100 has phi for promoted field V143.4; no phi-based threading -- no, jump tree cond is constant --- Trying RBO in BB96 --- Relop [001701] BB96 has known value true Redundant branch opt in BB96: removing useless STMT00353 ( INL23 @ 0x000[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 5, 6) [001702] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001701] ----------- \--* CNS_INT int 1 from BB96 Conditional folded at BB96 BB96 becomes a BBJ_ALWAYS to BB98 optRedundantBranch removed tree: N004 ( 5, 6) [001702] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001701] ----------- \--* CNS_INT int 1 Will retry RBO in BB99; pred BB97 now unreachable --- Trying RBO in BB99 --- optRedundantRelop in BB94; jump tree is N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ... checking previous tree N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 -- prev tree not ASG --- Trying RBO in BB94 --- Relop [001628] BB94 value unknown, trying inference BB94 has phi for promoted field V159.1; no phi-based threading -- no, jump tree cond is constant --- Trying RBO in BB91 --- Relop [001589] BB91 has known value true Redundant branch opt in BB91: removing useless STMT00329 ( INL15 @ 0x000[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 5, 6) [001590] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001589] ----------- \--* CNS_INT int 1 from BB91 Conditional folded at BB91 BB91 becomes a BBJ_ALWAYS to BB93 optRedundantBranch removed tree: N004 ( 5, 6) [001590] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001589] ----------- \--* CNS_INT int 1 Will retry RBO in BB94; pred BB92 now unreachable --- Trying RBO in BB94 --- Relop [001628] BB94 value unknown, trying inference BB94 has phi for promoted field V159.1; no phi-based threading optRedundantRelop in BB90; jump tree is N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ... checking previous tree N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related --- Trying RBO in BB90 --- Relop [001020] BB90 value unknown, trying inference BB90 has side effects; no threading optRedundantRelop in BB89; jump tree is N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 -- prev tree is a phi --- Trying RBO in BB89 --- Relop [001008] BB89 value unknown, trying inference BB89 is the entry for L02; no threading optRedundantRelop in BB88; jump tree is N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ... checking previous tree N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 -- prev tree is a phi --- Trying RBO in BB88 --- Relop [003157] BB88 value unknown, trying inference BB88 is the header for L02; no threading optRedundantRelop in BB85; jump tree is N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ... checking previous tree N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 -- prev tree is a phi --- Trying RBO in BB85 --- Relop [000993] BB85 value unknown, trying inference BB85 has side effects; no threading optRedundantRelop in BB82; jump tree is N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 -- prev tree is a phi --- Trying RBO in BB82 --- Relop [000972] BB82 value unknown, trying inference BB82 has global phi for V28.2; no phi-based threading optRedundantRelop in BB80; jump tree is N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 -- prev tree VN is not related ... checking previous tree N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 -- prev tree VN is not related --- Trying RBO in BB80 --- Relop [000964] BB80 value unknown, trying inference BB80 has side effects; no threading --- Trying RBO in BB79 --- Relop [000946] BB79 value unknown, trying inference BB79 has side effects; no threading optRedundantRelop in BB78; jump tree is N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 -- prev tree VN is not related ... checking previous tree N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) $c8 -- prev tree not ASG --- Trying RBO in BB78 --- Relop [000180] BB78 value unknown, trying inference BB78 has global phi for V14.1; no phi-based threading --- Trying RBO in BB74 --- Relop [000139] BB74 value unknown, trying inference BB74 has side effects; no threading optRedundantRelop in BB72; jump tree is N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba -- prev tree is a phi --- Trying RBO in BB72 --- Relop [000134] BB72 value unknown, trying inference BB72 has side effects; no threading optRedundantRelop in BB69; jump tree is N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ... checking previous tree N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 -- prev tree is a phi --- Trying RBO in BB69 --- Relop [000121] BB69 value unknown, trying inference BB69 has side effects; no threading --- Trying RBO in BB66 --- Relop [000108] BB66 value unknown, trying inference ... JT-PHI [interestingVN] in BB66 relop first operand VN is PhiDef for V06:2 $34f N003 ( 3, 3) [000108] J------N--- * LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ... JT-PHI [interestingVN] in BB66 relop second operand VN is PhiDef for V05:3 $34e N003 ( 3, 3) [000108] J------N--- * LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d No usable PhiDef VNs --- Trying RBO in BB63 --- Relop [000100] BB63 value unknown, trying inference BB63 has side effects; no threading optRedundantRelop in BB61; jump tree is N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ... checking previous tree N008 ( 23, 23) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 -- prev tree has side effects, allowing as prev tree is immediately before jumpTree -- prev tree VN is not related --- Trying RBO in BB61 --- Relop [001166] BB61 value unknown, trying inference BB61 has side effects; no threading optRedundantRelop in BB60; jump tree is N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 -- prev tree has side effects, allowing as prev tree is immediately before jumpTree -- prev tree not ASG --- Trying RBO in BB60 --- Relop [001155] BB60 value unknown, trying inference BB60 has side effects; no threading optRedundantRelop in BB57; jump tree is N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] D--XG--N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e -- prev tree not ASG(LCL...) --- Trying RBO in BB57 --- Relop [001139] BB57 value unknown, trying inference BB57 has side effects; no threading optRedundantRelop in BB56; jump tree is N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 -- prev tree is a phi --- Trying RBO in BB56 --- Relop [000095] BB56 value unknown, trying inference BB56 has global phi for V12.3; no phi-based threading --- Trying RBO in BB53 --- Relop [001182] BB53 value unknown, trying inference ... JT-PHI [interestingVN] in BB53 relop first operand VN is PhiDef for V10:2 $353 N003 ( 3, 3) [001182] N------N-U- * NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ... JT-PHI [interestingVN] in BB53 relop second operand VN is PhiDef for V05:3 $34e N003 ( 3, 3) [001182] N------N-U- * NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d No usable PhiDef VNs optRedundantRelop in BB52; jump tree is N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 -- prev tree is a phi --- Trying RBO in BB52 --- Relop [000090] BB52 value unknown, trying inference BB52 has global phi for V05.3; no phi-based threading optRedundantRelop in BB50; jump tree is N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 -- prev tree defs untracked V23 --- Trying RBO in BB50 --- Relop [000086] BB50 value unknown, trying inference BB50 has side effects; no threading --- Trying RBO in BB45 --- Relop [001328] BB45 value unknown, trying inference BB45 has side effects; no threading optRedundantRelop in BB44; jump tree is N004 ( 7, 8) [001315] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ... checking previous tree N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 -- prev tree VN is not related ... checking previous tree N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 -- prev tree is a phi --- Trying RBO in BB44 --- Relop [001314] BB44 value unknown, trying inference BB44 has side effects; no threading --- Trying RBO in BB43 --- Relop [001299] BB43 value unknown, trying inference BB43 has side effects; no threading --- Trying RBO in BB42 --- Relop [001339] BB42 value unknown, trying inference BB42 has side effects; no threading --- Trying RBO in BB41 --- Relop [001286] BB41 value unknown, trying inference BB41 has side effects; no threading --- Trying RBO in BB40 --- Relop [001275] BB40 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB39 --- Relop [001350] BB39 value unknown, trying inference BB39 has side effects; no threading --- Trying RBO in BB38 --- Relop [001266] BB38 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB36 --- Relop [001250] BB36 value unknown, trying inference BB36 has side effects; no threading --- Trying RBO in BB35 --- Relop [001239] BB35 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB15 --- Relop [001354] BB15 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB14 --- Relop [001259] BB14 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB13 --- Relop [001232] BB13 value unknown, trying inference No usable PhiDef VNs optRedundantRelop in BB33; jump tree is N010 ( 13, 14) [001471] ---XG------ * JTRUE void $876 N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001466] ----------- | \--* LSH long $3df N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ... checking previous tree N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 -- prev tree VN is not related --- Trying RBO in BB33 --- Relop [001470] BB33 value unknown, trying inference BB33 has side effects; no threading --- Trying RBO in BB32 --- Relop [001451] BB32 value unknown, trying inference BB32 has side effects; no threading optRedundantRelop in BB31; jump tree is N004 ( 7, 8) [001441] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ... checking previous tree N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 -- prev tree is a phi --- Trying RBO in BB31 --- Relop [001440] BB31 value unknown, trying inference BB31 has global phi for V16.21; no phi-based threading --- Trying RBO in BB26 --- Relop [001415] BB26 value unknown, trying inference ... JT-PHI [interestingVN] in BB26 relop first operand VN is PhiDef for V10:2 $353 N003 ( 3, 3) [001415] N------N-U- * NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ... JT-PHI [interestingVN] in BB26 relop second operand VN is PhiDef for V04:2 $35a N003 ( 3, 3) [001415] N------N-U- * NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a No usable PhiDef VNs --- Trying RBO in BB25 --- Relop [001405] BB25 value unknown, trying inference ... JT-PHI [interestingVN] in BB25 relop first operand VN is PhiDef for V10:2 $353 N003 ( 3, 4) [001405] J------N--- * LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB24 --- Relop [001401] BB24 value unknown, trying inference ... JT-PHI [interestingVN] in BB24 relop first operand VN is PhiDef for V05:2 $351 N003 ( 3, 4) [001401] J------N--- * GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB23 --- Relop [001397] BB23 value unknown, trying inference ... JT-PHI [interestingVN] in BB23 relop first operand VN is PhiDef for V04:2 $35a N003 ( 3, 4) [001397] J------N--- * LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB21 --- Relop [001390] BB21 value unknown, trying inference ... JT-PHI [interestingVN] in BB21 relop first operand VN is PhiDef for V05:2 $351 N003 ( 3, 4) [001390] J------N--- * GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 No usable PhiDef VNs --- Trying RBO in BB18 --- Relop [001375] BB18 value unknown, trying inference ... JT-PHI [interestingVN] in BB18 relop first operand VN is PhiDef for V06:2 $34f N003 ( 3, 6) [001375] N------N-U- * NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 No usable PhiDef VNs --- Trying RBO in BB11 --- Relop [001371] BB11 value unknown, trying inference Can infer EQ from [true] dominating GT_UN Dominator BB08 of BB11 has same VN operands but different relop N003 ( 3, 4) [001228] N------N-U- * GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 Redundant compare; current relop: N003 ( 3, 4) [001371] J------N--- * EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 inference failed -- will keep looking higher No usable PhiDef VNs --- Trying RBO in BB08 --- Relop [001228] BB08 value unknown, trying inference No usable PhiDef VNs --- Trying RBO in BB49 --- Relop [001224] BB49 value unknown, trying inference No usable PhiDef VNs optRedundantRelop in BB48; jump tree is N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 -- prev tree VN is not related ... checking previous tree N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 -- prev tree VN is not related ... checking previous tree N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 -- prev tree VN is not related ... checking previous tree N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b -- prev tree VN is not related --- Trying RBO in BB48 --- Relop [001220] BB48 value unknown, trying inference BB48 has side effects; no threading optRedundantRelop in BB47; jump tree is N004 ( 7, 8) [000079] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ... checking previous tree N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 -- prev tree is a phi --- Trying RBO in BB47 --- Relop [000078] BB47 value unknown, trying inference BB47 is the entry for L01; no threading optRedundantRelop in BB02; jump tree is N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 -- prev tree not ASG --- Trying RBO in BB02 --- Relop [001475] BB02 value unknown, trying inference BB02 has side effects; no threading optRedundantRelop in BB01; jump tree is N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ... checking previous tree N007 ( 14, 14) [002563] -A--------- * COMMA void $VN.Void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N006 ( 7, 7) [002562] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 -- prev tree not ASG --- Trying RBO in BB01 --- ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 (always) i hascall bwd BB92 [0219] 0 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 (always) i gcsafe bwd BB97 [0242] 0 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB213 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 1 BB208 2 3 [6A8..6B5)-> BB215 (always) i bwd BB213 [0169] 2 BB209,BB210 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Redundant branch opts Trees after Redundant branch opts ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 (always) i hascall bwd BB92 [0219] 0 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 (always) i gcsafe bwd BB97 [0242] 0 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB213 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 1 BB208 2 3 [6A8..6B5)-> BB215 (always) i bwd BB213 [0169] 2 BB209,BB210 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N007 ( 14, 14) [002563] -A--------- * COMMA void $VN.Void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N006 ( 7, 7) [002562] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N004 ( 3, 4) [002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 3, 4) [002606] -A--------- * COMMA void $580 N003 ( 3, 4) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 3, 4) [002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 3, 4) [003623] ----------- * COMMA void N001 ( 3, 4) [003621] -------H--- +--* LCL_FLD int V02 arg2 u:1[+8] $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 7, 8) [001441] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 3, 4) [001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N010 ( 13, 15) [001452] ---XG------ * JTRUE void $876 N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) [001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N010 ( 13, 14) [001471] ---XG------ * JTRUE void $876 N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) [001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001466] ----------- | \--* LSH long $3df N003 ( 2, 3) [001463] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 7, 8) [001240] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N010 ( 13, 15) [001251] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) [001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 7, 8) [001267] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) [001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N010 ( 13, 15) [001351] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) [001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 9, 11) [001276] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N010 ( 13, 15) [001287] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) [001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N010 ( 13, 15) [001340] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) [001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001335] ----------- | \--* LSH long $3c9 N003 ( 2, 3) [001332] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 7, 8) [001315] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 3, 4) [001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 7, 8) [000079] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 3, 4) [001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] D--XG--N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 3, 4) [002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool $301 N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int $301 N004 ( 4, 3) [000104] D--XG--N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N007 ( 8, 7) [000140] ---XG------ * JTRUE void $301 N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) [000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int $301 N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N004 ( 4, 3) [000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref $24a N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 $207 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) [000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [373..39A) -> BB93 (always), preds={BB90} succs={BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ------------ BB92 [383..384) -> BB94 (always), preds={} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (always), preds={BB95} succs={BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ------------ BB97 [391..392) -> BB99 (always), preds={} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void $845 N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001780] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 3, 4) [002788] -A--------- * COMMA void $588 N003 ( 3, 4) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 3, 4) [002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N005 ( 8, 8) [000834] ---XG------ * JTRUE void $c1a N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) [000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 $904 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int $c1a N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N002 ( 4, 3) [000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) $904 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001833] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) [001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001893] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001938] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001996] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002056] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002116] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002176] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort $bec N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N007 ( 9, 10) [000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long $acc N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000817] ----------- \--* LSH long $acb N003 ( 2, 3) [000814] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 $204 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002222] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 7, 8) [000757] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N010 ( 13, 15) [000791] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) [000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N010 ( 13, 14) [000802] ---XG------ * JTRUE void $bec N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) [000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000797] ----------- | \--* LSH long $acb N003 ( 2, 3) [000794] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 7, 8) [000764] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) [002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N010 ( 13, 15) [000775] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) [000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 7, 8) [000289] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N010 ( 13, 15) [000300] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) [000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N007 ( 9, 10) [000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000315] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002280] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 7, 8) [000425] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N010 ( 13, 15) [000575] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) [000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 9, 11) [000434] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) [002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N010 ( 13, 15) [000548] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) [000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB213 (cond), preds={BB209} succs={BB211,BB213} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB212 [6A8..6B5) -> BB215 (always), preds={BB208} succs={BB215} ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209,BB210} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N010 ( 13, 15) [000457] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) [000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000452] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000449] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002337] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 7, 8) [000485] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 3, 4) [002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002384] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 7, 8) [000342] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) [002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N010 ( 13, 15) [000353] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) [000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N010 ( 13, 15) [000418] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) [000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000413] ----------- | \--* LSH long $3e6 N003 ( 2, 3) [000410] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N007 ( 9, 10) [000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000368] ----------- \--* LSH long $3e6 N003 ( 2, 3) [000365] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 $204 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002432] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort $c02 N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N007 ( 9, 10) [000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000404] ----------- \--* LSH long $ad2 N003 ( 2, 3) [000401] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 $204 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002478] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 7, 8) [000378] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 3, 4) [002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N010 ( 13, 15) [000389] ---XG------ * JTRUE void $c02 N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) [000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002527] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 7, 8) [000210] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 3, 4) [002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [info] NumUses overestimated for V00.1: IR 80 SSA 108 [info] NumUses overestimated for V01.1: IR 17 SSA 21 [info] NumUses overestimated for V02.1: IR 22 SSA 23 [info] NumUses overestimated for V15.2: IR 4 SSA 5 [info] NumUses overestimated for V16.2: IR 2 SSA 3 [info] NumUses overestimated for V16.4: IR 2 SSA 3 [info] NumUses overestimated for V16.5: IR 19 SSA 22 [info] NumUses overestimated for V16.6: IR 4 SSA 5 [info] NumUses overestimated for V16.13: IR 8 SSA 9 [info] NumUses overestimated for V16.21: IR 4 SSA 5 [info] NumUses overestimated for V28.2: IR 2 SSA 3 [info] NumUses overestimated for V33.1: IR 4 SSA 10 [info] NumUses overestimated for V36.3: IR 6 SSA 7 [info] NumUses overestimated for V36.7: IR 4 SSA 5 [info] NumUses overestimated for V50.1: IR 1 SSA 2 [info] NumUses overestimated for V54.1: IR 1 SSA 2 [info] NumUses overestimated for V60.1: IR 0 SSA 2 [info] HasGlobalUse overestimated for V60.1 [info] NumUses overestimated for V62.1: IR 0 SSA 7 [info] HasGlobalUse overestimated for V62.1 [info] NumUses overestimated for V72.1: IR 1 SSA 2 [info] NumUses overestimated for V73.1: IR 1 SSA 2 [info] NumUses overestimated for V167.1: IR 1 SSA 2 SSA checks completed successfully *************** In fgDebugCheckLoopTable *************** Starting PHASE Optimize Valnum CSEs Candidate CSE #01, key=$246 in BB07, [cost= 3, size= 4]: N001 ( 3, 4) CSE #01 (use)[002601] ----------- * LCL_FLD byref V02 arg2 u:1[+0] $246 Candidate CSE #02, key=$342 in BB07, [cost= 3, size= 4]: N001 ( 3, 4) CSE #02 (use)[003621] -------H--- * LCL_FLD int V02 arg2 u:1[+8] $342 Candidate CSE #03, key=$68f in BB20, [cost= 3, size= 4]: N003 ( 3, 4) CSE #03 (use)[001379] ----------- * ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 Candidate CSE #04, key=$3de in BB33, [cost= 2, size= 3]: N003 ( 2, 3) CSE #04 (use)[001463] ----------- * CAST long <- int $3de N002 ( 1, 1) [001462] ----------- \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 Candidate CSE #05, key=$3df in BB33, [cost= 4, size= 6]: N005 ( 4, 6) CSE #05 (use)[001466] ----------- * LSH long $3df N003 ( 2, 3) CSE #04 (use)[001463] ----------- +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- \--* CNS_INT long 1 $204 Candidate CSE #06, key=$5c4 in BB33, [cost= 9, size=10]: N007 ( 9, 10) CSE #06 (use)[001468] ---XG------ * IND ushort N006 ( 6, 8) [001467] -------N--- \--* ADD long $3e0 N001 ( 1, 1) [001453] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #05 (use)[001466] ----------- \--* LSH long $3df N003 ( 2, 3) CSE #04 (use)[001463] ----------- +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- \--* CNS_INT long 1 $204 Candidate CSE #07, key=$3c8 in BB39, [cost= 2, size= 3]: N003 ( 2, 3) CSE #07 (use)[001343] ----------- * CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- \--* LCL_VAR int V16 loc12 u:17 $361 Candidate CSE #08, key=$3c9 in BB39, [cost= 4, size= 6]: N005 ( 4, 6) CSE #08 (use)[001346] ----------- * LSH long $3c9 N003 ( 2, 3) CSE #07 (use)[001343] ----------- +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- \--* CNS_INT long 1 $204 Candidate CSE #09, key=$5c1 in BB39, [cost= 9, size=10]: N007 ( 9, 10) CSE #09 (use)[001348] ---XG------ * IND ushort N006 ( 6, 8) [001347] -------N--- \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (use)[001346] ----------- \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (use)[001343] ----------- +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- \--* CNS_INT long 1 $204 Candidate CSE #10, key=$371 in BB40, [cost= 3, size= 4]: N003 ( 3, 4) CSE #10 (use)[001270] ----------- * ADD int $371 N001 ( 1, 1) [001268] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- \--* CNS_INT int 1 $c1 Candidate CSE #11, key=$43 in BB61, [cost= 2, size= 8]: N004 ( 2, 8) CSE #11 (use)[002625] H---------- * CNS_INT(h) long 0x40000000005401e8 ftn $43 Candidate CSE #12, key=$294 in BB76, [cost= 4, size= 3]: N004 ( 4, 3) CSE #12 (use)[000142] ---XG------ * IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref $24a N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 $207 Candidate CSE #13, key=$2c9 in BB81, [cost= 3, size= 3]: N003 ( 3, 3) CSE #13 (use)[002661] ---X------- * ARR_LENGTH int N002 ( 1, 1) [001098] ----------- \--* LCL_VAR ref V26 loc22 u:1 Candidate CSE #14, key=$253 in BB98, [cost= 3, size= 4]: N003 ( 3, 4) CSE #14 (use)[002720] -----O----- * ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 Candidate CSE #15, key=$2cc in BB98, [cost= 3, size= 3]: N002 ( 3, 3) CSE #15 (use)[001720] ---X------- * ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 Candidate CSE #16, key=$24e in BB101, [cost= 3, size= 4]: N007 ( 3, 4) CSE #16 (use)[002738] ----------- * ADD byref N005 ( 1, 1) [002730] ----------- +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- \--* CNS_INT long 16 $200 Candidate CSE #17, key=$2d0 in BB109, [cost= 3, size= 3]: N018 ( 3, 3) CSE #17 (use)[002767] ---X------- * ARR_LENGTH int N017 ( 1, 1) [001770] ----------- \--* LCL_VAR ref V86 tmp46 u:1 Candidate CSE #18, key=$406 in BB120, [cost= 4, size= 3]: N002 ( 4, 3) CSE #18 (use)[000850] ---XG------ * IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) $904 Candidate CSE #19, key=$25c in BB122, [cost= 3, size= 4]: N003 ( 3, 4) CSE #19 (use)[002805] -----O----- * ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 Candidate CSE #20, key=$c89 in BB131, [cost= 3, size= 3]: N018 ( 3, 3) CSE #20 (use)[002834] ---X------- * ARR_LENGTH int N017 ( 1, 1) [001883] ----------- \--* LCL_VAR ref V95 tmp55 u:1 Candidate CSE #21, key=$4f in BB132, [cost= 2, size= 8]: N003 ( 2, 8) CSE #21 (use)[002847] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn $4f Candidate CSE #22, key=$404 in BB154, [cost= 4, size= 3]: N002 ( 4, 3) CSE #22 (use)[000658] ---XG------ * IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 Candidate CSE #23, key=$53 in BB159, [cost= 2, size= 8]: N003 ( 2, 8) CSE #23 (use)[002870] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 Candidate CSE #24, key=$2ef in BB167, [cost= 3, size= 3]: N018 ( 3, 3) CSE #24 (use)[002892] ---X------- * ARR_LENGTH int N017 ( 1, 1) [001986] ----------- \--* LCL_VAR ref V102 tmp62 u:1 Candidate CSE #25, key=$2b6 in BB176, [cost= 4, size= 3]: N004 ( 4, 3) CSE #25 (use)[002012] ---XG------ * IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 Candidate CSE #26, key=$2b7 in BB177, [cost= 4, size= 3]: N005 ( 4, 3) CSE #26 (use)[002062] ---XG------ * IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c Candidate CSE #27, key=$2b8 in BB178, [cost= 4, size= 3]: N005 ( 4, 3) CSE #27 (use)[002038] ---XG------ * IND int N004 ( 3, 4) [002922] -------N--- \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- \--* CNS_INT long 8 $201 Candidate CSE #28, key=$387 in BB178, [cost= 3, size= 2]: N008 ( 3, 2) CSE #28 (use)[002043] ---XG------ * IND byref N007 ( 1, 1) [002036] ----------- \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c Candidate CSE #29, key=$3e8 in BB178, [cost= 2, size= 3]: N010 ( 2, 3) CSE #29 (use)[002040] ---------U- * CAST long <- uint N009 ( 1, 1) [002033] ----------- \--* LCL_VAR int V107 tmp67 u:1 Candidate CSE #30, key=$3ea in BB178, [cost= 4, size= 6]: N012 ( 4, 6) CSE #30 (use)[002042] ----------- * LSH long N010 ( 2, 3) CSE #29 (use)[002040] ---------U- +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- \--* CNS_INT long 1 $204 Candidate CSE #31, key=$2f4 in BB178, [cost= 3, size= 3]: N018 ( 3, 3) CSE #31 (use)[002926] ---X------- * ARR_LENGTH int N017 ( 1, 1) [002046] ----------- \--* LCL_VAR ref V106 tmp66 u:1 Candidate CSE #32, key=$961 in BB178, [cost= 3, size= 4]: N003 ( 3, 4) CSE #32 (use)[002055] ----------- * ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 Candidate CSE #33, key=$2da in BB184, [cost= 3, size= 3]: N018 ( 3, 3) CSE #33 (use)[002959] ---X------- * ARR_LENGTH int N017 ( 1, 1) [002106] ----------- \--* LCL_VAR ref V110 tmp70 u:1 Candidate CSE #34, key=$2f9 in BB189, [cost= 3, size= 3]: N018 ( 3, 3) CSE #34 (use)[002993] ---X------- * ARR_LENGTH int N017 ( 1, 1) [002166] ----------- \--* LCL_VAR ref V114 tmp74 u:1 Candidate CSE #35, key=$aca in BB195, [cost= 2, size= 3]: N003 ( 2, 3) CSE #35 (use)[000783] ----------- * CAST long <- int $aca N002 ( 1, 1) [000782] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 Candidate CSE #36, key=$acb in BB195, [cost= 4, size= 6]: N005 ( 4, 6) CSE #36 (use)[000786] ----------- * LSH long $acb N003 ( 2, 3) CSE #35 (use)[000783] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- \--* CNS_INT long 1 $204 Candidate CSE #37, key=$5ca in BB195, [cost= 9, size=10]: N007 ( 9, 10) CSE #37 (use)[000788] ---XG------ * IND ushort N006 ( 6, 8) [000787] -------N--- \--* ADD long $acc N001 ( 1, 1) [000781] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #36 (use)[000786] ----------- \--* LSH long $acb N003 ( 2, 3) CSE #35 (use)[000783] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- \--* CNS_INT long 1 $204 Candidate CSE #38, key=$bad in BB199, [cost= 3, size= 4]: N003 ( 3, 4) CSE #38 (use)[000778] ----------- * ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 Candidate CSE #39, key=$3e5 in BB202, [cost= 2, size= 3]: N003 ( 2, 3) CSE #39 (use)[000312] ----------- * CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 Candidate CSE #40, key=$3e6 in BB202, [cost= 4, size= 6]: N005 ( 4, 6) CSE #40 (use)[000315] ----------- * LSH long $3e6 N003 ( 2, 3) CSE #39 (use)[000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 Candidate CSE #41, key=$5c6 in BB202, [cost= 9, size=10]: N007 ( 9, 10) CSE #41 (use)[000317] ---XG------ * IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (use)[000315] ----------- \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (use)[000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 Candidate CSE #42, key=$952 in BB208, [cost= 3, size= 4]: N003 ( 3, 4) CSE #42 (use)[000428] ----------- * ADD int $952 N001 ( 1, 1) [000426] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- \--* CNS_INT int 1 $c1 Candidate CSE #43, key=$3f4 in BB214, [cost= 4, size= 6]: N005 ( 4, 6) CSE #43 (use)[000462] ----------- * CAST long <- int $3f4 N004 ( 3, 4) CSE #42 (use)[000461] ----------- \--* ADD int $952 N002 ( 1, 1) [000459] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- \--* CNS_INT int 1 $c1 Candidate CSE #44, key=$3f5 in BB214, [cost= 6, size= 9]: N007 ( 6, 9) CSE #44 (use)[000465] ----------- * LSH long $3f5 N005 ( 4, 6) CSE #43 (use)[000462] ----------- +--* CAST long <- int $3f4 N004 ( 3, 4) CSE #42 (use)[000461] ----------- | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- \--* CNS_INT long 1 $204 Candidate CSE #45, key=$5c8 in BB214, [cost=11, size=13]: N009 ( 11, 13) CSE #45 (use)[000467] ---XG------ * IND ushort N008 ( 8, 11) [000466] -------N--- \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) CSE #44 (use)[000465] ----------- \--* LSH long $3f5 N005 ( 4, 6) CSE #43 (use)[000462] ----------- +--* CAST long <- int $3f4 N004 ( 3, 4) CSE #42 (use)[000461] ----------- | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- \--* CNS_INT long 1 $204 Candidate CSE #46, key=$5c7 in BB232, [cost= 9, size=10]: N007 ( 9, 10) CSE #46 (use)[000415] ---XG------ * IND ushort N006 ( 6, 8) [000414] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000408] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (use)[000413] ----------- \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (use)[000410] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000409] ----------- | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000412] ----------- \--* CNS_INT long 1 $204 Candidate CSE #47, key=$ad1 in BB240, [cost= 2, size= 3]: N003 ( 2, 3) CSE #47 (use)[000381] ----------- * CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 Candidate CSE #48, key=$ad2 in BB240, [cost= 4, size= 6]: N005 ( 4, 6) CSE #48 (use)[000384] ----------- * LSH long $ad2 N003 ( 2, 3) CSE #47 (use)[000381] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- \--* CNS_INT long 1 $204 Candidate CSE #49, key=$5cb in BB240, [cost= 9, size=10]: N007 ( 9, 10) CSE #49 (use)[000386] ---XG------ * IND ushort N006 ( 6, 8) [000385] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #48 (use)[000384] ----------- \--* LSH long $ad2 N003 ( 2, 3) CSE #47 (use)[000381] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- \--* CNS_INT long 1 $204 Blocks that generate CSE def/uses BB01 cseGen = 0000000000000000000000000000000F CSE #01.c, CSE #02.c BB06 cseGen = 00000000000000000000000000100000 CSE #11 BB07 cseGen = 0000000000000000000000000000000F CSE #01.c, CSE #02.c BB17 cseGen = 00000000000000000000000000000030 CSE #03.c BB20 cseGen = 00000000000000000000000000000030 CSE #03.c BB31 cseGen = 0000000000000000000000000000000C CSE #02.c BB32 cseGen = 00000000000000000000000000000FC0 CSE #04.c, CSE #05.c, CSE #06.c BB33 cseGen = 00000000000000000000000000000FC0 CSE #04.c, CSE #05.c, CSE #06.c BB35 cseGen = 0000000000000000000000000000000C CSE #02.c BB36 cseGen = 0000000000000000000000000003F000 CSE #07.c, CSE #08.c, CSE #09.c BB37 cseGen = 000000000000000000000000000C0000 CSE #10.c BB38 cseGen = 0000000000000000000000000000000C CSE #02.c BB39 cseGen = 0000000000000000000000000003F000 CSE #07.c, CSE #08.c, CSE #09.c BB40 cseGen = 000000000000000000000000000C000C CSE #02.c, CSE #10.c BB41 cseGen = 0000000000000000000000000003F000 CSE #07.c, CSE #08.c, CSE #09.c BB42 cseGen = 0000000000000000000000000003F000 CSE #07.c, CSE #08.c, CSE #09.c BB43 cseGen = 000000000000000000000000000C0000 CSE #10.c BB44 cseGen = 0000000000000000000000000000000C CSE #02.c BB47 cseGen = 0000000000000000000000000000000C CSE #02.c BB61 cseGen = 00000000000000000000000000100001 CSE #01, CSE #11 BB74 cseGen = 00000000000000000000000000C00000 CSE #12.c BB76 cseGen = 00000000000000000000000000C00000 CSE #12.c BB77 cseGen = 00000000000000000000000000C00000 CSE #12.c BB80 cseGen = 00000000000000000000000003000000 CSE #13.c BB81 cseGen = 000000000000000000000000C3000000 CSE #13.c, CSE #16.c BB93 cseGen = 0000000000000000000000003C000000 CSE #14.c, CSE #15.c BB98 cseGen = 0000000000000000000000003C000000 CSE #14.c, CSE #15.c BB101 cseGen = 000000000000000000000000C3000000 CSE #13.c, CSE #16.c BB107 cseGen = 00000000000000000000000300000000 CSE #17.c BB109 cseGen = 00000000000000000000003300000000 CSE #17.c, CSE #19.c BB111 cseGen = 00000000000000000000010000000000 CSE #21 BB112 cseGen = 00000000000000000000000000000003 CSE #01.c BB118 cseGen = 00000000000000000000000C00000000 CSE #18.c BB120 cseGen = 00000000000000000000000C00000000 CSE #18.c BB122 cseGen = 00000000000000000000003000000000 CSE #19.c BB123 cseGen = 00000000000000000000100000000000 CSE #23 BB129 cseGen = 0000000000000000000000C000000000 CSE #20.c BB131 cseGen = 0000000000000000000000F000000000 CSE #19.c, CSE #20.c BB132 cseGen = 00000000000000000000010000000000 CSE #21 BB150 cseGen = 000000000000000000000C0000000000 CSE #22.c BB154 cseGen = 000000000000000000000C0000000000 CSE #22.c BB157 cseGen = 0000000000000000000F000000000000 CSE #25.c, CSE #26.c BB158 cseGen = 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c BB159 cseGen = 00000000000000000000100000000000 CSE #23 BB165 cseGen = 00000000000000000000C00000000000 CSE #24.c BB167 cseGen = 00000000000000000000C03000000000 CSE #19.c, CSE #24.c BB168 cseGen = 00000000000000000000010000000000 CSE #21 BB174 cseGen = 000000000000000000000C0000000000 CSE #22.c BB176 cseGen = 00000000000000003003000000000000 CSE #25.c, CSE #31.c BB177 cseGen = 0000000000000000000C000000000000 CSE #26.c BB178 cseGen = 0000000000000000FFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #31.c, CSE #32.c BB179 cseGen = 00000000000000000000010000000000 CSE #21 BB182 cseGen = 00000000000000030003000000000000 CSE #25.c, CSE #33.c BB183 cseGen = 0000000000000000000C000000000000 CSE #26.c BB184 cseGen = 0000000000000003CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c, CSE #33.c BB185 cseGen = 00000000000000000000010000000000 CSE #21 BB187 cseGen = 000000000000000C0003000000000000 CSE #25.c, CSE #34.c BB188 cseGen = 0000000000000000000C000000000000 CSE #26.c BB189 cseGen = 000000000000000CCFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c, CSE #34.c BB190 cseGen = 00000000000000000000010000000000 CSE #21 BB191 cseGen = 0000000000000FF00000000000000000 CSE #35.c, CSE #36.c, CSE #37.c, CSE #38.c BB192 cseGen = 00000000000000000000003000000000 CSE #19.c BB193 cseGen = 00000000000000000000100000000000 CSE #23 BB194 cseGen = 0000000000000000000000000000000C CSE #02.c BB195 cseGen = 00000000000003F00000000000000000 CSE #35.c, CSE #36.c, CSE #37.c BB196 cseGen = 00000000000003F00000000000000000 CSE #35.c, CSE #36.c, CSE #37.c BB197 cseGen = 0000000000000000000000000000000C CSE #02.c BB198 cseGen = 00000000000003F00000000000000000 CSE #35.c, CSE #36.c, CSE #37.c BB199 cseGen = 0000000000000C000000000000000000 CSE #38.c BB200 cseGen = 0000000000000000000000000000000C CSE #02.c BB201 cseGen = 000000000003F0000000000000000000 CSE #39.c, CSE #40.c, CSE #41.c BB202 cseGen = 00000000000FF000000F000000000000 CSE #25.c, CSE #26.c, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c BB203 cseGen = 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c BB204 cseGen = 00000000000000000000100000000000 CSE #23 BB206 cseGen = 0000000000000000000000000000000C CSE #02.c BB207 cseGen = 000000000003F0000000000000000000 CSE #39.c, CSE #40.c, CSE #41.c BB208 cseGen = 00000000000C0000000000000000000C CSE #02.c, CSE #42.c BB209 cseGen = 000000000003F0000000000000000000 CSE #39.c, CSE #40.c, CSE #41.c BB210 cseGen = 0000000003FC00000000000000000000 CSE #42.c, CSE #43.c, CSE #44.c, CSE #45.c BB213 cseGen = 000000000003F0000000000000000000 CSE #39.c, CSE #40.c, CSE #41.c BB214 cseGen = 0000000003FC00000000000000000000 CSE #42.c, CSE #43.c, CSE #44.c, CSE #45.c BB215 cseGen = 0000000000000000000F000000000000 CSE #25.c, CSE #26.c BB216 cseGen = 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c BB219 cseGen = 0000000000000000000000000000000C CSE #02.c BB227 cseGen = 0000000000000000000F000000000000 CSE #25.c, CSE #26.c BB228 cseGen = 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c BB229 cseGen = 00000000000000000000100000000000 CSE #23 BB230 cseGen = 0000000000000000000000000000000C CSE #02.c BB231 cseGen = 000000000C00F0000000000000000000 CSE #39.c, CSE #40.c, CSE #46.c BB232 cseGen = 000000000C00F0000000000000000000 CSE #39.c, CSE #40.c, CSE #46.c BB233 cseGen = 000000000C0CF0000000000000000000 CSE #39.c, CSE #40.c, CSE #42.c, CSE #46.c BB234 cseGen = 00000000000000000000003000000000 CSE #19.c BB235 cseGen = 00000000000000000000100000000000 CSE #23 BB236 cseGen = 00000003F00000000000000000000000 CSE #47.c, CSE #48.c, CSE #49.c BB237 cseGen = 00000000000000000000003000000000 CSE #19.c BB238 cseGen = 00000000000000000000100000000000 CSE #23 BB239 cseGen = 0000000000000000000000000000000C CSE #02.c BB240 cseGen = 00000003F00000000000000000000000 CSE #47.c, CSE #48.c, CSE #49.c BB242 cseGen = 0000000000000000000F000000000000 CSE #25.c, CSE #26.c BB243 cseGen = 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c BB244 cseGen = 00000000000000000000100000000000 CSE #23 BB245 cseGen = 0000000000000000000000000000000C CSE #02.c [info] NumUses overestimated for V00.1: IR 80 SSA 108 [info] NumUses overestimated for V01.1: IR 17 SSA 21 [info] NumUses overestimated for V02.1: IR 22 SSA 23 [info] NumUses overestimated for V15.2: IR 4 SSA 5 [info] NumUses overestimated for V16.2: IR 2 SSA 3 [info] NumUses overestimated for V16.4: IR 2 SSA 3 [info] NumUses overestimated for V16.5: IR 19 SSA 22 [info] NumUses overestimated for V16.6: IR 4 SSA 5 [info] NumUses overestimated for V16.13: IR 8 SSA 9 [info] NumUses overestimated for V16.21: IR 4 SSA 5 [info] NumUses overestimated for V28.2: IR 2 SSA 3 [info] NumUses overestimated for V33.1: IR 4 SSA 10 [info] NumUses overestimated for V36.3: IR 6 SSA 7 [info] NumUses overestimated for V36.7: IR 4 SSA 5 [info] NumUses overestimated for V50.1: IR 1 SSA 2 [info] NumUses overestimated for V54.1: IR 1 SSA 2 [info] NumUses overestimated for V60.1: IR 0 SSA 2 [info] HasGlobalUse overestimated for V60.1 [info] NumUses overestimated for V62.1: IR 0 SSA 7 [info] HasGlobalUse overestimated for V62.1 [info] NumUses overestimated for V72.1: IR 1 SSA 2 [info] NumUses overestimated for V73.1: IR 1 SSA 2 [info] NumUses overestimated for V167.1: IR 1 SSA 2 SSA checks completed successfully Performing DataFlow for ValnumCSE's After performing DataFlow for ValnumCSE's BB01 in: 00000000000000000000000000000000 gen: 0000000000000000000000000000000F CSE #01.c, CSE #02.c out: 0000000000000000000000000000000F CSE #01.c, CSE #02.c BB02 in: 0000000000000000000000000000000F CSE #01.c, CSE #02.c gen: 00000000000000000000000000000000 out: 0000000000000000000000000000000F CSE #01.c, CSE #02.c BB03 in: 0000000000000000000000000000000F CSE #01.c, CSE #02.c gen: 00000000000000000000000000000000 out: 0000000000000000000000000000000F CSE #01.c, CSE #02.c BB04 in: 0000000000000000000000000000000F CSE #01.c, CSE #02.c gen: 00000000000000000000000000000000 out: 0000000000000000000000000000000F CSE #01.c, CSE #02.c BB05 in: 0000000000000000000000000000000F CSE #01.c, CSE #02.c gen: 00000000000000000000000000000000 out: 0000000000000000000000000000000F CSE #01.c, CSE #02.c BB06 in: 0000000000000000000000000000000F CSE #01.c, CSE #02.c gen: 00000000000000000000000000100000 CSE #11 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB07 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 0000000000000000000000000000000F CSE #01.c, CSE #02.c out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB08 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB09 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB10 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB11 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB12 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB13 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB14 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB15 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB16 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB17 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000030 CSE #03.c out: 0000000000000000000000000010003F CSE #01.c, CSE #02.c, CSE #03.c, CSE #11 BB18 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB19 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB20 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000030 CSE #03.c out: 0000000000000000000000000010003F CSE #01.c, CSE #02.c, CSE #03.c, CSE #11 BB21 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB22 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB23 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB24 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB25 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB26 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB27 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB28 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB29 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB30 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB31 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB32 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000FC0 CSE #04.c, CSE #05.c, CSE #06.c out: 00000000000000000000000000100FCF CSE #01.c, CSE #02.c, CSE #04.c, CSE #05.c, CSE #06.c, CSE #11 BB33 in: 00000000000000000000000000100FCF CSE #01.c, CSE #02.c, CSE #04.c, CSE #05.c, CSE #06.c, CSE #11 gen: 00000000000000000000000000000FC0 CSE #04.c, CSE #05.c, CSE #06.c out: 00000000000000000000000000100FCF CSE #01.c, CSE #02.c, CSE #04.c, CSE #05.c, CSE #06.c, CSE #11 BB34 in: 00000000000000000000000000100FCF CSE #01.c, CSE #02.c, CSE #04.c, CSE #05.c, CSE #06.c, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100FCF CSE #01.c, CSE #02.c, CSE #04.c, CSE #05.c, CSE #06.c, CSE #11 BB35 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB36 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 0000000000000000000000000003F000 CSE #07.c, CSE #08.c, CSE #09.c out: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 BB37 in: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 gen: 000000000000000000000000000C0000 CSE #10.c out: 000000000000000000000000001FF00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #10.c, CSE #11 BB38 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB39 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 0000000000000000000000000003F000 CSE #07.c, CSE #08.c, CSE #09.c out: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 BB40 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 000000000000000000000000000C000C CSE #02.c, CSE #10.c out: 000000000000000000000000001C000F CSE #01.c, CSE #02.c, CSE #10.c, CSE #11 BB41 in: 000000000000000000000000001C000F CSE #01.c, CSE #02.c, CSE #10.c, CSE #11 gen: 0000000000000000000000000003F000 CSE #07.c, CSE #08.c, CSE #09.c out: 000000000000000000000000001FF00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #10.c, CSE #11 BB42 in: 000000000000000000000000001FF00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #10.c, CSE #11 gen: 0000000000000000000000000003F000 CSE #07.c, CSE #08.c, CSE #09.c out: 000000000000000000000000001FF00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #10.c, CSE #11 BB43 in: 000000000000000000000000001FF00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #10.c, CSE #11 gen: 000000000000000000000000000C0000 CSE #10.c out: 000000000000000000000000001FF00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #10.c, CSE #11 BB44 in: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 BB45 in: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 BB46 in: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000013F00F CSE #01.c, CSE #02.c, CSE #07.c, CSE #08.c, CSE #09.c, CSE #11 BB47 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB48 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB49 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB50 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB51 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB52 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB53 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB54 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB55 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB56 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB57 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB58 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB59 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB60 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB61 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000100001 CSE #01, CSE #11 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB62 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB63 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB64 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB65 in: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000F CSE #01.c, CSE #02.c, CSE #11 BB66 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB67 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB68 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB69 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB70 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB71 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB72 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB73 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB74 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000C00000 CSE #12.c out: 00000000000000000000000000D00005 CSE #01, CSE #02, CSE #11, CSE #12.c BB75 in: 00000000000000000000000000D00005 CSE #01, CSE #02, CSE #11, CSE #12.c gen: 00000000000000000000000000000000 out: 00000000000000000000000000D00005 CSE #01, CSE #02, CSE #11, CSE #12.c BB76 in: 00000000000000000000000000D00005 CSE #01, CSE #02, CSE #11, CSE #12.c gen: 00000000000000000000000000C00000 CSE #12.c out: 00000000000000000000000000D00005 CSE #01, CSE #02, CSE #11, CSE #12.c BB77 in: 00000000000000000000000000D00005 CSE #01, CSE #02, CSE #11, CSE #12.c gen: 00000000000000000000000000C00000 CSE #12.c out: 00000000000000000000000000D00005 CSE #01, CSE #02, CSE #11, CSE #12.c BB78 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB79 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB80 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000003000000 CSE #13.c out: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c BB81 in: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c gen: 000000000000000000000000C3000000 CSE #13.c, CSE #16.c out: 000000000000000000000000C3100005 CSE #01, CSE #02, CSE #11, CSE #13.c, CSE #16.c BB82 in: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c gen: 00000000000000000000000000000000 out: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c BB83 in: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c gen: 00000000000000000000000000000000 out: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c BB84 in: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c gen: 00000000000000000000000000000000 out: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c BB85 in: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c gen: 00000000000000000000000000000000 out: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c BB86 in: 00000000000000000000000003100005 CSE #01, CSE #02, CSE #11, CSE #13.c gen: 00000000000000000000000000000000 out: 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00000000000000000000C03000000000 CSE #19.c, CSE #24.c out: 00000000000000000005C03000100005 CSE #01, CSE #02, CSE #11, CSE #19.c, CSE #24.c, CSE #25, CSE #26 BB168 in: 00000000000000000005C00000100005 CSE #01, CSE #02, CSE #11, CSE #24.c, CSE #25, CSE #26 gen: 00000000000000000000010000000000 CSE #21 out: 00000000000000000005410000100005 CSE #01, CSE #02, CSE #11, CSE #21, CSE #24, CSE #25, CSE #26 BB169 in: 00000000000000000005000000100005 CSE #01, CSE #02, CSE #11, CSE #25, CSE #26 gen: 00000000000000000000000000000000 out: 00000000000000000005000000100005 CSE #01, CSE #02, CSE #11, CSE #25, CSE #26 BB170 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB171 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB172 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB173 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB174 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 000000000000000000000C0000000000 CSE #22.c out: 000000000000000000000C0000100005 CSE #01, CSE #02, CSE #11, CSE #22.c BB175 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB176 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000003003000000000000 CSE #25.c, CSE #31.c out: 00000000000000003003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #31.c BB177 in: 00000000000000003003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #31.c gen: 0000000000000000000C000000000000 CSE #26.c out: 0000000000000000300F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c, CSE #31.c BB178 in: 0000000000000000300F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c, CSE #31.c gen: 0000000000000000FFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #31.c, CSE #32.c out: 0000000000000000FFFF003000100005 CSE #01, CSE #02, CSE #11, CSE #19.c, CSE #25.c, CSE #26.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #31.c, CSE #32.c BB179 in: 00000000000000003003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #31.c gen: 00000000000000000000010000000000 CSE #21 out: 00000000000000001001010000100005 CSE #01, CSE #02, CSE #11, CSE #21, CSE #25, CSE #31 BB180 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB181 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB182 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000030003000000000000 CSE #25.c, CSE #33.c out: 00000000000000030003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #33.c BB183 in: 00000000000000030003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #33.c gen: 0000000000000000000C000000000000 CSE #26.c out: 0000000000000003000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c, CSE #33.c BB184 in: 0000000000000003000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c, CSE #33.c gen: 0000000000000003CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c, CSE #33.c out: 0000000000000003CFFF003000100005 CSE #01, CSE #02, CSE #11, CSE #19.c, CSE #25.c, CSE #26.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c, CSE #33.c BB185 in: 00000000000000030003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #33.c gen: 00000000000000000000010000000000 CSE #21 out: 00000000000000010001010000100005 CSE #01, CSE #02, CSE #11, CSE #21, CSE #25, CSE #33 BB186 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB187 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 000000000000000C0003000000000000 CSE #25.c, CSE #34.c out: 000000000000000C0003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #34.c BB188 in: 000000000000000C0003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #34.c gen: 0000000000000000000C000000000000 CSE #26.c out: 000000000000000C000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c, CSE #34.c BB189 in: 000000000000000C000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c, CSE #34.c gen: 000000000000000CCFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c, CSE #34.c out: 000000000000000CCFFF003000100005 CSE #01, CSE #02, CSE #11, CSE #19.c, CSE #25.c, CSE #26.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c, CSE #34.c BB190 in: 000000000000000C0003000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #34.c gen: 00000000000000000000010000000000 CSE #21 out: 00000000000000040001010000100005 CSE #01, CSE #02, CSE #11, CSE #21, CSE #25, CSE #34 BB191 in: 00000000000003F0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c gen: 0000000000000FF00000000000000000 CSE #35.c, CSE #36.c, CSE #37.c, CSE #38.c out: 0000000000000FF0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c, CSE #38.c BB192 in: 0000000000000FF0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c, CSE #38.c gen: 00000000000000000000003000000000 CSE #19.c out: 0000000000000FF0000000300010000D CSE #01, CSE #02.c, CSE #11, CSE #19.c, CSE #35.c, CSE #36.c, CSE #37.c, CSE #38.c BB193 in: 0000000000000FF0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c, CSE #38.c gen: 00000000000000000000100000000000 CSE #23 out: 00000000000005500000100000100005 CSE #01, CSE #02, CSE #11, CSE #23, CSE #35, CSE #36, CSE #37, CSE #38 BB194 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB195 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000003F00000000000000000 CSE #35.c, CSE #36.c, CSE #37.c out: 00000000000003F0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c BB196 in: 00000000000003F0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c gen: 00000000000003F00000000000000000 CSE #35.c, CSE #36.c, CSE #37.c out: 00000000000003F0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c BB197 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB198 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000003F00000000000000000 CSE #35.c, CSE #36.c, CSE #37.c out: 00000000000003F0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c BB199 in: 00000000000003F0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c gen: 0000000000000C000000000000000000 CSE #38.c out: 0000000000000FF0000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #35.c, CSE #36.c, CSE #37.c, CSE #38.c BB200 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB201 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 000000000003F0000000000000000000 CSE #39.c, CSE #40.c, CSE #41.c out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB202 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000FF000000F000000000000 CSE #25.c, CSE #26.c, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c out: 00000000000FF000000F00000010000D CSE #01, CSE #02.c, CSE #11, CSE #25.c, CSE #26.c, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c BB203 in: 00000000000FF000000F00000010000D CSE #01, CSE #02.c, CSE #11, CSE #25.c, CSE #26.c, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c gen: 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c out: 00000000000FF000CFFF00300010000D CSE #01, CSE #02.c, CSE #11, CSE #19.c, CSE #25.c, CSE #26.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c BB204 in: 00000000000FF000000F00000010000D CSE #01, CSE #02.c, CSE #11, CSE #25.c, CSE #26.c, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c gen: 00000000000000000000100000000000 CSE #23 out: 00000000000550000005100000100005 CSE #01, CSE #02, CSE #11, CSE #23, CSE #25, CSE #26, CSE #39, CSE #40, CSE #41, CSE #42 BB205 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB206 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB207 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 000000000003F0000000000000000000 CSE #39.c, CSE #40.c, CSE #41.c out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB208 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000C0000000000000000000C CSE #02.c, CSE #42.c out: 00000000000C0000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #42.c BB209 in: 00000000000C0000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #42.c gen: 000000000003F0000000000000000000 CSE #39.c, CSE #40.c, CSE #41.c out: 00000000000FF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c BB210 in: 00000000000FF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c gen: 0000000003FC00000000000000000000 CSE #42.c, CSE #43.c, CSE #44.c, CSE #45.c out: 0000000003FFF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c, CSE #43.c, CSE #44.c, CSE #45.c BB211 in: 0000000003FFF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c, CSE #43.c, CSE #44.c, CSE #45.c gen: 00000000000000000000000000000000 out: 0000000003FFF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c, CSE #43.c, CSE #44.c, CSE #45.c BB212 in: 00000000000C0000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #42.c gen: 00000000000000000000000000000000 out: 00000000000C0000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #42.c BB213 in: 00000000000FF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c gen: 000000000003F0000000000000000000 CSE #39.c, CSE #40.c, CSE #41.c out: 00000000000FF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c BB214 in: 00000000000FF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c gen: 0000000003FC00000000000000000000 CSE #42.c, CSE #43.c, CSE #44.c, CSE #45.c out: 0000000003FFF000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c, CSE #42.c, CSE #43.c, CSE #44.c, CSE #45.c BB215 in: 00000000000C0000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #42.c gen: 0000000000000000000F000000000000 CSE #25.c, CSE #26.c out: 00000000000C0000000F00000010000D CSE #01, CSE #02.c, CSE #11, CSE #25.c, CSE #26.c, CSE #42.c BB216 in: 00000000000C0000000F00000010000D CSE #01, CSE #02.c, CSE #11, CSE #25.c, CSE #26.c, CSE #42.c gen: 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c out: 00000000000C0000CFFF00300010000D CSE #01, CSE #02.c, CSE #11, CSE #19.c, CSE #25.c, CSE #26.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c, CSE #42.c BB217 in: 00000000000C0000000F00000010000D CSE #01, CSE #02.c, CSE #11, CSE #25.c, CSE #26.c, CSE #42.c gen: 00000000000000000000000000000000 out: 00000000000400000005000000100005 CSE #01, CSE #02, CSE #11, CSE #25, CSE #26, CSE #42 BB218 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000000000000000000000000 out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB219 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 0000000000000000000000000000000C CSE #02.c out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB220 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000000000000000000000000 out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB221 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000000000000000000000000 out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB222 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000000000000000000000000 out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB223 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000000000000000000000000 out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB224 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000000000000000000000000 out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB225 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000000000000000000000000 out: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c BB226 in: 000000000003F000000000000010000D CSE #01, CSE #02.c, CSE #11, CSE #39.c, CSE #40.c, CSE #41.c gen: 00000000000000000000000000000000 out: 00000000000150000000000000100005 CSE #01, CSE #02, CSE #11, CSE #39, CSE #40, CSE #41 BB227 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 0000000000000000000F000000000000 CSE #25.c, CSE #26.c out: 0000000000000000000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c BB228 in: 0000000000000000000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c gen: 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c out: 0000000000000000CFFF003000100005 CSE #01, CSE #02, CSE #11, CSE #19.c, CSE #25.c, CSE #26.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c BB229 in: 0000000000000000000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c gen: 00000000000000000000100000000000 CSE #23 out: 00000000000000000005100000100005 CSE #01, CSE #02, CSE #11, CSE #23, CSE #25, CSE #26 BB230 in: 00000000000000000005000000100005 CSE #01, CSE #02, CSE #11, CSE #25, CSE #26 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26 BB231 in: 0000000000000000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26 gen: 000000000C00F0000000000000000000 CSE #39.c, CSE #40.c, CSE #46.c out: 000000000C00F000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39.c, CSE #40.c, CSE #46.c BB232 in: 000000000C00F000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39.c, CSE #40.c, CSE #46.c gen: 000000000C00F0000000000000000000 CSE #39.c, CSE #40.c, CSE #46.c out: 000000000C00F000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39.c, CSE #40.c, CSE #46.c BB233 in: 000000000C00F000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39.c, CSE #40.c, CSE #46.c gen: 000000000C0CF0000000000000000000 CSE #39.c, CSE #40.c, CSE #42.c, CSE #46.c out: 000000000C0CF000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39.c, CSE #40.c, CSE #42.c, CSE #46.c BB234 in: 000000000C0CF000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39.c, CSE #40.c, CSE #42.c, CSE #46.c gen: 00000000000000000000003000000000 CSE #19.c out: 000000000C0CF000000500300010000D CSE #01, CSE #02.c, CSE #11, CSE #19.c, CSE #25, CSE #26, CSE #39.c, CSE #40.c, CSE #42.c, CSE #46.c BB235 in: 000000000C0CF000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39.c, CSE #40.c, CSE #42.c, CSE #46.c gen: 00000000000000000000100000000000 CSE #23 out: 00000000040450000005100000100005 CSE #01, CSE #02, CSE #11, CSE #23, CSE #25, CSE #26, CSE #39, CSE #40, CSE #42, CSE #46 BB236 in: 00000003F4005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47.c, CSE #48.c, CSE #49.c gen: 00000003F00000000000000000000000 CSE #47.c, CSE #48.c, CSE #49.c out: 00000003F4005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47.c, CSE #48.c, CSE #49.c BB237 in: 00000003F4005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47.c, CSE #48.c, CSE #49.c gen: 00000000000000000000003000000000 CSE #19.c out: 00000003F4005000000500300010000D CSE #01, CSE #02.c, CSE #11, CSE #19.c, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47.c, CSE #48.c, CSE #49.c BB238 in: 00000003F4005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47.c, CSE #48.c, CSE #49.c gen: 00000000000000000000100000000000 CSE #23 out: 00000001540050000005100000100005 CSE #01, CSE #02, CSE #11, CSE #23, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47, CSE #48, CSE #49 BB239 in: 00000000040050000005000000100005 CSE #01, CSE #02, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000004005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46 BB240 in: 0000000004005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46 gen: 00000003F00000000000000000000000 CSE #47.c, CSE #48.c, CSE #49.c out: 00000003F4005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47.c, CSE #48.c, CSE #49.c BB241 in: 00000003F4005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47.c, CSE #48.c, CSE #49.c gen: 00000000000000000000000000000000 out: 00000003F4005000000500000010000D CSE #01, CSE #02.c, CSE #11, CSE #25, CSE #26, CSE #39, CSE #40, CSE #46, CSE #47.c, CSE #48.c, CSE #49.c BB242 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 0000000000000000000F000000000000 CSE #25.c, CSE #26.c out: 0000000000000000000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c BB243 in: 0000000000000000000F000000100005 CSE #01, CSE #02, CSE #11, CSE #25.c, CSE #26.c gen: 0000000000000000CFF0003000000000 CSE #19.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c out: 0000000000000000CFFF003000100005 CSE #01, CSE #02, CSE #11, CSE #19.c, CSE #25.c, CSE #26.c, CSE #27.c, CSE #28.c, CSE #29.c, CSE #30.c, CSE #32.c BB244 in: 00000000000000000005000000100005 CSE #01, CSE #02, CSE #11, CSE #25, CSE #26 gen: 00000000000000000000100000000000 CSE #23 out: 00000000000000000005100000100005 CSE #01, CSE #02, CSE #11, CSE #23, CSE #25, CSE #26 BB245 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 0000000000000000000000000000000C CSE #02.c out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB246 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB247 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB248 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB249 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB250 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB251 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 BB252 in: 0000000000000000000000000010000D CSE #01, CSE #02.c, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 BB253 in: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 gen: 00000000000000000000000000000000 out: 00000000000000000000000000100005 CSE #01, CSE #02, CSE #11 Labeling the CSEs with Use/Def information BB01 [002558] Def of CSE #01 [weight=1 ] BB01 [002561] Def of CSE #02 [weight=1 ] BB06 [002594] Def of CSE #11 [weight=1 ] BB07 [002601] Use of CSE #01 [weight=8 ] *** Now Live Across Call *** BB07 [003621] Use of CSE #02 [weight=8 ] *** Now Live Across Call *** BB17 [001432] Def of CSE #03 [weight=8 ] BB20 [001379] Def of CSE #03 [weight=8 ] BB31 [001518] Use of CSE #02 [weight=64 ] BB32 [001444] Def of CSE #04 [weight=64 ] BB32 [001447] Def of CSE #05 [weight=64 ] BB32 [001449] Def of CSE #06 [weight=64 ] BB33 [001463] Use of CSE #04 [weight=64 ] BB33 [001466] Use of CSE #05 [weight=64 ] BB33 [001468] Use of CSE #06 [weight=64 ] BB35 [001522] Use of CSE #02 [weight=8 ] BB36 [001243] Def of CSE #07 [weight=8 ] BB36 [001246] Def of CSE #08 [weight=8 ] BB36 [001248] Def of CSE #09 [weight=8 ] BB37 [001254] Def of CSE #10 [weight=8 ] BB38 [001526] Use of CSE #02 [weight=8 ] BB39 [001343] Def of CSE #07 [weight=8 ] BB39 [001346] Def of CSE #08 [weight=8 ] BB39 [001348] Def of CSE #09 [weight=8 ] BB40 [001270] Def of CSE #10 [weight=8 ] BB40 [001530] Use of CSE #02 [weight=8 ] BB41 [001279] Def of CSE #07 [weight=8 ] BB41 [001282] Def of CSE #08 [weight=8 ] BB41 [001284] Def of CSE #09 [weight=8 ] BB42 [001332] Use of CSE #07 [weight=8 ] BB42 [001335] Use of CSE #08 [weight=8 ] BB42 [001337] Use of CSE #09 [weight=8 ] BB43 [001291] Use of CSE #10 [weight=8 ] BB44 [001534] Use of CSE #02 [weight=64 ] BB47 [001538] Use of CSE #02 [weight=64 ] BB61 [002627] Use of CSE #01 [weight=4 ] BB61 [002625] Use of CSE #11 [weight=4 ] *** Now Live Across Call *** BB74 [000137] Def of CSE #12 [weight=0.50] BB76 [000142] Use of CSE #12 [weight=0.50] BB77 [000150] Use of CSE #12 [weight=0.50] BB80 [000959] Def of CSE #13 [weight=0.50] BB81 [002661] Use of CSE #13 [weight=0.50] BB81 [002667] Def of CSE #16 [weight=0.50] BB93 [002691] Def of CSE #14 [weight=2 ] BB93 [001608] Def of CSE #15 [weight=2 ] BB98 [002720] Use of CSE #14 [weight=2 ] *** Now Live Across Call *** BB98 [001720] Use of CSE #15 [weight=2 ] *** Now Live Across Call *** BB101 [002732] Use of CSE #13 [weight=2 ] *** Now Live Across Call *** BB101 [002738] Def of CSE #16 [weight=2 ] BB107 [001740] Def of CSE #17 [weight=0.50] BB109 [002760] Def of CSE #19 [weight=0.50] BB109 [002767] Use of CSE #17 [weight=0.50] BB111 [002780] Def of CSE #21 [weight=0.50] BB112 [002783] Use of CSE #01 [weight=1 ] BB118 [000831] Def of CSE #18 [weight=8 ] BB120 [000850] Use of CSE #18 [weight=8 ] BB122 [002805] Def of CSE #19 [weight=8 ] BB123 [002812] Def of CSE #23 [weight=8 ] BB129 [001853] Def of CSE #20 [weight=8 ] BB131 [002827] Def of CSE #19 [weight=8 ] BB131 [002834] Use of CSE #20 [weight=8 ] BB132 [002847] Def of CSE #21 [weight=8 ] BB150 [000644] Def of CSE #22 [weight=2 ] BB154 [000658] Use of CSE #22 [weight=2 ] BB157 [001903] Def of CSE #25 [weight=2 ] BB157 [001942] Def of CSE #26 [weight=2 ] BB158 [002863] Def of CSE #19 [weight=2 ] BB158 [001923] Def of CSE #27 [weight=2 ] BB158 [001928] Def of CSE #28 [weight=2 ] BB158 [001925] Def of CSE #29 [weight=2 ] BB158 [001927] Def of CSE #30 [weight=2 ] BB158 [001937] Def of CSE #32 [weight=2 ] BB159 [002870] Def of CSE #23 [weight=2 ] BB165 [001956] Def of CSE #24 [weight=2 ] BB167 [002885] Def of CSE #19 [weight=2 ] BB167 [002892] Use of CSE #24 [weight=2 ] BB168 [002905] Def of CSE #21 [weight=2 ] BB174 [000630] Def of CSE #22 [weight=2 ] BB176 [002012] Def of CSE #25 [weight=2 ] BB176 [002016] Def of CSE #31 [weight=2 ] BB177 [002062] Def of CSE #26 [weight=2 ] BB178 [002919] Def of CSE #19 [weight=2 ] BB178 [002038] Def of CSE #27 [weight=2 ] BB178 [002043] Def of CSE #28 [weight=2 ] BB178 [002040] Def of CSE #29 [weight=2 ] BB178 [002042] Def of CSE #30 [weight=2 ] BB178 [002926] Use of CSE #31 [weight=2 ] BB178 [002055] Def of CSE #32 [weight=2 ] BB179 [002939] Def of CSE #21 [weight=2 ] BB182 [002072] Def of CSE #25 [weight=2 ] BB182 [002076] Def of CSE #33 [weight=2 ] BB183 [002122] Def of CSE #26 [weight=2 ] BB184 [002952] Def of CSE #19 [weight=2 ] BB184 [002098] Def of CSE #27 [weight=2 ] BB184 [002103] Def of CSE #28 [weight=2 ] BB184 [002100] Def of CSE #29 [weight=2 ] BB184 [002102] Def of CSE #30 [weight=2 ] BB184 [002959] Use of CSE #33 [weight=2 ] BB184 [002115] Def of CSE #32 [weight=2 ] BB185 [002972] Def of CSE #21 [weight=2 ] BB187 [002132] Def of CSE #25 [weight=2 ] BB187 [002136] Def of CSE #34 [weight=2 ] BB188 [002182] Def of CSE #26 [weight=2 ] BB189 [002986] Def of CSE #19 [weight=2 ] BB189 [002158] Def of CSE #27 [weight=2 ] BB189 [002163] Def of CSE #28 [weight=2 ] BB189 [002160] Def of CSE #29 [weight=2 ] BB189 [002162] Def of CSE #30 [weight=2 ] BB189 [002993] Use of CSE #34 [weight=2 ] BB189 [002175] Def of CSE #32 [weight=2 ] BB190 [003006] Def of CSE #21 [weight=2 ] BB191 [000808] Def of CSE #38 [weight=8 ] BB191 [000814] Use of CSE #35 [weight=8 ] BB191 [000817] Use of CSE #36 [weight=8 ] BB191 [000819] Use of CSE #37 [weight=8 ] BB192 [003018] Def of CSE #19 [weight=8 ] BB193 [003025] Def of CSE #23 [weight=8 ] BB194 [002234] Use of CSE #02 [weight=16 ] BB195 [000783] Def of CSE #35 [weight=16 ] BB195 [000786] Def of CSE #36 [weight=16 ] BB195 [000788] Def of CSE #37 [weight=16 ] BB196 [000794] Use of CSE #35 [weight=16 ] BB196 [000797] Use of CSE #36 [weight=16 ] BB196 [000799] Use of CSE #37 [weight=16 ] BB197 [002238] Use of CSE #02 [weight=2 ] BB198 [000767] Def of CSE #35 [weight=2 ] BB198 [000770] Def of CSE #36 [weight=2 ] BB198 [000772] Def of CSE #37 [weight=2 ] BB199 [000778] Def of CSE #38 [weight=2 ] BB200 [002242] Use of CSE #02 [weight=2 ] BB201 [000292] Def of CSE #39 [weight=2 ] BB201 [000295] Def of CSE #40 [weight=2 ] BB201 [000297] Def of CSE #41 [weight=2 ] BB202 [000306] Def of CSE #42 [weight=2 ] BB202 [000312] Use of CSE #39 [weight=2 ] BB202 [000315] Use of CSE #40 [weight=2 ] BB202 [000317] Use of CSE #41 [weight=2 ] BB202 [002244] Def of CSE #25 [weight=2 ] BB202 [002286] Def of CSE #26 [weight=2 ] BB203 [003037] Def of CSE #19 [weight=2 ] BB203 [002265] Def of CSE #27 [weight=2 ] BB203 [002270] Def of CSE #28 [weight=2 ] BB203 [002267] Def of CSE #29 [weight=2 ] BB203 [002269] Def of CSE #30 [weight=2 ] BB203 [002279] Def of CSE #32 [weight=2 ] BB204 [003044] Def of CSE #23 [weight=2 ] BB206 [002292] Use of CSE #02 [weight=2 ] BB207 [000567] Def of CSE #39 [weight=2 ] BB207 [000570] Def of CSE #40 [weight=2 ] BB207 [000572] Def of CSE #41 [weight=2 ] BB208 [000428] Def of CSE #42 [weight=2 ] BB208 [002296] Use of CSE #02 [weight=2 ] BB209 [000540] Def of CSE #39 [weight=2 ] BB209 [000543] Def of CSE #40 [weight=2 ] BB209 [000545] Def of CSE #41 [weight=2 ] BB210 [000552] Use of CSE #42 [weight=2 ] BB210 [000553] Def of CSE #43 [weight=2 ] BB210 [000556] Def of CSE #44 [weight=2 ] BB210 [000558] Def of CSE #45 [weight=2 ] BB213 [000449] Use of CSE #39 [weight=2 ] BB213 [000452] Use of CSE #40 [weight=2 ] BB213 [000454] Use of CSE #41 [weight=2 ] BB214 [000461] Use of CSE #42 [weight=2 ] BB214 [000462] Def of CSE #43 [weight=2 ] BB214 [000465] Def of CSE #44 [weight=2 ] BB214 [000467] Def of CSE #45 [weight=2 ] BB215 [002302] Def of CSE #25 [weight=2 ] BB215 [002341] Def of CSE #26 [weight=2 ] BB216 [003058] Def of CSE #19 [weight=2 ] BB216 [002322] Def of CSE #27 [weight=2 ] BB216 [002327] Def of CSE #28 [weight=2 ] BB216 [002324] Def of CSE #29 [weight=2 ] BB216 [002326] Def of CSE #30 [weight=2 ] BB216 [002336] Def of CSE #32 [weight=2 ] BB219 [002347] Use of CSE #02 [weight=16 ] BB227 [002349] Def of CSE #25 [weight=2 ] BB227 [002388] Def of CSE #26 [weight=2 ] BB228 [003081] Def of CSE #19 [weight=2 ] BB228 [002369] Def of CSE #27 [weight=2 ] BB228 [002374] Def of CSE #28 [weight=2 ] BB228 [002371] Def of CSE #29 [weight=2 ] BB228 [002373] Def of CSE #30 [weight=2 ] BB228 [002383] Def of CSE #32 [weight=2 ] BB229 [003088] Def of CSE #23 [weight=2 ] BB230 [002394] Use of CSE #02 [weight=2 ] BB231 [000345] Def of CSE #39 [weight=2 ] BB231 [000348] Def of CSE #40 [weight=2 ] BB231 [000350] Def of CSE #46 [weight=2 ] BB232 [000410] Use of CSE #39 [weight=2 ] BB232 [000413] Use of CSE #40 [weight=2 ] BB232 [000415] Use of CSE #46 [weight=2 ] BB233 [000359] Def of CSE #42 [weight=2 ] BB233 [000365] Use of CSE #39 [weight=2 ] BB233 [000368] Use of CSE #40 [weight=2 ] BB233 [000370] Use of CSE #46 [weight=2 ] BB234 [003100] Def of CSE #19 [weight=2 ] BB235 [003107] Def of CSE #23 [weight=2 ] BB236 [000401] Use of CSE #47 [weight=8 ] BB236 [000404] Use of CSE #48 [weight=8 ] BB236 [000406] Use of CSE #49 [weight=8 ] BB237 [003119] Def of CSE #19 [weight=8 ] BB238 [003126] Def of CSE #23 [weight=8 ] BB239 [002490] Use of CSE #02 [weight=16 ] BB240 [000381] Def of CSE #47 [weight=16 ] BB240 [000384] Def of CSE #48 [weight=16 ] BB240 [000386] Def of CSE #49 [weight=16 ] BB242 [002492] Def of CSE #25 [weight=2 ] BB242 [002531] Def of CSE #26 [weight=2 ] BB243 [003138] Def of CSE #19 [weight=2 ] BB243 [002512] Def of CSE #27 [weight=2 ] BB243 [002517] Def of CSE #28 [weight=2 ] BB243 [002514] Def of CSE #29 [weight=2 ] BB243 [002516] Def of CSE #30 [weight=2 ] BB243 [002526] Def of CSE #32 [weight=2 ] BB244 [003145] Def of CSE #23 [weight=2 ] BB245 [002537] Use of CSE #02 [weight=8 ] ************ Trees at start of optValnumCSE_Heuristic() ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N007 ( 14, 14) [002563] -A--------- * COMMA void $VN.Void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N001 ( 3, 4) CSE #01 (def)[002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N006 ( 7, 7) [002562] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N004 ( 3, 4) CSE #02 (def)[002561] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) CSE #11 (def)[002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 3, 4) [002606] -A--------- * COMMA void $580 N003 ( 3, 4) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 3, 4) CSE #01 (use)[002601] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 3, 4) [003623] ----------- * COMMA void N001 ( 3, 4) CSE #02 (use)[003621] -------H--- +--* LCL_FLD int V02 arg2 u:1[+8] $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) CSE #03 (def)[001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) CSE #03 (def)[001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 7, 8) [001441] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 3, 4) CSE #02 (use)[001518] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N010 ( 13, 15) [001452] ---XG------ * JTRUE void $876 N009 ( 11, 13) [001451] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #06 (def)[001449] ---XG------ +--* IND ushort N006 ( 6, 8) [001448] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #05 (def)[001447] ----------- | \--* LSH long $3df N003 ( 2, 3) CSE #04 (def)[001444] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N010 ( 13, 14) [001471] ---XG------ * JTRUE void $876 N009 ( 11, 12) [001470] N--XG--N-U- \--* NE int N007 ( 9, 10) CSE #06 (use)[001468] ---XG------ +--* IND ushort N006 ( 6, 8) [001467] -------N--- | \--* ADD long $3e0 N001 ( 1, 1) [001453] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #05 (use)[001466] ----------- | \--* LSH long $3df N003 ( 2, 3) CSE #04 (use)[001463] ----------- | +--* CAST long <- int $3de N002 ( 1, 1) [001462] ----------- | | \--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N004 ( 1, 2) [001465] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 7, 8) [001240] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) CSE #02 (use)[001522] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N010 ( 13, 15) [001251] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001250] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #09 (def)[001248] ---XG------ +--* IND ushort N006 ( 6, 8) [001247] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (def)[001246] ----------- | \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (def)[001243] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) CSE #10 (def)[001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 7, 8) [001267] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 3, 4) CSE #02 (use)[001526] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N010 ( 13, 15) [001351] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001350] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #09 (def)[001348] ---XG------ +--* IND ushort N006 ( 6, 8) [001347] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (def)[001346] ----------- | \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (def)[001343] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 9, 11) [001276] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) CSE #10 (def)[001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) CSE #02 (use)[001530] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N010 ( 13, 15) [001287] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001286] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #09 (def)[001284] ---XG------ +--* IND ushort N006 ( 6, 8) [001283] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (def)[001282] ----------- | \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (def)[001279] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N010 ( 13, 15) [001340] ---XG------ * JTRUE void $311 N009 ( 11, 13) [001339] N--XG--N-U- \--* NE int N007 ( 9, 10) CSE #09 (use)[001337] ---XG------ +--* IND ushort N006 ( 6, 8) [001336] -------N--- | \--* ADD long $3ca N001 ( 1, 1) [001330] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (use)[001335] ----------- | \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (use)[001332] ----------- | +--* CAST long <- int $3c8 N002 ( 1, 1) [001331] ----------- | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001334] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) CSE #10 (use)[001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 7, 8) [001315] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 3, 4) CSE #02 (use)[001534] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 7, 8) [000079] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 3, 4) CSE #02 (use)[001538] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] D--XG--N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 23, 23) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 23, 23) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 6, 8) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 3, 4) CSE #01 (use)[002627] ----------- ofs 0 | +--* LCL_FLD byref V02 arg2 u:1[+0] $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) CSE #11 (use)[002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool $301 N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int $301 N004 ( 4, 3) [000104] D--XG--N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N007 ( 8, 7) [000140] ---XG------ * JTRUE void $301 N006 ( 6, 5) [000139] J--XG--N--- \--* GT int N004 ( 4, 3) CSE #12 (def)[000137] ---XG------ +--* IND int N003 ( 3, 4) [002636] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N006 ( 8, 6) [000144] -A-XG---R-- * ASG int $301 N005 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N004 ( 4, 3) CSE #12 (use)[000142] ---XG------ \--* IND int N003 ( 3, 4) [002638] -------N--- \--* ADD byref $24a N001 ( 1, 1) [000141] ----------- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002637] ----------- \--* CNS_INT long 4 $207 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N008 ( 6, 5) [000154] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N006 ( 6, 5) [000152] ---XG------ \--* SUB int N004 ( 4, 3) CSE #12 (use)[000150] ---XG------ +--* IND int N003 ( 3, 4) [002640] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000149] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002639] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) CSE #13 (def)[000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 $c0 N003 ( 3, 3) CSE #13 (use)[002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) CSE #16 (def)[002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [373..39A) -> BB93 (always), preds={BB90} succs={BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ------------ BB92 [383..384) -> BB94 (always), preds={} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) CSE #14 (def)[002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) CSE #15 (def)[001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (always), preds={BB95} succs={BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ------------ BB97 [391..392) -> BB99 (always), preds={} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) CSE #14 (use)[002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) CSE #15 (use)[001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) CSE #13 (use)[002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) CSE #16 (def)[002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) CSE #17 (def)[001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void $845 N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) CSE #17 (use)[002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001780] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) CSE #21 (def)[002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 3, 4) [002788] -A--------- * COMMA void $588 N003 ( 3, 4) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 3, 4) CSE #01 (use)[002783] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N005 ( 8, 8) [000834] ---XG------ * JTRUE void $c1a N004 ( 6, 6) [000833] J--XG--N--- \--* NE int N002 ( 4, 3) CSE #18 (def)[000831] ---XG------ +--* IND ubyte N001 ( 1, 1) [000830] ----------- | \--* LCL_VAR long V36 loc32 u:7 $904 N003 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N004 ( 4, 3) [000855] -A-XG---R-- * ASG int $c1a N003 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N002 ( 4, 3) CSE #18 (use)[000850] ---XG------ \--* IND ubyte N001 ( 1, 1) [000849] ----------- \--* LCL_VAR long V61 tmp21 u:1 (last use) $904 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001833] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) CSE #23 (def)[002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 7, 8) [001856] ---X------- * JTRUE void N004 ( 5, 6) [001855] N--X---N-U- \--* NE int N002 ( 3, 3) CSE #20 (def)[001853] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N003 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N026 ( 34, 39) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002842] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) CSE #20 (use)[002834] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001883] ----------- | \--* LCL_VAR ref V95 tmp55 u:1 N024 ( 5, 4) [002844] n---GO----- \--* IND ushort N023 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N022 ( 1, 1) [002839] -------N--- \--* ADD byref N020 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N021 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001893] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) CSE #21 (def)[002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) CSE #22 (def)[000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) CSE #22 (use)[000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) CSE #25 (def)[001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) CSE #26 (def)[001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) CSE #27 (def)[001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) CSE #28 (def)[001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) CSE #30 (def)[001927] ----------- | \--* LSH long N010 ( 2, 3) CSE #29 (def)[001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001938] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) CSE #32 (def)[001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) CSE #23 (def)[002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) CSE #24 (def)[001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) CSE #24 (use)[002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001996] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) CSE #21 (def)[002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) CSE #22 (def)[000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) CSE #25 (def)[002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) CSE #31 (def)[002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) CSE #26 (def)[002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) CSE #27 (def)[002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) CSE #28 (def)[002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) CSE #30 (def)[002042] ----------- | \--* LSH long N010 ( 2, 3) CSE #29 (def)[002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) CSE #31 (use)[002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002056] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) CSE #32 (def)[002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) CSE #21 (def)[002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) CSE #25 (def)[002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) CSE #33 (def)[002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) CSE #26 (def)[002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) CSE #27 (def)[002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) CSE #28 (def)[002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) CSE #30 (def)[002102] ----------- | \--* LSH long N010 ( 2, 3) CSE #29 (def)[002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) CSE #33 (use)[002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002116] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) CSE #32 (def)[002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) CSE #21 (def)[002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) CSE #25 (def)[002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) CSE #34 (def)[002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) CSE #26 (def)[002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) CSE #27 (def)[002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) CSE #28 (def)[002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) CSE #30 (def)[002162] ----------- | \--* LSH long N010 ( 2, 3) CSE #29 (def)[002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) CSE #34 (use)[002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002176] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) CSE #32 (def)[002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) CSE #21 (def)[003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) CSE #38 (def)[000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N009 ( 9, 10) [002225] -A-XG---R-- * ASG ushort $bec N008 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N007 ( 9, 10) CSE #37 (use)[000819] ---XG------ \--* IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long $acc N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #36 (use)[000817] ----------- \--* LSH long $acb N003 ( 2, 3) CSE #35 (use)[000814] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 $204 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002222] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) CSE #23 (def)[003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 7, 8) [000757] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) CSE #02 (use)[002234] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N010 ( 13, 15) [000791] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000790] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #37 (def)[000788] ---XG------ +--* IND ushort N006 ( 6, 8) [000787] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #36 (def)[000786] ----------- | \--* LSH long $acb N003 ( 2, 3) CSE #35 (def)[000783] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N010 ( 13, 14) [000802] ---XG------ * JTRUE void $bec N009 ( 11, 12) [000801] N--XG--N-U- \--* NE int N007 ( 9, 10) CSE #37 (use)[000799] ---XG------ +--* IND ushort N006 ( 6, 8) [000798] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000792] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #36 (use)[000797] ----------- | \--* LSH long $acb N003 ( 2, 3) CSE #35 (use)[000794] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000793] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000796] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 7, 8) [000764] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 3, 4) CSE #02 (use)[002238] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N010 ( 13, 15) [000775] ---XG------ * JTRUE void $bec N009 ( 11, 13) [000774] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #37 (def)[000772] ---XG------ +--* IND ushort N006 ( 6, 8) [000771] -------N--- | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #36 (def)[000770] ----------- | \--* LSH long $acb N003 ( 2, 3) CSE #35 (def)[000767] ----------- | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) CSE #38 (def)[000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 7, 8) [000289] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) CSE #02 (use)[002242] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N010 ( 13, 15) [000300] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000299] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #41 (def)[000297] ---XG------ +--* IND ushort N006 ( 6, 8) [000296] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000295] ----------- | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000292] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) CSE #42 (def)[000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N009 ( 9, 10) [002283] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N007 ( 9, 10) CSE #41 (use)[000317] ---XG------ \--* IND ushort N006 ( 6, 8) [000316] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000302] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (use)[000315] ----------- \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (use)[000312] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000311] ----------- | \--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N004 ( 1, 2) [000314] ----------- \--* CNS_INT long 1 $204 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) CSE #25 (def)[002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) CSE #26 (def)[002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) CSE #27 (def)[002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) CSE #28 (def)[002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) CSE #30 (def)[002269] ----------- | \--* LSH long N010 ( 2, 3) CSE #29 (def)[002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002280] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) CSE #32 (def)[002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) CSE #23 (def)[003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 7, 8) [000425] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) CSE #02 (use)[002292] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N010 ( 13, 15) [000575] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000574] N--XG--N-U- \--* EQ int N007 ( 9, 10) CSE #41 (def)[000572] ---XG------ +--* IND ushort N006 ( 6, 8) [000571] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000570] ----------- | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000567] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 9, 11) [000434] ----------- * JTRUE void $VN.Void N005 ( 7, 9) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) CSE #42 (def)[000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 3, 4) CSE #02 (use)[002296] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N010 ( 13, 15) [000548] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000547] N--XG--N-U- \--* NE int N007 ( 9, 10) CSE #41 (def)[000545] ---XG------ +--* IND ushort N006 ( 6, 8) [000544] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000543] ----------- | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000540] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB213 (cond), preds={BB209} succs={BB211,BB213} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) CSE #45 (def)[000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) CSE #44 (def)[000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) CSE #43 (def)[000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) CSE #42 (use)[000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB212 [6A8..6B5) -> BB215 (always), preds={BB208} succs={BB215} ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209,BB210} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N010 ( 13, 15) [000457] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000456] N--XG--N-U- \--* NE int N007 ( 9, 10) CSE #41 (use)[000454] ---XG------ +--* IND ushort N006 ( 6, 8) [000453] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000447] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (use)[000452] ----------- | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (use)[000449] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000448] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000451] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) CSE #45 (def)[000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) CSE #44 (def)[000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) CSE #43 (def)[000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) CSE #42 (use)[000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) CSE #25 (def)[002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) CSE #26 (def)[002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) CSE #27 (def)[002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) CSE #28 (def)[002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) CSE #30 (def)[002326] ----------- | \--* LSH long N010 ( 2, 3) CSE #29 (def)[002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002337] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) CSE #32 (def)[002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 7, 8) [000485] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 3, 4) CSE #02 (use)[002347] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) CSE #25 (def)[002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) CSE #26 (def)[002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) CSE #27 (def)[002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) CSE #28 (def)[002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) CSE #30 (def)[002373] ----------- | \--* LSH long N010 ( 2, 3) CSE #29 (def)[002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002384] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) CSE #32 (def)[002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) CSE #23 (def)[003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 7, 8) [000342] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 3, 4) CSE #02 (use)[002394] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N010 ( 13, 15) [000353] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000352] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #46 (def)[000350] ---XG------ +--* IND ushort N006 ( 6, 8) [000349] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000348] ----------- | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000345] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N010 ( 13, 15) [000418] ---XG------ * JTRUE void $87a N009 ( 11, 13) [000417] N--XG--N-U- \--* NE int N007 ( 9, 10) CSE #46 (use)[000415] ---XG------ +--* IND ushort N006 ( 6, 8) [000414] -------N--- | \--* ADD long $3e7 N001 ( 1, 1) [000408] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (use)[000413] ----------- | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (use)[000410] ----------- | +--* CAST long <- int $3e5 N002 ( 1, 1) [000409] ----------- | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000412] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) CSE #42 (def)[000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N009 ( 9, 10) [002435] -A-XG---R-- * ASG ushort $87a N008 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N007 ( 9, 10) CSE #46 (use)[000370] ---XG------ \--* IND ushort N006 ( 6, 8) [000369] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000355] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (use)[000368] ----------- \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (use)[000365] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000364] ----------- | \--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N004 ( 1, 2) [000367] ----------- \--* CNS_INT long 1 $204 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002432] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) CSE #23 (def)[003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N009 ( 9, 10) [002481] -A-XG---R-- * ASG ushort $c02 N008 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N007 ( 9, 10) CSE #49 (use)[000406] ---XG------ \--* IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #48 (use)[000404] ----------- \--* LSH long $ad2 N003 ( 2, 3) CSE #47 (use)[000401] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 $204 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002478] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) CSE #23 (def)[003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 7, 8) [000378] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 3, 4) CSE #02 (use)[002490] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N010 ( 13, 15) [000389] ---XG------ * JTRUE void $c02 N009 ( 11, 13) [000388] J--XG--N--- \--* EQ int N007 ( 9, 10) CSE #49 (def)[000386] ---XG------ +--* IND ushort N006 ( 6, 8) [000385] -------N--- | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #48 (def)[000384] ----------- | \--* LSH long $ad2 N003 ( 2, 3) CSE #47 (def)[000381] ----------- | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) CSE #25 (def)[002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) CSE #26 (def)[002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) CSE #19 (def)[003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) CSE #27 (def)[002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) CSE #28 (def)[002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) CSE #30 (def)[002516] ----------- | \--* LSH long N010 ( 2, 3) CSE #29 (def)[002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002527] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) CSE #32 (def)[002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) CSE #23 (def)[003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 7, 8) [000210] ----------- * JTRUE void $VN.Void N003 ( 5, 6) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 3, 4) CSE #02 (use)[002537] ----------- \--* LCL_FLD int V02 arg2 u:1[+8] $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- Aggressive CSE Promotion cutoff is 4900.000000 Moderate CSE Promotion cutoff is 1250.000000 enregCount is 130 Framesize estimate is 0x025C We have a small frame Sorted CSE candidates: CSE #45, {$5c8, $2 } useCnt=0: [def=400.000000, use=0.000000, cost= 11 ] :: N009 ( 11, 13) CSE #45 (def)[000558] ---XG------ * IND ushort CSE #06, {$5c4, $875} useCnt=1: [def=6400.000000, use=6400.000000, cost= 9 ] :: N007 ( 9, 10) CSE #06 (def)[001449] ---XG------ * IND ushort CSE #37, {$5ca, $beb} useCnt=2: [def=1800.000000, use=2400.000000, cost= 9 ] :: N007 ( 9, 10) CSE #37 (use)[000819] ---XG------ * IND ushort CSE #49, {$5cb, $c01} useCnt=1: [def=1600.000000, use=800.000000, cost= 9 ] :: N007 ( 9, 10) CSE #49 (use)[000406] ---XG------ * IND ushort CSE #09, {$5c1, $310} useCnt=1: [def=2400.000000, use=800.000000, cost= 9 ] :: N007 ( 9, 10) CSE #09 (def)[001248] ---XG------ * IND ushort CSE #46, {$5c7, $879} useCnt=2: [def=200.000000, use=400.000000, cost= 9 ] :: N007 ( 9, 10) CSE #46 (def)[000350] ---XG------ * IND ushort CSE #41, {$5c6, $879} useCnt=2: [def=600.000000, use=400.000000, cost= 9 ] :: N007 ( 9, 10) CSE #41 (def)[000297] ---XG------ * IND ushort CSE #44, {$3f5, $2 } useCnt=0: [def=400.000000, use=0.000000, cost= 6 ] :: N007 ( 6, 9) CSE #44 (def)[000556] ----------- * LSH long $3f5 CSE #05, {$3df, $2 } useCnt=1: [def=6400.000000, use=6400.000000, cost= 4 ] :: N005 ( 4, 6) CSE #05 (def)[001447] ----------- * LSH long $3df CSE #36, {$acb, $2 } useCnt=2: [def=1800.000000, use=2400.000000, cost= 4 ] :: N005 ( 4, 6) CSE #36 (use)[000817] ----------- * LSH long $acb CSE #18, {$406, $c19} useCnt=1: [def=800.000000, use=800.000000, cost= 4 ] :: N002 ( 4, 3) CSE #18 (def)[000831] ---XG------ * IND ubyte CSE #40, {$3e6, $2 } useCnt=4: [def=800.000000, use=800.000000, cost= 4 ] :: N005 ( 4, 6) CSE #40 (def)[000295] ----------- * LSH long $3e6 CSE #48, {$ad2, $2 } useCnt=1: [def=1600.000000, use=800.000000, cost= 4 ] :: N005 ( 4, 6) CSE #48 (use)[000404] ----------- * LSH long $ad2 CSE #08, {$3c9, $2 } useCnt=1: [def=2400.000000, use=800.000000, cost= 4 ] :: N005 ( 4, 6) CSE #08 (def)[001246] ----------- * LSH long $3c9 CSE #22, {$404, $a26} useCnt=1: [def=400.000000, use=200.000000, cost= 4 ] :: N002 ( 4, 3) CSE #22 (def)[000644] ---XG------ * IND ubyte CSE #12, {$294, $300} useCnt=2: [def=50.000000, use=100.000000, cost= 4 ] :: N004 ( 4, 3) CSE #12 (def)[000137] ---XG------ * IND int CSE #43, {$3f4, $2 } useCnt=0: [def=400.000000, use=0.000000, cost= 4 ] :: N005 ( 4, 6) CSE #43 (def)[000553] ----------- * CAST long <- int $3f4 CSE #25, {$2b6, $2 } useCnt=0: [def=1600.000000, use=0.000000, cost= 4 ] :: N004 ( 4, 3) CSE #25 (def)[001903] ---XG------ * IND int CSE #26, {$2b7, $2 } useCnt=0: [def=1600.000000, use=0.000000, cost= 4 ] :: N005 ( 4, 3) CSE #26 (def)[001942] ---XG------ * IND int CSE #27, {$2b8, $2 } useCnt=0: [def=1600.000000, use=0.000000, cost= 4 ] :: N005 ( 4, 3) CSE #27 (def)[001923] ---XG------ * IND int CSE #30, {$3ea, $2 } useCnt=0: [def=1600.000000, use=0.000000, cost= 4 ] :: N012 ( 4, 6) CSE #30 (def)[001927] ----------- * LSH long CSE #02, {$342, $2 } useCnt=16: [def=100.000000, use=29000.000000, cost= 3, call] :: N004 ( 3, 4) CSE #02 (def)[002561] ----------- * LCL_FLD int V02 arg2 u:1[+8] $342 CSE #01, {$246, $2 } useCnt=3: [def=100.000000, use=1300.000000, cost= 3, call] :: N001 ( 3, 4) CSE #01 (def)[002558] ----------- * LCL_FLD byref V02 arg2 u:1[+0] $246 CSE #20, {$c89, $c38} useCnt=1: [def=800.000000, use=800.000000, cost= 3 ] :: N002 ( 3, 3) CSE #20 (def)[001853] ---X------- * ARR_LENGTH int CSE #10, {$371, $2 } useCnt=1: [def=1600.000000, use=800.000000, cost= 3 ] :: N003 ( 3, 4) CSE #10 (def)[001254] ----------- * ADD int $371 CSE #42, {$952, $2 } useCnt=2: [def=600.000000, use=400.000000, cost= 3 ] :: N003 ( 3, 4) CSE #42 (def)[000306] ----------- * ADD int $952 CSE #13, {$2c9, $322} useCnt=2: [def=50.000000, use=250.000000, cost= 3, call] :: N002 ( 3, 3) CSE #13 (def)[000959] ---X------- * ARR_LENGTH int CSE #14, {$253, $2 } useCnt=1: [def=200.000000, use=200.000000, cost= 3, call] :: N003 ( 3, 4) CSE #14 (def)[002691] -----O----- * ADD byref $253 CSE #15, {$2cc, $2 } useCnt=1: [def=200.000000, use=200.000000, cost= 3, call] :: N002 ( 3, 3) CSE #15 (def)[001608] ---X------- * ARR_LENGTH int $2cc CSE #24, {$2ef, $a3b} useCnt=1: [def=200.000000, use=200.000000, cost= 3 ] :: N002 ( 3, 3) CSE #24 (def)[001956] ---X------- * ARR_LENGTH int CSE #31, {$2f4, $b68} useCnt=1: [def=200.000000, use=200.000000, cost= 3 ] :: N002 ( 3, 3) CSE #31 (def)[002016] ---X------- * ARR_LENGTH int CSE #33, {$2da, $992} useCnt=1: [def=200.000000, use=200.000000, cost= 3 ] :: N002 ( 3, 3) CSE #33 (def)[002076] ---X------- * ARR_LENGTH int CSE #34, {$2f9, $bcb} useCnt=1: [def=200.000000, use=200.000000, cost= 3 ] :: N002 ( 3, 3) CSE #34 (def)[002136] ---X------- * ARR_LENGTH int CSE #17, {$2d0, $846} useCnt=1: [def=50.000000, use=50.000000, cost= 3 ] :: N002 ( 3, 3) CSE #17 (def)[001740] ---X------- * ARR_LENGTH int CSE #16, {$24e, $2 } useCnt=0: [def=250.000000, use=0.000000, cost= 3 ] :: N007 ( 3, 4) CSE #16 (def)[002667] ----------- * ADD byref CSE #38, {$bad, $2 } useCnt=0: [def=1000.000000, use=0.000000, cost= 3 ] :: N003 ( 3, 4) CSE #38 (def)[000808] ----------- * ADD int $bad CSE #03, {$68f, $2 } useCnt=0: [def=1600.000000, use=0.000000, cost= 3 ] :: N003 ( 3, 4) CSE #03 (def)[001432] ----------- * ADD int $68f CSE #28, {$387, $2 } useCnt=0: [def=1600.000000, use=0.000000, cost= 3 ] :: N008 ( 3, 2) CSE #28 (def)[001928] ---XG------ * IND byref CSE #32, {$961, $2 } useCnt=0: [def=1600.000000, use=0.000000, cost= 3 ] :: N003 ( 3, 4) CSE #32 (def)[001937] ----------- * ADD int CSE #19, {$25c, $2 } useCnt=0: [def=5250.000000, use=0.000000, cost= 3 ] :: N003 ( 3, 4) CSE #19 (def)[002760] -----O----- * ADD byref $25c CSE #04, {$3de, $2 } useCnt=1: [def=6400.000000, use=6400.000000, cost= 2 ] :: N003 ( 2, 3) CSE #04 (def)[001444] ----------- * CAST long <- int $3de CSE #35, {$aca, $2 } useCnt=2: [def=1800.000000, use=2400.000000, cost= 2 ] :: N003 ( 2, 3) CSE #35 (use)[000814] ----------- * CAST long <- int $aca CSE #39, {$3e5, $2 } useCnt=4: [def=800.000000, use=800.000000, cost= 2 ] :: N003 ( 2, 3) CSE #39 (def)[000292] ----------- * CAST long <- int $3e5 CSE #47, {$ad1, $2 } useCnt=1: [def=1600.000000, use=800.000000, cost= 2 ] :: N003 ( 2, 3) CSE #47 (use)[000401] ----------- * CAST long <- int $ad1 CSE #07, {$3c8, $2 } useCnt=1: [def=2400.000000, use=800.000000, cost= 2 ] :: N003 ( 2, 3) CSE #07 (def)[001243] ----------- * CAST long <- int $3c8 CSE #11, {$43 , $2 } useCnt=1: [def=100.000000, use=400.000000, cost= 2, call] :: N005 ( 2, 8) CSE #11 (def)[002594] H---------- * CNS_INT(h) long 0x40000000005401e8 ftn $43 CSE #29, {$3e8, $2 } useCnt=0: [def=1600.000000, use=0.000000, cost= 2 ] :: N010 ( 2, 3) CSE #29 (def)[001925] ---------U- * CAST long <- uint CSE #21, {$4f , $2 } useCnt=0: [def=1650.000000, use=0.000000, cost= 2 ] :: N003 ( 2, 8) CSE #21 (def)[002780] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn $4f CSE #23, {$53 , $2 } useCnt=0: [def=3400.000000, use=0.000000, cost= 2 ] :: N003 ( 2, 8) CSE #23 (def)[002812] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 Skipped CSE #45 because use count is 0 Considering CSE #06 {$5c4, $875} [def=6400.000000, use=6400.000000, cost= 9 ] CSE Expression : N007 ( 9, 10) CSE #06 (def)[001449] ---XG------ * IND ushort N006 ( 6, 8) [001448] -------N--- \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #05 (def)[001447] ----------- \--* LSH long $3df N003 ( 2, 3) CSE #04 (def)[001444] ----------- +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- \--* CNS_INT long 1 $204 Aggressive CSE Promotion (19200.000000 >= 4900.000000) cseRefCnt=19200.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=6400.000000, useCnt=6400.000000, cost=9, size=10 def_cost=1, use_cost=1, extra_no_cost=18, extra_yes_cost=0 CSE cost savings check (57618.000000 >= 12800.000000) passes Promoting CSE: lvaGrabTemp returning 171 (V171 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #06 is single-def, so associated CSE temp V171 will be in SSA New refCnts for V171: refCnt = 2, refCntWtd = 128 New refCnts for V171: refCnt = 3, refCntWtd = 192 CSE #06 def at [001449] replaced in BB32 with def of V171 optValnumCSE morphed tree: N014 ( 14, 16) [001452] -A-XG------ * JTRUE void $876 N013 ( 12, 14) [001451] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003627] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #06 (def)[003625] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N007 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #05 (def)[001447] ----------- | | \--* LSH long $3df N003 ( 2, 3) CSE #04 (def)[001444] ----------- | | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N012 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 Working on the replacement of the CSE #06 use at [001468] in BB33 Unmark CSE use #05 at [001466]: 1 -> 0 Unmark CSE use #04 at [001463]: 1 -> 0 optValnumCSE morphed tree: N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 N003 ( 3, 3) [001470] N---G--N-U- \--* NE int N001 ( 1, 1) [003628] ----------- +--* LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 Considering CSE #37 {$5ca, $beb} [def=1800.000000, use=2400.000000, cost= 9 ] CSE Expression : N007 ( 9, 10) CSE #37 (use)[000819] ---XG------ * IND ushort N006 ( 6, 8) [000818] -------N--- \--* ADD long $acc N001 ( 1, 1) [000804] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #36 (use)[000817] ----------- \--* LSH long $acb N003 ( 2, 3) CSE #35 (use)[000814] ----------- +--* CAST long <- int $aca N002 ( 1, 1) [000813] ----------- | \--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N004 ( 1, 2) [000816] ----------- \--* CNS_INT long 1 $204 Aggressive CSE Promotion (6000.000000 >= 4900.000000) cseRefCnt=6000.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=1800.000000, useCnt=2400.000000, cost=9, size=10 def_cost=1, use_cost=1, extra_no_cost=36, extra_yes_cost=0 CSE cost savings check (21636.000000 >= 4200.000000) passes Promoting CSE: lvaGrabTemp returning 172 (V172 rat0) (a long lifetime temp) called for CSE - aggressive. New refCnts for V172: refCnt = 2, refCntWtd = 24 New refCnts for V172: refCnt = 3, refCntWtd = 40 New refCnts for V172: refCnt = 4, refCntWtd = 56 New refCnts for V172: refCnt = 5, refCntWtd = 58 New refCnts for V172: refCnt = 6, refCntWtd = 60 Working on the replacement of the CSE #37 use at [000819] in BB191 Unmark CSE use #36 at [000817]: 2 -> 1 Unmark CSE use #35 at [000814]: 2 -> 1 optValnumCSE morphed tree: N003 ( 1, 3) [002225] -A--G---R-- * ASG ushort $bec N002 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N001 ( 1, 1) [003629] ----------- \--* LCL_VAR int V172 cse1 CSE #37 def at [000788] replaced in BB195 with def of V172 optValnumCSE morphed tree: N014 ( 14, 16) [000791] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000790] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003633] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #37 (def)[003631] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003630] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000788] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000787] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #36 (def)[000786] ----------- | | \--* LSH long $acb N003 ( 2, 3) CSE #35 (def)[000783] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003632] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 Working on the replacement of the CSE #37 use at [000799] in BB196 Unmark CSE use #36 at [000797]: 1 -> 0 Unmark CSE use #35 at [000794]: 1 -> 0 optValnumCSE morphed tree: N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec N003 ( 3, 3) [000801] N---G--N-U- \--* NE int N001 ( 1, 1) [003634] ----------- +--* LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 CSE #37 def at [000772] replaced in BB198 with def of V172 optValnumCSE morphed tree: N014 ( 14, 16) [000775] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000774] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003638] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #37 (def)[003636] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003635] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000772] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000771] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #36 (def)[000770] ----------- | | \--* LSH long $acb N003 ( 2, 3) CSE #35 (def)[000767] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003637] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 Considering CSE #49 {$5cb, $c01} [def=1600.000000, use=800.000000, cost= 9 ] CSE Expression : N007 ( 9, 10) CSE #49 (use)[000406] ---XG------ * IND ushort N006 ( 6, 8) [000405] -------N--- \--* ADD long $ad3 N001 ( 1, 1) [000391] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #48 (use)[000404] ----------- \--* LSH long $ad2 N003 ( 2, 3) CSE #47 (use)[000401] ----------- +--* CAST long <- int $ad1 N002 ( 1, 1) [000400] ----------- | \--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N004 ( 1, 2) [000403] ----------- \--* CNS_INT long 1 $204 Moderate CSE Promotion (CSE never live at call) (4000.000000 >= 1250.000000) cseRefCnt=4000.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=1600.000000, useCnt=800.000000, cost=9, size=10 def_cost=2, use_cost=1, extra_no_cost=18, extra_yes_cost=0 CSE cost savings check (7218.000000 >= 4000.000000) passes Promoting CSE: lvaGrabTemp returning 173 (V173 rat0) (a long lifetime temp) called for CSE - moderate. CSE #49 is single-def, so associated CSE temp V173 will be in SSA New refCnts for V173: refCnt = 2, refCntWtd = 24 New refCnts for V173: refCnt = 3, refCntWtd = 40 Working on the replacement of the CSE #49 use at [000406] in BB236 Unmark CSE use #48 at [000404]: 1 -> 0 Unmark CSE use #47 at [000401]: 1 -> 0 optValnumCSE morphed tree: N003 ( 1, 3) [002481] -A--G---R-- * ASG ushort $c02 N002 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N001 ( 1, 1) [003639] ----------- \--* LCL_VAR int V173 cse2 u:1 CSE #49 def at [000386] replaced in BB240 with def of V173 optValnumCSE morphed tree: N014 ( 14, 16) [000389] -A-XG------ * JTRUE void $c02 N013 ( 12, 14) [000388] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003643] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #49 (def)[003641] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003640] D------N--- | | +--* LCL_VAR int V173 cse2 d:1 $VN.Void N007 ( 9, 10) [000386] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000385] -------N--- | | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #48 (def)[000384] ----------- | | \--* LSH long $ad2 N003 ( 2, 3) CSE #47 (def)[000381] ----------- | | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003642] ----------- | \--* LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 Considering CSE #09 {$5c1, $310} [def=2400.000000, use=800.000000, cost= 9 ] CSE Expression : N007 ( 9, 10) CSE #09 (def)[001248] ---XG------ * IND ushort N006 ( 6, 8) [001247] -------N--- \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (def)[001246] ----------- \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (def)[001243] ----------- +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- \--* CNS_INT long 1 $204 Aggressive CSE Promotion (5600.000000 >= 4900.000000) cseRefCnt=5600.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=2400.000000, useCnt=800.000000, cost=9, size=10 def_cost=1, use_cost=1, extra_no_cost=18, extra_yes_cost=0 CSE cost savings check (7218.000000 >= 3200.000000) passes Promoting CSE: lvaGrabTemp returning 174 (V174 rat0) (a long lifetime temp) called for CSE - aggressive. New refCnts for V174: refCnt = 2, refCntWtd = 16 New refCnts for V174: refCnt = 3, refCntWtd = 24 New refCnts for V174: refCnt = 4, refCntWtd = 32 New refCnts for V174: refCnt = 5, refCntWtd = 40 New refCnts for V174: refCnt = 6, refCntWtd = 48 New refCnts for V174: refCnt = 7, refCntWtd = 56 CSE #09 def at [001248] replaced in BB36 with def of V174 optValnumCSE morphed tree: N014 ( 14, 16) [001251] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001250] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003647] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #09 (def)[003645] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (def)[001246] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (def)[001243] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 CSE #09 def at [001348] replaced in BB39 with def of V174 optValnumCSE morphed tree: N014 ( 14, 16) [001351] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001350] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003651] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #09 (def)[003649] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003648] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001348] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001347] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (def)[001346] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (def)[001343] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003650] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 CSE #09 def at [001284] replaced in BB41 with def of V174 optValnumCSE morphed tree: N014 ( 14, 16) [001287] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001286] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003655] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #09 (def)[003653] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003652] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001284] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001283] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) CSE #08 (def)[001282] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) CSE #07 (def)[001279] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003654] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 Working on the replacement of the CSE #09 use at [001337] in BB42 Unmark CSE use #08 at [001335]: 1 -> 0 Unmark CSE use #07 at [001332]: 1 -> 0 optValnumCSE morphed tree: N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 N003 ( 3, 4) [001339] N---G--N-U- \--* NE int N001 ( 1, 1) [003656] ----------- +--* LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da Considering CSE #46 {$5c7, $879} [def=200.000000, use=400.000000, cost= 9 ] CSE Expression : N007 ( 9, 10) CSE #46 (def)[000350] ---XG------ * IND ushort N006 ( 6, 8) [000349] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000348] ----------- \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000345] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- \--* CNS_INT long 1 $204 Conservative CSE Promotion (not enregisterable) (800.000000 < 1250.000000) cseRefCnt=800.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=200.000000, useCnt=400.000000, cost=9, size=10 def_cost=2, use_cost=2, extra_no_cost=32, extra_yes_cost=0 CSE cost savings check (3632.000000 >= 1200.000000) passes Promoting CSE: lvaGrabTemp returning 175 (V175 rat0) (a long lifetime temp) called for CSE - conservative. CSE #46 is single-def, so associated CSE temp V175 will be in SSA New refCnts for V175: refCnt = 2, refCntWtd = 4 New refCnts for V175: refCnt = 3, refCntWtd = 6 New refCnts for V175: refCnt = 4, refCntWtd = 8 CSE #46 def at [000350] replaced in BB231 with def of V175 optValnumCSE morphed tree: N014 ( 14, 16) [000353] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000352] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003660] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #46 (def)[003658] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003657] D------N--- | | +--* LCL_VAR int V175 cse4 d:1 $VN.Void N007 ( 9, 10) [000350] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000349] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000348] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000345] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003659] ----------- | \--* LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 Working on the replacement of the CSE #46 use at [000415] in BB232 Unmark CSE use #40 at [000413]: 4 -> 3 Unmark CSE use #39 at [000410]: 4 -> 3 optValnumCSE morphed tree: N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a N003 ( 3, 4) [000417] N---G--N-U- \--* NE int N001 ( 1, 1) [003661] ----------- +--* LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da Working on the replacement of the CSE #46 use at [000370] in BB233 Unmark CSE use #40 at [000368]: 3 -> 2 Unmark CSE use #39 at [000365]: 3 -> 2 optValnumCSE morphed tree: N003 ( 1, 3) [002435] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N001 ( 1, 1) [003662] ----------- \--* LCL_VAR int V175 cse4 u:1 Considering CSE #41 {$5c6, $879} [def=600.000000, use=400.000000, cost= 9 ] CSE Expression : N007 ( 9, 10) CSE #41 (def)[000297] ---XG------ * IND ushort N006 ( 6, 8) [000296] -------N--- \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000295] ----------- \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000292] ----------- +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- \--* CNS_INT long 1 $204 Moderate CSE Promotion (CSE never live at call) (1600.000000 >= 1250.000000) cseRefCnt=1600.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=600.000000, useCnt=400.000000, cost=9, size=10 def_cost=2, use_cost=1, extra_no_cost=36, extra_yes_cost=0 CSE cost savings check (3636.000000 >= 1600.000000) passes Promoting CSE: lvaGrabTemp returning 176 (V176 rat0) (a long lifetime temp) called for CSE - moderate. New refCnts for V176: refCnt = 2, refCntWtd = 4 New refCnts for V176: refCnt = 3, refCntWtd = 6 New refCnts for V176: refCnt = 4, refCntWtd = 8 New refCnts for V176: refCnt = 5, refCntWtd = 10 New refCnts for V176: refCnt = 6, refCntWtd = 12 New refCnts for V176: refCnt = 7, refCntWtd = 14 New refCnts for V176: refCnt = 8, refCntWtd = 16 CSE #41 def at [000297] replaced in BB201 with def of V176 optValnumCSE morphed tree: N014 ( 14, 16) [000300] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000299] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003666] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #41 (def)[003664] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000295] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000292] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 Working on the replacement of the CSE #41 use at [000317] in BB202 Unmark CSE use #40 at [000315]: 2 -> 1 Unmark CSE use #39 at [000312]: 2 -> 1 optValnumCSE morphed tree: N003 ( 1, 3) [002283] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N001 ( 1, 1) [003667] ----------- \--* LCL_VAR int V176 cse5 CSE #41 def at [000572] replaced in BB207 with def of V176 optValnumCSE morphed tree: N014 ( 14, 16) [000575] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000574] NA-XG--N-U- \--* EQ int N011 ( 10, 11) [003671] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #41 (def)[003669] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003668] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000572] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000571] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000570] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000567] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003670] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 CSE #41 def at [000545] replaced in BB209 with def of V176 optValnumCSE morphed tree: N014 ( 14, 16) [000548] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000547] NA-XG--N-U- \--* NE int N011 ( 10, 11) [003675] -A-XG------ +--* COMMA int N009 ( 9, 10) CSE #41 (def)[003673] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) CSE #40 (def)[000543] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) CSE #39 (def)[000540] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 Working on the replacement of the CSE #41 use at [000454] in BB213 Unmark CSE use #40 at [000452]: 1 -> 0 Unmark CSE use #39 at [000449]: 1 -> 0 optValnumCSE morphed tree: N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a N003 ( 3, 4) [000456] N---G--N-U- \--* NE int N001 ( 1, 1) [003676] ----------- +--* LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da Skipped CSE #44 because use count is 0 Skipped CSE #05 because use count is 0 Skipped CSE #36 because use count is 0 Considering CSE #18 {$406, $c19} [def=800.000000, use=800.000000, cost= 4 ] CSE Expression : N002 ( 4, 3) CSE #18 (def)[000831] ---XG------ * IND ubyte N001 ( 1, 1) [000830] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 Moderate CSE Promotion (CSE never live at call) (2400.000000 >= 1250.000000) cseRefCnt=2400.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=800.000000, useCnt=800.000000, cost=4, size=3 def_cost=2, use_cost=1, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (3204.000000 >= 2400.000000) passes Promoting CSE: lvaGrabTemp returning 177 (V177 rat0) (a long lifetime temp) called for CSE - moderate. CSE #18 is single-def, so associated CSE temp V177 will be in SSA New refCnts for V177: refCnt = 2, refCntWtd = 16 New refCnts for V177: refCnt = 3, refCntWtd = 24 CSE #18 def at [000831] replaced in BB118 with def of V177 optValnumCSE morphed tree: N009 ( 9, 9) [000834] -A-XG------ * JTRUE void $c1a N008 ( 7, 7) [000833] JA-XG--N--- \--* NE int N006 ( 5, 4) [003680] -A-XG------ +--* COMMA int N004 ( 4, 3) CSE #18 (def)[003678] -A-XG---R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003677] D------N--- | | +--* LCL_VAR int V177 cse6 d:1 $VN.Void N002 ( 4, 3) [000831] ---XG------ | | \--* IND ubyte N001 ( 1, 1) [000830] ----------- | | \--* LCL_VAR long V36 loc32 u:7 $904 N005 ( 1, 1) [003679] ----------- | \--* LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 Working on the replacement of the CSE #18 use at [000850] in BB120 optValnumCSE morphed tree: N003 ( 1, 3) [000855] -A--G---R-- * ASG int $c1a N002 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N001 ( 1, 1) [003681] ----------- \--* LCL_VAR int V177 cse6 u:1 Skipped CSE #40 because use count is 0 Skipped CSE #48 because use count is 0 Skipped CSE #08 because use count is 0 Considering CSE #22 {$404, $a26} [def=400.000000, use=200.000000, cost= 4 ] CSE Expression : N002 ( 4, 3) CSE #22 (def)[000644] ---XG------ * IND ubyte N001 ( 1, 1) [000643] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 Conservative CSE Promotion (not enregisterable) (1000.000000 < 1250.000000) cseRefCnt=1000.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=400.000000, useCnt=200.000000, cost=4, size=3 def_cost=2, use_cost=2, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (802.000000 >= 1200.000000) fails Did Not promote this CSE Considering CSE #12 {$294, $300} [def=50.000000, use=100.000000, cost= 4 ] CSE Expression : N004 ( 4, 3) CSE #12 (def)[000137] ---XG------ * IND int N003 ( 3, 4) [002636] -------N--- \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- \--* CNS_INT long 4 $207 Conservative CSE Promotion (not enregisterable) (200.000000 < 1250.000000) cseRefCnt=200.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=50.000000, useCnt=100.000000, cost=4, size=3 def_cost=2, use_cost=2, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (404.000000 >= 300.000000) passes Promoting CSE: lvaGrabTemp returning 178 (V178 rat0) (a long lifetime temp) called for CSE - conservative. CSE #12 is single-def, so associated CSE temp V178 will be in SSA New refCnts for V178: refCnt = 2, refCntWtd = 1 New refCnts for V178: refCnt = 3, refCntWtd = 1.50 New refCnts for V178: refCnt = 4, refCntWtd = 2 CSE #12 def at [000137] replaced in BB74 with def of V178 optValnumCSE morphed tree: N011 ( 15, 12) [000140] -A-XG------ * JTRUE void $301 N010 ( 13, 10) [000139] JA-XG--N--- \--* GT int N008 ( 11, 8) [003685] -A-XG------ +--* COMMA int N006 ( 8, 6) CSE #12 (def)[003683] -A-XG---R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] ---XG------ | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d Working on the replacement of the CSE #12 use at [000142] in BB76 optValnumCSE morphed tree: N003 ( 7, 5) [000144] -A--G---R-- * ASG int $301 N002 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N001 ( 3, 2) [003686] ----------- \--* LCL_VAR int V178 cse7 u:1 Working on the replacement of the CSE #12 use at [000150] in BB77 optValnumCSE morphed tree: N005 ( 5, 4) [000154] -A--G---R-- * ASG int $301 N004 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N003 ( 5, 4) [000152] ----G------ \--* SUB int N001 ( 3, 2) [003687] ----------- +--* LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d Skipped CSE #43 because use count is 0 Skipped CSE #25 because use count is 0 Skipped CSE #26 because use count is 0 Skipped CSE #27 because use count is 0 Skipped CSE #30 because use count is 0 Considering CSE #02 {$342, $2 } [def=100.000000, use=29000.000000, cost= 3, call] CSE Expression : N004 ( 3, 4) CSE #02 (def)[002561] ----------- * LCL_FLD int V02 arg2 u:1[+8] $342 Aggressive CSE Promotion (29200.000000 >= 4900.000000) cseRefCnt=29200.000000, aggressiveRefCnt=4900.000000, moderateRefCnt=1250.000000 defCnt=100.000000, useCnt=29000.000000, cost=3, size=4, LiveAcrossCall def_cost=1, use_cost=1, extra_no_cost=96, extra_yes_cost=0 CSE cost savings check (87096.000000 >= 29100.000000) passes Promoting CSE: lvaGrabTemp returning 179 (V179 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #02 is single-def, so associated CSE temp V179 will be in SSA New refCnts for V179: refCnt = 2, refCntWtd = 2 New refCnts for V179: refCnt = 3, refCntWtd = 10 New refCnts for V179: refCnt = 4, refCntWtd = 74 New refCnts for V179: refCnt = 5, refCntWtd = 82 New refCnts for V179: refCnt = 6, refCntWtd = 90 New refCnts for V179: refCnt = 7, refCntWtd = 98 New refCnts for V179: refCnt = 8, refCntWtd = 162 New refCnts for V179: refCnt = 9, refCntWtd = 226 New refCnts for V179: refCnt = 10, refCntWtd = 242 New refCnts for V179: refCnt = 11, refCntWtd = 244 New refCnts for V179: refCnt = 12, refCntWtd = 246 New refCnts for V179: refCnt = 13, refCntWtd = 248 New refCnts for V179: refCnt = 14, refCntWtd = 250 New refCnts for V179: refCnt = 15, refCntWtd = 266 New refCnts for V179: refCnt = 16, refCntWtd = 268 New refCnts for V179: refCnt = 17, refCntWtd = 284 New refCnts for V179: refCnt = 18, refCntWtd = 292 CSE #02 def at [002561] replaced in BB01 with def of V179 optValnumCSE morphed tree: N011 ( 15, 15) [002563] -A--------- * COMMA void $VN.Void N003 ( 7, 7) [002559] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N001 ( 3, 4) CSE #01 (def)[002558] ----------- | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N010 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N009 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N008 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N006 ( 3, 4) CSE #02 (def)[003689] -A------R-- +--* ASG int $VN.Void N005 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N004 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N007 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [003621] in BB07 optValnumCSE morphed tree: N003 ( 1, 1) [003623] ----------- * COMMA void N001 ( 1, 1) [003692] ----------- +--* LCL_VAR int V179 cse8 u:1 $342 N002 ( 0, 0) [003622] ----------- \--* NOP void Working on the replacement of the CSE #02 use at [001518] in BB31 optValnumCSE morphed tree: N004 ( 5, 5) [001441] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [001522] in BB35 optValnumCSE morphed tree: N004 ( 5, 5) [001240] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [001526] in BB38 optValnumCSE morphed tree: N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [001530] in BB40 optValnumCSE morphed tree: N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) CSE #10 (def)[001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003696] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [001534] in BB44 optValnumCSE morphed tree: N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [001538] in BB47 optValnumCSE morphed tree: N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002234] in BB194 optValnumCSE morphed tree: N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002238] in BB197 optValnumCSE morphed tree: N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002242] in BB200 optValnumCSE morphed tree: N004 ( 5, 5) [000289] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002292] in BB206 optValnumCSE morphed tree: N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002296] in BB208 optValnumCSE morphed tree: N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) CSE #42 (def)[000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003703] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002347] in BB219 optValnumCSE morphed tree: N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002394] in BB230 optValnumCSE morphed tree: N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002490] in BB239 optValnumCSE morphed tree: N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #02 use at [002537] in BB245 optValnumCSE morphed tree: N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Considering CSE #01 {$246, $2 } [def=100.000000, use=1300.000000, cost= 3, call] CSE Expression : N001 ( 3, 4) CSE #01 (def)[002558] ----------- * LCL_FLD byref V02 arg2 u:1[+0] $246 Moderate CSE Promotion (CSE is live across a call) (1500.000000 >= 1300.000000) cseRefCnt=1500.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1300.000000 defCnt=100.000000, useCnt=1300.000000, cost=3, size=4, LiveAcrossCall def_cost=2, use_cost=2, extra_no_cost=12, extra_yes_cost=0 CSE cost savings check (3912.000000 >= 2800.000000) passes Promoting CSE: lvaGrabTemp returning 180 (V180 rat0) (a long lifetime temp) called for CSE - moderate. CSE #01 is single-def, so associated CSE temp V180 will be in SSA New refCnts for V180: refCnt = 2, refCntWtd = 2 New refCnts for V180: refCnt = 3, refCntWtd = 10 New refCnts for V180: refCnt = 4, refCntWtd = 14 New refCnts for V180: refCnt = 5, refCntWtd = 15 CSE #01 def at [002558] replaced in BB01 with def of V180 optValnumCSE morphed tree: N015 ( 16, 16) [002563] -A--------- * COMMA void $VN.Void N007 ( 8, 8) [002559] -A------R-- +--* ASG byref $VN.Void N006 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N005 ( 4, 5) [003711] -A--------- | \--* COMMA byref $246 N003 ( 3, 4) CSE #01 (def)[003709] -A------R-- | +--* ASG byref $VN.Void N002 ( 1, 1) [003708] D------N--- | | +--* LCL_VAR byref V180 cse9 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 1, 1) [003710] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N014 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N013 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N012 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N010 ( 3, 4) CSE #02 (def)[003689] -A------R-- +--* ASG int $VN.Void N009 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N008 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N011 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 Working on the replacement of the CSE #01 use at [002601] in BB07 optValnumCSE morphed tree: N005 ( 1, 3) [002606] -A--------- * COMMA void $580 N003 ( 1, 3) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 1, 1) [003712] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 Working on the replacement of the CSE #01 use at [002627] in BB61 ReMorphing args for 1159.CALL: Args for [001159].CALL after fgMorphArgs: CallArg[[002625].CNS_INT long (By value), 1 reg: x11, byteAlignment=8, isLate, processed, wellKnown[R2RIndirectionCell]] CallArg[[002626].FIELD_LIST struct (By value), 2 regs: x0 x1, byteAlignment=8, isLate, processed, isStruct] CallArg[[001158].CNS_INT int (By value), 1 reg: x2, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 optValnumCSE morphed tree: N008 ( 21, 20) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 21, 20) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 4, 5) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 1, 1) [003713] ----------- ofs 0 | +--* LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) CSE #11 (use)[002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 Working on the replacement of the CSE #01 use at [002783] in BB112 optValnumCSE morphed tree: N005 ( 1, 3) [002788] -A--------- * COMMA void $588 N003 ( 1, 3) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 1, 1) [003714] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 Considering CSE #20 {$c89, $c38} [def=800.000000, use=800.000000, cost= 3 ] CSE Expression : N002 ( 3, 3) CSE #20 (def)[001853] ---X------- * ARR_LENGTH int N001 ( 1, 1) [001852] ----------- \--* LCL_VAR ref V95 tmp55 u:1 Moderate CSE Promotion (CSE never live at call) (2400.000000 >= 1350.000000) cseRefCnt=2400.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=800.000000, useCnt=800.000000, cost=3, size=3 def_cost=2, use_cost=1, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (2404.000000 >= 2400.000000) passes Promoting CSE: lvaGrabTemp returning 181 (V181 rat0) (a long lifetime temp) called for CSE - moderate. CSE #20 is single-def, so associated CSE temp V181 will be in SSA New refCnts for V181: refCnt = 2, refCntWtd = 16 New refCnts for V181: refCnt = 3, refCntWtd = 24 CSE #20 def at [001853] replaced in BB129 with def of V181 optValnumCSE morphed tree: N009 ( 8, 9) [001856] -A-X------- * JTRUE void N008 ( 6, 7) [001855] NA-X---N-U- \--* NE int N006 ( 4, 4) [003718] -A-X------- +--* COMMA int N004 ( 3, 3) CSE #20 (def)[003716] -A-X----R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 Working on the replacement of the CSE #20 use at [002834] in BB131 optValnumCSE morphed tree: N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d Considering CSE #10 {$371, $2 } [def=1600.000000, use=800.000000, cost= 3 ] CSE Expression : N003 ( 3, 4) CSE #10 (def)[001254] ----------- * ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 Moderate CSE Promotion (CSE never live at call) (4000.000000 >= 1350.000000) cseRefCnt=4000.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=1600.000000, useCnt=800.000000, cost=3, size=4 def_cost=2, use_cost=1, extra_no_cost=6, extra_yes_cost=0 CSE cost savings check (2406.000000 >= 4000.000000) fails Did Not promote this CSE Considering CSE #42 {$952, $2 } [def=600.000000, use=400.000000, cost= 3 ] CSE Expression : N003 ( 3, 4) CSE #42 (def)[000306] ----------- * ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 Moderate CSE Promotion (CSE never live at call) (1600.000000 >= 1350.000000) cseRefCnt=1600.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=600.000000, useCnt=400.000000, cost=3, size=4 def_cost=2, use_cost=1, extra_no_cost=12, extra_yes_cost=0 CSE cost savings check (1212.000000 >= 1600.000000) fails Did Not promote this CSE Considering CSE #13 {$2c9, $322} [def=50.000000, use=250.000000, cost= 3, call] CSE Expression : N002 ( 3, 3) CSE #13 (def)[000959] ---X------- * ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 Conservative CSE Promotion (350.000000 < 1350.000000) cseRefCnt=350.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=50.000000, useCnt=250.000000, cost=3, size=3, LiveAcrossCall def_cost=2, use_cost=3, extra_no_cost=0, extra_yes_cost=0 CSE cost savings check (750.000000 >= 850.000000) fails Did Not promote this CSE Considering CSE #14 {$253, $2 } [def=200.000000, use=200.000000, cost= 3, call] CSE Expression : N003 ( 3, 4) CSE #14 (def)[002691] -----O----- * ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 Conservative CSE Promotion (600.000000 < 1350.000000) cseRefCnt=600.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=200.000000, useCnt=200.000000, cost=3, size=4, LiveAcrossCall def_cost=2, use_cost=3, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (602.000000 >= 1000.000000) fails Did Not promote this CSE Considering CSE #15 {$2cc, $2 } [def=200.000000, use=200.000000, cost= 3, call] CSE Expression : N002 ( 3, 3) CSE #15 (def)[001608] ---X------- * ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 Conservative CSE Promotion (600.000000 < 1350.000000) cseRefCnt=600.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=200.000000, useCnt=200.000000, cost=3, size=3, LiveAcrossCall def_cost=2, use_cost=3, extra_no_cost=0, extra_yes_cost=0 CSE cost savings check (600.000000 >= 1000.000000) fails Did Not promote this CSE Considering CSE #24 {$2ef, $a3b} [def=200.000000, use=200.000000, cost= 3 ] CSE Expression : N002 ( 3, 3) CSE #24 (def)[001956] ---X------- * ARR_LENGTH int N001 ( 1, 1) [001955] ----------- \--* LCL_VAR ref V102 tmp62 u:1 Conservative CSE Promotion (not enregisterable) (600.000000 < 1350.000000) cseRefCnt=600.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=200.000000, useCnt=200.000000, cost=3, size=3 def_cost=2, use_cost=2, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (602.000000 >= 800.000000) fails Did Not promote this CSE Considering CSE #31 {$2f4, $b68} [def=200.000000, use=200.000000, cost= 3 ] CSE Expression : N002 ( 3, 3) CSE #31 (def)[002016] ---X------- * ARR_LENGTH int N001 ( 1, 1) [002015] ----------- \--* LCL_VAR ref V106 tmp66 u:1 Conservative CSE Promotion (not enregisterable) (600.000000 < 1350.000000) cseRefCnt=600.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=200.000000, useCnt=200.000000, cost=3, size=3 def_cost=2, use_cost=2, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (602.000000 >= 800.000000) fails Did Not promote this CSE Considering CSE #33 {$2da, $992} [def=200.000000, use=200.000000, cost= 3 ] CSE Expression : N002 ( 3, 3) CSE #33 (def)[002076] ---X------- * ARR_LENGTH int N001 ( 1, 1) [002075] ----------- \--* LCL_VAR ref V110 tmp70 u:1 Conservative CSE Promotion (not enregisterable) (600.000000 < 1350.000000) cseRefCnt=600.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=200.000000, useCnt=200.000000, cost=3, size=3 def_cost=2, use_cost=2, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (602.000000 >= 800.000000) fails Did Not promote this CSE Considering CSE #34 {$2f9, $bcb} [def=200.000000, use=200.000000, cost= 3 ] CSE Expression : N002 ( 3, 3) CSE #34 (def)[002136] ---X------- * ARR_LENGTH int N001 ( 1, 1) [002135] ----------- \--* LCL_VAR ref V114 tmp74 u:1 Conservative CSE Promotion (not enregisterable) (600.000000 < 1350.000000) cseRefCnt=600.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=200.000000, useCnt=200.000000, cost=3, size=3 def_cost=2, use_cost=2, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (602.000000 >= 800.000000) fails Did Not promote this CSE Considering CSE #17 {$2d0, $846} [def=50.000000, use=50.000000, cost= 3 ] CSE Expression : N002 ( 3, 3) CSE #17 (def)[001740] ---X------- * ARR_LENGTH int N001 ( 1, 1) [001739] ----------- \--* LCL_VAR ref V86 tmp46 u:1 Conservative CSE Promotion (not enregisterable) (150.000000 < 1350.000000) cseRefCnt=150.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=50.000000, useCnt=50.000000, cost=3, size=3 def_cost=2, use_cost=2, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (152.000000 >= 200.000000) fails Did Not promote this CSE Skipped CSE #16 because use count is 0 Skipped CSE #38 because use count is 0 Skipped CSE #03 because use count is 0 Skipped CSE #28 because use count is 0 Skipped CSE #32 because use count is 0 Skipped CSE #19 because use count is 0 Skipped CSE #04 because use count is 0 Skipped CSE #35 because use count is 0 Skipped CSE #39 because use count is 0 Skipped CSE #47 because use count is 0 Skipped CSE #07 because use count is 0 Considering CSE #11 {$43 , $2 } [def=100.000000, use=400.000000, cost= 2, call] CSE Expression : N005 ( 2, 8) CSE #11 (def)[002594] H---------- * CNS_INT(h) long 0x40000000005401e8 ftn $43 Conservative CSE Promotion (600.000000 < 1350.000000) cseRefCnt=600.000000, aggressiveRefCnt=5000.000000, moderateRefCnt=1350.000000 defCnt=100.000000, useCnt=400.000000, cost=2, size=8, LiveAcrossCall def_cost=2, use_cost=3, extra_no_cost=10, extra_yes_cost=0 CSE cost savings check (810.000000 >= 1400.000000) fails Did Not promote this CSE Skipped CSE #29 because use count is 0 Skipped CSE #21 because use count is 0 Skipped CSE #23 because use count is 0 *************** Finishing PHASE Optimize Valnum CSEs Trees after Optimize Valnum CSEs ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 (always) i hascall bwd BB92 [0219] 0 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 (always) i gcsafe bwd BB97 [0242] 0 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB213 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 1 BB208 2 3 [6A8..6B5)-> BB215 (always) i bwd BB213 [0169] 2 BB209,BB210 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] ---XG------ | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N015 ( 16, 16) [002563] -A--------- * COMMA void $VN.Void N007 ( 8, 8) [002559] -A------R-- +--* ASG byref $VN.Void N006 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N005 ( 4, 5) [003711] -A--------- | \--* COMMA byref $246 N003 ( 3, 4) [003709] -A------R-- | +--* ASG byref $VN.Void N002 ( 1, 1) [003708] D------N--- | | +--* LCL_VAR byref V180 cse9 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 1, 1) [003710] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N014 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N013 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N012 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N010 ( 3, 4) [003689] -A------R-- +--* ASG int $VN.Void N009 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N008 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N011 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] ---XG------ +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 1, 3) [002606] -A--------- * COMMA void $580 N003 ( 1, 3) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 1, 1) [003712] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 1, 1) [003623] ----------- * COMMA void N001 ( 1, 1) [003692] ----------- +--* LCL_VAR int V179 cse8 u:1 $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 5, 5) [001441] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N014 ( 14, 16) [001452] -A-XG------ * JTRUE void $876 N013 ( 12, 14) [001451] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003627] -A-XG------ +--* COMMA int N009 ( 9, 10) [003625] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N007 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N012 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 N003 ( 3, 3) [001470] N---G--N-U- \--* NE int N001 ( 1, 1) [003628] ----------- +--* LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 5, 5) [001240] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N014 ( 14, 16) [001251] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001250] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003647] -A-XG------ +--* COMMA int N009 ( 9, 10) [003645] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N014 ( 14, 16) [001351] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001350] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003651] -A-XG------ +--* COMMA int N009 ( 9, 10) [003649] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003648] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001348] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001347] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003650] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003696] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N014 ( 14, 16) [001287] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001286] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003655] -A-XG------ +--* COMMA int N009 ( 9, 10) [003653] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003652] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001284] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001283] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003654] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 N003 ( 3, 4) [001339] N---G--N-U- \--* NE int N001 ( 1, 1) [003656] ----------- +--* LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] D--XG--N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] ---XG------ +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] ---XG------ | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 21, 20) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 21, 20) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 4, 5) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 1, 1) [003713] ----------- ofs 0 | +--* LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] ---XG------ +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool $301 N004 ( 5, 4) [001124] D--XG--N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int $301 N004 ( 4, 3) [000104] D--XG--N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N011 ( 15, 12) [000140] -A-XG------ * JTRUE void $301 N010 ( 13, 10) [000139] JA-XG--N--- \--* GT int N008 ( 11, 8) [003685] -A-XG------ +--* COMMA int N006 ( 8, 6) [003683] -A-XG---R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] ---XG------ | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N003 ( 7, 5) [000144] -A--G---R-- * ASG int $301 N002 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N001 ( 3, 2) [003686] ----------- \--* LCL_VAR int V178 cse7 u:1 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N005 ( 5, 4) [000154] -A--G---R-- * ASG int $301 N004 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N003 ( 5, 4) [000152] ----G------ \--* SUB int N001 ( 3, 2) [003687] ----------- +--* LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 1) [002652] ----------- \--* LCL_VAR int V152 tmp112 u:1 (last use) $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] ---XG------ \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001099] ----------- | +--* LCL_VAR int V27 loc23 u:1 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [373..39A) -> BB93 (always), preds={BB90} succs={BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ------------ BB92 [383..384) -> BB94 (always), preds={} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (always), preds={BB95} succs={BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ------------ BB97 [391..392) -> BB99 (always), preds={} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] ---XG------ +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] ---XG------ +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void $845 N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] ---XG------ \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] ---XG------ | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] ---XG------ | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001780] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 1, 3) [002788] -A--------- * COMMA void $588 N003 ( 1, 3) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 1, 1) [003714] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N009 ( 9, 9) [000834] -A-XG------ * JTRUE void $c1a N008 ( 7, 7) [000833] JA-XG--N--- \--* NE int N006 ( 5, 4) [003680] -A-XG------ +--* COMMA int N004 ( 4, 3) [003678] -A-XG---R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003677] D------N--- | | +--* LCL_VAR int V177 cse6 d:1 $VN.Void N002 ( 4, 3) [000831] ---XG------ | | \--* IND ubyte N001 ( 1, 1) [000830] ----------- | | \--* LCL_VAR long V36 loc32 u:7 $904 N005 ( 1, 1) [003679] ----------- | \--* LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N003 ( 1, 3) [000855] -A--G---R-- * ASG int $c1a N002 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N001 ( 1, 1) [003681] ----------- \--* LCL_VAR int V177 cse6 u:1 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] ---XG------ \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] ---XG------ | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] ---XG------ | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001833] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] ---XG------ \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N009 ( 8, 9) [001856] -A-X------- * JTRUE void N008 ( 6, 7) [001855] NA-X---N-U- \--* NE int N006 ( 4, 4) [003718] -A-X------- +--* COMMA int N004 ( 3, 3) [003716] -A-X----R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] ---XG------ \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] ---XG------ | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] ---XG------ | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001893] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] ---XG------ \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] ---XG------ | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] ---XG------ | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001938] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] ---XG------ \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] ---XG------ \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] ---XG------ | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] ---XG------ | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001996] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] ---XG------ \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] ---XG------ | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] ---XG------ | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002056] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] ---XG------ \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] ---XG------ | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] ---XG------ | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002116] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] ---XG------ \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] ---XG------ | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] ---XG------ | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002176] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N003 ( 1, 3) [002225] -A--G---R-- * ASG ushort $bec N002 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N001 ( 1, 1) [003629] ----------- \--* LCL_VAR int V172 cse1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] ---XG------ \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] ---XG------ | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] ---XG------ | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002222] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N014 ( 14, 16) [000791] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000790] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003633] -A-XG------ +--* COMMA int N009 ( 9, 10) [003631] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003630] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000788] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000787] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003632] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec N003 ( 3, 3) [000801] N---G--N-U- \--* NE int N001 ( 1, 1) [003634] ----------- +--* LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N014 ( 14, 16) [000775] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000774] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003638] -A-XG------ +--* COMMA int N009 ( 9, 10) [003636] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003635] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000772] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000771] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003637] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 5, 5) [000289] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N014 ( 14, 16) [000300] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000299] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003666] -A-XG------ +--* COMMA int N009 ( 9, 10) [003664] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N003 ( 1, 3) [002283] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N001 ( 1, 1) [003667] ----------- \--* LCL_VAR int V176 cse5 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] ---XG------ \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] ---XG------ | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] ---XG------ | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002280] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N014 ( 14, 16) [000575] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000574] NA-XG--N-U- \--* EQ int N011 ( 10, 11) [003671] -A-XG------ +--* COMMA int N009 ( 9, 10) [003669] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003668] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000572] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000571] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003670] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003703] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N014 ( 14, 16) [000548] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000547] NA-XG--N-U- \--* NE int N011 ( 10, 11) [003675] -A-XG------ +--* COMMA int N009 ( 9, 10) [003673] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB213 (cond), preds={BB209} succs={BB211,BB213} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB212 [6A8..6B5) -> BB215 (always), preds={BB208} succs={BB215} ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209,BB210} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a N003 ( 3, 4) [000456] N---G--N-U- \--* NE int N001 ( 1, 1) [003676] ----------- +--* LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] ---XG------ \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] ---XG------ | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] ---XG------ | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002337] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] ---XG------ +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] ---XG------ \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] ---XG------ | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] ---XG------ | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002384] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N014 ( 14, 16) [000353] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000352] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003660] -A-XG------ +--* COMMA int N009 ( 9, 10) [003658] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003657] D------N--- | | +--* LCL_VAR int V175 cse4 d:1 $VN.Void N007 ( 9, 10) [000350] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000349] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003659] ----------- | \--* LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a N003 ( 3, 4) [000417] N---G--N-U- \--* NE int N001 ( 1, 1) [003661] ----------- +--* LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N003 ( 1, 3) [002435] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N001 ( 1, 1) [003662] ----------- \--* LCL_VAR int V175 cse4 u:1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] ---XG------ \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] ---XG------ \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] ---XG------ | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] ---XG------ | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002432] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N003 ( 1, 3) [002481] -A--G---R-- * ASG ushort $c02 N002 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N001 ( 1, 1) [003639] ----------- \--* LCL_VAR int V173 cse2 u:1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] ---XG------ \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] ---XG------ \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] ---XG------ | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] ---XG------ | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002478] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N014 ( 14, 16) [000389] -A-XG------ * JTRUE void $c02 N013 ( 12, 14) [000388] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003643] -A-XG------ +--* COMMA int N009 ( 9, 10) [003641] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003640] D------N--- | | +--* LCL_VAR int V173 cse2 d:1 $VN.Void N007 ( 9, 10) [000386] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000385] -------N--- | | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003642] ----------- | \--* LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] ---XG------ \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] ---XG------ | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] ---XG------ | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002527] D--XG--N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] ---XG------ +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] ---XG------ +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [info] NumUses overestimated for V00.1: IR 80 SSA 108 [info] NumUses overestimated for V01.1: IR 15 SSA 21 [info] NumUses overestimated for V02.1: IR 3 SSA 23 [info] NumUses overestimated for V15.2: IR 4 SSA 5 [info] NumUses overestimated for V16.2: IR 2 SSA 3 [info] NumUses overestimated for V16.4: IR 2 SSA 3 [info] NumUses overestimated for V16.5: IR 17 SSA 22 [info] NumUses overestimated for V16.6: IR 4 SSA 5 [info] NumUses overestimated for V16.13: IR 7 SSA 9 [info] NumUses overestimated for V16.17: IR 11 SSA 12 [info] NumUses overestimated for V16.21: IR 4 SSA 5 [info] NumUses overestimated for V22.1: IR 7 SSA 9 [info] NumUses overestimated for V28.2: IR 2 SSA 3 [info] NumUses overestimated for V33.1: IR 4 SSA 10 [info] NumUses overestimated for V34.1: IR 11 SSA 18 [info] NumUses overestimated for V36.3: IR 6 SSA 7 [info] NumUses overestimated for V36.7: IR 4 SSA 5 [info] NumUses overestimated for V50.1: IR 1 SSA 2 [info] NumUses overestimated for V51.1: IR 1 SSA 2 [info] NumUses overestimated for V52.1: IR 1 SSA 2 [info] NumUses overestimated for V53.1: IR 1 SSA 2 [info] NumUses overestimated for V54.1: IR 1 SSA 2 [info] NumUses overestimated for V59.1: IR 1 SSA 2 [info] NumUses overestimated for V60.1: IR 0 SSA 2 [info] HasGlobalUse overestimated for V60.1 [info] NumUses overestimated for V61.1: IR 1 SSA 2 [info] NumUses overestimated for V62.1: IR 0 SSA 7 [info] HasGlobalUse overestimated for V62.1 [info] NumUses overestimated for V72.1: IR 1 SSA 2 [info] NumUses overestimated for V73.1: IR 1 SSA 2 [info] NumUses overestimated for V74.1: IR 1 SSA 2 [info] NumUses overestimated for V95.1: IR 4 SSA 5 [info] NumUses overestimated for V167.1: IR 1 SSA 2 SSA checks completed successfully *************** In fgDebugCheckLoopTable Disabling SSA checking before assertion prop *************** Starting PHASE Assertion prop GenTreeNode creates assertion: N005 ( 4, 3) [001503] ---XG------ * IND int In BB01 New Global Constant Assertion: ($101,$0) Value_Number {InitVal($c1)} is not 0, index = #01 GenTreeNode creates assertion: N006 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng void In BB01 New Global ArrBnds Assertion: ($0,$0) [idx: {IntCns 0};len: {MemOpaque:NotInLoop}] in range , index = #02 GenTreeNode creates assertion: N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void In BB11 New Global Constant Assertion: ($363,$d2) V18.05 == 69, index = #03 GenTreeNode creates assertion: N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void In BB11 New Global Constant Assertion: ($363,$d2) V18.05 != 69, index = #04 GenTreeNode creates assertion: N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void In BB13 New Global Constant Assertion: ($363,$d3) V18.05 == 92, index = #05 GenTreeNode creates assertion: N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void In BB13 New Global Constant Assertion: ($363,$d3) V18.05 != 92, index = #06 GenTreeNode creates assertion: N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void In BB14 New Global Constant Assertion: ($363,$d4) V18.05 == 101, index = #07 GenTreeNode creates assertion: N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void In BB14 New Global Constant Assertion: ($363,$d4) V18.05 != 101, index = #08 GenTreeNode creates assertion: N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void In BB15 New Global Constant Assertion: ($363,$d5) V18.05 != 8240, index = #09 GenTreeNode creates assertion: N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void In BB15 New Global Constant Assertion: ($363,$d5) V18.05 == 8240, index = #10 GenTreeNode creates assertion: N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void In BB18 New Global Constant Assertion: ($284,$c9) V06.02 != 2147483647, index = #11 GenTreeNode creates assertion: N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void In BB18 New Global Constant Assertion: ($284,$c9) V06.02 == 2147483647, index = #12 GenTreeNode creates assertion: N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void In BB21 New Global Constant Assertion: ($690,$c0) Const_Loop_Bnd {GE($286, $c0)} is not {IntCns 0}, index = #13 GenTreeNode creates assertion: N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void In BB21 New Global Constant Assertion: ($690,$c0) Const_Loop_Bnd {GE($286, $c0)} is {IntCns 0}, index = #14 GenTreeNode creates assertion: N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void In BB23 New Global Constant Assertion: ($691,$c0) Const_Loop_Bnd {LE($28a, $c0)} is not {IntCns 0}, index = #15 GenTreeNode creates assertion: N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void In BB23 New Global Constant Assertion: ($691,$c0) Const_Loop_Bnd {LE($28a, $c0)} is {IntCns 0}, index = #16 GenTreeNode creates assertion: N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void In BB25 New Global Constant Assertion: ($692,$c0) Const_Loop_Bnd {LT($287, $c0)} is not {IntCns 0}, index = #17 GenTreeNode creates assertion: N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void In BB25 New Global Constant Assertion: ($692,$c0) Const_Loop_Bnd {LT($287, $c0)} is {IntCns 0}, index = #18 GenTreeNode creates assertion: N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void In BB26 New Global Copy Assertion: ($287,$28a) V10.02 != V04.02, index = #19 GenTreeNode creates assertion: N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void In BB26 New Global Copy Assertion: ($287,$28a) V10.02 == V04.02, index = #20 GenTreeNode creates assertion: N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void In BB48 New Global Constant Assertion: ($363,$c0) V18.05 == 0, index = #21 GenTreeNode creates assertion: N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void In BB48 New Global Constant Assertion: ($363,$c0) V18.05 != 0, index = #22 GenTreeNode creates assertion: N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void In BB49 New Global Constant Assertion: ($363,$d1) V18.05 != 59, index = #23 GenTreeNode creates assertion: N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void In BB49 New Global Constant Assertion: ($363,$d1) V18.05 == 59, index = #24 GenTreeNode creates assertion: N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void In BB53 New Global Copy Assertion: ($287,$28d) V10.02 != V05.02, index = #25 GenTreeNode creates assertion: N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void In BB53 New Global Copy Assertion: ($287,$28d) V10.02 == V05.02, index = #26 GenTreeNode creates assertion: N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void In BB57 New Global Constant Assertion: ($4c1,$c0) V09.02 != 0, index = #27 GenTreeNode creates assertion: N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void In BB57 New Global Constant Assertion: ($4c1,$c0) V09.02 == 0, index = #28 GenTreeNode creates assertion: N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void In BB61 New Global Copy Assertion: ($2c4,$283) V16.16 == V15.16, index = #29 GenTreeNode creates assertion: N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void In BB61 New Global Copy Assertion: ($2c4,$283) V16.16 != V15.16, index = #30 After constant propagation on [002652]: STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void [003720] ----------- \--* CNS_INT int 4 $c8 optVNAssertionPropCurStmt morphed tree: N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 2) [003720] ----------- \--* CNS_INT int 4 $c8 GenTreeNode creates assertion: N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void In BB78 New Global Constant Assertion: ($4c4,$c0) V12.03 == 0, index = #31 GenTreeNode creates assertion: N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void In BB78 New Global Constant Assertion: ($4c4,$c0) V12.03 != 0, index = #32 GenTreeNode creates assertion: N004 ( 4, 3) [001570] ---XG------ * IND ref In BB79 New Global Constant Assertion: ($180,$0) V03.01 != null, index = #33 GenTreeNode creates assertion: N008 ( 10, 10) [000947] ---XG------ * JTRUE void In BB79 New Global Constant Assertion: ($70e,$c0) Loop_Bnd { {IntCns 0} GE {ARR_LENGTH($187)}} is not {IntCns 0}, index = #34 GenTreeNode creates assertion: N008 ( 10, 10) [000947] ---XG------ * JTRUE void In BB79 New Global Constant Assertion: ($70e,$c0) Loop_Bnd { {IntCns 0} GE {ARR_LENGTH($187)}} is {IntCns 0}, index = #35 GenTreeNode creates assertion: N002 ( 3, 3) [000959] ---X------- * ARR_LENGTH int In BB80 New Global Constant Assertion: ($18b,$0) V26.01 != null, index = #36 GenTreeNode creates assertion: N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void In BB80 New Global Constant Assertion: ($2ca,$c0) V29.01 == 0, index = #37 GenTreeNode creates assertion: N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void In BB80 New Global Constant Assertion: ($2ca,$c0) V29.01 != 0, index = #38 After constant propagation on [001099]: STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void [003721] ----------- | +--* CNS_INT int 0 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 N008 ( 1, 1) [002660] ----------- | \--* LCL_VAR int V27 loc23 u:1 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a After constant propagation on [002660]: STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void [003721] ----------- | +--* CNS_INT int 0 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 N009 ( 2, 3) [002663] ---------U- +--* CAST long <- uint $205 [003722] ----------- | \--* CNS_INT int 0 $c0 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a After constant propagation on [002663]: STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void [003721] ----------- | +--* CNS_INT int 0 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002665] ----------- \--* LSH long $205 [003723] ----------- +--* CNS_INT long 0 $205 N010 ( 1, 2) [002664] -------N--- \--* CNS_INT long 2 $20a After constant propagation on [002665]: STMT00238 ( 0x336[E-] ... 0x33B ) N017 ( 18, 23) [001103] -A-XGO--R-- * ASG int N016 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N015 ( 18, 23) [002670] ---XGO----- \--* COMMA int N004 ( 8, 11) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void [003721] ----------- | +--* CNS_INT int 0 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002671] n---GO----- \--* IND int N013 ( 7, 10) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N012 ( 7, 10) [002668] -------N--- \--* ADD byref N007 ( 3, 4) [002667] ----------- +--* ADD byref N005 ( 1, 1) [002659] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- | \--* CNS_INT long 16 $200 [003724] ----------- \--* CNS_INT long 0 $205 Folding long operator with constant nodes into a constant: [003725] ----------- * ADD long N006 ( 1, 2) [002666] ----------- +--* CNS_INT long 16 $200 [003724] ----------- \--* CNS_INT long 0 $205 Bashed to long constant: [003725] ----------- * CNS_INT long 16 $200 optVNAssertionPropCurStmt morphed tree: N012 ( 12, 15) [001103] -A-XGO--R-- * ASG int N011 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N010 ( 12, 15) [002670] ---XGO----- \--* COMMA int N004 ( 8, 12) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [003721] ----------- | +--* CNS_INT int 0 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N009 ( 4, 3) [002671] n---GO----- \--* IND int N008 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N007 ( 1, 1) [002667] -------N--- \--* ADD byref N005 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 GenTreeNode creates assertion: N004 ( 8, 12) [002662] ---X-O----- * BOUNDS_CHECK_Rng void In BB81 New Global ArrBnds Assertion: ($0,$0) [idx: {IntCns 0};len: {ARR_LENGTH($18b)}] in range , index = #39 GenTreeNode creates assertion: N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void In BB82 New Global Constant Assertion: ($719,$c0) Const_Loop_Bnd {LT($296, $c0)} is not {IntCns 0}, index = #40 GenTreeNode creates assertion: N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void In BB82 New Global Constant Assertion: ($719,$c0) Const_Loop_Bnd {LT($296, $c0)} is {IntCns 0}, index = #41 GenTreeNode creates assertion: N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void In BB89 New Global Constant Assertion: ($29d,$c0) V30.02 == 0, index = #42 GenTreeNode creates assertion: N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void In BB89 New Global Constant Assertion: ($29d,$c0) V30.02 != 0, index = #43 GenTreeNode creates assertion: N002 ( 3, 3) [001608] ---X------- * ARR_LENGTH int $2cc In BB93 New Global Constant Assertion: ($800,$0) V33.01 != null, index = #44 GenTreeNode creates assertion: N003 ( 6, 9) [001029] ---X-O----- * BOUNDS_CHECK_Rng void $334 In BB100 New Global ArrBnds Assertion: ($0,$0) [idx: {ADD($c1, $29b)};len: {PhiDef($90, $4, $254)}] in range , index = #45 GenTreeNode creates assertion: N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void In BB100 New Global Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is not {IntCns 0}, index = #46 GenTreeNode creates assertion: N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void In BB100 New Global Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 GenTreeNode creates assertion: N004 ( 8, 11) [002733] ---X-O----- * BOUNDS_CHECK_Rng void In BB101 New Global ArrBnds Assertion: ($0,$0) [idx: {ADD($c1, $29e)};len: {ARR_LENGTH($18b)}] in range , index = #48 GenTreeNode creates assertion: N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void In BB104 New Global Constant Assertion: ($283,$c0) V16.03 != 0, index = #49 GenTreeNode creates assertion: N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void In BB104 New Global Constant Assertion: ($283,$c0) V16.03 == 0, index = #50 GenTreeNode creates assertion: N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void In BB106 New Global Constant Assertion: ($191,$0) V86.01 == null, index = #51 GenTreeNode creates assertion: N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void In BB106 New Global Constant Assertion: ($191,$0) V86.01 != null, index = #52 GenTreeNode creates assertion: N004 ( 4, 3) [001736] ---XG------ * IND int In BB107 New Global Constant Assertion: ($100,$0) Value_Number {InitVal($c0)} is not 0, index = #53 GenTreeNode creates assertion: N005 ( 7, 8) [001743] ---X------- * JTRUE void In BB107 New Global ArrBnds Assertion: ($2d1,$c1) [idx: {IntCns 0};len: {ARR_LENGTH($191)}] is , index = #54 GenTreeNode creates assertion: N006 ( 11, 12) [001763] ---XGO----- * BOUNDS_CHECK_Rng void In BB109 New Global ArrBnds Assertion: ($0,$0) [idx: {MemOpaque:NotInLoop};len: {MemOpaque:NotInLoop}] in range , index = #55 GenTreeNode creates assertion: N019 ( 8, 12) [002768] ---X-O----- * BOUNDS_CHECK_Rng void In BB109 New Global ArrBnds Assertion: ($0,$0) [idx: {IntCns 0};len: {ARR_LENGTH($191)}] in range , index = #56 GenTreeNode creates assertion: N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void In BB113 New Global Constant Assertion: ($89f,$c0) Const_Loop_Bnd {LE($2ab, $c0)} is not {IntCns 0}, index = #57 GenTreeNode creates assertion: N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void In BB113 New Global Constant Assertion: ($89f,$c0) Const_Loop_Bnd {LE($2ab, $c0)} is {IntCns 0}, index = #58 GenTreeNode creates assertion: N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void In BB114 New Global Constant Assertion: ($89a,$ea) V18.01 == 35, index = #59 GenTreeNode creates assertion: N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void In BB114 New Global Constant Assertion: ($89a,$ea) V18.01 != 35, index = #60 GenTreeNode creates assertion: N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void In BB115 New Global Constant Assertion: ($89a,$eb) V18.01 == 46, index = #61 GenTreeNode creates assertion: N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void In BB115 New Global Constant Assertion: ($89a,$eb) V18.01 != 46, index = #62 GenTreeNode creates assertion: N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void In BB116 New Global Constant Assertion: ($89a,$d8) V18.01 == 48, index = #63 GenTreeNode creates assertion: N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void In BB116 New Global Constant Assertion: ($89a,$d8) V18.01 != 48, index = #64 BB01 valueGen = #01 #02 => BB05 valueGen = #01 #02 BB02 valueGen = #01 => BB04 valueGen = #01 BB03 valueGen = #NA BB04 valueGen = #NA BB05 valueGen = #NA BB06 valueGen = #NA BB07 valueGen = #NA BB08 valueGen = #NA => BB13 valueGen = #NA BB09 valueGen = #NA BB10 valueGen = #NA Compiler::optImpliedByConstAssertion: const assertion #03 implies assertion #06 Compiler::optImpliedByConstAssertion: const assertion #03 implies assertion #08 Compiler::optImpliedByConstAssertion: const assertion #03 implies assertion #09 Compiler::optImpliedByConstAssertion: const assertion #03 implies assertion #22 Compiler::optImpliedByConstAssertion: const assertion #03 implies assertion #23 BB11 valueGen = #04 => BB38 valueGen = #03 #06 #08 #09 #22 #23 BB12 valueGen = #NA Compiler::optImpliedByConstAssertion: const assertion #05 implies assertion #04 Compiler::optImpliedByConstAssertion: const assertion #05 implies assertion #08 Compiler::optImpliedByConstAssertion: const assertion #05 implies assertion #09 Compiler::optImpliedByConstAssertion: const assertion #05 implies assertion #22 Compiler::optImpliedByConstAssertion: const assertion #05 implies assertion #23 BB13 valueGen = #06 => BB35 valueGen = #04 #05 #08 #09 #22 #23 Compiler::optImpliedByConstAssertion: const assertion #07 implies assertion #04 Compiler::optImpliedByConstAssertion: const assertion #07 implies assertion #06 Compiler::optImpliedByConstAssertion: const assertion #07 implies assertion #09 Compiler::optImpliedByConstAssertion: const assertion #07 implies assertion #22 Compiler::optImpliedByConstAssertion: const assertion #07 implies assertion #23 BB14 valueGen = #08 => BB38 valueGen = #04 #06 #07 #09 #22 #23 Compiler::optImpliedByConstAssertion: const assertion #10 implies assertion #04 Compiler::optImpliedByConstAssertion: const assertion #10 implies assertion #06 Compiler::optImpliedByConstAssertion: const assertion #10 implies assertion #08 Compiler::optImpliedByConstAssertion: const assertion #10 implies assertion #22 Compiler::optImpliedByConstAssertion: const assertion #10 implies assertion #23 BB15 valueGen = #04 #06 #08 #10 #22 #23 => BB47 valueGen = #09 BB16 valueGen = #NA BB17 valueGen = #NA BB18 valueGen = #12 => BB20 valueGen = #11 BB19 valueGen = #NA BB20 valueGen = #NA BB21 valueGen = #14 => BB47 valueGen = #13 BB22 valueGen = #NA BB23 valueGen = #16 => BB47 valueGen = #15 BB24 valueGen = #14 => BB47 valueGen = #13 BB25 valueGen = #18 => BB29 valueGen = #17 BB26 valueGen = #20 => BB28 valueGen = #19 BB27 valueGen = #NA BB28 valueGen = #NA BB29 valueGen = #NA BB30 valueGen = #NA BB31 valueGen = #NA => BB47 valueGen = #NA BB32 valueGen = #NA => BB47 valueGen = #NA BB33 valueGen = #NA => BB31 valueGen = #NA BB34 valueGen = #NA BB35 valueGen = #NA => BB47 valueGen = #NA BB36 valueGen = #NA => BB47 valueGen = #NA BB37 valueGen = #NA BB38 valueGen = #NA => BB40 valueGen = #NA BB39 valueGen = #NA => BB44 valueGen = #NA BB40 valueGen = #NA => BB47 valueGen = #NA BB41 valueGen = #NA => BB43 valueGen = #NA BB42 valueGen = #NA => BB47 valueGen = #NA BB43 valueGen = #NA => BB47 valueGen = #NA BB44 valueGen = #NA => BB46 valueGen = #NA BB45 valueGen = #NA => BB44 valueGen = #NA BB46 valueGen = #NA BB47 valueGen = #NA => BB50 valueGen = #NA Compiler::optImpliedByConstAssertion: const assertion #21 implies assertion #04 Compiler::optImpliedByConstAssertion: const assertion #21 implies assertion #06 Compiler::optImpliedByConstAssertion: const assertion #21 implies assertion #08 Compiler::optImpliedByConstAssertion: const assertion #21 implies assertion #09 Compiler::optImpliedByConstAssertion: const assertion #21 implies assertion #23 BB48 valueGen = #22 => BB50 valueGen = #04 #06 #08 #09 #21 #23 Compiler::optImpliedByConstAssertion: const assertion #24 implies assertion #04 Compiler::optImpliedByConstAssertion: const assertion #24 implies assertion #06 Compiler::optImpliedByConstAssertion: const assertion #24 implies assertion #08 Compiler::optImpliedByConstAssertion: const assertion #24 implies assertion #09 Compiler::optImpliedByConstAssertion: const assertion #24 implies assertion #22 BB49 valueGen = #04 #06 #08 #09 #22 #24 => BB08 valueGen = #23 BB50 valueGen = #14 => BB52 valueGen = #13 BB51 valueGen = #NA BB52 valueGen = #18 => BB56 valueGen = #17 BB53 valueGen = #26 => BB55 valueGen = #25 BB54 valueGen = #NA BB55 valueGen = #NA BB56 valueGen = #NA => BB63 valueGen = #NA BB57 valueGen = #01 #28 => BB59 valueGen = #01 #27 BB58 valueGen = #01 BB59 valueGen = #NA BB60 valueGen = #NA => BB66 valueGen = #NA BB61 valueGen = #30 => BB66 valueGen = #29 BB62 valueGen = #NA BB63 valueGen = #01 => BB65 valueGen = #01 BB64 valueGen = #01 BB65 valueGen = #01 BB66 valueGen = #NA => BB68 valueGen = #NA BB67 valueGen = #NA BB68 valueGen = #NA BB69 valueGen = #NA => BB71 valueGen = #NA BB70 valueGen = #NA BB71 valueGen = #NA BB72 valueGen = #27 => BB74 valueGen = #28 BB73 valueGen = #NA BB74 valueGen = #01 => BB76 valueGen = #01 BB75 valueGen = #NA BB76 valueGen = #NA BB77 valueGen = #NA BB78 valueGen = #32 => BB103 valueGen = #31 BB79 valueGen = #33 #35 => BB103 valueGen = #33 #34 BB80 valueGen = #33 #36 #38 => BB82 valueGen = #33 #36 #37 BB81 valueGen = #36 #39 BB82 valueGen = #41 => BB84 valueGen = #40 BB83 valueGen = #NA BB84 valueGen = #NA BB85 valueGen = #NA => BB87 valueGen = #NA BB86 valueGen = #NA BB87 valueGen = #NA BB88 valueGen = #NA => BB103 valueGen = #NA BB89 valueGen = #43 => BB103 valueGen = #42 BB90 valueGen = #NA => BB100 valueGen = #NA BB91 valueGen = #NA BB92 valueGen = #NA BB93 valueGen = #44 BB94 valueGen = #NA => BB110 valueGen = #NA BB95 valueGen = #NA BB96 valueGen = #NA BB97 valueGen = #NA BB98 valueGen = #44 BB99 valueGen = #NA BB100 valueGen = #45 #47 => BB102 valueGen = #45 #46 BB101 valueGen = #36 #48 BB102 valueGen = #NA => BB89 valueGen = #NA BB103 valueGen = #01 => BB112 valueGen = #01 BB104 valueGen = #50 => BB112 valueGen = #49 BB105 valueGen = #01 => BB112 valueGen = #01 BB106 valueGen = #33 #52 => BB112 valueGen = #33 #51 BB107 valueGen = #52 #53 #54 => BB111 valueGen = #52 #53 BB108 valueGen = #53 => BB111 valueGen = #53 BB109 valueGen = #52 #53 #55 #56 BB110 valueGen = #NA BB111 valueGen = #NA BB112 valueGen = #NA BB113 valueGen = #58 => BB136 valueGen = #57 Compiler::optImpliedByConstAssertion: const assertion #59 implies assertion #62 Compiler::optImpliedByConstAssertion: const assertion #59 implies assertion #64 BB114 valueGen = #60 => BB135 valueGen = #59 #62 #64 Compiler::optImpliedByConstAssertion: const assertion #61 implies assertion #60 Compiler::optImpliedByConstAssertion: const assertion #61 implies assertion #64 BB115 valueGen = #62 => BB135 valueGen = #60 #61 #64 Compiler::optImpliedByConstAssertion: const assertion #63 implies assertion #60 Compiler::optImpliedByConstAssertion: const assertion #63 implies assertion #62 BB116 valueGen = #64 => BB135 valueGen = #60 #62 #63 BB117 valueGen = #NA BB118 valueGen = #NA => BB120 valueGen = #NA BB119 valueGen = #NA BB120 valueGen = #NA BB121 valueGen = #53 => BB123 valueGen = #53 BB122 valueGen = #53 BB123 valueGen = #NA BB124 valueGen = #32 => BB134 valueGen = #31 BB125 valueGen = #NA => BB134 valueGen = #NA BB126 valueGen = #NA => BB134 valueGen = #NA BB127 valueGen = #NA => BB134 valueGen = #NA BB128 valueGen = #33 => BB133 valueGen = #33 BB129 valueGen = #53 => BB132 valueGen = #53 BB130 valueGen = #53 => BB132 valueGen = #53 BB131 valueGen = #53 BB132 valueGen = #NA BB133 valueGen = #NA BB134 valueGen = #NA BB135 valueGen = #NA => BB118 valueGen = #NA BB136 valueGen = #NA => BB141 valueGen = #NA BB137 valueGen = #NA BB138 valueGen = #NA BB139 valueGen = #NA => BB205 valueGen = #NA BB140 valueGen = #NA BB141 valueGen = #NA => BB200 valueGen = #NA BB142 valueGen = #NA => BB205 valueGen = #NA BB143 valueGen = #NA => BB242 valueGen = #NA BB144 valueGen = #33 BB145 valueGen = #NA => BB150 valueGen = #NA BB146 valueGen = #NA => BB148 valueGen = #NA BB147 valueGen = #NA BB148 valueGen = #NA BB149 valueGen = #NA BB150 valueGen = #NA => BB154 valueGen = #NA BB151 valueGen = #NA => BB153 valueGen = #NA BB152 valueGen = #NA BB153 valueGen = #NA BB154 valueGen = #NA BB155 valueGen = #NA BB156 valueGen = #NA => BB170 valueGen = #NA BB157 valueGen = #53 => BB159 valueGen = #53 BB158 valueGen = #53 BB159 valueGen = #NA BB160 valueGen = #32 => BB170 valueGen = #31 BB161 valueGen = #NA => BB170 valueGen = #NA BB162 valueGen = #NA => BB170 valueGen = #NA BB163 valueGen = #NA => BB170 valueGen = #NA BB164 valueGen = #33 => BB169 valueGen = #33 BB165 valueGen = #53 => BB168 valueGen = #53 BB166 valueGen = #53 => BB168 valueGen = #53 BB167 valueGen = #53 BB168 valueGen = #NA BB169 valueGen = #NA BB170 valueGen = #NA BB171 valueGen = #NA => BB245 valueGen = #NA BB172 valueGen = #NA => BB175 valueGen = #NA BB173 valueGen = #NA => BB245 valueGen = #NA BB174 valueGen = #NA => BB245 valueGen = #NA BB175 valueGen = #33 => BB180 valueGen = #33 BB176 valueGen = #53 => BB179 valueGen = #53 BB177 valueGen = #53 => BB179 valueGen = #53 BB178 valueGen = #53 BB179 valueGen = #NA BB180 valueGen = #NA BB181 valueGen = #NA => BB245 valueGen = #NA BB182 valueGen = #53 => BB185 valueGen = #53 BB183 valueGen = #53 => BB185 valueGen = #53 BB184 valueGen = #53 BB185 valueGen = #NA BB186 valueGen = #33 => BB245 valueGen = #33 BB187 valueGen = #53 => BB190 valueGen = #53 BB188 valueGen = #53 => BB190 valueGen = #53 BB189 valueGen = #53 BB190 valueGen = #NA BB191 valueGen = #53 => BB193 valueGen = #53 BB192 valueGen = #53 BB193 valueGen = #NA BB194 valueGen = #NA => BB197 valueGen = #NA BB195 valueGen = #NA => BB198 valueGen = #NA BB196 valueGen = #NA => BB191 valueGen = #NA BB197 valueGen = #NA => BB245 valueGen = #NA BB198 valueGen = #NA => BB245 valueGen = #NA BB199 valueGen = #NA BB200 valueGen = #NA => BB245 valueGen = #NA BB201 valueGen = #NA => BB245 valueGen = #NA BB202 valueGen = #53 => BB204 valueGen = #53 BB203 valueGen = #53 BB204 valueGen = #NA BB205 valueGen = #NA => BB227 valueGen = #NA BB206 valueGen = #NA => BB208 valueGen = #NA BB207 valueGen = #NA => BB218 valueGen = #NA BB208 valueGen = #NA => BB212 valueGen = #NA BB209 valueGen = #NA => BB213 valueGen = #NA BB210 valueGen = #NA => BB213 valueGen = #NA BB211 valueGen = #NA BB212 valueGen = #NA BB213 valueGen = #NA => BB215 valueGen = #NA BB214 valueGen = #NA => BB219 valueGen = #NA BB215 valueGen = #53 => BB217 valueGen = #53 BB216 valueGen = #53 BB217 valueGen = #NA BB218 valueGen = #NA BB219 valueGen = #NA => BB221 valueGen = #NA BB220 valueGen = #NA => BB218 valueGen = #NA BB221 valueGen = #NA => BB223 valueGen = #NA BB222 valueGen = #NA BB223 valueGen = #NA => BB225 valueGen = #NA BB224 valueGen = #01 BB225 valueGen = #NA BB226 valueGen = #NA BB227 valueGen = #53 => BB229 valueGen = #53 BB228 valueGen = #53 BB229 valueGen = #NA BB230 valueGen = #NA => BB245 valueGen = #NA BB231 valueGen = #NA => BB233 valueGen = #NA BB232 valueGen = #NA => BB239 valueGen = #NA BB233 valueGen = #53 => BB235 valueGen = #53 BB234 valueGen = #53 BB235 valueGen = #NA BB236 valueGen = #53 => BB238 valueGen = #53 BB237 valueGen = #53 BB238 valueGen = #NA BB239 valueGen = #NA => BB245 valueGen = #NA BB240 valueGen = #NA => BB236 valueGen = #NA BB241 valueGen = #NA BB242 valueGen = #53 => BB244 valueGen = #53 BB243 valueGen = #53 BB244 valueGen = #NA BB245 valueGen = #NA => BB248 valueGen = #NA BB246 valueGen = #NA => BB248 valueGen = #NA BB247 valueGen = #NA => BB113 valueGen = #NA BB248 valueGen = #01 => BB253 valueGen = #01 BB249 valueGen = #50 => BB253 valueGen = #49 BB250 valueGen = #01 => BB253 valueGen = #01 BB251 valueGen = #53 => BB253 valueGen = #53 BB252 valueGen = #33 BB253 valueGen = #NA BB01: in = #NA out = #01 #02 BB05 = #01 #02 BB02: in = #01 #02 out = #01 #02 BB04 = #01 #02 BB03: in = #01 #02 out = #01 #02 BB04: in = #01 #02 out = #01 #02 BB05: in = #01 #02 out = #01 #02 BB06: in = #01 #02 out = #01 #02 BB07: in = #01 #02 out = #01 #02 BB08: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB13 = #01 #02 #22 #23 BB09: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB10: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB11: in = #01 #02 #22 #23 out = #01 #02 #04 #22 #23 BB38 = #01 #02 #03 #06 #08 #09 #22 #23 BB12: in = #01 #02 #04 #22 #23 out = #01 #02 #04 #22 #23 BB13: in = #01 #02 #22 #23 out = #01 #02 #06 #22 #23 BB35 = #01 #02 #04 #05 #08 #09 #22 #23 BB14: in = #01 #02 #06 #22 #23 out = #01 #02 #06 #08 #22 #23 BB38 = #01 #02 #04 #06 #07 #09 #22 #23 BB15: in = #01 #02 #06 #08 #22 #23 out = #01 #02 #04 #06 #08 #10 #22 #23 BB47 = #01 #02 #06 #08 #09 #22 #23 BB16: in = #01 #02 #04 #06 #08 #10 #22 #23 out = #01 #02 #04 #06 #08 #10 #22 #23 BB17: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB18: in = #01 #02 #22 #23 out = #01 #02 #12 #22 #23 BB20 = #01 #02 #11 #22 #23 BB19: in = #01 #02 #12 #22 #23 out = #01 #02 #12 #22 #23 BB20: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB21: in = #01 #02 #22 #23 out = #01 #02 #14 #22 #23 BB47 = #01 #02 #13 #22 #23 BB22: in = #01 #02 #14 #22 #23 out = #01 #02 #14 #22 #23 BB23: in = #01 #02 #22 #23 out = #01 #02 #16 #22 #23 BB47 = #01 #02 #15 #22 #23 BB24: in = #01 #02 #16 #22 #23 out = #01 #02 #14 #16 #22 #23 BB47 = #01 #02 #13 #16 #22 #23 BB25: in = #01 #02 #14 #16 #22 #23 out = #01 #02 #14 #16 #18 #22 #23 BB29 = #01 #02 #14 #16 #17 #22 #23 BB26: in = #01 #02 #14 #16 #18 #22 #23 out = #01 #02 #14 #16 #18 #20 #22 #23 BB28 = #01 #02 #14 #16 #18 #19 #22 #23 BB27: in = #01 #02 #14 #16 #18 #20 #22 #23 out = #01 #02 #14 #16 #18 #20 #22 #23 BB28: in = #01 #02 #14 #16 #18 #19 #22 #23 out = #01 #02 #14 #16 #18 #19 #22 #23 BB29: in = #01 #02 #14 #16 #22 #23 out = #01 #02 #14 #16 #22 #23 BB30: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB31: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB47 = #01 #02 #22 #23 BB32: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB47 = #01 #02 #22 #23 BB33: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB31 = #01 #02 #22 #23 BB34: in = #01 #02 #22 #23 out = #01 #02 #22 #23 BB35: in = #01 #02 #04 #05 #08 #09 #22 #23 out = #01 #02 #04 #05 #08 #09 #22 #23 BB47 = #01 #02 #04 #05 #08 #09 #22 #23 BB36: in = #01 #02 #04 #05 #08 #09 #22 #23 out = #01 #02 #04 #05 #08 #09 #22 #23 BB47 = #01 #02 #04 #05 #08 #09 #22 #23 BB37: in = #01 #02 #04 #05 #08 #09 #22 #23 out = #01 #02 #04 #05 #08 #09 #22 #23 BB38: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB40 = #01 #02 #06 #09 #22 #23 BB39: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB44 = #01 #02 #06 #09 #22 #23 BB40: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB47 = #01 #02 #06 #09 #22 #23 BB41: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB43 = #01 #02 #06 #09 #22 #23 BB42: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB47 = #01 #02 #06 #09 #22 #23 BB43: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB47 = #01 #02 #06 #09 #22 #23 BB44: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB46 = #01 #02 #06 #09 #22 #23 BB45: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB44 = #01 #02 #06 #09 #22 #23 BB46: in = #01 #02 #06 #09 #22 #23 out = #01 #02 #06 #09 #22 #23 BB47: in = #01 #02 out = #01 #02 BB50 = #01 #02 BB48: in = #01 #02 out = #01 #02 #22 BB50 = #01 #02 #04 #06 #08 #09 #21 #23 BB49: in = #01 #02 #22 out = #01 #02 #04 #06 #08 #09 #22 #24 BB08 = #01 #02 #22 #23 BB50: in = #01 #02 out = #01 #02 #14 BB52 = #01 #02 #13 BB51: in = #01 #02 #14 out = #01 #02 #14 BB52: in = #01 #02 out = #01 #02 #18 BB56 = #01 #02 #17 BB53: in = #01 #02 #18 out = #01 #02 #18 #26 BB55 = #01 #02 #18 #25 BB54: in = #01 #02 #18 #26 out = #01 #02 #18 #26 BB55: in = #01 #02 #18 #25 out = #01 #02 #18 #25 BB56: in = #01 #02 out = #01 #02 BB63 = #01 #02 BB57: in = #01 #02 out = #01 #02 #28 BB59 = #01 #02 #27 BB58: in = #01 #02 #28 out = #01 #02 #28 BB59: in = #01 #02 #27 out = #01 #02 #27 BB60: in = #01 #02 out = #01 #02 BB66 = #01 #02 BB61: in = #01 #02 out = #01 #02 #30 BB66 = #01 #02 #29 BB62: in = #01 #02 #30 out = #01 #02 #30 BB63: in = #01 #02 out = #01 #02 BB65 = #01 #02 BB64: in = #01 #02 out = #01 #02 BB65: in = #01 #02 out = #01 #02 BB66: in = #01 #02 out = #01 #02 BB68 = #01 #02 BB67: in = #01 #02 out = #01 #02 BB68: in = #01 #02 out = #01 #02 BB69: in = #01 #02 out = #01 #02 BB71 = #01 #02 BB70: in = #01 #02 out = #01 #02 BB71: in = #01 #02 out = #01 #02 BB72: in = #01 #02 out = #01 #02 #27 BB74 = #01 #02 #28 BB73: in = #01 #02 #27 out = #01 #02 #27 BB74: in = #01 #02 #28 out = #01 #02 #28 BB76 = #01 #02 #28 BB75: in = #01 #02 #28 out = #01 #02 #28 BB76: in = #01 #02 #28 out = #01 #02 #28 BB77: in = #01 #02 #28 out = #01 #02 #28 BB78: in = #01 #02 out = #01 #02 #32 BB103 = #01 #02 #31 BB79: in = #01 #02 #32 out = #01 #02 #32 #33 #35 BB103 = #01 #02 #32 #33 #34 BB80: in = #01 #02 #32 #33 #35 out = #01 #02 #32 #33 #35 #36 #38 BB82 = #01 #02 #32 #33 #35 #36 #37 BB81: in = #01 #02 #32 #33 #35 #36 #38 out = #01 #02 #32 #33 #35 #36 #38 #39 BB82: in = #01 #02 #32 #33 #35 #36 out = #01 #02 #32 #33 #35 #36 #41 BB84 = #01 #02 #32 #33 #35 #36 #40 BB83: in = #01 #02 #32 #33 #35 #36 #41 out = #01 #02 #32 #33 #35 #36 #41 BB84: in = #01 #02 #32 #33 #35 #36 #40 out = #01 #02 #32 #33 #35 #36 #40 BB85: in = #01 #02 #32 #33 #35 #36 out = #01 #02 #32 #33 #35 #36 BB87 = #01 #02 #32 #33 #35 #36 BB86: in = #01 #02 #32 #33 #35 #36 out = #01 #02 #32 #33 #35 #36 BB87: in = #01 #02 #32 #33 #35 #36 out = #01 #02 #32 #33 #35 #36 BB88: in = #01 #02 #32 #33 #35 #36 out = #01 #02 #32 #33 #35 #36 BB103 = #01 #02 #32 #33 #35 #36 BB89: in = #01 #02 #32 #33 #35 #36 out = #01 #02 #32 #33 #35 #36 #43 BB103 = #01 #02 #32 #33 #35 #36 #42 BB90: in = #01 #02 #32 #33 #35 #36 #43 out = #01 #02 #32 #33 #35 #36 #43 BB100 = #01 #02 #32 #33 #35 #36 #43 BB91: in = #01 #02 #32 #33 #35 #36 #43 out = #01 #02 #32 #33 #35 #36 #43 BB92: in = #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 out = #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 BB93: in = #01 #02 #32 #33 #35 #36 #43 out = #01 #02 #32 #33 #35 #36 #43 #44 BB94: in = #01 #02 #32 #33 #35 #36 #43 #44 out = #01 #02 #32 #33 #35 #36 #43 #44 BB110 = #01 #02 #32 #33 #35 #36 #43 #44 BB95: in = #01 #02 #32 #33 #35 #36 #43 #44 out = #01 #02 #32 #33 #35 #36 #43 #44 BB96: in = #01 #02 #32 #33 #35 #36 #43 #44 out = #01 #02 #32 #33 #35 #36 #43 #44 BB97: in = #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 out = #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 BB98: in = #01 #02 #32 #33 #35 #36 #43 #44 out = #01 #02 #32 #33 #35 #36 #43 #44 BB99: in = #01 #02 #32 #33 #35 #36 #43 #44 out = #01 #02 #32 #33 #35 #36 #43 #44 BB100: in = #01 #02 #32 #33 #35 #36 #43 out = #01 #02 #32 #33 #35 #36 #43 #45 #47 BB102 = #01 #02 #32 #33 #35 #36 #43 #45 #46 BB101: in = #01 #02 #32 #33 #35 #36 #43 #45 #47 out = #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 BB102: in = #01 #02 #32 #33 #35 #36 #43 #45 out = #01 #02 #32 #33 #35 #36 #43 #45 BB89 = #01 #02 #32 #33 #35 #36 #43 #45 BB103: in = #01 #02 out = #01 #02 BB112 = #01 #02 BB104: in = #01 #02 out = #01 #02 #50 BB112 = #01 #02 #49 BB105: in = #01 #02 #50 out = #01 #02 #50 BB112 = #01 #02 #50 BB106: in = #01 #02 #50 out = #01 #02 #33 #50 #52 BB112 = #01 #02 #33 #50 #51 BB107: in = #01 #02 #33 #50 #52 out = #01 #02 #33 #50 #52 #53 #54 BB111 = #01 #02 #33 #50 #52 #53 BB108: in = #01 #02 #33 #50 #52 #53 #54 out = #01 #02 #33 #50 #52 #53 #54 BB111 = #01 #02 #33 #50 #52 #53 #54 BB109: in = #01 #02 #33 #50 #52 #53 #54 out = #01 #02 #33 #50 #52 #53 #54 #55 #56 BB110: in = #01 #02 #32 #33 #35 #36 #43 #44 out = #01 #02 #32 #33 #35 #36 #43 #44 BB111: in = #01 #02 #33 #50 #52 #53 out = #01 #02 #33 #50 #52 #53 BB112: in = #01 #02 out = #01 #02 BB113: in = #01 #02 out = #01 #02 #58 BB136 = #01 #02 #57 BB114: in = #01 #02 #58 out = #01 #02 #58 #60 BB135 = #01 #02 #58 #59 #62 #64 BB115: in = #01 #02 #58 #60 out = #01 #02 #58 #60 #62 BB135 = #01 #02 #58 #60 #61 #64 BB116: in = #01 #02 #58 #60 #62 out = #01 #02 #58 #60 #62 #64 BB135 = #01 #02 #58 #60 #62 #63 BB117: in = #01 #02 #58 #60 #62 #64 out = #01 #02 #58 #60 #62 #64 BB118: in = #01 #02 #58 out = #01 #02 #58 BB120 = #01 #02 #58 BB119: in = #01 #02 #58 out = #01 #02 #58 BB120: in = #01 #02 #58 out = #01 #02 #58 BB121: in = #01 #02 #58 out = #01 #02 #53 #58 BB123 = #01 #02 #53 #58 BB122: in = #01 #02 #53 #58 out = #01 #02 #53 #58 BB123: in = #01 #02 #53 #58 out = #01 #02 #53 #58 BB124: in = #01 #02 #53 #58 out = #01 #02 #32 #53 #58 BB134 = #01 #02 #31 #53 #58 BB125: in = #01 #02 #32 #53 #58 out = #01 #02 #32 #53 #58 BB134 = #01 #02 #32 #53 #58 BB126: in = #01 #02 #32 #53 #58 out = #01 #02 #32 #53 #58 BB134 = #01 #02 #32 #53 #58 BB127: in = #01 #02 #32 #53 #58 out = #01 #02 #32 #53 #58 BB134 = #01 #02 #32 #53 #58 BB128: in = #01 #02 #32 #53 #58 out = #01 #02 #32 #33 #53 #58 BB133 = #01 #02 #32 #33 #53 #58 BB129: in = #01 #02 #32 #33 #53 #58 out = #01 #02 #32 #33 #53 #58 BB132 = #01 #02 #32 #33 #53 #58 BB130: in = #01 #02 #32 #33 #53 #58 out = #01 #02 #32 #33 #53 #58 BB132 = #01 #02 #32 #33 #53 #58 BB131: in = #01 #02 #32 #33 #53 #58 out = #01 #02 #32 #33 #53 #58 BB132: in = #01 #02 #32 #33 #53 #58 out = #01 #02 #32 #33 #53 #58 BB133: in = #01 #02 #32 #33 #53 #58 out = #01 #02 #32 #33 #53 #58 BB134: in = #01 #02 #53 #58 out = #01 #02 #53 #58 BB135: in = #01 #02 #58 out = #01 #02 #58 BB118 = #01 #02 #58 BB136: in = #01 #02 out = #01 #02 BB141 = #01 #02 BB137: in = #01 #02 out = #01 #02 BB138: in = #01 #02 out = #01 #02 BB139: in = #01 #02 out = #01 #02 BB205 = #01 #02 BB140: in = #01 #02 out = #01 #02 BB141: in = #01 #02 out = #01 #02 BB200 = #01 #02 BB142: in = #01 #02 out = #01 #02 BB205 = #01 #02 BB143: in = #01 #02 out = #01 #02 BB242 = #01 #02 BB144: in = #01 #02 out = #01 #02 #33 BB145: in = #01 #02 out = #01 #02 BB150 = #01 #02 BB146: in = #01 #02 out = #01 #02 BB148 = #01 #02 BB147: in = #01 #02 out = #01 #02 BB148: in = #01 #02 out = #01 #02 BB149: in = #01 #02 out = #01 #02 BB150: in = #01 #02 out = #01 #02 BB154 = #01 #02 BB151: in = #01 #02 out = #01 #02 BB153 = #01 #02 BB152: in = #01 #02 out = #01 #02 BB153: in = #01 #02 out = #01 #02 BB154: in = #01 #02 out = #01 #02 BB155: in = #01 #02 out = #01 #02 BB156: in = #01 #02 out = #01 #02 BB170 = #01 #02 BB157: in = #01 #02 out = #01 #02 #53 BB159 = #01 #02 #53 BB158: in = #01 #02 #53 out = #01 #02 #53 BB159: in = #01 #02 #53 out = #01 #02 #53 BB160: in = #01 #02 #53 out = #01 #02 #32 #53 BB170 = #01 #02 #31 #53 BB161: in = #01 #02 #32 #53 out = #01 #02 #32 #53 BB170 = #01 #02 #32 #53 BB162: in = #01 #02 #32 #53 out = #01 #02 #32 #53 BB170 = #01 #02 #32 #53 BB163: in = #01 #02 #32 #53 out = #01 #02 #32 #53 BB170 = #01 #02 #32 #53 BB164: in = #01 #02 #32 #53 out = #01 #02 #32 #33 #53 BB169 = #01 #02 #32 #33 #53 BB165: in = #01 #02 #32 #33 #53 out = #01 #02 #32 #33 #53 BB168 = #01 #02 #32 #33 #53 BB166: in = #01 #02 #32 #33 #53 out = #01 #02 #32 #33 #53 BB168 = #01 #02 #32 #33 #53 BB167: in = #01 #02 #32 #33 #53 out = #01 #02 #32 #33 #53 BB168: in = #01 #02 #32 #33 #53 out = #01 #02 #32 #33 #53 BB169: in = #01 #02 #32 #33 #53 out = #01 #02 #32 #33 #53 BB170: in = #01 #02 out = #01 #02 BB171: in = #01 #02 out = #01 #02 BB245 = #01 #02 BB172: in = #01 #02 out = #01 #02 BB175 = #01 #02 BB173: in = #01 #02 out = #01 #02 BB245 = #01 #02 BB174: in = #01 #02 out = #01 #02 BB245 = #01 #02 BB175: in = #01 #02 out = #01 #02 #33 BB180 = #01 #02 #33 BB176: in = #01 #02 #33 out = #01 #02 #33 #53 BB179 = #01 #02 #33 #53 BB177: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB179 = #01 #02 #33 #53 BB178: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB179: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB180: in = #01 #02 #33 out = #01 #02 #33 BB181: in = #01 #02 #33 out = #01 #02 #33 BB245 = #01 #02 #33 BB182: in = #01 #02 #33 out = #01 #02 #33 #53 BB185 = #01 #02 #33 #53 BB183: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB185 = #01 #02 #33 #53 BB184: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB185: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB186: in = #01 #02 out = #01 #02 #33 BB245 = #01 #02 #33 BB187: in = #01 #02 #33 out = #01 #02 #33 #53 BB190 = #01 #02 #33 #53 BB188: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB190 = #01 #02 #33 #53 BB189: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB190: in = #01 #02 #33 #53 out = #01 #02 #33 #53 BB191: in = #01 #02 out = #01 #02 #53 BB193 = #01 #02 #53 BB192: in = #01 #02 #53 out = #01 #02 #53 BB193: in = #01 #02 #53 out = #01 #02 #53 BB194: in = #01 #02 out = #01 #02 BB197 = #01 #02 BB195: in = #01 #02 out = #01 #02 BB198 = #01 #02 BB196: in = #01 #02 out = #01 #02 BB191 = #01 #02 BB197: in = #01 #02 out = #01 #02 BB245 = #01 #02 BB198: in = #01 #02 out = #01 #02 BB245 = #01 #02 BB199: in = #01 #02 out = #01 #02 BB200: in = #01 #02 out = #01 #02 BB245 = #01 #02 BB201: in = #01 #02 out = #01 #02 BB245 = #01 #02 BB202: in = #01 #02 out = #01 #02 #53 BB204 = #01 #02 #53 BB203: in = #01 #02 #53 out = #01 #02 #53 BB204: in = #01 #02 #53 out = #01 #02 #53 BB205: in = #01 #02 out = #01 #02 BB227 = #01 #02 BB206: in = #01 #02 out = #01 #02 BB208 = #01 #02 BB207: in = #01 #02 out = #01 #02 BB218 = #01 #02 BB208: in = #01 #02 out = #01 #02 BB212 = #01 #02 BB209: in = #01 #02 out = #01 #02 BB213 = #01 #02 BB210: in = #01 #02 out = #01 #02 BB213 = #01 #02 BB211: in = #01 #02 out = #01 #02 BB212: in = #01 #02 out = #01 #02 BB213: in = #01 #02 out = #01 #02 BB215 = #01 #02 BB214: in = #01 #02 out = #01 #02 BB219 = #01 #02 BB215: in = #01 #02 out = #01 #02 #53 BB217 = #01 #02 #53 BB216: in = #01 #02 #53 out = #01 #02 #53 BB217: in = #01 #02 #53 out = #01 #02 #53 BB218: in = #01 #02 out = #01 #02 BB219: in = #01 #02 out = #01 #02 BB221 = #01 #02 BB220: in = #01 #02 out = #01 #02 BB218 = #01 #02 BB221: in = #01 #02 out = #01 #02 BB223 = #01 #02 BB222: in = #01 #02 out = #01 #02 BB223: in = #01 #02 out = #01 #02 BB225 = #01 #02 BB224: in = #01 #02 out = #01 #02 BB225: in = #01 #02 out = #01 #02 BB226: in = #01 #02 out = #01 #02 BB227: in = #01 #02 out = #01 #02 #53 BB229 = #01 #02 #53 BB228: in = #01 #02 #53 out = #01 #02 #53 BB229: in = #01 #02 #53 out = #01 #02 #53 BB230: in = #01 #02 #53 out = #01 #02 #53 BB245 = #01 #02 #53 BB231: in = #01 #02 #53 out = #01 #02 #53 BB233 = #01 #02 #53 BB232: in = #01 #02 #53 out = #01 #02 #53 BB239 = #01 #02 #53 BB233: in = #01 #02 #53 out = #01 #02 #53 BB235 = #01 #02 #53 BB234: in = #01 #02 #53 out = #01 #02 #53 BB235: in = #01 #02 #53 out = #01 #02 #53 BB236: in = #01 #02 #53 out = #01 #02 #53 BB238 = #01 #02 #53 BB237: in = #01 #02 #53 out = #01 #02 #53 BB238: in = #01 #02 #53 out = #01 #02 #53 BB239: in = #01 #02 #53 out = #01 #02 #53 BB245 = #01 #02 #53 BB240: in = #01 #02 #53 out = #01 #02 #53 BB236 = #01 #02 #53 BB241: in = #01 #02 #53 out = #01 #02 #53 BB242: in = #01 #02 out = #01 #02 #53 BB244 = #01 #02 #53 BB243: in = #01 #02 #53 out = #01 #02 #53 BB244: in = #01 #02 #53 out = #01 #02 #53 BB245: in = #01 #02 out = #01 #02 BB248 = #01 #02 BB246: in = #01 #02 out = #01 #02 BB248 = #01 #02 BB247: in = #01 #02 out = #01 #02 BB113 = #01 #02 BB248: in = #01 #02 out = #01 #02 BB253 = #01 #02 BB249: in = #01 #02 out = #01 #02 #50 BB253 = #01 #02 #49 BB250: in = #01 #02 #50 out = #01 #02 #50 BB253 = #01 #02 #50 BB251: in = #01 #02 #50 out = #01 #02 #50 #53 BB253 = #01 #02 #50 #53 BB252: in = #01 #02 #50 #53 out = #01 #02 #33 #50 #53 BB253: in = #01 #02 out = #01 #02 Propagating #NA for BB01, stmt STMT00000, tree [000000], tree -> #NA Propagating #NA for BB01, stmt STMT00000, tree [002543], tree -> #NA Propagating #NA for BB01, stmt STMT00000, tree [000001], tree -> #NA Propagating #NA for BB01, stmt STMT00001, tree [000002], tree -> #NA Propagating #NA for BB01, stmt STMT00001, tree [000003], tree -> #NA Propagating #NA for BB01, stmt STMT00001, tree [000004], tree -> #NA Propagating #NA for BB01, stmt STMT00320, tree [002546], tree -> #NA Propagating #NA for BB01, stmt STMT00320, tree [002547], tree -> #NA Propagating #NA for BB01, stmt STMT00320, tree [002548], tree -> #NA Propagating #NA for BB01, stmt STMT00320, tree [001499], tree -> #NA Propagating #NA for BB01, stmt STMT00320, tree [001500], tree -> #NA Propagating #NA for BB01, stmt STMT00003, tree [001497], tree -> #NA Propagating #NA for BB01, stmt STMT00003, tree [001502], tree -> #NA Propagating #NA for BB01, stmt STMT00003, tree [002555], tree -> #NA Propagating #NA for BB01, stmt STMT00003, tree [002556], tree -> #NA Propagating #NA for BB01, stmt STMT00003, tree [001503], tree -> #01 Propagating #01 for BB01, stmt STMT00003, tree [001504], tree -> #02 Propagating #01 #02 for BB01, stmt STMT00003, tree [001501], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00003, tree [001505], tree -> #01 VN based non-null prop in BB01: N008 ( 3, 2) [001505] ---XG------ * IND byref Propagating #01 #02 for BB01, stmt STMT00003, tree [001507], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00003, tree [002550], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00003, tree [002551], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00003, tree [002552], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00003, tree [002554], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00003, tree [000008], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00003, tree [000009], tree -> #NA Re-morphing this stmt: STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] n---GO----- | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 optAssertionPropMain morphed tree: N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] n---GO----- | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 Propagating #01 #02 for BB01, stmt STMT00005, tree [002558], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [003708], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [003709], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [003710], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [003711], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [002557], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [002559], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [002561], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [003688], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [003689], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [003690], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [003691], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [002560], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [002562], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00005, tree [002563], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00004, tree [000011], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00004, tree [000012], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00004, tree [000013], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00004, tree [000014], tree -> #NA Propagating #01 #02 for BB01, stmt STMT00004, tree [000015], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00315, tree [002565], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00315, tree [002564], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00315, tree [002566], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00315, tree [002568], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00315, tree [002567], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00315, tree [002569], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00315, tree [002570], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00314, tree [001472], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00314, tree [002571], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00314, tree [002572], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00314, tree [001473], tree -> #01 VN based non-null prop in BB02: N004 ( 5, 4) [001473] ---XG------ * IND bool Propagating #01 #02 for BB02, stmt STMT00314, tree [001474], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00314, tree [001475], tree -> #NA Propagating #01 #02 for BB02, stmt STMT00314, tree [001476], tree -> #NA Re-morphing this stmt: STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ---XG------ * JTRUE void $301 N006 ( 7, 7) [001475] J--XG--N--- \--* NE int N004 ( 5, 4) [001473] n---GO----- +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 optAssertionPropMain morphed tree: N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 N006 ( 7, 7) [001475] J---GO-N--- \--* NE int N004 ( 5, 4) [001473] n---GO----- +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 Propagating #01 #02 for BB03, stmt STMT00318, tree [002574], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00318, tree [002573], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00318, tree [002575], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00318, tree [002577], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00318, tree [002576], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00318, tree [002578], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00318, tree [002579], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00319, tree [001489], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00319, tree [001493], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00319, tree [001494], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00316, tree [002581], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00316, tree [002580], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00316, tree [002582], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00316, tree [002584], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00316, tree [002583], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00316, tree [002585], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00316, tree [002586], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00317, tree [001482], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00317, tree [001486], tree -> #NA Propagating #01 #02 for BB04, stmt STMT00317, tree [001487], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00006, tree [002588], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00006, tree [002587], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00006, tree [002589], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00006, tree [002591], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00006, tree [002590], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00006, tree [002592], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00006, tree [002593], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00007, tree [000021], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00007, tree [000025], tree -> #NA Propagating #01 #02 for BB05, stmt STMT00007, tree [000026], tree -> #NA Propagating #01 #02 for BB06, stmt STMT00008, tree [002596], tree -> #NA Propagating #01 #02 for BB06, stmt STMT00008, tree [002597], tree -> #NA Propagating #01 #02 for BB06, stmt STMT00008, tree [002595], tree -> #NA Propagating #01 #02 for BB06, stmt STMT00008, tree [000029], tree -> #NA Propagating #01 #02 for BB06, stmt STMT00008, tree [002594], tree -> #NA Propagating #01 #02 for BB06, stmt STMT00008, tree [000030], tree -> #NA Propagating #01 #02 for BB06, stmt STMT00008, tree [000033], tree -> #NA Propagating #01 #02 for BB06, stmt STMT00008, tree [000034], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00009, tree [000035], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00009, tree [000036], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00009, tree [000037], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00010, tree [000038], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00010, tree [000039], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00010, tree [000040], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00011, tree [000041], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00011, tree [000042], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00011, tree [000043], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00012, tree [000044], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00012, tree [000045], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00012, tree [000046], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00013, tree [002598], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00013, tree [000048], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00013, tree [000049], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00014, tree [000050], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00014, tree [000051], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00014, tree [000052], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00015, tree [002599], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00015, tree [000054], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00015, tree [000055], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00016, tree [000056], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00016, tree [000057], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00016, tree [000058], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00017, tree [000059], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00017, tree [000060], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00017, tree [000061], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00321, tree [003712], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00321, tree [002600], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00321, tree [002602], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00321, tree [002605], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00321, tree [002606], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00019, tree [001512], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00019, tree [000067], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00019, tree [000068], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00020, tree [000069], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00020, tree [002607], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00020, tree [002608], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00020, tree [002609], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00020, tree [002611], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00020, tree [000071], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00020, tree [000072], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00588, tree [003692], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00588, tree [003622], tree -> #NA Propagating #01 #02 for BB07, stmt STMT00588, tree [003623], tree -> #NA Propagating #01 #02 #22 #23 for BB08, stmt STMT00266, tree [001226], tree -> #NA Propagating #01 #02 #22 #23 for BB08, stmt STMT00266, tree [001227], tree -> #NA Propagating #01 #02 #22 #23 for BB08, stmt STMT00266, tree [001228], tree -> #NA Propagating #01 #02 #22 #23 for BB08, stmt STMT00266, tree [001229], tree -> #NA Propagating #01 #02 #22 #23 for BB09, stmt STMT00289, tree [001361], tree -> #NA Propagating #01 #02 #22 #23 for BB09, stmt STMT00289, tree [001362], tree -> #NA Propagating #01 #02 #22 #23 for BB09, stmt STMT00289, tree [001363], tree -> #NA Propagating #01 #02 #22 #23 for BB09, stmt STMT00289, tree [001364], tree -> #NA Propagating #01 #02 #22 #23 for BB10, stmt STMT00290, tree [001365], tree -> #NA Propagating #01 #02 #22 #23 for BB10, stmt STMT00290, tree [001366], tree -> #NA Propagating #01 #02 #22 #23 for BB10, stmt STMT00290, tree [001367], tree -> #NA Propagating #01 #02 #22 #23 for BB10, stmt STMT00290, tree [001368], tree -> #NA Propagating #01 #02 #22 #23 for BB11, stmt STMT00291, tree [001369], tree -> #NA Propagating #01 #02 #22 #23 for BB11, stmt STMT00291, tree [001370], tree -> #NA Propagating #01 #02 #22 #23 for BB11, stmt STMT00291, tree [001371], tree -> #NA Propagating #01 #02 #22 #23 for BB11, stmt STMT00291, tree [001372], tree -> #03 Propagating #01 #02 #22 #23 for BB13, stmt STMT00267, tree [001230], tree -> #NA Propagating #01 #02 #22 #23 for BB13, stmt STMT00267, tree [001231], tree -> #NA Propagating #01 #02 #22 #23 for BB13, stmt STMT00267, tree [001232], tree -> #NA Propagating #01 #02 #22 #23 for BB13, stmt STMT00267, tree [001233], tree -> #05 Propagating #01 #02 #06 #22 #23 for BB14, stmt STMT00272, tree [001257], tree -> #NA Propagating #01 #02 #06 #22 #23 for BB14, stmt STMT00272, tree [001258], tree -> #NA Propagating #01 #02 #06 #22 #23 for BB14, stmt STMT00272, tree [001259], tree -> #NA Propagating #01 #02 #06 #22 #23 for BB14, stmt STMT00272, tree [001260], tree -> #07 Propagating #01 #02 #06 #08 #22 #23 for BB15, stmt STMT00287, tree [001352], tree -> #NA Propagating #01 #02 #06 #08 #22 #23 for BB15, stmt STMT00287, tree [001353], tree -> #NA Propagating #01 #02 #06 #08 #22 #23 for BB15, stmt STMT00287, tree [001354], tree -> #NA Propagating #01 #02 #06 #08 #22 #23 for BB15, stmt STMT00287, tree [001355], tree -> #09 Propagating #01 #02 #04 #06 #08 #10 #22 #23 for BB16, stmt STMT00288, tree [001356], tree -> #NA Propagating #01 #02 #04 #06 #08 #10 #22 #23 for BB16, stmt STMT00288, tree [001357], tree -> #NA Propagating #01 #02 #04 #06 #08 #10 #22 #23 for BB16, stmt STMT00288, tree [001358], tree -> #NA Propagating #01 #02 #04 #06 #08 #10 #22 #23 for BB16, stmt STMT00288, tree [001359], tree -> #NA Propagating #01 #02 #04 #06 #08 #10 #22 #23 for BB16, stmt STMT00288, tree [001360], tree -> #NA Propagating #01 #02 #22 #23 for BB17, stmt STMT00307, tree [001430], tree -> #NA Propagating #01 #02 #22 #23 for BB17, stmt STMT00307, tree [001431], tree -> #NA Propagating #01 #02 #22 #23 for BB17, stmt STMT00307, tree [001432], tree -> #NA Propagating #01 #02 #22 #23 for BB17, stmt STMT00307, tree [001433], tree -> #NA Propagating #01 #02 #22 #23 for BB17, stmt STMT00307, tree [001434], tree -> #NA Propagating #01 #02 #22 #23 for BB18, stmt STMT00292, tree [001373], tree -> #NA Propagating #01 #02 #22 #23 for BB18, stmt STMT00292, tree [001374], tree -> #NA Propagating #01 #02 #22 #23 for BB18, stmt STMT00292, tree [001375], tree -> #NA Propagating #01 #02 #22 #23 for BB18, stmt STMT00292, tree [001376], tree -> #11 Propagating #01 #02 #12 #22 #23 for BB19, stmt STMT00295, tree [001385], tree -> #NA Propagating #01 #02 #12 #22 #23 for BB19, stmt STMT00295, tree [001386], tree -> #NA Propagating #01 #02 #12 #22 #23 for BB19, stmt STMT00295, tree [001387], tree -> #NA Propagating #01 #02 #22 #23 for BB20, stmt STMT00293, tree [001377], tree -> #NA Propagating #01 #02 #22 #23 for BB20, stmt STMT00293, tree [001378], tree -> #NA Propagating #01 #02 #22 #23 for BB20, stmt STMT00293, tree [001379], tree -> #NA Propagating #01 #02 #22 #23 for BB20, stmt STMT00293, tree [001380], tree -> #NA Propagating #01 #02 #22 #23 for BB20, stmt STMT00293, tree [001381], tree -> #NA Propagating #01 #02 #22 #23 for BB20, stmt STMT00294, tree [001382], tree -> #NA Propagating #01 #02 #22 #23 for BB20, stmt STMT00294, tree [001383], tree -> #NA Propagating #01 #02 #22 #23 for BB20, stmt STMT00294, tree [001384], tree -> #NA Propagating #01 #02 #22 #23 for BB21, stmt STMT00296, tree [001388], tree -> #NA Propagating #01 #02 #22 #23 for BB21, stmt STMT00296, tree [001389], tree -> #NA Propagating #01 #02 #22 #23 for BB21, stmt STMT00296, tree [001390], tree -> #NA Propagating #01 #02 #22 #23 for BB21, stmt STMT00296, tree [001391], tree -> #13 Propagating #01 #02 #14 #22 #23 for BB22, stmt STMT00297, tree [001392], tree -> #NA Propagating #01 #02 #14 #22 #23 for BB22, stmt STMT00297, tree [001393], tree -> #NA Propagating #01 #02 #14 #22 #23 for BB22, stmt STMT00297, tree [001394], tree -> #NA Propagating #01 #02 #22 #23 for BB23, stmt STMT00298, tree [001395], tree -> #NA Propagating #01 #02 #22 #23 for BB23, stmt STMT00298, tree [001396], tree -> #NA Propagating #01 #02 #22 #23 for BB23, stmt STMT00298, tree [001397], tree -> #NA Propagating #01 #02 #22 #23 for BB23, stmt STMT00298, tree [001398], tree -> #15 Propagating #01 #02 #16 #22 #23 for BB24, stmt STMT00299, tree [001399], tree -> #NA Propagating #01 #02 #16 #22 #23 for BB24, stmt STMT00299, tree [001400], tree -> #NA Propagating #01 #02 #16 #22 #23 for BB24, stmt STMT00299, tree [001401], tree -> #NA Propagating #01 #02 #16 #22 #23 for BB24, stmt STMT00299, tree [001402], tree -> #13 Propagating #01 #02 #14 #16 #22 #23 for BB25, stmt STMT00300, tree [001403], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB25, stmt STMT00300, tree [001404], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB25, stmt STMT00300, tree [001405], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB25, stmt STMT00300, tree [001406], tree -> #17 Propagating #01 #02 #14 #16 #18 #22 #23 for BB26, stmt STMT00303, tree [001413], tree -> #NA Propagating #01 #02 #14 #16 #18 #22 #23 for BB26, stmt STMT00303, tree [001414], tree -> #NA Propagating #01 #02 #14 #16 #18 #22 #23 for BB26, stmt STMT00303, tree [001415], tree -> #NA Propagating #01 #02 #14 #16 #18 #22 #23 for BB26, stmt STMT00303, tree [001416], tree -> #19 Propagating #01 #02 #14 #16 #18 #20 #22 #23 for BB27, stmt STMT00305, tree [001420], tree -> #NA Propagating #01 #02 #14 #16 #18 #20 #22 #23 for BB27, stmt STMT00305, tree [001421], tree -> #NA Propagating #01 #02 #14 #16 #18 #20 #22 #23 for BB27, stmt STMT00305, tree [001422], tree -> #NA Propagating #01 #02 #14 #16 #18 #20 #22 #23 for BB27, stmt STMT00305, tree [001423], tree -> #NA Propagating #01 #02 #14 #16 #18 #20 #22 #23 for BB27, stmt STMT00305, tree [001424], tree -> #NA Propagating #01 #02 #14 #16 #18 #19 #22 #23 for BB28, stmt STMT00304, tree [002612], tree -> #NA Propagating #01 #02 #14 #16 #18 #19 #22 #23 for BB28, stmt STMT00304, tree [001418], tree -> #NA Propagating #01 #02 #14 #16 #18 #19 #22 #23 for BB28, stmt STMT00304, tree [001419], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB29, stmt STMT00301, tree [001407], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB29, stmt STMT00301, tree [001408], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB29, stmt STMT00301, tree [001409], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB29, stmt STMT00302, tree [001410], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB29, stmt STMT00302, tree [001411], tree -> #NA Propagating #01 #02 #14 #16 #22 #23 for BB29, stmt STMT00302, tree [001412], tree -> #NA Propagating #01 #02 #22 #23 for BB30, stmt STMT00306, tree [001425], tree -> #NA Propagating #01 #02 #22 #23 for BB30, stmt STMT00306, tree [001426], tree -> #NA Propagating #01 #02 #22 #23 for BB30, stmt STMT00306, tree [001427], tree -> #NA Propagating #01 #02 #22 #23 for BB30, stmt STMT00306, tree [001428], tree -> #NA Propagating #01 #02 #22 #23 for BB30, stmt STMT00306, tree [001429], tree -> #NA Propagating #01 #02 #22 #23 for BB31, stmt STMT00309, tree [001435], tree -> #NA Propagating #01 #02 #22 #23 for BB31, stmt STMT00309, tree [003693], tree -> #NA Propagating #01 #02 #22 #23 for BB31, stmt STMT00309, tree [001440], tree -> #NA Propagating #01 #02 #22 #23 for BB31, stmt STMT00309, tree [001441], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001442], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001443], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001444], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001446], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001447], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001448], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001449], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [003624], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [003625], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [003626], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [003627], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001450], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001451], tree -> #NA Propagating #01 #02 #22 #23 for BB32, stmt STMT00310, tree [001452], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00312, tree [001454], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00312, tree [001460], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00312, tree [001461], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00311, tree [001455], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00311, tree [001456], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00311, tree [001457], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00311, tree [001458], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00311, tree [001459], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00313, tree [003628], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00313, tree [001469], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00313, tree [001470], tree -> #NA Propagating #01 #02 #22 #23 for BB33, stmt STMT00313, tree [001471], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB35, stmt STMT00269, tree [001234], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB35, stmt STMT00269, tree [003694], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB35, stmt STMT00269, tree [001239], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB35, stmt STMT00269, tree [001240], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001241], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001242], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001243], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001245], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001246], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001247], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001248], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [003644], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [003645], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [003646], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [003647], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001249], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001250], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB36, stmt STMT00270, tree [001251], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB37, stmt STMT00271, tree [001252], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB37, stmt STMT00271, tree [001253], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB37, stmt STMT00271, tree [001254], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB37, stmt STMT00271, tree [001255], tree -> #NA Propagating #01 #02 #04 #05 #08 #09 #22 #23 for BB37, stmt STMT00271, tree [001256], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB38, stmt STMT00274, tree [001261], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB38, stmt STMT00274, tree [003695], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB38, stmt STMT00274, tree [001266], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB38, stmt STMT00274, tree [001267], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001341], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001342], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001343], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001345], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001346], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001347], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001348], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [003648], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [003649], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [003650], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [003651], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001349], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001350], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB39, stmt STMT00286, tree [001351], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB40, stmt STMT00276, tree [001268], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB40, stmt STMT00276, tree [001269], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB40, stmt STMT00276, tree [001270], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB40, stmt STMT00276, tree [003696], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB40, stmt STMT00276, tree [001275], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB40, stmt STMT00276, tree [001276], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001277], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001278], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001279], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001281], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001282], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001283], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001284], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [003652], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [003653], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [003654], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [003655], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001285], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001286], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB41, stmt STMT00277, tree [001287], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB42, stmt STMT00285, tree [003656], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB42, stmt STMT00285, tree [001338], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB42, stmt STMT00285, tree [001339], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB42, stmt STMT00285, tree [001340], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001288], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001289], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001290], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001291], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001292], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001294], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001295], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001296], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001297], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001298], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001299], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB43, stmt STMT00278, tree [001300], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00279, tree [001301], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00279, tree [001302], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00279, tree [001303], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00279, tree [001304], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00279, tree [001305], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00280, tree [001307], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00280, tree [001308], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00280, tree [001309], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00282, tree [001306], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00282, tree [003697], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00282, tree [001314], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB44, stmt STMT00282, tree [001315], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001319], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001320], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001321], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001323], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001324], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001325], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001326], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001327], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001328], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB45, stmt STMT00284, tree [001329], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB46, stmt STMT00283, tree [002613], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB46, stmt STMT00283, tree [001317], tree -> #NA Propagating #01 #02 #06 #09 #22 #23 for BB46, stmt STMT00283, tree [001318], tree -> #NA Propagating #01 #02 for BB47, stmt STMT00022, tree [000073], tree -> #NA Propagating #01 #02 for BB47, stmt STMT00022, tree [003698], tree -> #NA Propagating #01 #02 for BB47, stmt STMT00022, tree [000078], tree -> #NA Propagating #01 #02 for BB47, stmt STMT00022, tree [000079], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00261, tree [001198], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00261, tree [001204], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00261, tree [001205], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00260, tree [001199], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00260, tree [001200], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00260, tree [001201], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00260, tree [001202], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00260, tree [001203], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001197], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001206], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001207], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001209], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001210], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001211], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001212], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001213], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00262, tree [001214], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00263, tree [001216], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00263, tree [001217], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00263, tree [001218], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00264, tree [001215], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00264, tree [001219], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00264, tree [001220], tree -> #NA Propagating #01 #02 for BB48, stmt STMT00264, tree [001221], tree -> #21 Propagating #01 #02 #22 for BB49, stmt STMT00265, tree [001222], tree -> #NA Propagating #01 #02 #22 for BB49, stmt STMT00265, tree [001223], tree -> #NA Propagating #01 #02 #22 for BB49, stmt STMT00265, tree [001224], tree -> #NA Propagating #01 #02 #22 for BB49, stmt STMT00265, tree [001225], tree -> #23 Propagating #01 #02 for BB50, stmt STMT00023, tree [000081], tree -> #NA Propagating #01 #02 for BB50, stmt STMT00023, tree [000082], tree -> #NA Propagating #01 #02 for BB50, stmt STMT00023, tree [000083], tree -> #NA Propagating #01 #02 for BB50, stmt STMT00024, tree [000084], tree -> #NA Propagating #01 #02 for BB50, stmt STMT00024, tree [000085], tree -> #NA Propagating #01 #02 for BB50, stmt STMT00024, tree [000086], tree -> #NA Propagating #01 #02 for BB50, stmt STMT00024, tree [000087], tree -> #13 Propagating #01 #02 #14 for BB51, stmt STMT00259, tree [001194], tree -> #NA Propagating #01 #02 #14 for BB51, stmt STMT00259, tree [001195], tree -> #NA Propagating #01 #02 #14 for BB51, stmt STMT00259, tree [001196], tree -> #NA Propagating #01 #02 for BB52, stmt STMT00025, tree [000088], tree -> #NA Propagating #01 #02 for BB52, stmt STMT00025, tree [000089], tree -> #NA Propagating #01 #02 for BB52, stmt STMT00025, tree [000090], tree -> #NA Propagating #01 #02 for BB52, stmt STMT00025, tree [000091], tree -> #17 Propagating #01 #02 #18 for BB53, stmt STMT00256, tree [001180], tree -> #NA Propagating #01 #02 #18 for BB53, stmt STMT00256, tree [001181], tree -> #NA Propagating #01 #02 #18 for BB53, stmt STMT00256, tree [001182], tree -> #NA Propagating #01 #02 #18 for BB53, stmt STMT00256, tree [001183], tree -> #25 Propagating #01 #02 #18 #26 for BB54, stmt STMT00258, tree [001187], tree -> #NA Propagating #01 #02 #18 #26 for BB54, stmt STMT00258, tree [001188], tree -> #NA Propagating #01 #02 #18 #26 for BB54, stmt STMT00258, tree [001189], tree -> #NA Propagating #01 #02 #18 #26 for BB54, stmt STMT00258, tree [001190], tree -> #NA Propagating #01 #02 #18 #26 for BB54, stmt STMT00258, tree [001191], tree -> #NA Propagating #01 #02 #18 #26 for BB54, stmt STMT00258, tree [001192], tree -> #NA Propagating #01 #02 #18 #26 for BB54, stmt STMT00258, tree [001193], tree -> #NA Propagating #01 #02 #18 #25 for BB55, stmt STMT00257, tree [002615], tree -> #NA Propagating #01 #02 #18 #25 for BB55, stmt STMT00257, tree [001185], tree -> #NA Propagating #01 #02 #18 #25 for BB55, stmt STMT00257, tree [001186], tree -> #NA Propagating #01 #02 for BB56, stmt STMT00026, tree [000092], tree -> #NA Propagating #01 #02 for BB56, stmt STMT00026, tree [000093], tree -> #NA Propagating #01 #02 for BB56, stmt STMT00026, tree [000094], tree -> #NA Propagating #01 #02 for BB56, stmt STMT00026, tree [000095], tree -> #NA Propagating #01 #02 for BB56, stmt STMT00026, tree [000096], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00245, tree [002618], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00245, tree [002619], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00245, tree [002620], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00245, tree [001128], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00245, tree [001129], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00246, tree [001131], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00246, tree [001132], tree -> #01 VN based non-null prop in BB57: N002 ( 3, 2) [001132] ---XG------ * IND int Propagating #01 #02 for BB57, stmt STMT00246, tree [001133], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00246, tree [001134], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00246, tree [001130], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00246, tree [001135], tree -> #NA VN based non-null prop in BB57: N006 ( 3, 2) [001135] D--XG--N--- * IND int $301 Propagating #01 #02 for BB57, stmt STMT00246, tree [001136], tree -> #01 Re-morphing this stmt: STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A-XG---R-- * ASG int $301 N006 ( 3, 2) [001135] n---GO-N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ---XG------ \--* ADD int N002 ( 3, 2) [001132] n---GO----- +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e optAssertionPropMain morphed tree: N007 ( 9, 7) [001136] -A--GO--R-- * ASG int $301 N006 ( 3, 2) [001135] n---GO-N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ----GO----- \--* ADD int N002 ( 3, 2) [001132] n---GO----- +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e Propagating #01 #02 for BB57, stmt STMT00247, tree [001137], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00247, tree [001138], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00247, tree [001139], tree -> #NA Propagating #01 #02 for BB57, stmt STMT00247, tree [001140], tree -> #27 Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [001171], tree -> #NA Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [002622], tree -> #NA Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [002623], tree -> #NA Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [001172], tree -> #01 VN based non-null prop in BB58: N004 ( 4, 3) [001172] ---XG------ * IND int Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [001173], tree -> #NA Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [001174], tree -> #NA Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [001175], tree -> #NA Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [001176], tree -> #NA Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [001177], tree -> #NA Propagating #01 #02 #28 for BB58, stmt STMT00255, tree [001178], tree -> #NA Re-morphing this stmt: STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A-XG---R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ---XG------ \--* SUB int N006 ( 6, 5) [001174] ---XG------ +--* ADD int N004 ( 4, 3) [001172] n---GO----- | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d optAssertionPropMain morphed tree: N010 ( 8, 7) [001178] -A--GO--R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ----GO----- \--* SUB int N006 ( 6, 5) [001174] ----GO----- +--* ADD int N004 ( 4, 3) [001172] n---GO----- | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d Propagating #01 #02 #27 for BB59, stmt STMT00248, tree [001141], tree -> #NA Propagating #01 #02 #27 for BB59, stmt STMT00248, tree [001142], tree -> #NA Propagating #01 #02 #27 for BB59, stmt STMT00248, tree [001143], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00250, tree [001145], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00250, tree [001148], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00250, tree [002624], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00250, tree [001150], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00250, tree [001151], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00251, tree [001152], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00251, tree [001153], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00251, tree [001154], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00251, tree [001155], tree -> #NA Propagating #01 #02 for BB60, stmt STMT00251, tree [001156], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00252, tree [003713], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00252, tree [002628], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00252, tree [002626], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00252, tree [002625], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00252, tree [001158], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00252, tree [001159], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00252, tree [001162], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00252, tree [001163], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00253, tree [001164], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00253, tree [001165], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00253, tree [001166], tree -> #NA Propagating #01 #02 for BB61, stmt STMT00253, tree [001167], tree -> #29 Propagating #01 #02 #30 for BB62, stmt STMT00254, tree [001168], tree -> #NA Propagating #01 #02 #30 for BB62, stmt STMT00254, tree [001169], tree -> #NA Propagating #01 #02 #30 for BB62, stmt STMT00254, tree [001170], tree -> #NA Propagating #01 #02 for BB63, stmt STMT00027, tree [000097], tree -> #NA Propagating #01 #02 for BB63, stmt STMT00027, tree [002629], tree -> #NA Propagating #01 #02 for BB63, stmt STMT00027, tree [002630], tree -> #NA Propagating #01 #02 for BB63, stmt STMT00027, tree [000098], tree -> #01 VN based non-null prop in BB63: N004 ( 5, 4) [000098] ---XG------ * IND ubyte Propagating #01 #02 for BB63, stmt STMT00027, tree [000099], tree -> #NA Propagating #01 #02 for BB63, stmt STMT00027, tree [000100], tree -> #NA Propagating #01 #02 for BB63, stmt STMT00027, tree [000101], tree -> #NA Re-morphing this stmt: STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000100] J--XG--N--- \--* EQ int N004 ( 5, 4) [000098] n---GO----- +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 optAssertionPropMain morphed tree: N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000100] J---GO-N--- \--* EQ int N004 ( 5, 4) [000098] n---GO----- +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 Propagating #01 #02 for BB64, stmt STMT00244, tree [001122], tree -> #NA Propagating #01 #02 for BB64, stmt STMT00244, tree [002631], tree -> #NA Propagating #01 #02 for BB64, stmt STMT00244, tree [002632], tree -> #NA Propagating #01 #02 for BB64, stmt STMT00244, tree [001124], tree -> #NA VN based non-null prop in BB64: N004 ( 5, 4) [001124] D--XG--N--- * IND bool $301 Propagating #01 #02 for BB64, stmt STMT00244, tree [001123], tree -> #NA Propagating #01 #02 for BB64, stmt STMT00244, tree [001125], tree -> #01 Re-morphing this stmt: STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A-XG------ * ASG bool $301 N004 ( 5, 4) [001124] n---GO-N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 optAssertionPropMain morphed tree: N006 ( 7, 7) [001125] -A--GO----- * ASG bool $301 N004 ( 5, 4) [001124] n---GO-N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 Propagating #01 #02 for BB65, stmt STMT00028, tree [000102], tree -> #NA Propagating #01 #02 for BB65, stmt STMT00028, tree [002633], tree -> #NA Propagating #01 #02 for BB65, stmt STMT00028, tree [002634], tree -> #NA Propagating #01 #02 for BB65, stmt STMT00028, tree [000104], tree -> #NA VN based non-null prop in BB65: N004 ( 4, 3) [000104] D--XG--N--- * IND int $301 Propagating #01 #02 for BB65, stmt STMT00028, tree [000103], tree -> #NA Propagating #01 #02 for BB65, stmt STMT00028, tree [000105], tree -> #01 Re-morphing this stmt: STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A-XG------ * ASG int $301 N004 ( 4, 3) [000104] n---GO-N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 optAssertionPropMain morphed tree: N006 ( 6, 6) [000105] -A--GO----- * ASG int $301 N004 ( 4, 3) [000104] n---GO-N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 Propagating #01 #02 for BB66, stmt STMT00029, tree [000106], tree -> #NA Propagating #01 #02 for BB66, stmt STMT00029, tree [000107], tree -> #NA Propagating #01 #02 for BB66, stmt STMT00029, tree [000108], tree -> #NA Propagating #01 #02 for BB66, stmt STMT00029, tree [000109], tree -> #NA Propagating #01 #02 for BB67, stmt STMT00243, tree [001118], tree -> #NA Propagating #01 #02 for BB67, stmt STMT00243, tree [001119], tree -> #NA Propagating #01 #02 for BB67, stmt STMT00243, tree [001120], tree -> #NA Propagating #01 #02 for BB68, stmt STMT00030, tree [000110], tree -> #NA Propagating #01 #02 for BB68, stmt STMT00030, tree [000111], tree -> #NA Propagating #01 #02 for BB68, stmt STMT00030, tree [000112], tree -> #NA Propagating #01 #02 for BB68, stmt STMT00030, tree [000113], tree -> #NA Propagating #01 #02 for BB68, stmt STMT00030, tree [000114], tree -> #NA Propagating #01 #02 for BB69, stmt STMT00031, tree [000116], tree -> #NA Propagating #01 #02 for BB69, stmt STMT00031, tree [000117], tree -> #NA Propagating #01 #02 for BB69, stmt STMT00031, tree [000118], tree -> #NA Propagating #01 #02 for BB69, stmt STMT00032, tree [000119], tree -> #NA Propagating #01 #02 for BB69, stmt STMT00032, tree [000120], tree -> #NA Propagating #01 #02 for BB69, stmt STMT00032, tree [000121], tree -> #NA Propagating #01 #02 for BB69, stmt STMT00032, tree [000122], tree -> #NA Propagating #01 #02 for BB70, stmt STMT00242, tree [001114], tree -> #NA Propagating #01 #02 for BB70, stmt STMT00242, tree [001115], tree -> #NA Propagating #01 #02 for BB70, stmt STMT00242, tree [001116], tree -> #NA Propagating #01 #02 for BB71, stmt STMT00033, tree [000123], tree -> #NA Propagating #01 #02 for BB71, stmt STMT00033, tree [000124], tree -> #NA Propagating #01 #02 for BB71, stmt STMT00033, tree [000125], tree -> #NA Propagating #01 #02 for BB71, stmt STMT00033, tree [000126], tree -> #NA Propagating #01 #02 for BB71, stmt STMT00033, tree [000127], tree -> #NA Propagating #01 #02 for BB72, stmt STMT00034, tree [000129], tree -> #NA Propagating #01 #02 for BB72, stmt STMT00034, tree [000130], tree -> #NA Propagating #01 #02 for BB72, stmt STMT00034, tree [000131], tree -> #NA Propagating #01 #02 for BB72, stmt STMT00035, tree [000132], tree -> #NA Propagating #01 #02 for BB72, stmt STMT00035, tree [000133], tree -> #NA Propagating #01 #02 for BB72, stmt STMT00035, tree [000134], tree -> #NA Propagating #01 #02 for BB72, stmt STMT00035, tree [000135], tree -> #28 Propagating #01 #02 #27 for BB73, stmt STMT00240, tree [001108], tree -> #NA Propagating #01 #02 #27 for BB73, stmt STMT00240, tree [001109], tree -> #NA Propagating #01 #02 #27 for BB73, stmt STMT00240, tree [001110], tree -> #NA Propagating #01 #02 #27 for BB73, stmt STMT00241, tree [001111], tree -> #NA Propagating #01 #02 #27 for BB73, stmt STMT00241, tree [001112], tree -> #NA Propagating #01 #02 #27 for BB73, stmt STMT00241, tree [001113], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [000136], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [002635], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [002636], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [000137], tree -> #01 VN based non-null prop in BB74: N004 ( 4, 3) [000137] ---XG------ * IND int Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [003682], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [003683], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [003684], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [003685], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [000138], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [000139], tree -> #NA Propagating #01 #02 #28 for BB74, stmt STMT00036, tree [000140], tree -> #NA Re-morphing this stmt: STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N011 ( 15, 12) [000140] -A-XG------ * JTRUE void $301 N010 ( 13, 10) [000139] JA-XG--N--- \--* GT int N008 ( 11, 8) [003685] -A-XG------ +--* COMMA int N006 ( 8, 6) [003683] -A-XG---R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d optAssertionPropMain morphed tree: N011 ( 15, 12) [000140] -A--GO----- * JTRUE void $301 N010 ( 13, 10) [000139] JA--GO-N--- \--* GT int N008 ( 11, 8) [003685] -A--GO----- +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d Propagating #01 #02 #28 for BB75, stmt STMT00239, tree [001104], tree -> #NA Propagating #01 #02 #28 for BB75, stmt STMT00239, tree [001105], tree -> #NA Propagating #01 #02 #28 for BB75, stmt STMT00239, tree [001106], tree -> #NA Propagating #01 #02 #28 for BB76, stmt STMT00037, tree [003686], tree -> #NA Propagating #01 #02 #28 for BB76, stmt STMT00037, tree [000143], tree -> #NA Propagating #01 #02 #28 for BB76, stmt STMT00037, tree [000144], tree -> #NA Propagating #01 #02 #28 for BB77, stmt STMT00038, tree [000146], tree -> #NA Propagating #01 #02 #28 for BB77, stmt STMT00038, tree [000147], tree -> #NA Propagating #01 #02 #28 for BB77, stmt STMT00038, tree [000148], tree -> #NA Propagating #01 #02 #28 for BB77, stmt STMT00039, tree [003687], tree -> #NA Propagating #01 #02 #28 for BB77, stmt STMT00039, tree [000151], tree -> #NA Propagating #01 #02 #28 for BB77, stmt STMT00039, tree [000152], tree -> #NA Propagating #01 #02 #28 for BB77, stmt STMT00039, tree [000153], tree -> #NA Propagating #01 #02 #28 for BB77, stmt STMT00039, tree [000154], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00040, tree [000155], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00040, tree [000156], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00040, tree [000157], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00041, tree [002643], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00041, tree [002646], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00041, tree [002647], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00324, tree [001550], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00324, tree [001552], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00324, tree [001553], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00325, tree [001556], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00325, tree [001557], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00325, tree [001558], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00044, tree [002649], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00044, tree [002648], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00044, tree [002650], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00044, tree [003720], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00044, tree [002651], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00044, tree [002653], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00044, tree [002654], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00045, tree [000175], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00045, tree [000176], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00045, tree [000177], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00046, tree [000178], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00046, tree [000179], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00046, tree [000180], tree -> #NA Propagating #01 #02 for BB78, stmt STMT00046, tree [000181], tree -> #31 Propagating #01 #02 #32 for BB79, stmt STMT00203, tree [000941], tree -> #NA Propagating #01 #02 #32 for BB79, stmt STMT00203, tree [002655], tree -> #NA Propagating #01 #02 #32 for BB79, stmt STMT00203, tree [002656], tree -> #NA Propagating #01 #02 #32 for BB79, stmt STMT00203, tree [001570], tree -> #33 Propagating #01 #02 #32 #33 for BB79, stmt STMT00203, tree [000944], tree -> #NA Propagating #01 #02 #32 #33 for BB79, stmt STMT00203, tree [000945], tree -> #NA Propagating #01 #02 #32 #33 for BB79, stmt STMT00203, tree [000946], tree -> #NA Propagating #01 #02 #32 #33 for BB79, stmt STMT00203, tree [000947], tree -> #34 Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00204, tree [000948], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00204, tree [002657], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00204, tree [002658], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00204, tree [000949], tree -> #33 VN based non-null prop in BB80: N004 ( 4, 3) [000949] ---XG------ * IND ref Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00204, tree [000950], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00204, tree [000951], tree -> #NA Re-morphing this stmt: STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] n---GO----- \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 optAssertionPropMain morphed tree: N006 ( 4, 3) [000951] -A--GO--R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] n---GO----- \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00205, tree [000952], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00205, tree [000953], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00205, tree [000954], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00206, tree [000955], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00206, tree [000956], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00206, tree [000957], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00207, tree [000958], tree -> #NA Propagating #01 #02 #32 #33 #35 for BB80, stmt STMT00207, tree [000959], tree -> #36 Propagating #01 #02 #32 #33 #35 #36 for BB80, stmt STMT00207, tree [000960], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB80, stmt STMT00207, tree [000961], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB80, stmt STMT00208, tree [000962], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB80, stmt STMT00208, tree [000963], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB80, stmt STMT00208, tree [000964], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB80, stmt STMT00208, tree [000965], tree -> #37 Propagating #01 #02 #32 #33 #35 #36 #38 for BB81, stmt STMT00238, tree [003721], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 for BB81, stmt STMT00238, tree [001098], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 for BB81, stmt STMT00238, tree [002661], tree -> #36 Propagating #01 #02 #32 #33 #35 #36 #38 for BB81, stmt STMT00238, tree [002662], tree -> #39 Propagating #01 #02 #32 #33 #35 #36 #38 #39 for BB81, stmt STMT00238, tree [002659], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 #39 for BB81, stmt STMT00238, tree [002666], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 #39 for BB81, stmt STMT00238, tree [002667], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 #39 for BB81, stmt STMT00238, tree [002669], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 #39 for BB81, stmt STMT00238, tree [002671], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 #39 for BB81, stmt STMT00238, tree [002670], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 #39 for BB81, stmt STMT00238, tree [001102], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #38 #39 for BB81, stmt STMT00238, tree [001103], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00209, tree [000966], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00209, tree [000967], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00209, tree [000968], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00211, tree [000969], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00211, tree [000974], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00211, tree [000975], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00210, tree [000970], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00210, tree [000971], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00210, tree [000972], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB82, stmt STMT00210, tree [000973], tree -> #40 Propagating #01 #02 #32 #33 #35 #36 #41 for BB83, stmt STMT00236, tree [000977], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #41 for BB83, stmt STMT00236, tree [001092], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #41 for BB83, stmt STMT00236, tree [001093], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #41 for BB83, stmt STMT00237, tree [001091], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #41 for BB83, stmt STMT00237, tree [001095], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #41 for BB83, stmt STMT00237, tree [001096], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #40 for BB84, stmt STMT00212, tree [000978], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #40 for BB84, stmt STMT00212, tree [000980], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #40 for BB84, stmt STMT00212, tree [000981], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #40 for BB84, stmt STMT00213, tree [000979], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #40 for BB84, stmt STMT00213, tree [000983], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #40 for BB84, stmt STMT00213, tree [000984], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00214, tree [000986], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00214, tree [000987], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00214, tree [000988], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00214, tree [000989], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00214, tree [000990], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00215, tree [000991], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00215, tree [000992], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00215, tree [000993], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB85, stmt STMT00215, tree [000994], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB86, stmt STMT00235, tree [001087], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB86, stmt STMT00235, tree [001088], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB86, stmt STMT00235, tree [001089], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB87, stmt STMT00216, tree [000995], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB87, stmt STMT00216, tree [000996], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB87, stmt STMT00216, tree [000997], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB88, stmt STMT00217, tree [000999], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB88, stmt STMT00217, tree [001000], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB88, stmt STMT00217, tree [001001], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB88, stmt STMT00502, tree [003158], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB88, stmt STMT00502, tree [003159], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB88, stmt STMT00502, tree [003157], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB88, stmt STMT00502, tree [003156], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB89, stmt STMT00219, tree [001006], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB89, stmt STMT00219, tree [001007], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB89, stmt STMT00219, tree [001008], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 for BB89, stmt STMT00219, tree [001009], tree -> #42 Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00220, tree [001010], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00220, tree [001011], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00220, tree [001012], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00220, tree [001013], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00220, tree [001014], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00222, tree [001015], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00222, tree [001574], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00222, tree [001020], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB90, stmt STMT00222, tree [001021], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00229, tree [001578], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00229, tree [001065], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00229, tree [001066], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00229, tree [001067], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00229, tree [002672], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00229, tree [001068], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00229, tree [001069], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00229, tree [001070], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00327, tree [002675], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00327, tree [002678], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB91, stmt STMT00327, tree [002679], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB92, stmt STMT00333, tree [002681], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB92, stmt STMT00333, tree [002680], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB92, stmt STMT00333, tree [002682], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB92, stmt STMT00333, tree [002684], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB92, stmt STMT00333, tree [002683], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB92, stmt STMT00333, tree [002685], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB92, stmt STMT00333, tree [002686], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB93, stmt STMT00331, tree [002689], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB93, stmt STMT00331, tree [002690], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB93, stmt STMT00331, tree [002691], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB93, stmt STMT00331, tree [001603], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB93, stmt STMT00331, tree [001604], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB93, stmt STMT00332, tree [001607], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB93, stmt STMT00332, tree [001608], tree -> #44 Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB93, stmt STMT00332, tree [001609], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB93, stmt STMT00332, tree [001610], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00339, tree [002694], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00339, tree [002693], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00339, tree [002695], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00339, tree [002698], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00339, tree [002699], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00336, tree [001620], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00336, tree [001647], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00336, tree [001628], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB94, stmt STMT00336, tree [001629], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00346, tree [001639], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00346, tree [001640], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00346, tree [001672], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00346, tree [001673], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00343, tree [001663], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00343, tree [001665], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00343, tree [001666], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00343, tree [001661], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00343, tree [001662], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00343, tree [002700], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00343, tree [001667], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00351, tree [002704], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00351, tree [002707], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB96, stmt STMT00351, tree [002708], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB97, stmt STMT00357, tree [002710], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB97, stmt STMT00357, tree [002709], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB97, stmt STMT00357, tree [002711], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB97, stmt STMT00357, tree [002713], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB97, stmt STMT00357, tree [002712], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB97, stmt STMT00357, tree [002714], tree -> #NA Propagating #01 #02 #03 #04 #05 #06 #07 #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 #44 #45 #46 #47 #48 #49 #50 #51 #52 #53 #54 #55 #56 #57 #58 #59 #60 #61 #62 #63 #64 for BB97, stmt STMT00357, tree [002715], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00355, tree [002718], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00355, tree [002719], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00355, tree [002720], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00355, tree [001715], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00355, tree [001716], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00356, tree [001719], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00356, tree [001720], tree -> #44 Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00356, tree [001721], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB98, stmt STMT00356, tree [001722], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB99, stmt STMT00234, tree [002723], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB99, stmt STMT00234, tree [002722], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB99, stmt STMT00234, tree [002724], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB99, stmt STMT00234, tree [002726], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB99, stmt STMT00234, tree [002725], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB99, stmt STMT00234, tree [002727], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB99, stmt STMT00234, tree [002728], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB100, stmt STMT00223, tree [001024], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB100, stmt STMT00223, tree [001028], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 for BB100, stmt STMT00223, tree [001029], tree -> #45 Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001033], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001025], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001030], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001031], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001032], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001034], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [002729], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001035], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001036], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00223, tree [001038], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00224, tree [001039], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00224, tree [001040], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00224, tree [001041], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00224, tree [001042], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00224, tree [001043], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB100, stmt STMT00224, tree [001044], tree -> #46 Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00226, tree [001050], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00226, tree [001051], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00226, tree [001052], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00226, tree [001053], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00226, tree [001054], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00227, tree [001056], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00227, tree [001055], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00227, tree [002732], tree -> #36 Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 for BB101, stmt STMT00227, tree [002733], tree -> #48 Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002730], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002737], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002738], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002731], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002734], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002735], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002736], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002739], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002740], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002742], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [002741], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [001059], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 for BB101, stmt STMT00227, tree [001060], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00225, tree [001045], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00225, tree [001046], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00225, tree [001047], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00225, tree [001048], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00225, tree [001049], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00218, tree [001002], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00218, tree [001003], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00218, tree [001004], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #45 for BB102, stmt STMT00218, tree [001005], tree -> #NA Propagating #01 #02 for BB103, stmt STMT00047, tree [000182], tree -> #NA Propagating #01 #02 for BB103, stmt STMT00047, tree [002743], tree -> #NA Propagating #01 #02 for BB103, stmt STMT00047, tree [002744], tree -> #NA Propagating #01 #02 for BB103, stmt STMT00047, tree [000183], tree -> #01 VN based non-null prop in BB103: N004 ( 5, 4) [000183] ---XG------ * IND bool Propagating #01 #02 for BB103, stmt STMT00047, tree [000184], tree -> #NA Propagating #01 #02 for BB103, stmt STMT00047, tree [000185], tree -> #NA Propagating #01 #02 for BB103, stmt STMT00047, tree [000186], tree -> #NA Re-morphing this stmt: STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000185] J--XG--N--- \--* EQ int N004 ( 5, 4) [000183] n---GO----- +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 optAssertionPropMain morphed tree: N007 ( 9, 9) [000186] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000185] J---GO-N--- \--* EQ int N004 ( 5, 4) [000183] n---GO----- +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 Propagating #01 #02 for BB104, stmt STMT00198, tree [000927], tree -> #NA Propagating #01 #02 for BB104, stmt STMT00198, tree [000928], tree -> #NA Propagating #01 #02 for BB104, stmt STMT00198, tree [000929], tree -> #NA Propagating #01 #02 for BB104, stmt STMT00198, tree [000930], tree -> #49 Propagating #01 #02 #50 for BB105, stmt STMT00199, tree [000931], tree -> #NA Propagating #01 #02 #50 for BB105, stmt STMT00199, tree [002745], tree -> #NA Propagating #01 #02 #50 for BB105, stmt STMT00199, tree [002746], tree -> #NA Propagating #01 #02 #50 for BB105, stmt STMT00199, tree [000932], tree -> #01 VN based non-null prop in BB105: N004 ( 4, 3) [000932] ---XG------ * IND int Propagating #01 #02 #50 for BB105, stmt STMT00199, tree [000933], tree -> #NA Propagating #01 #02 #50 for BB105, stmt STMT00199, tree [000934], tree -> #NA Propagating #01 #02 #50 for BB105, stmt STMT00199, tree [000935], tree -> #NA Re-morphing this stmt: STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000934] J--XG--N--- \--* EQ int N004 ( 4, 3) [000932] n---GO----- +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 optAssertionPropMain morphed tree: N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000934] J---GO-N--- \--* EQ int N004 ( 4, 3) [000932] n---GO----- +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 Propagating #01 #02 #50 for BB106, stmt STMT00367, tree [000937], tree -> #NA Propagating #01 #02 #50 for BB106, stmt STMT00367, tree [002747], tree -> #NA Propagating #01 #02 #50 for BB106, stmt STMT00367, tree [002748], tree -> #NA Propagating #01 #02 #50 for BB106, stmt STMT00367, tree [001730], tree -> #33 Propagating #01 #02 #33 #50 for BB106, stmt STMT00367, tree [001782], tree -> #NA Propagating #01 #02 #33 #50 for BB106, stmt STMT00367, tree [001783], tree -> #NA Propagating #01 #02 #33 #50 for BB106, stmt STMT00358, tree [001732], tree -> #NA Propagating #01 #02 #33 #50 for BB106, stmt STMT00358, tree [001733], tree -> #NA Propagating #01 #02 #33 #50 for BB106, stmt STMT00358, tree [001734], tree -> #NA Propagating #01 #02 #33 #50 for BB106, stmt STMT00358, tree [001735], tree -> #51 Propagating #01 #02 #33 #50 #52 for BB107, stmt STMT00359, tree [000936], tree -> #NA Propagating #01 #02 #33 #50 #52 for BB107, stmt STMT00359, tree [002749], tree -> #NA Propagating #01 #02 #33 #50 #52 for BB107, stmt STMT00359, tree [002750], tree -> #NA Propagating #01 #02 #33 #50 #52 for BB107, stmt STMT00359, tree [001736], tree -> #53 Propagating #01 #02 #33 #50 #52 #53 for BB107, stmt STMT00359, tree [001737], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB107, stmt STMT00359, tree [001738], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB107, stmt STMT00360, tree [001739], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB107, stmt STMT00360, tree [001740], tree -> #52 Propagating #01 #02 #33 #50 #52 #53 for BB107, stmt STMT00360, tree [001741], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB107, stmt STMT00360, tree [001742], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB107, stmt STMT00360, tree [001743], tree -> #54 Propagating #01 #02 #33 #50 #52 #53 #54 for BB108, stmt STMT00363, tree [001747], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB108, stmt STMT00363, tree [001748], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB108, stmt STMT00363, tree [002753], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB108, stmt STMT00363, tree [002754], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB108, stmt STMT00363, tree [001786], tree -> #53 VN based non-null prop in BB108: N005 ( 4, 3) [001786] ---XG------ * IND int Propagating #01 #02 #33 #50 #52 #53 #54 for BB108, stmt STMT00363, tree [001752], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB108, stmt STMT00363, tree [001753], tree -> #NA Re-morphing this stmt: STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ---XG------ * JTRUE void $845 N006 ( 8, 6) [001752] N--XG--N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] n---GO----- \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 10, 8) [001753] ----GO----- * JTRUE void $845 N006 ( 8, 6) [001752] N---GO-N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] n---GO----- \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00364, tree [002758], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00364, tree [002759], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00364, tree [002760], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00364, tree [001758], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00364, tree [001759], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00365, tree [001756], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00365, tree [001761], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00365, tree [002762], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00365, tree [002763], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00365, tree [001762], tree -> #53 VN based non-null prop in BB109: N005 ( 4, 3) [001762] ---XG------ * IND int Propagating #01 #02 #33 #50 #52 #53 #54 for BB109, stmt STMT00365, tree [001763], tree -> #55 Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001760], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001767], tree -> #53 VN based non-null prop in BB109: N008 ( 3, 2) [001767] ---XG------ * IND byref Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001757], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001764], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001765], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001766], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001768], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [002764], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001769], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001771], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [001770], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [002767], tree -> #52 Propagating #01 #02 #33 #50 #52 #53 #54 #55 for BB109, stmt STMT00365, tree [002768], tree -> #56 Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00365, tree [002765], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00365, tree [002771], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00365, tree [002772], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00365, tree [002774], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00365, tree [002777], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00365, tree [002775], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00365, tree [001775], tree -> #NA Re-morphing this stmt: STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d optAssertionPropMain morphed tree: N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00366, tree [001777], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00366, tree [001778], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00366, tree [001779], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00366, tree [001776], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00366, tree [002778], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00366, tree [002779], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00366, tree [001780], tree -> #NA VN based non-null prop in BB109: N007 ( 4, 3) [001780] D--XG--N--- * IND int $845 Propagating #01 #02 #33 #50 #52 #53 #54 #55 #56 for BB109, stmt STMT00366, tree [001781], tree -> #53 Re-morphing this stmt: STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001780] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 10, 9) [001781] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001780] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB110, stmt STMT00337, tree [002701], tree -> #NA Propagating #01 #02 #32 #33 #35 #36 #43 #44 for BB110, stmt STMT00337, tree [001630], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB111, stmt STMT00361, tree [001744], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB111, stmt STMT00361, tree [001745], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB111, stmt STMT00361, tree [002780], tree -> #NA Propagating #01 #02 #33 #50 #52 #53 for BB111, stmt STMT00361, tree [001746], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00048, tree [002781], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00048, tree [000188], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00048, tree [000189], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00369, tree [003714], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00369, tree [002782], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00369, tree [002784], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00369, tree [002787], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00369, tree [002788], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00050, tree [001792], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00050, tree [000195], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00050, tree [000196], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00051, tree [000197], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00051, tree [002789], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00051, tree [002790], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00051, tree [002791], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00051, tree [002793], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00051, tree [000199], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00051, tree [000200], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00052, tree [000201], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00052, tree [000202], tree -> #NA Propagating #01 #02 for BB112, stmt STMT00052, tree [000203], tree -> #NA Propagating #01 #02 for BB113, stmt STMT00070, tree [000271], tree -> #NA Propagating #01 #02 for BB113, stmt STMT00070, tree [000272], tree -> #NA Propagating #01 #02 for BB113, stmt STMT00070, tree [000273], tree -> #NA Propagating #01 #02 for BB113, stmt STMT00070, tree [000274], tree -> #57 Propagating #01 #02 #58 for BB114, stmt STMT00176, tree [000821], tree -> #NA Propagating #01 #02 #58 for BB114, stmt STMT00176, tree [000822], tree -> #NA Propagating #01 #02 #58 for BB114, stmt STMT00176, tree [000823], tree -> #NA Propagating #01 #02 #58 for BB114, stmt STMT00176, tree [000824], tree -> #59 Propagating #01 #02 #58 #60 for BB115, stmt STMT00196, tree [000919], tree -> #NA Propagating #01 #02 #58 #60 for BB115, stmt STMT00196, tree [000920], tree -> #NA Propagating #01 #02 #58 #60 for BB115, stmt STMT00196, tree [000921], tree -> #NA Propagating #01 #02 #58 #60 for BB115, stmt STMT00196, tree [000922], tree -> #61 Propagating #01 #02 #58 #60 #62 for BB116, stmt STMT00197, tree [000923], tree -> #NA Propagating #01 #02 #58 #60 #62 for BB116, stmt STMT00197, tree [000924], tree -> #NA Propagating #01 #02 #58 #60 #62 for BB116, stmt STMT00197, tree [000925], tree -> #NA Propagating #01 #02 #58 #60 #62 for BB116, stmt STMT00197, tree [000926], tree -> #63 Propagating #01 #02 #58 for BB118, stmt STMT00179, tree [000829], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00179, tree [000835], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00179, tree [000836], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [000830], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [000831], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [003677], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [003678], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [003679], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [003680], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [000832], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [000833], tree -> #NA Propagating #01 #02 #58 for BB118, stmt STMT00178, tree [000834], tree -> #NA Propagating #01 #02 #58 for BB119, stmt STMT00194, tree [000838], tree -> #NA Propagating #01 #02 #58 for BB119, stmt STMT00194, tree [000913], tree -> #NA Propagating #01 #02 #58 for BB119, stmt STMT00194, tree [000914], tree -> #NA Propagating #01 #02 #58 for BB119, stmt STMT00195, tree [000912], tree -> #NA Propagating #01 #02 #58 for BB119, stmt STMT00195, tree [000916], tree -> #NA Propagating #01 #02 #58 for BB119, stmt STMT00195, tree [000917], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00181, tree [000840], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00181, tree [000847], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00181, tree [000848], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00180, tree [000841], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00180, tree [000843], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00180, tree [000844], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00180, tree [000845], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00180, tree [000846], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00182, tree [000839], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00182, tree [000851], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00182, tree [000852], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00183, tree [003681], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00183, tree [000854], tree -> #NA Propagating #01 #02 #58 for BB120, stmt STMT00183, tree [000855], tree -> #NA Propagating #01 #02 #58 for BB121, stmt STMT00377, tree [000858], tree -> #NA Propagating #01 #02 #58 for BB121, stmt STMT00377, tree [001796], tree -> #NA Propagating #01 #02 #58 for BB121, stmt STMT00377, tree [001835], tree -> #NA Propagating #01 #02 #58 for BB121, stmt STMT00377, tree [001836], tree -> #NA Propagating #01 #02 #58 for BB121, stmt STMT00370, tree [000857], tree -> #NA Propagating #01 #02 #58 for BB121, stmt STMT00370, tree [002794], tree -> #NA Propagating #01 #02 #58 for BB121, stmt STMT00370, tree [002795], tree -> #NA Propagating #01 #02 #58 for BB121, stmt STMT00370, tree [001797], tree -> #53 Propagating #01 #02 #53 #58 for BB121, stmt STMT00370, tree [001798], tree -> #NA Propagating #01 #02 #53 #58 for BB121, stmt STMT00370, tree [001799], tree -> #NA Propagating #01 #02 #53 #58 for BB121, stmt STMT00372, tree [001800], tree -> #NA Propagating #01 #02 #53 #58 for BB121, stmt STMT00372, tree [001801], tree -> #NA Propagating #01 #02 #53 #58 for BB121, stmt STMT00372, tree [002798], tree -> #NA Propagating #01 #02 #53 #58 for BB121, stmt STMT00372, tree [002799], tree -> #NA Propagating #01 #02 #53 #58 for BB121, stmt STMT00372, tree [001839], tree -> #53 VN based non-null prop in BB121: N005 ( 4, 3) [001839] ---XG------ * IND int Propagating #01 #02 #53 #58 for BB121, stmt STMT00372, tree [001805], tree -> #NA Propagating #01 #02 #53 #58 for BB121, stmt STMT00372, tree [001806], tree -> #NA Re-morphing this stmt: STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001805] N--XG--N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] n---GO----- \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001805] N---GO-N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] n---GO----- \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 #58 for BB122, stmt STMT00374, tree [002803], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00374, tree [002804], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00374, tree [002805], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00374, tree [001814], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00374, tree [001815], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001812], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001817], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [002807], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [002808], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001818], tree -> #53 VN based non-null prop in BB122: N005 ( 4, 3) [001818] ---XG------ * IND int Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001819], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001816], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001823], tree -> #53 VN based non-null prop in BB122: N008 ( 3, 2) [001823] ---XG------ * IND byref Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001813], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001820], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001821], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001822], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001824], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [002809], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001825], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001826], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00375, tree [001828], tree -> #NA Re-morphing this stmt: STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] n---GO----- | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001823] n---GO----- | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 optAssertionPropMain morphed tree: N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] n---GO----- | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001823] n---GO----- | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 Propagating #01 #02 #53 #58 for BB122, stmt STMT00376, tree [001830], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00376, tree [001831], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00376, tree [001832], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00376, tree [001829], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00376, tree [002810], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00376, tree [002811], tree -> #NA Propagating #01 #02 #53 #58 for BB122, stmt STMT00376, tree [001833], tree -> #NA VN based non-null prop in BB122: N007 ( 4, 3) [001833] D--XG--N--- * IND int $845 Propagating #01 #02 #53 #58 for BB122, stmt STMT00376, tree [001834], tree -> #53 Re-morphing this stmt: STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001833] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [001834] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001833] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #53 #58 for BB123, stmt STMT00373, tree [001807], tree -> #NA Propagating #01 #02 #53 #58 for BB123, stmt STMT00373, tree [001808], tree -> #NA Propagating #01 #02 #53 #58 for BB123, stmt STMT00373, tree [002812], tree -> #NA Propagating #01 #02 #53 #58 for BB123, stmt STMT00373, tree [001809], tree -> #NA Propagating #01 #02 #53 #58 for BB124, stmt STMT00185, tree [000860], tree -> #NA Propagating #01 #02 #53 #58 for BB124, stmt STMT00185, tree [000861], tree -> #NA Propagating #01 #02 #53 #58 for BB124, stmt STMT00185, tree [000862], tree -> #NA Propagating #01 #02 #53 #58 for BB124, stmt STMT00185, tree [000863], tree -> #31 Propagating #01 #02 #32 #53 #58 for BB125, stmt STMT00188, tree [000874], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB125, stmt STMT00188, tree [000875], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB125, stmt STMT00188, tree [000876], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB125, stmt STMT00188, tree [000877], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB126, stmt STMT00189, tree [000878], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB126, stmt STMT00189, tree [000879], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB126, stmt STMT00189, tree [000880], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB126, stmt STMT00189, tree [000881], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000885], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000889], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000890], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000894], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000886], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000891], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000892], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000893], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000895], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [002813], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000896], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000898], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000899], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000882], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000900], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB127, stmt STMT00190, tree [000901], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB128, stmt STMT00388, tree [000903], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB128, stmt STMT00388, tree [002814], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB128, stmt STMT00388, tree [002815], tree -> #NA Propagating #01 #02 #32 #53 #58 for BB128, stmt STMT00388, tree [001843], tree -> #33 Propagating #01 #02 #32 #33 #53 #58 for BB128, stmt STMT00388, tree [001895], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB128, stmt STMT00388, tree [001896], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB128, stmt STMT00379, tree [001845], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB128, stmt STMT00379, tree [001846], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB128, stmt STMT00379, tree [001847], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB128, stmt STMT00379, tree [001848], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00380, tree [000902], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00380, tree [002816], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00380, tree [002817], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00380, tree [001849], tree -> #53 VN based non-null prop in BB129: N004 ( 4, 3) [001849] ---XG------ * IND int Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00380, tree [001850], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00380, tree [001851], tree -> #NA Re-morphing this stmt: STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 optAssertionPropMain morphed tree: N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [001852], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [001853], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [003715], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [003716], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [003717], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [003718], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [001854], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [001855], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB129, stmt STMT00381, tree [001856], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB130, stmt STMT00384, tree [001860], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB130, stmt STMT00384, tree [001861], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB130, stmt STMT00384, tree [002820], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB130, stmt STMT00384, tree [002821], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB130, stmt STMT00384, tree [001899], tree -> #53 VN based non-null prop in BB130: N005 ( 4, 3) [001899] ---XG------ * IND int Propagating #01 #02 #32 #33 #53 #58 for BB130, stmt STMT00384, tree [001865], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB130, stmt STMT00384, tree [001866], tree -> #NA Re-morphing this stmt: STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001865] N--XG--N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] n---GO----- \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [001866] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001865] N---GO-N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] n---GO----- \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00385, tree [002825], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00385, tree [002826], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00385, tree [002827], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00385, tree [001871], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00385, tree [001872], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001869], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001874], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002829], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002830], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001875], tree -> #53 VN based non-null prop in BB131: N005 ( 4, 3) [001875] ---XG------ * IND int Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001876], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001873], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001880], tree -> #53 VN based non-null prop in BB131: N008 ( 3, 2) [001880] ---XG------ * IND byref Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001870], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001877], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001878], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001879], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001881], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002831], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001882], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001884], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [003719], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002835], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002832], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002838], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002839], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002841], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002844], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [002842], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00386, tree [001888], tree -> #NA Re-morphing this stmt: STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] n---GO----- | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001880] n---GO----- | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d optAssertionPropMain morphed tree: N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] n---GO----- | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001880] n---GO----- | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00387, tree [001890], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00387, tree [001891], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00387, tree [001892], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00387, tree [001889], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00387, tree [002845], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00387, tree [002846], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00387, tree [001893], tree -> #NA VN based non-null prop in BB131: N007 ( 4, 3) [001893] D--XG--N--- * IND int $845 Propagating #01 #02 #32 #33 #53 #58 for BB131, stmt STMT00387, tree [001894], tree -> #53 Re-morphing this stmt: STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001893] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [001894] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001893] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #32 #33 #53 #58 for BB132, stmt STMT00382, tree [001857], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB132, stmt STMT00382, tree [001858], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB132, stmt STMT00382, tree [002847], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB132, stmt STMT00382, tree [001859], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB133, stmt STMT00193, tree [000907], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB133, stmt STMT00193, tree [000908], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB133, stmt STMT00193, tree [000909], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB133, stmt STMT00193, tree [000910], tree -> #NA Propagating #01 #02 #32 #33 #53 #58 for BB133, stmt STMT00193, tree [000911], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00186, tree [000864], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00186, tree [000865], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00186, tree [000866], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00186, tree [000867], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00186, tree [000868], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00187, tree [000869], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00187, tree [000870], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00187, tree [000871], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00187, tree [000872], tree -> #NA Propagating #01 #02 #53 #58 for BB134, stmt STMT00187, tree [000873], tree -> #NA Propagating #01 #02 #58 for BB135, stmt STMT00177, tree [000825], tree -> #NA Propagating #01 #02 #58 for BB135, stmt STMT00177, tree [000826], tree -> #NA Propagating #01 #02 #58 for BB135, stmt STMT00177, tree [000827], tree -> #NA Propagating #01 #02 #58 for BB135, stmt STMT00177, tree [000828], tree -> #NA Propagating #01 #02 for BB136, stmt STMT00071, tree [000275], tree -> #NA Propagating #01 #02 for BB136, stmt STMT00071, tree [000276], tree -> #NA Propagating #01 #02 for BB136, stmt STMT00071, tree [000277], tree -> #NA Propagating #01 #02 for BB136, stmt STMT00071, tree [000278], tree -> #NA Propagating #01 #02 for BB137, stmt STMT00129, tree [000593], tree -> #NA Propagating #01 #02 for BB137, stmt STMT00129, tree [000594], tree -> #NA Propagating #01 #02 for BB137, stmt STMT00129, tree [000595], tree -> #NA Propagating #01 #02 for BB137, stmt STMT00129, tree [000596], tree -> #NA Propagating #01 #02 for BB138, stmt STMT00130, tree [000597], tree -> #NA Propagating #01 #02 for BB138, stmt STMT00130, tree [000598], tree -> #NA Propagating #01 #02 for BB138, stmt STMT00130, tree [000599], tree -> #NA Propagating #01 #02 for BB138, stmt STMT00130, tree [000600], tree -> #NA Propagating #01 #02 for BB139, stmt STMT00131, tree [000601], tree -> #NA Propagating #01 #02 for BB139, stmt STMT00131, tree [000602], tree -> #NA Propagating #01 #02 for BB139, stmt STMT00131, tree [000603], tree -> #NA Propagating #01 #02 for BB139, stmt STMT00131, tree [000604], tree -> #NA Propagating #01 #02 for BB141, stmt STMT00072, tree [000279], tree -> #NA Propagating #01 #02 for BB141, stmt STMT00072, tree [000280], tree -> #NA Propagating #01 #02 for BB141, stmt STMT00072, tree [000281], tree -> #NA Propagating #01 #02 for BB141, stmt STMT00072, tree [000282], tree -> #NA Propagating #01 #02 for BB142, stmt STMT00079, tree [000319], tree -> #NA Propagating #01 #02 for BB142, stmt STMT00079, tree [000320], tree -> #NA Propagating #01 #02 for BB142, stmt STMT00079, tree [000321], tree -> #NA Propagating #01 #02 for BB142, stmt STMT00079, tree [000322], tree -> #NA Propagating #01 #02 for BB143, stmt STMT00125, tree [000581], tree -> #NA Propagating #01 #02 for BB143, stmt STMT00125, tree [000582], tree -> #NA Propagating #01 #02 for BB143, stmt STMT00125, tree [000583], tree -> #NA Propagating #01 #02 for BB143, stmt STMT00125, tree [000584], tree -> #NA Propagating #01 #02 for BB144, stmt STMT00429, tree [000586], tree -> #NA Propagating #01 #02 for BB144, stmt STMT00429, tree [002848], tree -> #NA Propagating #01 #02 for BB144, stmt STMT00429, tree [002849], tree -> #NA Propagating #01 #02 for BB144, stmt STMT00429, tree [002066], tree -> #33 Propagating #01 #02 #33 for BB144, stmt STMT00429, tree [002118], tree -> #NA Propagating #01 #02 #33 for BB144, stmt STMT00429, tree [002119], tree -> #NA Propagating #01 #02 for BB145, stmt STMT00141, tree [000639], tree -> #NA Propagating #01 #02 for BB145, stmt STMT00141, tree [000640], tree -> #NA Propagating #01 #02 for BB145, stmt STMT00141, tree [000641], tree -> #NA Propagating #01 #02 for BB145, stmt STMT00141, tree [000642], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00160, tree [000731], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00160, tree [000732], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00160, tree [000733], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00160, tree [000734], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00160, tree [000735], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00161, tree [000736], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00161, tree [000737], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00161, tree [000738], tree -> #NA Propagating #01 #02 for BB146, stmt STMT00161, tree [000739], tree -> #NA Propagating #01 #02 for BB147, stmt STMT00164, tree [000747], tree -> #NA Propagating #01 #02 for BB147, stmt STMT00164, tree [000748], tree -> #NA Propagating #01 #02 for BB147, stmt STMT00164, tree [000749], tree -> #NA Propagating #01 #02 for BB148, stmt STMT00162, tree [000740], tree -> #NA Propagating #01 #02 for BB148, stmt STMT00162, tree [000741], tree -> #NA Propagating #01 #02 for BB148, stmt STMT00162, tree [000742], tree -> #NA Propagating #01 #02 for BB149, stmt STMT00163, tree [000744], tree -> #NA Propagating #01 #02 for BB149, stmt STMT00163, tree [002850], tree -> #NA Propagating #01 #02 for BB149, stmt STMT00163, tree [000745], tree -> #NA Propagating #01 #02 for BB149, stmt STMT00163, tree [000746], tree -> #NA Propagating #01 #02 for BB150, stmt STMT00142, tree [000643], tree -> #NA Propagating #01 #02 for BB150, stmt STMT00142, tree [000644], tree -> #NA Propagating #01 #02 for BB150, stmt STMT00142, tree [000645], tree -> #NA Propagating #01 #02 for BB150, stmt STMT00142, tree [000646], tree -> #NA Propagating #01 #02 for BB150, stmt STMT00142, tree [000647], tree -> #NA Propagating #01 #02 for BB151, stmt STMT00157, tree [000719], tree -> #NA Propagating #01 #02 for BB151, stmt STMT00157, tree [000720], tree -> #NA Propagating #01 #02 for BB151, stmt STMT00157, tree [000721], tree -> #NA Propagating #01 #02 for BB151, stmt STMT00157, tree [000722], tree -> #NA Propagating #01 #02 for BB152, stmt STMT00159, tree [000727], tree -> #NA Propagating #01 #02 for BB152, stmt STMT00159, tree [000728], tree -> #NA Propagating #01 #02 for BB152, stmt STMT00159, tree [000729], tree -> #NA Propagating #01 #02 for BB153, stmt STMT00158, tree [000723], tree -> #NA Propagating #01 #02 for BB153, stmt STMT00158, tree [000724], tree -> #NA Propagating #01 #02 for BB153, stmt STMT00158, tree [000725], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00144, tree [000648], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00144, tree [000655], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00144, tree [000656], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00143, tree [000649], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00143, tree [000651], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00143, tree [000652], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00143, tree [000653], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00143, tree [000654], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00145, tree [000657], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00145, tree [000658], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00145, tree [000659], tree -> #NA Propagating #01 #02 for BB154, stmt STMT00145, tree [000660], tree -> #NA Propagating #01 #02 for BB155, stmt STMT00146, tree [000662], tree -> #NA Propagating #01 #02 for BB155, stmt STMT00146, tree [002851], tree -> #NA Propagating #01 #02 for BB155, stmt STMT00146, tree [000663], tree -> #NA Propagating #01 #02 for BB155, stmt STMT00146, tree [000664], tree -> #NA Propagating #01 #02 for BB156, stmt STMT00147, tree [000665], tree -> #NA Propagating #01 #02 for BB156, stmt STMT00147, tree [000666], tree -> #NA Propagating #01 #02 for BB156, stmt STMT00147, tree [000667], tree -> #NA Propagating #01 #02 for BB156, stmt STMT00147, tree [000668], tree -> #NA Propagating #01 #02 for BB157, stmt STMT00390, tree [000674], tree -> #NA Propagating #01 #02 for BB157, stmt STMT00390, tree [002852], tree -> #NA Propagating #01 #02 for BB157, stmt STMT00390, tree [002853], tree -> #NA Propagating #01 #02 for BB157, stmt STMT00390, tree [001903], tree -> #53 Propagating #01 #02 #53 for BB157, stmt STMT00390, tree [001904], tree -> #NA Propagating #01 #02 #53 for BB157, stmt STMT00390, tree [001905], tree -> #NA Propagating #01 #02 #53 for BB157, stmt STMT00392, tree [001906], tree -> #NA Propagating #01 #02 #53 for BB157, stmt STMT00392, tree [001907], tree -> #NA Propagating #01 #02 #53 for BB157, stmt STMT00392, tree [002856], tree -> #NA Propagating #01 #02 #53 for BB157, stmt STMT00392, tree [002857], tree -> #NA Propagating #01 #02 #53 for BB157, stmt STMT00392, tree [001942], tree -> #53 VN based non-null prop in BB157: N005 ( 4, 3) [001942] ---XG------ * IND int Propagating #01 #02 #53 for BB157, stmt STMT00392, tree [001911], tree -> #NA Propagating #01 #02 #53 for BB157, stmt STMT00392, tree [001912], tree -> #NA Re-morphing this stmt: STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001911] N--XG--N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] n---GO----- \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001911] N---GO-N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] n---GO----- \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 for BB158, stmt STMT00394, tree [002861], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00394, tree [002862], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00394, tree [002863], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00394, tree [001919], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00394, tree [001920], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001917], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001922], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [002865], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [002866], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001923], tree -> #53 VN based non-null prop in BB158: N005 ( 4, 3) [001923] ---XG------ * IND int Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001924], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001921], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001928], tree -> #53 VN based non-null prop in BB158: N008 ( 3, 2) [001928] ---XG------ * IND byref Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001918], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001925], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001926], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001927], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001929], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [002867], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001930], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001931], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00395, tree [001933], tree -> #NA Re-morphing this stmt: STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] n---GO----- | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001928] n---GO----- | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 optAssertionPropMain morphed tree: N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] n---GO----- | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001928] n---GO----- | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 Propagating #01 #02 #53 for BB158, stmt STMT00396, tree [001935], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00396, tree [001936], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00396, tree [001937], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00396, tree [001934], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00396, tree [002868], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00396, tree [002869], tree -> #NA Propagating #01 #02 #53 for BB158, stmt STMT00396, tree [001938], tree -> #NA VN based non-null prop in BB158: N007 ( 4, 3) [001938] D--XG--N--- * IND int $845 Propagating #01 #02 #53 for BB158, stmt STMT00396, tree [001939], tree -> #53 Re-morphing this stmt: STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001938] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [001939] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001938] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #53 for BB159, stmt STMT00393, tree [001913], tree -> #NA Propagating #01 #02 #53 for BB159, stmt STMT00393, tree [000675], tree -> #NA Propagating #01 #02 #53 for BB159, stmt STMT00393, tree [002870], tree -> #NA Propagating #01 #02 #53 for BB159, stmt STMT00393, tree [001914], tree -> #NA Propagating #01 #02 #53 for BB160, stmt STMT00150, tree [000677], tree -> #NA Propagating #01 #02 #53 for BB160, stmt STMT00150, tree [000678], tree -> #NA Propagating #01 #02 #53 for BB160, stmt STMT00150, tree [000679], tree -> #NA Propagating #01 #02 #53 for BB160, stmt STMT00150, tree [000680], tree -> #31 Propagating #01 #02 #32 #53 for BB161, stmt STMT00151, tree [000681], tree -> #NA Propagating #01 #02 #32 #53 for BB161, stmt STMT00151, tree [000682], tree -> #NA Propagating #01 #02 #32 #53 for BB161, stmt STMT00151, tree [000683], tree -> #NA Propagating #01 #02 #32 #53 for BB161, stmt STMT00151, tree [000684], tree -> #NA Propagating #01 #02 #32 #53 for BB162, stmt STMT00152, tree [000685], tree -> #NA Propagating #01 #02 #32 #53 for BB162, stmt STMT00152, tree [000686], tree -> #NA Propagating #01 #02 #32 #53 for BB162, stmt STMT00152, tree [000687], tree -> #NA Propagating #01 #02 #32 #53 for BB162, stmt STMT00152, tree [000688], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000692], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000696], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000697], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000701], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000693], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000698], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000699], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000700], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000702], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [002871], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000703], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000705], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000706], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000689], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000707], tree -> #NA Propagating #01 #02 #32 #53 for BB163, stmt STMT00153, tree [000708], tree -> #NA Propagating #01 #02 #32 #53 for BB164, stmt STMT00407, tree [000710], tree -> #NA Propagating #01 #02 #32 #53 for BB164, stmt STMT00407, tree [002872], tree -> #NA Propagating #01 #02 #32 #53 for BB164, stmt STMT00407, tree [002873], tree -> #NA Propagating #01 #02 #32 #53 for BB164, stmt STMT00407, tree [001946], tree -> #33 Propagating #01 #02 #32 #33 #53 for BB164, stmt STMT00407, tree [001998], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB164, stmt STMT00407, tree [001999], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB164, stmt STMT00398, tree [001948], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB164, stmt STMT00398, tree [001949], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB164, stmt STMT00398, tree [001950], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB164, stmt STMT00398, tree [001951], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00399, tree [000709], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00399, tree [002874], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00399, tree [002875], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00399, tree [001952], tree -> #53 VN based non-null prop in BB165: N004 ( 4, 3) [001952] ---XG------ * IND int Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00399, tree [001953], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00399, tree [001954], tree -> #NA Re-morphing this stmt: STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 optAssertionPropMain morphed tree: N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00400, tree [001955], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00400, tree [001956], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00400, tree [001957], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00400, tree [001958], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB165, stmt STMT00400, tree [001959], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB166, stmt STMT00403, tree [001963], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB166, stmt STMT00403, tree [001964], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB166, stmt STMT00403, tree [002878], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB166, stmt STMT00403, tree [002879], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB166, stmt STMT00403, tree [002002], tree -> #53 VN based non-null prop in BB166: N005 ( 4, 3) [002002] ---XG------ * IND int Propagating #01 #02 #32 #33 #53 for BB166, stmt STMT00403, tree [001968], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB166, stmt STMT00403, tree [001969], tree -> #NA Re-morphing this stmt: STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ---XG------ * JTRUE void $845 N006 ( 6, 5) [001968] N--XG--N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] n---GO----- \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [001969] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001968] N---GO-N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] n---GO----- \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00404, tree [002883], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00404, tree [002884], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00404, tree [002885], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00404, tree [001974], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00404, tree [001975], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001972], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001977], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002887], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002888], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001978], tree -> #53 VN based non-null prop in BB167: N005 ( 4, 3) [001978] ---XG------ * IND int Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001979], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001976], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001983], tree -> #53 VN based non-null prop in BB167: N008 ( 3, 2) [001983] ---XG------ * IND byref Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001973], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001980], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001981], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001982], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001984], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002889], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001985], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001987], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001986], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002892], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002893], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002890], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002896], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002897], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002899], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002902], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [002900], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00405, tree [001991], tree -> #NA Re-morphing this stmt: STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] n---GO----- | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [001983] n---GO----- | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d optAssertionPropMain morphed tree: N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] n---GO----- | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001983] n---GO----- | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00406, tree [001993], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00406, tree [001994], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00406, tree [001995], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00406, tree [001992], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00406, tree [002903], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00406, tree [002904], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00406, tree [001996], tree -> #NA VN based non-null prop in BB167: N007 ( 4, 3) [001996] D--XG--N--- * IND int $845 Propagating #01 #02 #32 #33 #53 for BB167, stmt STMT00406, tree [001997], tree -> #53 Re-morphing this stmt: STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [001996] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [001997] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001996] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #32 #33 #53 for BB168, stmt STMT00401, tree [001960], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB168, stmt STMT00401, tree [001961], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB168, stmt STMT00401, tree [002905], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB168, stmt STMT00401, tree [001962], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB169, stmt STMT00156, tree [000714], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB169, stmt STMT00156, tree [000715], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB169, stmt STMT00156, tree [000716], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB169, stmt STMT00156, tree [000717], tree -> #NA Propagating #01 #02 #32 #33 #53 for BB169, stmt STMT00156, tree [000718], tree -> #NA Propagating #01 #02 for BB170, stmt STMT00148, tree [000669], tree -> #NA Propagating #01 #02 for BB170, stmt STMT00148, tree [000670], tree -> #NA Propagating #01 #02 for BB170, stmt STMT00148, tree [000671], tree -> #NA Propagating #01 #02 for BB170, stmt STMT00148, tree [000672], tree -> #NA Propagating #01 #02 for BB170, stmt STMT00148, tree [000673], tree -> #NA Propagating #01 #02 for BB171, stmt STMT00132, tree [000605], tree -> #NA Propagating #01 #02 for BB171, stmt STMT00132, tree [000606], tree -> #NA Propagating #01 #02 for BB171, stmt STMT00132, tree [000607], tree -> #NA Propagating #01 #02 for BB171, stmt STMT00132, tree [000608], tree -> #NA Propagating #01 #02 for BB171, stmt STMT00132, tree [000609], tree -> #NA Propagating #01 #02 for BB171, stmt STMT00132, tree [000610], tree -> #NA Propagating #01 #02 for BB171, stmt STMT00132, tree [000611], tree -> #NA Propagating #01 #02 for BB171, stmt STMT00132, tree [000612], tree -> #NA Propagating #01 #02 for BB172, stmt STMT00133, tree [000613], tree -> #NA Propagating #01 #02 for BB172, stmt STMT00133, tree [000614], tree -> #NA Propagating #01 #02 for BB172, stmt STMT00133, tree [000615], tree -> #NA Propagating #01 #02 for BB172, stmt STMT00133, tree [000616], tree -> #NA Propagating #01 #02 for BB173, stmt STMT00137, tree [000625], tree -> #NA Propagating #01 #02 for BB173, stmt STMT00137, tree [000626], tree -> #NA Propagating #01 #02 for BB173, stmt STMT00137, tree [000627], tree -> #NA Propagating #01 #02 for BB173, stmt STMT00137, tree [000628], tree -> #NA Propagating #01 #02 for BB174, stmt STMT00138, tree [000629], tree -> #NA Propagating #01 #02 for BB174, stmt STMT00138, tree [000630], tree -> #NA Propagating #01 #02 for BB174, stmt STMT00138, tree [000631], tree -> #NA Propagating #01 #02 for BB174, stmt STMT00138, tree [000632], tree -> #NA Propagating #01 #02 for BB174, stmt STMT00138, tree [000633], tree -> #NA Propagating #01 #02 for BB175, stmt STMT00418, tree [000618], tree -> #NA Propagating #01 #02 for BB175, stmt STMT00418, tree [002906], tree -> #NA Propagating #01 #02 for BB175, stmt STMT00418, tree [002907], tree -> #NA Propagating #01 #02 for BB175, stmt STMT00418, tree [002006], tree -> #33 Propagating #01 #02 #33 for BB175, stmt STMT00418, tree [002058], tree -> #NA Propagating #01 #02 #33 for BB175, stmt STMT00418, tree [002059], tree -> #NA Propagating #01 #02 #33 for BB175, stmt STMT00409, tree [002008], tree -> #NA Propagating #01 #02 #33 for BB175, stmt STMT00409, tree [002009], tree -> #NA Propagating #01 #02 #33 for BB175, stmt STMT00409, tree [002010], tree -> #NA Propagating #01 #02 #33 for BB175, stmt STMT00409, tree [002011], tree -> #NA Propagating #01 #02 #33 for BB176, stmt STMT00410, tree [000617], tree -> #NA Propagating #01 #02 #33 for BB176, stmt STMT00410, tree [002908], tree -> #NA Propagating #01 #02 #33 for BB176, stmt STMT00410, tree [002909], tree -> #NA Propagating #01 #02 #33 for BB176, stmt STMT00410, tree [002012], tree -> #53 Propagating #01 #02 #33 #53 for BB176, stmt STMT00410, tree [002013], tree -> #NA Propagating #01 #02 #33 #53 for BB176, stmt STMT00410, tree [002014], tree -> #NA Propagating #01 #02 #33 #53 for BB176, stmt STMT00411, tree [002015], tree -> #NA Propagating #01 #02 #33 #53 for BB176, stmt STMT00411, tree [002016], tree -> #NA Propagating #01 #02 #33 #53 for BB176, stmt STMT00411, tree [002017], tree -> #NA Propagating #01 #02 #33 #53 for BB176, stmt STMT00411, tree [002018], tree -> #NA Propagating #01 #02 #33 #53 for BB176, stmt STMT00411, tree [002019], tree -> #NA Propagating #01 #02 #33 #53 for BB177, stmt STMT00414, tree [002023], tree -> #NA Propagating #01 #02 #33 #53 for BB177, stmt STMT00414, tree [002024], tree -> #NA Propagating #01 #02 #33 #53 for BB177, stmt STMT00414, tree [002912], tree -> #NA Propagating #01 #02 #33 #53 for BB177, stmt STMT00414, tree [002913], tree -> #NA Propagating #01 #02 #33 #53 for BB177, stmt STMT00414, tree [002062], tree -> #53 VN based non-null prop in BB177: N005 ( 4, 3) [002062] ---XG------ * IND int Propagating #01 #02 #33 #53 for BB177, stmt STMT00414, tree [002028], tree -> #NA Propagating #01 #02 #33 #53 for BB177, stmt STMT00414, tree [002029], tree -> #NA Re-morphing this stmt: STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002028] N--XG--N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] n---GO----- \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002029] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002028] N---GO-N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] n---GO----- \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #33 #53 for BB178, stmt STMT00415, tree [002917], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00415, tree [002918], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00415, tree [002919], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00415, tree [002034], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00415, tree [002035], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002032], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002037], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002921], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002922], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002038], tree -> #53 VN based non-null prop in BB178: N005 ( 4, 3) [002038] ---XG------ * IND int Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002039], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002036], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002043], tree -> #53 VN based non-null prop in BB178: N008 ( 3, 2) [002043] ---XG------ * IND byref Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002033], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002040], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002041], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002042], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002044], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002923], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002045], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002047], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002046], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002926], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002927], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002924], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002930], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002931], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002933], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002936], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002934], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00416, tree [002051], tree -> #NA Re-morphing this stmt: STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] n---GO----- | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002043] n---GO----- | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d optAssertionPropMain morphed tree: N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] n---GO----- | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002043] n---GO----- | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d Propagating #01 #02 #33 #53 for BB178, stmt STMT00417, tree [002053], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00417, tree [002054], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00417, tree [002055], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00417, tree [002052], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00417, tree [002937], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00417, tree [002938], tree -> #NA Propagating #01 #02 #33 #53 for BB178, stmt STMT00417, tree [002056], tree -> #NA VN based non-null prop in BB178: N007 ( 4, 3) [002056] D--XG--N--- * IND int $845 Propagating #01 #02 #33 #53 for BB178, stmt STMT00417, tree [002057], tree -> #53 Re-morphing this stmt: STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002056] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002057] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002056] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #33 #53 for BB179, stmt STMT00412, tree [002020], tree -> #NA Propagating #01 #02 #33 #53 for BB179, stmt STMT00412, tree [002021], tree -> #NA Propagating #01 #02 #33 #53 for BB179, stmt STMT00412, tree [002939], tree -> #NA Propagating #01 #02 #33 #53 for BB179, stmt STMT00412, tree [002022], tree -> #NA Propagating #01 #02 #33 for BB180, stmt STMT00136, tree [002940], tree -> #NA Propagating #01 #02 #33 for BB180, stmt STMT00136, tree [000623], tree -> #NA Propagating #01 #02 #33 for BB180, stmt STMT00136, tree [000624], tree -> #NA Propagating #01 #02 #33 for BB181, stmt STMT00420, tree [002068], tree -> #NA Propagating #01 #02 #33 for BB181, stmt STMT00420, tree [002069], tree -> #NA Propagating #01 #02 #33 for BB181, stmt STMT00420, tree [002070], tree -> #NA Propagating #01 #02 #33 for BB181, stmt STMT00420, tree [002071], tree -> #NA Propagating #01 #02 #33 for BB182, stmt STMT00421, tree [000585], tree -> #NA Propagating #01 #02 #33 for BB182, stmt STMT00421, tree [002941], tree -> #NA Propagating #01 #02 #33 for BB182, stmt STMT00421, tree [002942], tree -> #NA Propagating #01 #02 #33 for BB182, stmt STMT00421, tree [002072], tree -> #53 Propagating #01 #02 #33 #53 for BB182, stmt STMT00421, tree [002073], tree -> #NA Propagating #01 #02 #33 #53 for BB182, stmt STMT00421, tree [002074], tree -> #NA Propagating #01 #02 #33 #53 for BB182, stmt STMT00422, tree [002075], tree -> #NA Propagating #01 #02 #33 #53 for BB182, stmt STMT00422, tree [002076], tree -> #NA Propagating #01 #02 #33 #53 for BB182, stmt STMT00422, tree [002077], tree -> #NA Propagating #01 #02 #33 #53 for BB182, stmt STMT00422, tree [002078], tree -> #NA Propagating #01 #02 #33 #53 for BB182, stmt STMT00422, tree [002079], tree -> #NA Propagating #01 #02 #33 #53 for BB183, stmt STMT00425, tree [002083], tree -> #NA Propagating #01 #02 #33 #53 for BB183, stmt STMT00425, tree [002084], tree -> #NA Propagating #01 #02 #33 #53 for BB183, stmt STMT00425, tree [002945], tree -> #NA Propagating #01 #02 #33 #53 for BB183, stmt STMT00425, tree [002946], tree -> #NA Propagating #01 #02 #33 #53 for BB183, stmt STMT00425, tree [002122], tree -> #53 VN based non-null prop in BB183: N005 ( 4, 3) [002122] ---XG------ * IND int Propagating #01 #02 #33 #53 for BB183, stmt STMT00425, tree [002088], tree -> #NA Propagating #01 #02 #33 #53 for BB183, stmt STMT00425, tree [002089], tree -> #NA Re-morphing this stmt: STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002088] N--XG--N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] n---GO----- \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002089] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002088] N---GO-N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] n---GO----- \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #33 #53 for BB184, stmt STMT00426, tree [002950], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00426, tree [002951], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00426, tree [002952], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00426, tree [002094], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00426, tree [002095], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002092], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002097], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002954], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002955], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002098], tree -> #53 VN based non-null prop in BB184: N005 ( 4, 3) [002098] ---XG------ * IND int Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002099], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002096], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002103], tree -> #53 VN based non-null prop in BB184: N008 ( 3, 2) [002103] ---XG------ * IND byref Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002093], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002100], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002101], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002102], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002104], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002956], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002105], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002107], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002106], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002959], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002960], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002957], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002963], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002964], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002966], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002969], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002967], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00427, tree [002111], tree -> #NA Re-morphing this stmt: STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] n---GO----- | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002103] n---GO----- | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d optAssertionPropMain morphed tree: N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] n---GO----- | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002103] n---GO----- | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d Propagating #01 #02 #33 #53 for BB184, stmt STMT00428, tree [002113], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00428, tree [002114], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00428, tree [002115], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00428, tree [002112], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00428, tree [002970], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00428, tree [002971], tree -> #NA Propagating #01 #02 #33 #53 for BB184, stmt STMT00428, tree [002116], tree -> #NA VN based non-null prop in BB184: N007 ( 4, 3) [002116] D--XG--N--- * IND int $845 Propagating #01 #02 #33 #53 for BB184, stmt STMT00428, tree [002117], tree -> #53 Re-morphing this stmt: STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002116] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002117] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002116] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #33 #53 for BB185, stmt STMT00423, tree [002080], tree -> #NA Propagating #01 #02 #33 #53 for BB185, stmt STMT00423, tree [002081], tree -> #NA Propagating #01 #02 #33 #53 for BB185, stmt STMT00423, tree [002972], tree -> #NA Propagating #01 #02 #33 #53 for BB185, stmt STMT00423, tree [002082], tree -> #NA Propagating #01 #02 for BB186, stmt STMT00440, tree [000635], tree -> #NA Propagating #01 #02 for BB186, stmt STMT00440, tree [002973], tree -> #NA Propagating #01 #02 for BB186, stmt STMT00440, tree [002974], tree -> #NA Propagating #01 #02 for BB186, stmt STMT00440, tree [002126], tree -> #33 Propagating #01 #02 #33 for BB186, stmt STMT00440, tree [002178], tree -> #NA Propagating #01 #02 #33 for BB186, stmt STMT00440, tree [002179], tree -> #NA Propagating #01 #02 #33 for BB186, stmt STMT00431, tree [002128], tree -> #NA Propagating #01 #02 #33 for BB186, stmt STMT00431, tree [002129], tree -> #NA Propagating #01 #02 #33 for BB186, stmt STMT00431, tree [002130], tree -> #NA Propagating #01 #02 #33 for BB186, stmt STMT00431, tree [002131], tree -> #NA Propagating #01 #02 #33 for BB187, stmt STMT00432, tree [000634], tree -> #NA Propagating #01 #02 #33 for BB187, stmt STMT00432, tree [002975], tree -> #NA Propagating #01 #02 #33 for BB187, stmt STMT00432, tree [002976], tree -> #NA Propagating #01 #02 #33 for BB187, stmt STMT00432, tree [002132], tree -> #53 Propagating #01 #02 #33 #53 for BB187, stmt STMT00432, tree [002133], tree -> #NA Propagating #01 #02 #33 #53 for BB187, stmt STMT00432, tree [002134], tree -> #NA Propagating #01 #02 #33 #53 for BB187, stmt STMT00433, tree [002135], tree -> #NA Propagating #01 #02 #33 #53 for BB187, stmt STMT00433, tree [002136], tree -> #NA Propagating #01 #02 #33 #53 for BB187, stmt STMT00433, tree [002137], tree -> #NA Propagating #01 #02 #33 #53 for BB187, stmt STMT00433, tree [002138], tree -> #NA Propagating #01 #02 #33 #53 for BB187, stmt STMT00433, tree [002139], tree -> #NA Propagating #01 #02 #33 #53 for BB188, stmt STMT00436, tree [002143], tree -> #NA Propagating #01 #02 #33 #53 for BB188, stmt STMT00436, tree [002144], tree -> #NA Propagating #01 #02 #33 #53 for BB188, stmt STMT00436, tree [002979], tree -> #NA Propagating #01 #02 #33 #53 for BB188, stmt STMT00436, tree [002980], tree -> #NA Propagating #01 #02 #33 #53 for BB188, stmt STMT00436, tree [002182], tree -> #53 VN based non-null prop in BB188: N005 ( 4, 3) [002182] ---XG------ * IND int Propagating #01 #02 #33 #53 for BB188, stmt STMT00436, tree [002148], tree -> #NA Propagating #01 #02 #33 #53 for BB188, stmt STMT00436, tree [002149], tree -> #NA Re-morphing this stmt: STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002148] N--XG--N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] n---GO----- \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002149] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002148] N---GO-N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] n---GO----- \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #33 #53 for BB189, stmt STMT00437, tree [002984], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00437, tree [002985], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00437, tree [002986], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00437, tree [002154], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00437, tree [002155], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002152], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002157], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002988], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002989], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002158], tree -> #53 VN based non-null prop in BB189: N005 ( 4, 3) [002158] ---XG------ * IND int Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002159], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002156], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002163], tree -> #53 VN based non-null prop in BB189: N008 ( 3, 2) [002163] ---XG------ * IND byref Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002153], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002160], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002161], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002162], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002164], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002990], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002165], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002167], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002166], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002993], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002994], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002991], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002997], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002998], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [003000], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [003003], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [003001], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00438, tree [002171], tree -> #NA Re-morphing this stmt: STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] n---GO----- | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002163] n---GO----- | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d optAssertionPropMain morphed tree: N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] n---GO----- | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002163] n---GO----- | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d Propagating #01 #02 #33 #53 for BB189, stmt STMT00439, tree [002173], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00439, tree [002174], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00439, tree [002175], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00439, tree [002172], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00439, tree [003004], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00439, tree [003005], tree -> #NA Propagating #01 #02 #33 #53 for BB189, stmt STMT00439, tree [002176], tree -> #NA VN based non-null prop in BB189: N007 ( 4, 3) [002176] D--XG--N--- * IND int $845 Propagating #01 #02 #33 #53 for BB189, stmt STMT00439, tree [002177], tree -> #53 Re-morphing this stmt: STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002176] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002177] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002176] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #33 #53 for BB190, stmt STMT00434, tree [002140], tree -> #NA Propagating #01 #02 #33 #53 for BB190, stmt STMT00434, tree [002141], tree -> #NA Propagating #01 #02 #33 #53 for BB190, stmt STMT00434, tree [003006], tree -> #NA Propagating #01 #02 #33 #53 for BB190, stmt STMT00434, tree [002142], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00174, tree [000805], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00174, tree [000811], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00174, tree [000812], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00173, tree [000806], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00173, tree [000807], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00173, tree [000808], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00173, tree [000809], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00173, tree [000810], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00449, tree [003629], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00449, tree [002224], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00449, tree [002225], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00442, tree [000803], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00442, tree [003007], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00442, tree [003008], tree -> #NA Propagating #01 #02 for BB191, stmt STMT00442, tree [002186], tree -> #53 Propagating #01 #02 #53 for BB191, stmt STMT00442, tree [002187], tree -> #NA Propagating #01 #02 #53 for BB191, stmt STMT00442, tree [002188], tree -> #NA Propagating #01 #02 #53 for BB191, stmt STMT00444, tree [002189], tree -> #NA Propagating #01 #02 #53 for BB191, stmt STMT00444, tree [002190], tree -> #NA Propagating #01 #02 #53 for BB191, stmt STMT00444, tree [003011], tree -> #NA Propagating #01 #02 #53 for BB191, stmt STMT00444, tree [003012], tree -> #NA Propagating #01 #02 #53 for BB191, stmt STMT00444, tree [002228], tree -> #53 VN based non-null prop in BB191: N005 ( 4, 3) [002228] ---XG------ * IND int Propagating #01 #02 #53 for BB191, stmt STMT00444, tree [002194], tree -> #NA Propagating #01 #02 #53 for BB191, stmt STMT00444, tree [002195], tree -> #NA Re-morphing this stmt: STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002194] N--XG--N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] n---GO----- \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002194] N---GO-N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] n---GO----- \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 for BB192, stmt STMT00446, tree [003016], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00446, tree [003017], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00446, tree [003018], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00446, tree [002203], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00446, tree [002204], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002201], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002206], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [003020], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [003021], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002207], tree -> #53 VN based non-null prop in BB192: N005 ( 4, 3) [002207] ---XG------ * IND int Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002208], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002205], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002212], tree -> #53 VN based non-null prop in BB192: N008 ( 3, 2) [002212] ---XG------ * IND byref Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002202], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002209], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002210], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002211], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002213], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [003022], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002214], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002215], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00447, tree [002217], tree -> #NA Re-morphing this stmt: STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] n---GO----- | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002212] n---GO----- | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) optAssertionPropMain morphed tree: N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] n---GO----- | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002212] n---GO----- | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) Propagating #01 #02 #53 for BB192, stmt STMT00448, tree [002219], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00448, tree [002220], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00448, tree [002221], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00448, tree [002218], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00448, tree [003023], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00448, tree [003024], tree -> #NA Propagating #01 #02 #53 for BB192, stmt STMT00448, tree [002222], tree -> #NA VN based non-null prop in BB192: N007 ( 4, 3) [002222] D--XG--N--- * IND int $845 Propagating #01 #02 #53 for BB192, stmt STMT00448, tree [002223], tree -> #53 Re-morphing this stmt: STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002222] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002223] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002222] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #53 for BB193, stmt STMT00445, tree [002196], tree -> #NA Propagating #01 #02 #53 for BB193, stmt STMT00445, tree [002197], tree -> #NA Propagating #01 #02 #53 for BB193, stmt STMT00445, tree [003025], tree -> #NA Propagating #01 #02 #53 for BB193, stmt STMT00445, tree [002198], tree -> #NA Propagating #01 #02 for BB194, stmt STMT00166, tree [000751], tree -> #NA Propagating #01 #02 for BB194, stmt STMT00166, tree [003699], tree -> #NA Propagating #01 #02 for BB194, stmt STMT00166, tree [000756], tree -> #NA Propagating #01 #02 for BB194, stmt STMT00166, tree [000757], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000781], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000782], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000783], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000785], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000786], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000787], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000788], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [003630], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [003631], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [003632], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [003633], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000789], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000790], tree -> #NA Propagating #01 #02 for BB195, stmt STMT00171, tree [000791], tree -> #NA Propagating #01 #02 for BB196, stmt STMT00172, tree [003634], tree -> #NA Propagating #01 #02 for BB196, stmt STMT00172, tree [000800], tree -> #NA Propagating #01 #02 for BB196, stmt STMT00172, tree [000801], tree -> #NA Propagating #01 #02 for BB196, stmt STMT00172, tree [000802], tree -> #NA Propagating #01 #02 for BB197, stmt STMT00168, tree [000758], tree -> #NA Propagating #01 #02 for BB197, stmt STMT00168, tree [003700], tree -> #NA Propagating #01 #02 for BB197, stmt STMT00168, tree [000763], tree -> #NA Propagating #01 #02 for BB197, stmt STMT00168, tree [000764], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000765], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000766], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000767], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000769], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000770], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000771], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000772], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [003635], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [003636], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [003637], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [003638], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000773], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000774], tree -> #NA Propagating #01 #02 for BB198, stmt STMT00169, tree [000775], tree -> #NA Propagating #01 #02 for BB199, stmt STMT00170, tree [000776], tree -> #NA Propagating #01 #02 for BB199, stmt STMT00170, tree [000777], tree -> #NA Propagating #01 #02 for BB199, stmt STMT00170, tree [000778], tree -> #NA Propagating #01 #02 for BB199, stmt STMT00170, tree [000779], tree -> #NA Propagating #01 #02 for BB199, stmt STMT00170, tree [000780], tree -> #NA Propagating #01 #02 for BB200, stmt STMT00074, tree [000283], tree -> #NA Propagating #01 #02 for BB200, stmt STMT00074, tree [003701], tree -> #NA Propagating #01 #02 for BB200, stmt STMT00074, tree [000288], tree -> #NA Propagating #01 #02 for BB200, stmt STMT00074, tree [000289], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000290], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000291], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000292], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000294], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000295], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000296], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000297], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [003663], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [003664], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [003665], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [003666], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000298], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000299], tree -> #NA Propagating #01 #02 for BB201, stmt STMT00075, tree [000300], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00077, tree [000303], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00077, tree [000309], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00077, tree [000310], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00076, tree [000304], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00076, tree [000305], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00076, tree [000306], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00076, tree [000307], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00076, tree [000308], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00458, tree [003667], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00458, tree [002282], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00458, tree [002283], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00451, tree [000301], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00451, tree [003026], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00451, tree [003027], tree -> #NA Propagating #01 #02 for BB202, stmt STMT00451, tree [002244], tree -> #53 Propagating #01 #02 #53 for BB202, stmt STMT00451, tree [002245], tree -> #NA Propagating #01 #02 #53 for BB202, stmt STMT00451, tree [002246], tree -> #NA Propagating #01 #02 #53 for BB202, stmt STMT00453, tree [002247], tree -> #NA Propagating #01 #02 #53 for BB202, stmt STMT00453, tree [002248], tree -> #NA Propagating #01 #02 #53 for BB202, stmt STMT00453, tree [003030], tree -> #NA Propagating #01 #02 #53 for BB202, stmt STMT00453, tree [003031], tree -> #NA Propagating #01 #02 #53 for BB202, stmt STMT00453, tree [002286], tree -> #53 VN based non-null prop in BB202: N005 ( 4, 3) [002286] ---XG------ * IND int Propagating #01 #02 #53 for BB202, stmt STMT00453, tree [002252], tree -> #NA Propagating #01 #02 #53 for BB202, stmt STMT00453, tree [002253], tree -> #NA Re-morphing this stmt: STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002252] N--XG--N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] n---GO----- \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002252] N---GO-N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] n---GO----- \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 for BB203, stmt STMT00455, tree [003035], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00455, tree [003036], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00455, tree [003037], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00455, tree [002261], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00455, tree [002262], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002259], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002264], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [003039], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [003040], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002265], tree -> #53 VN based non-null prop in BB203: N005 ( 4, 3) [002265] ---XG------ * IND int Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002266], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002263], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002270], tree -> #53 VN based non-null prop in BB203: N008 ( 3, 2) [002270] ---XG------ * IND byref Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002260], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002267], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002268], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002269], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002271], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [003041], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002272], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002273], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00456, tree [002275], tree -> #NA Re-morphing this stmt: STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] n---GO----- | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002270] n---GO----- | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) optAssertionPropMain morphed tree: N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] n---GO----- | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002270] n---GO----- | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) Propagating #01 #02 #53 for BB203, stmt STMT00457, tree [002277], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00457, tree [002278], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00457, tree [002279], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00457, tree [002276], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00457, tree [003042], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00457, tree [003043], tree -> #NA Propagating #01 #02 #53 for BB203, stmt STMT00457, tree [002280], tree -> #NA VN based non-null prop in BB203: N007 ( 4, 3) [002280] D--XG--N--- * IND int $845 Propagating #01 #02 #53 for BB203, stmt STMT00457, tree [002281], tree -> #53 Re-morphing this stmt: STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002280] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002281] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002280] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #53 for BB204, stmt STMT00454, tree [002254], tree -> #NA Propagating #01 #02 #53 for BB204, stmt STMT00454, tree [002255], tree -> #NA Propagating #01 #02 #53 for BB204, stmt STMT00454, tree [003044], tree -> #NA Propagating #01 #02 #53 for BB204, stmt STMT00454, tree [002256], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00080, tree [003045], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00080, tree [000324], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00080, tree [000325], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00081, tree [000326], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00081, tree [000327], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00081, tree [000328], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00082, tree [000329], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00082, tree [000330], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00082, tree [000331], tree -> #NA Propagating #01 #02 for BB205, stmt STMT00082, tree [000332], tree -> #NA Propagating #01 #02 for BB206, stmt STMT00098, tree [000419], tree -> #NA Propagating #01 #02 for BB206, stmt STMT00098, tree [003702], tree -> #NA Propagating #01 #02 for BB206, stmt STMT00098, tree [000424], tree -> #NA Propagating #01 #02 for BB206, stmt STMT00098, tree [000425], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000565], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000566], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000567], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000569], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000570], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000571], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000572], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [003668], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [003669], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [003670], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [003671], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000573], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000574], tree -> #NA Propagating #01 #02 for BB207, stmt STMT00123, tree [000575], tree -> #NA Propagating #01 #02 for BB208, stmt STMT00100, tree [000426], tree -> #NA Propagating #01 #02 for BB208, stmt STMT00100, tree [000427], tree -> #NA Propagating #01 #02 for BB208, stmt STMT00100, tree [000428], tree -> #NA Propagating #01 #02 for BB208, stmt STMT00100, tree [003703], tree -> #NA Propagating #01 #02 for BB208, stmt STMT00100, tree [000433], tree -> #NA Propagating #01 #02 for BB208, stmt STMT00100, tree [000434], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000538], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000539], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000540], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000542], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000543], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000544], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000545], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [003672], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [003673], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [003674], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [003675], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000546], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000547], tree -> #NA Propagating #01 #02 for BB209, stmt STMT00120, tree [000548], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000549], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000550], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000551], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000552], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000553], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000555], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000556], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000557], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000558], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000559], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000560], tree -> #NA Propagating #01 #02 for BB210, stmt STMT00121, tree [000561], tree -> #NA Propagating #01 #02 for BB211, stmt STMT00122, tree [003046], tree -> #NA Propagating #01 #02 for BB211, stmt STMT00122, tree [000563], tree -> #NA Propagating #01 #02 for BB211, stmt STMT00122, tree [000564], tree -> #NA Propagating #01 #02 for BB213, stmt STMT00104, tree [003676], tree -> #NA Propagating #01 #02 for BB213, stmt STMT00104, tree [000455], tree -> #NA Propagating #01 #02 for BB213, stmt STMT00104, tree [000456], tree -> #NA Propagating #01 #02 for BB213, stmt STMT00104, tree [000457], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000458], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000459], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000460], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000461], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000462], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000464], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000465], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000466], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000467], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000468], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000469], tree -> #NA Propagating #01 #02 for BB214, stmt STMT00105, tree [000470], tree -> #NA Propagating #01 #02 for BB215, stmt STMT00460, tree [000444], tree -> #NA Propagating #01 #02 for BB215, stmt STMT00460, tree [003047], tree -> #NA Propagating #01 #02 for BB215, stmt STMT00460, tree [003048], tree -> #NA Propagating #01 #02 for BB215, stmt STMT00460, tree [002302], tree -> #53 Propagating #01 #02 #53 for BB215, stmt STMT00460, tree [002303], tree -> #NA Propagating #01 #02 #53 for BB215, stmt STMT00460, tree [002304], tree -> #NA Propagating #01 #02 #53 for BB215, stmt STMT00462, tree [002305], tree -> #NA Propagating #01 #02 #53 for BB215, stmt STMT00462, tree [002306], tree -> #NA Propagating #01 #02 #53 for BB215, stmt STMT00462, tree [003051], tree -> #NA Propagating #01 #02 #53 for BB215, stmt STMT00462, tree [003052], tree -> #NA Propagating #01 #02 #53 for BB215, stmt STMT00462, tree [002341], tree -> #53 VN based non-null prop in BB215: N005 ( 4, 3) [002341] ---XG------ * IND int Propagating #01 #02 #53 for BB215, stmt STMT00462, tree [002310], tree -> #NA Propagating #01 #02 #53 for BB215, stmt STMT00462, tree [002311], tree -> #NA Re-morphing this stmt: STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002310] N--XG--N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] n---GO----- \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002310] N---GO-N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] n---GO----- \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 for BB216, stmt STMT00464, tree [003056], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00464, tree [003057], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00464, tree [003058], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00464, tree [002318], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00464, tree [002319], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002316], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002321], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [003060], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [003061], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002322], tree -> #53 VN based non-null prop in BB216: N005 ( 4, 3) [002322] ---XG------ * IND int Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002323], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002320], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002327], tree -> #53 VN based non-null prop in BB216: N008 ( 3, 2) [002327] ---XG------ * IND byref Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002317], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002324], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002325], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002326], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002328], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [003062], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002329], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002330], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00465, tree [002332], tree -> #NA Re-morphing this stmt: STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] n---GO----- | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002327] n---GO----- | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) optAssertionPropMain morphed tree: N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] n---GO----- | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002327] n---GO----- | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) Propagating #01 #02 #53 for BB216, stmt STMT00466, tree [002334], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00466, tree [002335], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00466, tree [002336], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00466, tree [002333], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00466, tree [003063], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00466, tree [003064], tree -> #NA Propagating #01 #02 #53 for BB216, stmt STMT00466, tree [002337], tree -> #NA VN based non-null prop in BB216: N007 ( 4, 3) [002337] D--XG--N--- * IND int $845 Propagating #01 #02 #53 for BB216, stmt STMT00466, tree [002338], tree -> #53 Re-morphing this stmt: STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002337] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002338] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002337] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 for BB218, stmt STMT00119, tree [000533], tree -> #NA Propagating #01 #02 for BB218, stmt STMT00119, tree [000534], tree -> #NA Propagating #01 #02 for BB218, stmt STMT00119, tree [000535], tree -> #NA Propagating #01 #02 for BB218, stmt STMT00119, tree [000536], tree -> #NA Propagating #01 #02 for BB218, stmt STMT00119, tree [000537], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00106, tree [000471], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00106, tree [000472], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00106, tree [000473], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00106, tree [000474], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00106, tree [000475], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00107, tree [000477], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00107, tree [000478], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00107, tree [000479], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00109, tree [000476], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00109, tree [003704], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00109, tree [000484], tree -> #NA Propagating #01 #02 for BB219, stmt STMT00109, tree [000485], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000522], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000523], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000524], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000526], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000527], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000528], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000529], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000530], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000531], tree -> #NA Propagating #01 #02 for BB220, stmt STMT00118, tree [000532], tree -> #NA Propagating #01 #02 for BB221, stmt STMT00110, tree [000486], tree -> #NA Propagating #01 #02 for BB221, stmt STMT00110, tree [000487], tree -> #NA Propagating #01 #02 for BB221, stmt STMT00110, tree [000488], tree -> #NA Propagating #01 #02 for BB221, stmt STMT00110, tree [000489], tree -> #NA Propagating #01 #02 for BB222, stmt STMT00117, tree [000519], tree -> #NA Propagating #01 #02 for BB222, stmt STMT00117, tree [000520], tree -> #NA Propagating #01 #02 for BB222, stmt STMT00117, tree [000521], tree -> #NA Propagating #01 #02 for BB223, stmt STMT00111, tree [000490], tree -> #NA Propagating #01 #02 for BB223, stmt STMT00111, tree [000491], tree -> #NA Propagating #01 #02 for BB223, stmt STMT00111, tree [000492], tree -> #NA Propagating #01 #02 for BB223, stmt STMT00111, tree [000493], tree -> #NA Propagating #01 #02 for BB223, stmt STMT00111, tree [000494], tree -> #NA Propagating #01 #02 for BB224, stmt STMT00116, tree [000512], tree -> #NA Propagating #01 #02 for BB224, stmt STMT00116, tree [003066], tree -> #NA Propagating #01 #02 for BB224, stmt STMT00116, tree [003067], tree -> #NA Propagating #01 #02 for BB224, stmt STMT00116, tree [000513], tree -> #01 VN based non-null prop in BB224: N004 ( 4, 3) [000513] ---XG------ * IND int Propagating #01 #02 for BB224, stmt STMT00116, tree [000514], tree -> #NA Propagating #01 #02 for BB224, stmt STMT00116, tree [000515], tree -> #NA Propagating #01 #02 for BB224, stmt STMT00116, tree [000516], tree -> #NA Propagating #01 #02 for BB224, stmt STMT00116, tree [000517], tree -> #NA Re-morphing this stmt: STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A-XG---R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ---XG------ \--* SUB int N004 ( 4, 3) [000513] n---GO----- +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d optAssertionPropMain morphed tree: N008 ( 6, 5) [000517] -A--GO--R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ----GO----- \--* SUB int N004 ( 4, 3) [000513] n---GO----- +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d Propagating #01 #02 for BB225, stmt STMT00112, tree [000495], tree -> #NA Propagating #01 #02 for BB225, stmt STMT00112, tree [000496], tree -> #NA Propagating #01 #02 for BB225, stmt STMT00112, tree [000497], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00114, tree [000507], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00114, tree [000502], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00114, tree [000503], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00114, tree [000499], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00114, tree [000505], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00114, tree [000506], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00114, tree [003068], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00114, tree [000508], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00115, tree [003069], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00115, tree [000510], tree -> #NA Propagating #01 #02 for BB226, stmt STMT00115, tree [000511], tree -> #NA Propagating #01 #02 for BB227, stmt STMT00468, tree [000333], tree -> #NA Propagating #01 #02 for BB227, stmt STMT00468, tree [003070], tree -> #NA Propagating #01 #02 for BB227, stmt STMT00468, tree [003071], tree -> #NA Propagating #01 #02 for BB227, stmt STMT00468, tree [002349], tree -> #53 Propagating #01 #02 #53 for BB227, stmt STMT00468, tree [002350], tree -> #NA Propagating #01 #02 #53 for BB227, stmt STMT00468, tree [002351], tree -> #NA Propagating #01 #02 #53 for BB227, stmt STMT00470, tree [002352], tree -> #NA Propagating #01 #02 #53 for BB227, stmt STMT00470, tree [002353], tree -> #NA Propagating #01 #02 #53 for BB227, stmt STMT00470, tree [003074], tree -> #NA Propagating #01 #02 #53 for BB227, stmt STMT00470, tree [003075], tree -> #NA Propagating #01 #02 #53 for BB227, stmt STMT00470, tree [002388], tree -> #53 VN based non-null prop in BB227: N005 ( 4, 3) [002388] ---XG------ * IND int Propagating #01 #02 #53 for BB227, stmt STMT00470, tree [002357], tree -> #NA Propagating #01 #02 #53 for BB227, stmt STMT00470, tree [002358], tree -> #NA Re-morphing this stmt: STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002357] N--XG--N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] n---GO----- \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002357] N---GO-N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] n---GO----- \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 for BB228, stmt STMT00472, tree [003079], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00472, tree [003080], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00472, tree [003081], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00472, tree [002365], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00472, tree [002366], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002363], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002368], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [003083], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [003084], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002369], tree -> #53 VN based non-null prop in BB228: N005 ( 4, 3) [002369] ---XG------ * IND int Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002370], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002367], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002374], tree -> #53 VN based non-null prop in BB228: N008 ( 3, 2) [002374] ---XG------ * IND byref Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002364], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002371], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002372], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002373], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002375], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [003085], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002376], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002377], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00473, tree [002379], tree -> #NA Re-morphing this stmt: STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] n---GO----- | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002374] n---GO----- | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) optAssertionPropMain morphed tree: N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] n---GO----- | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002374] n---GO----- | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) Propagating #01 #02 #53 for BB228, stmt STMT00474, tree [002381], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00474, tree [002382], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00474, tree [002383], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00474, tree [002380], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00474, tree [003086], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00474, tree [003087], tree -> #NA Propagating #01 #02 #53 for BB228, stmt STMT00474, tree [002384], tree -> #NA VN based non-null prop in BB228: N007 ( 4, 3) [002384] D--XG--N--- * IND int $845 Propagating #01 #02 #53 for BB228, stmt STMT00474, tree [002385], tree -> #53 Re-morphing this stmt: STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002384] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002385] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002384] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #53 for BB229, stmt STMT00471, tree [002359], tree -> #NA Propagating #01 #02 #53 for BB229, stmt STMT00471, tree [000334], tree -> #NA Propagating #01 #02 #53 for BB229, stmt STMT00471, tree [003088], tree -> #NA Propagating #01 #02 #53 for BB229, stmt STMT00471, tree [002360], tree -> #NA Propagating #01 #02 #53 for BB230, stmt STMT00085, tree [000336], tree -> #NA Propagating #01 #02 #53 for BB230, stmt STMT00085, tree [003705], tree -> #NA Propagating #01 #02 #53 for BB230, stmt STMT00085, tree [000341], tree -> #NA Propagating #01 #02 #53 for BB230, stmt STMT00085, tree [000342], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000343], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000344], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000345], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000347], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000348], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000349], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000350], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [003657], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [003658], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [003659], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [003660], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000351], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000352], tree -> #NA Propagating #01 #02 #53 for BB231, stmt STMT00086, tree [000353], tree -> #NA Propagating #01 #02 #53 for BB232, stmt STMT00096, tree [003661], tree -> #NA Propagating #01 #02 #53 for BB232, stmt STMT00096, tree [000416], tree -> #NA Propagating #01 #02 #53 for BB232, stmt STMT00096, tree [000417], tree -> #NA Propagating #01 #02 #53 for BB232, stmt STMT00096, tree [000418], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00088, tree [000356], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00088, tree [000362], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00088, tree [000363], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00087, tree [000357], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00087, tree [000358], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00087, tree [000359], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00087, tree [000360], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00087, tree [000361], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00483, tree [003662], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00483, tree [002434], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00483, tree [002435], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00476, tree [000354], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00476, tree [003089], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00476, tree [003090], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00476, tree [002396], tree -> #53 VN based non-null prop in BB233: N004 ( 4, 3) [002396] ---XG------ * IND int Propagating #01 #02 #53 for BB233, stmt STMT00476, tree [002397], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00476, tree [002398], tree -> #NA Re-morphing this stmt: STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 optAssertionPropMain morphed tree: N006 ( 4, 3) [002398] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 Propagating #01 #02 #53 for BB233, stmt STMT00478, tree [002399], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00478, tree [002400], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00478, tree [003093], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00478, tree [003094], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00478, tree [002438], tree -> #53 VN based non-null prop in BB233: N005 ( 4, 3) [002438] ---XG------ * IND int Propagating #01 #02 #53 for BB233, stmt STMT00478, tree [002404], tree -> #NA Propagating #01 #02 #53 for BB233, stmt STMT00478, tree [002405], tree -> #NA Re-morphing this stmt: STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002404] N--XG--N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] n---GO----- \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002404] N---GO-N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] n---GO----- \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 for BB234, stmt STMT00480, tree [003098], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00480, tree [003099], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00480, tree [003100], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00480, tree [002413], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00480, tree [002414], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002411], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002416], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [003102], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [003103], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002417], tree -> #53 VN based non-null prop in BB234: N005 ( 4, 3) [002417] ---XG------ * IND int Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002418], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002415], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002422], tree -> #53 VN based non-null prop in BB234: N008 ( 3, 2) [002422] ---XG------ * IND byref Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002412], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002419], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002420], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002421], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002423], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [003104], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002424], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002425], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00481, tree [002427], tree -> #NA Re-morphing this stmt: STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] n---GO----- | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002422] n---GO----- | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) optAssertionPropMain morphed tree: N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] n---GO----- | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002422] n---GO----- | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) Propagating #01 #02 #53 for BB234, stmt STMT00482, tree [002429], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00482, tree [002430], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00482, tree [002431], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00482, tree [002428], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00482, tree [003105], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00482, tree [003106], tree -> #NA Propagating #01 #02 #53 for BB234, stmt STMT00482, tree [002432], tree -> #NA VN based non-null prop in BB234: N007 ( 4, 3) [002432] D--XG--N--- * IND int $845 Propagating #01 #02 #53 for BB234, stmt STMT00482, tree [002433], tree -> #53 Re-morphing this stmt: STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002432] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002433] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002432] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #53 for BB235, stmt STMT00479, tree [002406], tree -> #NA Propagating #01 #02 #53 for BB235, stmt STMT00479, tree [002407], tree -> #NA Propagating #01 #02 #53 for BB235, stmt STMT00479, tree [003107], tree -> #NA Propagating #01 #02 #53 for BB235, stmt STMT00479, tree [002408], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00094, tree [000392], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00094, tree [000398], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00094, tree [000399], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00093, tree [000393], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00093, tree [000394], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00093, tree [000395], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00093, tree [000396], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00093, tree [000397], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00492, tree [003639], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00492, tree [002480], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00492, tree [002481], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00485, tree [000390], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00485, tree [003108], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00485, tree [003109], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00485, tree [002442], tree -> #53 VN based non-null prop in BB236: N004 ( 4, 3) [002442] ---XG------ * IND int Propagating #01 #02 #53 for BB236, stmt STMT00485, tree [002443], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00485, tree [002444], tree -> #NA Re-morphing this stmt: STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 optAssertionPropMain morphed tree: N006 ( 4, 3) [002444] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 Propagating #01 #02 #53 for BB236, stmt STMT00487, tree [002445], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00487, tree [002446], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00487, tree [003112], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00487, tree [003113], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00487, tree [002484], tree -> #53 VN based non-null prop in BB236: N005 ( 4, 3) [002484] ---XG------ * IND int Propagating #01 #02 #53 for BB236, stmt STMT00487, tree [002450], tree -> #NA Propagating #01 #02 #53 for BB236, stmt STMT00487, tree [002451], tree -> #NA Re-morphing this stmt: STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002450] N--XG--N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] n---GO----- \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002450] N---GO-N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] n---GO----- \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 for BB237, stmt STMT00489, tree [003117], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00489, tree [003118], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00489, tree [003119], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00489, tree [002459], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00489, tree [002460], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002457], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002462], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [003121], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [003122], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002463], tree -> #53 VN based non-null prop in BB237: N005 ( 4, 3) [002463] ---XG------ * IND int Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002464], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002461], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002468], tree -> #53 VN based non-null prop in BB237: N008 ( 3, 2) [002468] ---XG------ * IND byref Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002458], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002465], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002466], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002467], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002469], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [003123], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002470], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002471], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00490, tree [002473], tree -> #NA Re-morphing this stmt: STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] n---GO----- | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002468] n---GO----- | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) optAssertionPropMain morphed tree: N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] n---GO----- | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002468] n---GO----- | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) Propagating #01 #02 #53 for BB237, stmt STMT00491, tree [002475], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00491, tree [002476], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00491, tree [002477], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00491, tree [002474], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00491, tree [003124], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00491, tree [003125], tree -> #NA Propagating #01 #02 #53 for BB237, stmt STMT00491, tree [002478], tree -> #NA VN based non-null prop in BB237: N007 ( 4, 3) [002478] D--XG--N--- * IND int $845 Propagating #01 #02 #53 for BB237, stmt STMT00491, tree [002479], tree -> #53 Re-morphing this stmt: STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002478] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002479] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002478] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #53 for BB238, stmt STMT00488, tree [002452], tree -> #NA Propagating #01 #02 #53 for BB238, stmt STMT00488, tree [002453], tree -> #NA Propagating #01 #02 #53 for BB238, stmt STMT00488, tree [003126], tree -> #NA Propagating #01 #02 #53 for BB238, stmt STMT00488, tree [002454], tree -> #NA Propagating #01 #02 #53 for BB239, stmt STMT00091, tree [000372], tree -> #NA Propagating #01 #02 #53 for BB239, stmt STMT00091, tree [003706], tree -> #NA Propagating #01 #02 #53 for BB239, stmt STMT00091, tree [000377], tree -> #NA Propagating #01 #02 #53 for BB239, stmt STMT00091, tree [000378], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000379], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000380], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000381], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000383], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000384], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000385], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000386], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [003640], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [003641], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [003642], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [003643], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000387], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000388], tree -> #NA Propagating #01 #02 #53 for BB240, stmt STMT00092, tree [000389], tree -> #NA Propagating #01 #02 for BB242, stmt STMT00494, tree [000590], tree -> #NA Propagating #01 #02 for BB242, stmt STMT00494, tree [003127], tree -> #NA Propagating #01 #02 for BB242, stmt STMT00494, tree [003128], tree -> #NA Propagating #01 #02 for BB242, stmt STMT00494, tree [002492], tree -> #53 Propagating #01 #02 #53 for BB242, stmt STMT00494, tree [002493], tree -> #NA Propagating #01 #02 #53 for BB242, stmt STMT00494, tree [002494], tree -> #NA Propagating #01 #02 #53 for BB242, stmt STMT00496, tree [002495], tree -> #NA Propagating #01 #02 #53 for BB242, stmt STMT00496, tree [002496], tree -> #NA Propagating #01 #02 #53 for BB242, stmt STMT00496, tree [003131], tree -> #NA Propagating #01 #02 #53 for BB242, stmt STMT00496, tree [003132], tree -> #NA Propagating #01 #02 #53 for BB242, stmt STMT00496, tree [002531], tree -> #53 VN based non-null prop in BB242: N005 ( 4, 3) [002531] ---XG------ * IND int Propagating #01 #02 #53 for BB242, stmt STMT00496, tree [002500], tree -> #NA Propagating #01 #02 #53 for BB242, stmt STMT00496, tree [002501], tree -> #NA Re-morphing this stmt: STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ---XG------ * JTRUE void $845 N006 ( 6, 5) [002500] N--XG--N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] n---GO----- \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c optAssertionPropMain morphed tree: N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002500] N---GO-N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] n---GO----- \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c Propagating #01 #02 #53 for BB243, stmt STMT00498, tree [003136], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00498, tree [003137], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00498, tree [003138], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00498, tree [002508], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00498, tree [002509], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002506], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002511], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [003140], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [003141], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002512], tree -> #53 VN based non-null prop in BB243: N005 ( 4, 3) [002512] ---XG------ * IND int Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002513], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002510], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002517], tree -> #53 VN based non-null prop in BB243: N008 ( 3, 2) [002517] ---XG------ * IND byref Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002507], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002514], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002515], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002516], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002518], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [003142], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002519], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002520], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00499, tree [002522], tree -> #NA Re-morphing this stmt: STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] n---GO----- | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ---XGO-N--- | \--* ADD byref N008 ( 3, 2) [002517] n---GO----- | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) optAssertionPropMain morphed tree: N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] n---GO----- | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002517] n---GO----- | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) Propagating #01 #02 #53 for BB243, stmt STMT00500, tree [002524], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00500, tree [002525], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00500, tree [002526], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00500, tree [002523], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00500, tree [003143], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00500, tree [003144], tree -> #NA Propagating #01 #02 #53 for BB243, stmt STMT00500, tree [002527], tree -> #NA VN based non-null prop in BB243: N007 ( 4, 3) [002527] D--XG--N--- * IND int $845 Propagating #01 #02 #53 for BB243, stmt STMT00500, tree [002528], tree -> #53 Re-morphing this stmt: STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A-XG---R-- * ASG int $845 N007 ( 4, 3) [002527] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 8, 8) [002528] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002527] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 Propagating #01 #02 #53 for BB244, stmt STMT00497, tree [002502], tree -> #NA Propagating #01 #02 #53 for BB244, stmt STMT00497, tree [000591], tree -> #NA Propagating #01 #02 #53 for BB244, stmt STMT00497, tree [003145], tree -> #NA Propagating #01 #02 #53 for BB244, stmt STMT00497, tree [002503], tree -> #NA Propagating #01 #02 for BB245, stmt STMT00054, tree [000204], tree -> #NA Propagating #01 #02 for BB245, stmt STMT00054, tree [003707], tree -> #NA Propagating #01 #02 for BB245, stmt STMT00054, tree [000209], tree -> #NA Propagating #01 #02 for BB245, stmt STMT00054, tree [000210], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00065, tree [000243], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00065, tree [000249], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00065, tree [000250], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00064, tree [000244], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00064, tree [000245], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00064, tree [000246], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00064, tree [000247], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00064, tree [000248], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000242], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000251], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000252], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000254], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000255], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000256], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000257], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000258], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00066, tree [000259], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00067, tree [000261], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00067, tree [000262], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00067, tree [000263], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00068, tree [000260], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00068, tree [000264], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00068, tree [000265], tree -> #NA Propagating #01 #02 for BB246, stmt STMT00068, tree [000266], tree -> #NA Propagating #01 #02 for BB247, stmt STMT00069, tree [000267], tree -> #NA Propagating #01 #02 for BB247, stmt STMT00069, tree [000268], tree -> #NA Propagating #01 #02 for BB247, stmt STMT00069, tree [000269], tree -> #NA Propagating #01 #02 for BB247, stmt STMT00069, tree [000270], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00055, tree [000212], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00055, tree [000213], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00055, tree [000214], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00056, tree [000215], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00056, tree [003147], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00056, tree [003148], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00056, tree [000216], tree -> #01 VN based non-null prop in BB248: N004 ( 5, 4) [000216] ---XG------ * IND bool Propagating #01 #02 for BB248, stmt STMT00056, tree [000217], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00056, tree [000218], tree -> #NA Propagating #01 #02 for BB248, stmt STMT00056, tree [000219], tree -> #NA Re-morphing this stmt: STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ---XG------ * JTRUE void $301 N006 ( 7, 7) [000218] J--XG--N--- \--* EQ int N004 ( 5, 4) [000216] n---GO----- +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 optAssertionPropMain morphed tree: N007 ( 9, 9) [000219] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000218] J---GO-N--- \--* EQ int N004 ( 5, 4) [000216] n---GO----- +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 Propagating #01 #02 for BB249, stmt STMT00058, tree [000221], tree -> #NA Propagating #01 #02 for BB249, stmt STMT00058, tree [000222], tree -> #NA Propagating #01 #02 for BB249, stmt STMT00058, tree [000223], tree -> #NA Propagating #01 #02 for BB249, stmt STMT00058, tree [000224], tree -> #49 Propagating #01 #02 #50 for BB250, stmt STMT00059, tree [000225], tree -> #NA Propagating #01 #02 #50 for BB250, stmt STMT00059, tree [003149], tree -> #NA Propagating #01 #02 #50 for BB250, stmt STMT00059, tree [003150], tree -> #NA Propagating #01 #02 #50 for BB250, stmt STMT00059, tree [000226], tree -> #01 VN based non-null prop in BB250: N004 ( 4, 3) [000226] ---XG------ * IND int Propagating #01 #02 #50 for BB250, stmt STMT00059, tree [000227], tree -> #NA Propagating #01 #02 #50 for BB250, stmt STMT00059, tree [000228], tree -> #NA Propagating #01 #02 #50 for BB250, stmt STMT00059, tree [000229], tree -> #NA Re-morphing this stmt: STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ---XG------ * JTRUE void $301 N006 ( 6, 6) [000228] J--XG--N--- \--* NE int N004 ( 4, 3) [000226] n---GO----- +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 optAssertionPropMain morphed tree: N007 ( 8, 8) [000229] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000228] J---GO-N--- \--* NE int N004 ( 4, 3) [000226] n---GO----- +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 Propagating #01 #02 #50 for BB251, stmt STMT00061, tree [000230], tree -> #NA Propagating #01 #02 #50 for BB251, stmt STMT00061, tree [003151], tree -> #NA Propagating #01 #02 #50 for BB251, stmt STMT00061, tree [003152], tree -> #NA Propagating #01 #02 #50 for BB251, stmt STMT00061, tree [002539], tree -> #53 Propagating #01 #02 #50 #53 for BB251, stmt STMT00061, tree [000233], tree -> #NA Propagating #01 #02 #50 #53 for BB251, stmt STMT00061, tree [000234], tree -> #NA Propagating #01 #02 #50 #53 for BB251, stmt STMT00061, tree [000235], tree -> #NA Propagating #01 #02 #50 #53 for BB252, stmt STMT00063, tree [000238], tree -> #NA Propagating #01 #02 #50 #53 for BB252, stmt STMT00063, tree [003154], tree -> #NA Propagating #01 #02 #50 #53 for BB252, stmt STMT00063, tree [003155], tree -> #NA Propagating #01 #02 #50 #53 for BB252, stmt STMT00063, tree [002541], tree -> #33 Propagating #01 #02 #33 #50 #53 for BB252, stmt STMT00063, tree [000236], tree -> #NA Propagating #01 #02 #33 #50 #53 for BB252, stmt STMT00063, tree [003153], tree -> #NA Propagating #01 #02 #33 #50 #53 for BB252, stmt STMT00063, tree [000237], tree -> #NA Propagating #01 #02 #33 #50 #53 for BB252, stmt STMT00063, tree [000241], tree -> #NA Propagating #01 #02 for BB253, stmt STMT00057, tree [000220], tree -> #NA *************** Finishing PHASE Assertion prop Trees after Assertion prop ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 (always) i hascall bwd BB92 [0219] 0 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 (always) i gcsafe bwd BB97 [0242] 0 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB213 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 1 BB208 2 3 [6A8..6B5)-> BB215 (always) i bwd BB213 [0169] 2 BB209,BB210 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] n---GO----- | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N015 ( 16, 16) [002563] -A--------- * COMMA void $VN.Void N007 ( 8, 8) [002559] -A------R-- +--* ASG byref $VN.Void N006 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N005 ( 4, 5) [003711] -A--------- | \--* COMMA byref $246 N003 ( 3, 4) [003709] -A------R-- | +--* ASG byref $VN.Void N002 ( 1, 1) [003708] D------N--- | | +--* LCL_VAR byref V180 cse9 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 1, 1) [003710] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N014 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N013 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N012 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N010 ( 3, 4) [003689] -A------R-- +--* ASG int $VN.Void N009 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N008 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N011 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 N006 ( 7, 7) [001475] J---GO-N--- \--* NE int N004 ( 5, 4) [001473] n---GO----- +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 1, 3) [002606] -A--------- * COMMA void $580 N003 ( 1, 3) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 1, 1) [003712] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 1, 1) [003623] ----------- * COMMA void N001 ( 1, 1) [003692] ----------- +--* LCL_VAR int V179 cse8 u:1 $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 5, 5) [001441] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N014 ( 14, 16) [001452] -A-XG------ * JTRUE void $876 N013 ( 12, 14) [001451] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003627] -A-XG------ +--* COMMA int N009 ( 9, 10) [003625] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N007 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N012 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 N003 ( 3, 3) [001470] N---G--N-U- \--* NE int N001 ( 1, 1) [003628] ----------- +--* LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 5, 5) [001240] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N014 ( 14, 16) [001251] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001250] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003647] -A-XG------ +--* COMMA int N009 ( 9, 10) [003645] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N014 ( 14, 16) [001351] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001350] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003651] -A-XG------ +--* COMMA int N009 ( 9, 10) [003649] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003648] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001348] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001347] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003650] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003696] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N014 ( 14, 16) [001287] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001286] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003655] -A-XG------ +--* COMMA int N009 ( 9, 10) [003653] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003652] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001284] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001283] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003654] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 N003 ( 3, 4) [001339] N---G--N-U- \--* NE int N001 ( 1, 1) [003656] ----------- +--* LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A--GO--R-- * ASG int $301 N006 ( 3, 2) [001135] n---GO-N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ----GO----- \--* ADD int N002 ( 3, 2) [001132] n---GO----- +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A--GO--R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ----GO----- \--* SUB int N006 ( 6, 5) [001174] ----GO----- +--* ADD int N004 ( 4, 3) [001172] n---GO----- | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 21, 20) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 21, 20) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 4, 5) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 1, 1) [003713] ----------- ofs 0 | +--* LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000100] J---GO-N--- \--* EQ int N004 ( 5, 4) [000098] n---GO----- +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A--GO----- * ASG bool $301 N004 ( 5, 4) [001124] n---GO-N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A--GO----- * ASG int $301 N004 ( 4, 3) [000104] n---GO-N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N011 ( 15, 12) [000140] -A--GO----- * JTRUE void $301 N010 ( 13, 10) [000139] JA--GO-N--- \--* GT int N008 ( 11, 8) [003685] -A--GO----- +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N003 ( 7, 5) [000144] -A--G---R-- * ASG int $301 N002 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N001 ( 3, 2) [003686] ----------- \--* LCL_VAR int V178 cse7 u:1 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N005 ( 5, 4) [000154] -A--G---R-- * ASG int $301 N004 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N003 ( 5, 4) [000152] ----G------ \--* SUB int N001 ( 3, 2) [003687] ----------- +--* LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 2) [003720] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A--GO--R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] n---GO----- \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N012 ( 12, 15) [001103] -A-XGO--R-- * ASG int N011 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N010 ( 12, 15) [002670] ---XGO----- \--* COMMA int N004 ( 8, 12) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [003721] ----------- | +--* CNS_INT int 0 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N009 ( 4, 3) [002671] n---GO----- \--* IND int N008 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N007 ( 1, 1) [002667] -------N--- \--* ADD byref N005 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [373..39A) -> BB93 (always), preds={BB90} succs={BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ------------ BB92 [383..384) -> BB94 (always), preds={} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (always), preds={BB95} succs={BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ------------ BB97 [391..392) -> BB99 (always), preds={} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000185] J---GO-N--- \--* EQ int N004 ( 5, 4) [000183] n---GO----- +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000934] J---GO-N--- \--* EQ int N004 ( 4, 3) [000932] n---GO----- +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ----GO----- * JTRUE void $845 N006 ( 8, 6) [001752] N---GO-N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] n---GO----- \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001780] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 1, 3) [002788] -A--------- * COMMA void $588 N003 ( 1, 3) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 1, 1) [003714] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N009 ( 9, 9) [000834] -A-XG------ * JTRUE void $c1a N008 ( 7, 7) [000833] JA-XG--N--- \--* NE int N006 ( 5, 4) [003680] -A-XG------ +--* COMMA int N004 ( 4, 3) [003678] -A-XG---R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003677] D------N--- | | +--* LCL_VAR int V177 cse6 d:1 $VN.Void N002 ( 4, 3) [000831] ---XG------ | | \--* IND ubyte N001 ( 1, 1) [000830] ----------- | | \--* LCL_VAR long V36 loc32 u:7 $904 N005 ( 1, 1) [003679] ----------- | \--* LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N003 ( 1, 3) [000855] -A--G---R-- * ASG int $c1a N002 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N001 ( 1, 1) [003681] ----------- \--* LCL_VAR int V177 cse6 u:1 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001805] N---GO-N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] n---GO----- \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] n---GO----- | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001823] n---GO----- | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001833] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N009 ( 8, 9) [001856] -A-X------- * JTRUE void N008 ( 6, 7) [001855] NA-X---N-U- \--* NE int N006 ( 4, 4) [003718] -A-X------- +--* COMMA int N004 ( 3, 3) [003716] -A-X----R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001865] N---GO-N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] n---GO----- \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] n---GO----- | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001880] n---GO----- | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001893] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001911] N---GO-N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] n---GO----- \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] n---GO----- | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001928] n---GO----- | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001938] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001968] N---GO-N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] n---GO----- \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] n---GO----- | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001983] n---GO----- | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001996] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002028] N---GO-N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] n---GO----- \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] n---GO----- | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002043] n---GO----- | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002056] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002088] N---GO-N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] n---GO----- \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] n---GO----- | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002103] n---GO----- | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002116] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002148] N---GO-N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] n---GO----- \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] n---GO----- | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002163] n---GO----- | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002176] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N003 ( 1, 3) [002225] -A--G---R-- * ASG ushort $bec N002 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N001 ( 1, 1) [003629] ----------- \--* LCL_VAR int V172 cse1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002194] N---GO-N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] n---GO----- \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] n---GO----- | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002212] n---GO----- | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002222] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N014 ( 14, 16) [000791] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000790] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003633] -A-XG------ +--* COMMA int N009 ( 9, 10) [003631] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003630] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000788] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000787] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003632] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec N003 ( 3, 3) [000801] N---G--N-U- \--* NE int N001 ( 1, 1) [003634] ----------- +--* LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N014 ( 14, 16) [000775] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000774] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003638] -A-XG------ +--* COMMA int N009 ( 9, 10) [003636] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003635] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000772] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000771] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003637] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 5, 5) [000289] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N014 ( 14, 16) [000300] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000299] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003666] -A-XG------ +--* COMMA int N009 ( 9, 10) [003664] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N003 ( 1, 3) [002283] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N001 ( 1, 1) [003667] ----------- \--* LCL_VAR int V176 cse5 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002252] N---GO-N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] n---GO----- \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] n---GO----- | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002270] n---GO----- | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002280] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N014 ( 14, 16) [000575] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000574] NA-XG--N-U- \--* EQ int N011 ( 10, 11) [003671] -A-XG------ +--* COMMA int N009 ( 9, 10) [003669] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003668] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000572] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000571] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003670] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003703] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N014 ( 14, 16) [000548] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000547] NA-XG--N-U- \--* NE int N011 ( 10, 11) [003675] -A-XG------ +--* COMMA int N009 ( 9, 10) [003673] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB213 (cond), preds={BB209} succs={BB211,BB213} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB212 [6A8..6B5) -> BB215 (always), preds={BB208} succs={BB215} ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209,BB210} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a N003 ( 3, 4) [000456] N---G--N-U- \--* NE int N001 ( 1, 1) [003676] ----------- +--* LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002310] N---GO-N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] n---GO----- \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] n---GO----- | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002327] n---GO----- | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002337] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A--GO--R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ----GO----- \--* SUB int N004 ( 4, 3) [000513] n---GO----- +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002357] N---GO-N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] n---GO----- \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] n---GO----- | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002374] n---GO----- | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002384] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N014 ( 14, 16) [000353] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000352] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003660] -A-XG------ +--* COMMA int N009 ( 9, 10) [003658] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003657] D------N--- | | +--* LCL_VAR int V175 cse4 d:1 $VN.Void N007 ( 9, 10) [000350] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000349] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003659] ----------- | \--* LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a N003 ( 3, 4) [000417] N---G--N-U- \--* NE int N001 ( 1, 1) [003661] ----------- +--* LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N003 ( 1, 3) [002435] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N001 ( 1, 1) [003662] ----------- \--* LCL_VAR int V175 cse4 u:1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002404] N---GO-N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] n---GO----- \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] n---GO----- | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002422] n---GO----- | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002432] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N003 ( 1, 3) [002481] -A--G---R-- * ASG ushort $c02 N002 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N001 ( 1, 1) [003639] ----------- \--* LCL_VAR int V173 cse2 u:1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002450] N---GO-N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] n---GO----- \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] n---GO----- | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002468] n---GO----- | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002478] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N014 ( 14, 16) [000389] -A-XG------ * JTRUE void $c02 N013 ( 12, 14) [000388] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003643] -A-XG------ +--* COMMA int N009 ( 9, 10) [003641] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003640] D------N--- | | +--* LCL_VAR int V173 cse2 d:1 $VN.Void N007 ( 9, 10) [000386] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000385] -------N--- | | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003642] ----------- | \--* LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002500] N---GO-N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] n---GO----- \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] n---GO----- | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002517] n---GO----- | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002527] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000218] J---GO-N--- \--* EQ int N004 ( 5, 4) [000216] n---GO----- +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000228] J---GO-N--- \--* NE int N004 ( 4, 3) [000226] n---GO----- +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Optimize index checks Looking for array size assertions for: $2c0 ArrSize for lengthVN:2C0 = 0 [RangeCheck::GetRange] BB01 N001 ( 1, 2) [001497] ----------- * CNS_INT int 0 $c0 { Computed Range [001497] => <0, 0> } Does overflow [001497]? [001497] does not overflow Range value <0, 0> [RangeCheck::Widen] BB01, [001497] <0, 0> BetweenBounds <0, [001503]> $2c0 upper bound is: {MemOpaque:NotInLoop} Looking for array size assertions for: $2ca Constant Assertion: ($2ca,$c0) V29.01 != 0, index = #38 The range after edge merging:<1, Dependent> ArrSize for lengthVN:2CA = 1 [RangeCheck::OptimizeRangeCheck] Is index 0 in <0, arrLenVn $2ca sz:1>. Removing range check Before optRemoveRangeCheck: N010 ( 12, 15) [002670] ---XGO----- * COMMA int N004 ( 8, 12) [002662] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [003721] ----------- | +--* CNS_INT int 0 $c0 N003 ( 3, 3) [002661] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001098] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N009 ( 4, 3) [002671] n---GO----- \--* IND int N008 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N007 ( 1, 1) [002667] -------N--- \--* ADD byref N005 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 After optRemoveRangeCheck for [002670]: N012 ( 12, 15) [001103] -A--GO--R-- * ASG int N011 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N010 ( 12, 15) [002670] ----GO-N--- \--* COMMA int N004 ( 8, 12) [002662] ----------- +--* NOP void N009 ( 4, 3) [002671] n---GO----- \--* IND int N008 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N007 ( 1, 1) [002667] -------N--- \--* ADD byref N005 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 Looking for array size assertions for: $2a2 ArrSize for lengthVN:2A2 = 0 [RangeCheck::GetRange] BB100 N001 ( 1, 1) [001024] ----------- * LCL_VAR int V20 loc16 u:11 $71f { ---------------------------------------------------- N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB90 N003 ( 3, 4) [001012] ----------- * ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 { [RangeCheck::GetRange] BB90 N001 ( 1, 1) [001010] ----------- * LCL_VAR int V20 loc16 u:10 (last use) $29b { ---------------------------------------------------- N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003320] ----------- * PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 { [RangeCheck::GetRange] BB89 N001 ( 0, 0) [003536] ----------- * PHI_ARG int V20 loc16 u:11 { ---------------------------------------------------- N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB90 N003 ( 3, 4) [001012] ----------- * ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 { Merging assertions from pred edges of BB90 for op [001010] $29b [RangeCheck::GetRange] BB90 N002 ( 1, 2) [001011] ----------- * CNS_INT int 1 $c1 { Computed Range [001011] => <1, 1> } Merging assertions from pred edges of BB90 for op [001011] $c1 BinOp add ranges <1, 1> = Computed Range [001012] => } Merge assertions from BB89: #01 #02 #32 #33 #35 #36 for assignment about [001013] done merging Merging assertions from pred edges of BB89 for op [003536] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Computed Range [003536] => } Merging assertions from pred edges of BB89 for op [003536] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges : [RangeCheck::GetRange] BB89 N002 ( 0, 0) [003520] ----------- * PHI_ARG int V20 loc16 u:1 $c4 { Computed Range [003520] => <-1, -1> } Merging assertions from pred edges of BB89 for op [003520] $c4 Merge assertions from pred BB88 edge: #01 #02 #32 #33 #35 #36 Merging ranges <-1, -1>: Computed Range [003320] => } Merge assertions from BB90: #01 #02 #32 #33 #35 #36 #43 for assignment about [003319] done merging Merging assertions from pred edges of BB90 for op [001010] $29b Computed Range [001010] => } Merging assertions from pred edges of BB90 for op [001010] $29b BinOp add ranges <1, 1> = Computed Range [001012] => } Merge assertions from BB100: #01 #02 #32 #33 #35 #36 #43 for assignment about [001013] done merging Merging assertions from pred edges of BB100 for op [001024] $71f Computed Range [001024] => } Does overflow [001024]? Does overflow [001012]? Does overflow [001010]? Does overflow [003320]? Does overflow [003536]? Does overflow [001012]? Does overflow [001011]? [001011] does not overflow Checking bin op overflow ADD <1, 1> [001012] overflows [003536] overflows [003320] overflows [001010] overflows [001012] overflows [001024] overflows Method determined to overflow. Looking for array size assertions for: $2ca ArrSize for lengthVN:2CA = 0 [RangeCheck::GetRange] BB101 N001 ( 1, 1) [001056] ----------- * LCL_VAR int V27 loc23 u:4 $727 { ---------------------------------------------------- N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB101 N003 ( 3, 4) [001052] ----------- * ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 { [RangeCheck::GetRange] BB101 N001 ( 1, 1) [001050] ----------- * LCL_VAR int V27 loc23 u:2 (last use) $29e { ---------------------------------------------------- N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003278] ----------- * PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 { [RangeCheck::GetRange] BB89 N001 ( 0, 0) [003540] ----------- * PHI_ARG int V27 loc23 u:3 { ---------------------------------------------------- N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ---------------------------------------------------- [RangeCheck::GetRange] BB102 N003 ( 0, 0) [003275] ----------- * PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e { [RangeCheck::GetRange] BB102 N001 ( 0, 0) [003543] ----------- * PHI_ARG int V27 loc23 u:4 $727 { ---------------------------------------------------- N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB101 N003 ( 3, 4) [001052] ----------- * ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 { Merging assertions from pred edges of BB101 for op [001050] $29e Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 The range after edge merging: [RangeCheck::GetRange] BB101 N002 ( 1, 2) [001051] ----------- * CNS_INT int 1 $c1 { Computed Range [001051] => <1, 1> } Merging assertions from pred edges of BB101 for op [001051] $c1 BinOp add ranges <1, 1> = Computed Range [001052] => } Merge assertions from BB102: #01 #02 #32 #33 #35 #36 #43 #45 for assignment about [001053] done merging Merging assertions from pred edges of BB102 for op [003543] $727 Merge assertions from pred BB101 edge: #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 Computed Range [003543] => } Merging assertions from pred edges of BB102 for op [003543] $727 Merge assertions from pred BB101 edge: #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 Merging ranges : [RangeCheck::GetRange] BB102 N002 ( 0, 0) [003532] ----------- * PHI_ARG int V27 loc23 u:2 $29e { ---------------------------------------------------- N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003278] ----------- * PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 { PhiArg [003540] is already being computed Merging assertions from pred edges of BB89 for op [003540] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges : [RangeCheck::GetRange] BB89 N002 ( 0, 0) [003524] ----------- * PHI_ARG int V27 loc23 u:1 $c0 { Computed Range [003524] => <0, 0> } Merging assertions from pred edges of BB89 for op [003524] $c0 Merge assertions from pred BB88 edge: #01 #02 #32 #33 #35 #36 Constant Assertion: ($70e,$c0) Loop_Bnd { {IntCns 0} GE {ARR_LENGTH($187)}} is {IntCns 0}, index = #35 Merging ranges <0, 0>: Computed Range [003278] => } Merge assertions from BB102: #01 #02 #32 #33 #35 #36 #43 #45 for assignment about [003277] done merging Merging assertions from pred edges of BB102 for op [003532] $29e Merge assertions from pred BB100 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 #46 Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is not {IntCns 0}, index = #46 The range after edge merging:<$2ca + -1, Dependent> Computed Range [003532] => <$2ca + -1, Dependent> } Merging assertions from pred edges of BB102 for op [003532] $29e Merge assertions from pred BB100 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 #46 Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is not {IntCns 0}, index = #46 The range after edge merging:<$2ca + -1, Dependent> Merging ranges <$2ca + -1, Dependent>: Computed Range [003275] => } Merge assertions from BB89: #01 #02 #32 #33 #35 #36 for assignment about [003274] done merging Merging assertions from pred edges of BB89 for op [003540] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Computed Range [003540] => } Merging assertions from pred edges of BB89 for op [003540] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges : [RangeCheck::GetRange] BB89 N002 ( 0, 0) [003524] ----------- * PHI_ARG int V27 loc23 u:1 $c0 { Cached Range [003524] => <0, 0> } Merging assertions from pred edges of BB89 for op [003524] $c0 Merge assertions from pred BB88 edge: #01 #02 #32 #33 #35 #36 Constant Assertion: ($70e,$c0) Loop_Bnd { {IntCns 0} GE {ARR_LENGTH($187)}} is {IntCns 0}, index = #35 Merging ranges <0, 0>: Computed Range [003278] => } Merge assertions from BB101: #01 #02 #32 #33 #35 #36 #43 #45 #47 for assignment about [003277] Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 The range after edge merging: done merging Merging assertions from pred edges of BB101 for op [001050] $29e Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 Bound limit -2 doesn't tighten current bound -2 Computed Range [001050] => } Merging assertions from pred edges of BB101 for op [001050] $29e Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 Bound limit -2 doesn't tighten current bound -2 BinOp add ranges <1, 1> = Computed Range [001052] => } Merge assertions from BB101: #01 #02 #32 #33 #35 #36 #43 #45 #47 for assignment about [001053] done merging Merging assertions from pred edges of BB101 for op [001056] $727 Computed Range [001056] => } Does overflow [001056]? Does overflow [001052]? Does overflow [001050]? Does overflow [003278]? Does overflow [003540]? Does overflow [003275]? Does overflow [003543]? Does overflow [001052]? Does overflow [001051]? [001051] does not overflow Checking bin op overflow ADD <1, 1> [001052] does not overflow [003543] does not overflow Does overflow [003532]? Does overflow [003278]? Does overflow [003524]? [003524] does not overflow [003278] does not overflow [003532] does not overflow [003275] does not overflow [003540] does not overflow [003278] does not overflow [001050] does not overflow Checking bin op overflow ADD <1, 1> [001052] does not overflow [001056] does not overflow Range value [RangeCheck::Widen] BB101, [001056] [RangeCheck::IsMonotonicallyIncreasing] [001056] [RangeCheck::IsMonotonicallyIncreasing] [001052] [RangeCheck::IsBinOpMonotonicallyIncreasing] [001050], [001051] [RangeCheck::IsMonotonicallyIncreasing] [001050] [RangeCheck::IsMonotonicallyIncreasing] [003278] [RangeCheck::IsMonotonicallyIncreasing] [003540] [RangeCheck::IsMonotonicallyIncreasing] [003275] [RangeCheck::IsMonotonicallyIncreasing] [003543] [RangeCheck::IsMonotonicallyIncreasing] [001052] [RangeCheck::IsMonotonicallyIncreasing] [003532] [RangeCheck::IsMonotonicallyIncreasing] [003278] [RangeCheck::IsMonotonicallyIncreasing] [003524] [001056] is monotonically increasing. [RangeCheck::GetRange] BB101 N001 ( 1, 1) [001056] ----------- * LCL_VAR int V27 loc23 u:4 $727 { ---------------------------------------------------- N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB101 N003 ( 3, 4) [001052] ----------- * ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 { [RangeCheck::GetRange] BB101 N001 ( 1, 1) [001050] ----------- * LCL_VAR int V27 loc23 u:2 (last use) $29e { ---------------------------------------------------- N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003278] ----------- * PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 { [RangeCheck::GetRange] BB89 N001 ( 0, 0) [003540] ----------- * PHI_ARG int V27 loc23 u:3 { ---------------------------------------------------- N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ---------------------------------------------------- [RangeCheck::GetRange] BB102 N003 ( 0, 0) [003275] ----------- * PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e { [RangeCheck::GetRange] BB102 N001 ( 0, 0) [003543] ----------- * PHI_ARG int V27 loc23 u:4 $727 { ---------------------------------------------------- N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB101 N003 ( 3, 4) [001052] ----------- * ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 { Merging assertions from pred edges of BB101 for op [001050] $29e Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 The range after edge merging: [RangeCheck::GetRange] BB101 N002 ( 1, 2) [001051] ----------- * CNS_INT int 1 $c1 { Computed Range [001051] => <1, 1> } Merging assertions from pred edges of BB101 for op [001051] $c1 BinOp add ranges <1, 1> = Computed Range [001052] => } Merge assertions from BB102: #01 #02 #32 #33 #35 #36 #43 #45 for assignment about [001053] done merging Merging assertions from pred edges of BB102 for op [003543] $727 Merge assertions from pred BB101 edge: #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 Computed Range [003543] => } Merging assertions from pred edges of BB102 for op [003543] $727 Merge assertions from pred BB101 edge: #01 #02 #32 #33 #35 #36 #43 #45 #47 #48 Merging ranges : [RangeCheck::GetRange] BB102 N002 ( 0, 0) [003532] ----------- * PHI_ARG int V27 loc23 u:2 $29e { ---------------------------------------------------- N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003278] ----------- * PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 { PhiArg [003540] is already being computed Merging assertions from pred edges of BB89 for op [003540] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges : [RangeCheck::GetRange] BB89 N002 ( 0, 0) [003524] ----------- * PHI_ARG int V27 loc23 u:1 $c0 { Computed Range [003524] => <0, 0> } Merging assertions from pred edges of BB89 for op [003524] $c0 Merge assertions from pred BB88 edge: #01 #02 #32 #33 #35 #36 Constant Assertion: ($70e,$c0) Loop_Bnd { {IntCns 0} GE {ARR_LENGTH($187)}} is {IntCns 0}, index = #35 Merging ranges <0, 0>:<0, Dependent> Computed Range [003278] => <0, Dependent> } Merge assertions from BB102: #01 #02 #32 #33 #35 #36 #43 #45 for assignment about [003277] done merging Merging assertions from pred edges of BB102 for op [003532] $29e Merge assertions from pred BB100 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 #46 Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is not {IntCns 0}, index = #46 The range after edge merging:<$2ca + -1, Dependent> Computed Range [003532] => <$2ca + -1, Dependent> } Merging assertions from pred edges of BB102 for op [003532] $29e Merge assertions from pred BB100 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 #46 Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is not {IntCns 0}, index = #46 The range after edge merging:<$2ca + -1, Dependent> Merging ranges <$2ca + -1, Dependent>:<$2ca + -1, Dependent> Computed Range [003275] => <$2ca + -1, Dependent> } Merge assertions from BB89: #01 #02 #32 #33 #35 #36 for assignment about [003274] done merging Merging assertions from pred edges of BB89 for op [003540] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Computed Range [003540] => <$2ca + -1, Dependent> } Merging assertions from pred edges of BB89 for op [003540] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges <$2ca + -1, Dependent>:<$2ca + -1, Dependent> [RangeCheck::GetRange] BB89 N002 ( 0, 0) [003524] ----------- * PHI_ARG int V27 loc23 u:1 $c0 { Cached Range [003524] => <0, 0> } Merging assertions from pred edges of BB89 for op [003524] $c0 Merge assertions from pred BB88 edge: #01 #02 #32 #33 #35 #36 Constant Assertion: ($70e,$c0) Loop_Bnd { {IntCns 0} GE {ARR_LENGTH($187)}} is {IntCns 0}, index = #35 Merging ranges <$2ca + -1, Dependent> <0, 0>: Computed Range [003278] => } Merge assertions from BB101: #01 #02 #32 #33 #35 #36 #43 #45 #47 for assignment about [003277] Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 The range after edge merging: done merging Merging assertions from pred edges of BB101 for op [001050] $29e Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 Bound limit -2 doesn't tighten current bound -2 Computed Range [001050] => } Merging assertions from pred edges of BB101 for op [001050] $29e Constant Assertion: ($726,$c0) Oper_Bnd { {PhiDef($1b, $2, $34d)} GE {ARR_LENGTH($18b)}ADD {IntCns 4294967295}} is {IntCns 0}, index = #47 Bound limit -2 doesn't tighten current bound -2 BinOp add ranges <1, 1> = Computed Range [001052] => } Merge assertions from BB101: #01 #02 #32 #33 #35 #36 #43 #45 #47 for assignment about [001053] done merging Merging assertions from pred edges of BB101 for op [001056] $727 Computed Range [001056] => } Looking for array size assertions for: $2d3 ArrSize for lengthVN:2D3 = 0 [RangeCheck::GetRange] BB109 N001 ( 3, 2) [001756] ----------- * LCL_VAR int V87 tmp47 u:1 { ---------------------------------------------------- N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB107 N004 ( 4, 3) [001736] ---XG------ * IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 { Computed Range [001736] => } Merge assertions from BB109: #01 #02 #33 #50 #52 #53 #54 for assignment about [001737] done merging Merging assertions from pred edges of BB109 for op [001756] $2cf Computed Range [001756] => } Looking for array size assertions for: $2d1 ArrBnds Assertion: ($2d1,$c1) [idx: {IntCns 0};len: {ARR_LENGTH($191)}] is , index = #54 The range after edge merging:<1, 1> ArrSize for lengthVN:2D1 = 1 [RangeCheck::OptimizeRangeCheck] Is index 0 in <0, arrLenVn $2d1 sz:1>. Removing range check Before optRemoveRangeCheck: N025 ( 13, 16) [002775] ---XGO----- * COMMA ushort N019 ( 8, 12) [002768] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001771] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002767] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001770] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d After optRemoveRangeCheck for [002775]: N026 ( 38, 41) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002775] ----GO-N--- \--* COMMA ushort N019 ( 8, 12) [002768] ----------- +--* NOP void N024 ( 5, 4) [002777] n---GO----- \--* IND ushort N023 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N022 ( 1, 1) [002772] -------N--- \--* ADD byref N020 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N021 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d Looking for array size assertions for: $c86 ArrSize for lengthVN:C86 = 0 [RangeCheck::GetRange] BB122 N001 ( 1, 1) [001812] ----------- * LCL_VAR int V91 tmp51 u:1 { ---------------------------------------------------- N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB121 N004 ( 4, 3) [001797] ---XG------ * IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 { Computed Range [001797] => } Merge assertions from BB122: #01 #02 #53 #58 for assignment about [001798] done merging Merging assertions from pred edges of BB122 for op [001812] $c84 Computed Range [001812] => } Looking for array size assertions for: $2a6 ArrSize for lengthVN:2A6 = 0 [RangeCheck::GetRange] BB127 N001 ( 1, 1) [000885] ----------- * LCL_VAR int V20 loc16 u:7 $b13 { ---------------------------------------------------- N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB135 N003 ( 0, 0) [003251] ----------- * PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac { [RangeCheck::GetRange] BB135 N001 ( 0, 0) [003509] ----------- * PHI_ARG int V20 loc16 u:8 { ---------------------------------------------------- N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ---------------------------------------------------- [RangeCheck::GetRange] BB134 N003 ( 0, 0) [003248] ----------- * PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 { [RangeCheck::GetRange] BB134 N001 ( 0, 0) [003512] ----------- * PHI_ARG int V20 loc16 u:9 $d27 { ---------------------------------------------------- N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB133 N003 ( 3, 4) [000909] ----------- * ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 { [RangeCheck::GetRange] BB133 N001 ( 1, 1) [000907] ----------- * LCL_VAR int V20 loc16 u:7 (last use) $b13 { ---------------------------------------------------- N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB135 N003 ( 0, 0) [003251] ----------- * PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac { PhiArg [003509] is already being computed Merging assertions from pred edges of BB135 for op [003509] $ffffffff Merge assertions from pred BB134 edge: #01 #02 #53 #58 Merging ranges : [RangeCheck::GetRange] BB135 N002 ( 0, 0) [003500] ----------- * PHI_ARG int V20 loc16 u:3 $2ac { ---------------------------------------------------- N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ---------------------------------------------------- [RangeCheck::GetRange] BB245 N004 ( 0, 0) [003176] ----------- * PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 { [RangeCheck::GetRange] BB245 N001 ( 0, 0) [003482] ----------- * PHI_ARG int V20 loc16 u:5 { ---------------------------------------------------- N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ---------------------------------------------------- [RangeCheck::GetRange] BB170 N003 ( 0, 0) [003173] ----------- * PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 { [RangeCheck::GetRange] BB170 N001 ( 0, 0) [003484] ----------- * PHI_ARG int V20 loc16 u:6 $ab7 { ---------------------------------------------------- N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB169 N003 ( 3, 4) [000716] ----------- * ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 { [RangeCheck::GetRange] BB169 N001 ( 1, 1) [000714] ----------- * LCL_VAR int V20 loc16 u:4 (last use) $2b3 { ---------------------------------------------------- N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB136 N003 ( 0, 0) [003254] ----------- * PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac { [RangeCheck::GetRange] BB136 N001 ( 0, 0) [003504] ----------- * PHI_ARG int V20 loc16 u:7 { ---------------------------------------------------- N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB135 N003 ( 0, 0) [003251] ----------- * PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac { PhiArg [003509] is already being computed Merging assertions from pred edges of BB135 for op [003509] $ffffffff Merge assertions from pred BB134 edge: #01 #02 #53 #58 Merging ranges : PhiArg [003500] is already being computed Merging assertions from pred edges of BB135 for op [003500] $2ac Merge assertions from pred BB114 JTrue edge: #01 #02 #58 #59 #62 #64 Merging ranges : Computed Range [003251] => } Merge assertions from BB136: #01 #02 for assignment about [003250] done merging Merging assertions from pred edges of BB136 for op [003504] $ffffffff Merge assertions from pred BB135 edge: #01 #02 #58 Computed Range [003504] => } Merging assertions from pred edges of BB136 for op [003504] $ffffffff Merge assertions from pred BB135 edge: #01 #02 #58 Merging ranges : [RangeCheck::GetRange] BB136 N002 ( 0, 0) [003441] ----------- * PHI_ARG int V20 loc16 u:3 $2ac { ---------------------------------------------------- N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ---------------------------------------------------- [RangeCheck::GetRange] BB245 N004 ( 0, 0) [003176] ----------- * PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 { PhiArg [003482] is already being computed Merging assertions from pred edges of BB245 for op [003482] $ffffffff Merge assertions from pred BB170 JTrue edge: #01 #02 Merging ranges : [RangeCheck::GetRange] BB245 N002 ( 0, 0) [003448] ----------- * PHI_ARG int V20 loc16 u:4 { ---------------------------------------------------- N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB136 N003 ( 0, 0) [003254] ----------- * PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac { [RangeCheck::GetRange] BB136 N001 ( 0, 0) [003504] ----------- * PHI_ARG int V20 loc16 u:7 { Cached Range [003504] => } Merging assertions from pred edges of BB136 for op [003504] $ffffffff Merge assertions from pred BB135 edge: #01 #02 #58 Merging ranges : PhiArg [003441] is already being computed Merging assertions from pred edges of BB136 for op [003441] $2ac Merge assertions from pred BB113 JTrue edge: #01 #02 #57 Merging ranges : Computed Range [003254] => } Merge assertions from BB245: #01 #02 for assignment about [003253] done merging Merging assertions from pred edges of BB245 for op [003448] $ffffffff Merge assertions from pred BB244 edge: #01 #02 #53 Computed Range [003448] => } Merging assertions from pred edges of BB245 for op [003448] $ffffffff Merge assertions from pred BB244 edge: #01 #02 #53 Merging ranges : [RangeCheck::GetRange] BB245 N003 ( 0, 0) [003437] ----------- * PHI_ARG int V20 loc16 u:2 $2a5 { ---------------------------------------------------- N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB103 N004 ( 0, 0) [003317] ----------- * PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 { [RangeCheck::GetRange] BB103 N001 ( 0, 0) [003533] ----------- * PHI_ARG int V20 loc16 u:11 $71f { ---------------------------------------------------- N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB90 N003 ( 3, 4) [001012] ----------- * ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 { [RangeCheck::GetRange] BB90 N001 ( 1, 1) [001010] ----------- * LCL_VAR int V20 loc16 u:10 (last use) $29b { ---------------------------------------------------- N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003320] ----------- * PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 { [RangeCheck::GetRange] BB89 N001 ( 0, 0) [003536] ----------- * PHI_ARG int V20 loc16 u:11 { ---------------------------------------------------- N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB90 N003 ( 3, 4) [001012] ----------- * ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 { Merging assertions from pred edges of BB90 for op [001010] $29b [RangeCheck::GetRange] BB90 N002 ( 1, 2) [001011] ----------- * CNS_INT int 1 $c1 { Computed Range [001011] => <1, 1> } Merging assertions from pred edges of BB90 for op [001011] $c1 BinOp add ranges <1, 1> = Computed Range [001012] => } Merge assertions from BB89: #01 #02 #32 #33 #35 #36 for assignment about [001013] done merging Merging assertions from pred edges of BB89 for op [003536] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Computed Range [003536] => } Merging assertions from pred edges of BB89 for op [003536] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges : [RangeCheck::GetRange] BB89 N002 ( 0, 0) [003520] ----------- * PHI_ARG int V20 loc16 u:1 $c4 { Computed Range [003520] => <-1, -1> } Merging assertions from pred edges of BB89 for op [003520] $c4 Merge assertions from pred BB88 edge: #01 #02 #32 #33 #35 #36 Merging ranges <-1, -1>: Computed Range [003320] => } Merge assertions from BB90: #01 #02 #32 #33 #35 #36 #43 for assignment about [003319] done merging Merging assertions from pred edges of BB90 for op [001010] $29b Computed Range [001010] => } Merging assertions from pred edges of BB90 for op [001010] $29b BinOp add ranges <1, 1> = Computed Range [001012] => } Merge assertions from BB103: #01 #02 for assignment about [001013] done merging Merging assertions from pred edges of BB103 for op [003533] $71f Merge assertions from pred BB102 edge: #01 #02 #32 #33 #35 #36 #43 #45 Computed Range [003533] => } Merging assertions from pred edges of BB103 for op [003533] $71f Merge assertions from pred BB102 edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges : [RangeCheck::GetRange] BB103 N002 ( 0, 0) [003526] ----------- * PHI_ARG int V20 loc16 u:10 $29b { ---------------------------------------------------- N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003320] ----------- * PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 { Cached Range [003320] => } Merge assertions from BB103: #01 #02 for assignment about [003319] done merging Merging assertions from pred edges of BB103 for op [003526] $29b Merge assertions from pred BB89 JTrue edge: #01 #02 #32 #33 #35 #36 #42 Computed Range [003526] => } Merging assertions from pred edges of BB103 for op [003526] $29b Merge assertions from pred BB89 JTrue edge: #01 #02 #32 #33 #35 #36 #42 Merging ranges : [RangeCheck::GetRange] BB103 N003 ( 0, 0) [003430] ----------- * PHI_ARG int V20 loc16 u:1 $c4 { Computed Range [003430] => <-1, -1> } Merging assertions from pred edges of BB103 for op [003430] $c4 Merge assertions from pred BB78 JTrue edge: #01 #02 #31 Merging ranges <-1, -1>: Computed Range [003317] => } Merge assertions from BB245: #01 #02 for assignment about [003316] done merging Merging assertions from pred edges of BB245 for op [003437] $2a5 Merge assertions from pred BB112 JTrue edge: #01 #02 Computed Range [003437] => } Merging assertions from pred edges of BB245 for op [003437] $2a5 Merge assertions from pred BB112 JTrue edge: #01 #02 Merging ranges : Computed Range [003176] => } Merge assertions from BB136: #01 #02 for assignment about [003175] done merging Merging assertions from pred edges of BB136 for op [003441] $2ac Merge assertions from pred BB113 JTrue edge: #01 #02 #57 Computed Range [003441] => } Merging assertions from pred edges of BB136 for op [003441] $2ac Merge assertions from pred BB113 JTrue edge: #01 #02 #57 Merging ranges : Computed Range [003254] => } Merge assertions from BB169: #01 #02 #32 #33 #53 for assignment about [003253] done merging Merging assertions from pred edges of BB169 for op [000714] $2b3 Computed Range [000714] => } Merging assertions from pred edges of BB169 for op [000714] $2b3 [RangeCheck::GetRange] BB169 N002 ( 1, 2) [000715] ----------- * CNS_INT int -1 $c4 { Computed Range [000715] => <-1, -1> } Merging assertions from pred edges of BB169 for op [000715] $c4 BinOp add ranges <-1, -1> = Computed Range [000716] => } Merge assertions from BB170: #01 #02 for assignment about [000717] done merging Merging assertions from pred edges of BB170 for op [003484] $ab7 Merge assertions from pred BB169 edge: #01 #02 #32 #33 #53 Computed Range [003484] => } Merging assertions from pred edges of BB170 for op [003484] $ab7 Merge assertions from pred BB169 edge: #01 #02 #32 #33 #53 Merging ranges : [RangeCheck::GetRange] BB170 N002 ( 0, 0) [003479] ----------- * PHI_ARG int V20 loc16 u:4 $2b3 { ---------------------------------------------------- N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB136 N003 ( 0, 0) [003254] ----------- * PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac { Cached Range [003254] => } Merge assertions from BB170: #01 #02 for assignment about [003253] done merging Merging assertions from pred edges of BB170 for op [003479] $2b3 Merge assertions from pred BB156 JTrue edge: #01 #02 Computed Range [003479] => } Merging assertions from pred edges of BB170 for op [003479] $2b3 Merge assertions from pred BB156 JTrue edge: #01 #02 Merging ranges : Computed Range [003173] => } Merge assertions from BB245: #01 #02 for assignment about [003172] done merging Merging assertions from pred edges of BB245 for op [003482] $ffffffff Merge assertions from pred BB170 JTrue edge: #01 #02 Computed Range [003482] => } Merging assertions from pred edges of BB245 for op [003482] $ffffffff Merge assertions from pred BB170 JTrue edge: #01 #02 Merging ranges : [RangeCheck::GetRange] BB245 N002 ( 0, 0) [003448] ----------- * PHI_ARG int V20 loc16 u:4 { Cached Range [003448] => } Merging assertions from pred edges of BB245 for op [003448] $ffffffff Merge assertions from pred BB244 edge: #01 #02 #53 Merging ranges : [RangeCheck::GetRange] BB245 N003 ( 0, 0) [003437] ----------- * PHI_ARG int V20 loc16 u:2 $2a5 { Cached Range [003437] => } Merging assertions from pred edges of BB245 for op [003437] $2a5 Merge assertions from pred BB112 JTrue edge: #01 #02 Merging ranges : Computed Range [003176] => } Merge assertions from BB135: #01 #02 #58 for assignment about [003175] done merging Merging assertions from pred edges of BB135 for op [003500] $2ac Merge assertions from pred BB114 JTrue edge: #01 #02 #58 #59 #62 #64 Computed Range [003500] => } Merging assertions from pred edges of BB135 for op [003500] $2ac Merge assertions from pred BB114 JTrue edge: #01 #02 #58 #59 #62 #64 Merging ranges : Computed Range [003251] => } Merge assertions from BB133: #01 #02 #32 #33 #53 #58 for assignment about [003250] done merging Merging assertions from pred edges of BB133 for op [000907] $b13 Computed Range [000907] => } Merging assertions from pred edges of BB133 for op [000907] $b13 [RangeCheck::GetRange] BB133 N002 ( 1, 2) [000908] ----------- * CNS_INT int -1 $c4 { Computed Range [000908] => <-1, -1> } Merging assertions from pred edges of BB133 for op [000908] $c4 BinOp add ranges <-1, -1> = Computed Range [000909] => } Merge assertions from BB134: #01 #02 #53 #58 for assignment about [000910] done merging Merging assertions from pred edges of BB134 for op [003512] $d27 Merge assertions from pred BB133 edge: #01 #02 #32 #33 #53 #58 Computed Range [003512] => } Merging assertions from pred edges of BB134 for op [003512] $d27 Merge assertions from pred BB133 edge: #01 #02 #32 #33 #53 #58 Merging ranges : [RangeCheck::GetRange] BB134 N002 ( 0, 0) [003507] ----------- * PHI_ARG int V20 loc16 u:7 $b13 { ---------------------------------------------------- N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB135 N003 ( 0, 0) [003251] ----------- * PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac { Cached Range [003251] => } Merge assertions from BB134: #01 #02 #53 #58 for assignment about [003250] done merging Merging assertions from pred edges of BB134 for op [003507] $b13 Merge assertions from pred BB124 JTrue edge: #01 #02 #31 #53 #58 Computed Range [003507] => } Merging assertions from pred edges of BB134 for op [003507] $b13 Merge assertions from pred BB124 JTrue edge: #01 #02 #31 #53 #58 Merging ranges : Computed Range [003248] => } Merge assertions from BB135: #01 #02 #58 for assignment about [003247] done merging Merging assertions from pred edges of BB135 for op [003509] $ffffffff Merge assertions from pred BB134 edge: #01 #02 #53 #58 Computed Range [003509] => } Merging assertions from pred edges of BB135 for op [003509] $ffffffff Merge assertions from pred BB134 edge: #01 #02 #53 #58 Merging ranges : [RangeCheck::GetRange] BB135 N002 ( 0, 0) [003500] ----------- * PHI_ARG int V20 loc16 u:3 $2ac { Cached Range [003500] => } Merging assertions from pred edges of BB135 for op [003500] $2ac Merge assertions from pred BB114 JTrue edge: #01 #02 #58 #59 #62 #64 Merging ranges : Computed Range [003251] => } Merge assertions from BB127: #01 #02 #32 #53 #58 for assignment about [003250] done merging Merging assertions from pred edges of BB127 for op [000885] $b13 Computed Range [000885] => } Does overflow [000885]? Does overflow [003251]? Does overflow [003509]? Does overflow [003248]? Does overflow [003512]? Does overflow [000909]? Does overflow [000907]? Does overflow [003251]? Does overflow [003500]? Does overflow [003176]? Does overflow [003482]? Does overflow [003173]? Does overflow [003484]? Does overflow [000716]? Does overflow [000714]? Does overflow [003254]? Does overflow [003504]? Does overflow [003251]? [003251] does not overflow [003504] does not overflow Does overflow [003441]? Does overflow [003176]? Does overflow [003448]? Does overflow [003254]? [003254] does not overflow [003448] does not overflow Does overflow [003437]? Does overflow [003317]? Does overflow [003533]? Does overflow [001012]? Does overflow [001010]? Does overflow [003320]? Does overflow [003536]? Does overflow [001012]? Does overflow [001011]? [001011] does not overflow Checking bin op overflow ADD <1, 1> [001012] overflows [003536] overflows [003320] overflows [001010] overflows [001012] overflows [003533] overflows [003317] overflows [003437] overflows [003176] overflows [003441] overflows [003254] overflows [000714] overflows [000716] overflows [003484] overflows [003173] overflows [003482] overflows [003176] overflows [003500] overflows [003251] overflows [000907] overflows [000909] overflows [003512] overflows [003248] overflows [003509] overflows [003251] overflows [000885] overflows Method determined to overflow. Looking for array size assertions for: $c8c ArrSize for lengthVN:C8C = 0 [RangeCheck::GetRange] BB131 N001 ( 1, 1) [001869] ----------- * LCL_VAR int V96 tmp56 u:1 { ---------------------------------------------------- N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB129 N004 ( 4, 3) [001849] n---GO----- * IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 { Computed Range [001849] => } Merge assertions from BB131: #01 #02 #32 #33 #53 #58 for assignment about [001850] done merging Merging assertions from pred edges of BB131 for op [001869] $c88 Computed Range [001869] => } Looking for array size assertions for: $c8a ArrSize for lengthVN:C8A = 0 [RangeCheck::GetRange] BB131 N016 ( 1, 2) [001884] ----------- * CNS_INT int 0 $c0 { Computed Range [001884] => <0, 0> } Does overflow [001884]? [001884] does not overflow Range value <0, 0> [RangeCheck::Widen] BB131, [001884] <0, 0> BetweenBounds <0, [003719]> $c8a upper bound is: {ARR_LENGTH($cc3)} Array size is: 0 Looking for array size assertions for: $2ec ArrSize for lengthVN:2EC = 0 [RangeCheck::GetRange] BB158 N001 ( 1, 1) [001917] ----------- * LCL_VAR int V99 tmp59 u:1 { ---------------------------------------------------- N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB157 N004 ( 4, 3) [001903] ---XG------ * IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 { Computed Range [001903] => } Merge assertions from BB158: #01 #02 #53 for assignment about [001904] done merging Merging assertions from pred edges of BB158 for op [001917] $2ea Computed Range [001917] => } Looking for array size assertions for: $2a6 ArrSize for lengthVN:2A6 = 0 [RangeCheck::GetRange] BB163 N001 ( 1, 1) [000692] ----------- * LCL_VAR int V20 loc16 u:4 $2b3 { ---------------------------------------------------- N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB136 N003 ( 0, 0) [003254] ----------- * PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac { [RangeCheck::GetRange] BB136 N001 ( 0, 0) [003504] ----------- * PHI_ARG int V20 loc16 u:7 { ---------------------------------------------------- N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB135 N003 ( 0, 0) [003251] ----------- * PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac { [RangeCheck::GetRange] BB135 N001 ( 0, 0) [003509] ----------- * PHI_ARG int V20 loc16 u:8 { ---------------------------------------------------- N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ---------------------------------------------------- [RangeCheck::GetRange] BB134 N003 ( 0, 0) [003248] ----------- * PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 { [RangeCheck::GetRange] BB134 N001 ( 0, 0) [003512] ----------- * PHI_ARG int V20 loc16 u:9 $d27 { ---------------------------------------------------- N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB133 N003 ( 3, 4) [000909] ----------- * ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 { [RangeCheck::GetRange] BB133 N001 ( 1, 1) [000907] ----------- * LCL_VAR int V20 loc16 u:7 (last use) $b13 { ---------------------------------------------------- N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB135 N003 ( 0, 0) [003251] ----------- * PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac { PhiArg [003509] is already being computed Merging assertions from pred edges of BB135 for op [003509] $ffffffff Merge assertions from pred BB134 edge: #01 #02 #53 #58 Merging ranges : [RangeCheck::GetRange] BB135 N002 ( 0, 0) [003500] ----------- * PHI_ARG int V20 loc16 u:3 $2ac { ---------------------------------------------------- N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ---------------------------------------------------- [RangeCheck::GetRange] BB245 N004 ( 0, 0) [003176] ----------- * PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 { [RangeCheck::GetRange] BB245 N001 ( 0, 0) [003482] ----------- * PHI_ARG int V20 loc16 u:5 { ---------------------------------------------------- N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ---------------------------------------------------- [RangeCheck::GetRange] BB170 N003 ( 0, 0) [003173] ----------- * PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 { [RangeCheck::GetRange] BB170 N001 ( 0, 0) [003484] ----------- * PHI_ARG int V20 loc16 u:6 $ab7 { ---------------------------------------------------- N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB169 N003 ( 3, 4) [000716] ----------- * ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 { [RangeCheck::GetRange] BB169 N001 ( 1, 1) [000714] ----------- * LCL_VAR int V20 loc16 u:4 (last use) $2b3 { ---------------------------------------------------- N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB136 N003 ( 0, 0) [003254] ----------- * PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac { PhiArg [003504] is already being computed Merging assertions from pred edges of BB136 for op [003504] $ffffffff Merge assertions from pred BB135 edge: #01 #02 #58 Merging ranges : [RangeCheck::GetRange] BB136 N002 ( 0, 0) [003441] ----------- * PHI_ARG int V20 loc16 u:3 $2ac { ---------------------------------------------------- N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ---------------------------------------------------- [RangeCheck::GetRange] BB245 N004 ( 0, 0) [003176] ----------- * PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 { PhiArg [003482] is already being computed Merging assertions from pred edges of BB245 for op [003482] $ffffffff Merge assertions from pred BB170 JTrue edge: #01 #02 Merging ranges : [RangeCheck::GetRange] BB245 N002 ( 0, 0) [003448] ----------- * PHI_ARG int V20 loc16 u:4 { ---------------------------------------------------- N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB136 N003 ( 0, 0) [003254] ----------- * PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac { PhiArg [003504] is already being computed Merging assertions from pred edges of BB136 for op [003504] $ffffffff Merge assertions from pred BB135 edge: #01 #02 #58 Merging ranges : PhiArg [003441] is already being computed Merging assertions from pred edges of BB136 for op [003441] $2ac Merge assertions from pred BB113 JTrue edge: #01 #02 #57 Merging ranges : Computed Range [003254] => } Merge assertions from BB245: #01 #02 for assignment about [003253] done merging Merging assertions from pred edges of BB245 for op [003448] $ffffffff Merge assertions from pred BB244 edge: #01 #02 #53 Computed Range [003448] => } Merging assertions from pred edges of BB245 for op [003448] $ffffffff Merge assertions from pred BB244 edge: #01 #02 #53 Merging ranges : [RangeCheck::GetRange] BB245 N003 ( 0, 0) [003437] ----------- * PHI_ARG int V20 loc16 u:2 $2a5 { ---------------------------------------------------- N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB103 N004 ( 0, 0) [003317] ----------- * PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 { [RangeCheck::GetRange] BB103 N001 ( 0, 0) [003533] ----------- * PHI_ARG int V20 loc16 u:11 $71f { ---------------------------------------------------- N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB90 N003 ( 3, 4) [001012] ----------- * ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 { [RangeCheck::GetRange] BB90 N001 ( 1, 1) [001010] ----------- * LCL_VAR int V20 loc16 u:10 (last use) $29b { ---------------------------------------------------- N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003320] ----------- * PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 { [RangeCheck::GetRange] BB89 N001 ( 0, 0) [003536] ----------- * PHI_ARG int V20 loc16 u:11 { ---------------------------------------------------- N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ---------------------------------------------------- [RangeCheck::GetRange] BB90 N003 ( 3, 4) [001012] ----------- * ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 { Merging assertions from pred edges of BB90 for op [001010] $29b [RangeCheck::GetRange] BB90 N002 ( 1, 2) [001011] ----------- * CNS_INT int 1 $c1 { Computed Range [001011] => <1, 1> } Merging assertions from pred edges of BB90 for op [001011] $c1 BinOp add ranges <1, 1> = Computed Range [001012] => } Merge assertions from BB89: #01 #02 #32 #33 #35 #36 for assignment about [001013] done merging Merging assertions from pred edges of BB89 for op [003536] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Computed Range [003536] => } Merging assertions from pred edges of BB89 for op [003536] $ffffffff Merge assertions from pred BB102 JTrue edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges : [RangeCheck::GetRange] BB89 N002 ( 0, 0) [003520] ----------- * PHI_ARG int V20 loc16 u:1 $c4 { Computed Range [003520] => <-1, -1> } Merging assertions from pred edges of BB89 for op [003520] $c4 Merge assertions from pred BB88 edge: #01 #02 #32 #33 #35 #36 Merging ranges <-1, -1>: Computed Range [003320] => } Merge assertions from BB90: #01 #02 #32 #33 #35 #36 #43 for assignment about [003319] done merging Merging assertions from pred edges of BB90 for op [001010] $29b Computed Range [001010] => } Merging assertions from pred edges of BB90 for op [001010] $29b BinOp add ranges <1, 1> = Computed Range [001012] => } Merge assertions from BB103: #01 #02 for assignment about [001013] done merging Merging assertions from pred edges of BB103 for op [003533] $71f Merge assertions from pred BB102 edge: #01 #02 #32 #33 #35 #36 #43 #45 Computed Range [003533] => } Merging assertions from pred edges of BB103 for op [003533] $71f Merge assertions from pred BB102 edge: #01 #02 #32 #33 #35 #36 #43 #45 Merging ranges : [RangeCheck::GetRange] BB103 N002 ( 0, 0) [003526] ----------- * PHI_ARG int V20 loc16 u:10 $29b { ---------------------------------------------------- N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ---------------------------------------------------- [RangeCheck::GetRange] BB89 N003 ( 0, 0) [003320] ----------- * PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 { Cached Range [003320] => } Merge assertions from BB103: #01 #02 for assignment about [003319] done merging Merging assertions from pred edges of BB103 for op [003526] $29b Merge assertions from pred BB89 JTrue edge: #01 #02 #32 #33 #35 #36 #42 Computed Range [003526] => } Merging assertions from pred edges of BB103 for op [003526] $29b Merge assertions from pred BB89 JTrue edge: #01 #02 #32 #33 #35 #36 #42 Merging ranges : [RangeCheck::GetRange] BB103 N003 ( 0, 0) [003430] ----------- * PHI_ARG int V20 loc16 u:1 $c4 { Computed Range [003430] => <-1, -1> } Merging assertions from pred edges of BB103 for op [003430] $c4 Merge assertions from pred BB78 JTrue edge: #01 #02 #31 Merging ranges <-1, -1>: Computed Range [003317] => } Merge assertions from BB245: #01 #02 for assignment about [003316] done merging Merging assertions from pred edges of BB245 for op [003437] $2a5 Merge assertions from pred BB112 JTrue edge: #01 #02 Computed Range [003437] => } Merging assertions from pred edges of BB245 for op [003437] $2a5 Merge assertions from pred BB112 JTrue edge: #01 #02 Merging ranges : Computed Range [003176] => } Merge assertions from BB136: #01 #02 for assignment about [003175] done merging Merging assertions from pred edges of BB136 for op [003441] $2ac Merge assertions from pred BB113 JTrue edge: #01 #02 #57 Computed Range [003441] => } Merging assertions from pred edges of BB136 for op [003441] $2ac Merge assertions from pred BB113 JTrue edge: #01 #02 #57 Merging ranges : Computed Range [003254] => } Merge assertions from BB169: #01 #02 #32 #33 #53 for assignment about [003253] done merging Merging assertions from pred edges of BB169 for op [000714] $2b3 Computed Range [000714] => } Merging assertions from pred edges of BB169 for op [000714] $2b3 [RangeCheck::GetRange] BB169 N002 ( 1, 2) [000715] ----------- * CNS_INT int -1 $c4 { Computed Range [000715] => <-1, -1> } Merging assertions from pred edges of BB169 for op [000715] $c4 BinOp add ranges <-1, -1> = Computed Range [000716] => } Merge assertions from BB170: #01 #02 for assignment about [000717] done merging Merging assertions from pred edges of BB170 for op [003484] $ab7 Merge assertions from pred BB169 edge: #01 #02 #32 #33 #53 Computed Range [003484] => } Merging assertions from pred edges of BB170 for op [003484] $ab7 Merge assertions from pred BB169 edge: #01 #02 #32 #33 #53 Merging ranges : [RangeCheck::GetRange] BB170 N002 ( 0, 0) [003479] ----------- * PHI_ARG int V20 loc16 u:4 $2b3 { ---------------------------------------------------- N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB136 N003 ( 0, 0) [003254] ----------- * PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac { Cached Range [003254] => } Merge assertions from BB170: #01 #02 for assignment about [003253] done merging Merging assertions from pred edges of BB170 for op [003479] $2b3 Merge assertions from pred BB156 JTrue edge: #01 #02 Computed Range [003479] => } Merging assertions from pred edges of BB170 for op [003479] $2b3 Merge assertions from pred BB156 JTrue edge: #01 #02 Merging ranges : Computed Range [003173] => } Merge assertions from BB245: #01 #02 for assignment about [003172] done merging Merging assertions from pred edges of BB245 for op [003482] $ffffffff Merge assertions from pred BB170 JTrue edge: #01 #02 Computed Range [003482] => } Merging assertions from pred edges of BB245 for op [003482] $ffffffff Merge assertions from pred BB170 JTrue edge: #01 #02 Merging ranges : [RangeCheck::GetRange] BB245 N002 ( 0, 0) [003448] ----------- * PHI_ARG int V20 loc16 u:4 { Cached Range [003448] => } Merging assertions from pred edges of BB245 for op [003448] $ffffffff Merge assertions from pred BB244 edge: #01 #02 #53 Merging ranges : [RangeCheck::GetRange] BB245 N003 ( 0, 0) [003437] ----------- * PHI_ARG int V20 loc16 u:2 $2a5 { Cached Range [003437] => } Merging assertions from pred edges of BB245 for op [003437] $2a5 Merge assertions from pred BB112 JTrue edge: #01 #02 Merging ranges : Computed Range [003176] => } Merge assertions from BB135: #01 #02 #58 for assignment about [003175] done merging Merging assertions from pred edges of BB135 for op [003500] $2ac Merge assertions from pred BB114 JTrue edge: #01 #02 #58 #59 #62 #64 Computed Range [003500] => } Merging assertions from pred edges of BB135 for op [003500] $2ac Merge assertions from pred BB114 JTrue edge: #01 #02 #58 #59 #62 #64 Merging ranges : Computed Range [003251] => } Merge assertions from BB133: #01 #02 #32 #33 #53 #58 for assignment about [003250] done merging Merging assertions from pred edges of BB133 for op [000907] $b13 Computed Range [000907] => } Merging assertions from pred edges of BB133 for op [000907] $b13 [RangeCheck::GetRange] BB133 N002 ( 1, 2) [000908] ----------- * CNS_INT int -1 $c4 { Computed Range [000908] => <-1, -1> } Merging assertions from pred edges of BB133 for op [000908] $c4 BinOp add ranges <-1, -1> = Computed Range [000909] => } Merge assertions from BB134: #01 #02 #53 #58 for assignment about [000910] done merging Merging assertions from pred edges of BB134 for op [003512] $d27 Merge assertions from pred BB133 edge: #01 #02 #32 #33 #53 #58 Computed Range [003512] => } Merging assertions from pred edges of BB134 for op [003512] $d27 Merge assertions from pred BB133 edge: #01 #02 #32 #33 #53 #58 Merging ranges : [RangeCheck::GetRange] BB134 N002 ( 0, 0) [003507] ----------- * PHI_ARG int V20 loc16 u:7 $b13 { ---------------------------------------------------- N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ---------------------------------------------------- [RangeCheck::GetRange] BB135 N003 ( 0, 0) [003251] ----------- * PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac { Cached Range [003251] => } Merge assertions from BB134: #01 #02 #53 #58 for assignment about [003250] done merging Merging assertions from pred edges of BB134 for op [003507] $b13 Merge assertions from pred BB124 JTrue edge: #01 #02 #31 #53 #58 Computed Range [003507] => } Merging assertions from pred edges of BB134 for op [003507] $b13 Merge assertions from pred BB124 JTrue edge: #01 #02 #31 #53 #58 Merging ranges : Computed Range [003248] => } Merge assertions from BB135: #01 #02 #58 for assignment about [003247] done merging Merging assertions from pred edges of BB135 for op [003509] $ffffffff Merge assertions from pred BB134 edge: #01 #02 #53 #58 Computed Range [003509] => } Merging assertions from pred edges of BB135 for op [003509] $ffffffff Merge assertions from pred BB134 edge: #01 #02 #53 #58 Merging ranges : [RangeCheck::GetRange] BB135 N002 ( 0, 0) [003500] ----------- * PHI_ARG int V20 loc16 u:3 $2ac { Cached Range [003500] => } Merging assertions from pred edges of BB135 for op [003500] $2ac Merge assertions from pred BB114 JTrue edge: #01 #02 #58 #59 #62 #64 Merging ranges : Computed Range [003251] => } Merge assertions from BB136: #01 #02 for assignment about [003250] done merging Merging assertions from pred edges of BB136 for op [003504] $ffffffff Merge assertions from pred BB135 edge: #01 #02 #58 Computed Range [003504] => } Merging assertions from pred edges of BB136 for op [003504] $ffffffff Merge assertions from pred BB135 edge: #01 #02 #58 Merging ranges : [RangeCheck::GetRange] BB136 N002 ( 0, 0) [003441] ----------- * PHI_ARG int V20 loc16 u:3 $2ac { Cached Range [003441] => } Merging assertions from pred edges of BB136 for op [003441] $2ac Merge assertions from pred BB113 JTrue edge: #01 #02 #57 Merging ranges : Computed Range [003254] => } Merge assertions from BB163: #01 #02 #32 #53 for assignment about [003253] done merging Merging assertions from pred edges of BB163 for op [000692] $2b3 Computed Range [000692] => } Does overflow [000692]? Does overflow [003254]? Does overflow [003504]? Does overflow [003251]? Does overflow [003509]? Does overflow [003248]? Does overflow [003512]? Does overflow [000909]? Does overflow [000907]? Does overflow [003251]? Does overflow [003500]? Does overflow [003176]? Does overflow [003482]? Does overflow [003173]? Does overflow [003484]? Does overflow [000716]? Does overflow [000714]? Does overflow [003254]? Does overflow [003441]? Does overflow [003176]? Does overflow [003448]? Does overflow [003254]? [003254] does not overflow [003448] does not overflow Does overflow [003437]? Does overflow [003317]? Does overflow [003533]? Does overflow [001012]? Does overflow [001010]? Does overflow [003320]? Does overflow [003536]? Does overflow [001012]? Does overflow [001011]? [001011] does not overflow Checking bin op overflow ADD <1, 1> [001012] overflows [003536] overflows [003320] overflows [001010] overflows [001012] overflows [003533] overflows [003317] overflows [003437] overflows [003176] overflows [003441] overflows [003254] overflows [000714] overflows [000716] overflows [003484] overflows [003173] overflows [003482] overflows [003176] overflows [003500] overflows [003251] overflows [000907] overflows [000909] overflows [003512] overflows [003248] overflows [003509] overflows [003251] overflows [003504] overflows [003254] overflows [000692] overflows Method determined to overflow. Looking for array size assertions for: $2f2 ArrSize for lengthVN:2F2 = 0 [RangeCheck::GetRange] BB167 N001 ( 1, 1) [001972] ----------- * LCL_VAR int V103 tmp63 u:1 { ---------------------------------------------------- N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB165 N004 ( 4, 3) [001952] n---GO----- * IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 { Computed Range [001952] => } Merge assertions from BB167: #01 #02 #32 #33 #53 for assignment about [001953] done merging Merging assertions from pred edges of BB167 for op [001972] $2ee Computed Range [001972] => } Looking for array size assertions for: $2f0 ArrSize for lengthVN:2F0 = 0 [RangeCheck::GetRange] BB167 N016 ( 1, 2) [001987] ----------- * CNS_INT int 0 $c0 { Computed Range [001987] => <0, 0> } Does overflow [001987]? [001987] does not overflow Range value <0, 0> [RangeCheck::Widen] BB167, [001987] <0, 0> BetweenBounds <0, [002892]> $2f0 upper bound is: {ARR_LENGTH($1ab)} Array size is: 0 Looking for array size assertions for: $2f7 ArrSize for lengthVN:2F7 = 0 [RangeCheck::GetRange] BB178 N001 ( 1, 1) [002032] ----------- * LCL_VAR int V107 tmp67 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB176 N004 ( 4, 3) [002012] ---XG------ * IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 { Computed Range [002012] => } Merge assertions from BB178: #01 #02 #33 #53 for assignment about [002013] done merging Merging assertions from pred edges of BB178 for op [002032] $2f3 Computed Range [002032] => } Looking for array size assertions for: $2f5 ArrSize for lengthVN:2F5 = 0 [RangeCheck::GetRange] BB178 N016 ( 1, 2) [002047] ----------- * CNS_INT int 0 $c0 { Computed Range [002047] => <0, 0> } Does overflow [002047]? [002047] does not overflow Range value <0, 0> [RangeCheck::Widen] BB178, [002047] <0, 0> BetweenBounds <0, [002926]> $2f5 upper bound is: {ARR_LENGTH($1b0)} Array size is: 0 Looking for array size assertions for: $2dd ArrSize for lengthVN:2DD = 0 [RangeCheck::GetRange] BB184 N001 ( 1, 1) [002092] ----------- * LCL_VAR int V111 tmp71 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB182 N004 ( 4, 3) [002072] ---XG------ * IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 { Computed Range [002072] => } Merge assertions from BB184: #01 #02 #33 #53 for assignment about [002073] done merging Merging assertions from pred edges of BB184 for op [002092] $2d9 Computed Range [002092] => } Looking for array size assertions for: $2db ArrSize for lengthVN:2DB = 0 [RangeCheck::GetRange] BB184 N016 ( 1, 2) [002107] ----------- * CNS_INT int 0 $c0 { Computed Range [002107] => <0, 0> } Does overflow [002107]? [002107] does not overflow Range value <0, 0> [RangeCheck::Widen] BB184, [002107] <0, 0> BetweenBounds <0, [002959]> $2db upper bound is: {ARR_LENGTH($19e)} Array size is: 0 Looking for array size assertions for: $2fc ArrSize for lengthVN:2FC = 0 [RangeCheck::GetRange] BB189 N001 ( 1, 1) [002152] ----------- * LCL_VAR int V115 tmp75 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB187 N004 ( 4, 3) [002132] ---XG------ * IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 { Computed Range [002132] => } Merge assertions from BB189: #01 #02 #33 #53 for assignment about [002133] done merging Merging assertions from pred edges of BB189 for op [002152] $2f8 Computed Range [002152] => } Looking for array size assertions for: $2fa ArrSize for lengthVN:2FA = 0 [RangeCheck::GetRange] BB189 N016 ( 1, 2) [002167] ----------- * CNS_INT int 0 $c0 { Computed Range [002167] => <0, 0> } Does overflow [002167]? [002167] does not overflow Range value <0, 0> [RangeCheck::Widen] BB189, [002167] <0, 0> BetweenBounds <0, [002993]> $2fa upper bound is: {ARR_LENGTH($1b4)} Array size is: 0 Looking for array size assertions for: $2ff ArrSize for lengthVN:2FF = 0 [RangeCheck::GetRange] BB192 N001 ( 1, 1) [002201] ----------- * LCL_VAR int V118 tmp78 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB191 N004 ( 4, 3) [002186] ---XG------ * IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 { Computed Range [002186] => } Merge assertions from BB192: #01 #02 #53 for assignment about [002187] done merging Merging assertions from pred edges of BB192 for op [002201] $2fd Computed Range [002201] => } Looking for array size assertions for: $2d8 ArrSize for lengthVN:2D8 = 0 [RangeCheck::GetRange] BB203 N001 ( 1, 1) [002259] ----------- * LCL_VAR int V122 tmp82 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB202 N004 ( 4, 3) [002244] ---XG------ * IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 { Computed Range [002244] => } Merge assertions from BB203: #01 #02 #53 for assignment about [002245] done merging Merging assertions from pred edges of BB203 for op [002259] $2d6 Computed Range [002259] => } Looking for array size assertions for: $2e6 ArrSize for lengthVN:2E6 = 0 [RangeCheck::GetRange] BB216 N001 ( 1, 1) [002316] ----------- * LCL_VAR int V126 tmp86 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB215 N004 ( 4, 3) [002302] ---XG------ * IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 { Computed Range [002302] => } Merge assertions from BB216: #01 #02 #53 for assignment about [002303] done merging Merging assertions from pred edges of BB216 for op [002316] $2e4 Computed Range [002316] => } Looking for array size assertions for: $2e0 ArrSize for lengthVN:2E0 = 0 [RangeCheck::GetRange] BB228 N001 ( 1, 1) [002363] ----------- * LCL_VAR int V129 tmp89 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB227 N004 ( 4, 3) [002349] ---XG------ * IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 { Computed Range [002349] => } Merge assertions from BB228: #01 #02 #53 for assignment about [002350] done merging Merging assertions from pred edges of BB228 for op [002363] $2de Computed Range [002363] => } Looking for array size assertions for: $2e3 ArrSize for lengthVN:2E3 = 0 [RangeCheck::GetRange] BB234 N001 ( 1, 1) [002411] ----------- * LCL_VAR int V132 tmp92 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002398] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB233 N004 ( 4, 3) [002396] n---GO----- * IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 { Computed Range [002396] => } Merge assertions from BB234: #01 #02 #53 for assignment about [002397] done merging Merging assertions from pred edges of BB234 for op [002411] $2e1 Computed Range [002411] => } Looking for array size assertions for: $c82 ArrSize for lengthVN:C82 = 0 [RangeCheck::GetRange] BB237 N001 ( 1, 1) [002457] ----------- * LCL_VAR int V136 tmp96 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002444] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB236 N004 ( 4, 3) [002442] n---GO----- * IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 { Computed Range [002442] => } Merge assertions from BB237: #01 #02 #53 for assignment about [002443] done merging Merging assertions from pred edges of BB237 for op [002457] $c80 Computed Range [002457] => } Looking for array size assertions for: $2e9 ArrSize for lengthVN:2E9 = 0 [RangeCheck::GetRange] BB243 N001 ( 1, 1) [002506] ----------- * LCL_VAR int V140 tmp100 u:1 { ---------------------------------------------------- N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ---------------------------------------------------- [RangeCheck::GetRange] BB242 N004 ( 4, 3) [002492] ---XG------ * IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 { Computed Range [002492] => } Merge assertions from BB243: #01 #02 #53 for assignment about [002493] done merging Merging assertions from pred edges of BB243 for op [002506] $2e7 Computed Range [002506] => } *************** Finishing PHASE Optimize index checks Trees after Optimize index checks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [373..39A)-> BB93 (always) i hascall bwd BB92 [0219] 0 2 2 [383..384)-> BB94 (always) i bwd BB93 [0220] 1 BB91 2 2 [383..384) i idxlen nullcheck bwd BB94 [0224] 2 BB92,BB93 2 2 [000..000)-> BB110 ( cond ) internal bwd BB95 [0227] 1 BB94 2 2 [000..000) i internal hascall gcsafe bwd BB96 [0229] 1 BB95 2 2 [391..392)-> BB98 (always) i gcsafe bwd BB97 [0242] 0 2 2 [391..392)-> BB99 (always) i gcsafe bwd BB98 [0243] 1 BB96 2 2 [391..392) i gcsafe idxlen nullcheck bwd BB99 [0247] 2 BB97,BB98 2 2 [???..???) internal gcsafe bwd BB100 [0092] 2 BB90,BB99 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB94 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB212 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB213 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB212 [0168] 1 BB208 2 3 [6A8..6B5)-> BB215 (always) i bwd BB213 [0169] 2 BB209,BB210 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB212,BB213,BB214 2 3 [6D1..6DE)-> BB217 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB217 [0332] 1 BB215 2 3 [6D1..6D2)-> BB244 (always) i hascall gcsafe bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB217,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] n---GO----- | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N015 ( 16, 16) [002563] -A--------- * COMMA void $VN.Void N007 ( 8, 8) [002559] -A------R-- +--* ASG byref $VN.Void N006 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N005 ( 4, 5) [003711] -A--------- | \--* COMMA byref $246 N003 ( 3, 4) [003709] -A------R-- | +--* ASG byref $VN.Void N002 ( 1, 1) [003708] D------N--- | | +--* LCL_VAR byref V180 cse9 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 1, 1) [003710] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N014 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N013 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N012 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N010 ( 3, 4) [003689] -A------R-- +--* ASG int $VN.Void N009 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N008 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N011 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 N006 ( 7, 7) [001475] J---GO-N--- \--* NE int N004 ( 5, 4) [001473] n---GO----- +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 1, 3) [002606] -A--------- * COMMA void $580 N003 ( 1, 3) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 1, 1) [003712] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 1, 1) [003623] ----------- * COMMA void N001 ( 1, 1) [003692] ----------- +--* LCL_VAR int V179 cse8 u:1 $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 5, 5) [001441] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N014 ( 14, 16) [001452] -A-XG------ * JTRUE void $876 N013 ( 12, 14) [001451] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003627] -A-XG------ +--* COMMA int N009 ( 9, 10) [003625] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N007 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N012 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 N003 ( 3, 3) [001470] N---G--N-U- \--* NE int N001 ( 1, 1) [003628] ----------- +--* LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 5, 5) [001240] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N014 ( 14, 16) [001251] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001250] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003647] -A-XG------ +--* COMMA int N009 ( 9, 10) [003645] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N014 ( 14, 16) [001351] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001350] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003651] -A-XG------ +--* COMMA int N009 ( 9, 10) [003649] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003648] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001348] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001347] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003650] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003696] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N014 ( 14, 16) [001287] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001286] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003655] -A-XG------ +--* COMMA int N009 ( 9, 10) [003653] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003652] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001284] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001283] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003654] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 N003 ( 3, 4) [001339] N---G--N-U- \--* NE int N001 ( 1, 1) [003656] ----------- +--* LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A--GO--R-- * ASG int $301 N006 ( 3, 2) [001135] n---GO-N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ----GO----- \--* ADD int N002 ( 3, 2) [001132] n---GO----- +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A--GO--R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ----GO----- \--* SUB int N006 ( 6, 5) [001174] ----GO----- +--* ADD int N004 ( 4, 3) [001172] n---GO----- | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 21, 20) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 21, 20) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 4, 5) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 1, 1) [003713] ----------- ofs 0 | +--* LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000100] J---GO-N--- \--* EQ int N004 ( 5, 4) [000098] n---GO----- +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A--GO----- * ASG bool $301 N004 ( 5, 4) [001124] n---GO-N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A--GO----- * ASG int $301 N004 ( 4, 3) [000104] n---GO-N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N011 ( 15, 12) [000140] -A--GO----- * JTRUE void $301 N010 ( 13, 10) [000139] JA--GO-N--- \--* GT int N008 ( 11, 8) [003685] -A--GO----- +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N003 ( 7, 5) [000144] -A--G---R-- * ASG int $301 N002 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N001 ( 3, 2) [003686] ----------- \--* LCL_VAR int V178 cse7 u:1 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N005 ( 5, 4) [000154] -A--G---R-- * ASG int $301 N004 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N003 ( 5, 4) [000152] ----G------ \--* SUB int N001 ( 3, 2) [003687] ----------- +--* LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 2) [003720] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A--GO--R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] n---GO----- \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N009 ( 4, 3) [001103] -A--GO--R-- * ASG int N008 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N007 ( 4, 3) [002670] ----GO-N--- \--* COMMA int N001 ( 0, 0) [002662] ----------- +--* NOP void N006 ( 4, 3) [002671] n---GO----- \--* IND int N005 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N004 ( 1, 1) [002667] -------N--- \--* ADD byref N002 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N003 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [373..39A) -> BB93 (always), preds={BB90} succs={BB93} ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ------------ BB92 [383..384) -> BB94 (always), preds={} succs={BB94} ***** BB92 STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 ------------ BB93 [383..384), preds={BB91} succs={BB94} ***** BB93 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB93 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ------------ BB94 [000..000) -> BB110 (cond), preds={BB92,BB93} succs={BB95,BB110} ***** BB94 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB94 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB94 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB94 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..000), preds={BB94} succs={BB96} ------------ BB96 [391..392) -> BB98 (always), preds={BB95} succs={BB98} ***** BB96 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB96 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB96 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ------------ BB97 [391..392) -> BB99 (always), preds={} succs={BB99} ***** BB97 STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 ------------ BB98 [391..392), preds={BB96} succs={BB99} ***** BB98 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB98 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ------------ BB99 [???..???), preds={BB97,BB98} succs={BB100} ***** BB99 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB99 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB99 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB99} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000185] J---GO-N--- \--* EQ int N004 ( 5, 4) [000183] n---GO----- +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000934] J---GO-N--- \--* EQ int N004 ( 4, 3) [000932] n---GO----- +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ----GO----- * JTRUE void $845 N006 ( 8, 6) [001752] N---GO-N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] n---GO----- \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N023 ( 30, 29) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N022 ( 5, 4) [002775] ----GO-N--- \--* COMMA ushort N016 ( 0, 0) [002768] ----------- +--* NOP void N021 ( 5, 4) [002777] n---GO----- \--* IND ushort N020 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N019 ( 1, 1) [002772] -------N--- \--* ADD byref N017 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N018 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001780] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB94} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 1, 3) [002788] -A--------- * COMMA void $588 N003 ( 1, 3) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 1, 1) [003714] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N009 ( 9, 9) [000834] -A-XG------ * JTRUE void $c1a N008 ( 7, 7) [000833] JA-XG--N--- \--* NE int N006 ( 5, 4) [003680] -A-XG------ +--* COMMA int N004 ( 4, 3) [003678] -A-XG---R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003677] D------N--- | | +--* LCL_VAR int V177 cse6 d:1 $VN.Void N002 ( 4, 3) [000831] ---XG------ | | \--* IND ubyte N001 ( 1, 1) [000830] ----------- | | \--* LCL_VAR long V36 loc32 u:7 $904 N005 ( 1, 1) [003679] ----------- | \--* LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N003 ( 1, 3) [000855] -A--G---R-- * ASG int $c1a N002 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N001 ( 1, 1) [003681] ----------- \--* LCL_VAR int V177 cse6 u:1 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001805] N---GO-N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] n---GO----- \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] n---GO----- | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001823] n---GO----- | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001833] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N009 ( 8, 9) [001856] -A-X------- * JTRUE void N008 ( 6, 7) [001855] NA-X---N-U- \--* NE int N006 ( 4, 4) [003718] -A-X------- +--* COMMA int N004 ( 3, 3) [003716] -A-X----R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001865] N---GO-N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] n---GO----- \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] n---GO----- | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001880] n---GO----- | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001893] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001911] N---GO-N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] n---GO----- \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] n---GO----- | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001928] n---GO----- | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001938] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001968] N---GO-N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] n---GO----- \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] n---GO----- | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001983] n---GO----- | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001996] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002028] N---GO-N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] n---GO----- \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] n---GO----- | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002043] n---GO----- | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002056] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002088] N---GO-N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] n---GO----- \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] n---GO----- | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002103] n---GO----- | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002116] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002148] N---GO-N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] n---GO----- \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] n---GO----- | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002163] n---GO----- | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002176] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N003 ( 1, 3) [002225] -A--G---R-- * ASG ushort $bec N002 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N001 ( 1, 1) [003629] ----------- \--* LCL_VAR int V172 cse1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002194] N---GO-N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] n---GO----- \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] n---GO----- | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002212] n---GO----- | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002222] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N014 ( 14, 16) [000791] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000790] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003633] -A-XG------ +--* COMMA int N009 ( 9, 10) [003631] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003630] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000788] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000787] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003632] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec N003 ( 3, 3) [000801] N---G--N-U- \--* NE int N001 ( 1, 1) [003634] ----------- +--* LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N014 ( 14, 16) [000775] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000774] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003638] -A-XG------ +--* COMMA int N009 ( 9, 10) [003636] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003635] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000772] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000771] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003637] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 5, 5) [000289] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N014 ( 14, 16) [000300] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000299] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003666] -A-XG------ +--* COMMA int N009 ( 9, 10) [003664] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N003 ( 1, 3) [002283] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N001 ( 1, 1) [003667] ----------- \--* LCL_VAR int V176 cse5 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002252] N---GO-N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] n---GO----- \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] n---GO----- | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002270] n---GO----- | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002280] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N014 ( 14, 16) [000575] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000574] NA-XG--N-U- \--* EQ int N011 ( 10, 11) [003671] -A-XG------ +--* COMMA int N009 ( 9, 10) [003669] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003668] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000572] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000571] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003670] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB212 (cond), preds={BB206,BB207} succs={BB209,BB212} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003703] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N014 ( 14, 16) [000548] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000547] NA-XG--N-U- \--* NE int N011 ( 10, 11) [003675] -A-XG------ +--* COMMA int N009 ( 9, 10) [003673] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB213 (cond), preds={BB209} succs={BB211,BB213} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB212 [6A8..6B5) -> BB215 (always), preds={BB208} succs={BB215} ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209,BB210} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a N003 ( 3, 4) [000456] N---G--N-U- \--* NE int N001 ( 1, 1) [003676] ----------- +--* LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB217 (cond), preds={BB212,BB213,BB214} succs={BB216,BB217} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002310] N---GO-N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] n---GO----- \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] n---GO----- | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002327] n---GO----- | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002337] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB217 [6D1..6D2) -> BB244 (always), preds={BB215} succs={BB244} ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A--GO--R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ----GO----- \--* SUB int N004 ( 4, 3) [000513] n---GO----- +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002357] N---GO-N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] n---GO----- \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] n---GO----- | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002374] n---GO----- | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002384] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N014 ( 14, 16) [000353] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000352] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003660] -A-XG------ +--* COMMA int N009 ( 9, 10) [003658] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003657] D------N--- | | +--* LCL_VAR int V175 cse4 d:1 $VN.Void N007 ( 9, 10) [000350] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000349] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003659] ----------- | \--* LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a N003 ( 3, 4) [000417] N---G--N-U- \--* NE int N001 ( 1, 1) [003661] ----------- +--* LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N003 ( 1, 3) [002435] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N001 ( 1, 1) [003662] ----------- \--* LCL_VAR int V175 cse4 u:1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002404] N---GO-N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] n---GO----- \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] n---GO----- | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002422] n---GO----- | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002432] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N003 ( 1, 3) [002481] -A--G---R-- * ASG ushort $c02 N002 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N001 ( 1, 1) [003639] ----------- \--* LCL_VAR int V173 cse2 u:1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002450] N---GO-N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] n---GO----- \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] n---GO----- | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002468] n---GO----- | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002478] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N014 ( 14, 16) [000389] -A-XG------ * JTRUE void $c02 N013 ( 12, 14) [000388] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003643] -A-XG------ +--* COMMA int N009 ( 9, 10) [003641] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003640] D------N--- | | +--* LCL_VAR int V173 cse2 d:1 $VN.Void N007 ( 9, 10) [000386] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000385] -------N--- | | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003642] ----------- | \--* LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002500] N---GO-N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] n---GO----- \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] n---GO----- | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002517] n---GO----- | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002527] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB217,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000218] J---GO-N--- \--* EQ int N004 ( 5, 4) [000216] n---GO----- +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000228] J---GO-N--- \--* NE int N004 ( 4, 3) [000226] n---GO----- +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE VN-based dead store removal Considering [003369] for removal... Considering [001434] for removal... Considering [001381] for removal... Considering [003390] for removal... Considering [003360] for removal... Considering [001196] for removal... Considering [001394] for removal... Considering [003399] for removal... Considering [000118] for removal... Considering [003396] for removal... Considering [001387] for removal... Considering [003393] for removal... Considering [000131] for removal... Considering [001384] for removal... Considering [003171] for removal... Considering [003240] for removal... Considering [000673] for removal... Considering [003237] for removal... Considering [000868] for removal... Considering [000148] for removal... Considering [001110] for removal... Considering [003402] for removal... Considering [003207] for removal... Considering [000511] for removal... Considering [001318] for removal... Considering [003381] for removal... Considering [001409] for removal... Considering [003378] for removal... Considering [003375] for removal... Considering [001412] for removal... Considering [001424] for removal... Considering [003387] for removal... Considering [003357] for removal... Considering [001186] for removal... Considering [003384] for removal... Considering [001419] for removal... Considering [003372] for removal... Considering [003354] for removal... Considering [001193] for removal... Considering [001360] for removal... Considering [001429] for removal... Considering [003189] for removal... Considering [003246] for removal... Considering [003186] for removal... Considering [000735] for removal... Considering [003243] for removal... Considering [000873] for removal... Considering [000154] for removal... Considering [001113] for removal... Considering [003162] for removal... Considering [001170] for removal... Considering [003366] for removal... Considering [000157] for removal... Considering [003165] for removal... Considering [000248] for removal... Considering [003234] for removal... Considering [000397] for removal... Considering [000361] for removal... Considering [003225] for removal... Considering [000479] for removal... Considering [003222] for removal... Considering [000308] for removal... Considering [003168] for removal... Considering [000780] for removal... Considering [000810] for removal... Considering [001163] for removal... Considering [001203] for removal... Considering [003405] for removal... Considering [001309] for removal... Considering [001256] for removal... Considering [003363] for removal... Considering [001459] for removal... Considering [003180] for removal... Considering [000664] for removal... Considering [000746] for removal... Considering [001218] for removal... Considering [003318] for removal... Considering [003177] for removal... Considering [003255] for removal... Considering [003174] for removal... Considering [000718] for removal... Considering [003252] for removal... Considering [003249] for removal... Considering [000911] for removal... Considering [003321] for removal... Considering [001014] for removal... Considering [003204] for removal... Considering [000624] for removal... Considering [003279] for removal... Considering [003276] for removal... Considering [001054] for removal... Considering [003333] for removal... Considering [003273] for removal... Considering [001049] for removal... Considering [001103] for removal... Considering [003285] for removal... Considering [003282] for removal... Considering [001060] for removal... Considering [003201] for removal... Considering [003270] for removal... Considering [003198] for removal... Considering [003195] for removal... Considering [000654] for removal... Considering [003267] for removal... Considering [003264] for removal... Considering [000846] for removal... Considering [003228] for removal... Considering [003231] for removal... Considering [000564] for removal... Considering [003216] for removal... Considering [003213] for removal... Considering [000521] for removal... Considering [003219] for removal... Considering [000537] for removal... Considering [000026] for removal... Considering [001487] for removal... Considering [001494] for removal... Considering [000114] for removal... Considering [001120] for removal... Considering [000127] for removal... Considering [001116] for removal... Considering [000144] for removal... Considering [001106] for removal... Considering [000497] for removal... Considering [000517] for removal... Considering [000660] for removal... Considering [000725] for removal... Considering [000729] for removal... Considering [000742] for removal... Considering [000749] for removal... Considering [000852] for removal... Considering [000914] for removal... Considering [000855] for removal... Considering [000917] for removal... Considering [000981] for removal... Considering [001093] for removal... Considering [000984] for removal... Considering [001096] for removal... Considering [000997] for removal... Considering [001089] for removal... Considering [001143] for removal... Considering [001178] for removal... Considering [003300] for removal... Considering [003303] for removal... Considering [003297] for removal... Considering [002724] for removal... Considering [003291] for removal... Considering [003294] for removal... Considering [003288] for removal... Considering [002727] for removal... Considering [002589] for removal... Considering [002582] for removal... Considering [002575] for removal... Considering [002592] for removal... Considering [002585] for removal... Considering [002578] for removal... Considering [001604] for removal... Considering [002682] for removal... Considering [001610] for removal... Considering [002685] for removal... Considering [001716] for removal... Considering [002711] for removal... Considering [001722] for removal... Considering [002714] for removal... *************** Finishing PHASE VN-based dead store removal [no changes] *************** Starting PHASE Update flow graph opt pass fgRemoveBlock BB92, unreachable=true Removing unreachable BB92 removing useless STMT00333 ( INL15 @ 0x003[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N007 ( 2, 6) [002686] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002682] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002680] D------N--- | +--* LCL_VAR byref V159 tmp119 d:3 $VN.Void N001 ( 1, 2) [002681] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002685] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002683] D------N--- +--* LCL_VAR int V160 tmp120 d:3 $VN.Void N004 ( 1, 2) [002684] ----------- \--* CNS_INT int 0 $c0 from BB92 BB92 becomes empty Compacting blocks BB93 and BB94: *************** In fgDebugCheckBBlist Compacting blocks BB95 and BB96: *************** In fgDebugCheckBBlist fgRemoveBlock BB97, unreachable=true Removing unreachable BB97 removing useless STMT00357 ( INL23 @ 0x003[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N007 ( 2, 6) [002715] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002711] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002709] D------N--- | +--* LCL_VAR byref V163 tmp123 d:3 $VN.Void N001 ( 1, 2) [002710] ----------- | \--* CNS_INT byref 0 $VN.Null N006 ( 1, 3) [002714] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002712] D------N--- +--* LCL_VAR int V164 tmp124 d:3 $VN.Void N004 ( 1, 2) [002713] ----------- \--* CNS_INT int 0 $c0 from BB97 BB97 becomes empty Compacting blocks BB98 and BB99: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB208 -> BB212 -> BB215) Setting edge weights for BB208 -> BB215 to [0 .. 3.402823e+38] fgRemoveBlock BB212, unreachable=true Removing unreachable BB212 Optimizing a jump to an unconditional jump (BB215 -> BB217 -> BB244) Setting edge weights for BB215 -> BB244 to [0 .. 3.402823e+38] fgRemoveBlock BB217, unreachable=true Removing unreachable BB217 Compacting blocks BB91 and BB93: *************** In fgDebugCheckBBlist Compacting blocks BB95 and BB98: *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph opt pass Trees after Update flow graph opt pass ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109)-> BB47 ( cond ) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E)-> BB47 ( cond ) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E)-> BB47 ( cond ) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 27 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i BB79 [0079] 1 BB78 0.50 [30D..31E)-> BB103 ( cond ) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 5 BB78,BB79,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4)-> BB112 ( cond ) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB111 ( cond ) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 2 BB107,BB108 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 6 BB103,BB104,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412)-> BB135 ( cond ) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A)-> BB134 ( cond ) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F)-> BB134 ( cond ) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB132 ( cond ) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 2 BB129,BB130 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 5 BB124,BB125,BB126,BB127,BB133 8 3 [461..46D) i bwd BB135 [0115] 4 BB114,BB115,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532)-> BB170 ( cond ) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547)-> BB170 ( cond ) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB168 ( cond ) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 2 BB165,BB166 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 6 BB156,BB160,BB161,BB162,BB163,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584)-> BB245 ( cond ) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB179 ( cond ) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 2 BB176,BB177 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB185 ( cond ) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 2 BB182,BB183 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB190 ( cond ) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 2 BB187,BB188 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634)-> BB245 ( cond ) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3)-> BB213 ( cond ) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB213 [0169] 2 BB209,BB210 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 27 BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1)-> BB253 ( cond ) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2)-> BB253 ( cond ) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 5 BB248,BB249,BB250,BB251,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] n---GO----- | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N015 ( 16, 16) [002563] -A--------- * COMMA void $VN.Void N007 ( 8, 8) [002559] -A------R-- +--* ASG byref $VN.Void N006 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N005 ( 4, 5) [003711] -A--------- | \--* COMMA byref $246 N003 ( 3, 4) [003709] -A------R-- | +--* ASG byref $VN.Void N002 ( 1, 1) [003708] D------N--- | | +--* LCL_VAR byref V180 cse9 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 1, 1) [003710] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N014 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N013 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N012 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N010 ( 3, 4) [003689] -A------R-- +--* ASG int $VN.Void N009 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N008 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N011 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 N006 ( 7, 7) [001475] J---GO-N--- \--* NE int N004 ( 5, 4) [001473] n---GO----- +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 1, 3) [002606] -A--------- * COMMA void $580 N003 ( 1, 3) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 1, 1) [003712] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 1, 1) [003623] ----------- * COMMA void N001 ( 1, 1) [003692] ----------- +--* LCL_VAR int V179 cse8 u:1 $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N004 ( 5, 6) [001398] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001397] J------N--- \--* LE int $691 N001 ( 1, 1) [001395] ----------- +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109) -> BB47 (cond), preds={BB23} succs={BB25,BB47} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N004 ( 5, 6) [001402] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001401] J------N--- \--* GE int $690 N001 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N004 ( 5, 5) [001441] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001440] J------N--- \--* GE int $8b7 N001 ( 1, 1) [001435] ----------- +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB32 [150..15E) -> BB47 (cond), preds={BB31} succs={BB33,BB47} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N014 ( 14, 16) [001452] -A-XG------ * JTRUE void $876 N013 ( 12, 14) [001451] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003627] -A-XG------ +--* COMMA int N009 ( 9, 10) [003625] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N007 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N001 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001447] ----------- | | \--* LSH long $3df N003 ( 2, 3) [001444] ----------- | | +--* CAST long <- int $3de N002 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N004 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N012 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 N003 ( 3, 3) [001470] N---G--N-U- \--* NE int N001 ( 1, 1) [003628] ----------- +--* LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N004 ( 5, 5) [001240] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001239] J------N--- \--* GE int $36c N001 ( 1, 1) [001234] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB36 [183..18E) -> BB47 (cond), preds={BB35} succs={BB37,BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N014 ( 14, 16) [001251] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001250] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003647] -A-XG------ +--* COMMA int N009 ( 9, 10) [003645] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001246] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001243] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N014 ( 14, 16) [001351] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001350] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003651] -A-XG------ +--* COMMA int N009 ( 9, 10) [003649] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003648] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001348] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001347] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003650] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003696] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N014 ( 14, 16) [001287] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001286] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003655] -A-XG------ +--* COMMA int N009 ( 9, 10) [003653] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003652] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001284] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001283] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003654] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 N003 ( 3, 4) [001339] N---G--N-U- \--* NE int N001 ( 1, 1) [003656] ----------- +--* LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB24,BB27,BB29,BB30,BB31,BB32,BB34,BB35,BB36,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A--GO--R-- * ASG int $301 N006 ( 3, 2) [001135] n---GO-N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ----GO----- \--* ADD int N002 ( 3, 2) [001132] n---GO----- +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A--GO--R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ----GO----- \--* SUB int N006 ( 6, 5) [001174] ----GO----- +--* ADD int N004 ( 4, 3) [001172] n---GO----- | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 21, 20) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 21, 20) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 4, 5) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 1, 1) [003713] ----------- ofs 0 | +--* LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000100] J---GO-N--- \--* EQ int N004 ( 5, 4) [000098] n---GO----- +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A--GO----- * ASG bool $301 N004 ( 5, 4) [001124] n---GO-N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A--GO----- * ASG int $301 N004 ( 4, 3) [000104] n---GO-N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N011 ( 15, 12) [000140] -A--GO----- * JTRUE void $301 N010 ( 13, 10) [000139] JA--GO-N--- \--* GT int N008 ( 11, 8) [003685] -A--GO----- +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N003 ( 7, 5) [000144] -A--G---R-- * ASG int $301 N002 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N001 ( 3, 2) [003686] ----------- \--* LCL_VAR int V178 cse7 u:1 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N005 ( 5, 4) [000154] -A--G---R-- * ASG int $301 N004 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N003 ( 5, 4) [000152] ----G------ \--* SUB int N001 ( 3, 2) [003687] ----------- +--* LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 2) [003720] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N004 ( 5, 6) [000181] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000180] J------N--- \--* EQ int $70a N001 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E) -> BB103 (cond), preds={BB78} succs={BB80,BB103} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N008 ( 10, 10) [000947] ---XG------ * JTRUE void N007 ( 8, 8) [000946] J--XG--N--- \--* LE int N005 ( 6, 5) [000944] ---XG------ +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | \--* IND ref N003 ( 3, 4) [002656] -------N--- | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- \--* CNS_INT int 0 $c0 ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A--GO--R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] n---GO----- \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N009 ( 4, 3) [001103] -A--GO--R-- * ASG int N008 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N007 ( 4, 3) [002670] ----GO-N--- \--* COMMA int N001 ( 0, 0) [002662] ----------- +--* NOP void N006 ( 4, 3) [002671] n---GO----- \--* IND int N005 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N004 ( 1, 1) [002667] -------N--- \--* ADD byref N002 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N003 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} ***** BB91 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB91 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ***** BB91 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB91 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ***** BB91 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB91 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..392), preds={BB91} succs={BB100} ***** BB95 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB95 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB95 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB95 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB95 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ***** BB95 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB95 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ***** BB95 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB79,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N007 ( 9, 9) [000186] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000185] J---GO-N--- \--* EQ int N004 ( 5, 4) [000183] n---GO----- +--* IND bool N003 ( 3, 4) [002744] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4) -> BB112 (cond), preds={BB103} succs={BB105,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N004 ( 5, 6) [000930] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000929] J------N--- \--* NE int $733 N001 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N002 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000934] J---GO-N--- \--* EQ int N004 ( 4, 3) [000932] n---GO----- +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 7, 8) [001743] ---X------- * JTRUE void N004 ( 5, 6) [001742] N--X---N-U- \--* NE int N002 ( 3, 3) [001740] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- \--* CNS_INT int 1 $c1 ------------ BB108 [3DC..3DD) -> BB111 (cond), preds={BB107} succs={BB109,BB111} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N007 ( 10, 8) [001753] ----GO----- * JTRUE void $845 N006 ( 8, 6) [001752] N---GO-N-U- \--* GE int N001 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001786] n---GO----- \--* IND int N004 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N023 ( 30, 29) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N022 ( 5, 4) [002775] ----GO-N--- \--* COMMA ushort N016 ( 0, 0) [002768] ----------- +--* NOP void N021 ( 5, 4) [002777] n---GO----- \--* IND ushort N020 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N019 ( 1, 1) [002772] -------N--- \--* ADD byref N017 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N018 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001780] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB91} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107,BB108} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB104,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 1, 3) [002788] -A--------- * COMMA void $588 N003 ( 1, 3) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 1, 1) [003714] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N004 ( 5, 6) [000824] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000823] J------N--- \--* EQ int N001 ( 1, 1) [000821] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- \--* CNS_INT int 35 $ea ------------ BB115 [40C..412) -> BB135 (cond), preds={BB114} succs={BB116,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N004 ( 5, 6) [000922] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000921] J------N--- \--* EQ int N001 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N009 ( 9, 9) [000834] -A-XG------ * JTRUE void $c1a N008 ( 7, 7) [000833] JA-XG--N--- \--* NE int N006 ( 5, 4) [003680] -A-XG------ +--* COMMA int N004 ( 4, 3) [003678] -A-XG---R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003677] D------N--- | | +--* LCL_VAR int V177 cse6 d:1 $VN.Void N002 ( 4, 3) [000831] ---XG------ | | \--* IND ubyte N001 ( 1, 1) [000830] ----------- | | \--* LCL_VAR long V36 loc32 u:7 $904 N005 ( 1, 1) [003679] ----------- | \--* LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N003 ( 1, 3) [000855] -A--G---R-- * ASG int $c1a N002 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N001 ( 1, 1) [003681] ----------- \--* LCL_VAR int V177 cse6 u:1 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001805] N---GO-N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] n---GO----- \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] n---GO----- | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001823] n---GO----- | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001833] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N004 ( 5, 6) [000863] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000862] J------N--- \--* EQ int $70a N001 ( 1, 1) [000860] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- \--* CNS_INT int 0 $c0 ------------ BB125 [435..43A) -> BB134 (cond), preds={BB124} succs={BB126,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N004 ( 5, 6) [000877] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000876] J------N--- \--* LE int $d03 N001 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N002 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N004 ( 5, 6) [000881] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000880] J------N--- \--* LT int $d04 N001 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F) -> BB134 (cond), preds={BB126} succs={BB128,BB134} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N016 ( 20, 25) [000901] ---XGO----- * JTRUE void $c34 N015 ( 18, 23) [000900] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000899] ---XGO----- +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- \--* LCL_VAR int V08 loc4 u:5 $b15 ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N009 ( 8, 9) [001856] -A-X------- * JTRUE void N008 ( 6, 7) [001855] NA-X---N-U- \--* NE int N006 ( 4, 4) [003718] -A-X------- +--* COMMA int N004 ( 3, 3) [003716] -A-X----R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- \--* CNS_INT int 1 $c1 ------------ BB130 [44F..450) -> BB132 (cond), preds={BB129} succs={BB131,BB132} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N007 ( 8, 7) [001866] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001865] N---GO-N-U- \--* GE int N001 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001899] n---GO----- \--* IND int N004 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] n---GO----- | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001880] n---GO----- | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001893] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129,BB130} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB126,BB127,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001911] N---GO-N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] n---GO----- \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] n---GO----- | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001928] n---GO----- | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001938] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N004 ( 5, 6) [000680] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000679] J------N--- \--* EQ int $70a N001 ( 1, 1) [000677] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- \--* CNS_INT int 0 $c0 ------------ BB161 [52D..532) -> BB170 (cond), preds={BB160} succs={BB162,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N004 ( 5, 6) [000684] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000683] J------N--- \--* LE int $a93 N001 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N004 ( 5, 6) [000688] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000687] J------N--- \--* LT int $a94 N001 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547) -> BB170 (cond), preds={BB162} succs={BB164,BB170} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N016 ( 20, 25) [000708] ---XGO----- * JTRUE void $a37 N015 ( 18, 23) [000707] N--XGO-N-U- \--* NE int N013 ( 16, 21) [000706] ---XGO----- +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- \--* LCL_VAR int V08 loc4 u:3 $2b5 ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 7, 8) [001959] ---X------- * JTRUE void N004 ( 5, 6) [001958] N--X---N-U- \--* NE int N002 ( 3, 3) [001956] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- \--* CNS_INT int 1 $c1 ------------ BB166 [547..548) -> BB168 (cond), preds={BB165} succs={BB167,BB168} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N007 ( 8, 7) [001969] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001968] N---GO-N-U- \--* GE int N001 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [002002] n---GO----- \--* IND int N004 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] n---GO----- | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001983] n---GO----- | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001996] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165,BB166} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB162,BB163,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N004 ( 5, 5) [000628] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000627] J------N--- \--* GE int $abe N001 ( 1, 1) [000625] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB174 [57C..584) -> BB245 (cond), preds={BB173} succs={BB175,BB245} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N005 ( 8, 8) [000633] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000632] J--XG--N--- \--* EQ int N002 ( 4, 3) [000630] ---XG------ +--* IND ubyte N001 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 7, 8) [002019] ---X------- * JTRUE void N004 ( 5, 6) [002018] N--X---N-U- \--* NE int N002 ( 3, 3) [002016] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- \--* CNS_INT int 1 $c1 ------------ BB177 [584..585) -> BB179 (cond), preds={BB176} succs={BB178,BB179} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N007 ( 8, 7) [002029] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002028] N---GO-N-U- \--* GE int N001 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002062] n---GO----- \--* IND int N004 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] n---GO----- | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002043] n---GO----- | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002056] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176,BB177} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 7, 8) [002079] ---X------- * JTRUE void N004 ( 5, 6) [002078] N--X---N-U- \--* NE int N002 ( 3, 3) [002076] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- \--* CNS_INT int 1 $c1 ------------ BB183 [598..599) -> BB185 (cond), preds={BB182} succs={BB184,BB185} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N007 ( 8, 7) [002089] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002088] N---GO-N-U- \--* GE int N001 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002122] n---GO----- \--* IND int N004 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] n---GO----- | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002103] n---GO----- | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002116] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182,BB183} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 7, 8) [002139] ---X------- * JTRUE void N004 ( 5, 6) [002138] N--X---N-U- \--* NE int N002 ( 3, 3) [002136] ---X------- +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- \--* CNS_INT int 1 $c1 ------------ BB188 [5A9..5AA) -> BB190 (cond), preds={BB187} succs={BB189,BB190} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N007 ( 8, 7) [002149] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002148] N---GO-N-U- \--* GE int N001 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002182] n---GO----- \--* IND int N004 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] n---GO----- | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002163] n---GO----- | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002176] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187,BB188} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N003 ( 1, 3) [002225] -A--G---R-- * ASG ushort $bec N002 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N001 ( 1, 1) [003629] ----------- \--* LCL_VAR int V172 cse1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002194] N---GO-N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] n---GO----- \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] n---GO----- | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002212] n---GO----- | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002222] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N014 ( 14, 16) [000791] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000790] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003633] -A-XG------ +--* COMMA int N009 ( 9, 10) [003631] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003630] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000788] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000787] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003632] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec N003 ( 3, 3) [000801] N---G--N-U- \--* NE int N001 ( 1, 1) [003634] ----------- +--* LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N014 ( 14, 16) [000775] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000774] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003638] -A-XG------ +--* COMMA int N009 ( 9, 10) [003636] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003635] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000772] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000771] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003637] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N004 ( 5, 5) [000289] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000288] J------N--- \--* GE int $94d N001 ( 1, 1) [000283] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB201 [626..634) -> BB245 (cond), preds={BB200} succs={BB202,BB245} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N014 ( 14, 16) [000300] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000299] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003666] -A-XG------ +--* COMMA int N009 ( 9, 10) [003664] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000295] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000292] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N003 ( 1, 3) [002283] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N001 ( 1, 1) [003667] ----------- \--* LCL_VAR int V176 cse5 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002252] N---GO-N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] n---GO----- \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] n---GO----- | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002270] n---GO----- | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002280] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N014 ( 14, 16) [000575] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000574] NA-XG--N-U- \--* EQ int N011 ( 10, 11) [003671] -A-XG------ +--* COMMA int N009 ( 9, 10) [003669] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003668] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000572] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000571] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003670] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003703] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N014 ( 14, 16) [000548] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000547] NA-XG--N-U- \--* NE int N011 ( 10, 11) [003675] -A-XG------ +--* COMMA int N009 ( 9, 10) [003673] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- \--* CNS_INT int 43 $d9 ------------ BB210 [694..6A3) -> BB213 (cond), preds={BB209} succs={BB211,BB213} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N012 ( 15, 18) [000561] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000560] N--XG--N-U- \--* NE int N009 ( 11, 13) [000558] ---XG------ +--* IND ushort N008 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209,BB210} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a N003 ( 3, 4) [000456] N---G--N-U- \--* NE int N001 ( 1, 1) [003676] ----------- +--* LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002310] N---GO-N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] n---GO----- \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] n---GO----- | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002327] n---GO----- | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002337] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A--GO--R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ----GO----- \--* SUB int N004 ( 4, 3) [000513] n---GO----- +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002357] N---GO-N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] n---GO----- \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] n---GO----- | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002374] n---GO----- | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002384] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N014 ( 14, 16) [000353] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000352] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003660] -A-XG------ +--* COMMA int N009 ( 9, 10) [003658] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003657] D------N--- | | +--* LCL_VAR int V175 cse4 d:1 $VN.Void N007 ( 9, 10) [000350] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000349] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003659] ----------- | \--* LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a N003 ( 3, 4) [000417] N---G--N-U- \--* NE int N001 ( 1, 1) [003661] ----------- +--* LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N003 ( 1, 3) [002435] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N001 ( 1, 1) [003662] ----------- \--* LCL_VAR int V175 cse4 u:1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002404] N---GO-N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] n---GO----- \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] n---GO----- | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002422] n---GO----- | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002432] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N003 ( 1, 3) [002481] -A--G---R-- * ASG ushort $c02 N002 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N001 ( 1, 1) [003639] ----------- \--* LCL_VAR int V173 cse2 u:1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002450] N---GO-N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] n---GO----- \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] n---GO----- | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002468] n---GO----- | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002478] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N014 ( 14, 16) [000389] -A-XG------ * JTRUE void $c02 N013 ( 12, 14) [000388] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003643] -A-XG------ +--* COMMA int N009 ( 9, 10) [003641] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003640] D------N--- | | +--* LCL_VAR int V173 cse2 d:1 $VN.Void N007 ( 9, 10) [000386] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000385] -------N--- | | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003642] ----------- | \--* LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002500] N---GO-N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] n---GO----- \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] n---GO----- | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002517] n---GO----- | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002527] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB215,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB174,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB201,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N007 ( 9, 9) [000219] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000218] J---GO-N--- \--* EQ int N004 ( 5, 4) [000216] n---GO----- +--* IND bool N003 ( 3, 4) [003148] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1) -> BB253 (cond), preds={BB248} succs={BB250,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N004 ( 5, 6) [000224] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000223] J------N--- \--* NE int $733 N001 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N002 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N007 ( 8, 8) [000229] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000228] J---GO-N--- \--* NE int N004 ( 4, 3) [000226] n---GO----- +--* IND int N003 ( 3, 4) [003150] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2) -> BB253 (cond), preds={BB250} succs={BB252,BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N007 ( 8, 8) [000235] ---XG------ * JTRUE void $845 N006 ( 6, 6) [000234] J--XG--N--- \--* LE int N004 ( 4, 3) [002539] ---XG------ +--* IND int N003 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N001 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB250,BB251,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Compute edge weights (2, false) -- not optimizing or no profile data, so not computing edge weights *************** Finishing PHASE Compute edge weights (2, false) [no changes] *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Optimize bools *************** In optOptimizeBools() HERE Optimized: ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N008 ( 15, 11) [001398] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003726] J------N--- \--* AND int N003 ( 6, 4) [001397] -------N--- +--* LE int $691 N001 ( 1, 1) [001395] ----------- | +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [001401] -------N--- \--* GE int $690 N004 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109), preds={BB23} succs={BB25} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N001 ( 0, 0) [003727] ----------- * NOP void HERE Optimized: ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N018 ( 24, 20) [001441] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003728] JA-XG--N--- \--* AND int N003 ( 6, 3) [001440] -------N--- +--* GE int $8b7 N001 ( 1, 1) [001435] ----------- | +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001451] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003627] -A-XG------ +--* COMMA int N012 ( 9, 10) [003625] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N010 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N009 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N004 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N008 ( 4, 6) [001447] ----------- | | \--* LSH long $3df N006 ( 2, 3) [001444] ----------- | | +--* CAST long <- int $3de N005 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N007 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB32 [150..15E), preds={BB31} succs={BB33} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N001 ( 0, 0) [003729] ----------- * NOP void HERE Optimized: ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N018 ( 24, 20) [001240] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003730] JA-XG--N--- \--* AND int N003 ( 6, 3) [001239] -------N--- +--* GE int $36c N001 ( 1, 1) [001234] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001250] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003647] -A-XG------ +--* COMMA int N012 ( 9, 10) [003645] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N010 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N009 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N004 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N008 ( 4, 6) [001246] ----------- | | \--* LSH long $3c9 N006 ( 2, 3) [001243] ----------- | | +--* CAST long <- int $3c8 N005 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N007 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N015 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB36 [183..18E), preds={BB35} succs={BB37} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N001 ( 0, 0) [003731] ----------- * NOP void HERE HERE HERE HERE HERE HERE HERE HERE Optimized: ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 2) [003720] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N012 ( 20, 15) [000181] ---XG------ * JTRUE void $VN.Void N011 ( 18, 13) [003732] J--XG--N--- \--* AND int N007 ( 11, 8) [000946] ---XG--N--- +--* LE int N005 ( 6, 5) [000944] ---XG------ | +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | | \--* IND ref N003 ( 3, 4) [002656] -------N--- | | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- | \--* CNS_INT int 0 $c0 N010 ( 6, 4) [000180] -------N--- \--* EQ int $70a N008 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E), preds={BB78} succs={BB80} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N001 ( 0, 0) [003733] ----------- * NOP void HERE HERE Optimized: ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N011 ( 19, 14) [000186] ----GO----- * JTRUE void $301 N010 ( 17, 12) [003734] J---GO-N--- \--* AND int N006 ( 10, 7) [000185] ----GO-N--- +--* EQ int N004 ( 5, 4) [000183] n---GO----- | +--* IND bool N003 ( 3, 4) [002744] -------N--- | | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000929] -------N--- \--* NE int $733 N007 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4), preds={BB103} succs={BB105} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N001 ( 0, 0) [003735] ----------- * NOP void HERE HERE Optimized: ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N012 ( 22, 15) [001743] ---XGO----- * JTRUE void N011 ( 20, 13) [003736] J--XGO-N--- \--* AND int N004 ( 8, 6) [001742] N--X---N-U- +--* NE int N002 ( 3, 3) [001740] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- | \--* CNS_INT int 1 $c1 N010 ( 11, 6) [001752] N---GO-N-U- \--* GE int N005 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N009 ( 4, 3) [001786] n---GO----- \--* IND int N008 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N006 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB108 [3DC..3DD), preds={BB107} succs={BB109} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N001 ( 0, 0) [003737] ----------- * NOP void HERE Optimized: ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N008 ( 15, 11) [000824] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003738] J------N--- \--* AND int N003 ( 6, 4) [000823] -------N--- +--* EQ int N001 ( 1, 1) [000821] ----------- | +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- | \--* CNS_INT int 35 $ea N006 ( 6, 4) [000921] -------N--- \--* EQ int N004 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB115 [40C..412), preds={BB114} succs={BB116} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N001 ( 0, 0) [003739] ----------- * NOP void HERE Optimized: ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N008 ( 15, 11) [000863] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003740] J------N--- \--* AND int N003 ( 6, 4) [000862] -------N--- +--* EQ int $70a N001 ( 1, 1) [000860] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000876] -------N--- \--* LE int $d03 N004 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB125 [435..43A), preds={BB124} succs={BB126} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N001 ( 0, 0) [003741] ----------- * NOP void HERE Optimized: ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N020 ( 30, 30) [000881] ---XGO----- * JTRUE void $VN.Void N019 ( 28, 28) [003742] J--XGO-N--- \--* AND int N015 ( 21, 23) [000900] N--XGO-N-U- +--* NE int N013 ( 16, 21) [000899] ---XGO----- | +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- | \--* LCL_VAR int V08 loc4 u:5 $b15 N018 ( 6, 4) [000880] -------N--- \--* LT int $d04 N016 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F), preds={BB126} succs={BB128} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N001 ( 0, 0) [003743] ----------- * NOP void HERE Optimized: ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N016 ( 21, 15) [001856] -A-XGO----- * JTRUE void N015 ( 19, 13) [003744] JA-XGO-N--- \--* AND int N008 ( 9, 7) [001855] NA-X---N-U- +--* NE int N006 ( 4, 4) [003718] -A-X------- | +--* COMMA int N004 ( 3, 3) [003716] -A-X----R-- | | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- | \--* CNS_INT int 1 $c1 N014 ( 9, 5) [001865] N---GO-N-U- \--* GE int N009 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N013 ( 4, 3) [001899] n---GO----- \--* IND int N012 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N010 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N011 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB130 [44F..450), preds={BB129} succs={BB131} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N001 ( 0, 0) [003745] ----------- * NOP void HERE Optimized: ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N008 ( 15, 11) [000680] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003746] J------N--- \--* AND int N003 ( 6, 4) [000679] -------N--- +--* EQ int $70a N001 ( 1, 1) [000677] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000683] -------N--- \--* LE int $a93 N004 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB161 [52D..532), preds={BB160} succs={BB162} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N001 ( 0, 0) [003747] ----------- * NOP void HERE Optimized: ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N020 ( 30, 30) [000688] ---XGO----- * JTRUE void $VN.Void N019 ( 28, 28) [003748] J--XGO-N--- \--* AND int N015 ( 21, 23) [000707] N--XGO-N-U- +--* NE int N013 ( 16, 21) [000706] ---XGO----- | +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- | \--* LCL_VAR int V08 loc4 u:3 $2b5 N018 ( 6, 4) [000687] -------N--- \--* LT int $a94 N016 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547), preds={BB162} succs={BB164} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N001 ( 0, 0) [003749] ----------- * NOP void HERE Optimized: ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N012 ( 20, 14) [001959] ---XGO----- * JTRUE void N011 ( 18, 12) [003750] J--XGO-N--- \--* AND int N004 ( 8, 6) [001958] N--X---N-U- +--* NE int N002 ( 3, 3) [001956] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [001968] N---GO-N-U- \--* GE int N005 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N009 ( 4, 3) [002002] n---GO----- \--* IND int N008 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N006 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB166 [547..548), preds={BB165} succs={BB167} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N001 ( 0, 0) [003751] ----------- * NOP void HERE Optimized: ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N009 ( 18, 12) [000628] ---XG------ * JTRUE void $VN.Void N008 ( 16, 10) [003752] J--XG--N--- \--* AND int N003 ( 6, 3) [000627] -------N--- +--* GE int $abe N001 ( 1, 1) [000625] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 9, 6) [000632] ---XG--N--- \--* EQ int N005 ( 4, 3) [000630] ---XG------ +--* IND ubyte N004 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N006 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB174 [57C..584), preds={BB173} succs={BB175} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N001 ( 0, 0) [003753] ----------- * NOP void HERE Optimized: ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N012 ( 20, 14) [002019] ---XGO----- * JTRUE void N011 ( 18, 12) [003754] J--XGO-N--- \--* AND int N004 ( 8, 6) [002018] N--X---N-U- +--* NE int N002 ( 3, 3) [002016] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002028] N---GO-N-U- \--* GE int N005 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N009 ( 4, 3) [002062] n---GO----- \--* IND int N008 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB177 [584..585), preds={BB176} succs={BB178} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N001 ( 0, 0) [003755] ----------- * NOP void HERE Optimized: ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N012 ( 20, 14) [002079] ---XGO----- * JTRUE void N011 ( 18, 12) [003756] J--XGO-N--- \--* AND int N004 ( 8, 6) [002078] N--X---N-U- +--* NE int N002 ( 3, 3) [002076] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002088] N---GO-N-U- \--* GE int N005 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N009 ( 4, 3) [002122] n---GO----- \--* IND int N008 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB183 [598..599), preds={BB182} succs={BB184} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N001 ( 0, 0) [003757] ----------- * NOP void HERE Optimized: ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N012 ( 20, 14) [002139] ---XGO----- * JTRUE void N011 ( 18, 12) [003758] J--XGO-N--- \--* AND int N004 ( 8, 6) [002138] N--X---N-U- +--* NE int N002 ( 3, 3) [002136] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002148] N---GO-N-U- \--* GE int N005 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N009 ( 4, 3) [002182] n---GO----- \--* IND int N008 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB188 [5A9..5AA), preds={BB187} succs={BB189} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N001 ( 0, 0) [003759] ----------- * NOP void HERE HERE Optimized: ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N018 ( 24, 20) [000289] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003760] JA-XG--N--- \--* AND int N003 ( 6, 3) [000288] -------N--- +--* GE int $94d N001 ( 1, 1) [000283] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [000299] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003666] -A-XG------ +--* COMMA int N012 ( 9, 10) [003664] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N010 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N009 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N004 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N008 ( 4, 6) [000295] ----------- | | \--* LSH long $3e6 N006 ( 2, 3) [000292] ----------- | | +--* CAST long <- int $3e5 N005 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N007 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB201 [626..634), preds={BB200} succs={BB202} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N001 ( 0, 0) [003761] ----------- * NOP void HERE HERE Optimized: ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N026 ( 34, 33) [000548] -A-XG------ * JTRUE void $87a N025 ( 32, 31) [003762] JA-XG--N--- \--* AND int N013 ( 15, 14) [000547] NA-XG--N-U- +--* NE int N011 ( 10, 11) [003675] -A-XG------ | +--* COMMA int N009 ( 9, 10) [003673] -A-XG---R-- | | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | | | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- | \--* CNS_INT int 43 $d9 N024 ( 16, 16) [000560] N--XG--N-U- \--* NE int N022 ( 11, 13) [000558] ---XG------ +--* IND ushort N021 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N014 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N020 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N018 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N017 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N015 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N016 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N019 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N023 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB210 [694..6A3), preds={BB209} succs={BB211} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N001 ( 0, 0) [003763] ----------- * NOP void HERE HERE HERE HERE HERE HERE Optimized: ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N011 ( 19, 14) [000219] ----GO----- * JTRUE void $301 N010 ( 17, 12) [003764] J---GO-N--- \--* AND int N006 ( 10, 7) [000218] ----GO-N--- +--* EQ int N004 ( 5, 4) [000216] n---GO----- | +--* IND bool N003 ( 3, 4) [003148] -------N--- | | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000223] -------N--- \--* NE int $733 N007 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1), preds={BB248} succs={BB250} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N001 ( 0, 0) [003765] ----------- * NOP void HERE Optimized: ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N014 ( 21, 15) [000229] ---XGO----- * JTRUE void $301 N013 ( 19, 13) [003766] J--XGO-N--- \--* AND int N006 ( 9, 6) [000228] ----GO-N--- +--* NE int N004 ( 4, 3) [000226] n---GO----- | +--* IND int N003 ( 3, 4) [003150] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- | \--* CNS_INT int 0 $c0 N012 ( 9, 6) [000234] ---XG--N--- \--* LE int N010 ( 4, 3) [002539] ---XG------ +--* IND int N009 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N007 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N008 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N011 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2), preds={BB250} succs={BB252} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N001 ( 0, 0) [003767] ----------- * NOP void HERE HERE HERE HERE HERE HERE HERE HERE HERE HERE HERE HERE HERE HERE HERE HERE optimized 21 BBJ_COND cases, 0 BBJ_RETURN cases in 2 passes *************** Finishing PHASE Optimize bools Trees after Optimize bools ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 ( cond ) i BB67 [0067] 1 BB66 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 ( cond ) i BB70 [0070] 1 BB69 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 ( cond ) i BB75 [0075] 1 BB74 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..31E) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 ( cond ) i BB86 [0086] 1 BB85 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 1 BB107 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 5 BB103,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB126,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB162,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 3 BB248,BB250,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] n---GO----- | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N015 ( 16, 16) [002563] -A--------- * COMMA void $VN.Void N007 ( 8, 8) [002559] -A------R-- +--* ASG byref $VN.Void N006 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N005 ( 4, 5) [003711] -A--------- | \--* COMMA byref $246 N003 ( 3, 4) [003709] -A------R-- | +--* ASG byref $VN.Void N002 ( 1, 1) [003708] D------N--- | | +--* LCL_VAR byref V180 cse9 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 1, 1) [003710] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N014 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N013 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N012 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N010 ( 3, 4) [003689] -A------R-- +--* ASG int $VN.Void N009 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N008 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N011 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 N006 ( 7, 7) [001475] J---GO-N--- \--* NE int N004 ( 5, 4) [001473] n---GO----- +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 1, 3) [002606] -A--------- * COMMA void $580 N003 ( 1, 3) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 1, 1) [003712] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 1, 1) [003623] ----------- * COMMA void N001 ( 1, 1) [003692] ----------- +--* LCL_VAR int V179 cse8 u:1 $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N008 ( 15, 11) [001398] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003726] J------N--- \--* AND int N003 ( 6, 4) [001397] -------N--- +--* LE int $691 N001 ( 1, 1) [001395] ----------- | +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [001401] -------N--- \--* GE int $690 N004 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109), preds={BB23} succs={BB25} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N001 ( 0, 0) [003727] ----------- * NOP void ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N018 ( 24, 20) [001441] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003728] JA-XG--N--- \--* AND int N003 ( 6, 3) [001440] -------N--- +--* GE int $8b7 N001 ( 1, 1) [001435] ----------- | +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001451] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003627] -A-XG------ +--* COMMA int N012 ( 9, 10) [003625] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N010 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N009 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N004 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N008 ( 4, 6) [001447] ----------- | | \--* LSH long $3df N006 ( 2, 3) [001444] ----------- | | +--* CAST long <- int $3de N005 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N007 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB32 [150..15E), preds={BB31} succs={BB33} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N001 ( 0, 0) [003729] ----------- * NOP void ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 N003 ( 3, 3) [001470] N---G--N-U- \--* NE int N001 ( 1, 1) [003628] ----------- +--* LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N018 ( 24, 20) [001240] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003730] JA-XG--N--- \--* AND int N003 ( 6, 3) [001239] -------N--- +--* GE int $36c N001 ( 1, 1) [001234] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001250] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003647] -A-XG------ +--* COMMA int N012 ( 9, 10) [003645] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N010 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N009 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N004 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N008 ( 4, 6) [001246] ----------- | | \--* LSH long $3c9 N006 ( 2, 3) [001243] ----------- | | +--* CAST long <- int $3c8 N005 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N007 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N015 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB36 [183..18E), preds={BB35} succs={BB37} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N001 ( 0, 0) [003731] ----------- * NOP void ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N014 ( 14, 16) [001351] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001350] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003651] -A-XG------ +--* COMMA int N009 ( 9, 10) [003649] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003648] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001348] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001347] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003650] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003696] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N014 ( 14, 16) [001287] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001286] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003655] -A-XG------ +--* COMMA int N009 ( 9, 10) [003653] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003652] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001284] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001283] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003654] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 N003 ( 3, 4) [001339] N---G--N-U- \--* NE int N001 ( 1, 1) [003656] ----------- +--* LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A--GO--R-- * ASG int $301 N006 ( 3, 2) [001135] n---GO-N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ----GO----- \--* ADD int N002 ( 3, 2) [001132] n---GO----- +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A--GO--R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ----GO----- \--* SUB int N006 ( 6, 5) [001174] ----GO----- +--* ADD int N004 ( 4, 3) [001172] n---GO----- | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 21, 20) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 21, 20) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 4, 5) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 1, 1) [003713] ----------- ofs 0 | +--* LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000100] J---GO-N--- \--* EQ int N004 ( 5, 4) [000098] n---GO----- +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A--GO----- * ASG bool $301 N004 ( 5, 4) [001124] n---GO-N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A--GO----- * ASG int $301 N004 ( 4, 3) [000104] n---GO-N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N011 ( 15, 12) [000140] -A--GO----- * JTRUE void $301 N010 ( 13, 10) [000139] JA--GO-N--- \--* GT int N008 ( 11, 8) [003685] -A--GO----- +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N003 ( 7, 5) [000144] -A--G---R-- * ASG int $301 N002 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N001 ( 3, 2) [003686] ----------- \--* LCL_VAR int V178 cse7 u:1 ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N005 ( 5, 4) [000154] -A--G---R-- * ASG int $301 N004 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N003 ( 5, 4) [000152] ----G------ \--* SUB int N001 ( 3, 2) [003687] ----------- +--* LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 2) [003720] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N012 ( 20, 15) [000181] ---XG------ * JTRUE void $VN.Void N011 ( 18, 13) [003732] J--XG--N--- \--* AND int N007 ( 11, 8) [000946] ---XG--N--- +--* LE int N005 ( 6, 5) [000944] ---XG------ | +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | | \--* IND ref N003 ( 3, 4) [002656] -------N--- | | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- | \--* CNS_INT int 0 $c0 N010 ( 6, 4) [000180] -------N--- \--* EQ int $70a N008 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E), preds={BB78} succs={BB80} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N001 ( 0, 0) [003733] ----------- * NOP void ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A--GO--R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] n---GO----- \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N009 ( 4, 3) [001103] -A--GO--R-- * ASG int N008 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N007 ( 4, 3) [002670] ----GO-N--- \--* COMMA int N001 ( 0, 0) [002662] ----------- +--* NOP void N006 ( 4, 3) [002671] n---GO----- \--* IND int N005 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N004 ( 1, 1) [002667] -------N--- \--* ADD byref N002 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N003 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} ***** BB91 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB91 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ***** BB91 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB91 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ***** BB91 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB91 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..392), preds={BB91} succs={BB100} ***** BB95 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB95 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB95 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB95 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB95 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ***** BB95 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB95 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ***** BB95 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N011 ( 19, 14) [000186] ----GO----- * JTRUE void $301 N010 ( 17, 12) [003734] J---GO-N--- \--* AND int N006 ( 10, 7) [000185] ----GO-N--- +--* EQ int N004 ( 5, 4) [000183] n---GO----- | +--* IND bool N003 ( 3, 4) [002744] -------N--- | | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000929] -------N--- \--* NE int $733 N007 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4), preds={BB103} succs={BB105} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N001 ( 0, 0) [003735] ----------- * NOP void ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000934] J---GO-N--- \--* EQ int N004 ( 4, 3) [000932] n---GO----- +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N012 ( 22, 15) [001743] ---XGO----- * JTRUE void N011 ( 20, 13) [003736] J--XGO-N--- \--* AND int N004 ( 8, 6) [001742] N--X---N-U- +--* NE int N002 ( 3, 3) [001740] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- | \--* CNS_INT int 1 $c1 N010 ( 11, 6) [001752] N---GO-N-U- \--* GE int N005 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N009 ( 4, 3) [001786] n---GO----- \--* IND int N008 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N006 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB108 [3DC..3DD), preds={BB107} succs={BB109} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N001 ( 0, 0) [003737] ----------- * NOP void ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N023 ( 30, 29) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N022 ( 5, 4) [002775] ----GO-N--- \--* COMMA ushort N016 ( 0, 0) [002768] ----------- +--* NOP void N021 ( 5, 4) [002777] n---GO----- \--* IND ushort N020 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N019 ( 1, 1) [002772] -------N--- \--* ADD byref N017 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N018 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001780] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB91} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 1, 3) [002788] -A--------- * COMMA void $588 N003 ( 1, 3) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 1, 1) [003714] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N008 ( 15, 11) [000824] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003738] J------N--- \--* AND int N003 ( 6, 4) [000823] -------N--- +--* EQ int N001 ( 1, 1) [000821] ----------- | +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- | \--* CNS_INT int 35 $ea N006 ( 6, 4) [000921] -------N--- \--* EQ int N004 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB115 [40C..412), preds={BB114} succs={BB116} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N001 ( 0, 0) [003739] ----------- * NOP void ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N009 ( 9, 9) [000834] -A-XG------ * JTRUE void $c1a N008 ( 7, 7) [000833] JA-XG--N--- \--* NE int N006 ( 5, 4) [003680] -A-XG------ +--* COMMA int N004 ( 4, 3) [003678] -A-XG---R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003677] D------N--- | | +--* LCL_VAR int V177 cse6 d:1 $VN.Void N002 ( 4, 3) [000831] ---XG------ | | \--* IND ubyte N001 ( 1, 1) [000830] ----------- | | \--* LCL_VAR long V36 loc32 u:7 $904 N005 ( 1, 1) [003679] ----------- | \--* LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N003 ( 1, 3) [000855] -A--G---R-- * ASG int $c1a N002 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N001 ( 1, 1) [003681] ----------- \--* LCL_VAR int V177 cse6 u:1 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001805] N---GO-N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] n---GO----- \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] n---GO----- | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001823] n---GO----- | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001833] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N008 ( 15, 11) [000863] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003740] J------N--- \--* AND int N003 ( 6, 4) [000862] -------N--- +--* EQ int $70a N001 ( 1, 1) [000860] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000876] -------N--- \--* LE int $d03 N004 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB125 [435..43A), preds={BB124} succs={BB126} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N001 ( 0, 0) [003741] ----------- * NOP void ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N020 ( 30, 30) [000881] ---XGO----- * JTRUE void $VN.Void N019 ( 28, 28) [003742] J--XGO-N--- \--* AND int N015 ( 21, 23) [000900] N--XGO-N-U- +--* NE int N013 ( 16, 21) [000899] ---XGO----- | +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- | \--* LCL_VAR int V08 loc4 u:5 $b15 N018 ( 6, 4) [000880] -------N--- \--* LT int $d04 N016 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F), preds={BB126} succs={BB128} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N001 ( 0, 0) [003743] ----------- * NOP void ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N016 ( 21, 15) [001856] -A-XGO----- * JTRUE void N015 ( 19, 13) [003744] JA-XGO-N--- \--* AND int N008 ( 9, 7) [001855] NA-X---N-U- +--* NE int N006 ( 4, 4) [003718] -A-X------- | +--* COMMA int N004 ( 3, 3) [003716] -A-X----R-- | | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- | \--* CNS_INT int 1 $c1 N014 ( 9, 5) [001865] N---GO-N-U- \--* GE int N009 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N013 ( 4, 3) [001899] n---GO----- \--* IND int N012 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N010 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N011 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB130 [44F..450), preds={BB129} succs={BB131} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N001 ( 0, 0) [003745] ----------- * NOP void ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] n---GO----- | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001880] n---GO----- | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001893] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB126,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001911] N---GO-N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] n---GO----- \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] n---GO----- | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001928] n---GO----- | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001938] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N008 ( 15, 11) [000680] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003746] J------N--- \--* AND int N003 ( 6, 4) [000679] -------N--- +--* EQ int $70a N001 ( 1, 1) [000677] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000683] -------N--- \--* LE int $a93 N004 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB161 [52D..532), preds={BB160} succs={BB162} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N001 ( 0, 0) [003747] ----------- * NOP void ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N020 ( 30, 30) [000688] ---XGO----- * JTRUE void $VN.Void N019 ( 28, 28) [003748] J--XGO-N--- \--* AND int N015 ( 21, 23) [000707] N--XGO-N-U- +--* NE int N013 ( 16, 21) [000706] ---XGO----- | +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- | \--* LCL_VAR int V08 loc4 u:3 $2b5 N018 ( 6, 4) [000687] -------N--- \--* LT int $a94 N016 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547), preds={BB162} succs={BB164} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N001 ( 0, 0) [003749] ----------- * NOP void ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N012 ( 20, 14) [001959] ---XGO----- * JTRUE void N011 ( 18, 12) [003750] J--XGO-N--- \--* AND int N004 ( 8, 6) [001958] N--X---N-U- +--* NE int N002 ( 3, 3) [001956] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [001968] N---GO-N-U- \--* GE int N005 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N009 ( 4, 3) [002002] n---GO----- \--* IND int N008 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N006 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB166 [547..548), preds={BB165} succs={BB167} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N001 ( 0, 0) [003751] ----------- * NOP void ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] n---GO----- | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001983] n---GO----- | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001996] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB162,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N009 ( 18, 12) [000628] ---XG------ * JTRUE void $VN.Void N008 ( 16, 10) [003752] J--XG--N--- \--* AND int N003 ( 6, 3) [000627] -------N--- +--* GE int $abe N001 ( 1, 1) [000625] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 9, 6) [000632] ---XG--N--- \--* EQ int N005 ( 4, 3) [000630] ---XG------ +--* IND ubyte N004 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N006 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB174 [57C..584), preds={BB173} succs={BB175} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N001 ( 0, 0) [003753] ----------- * NOP void ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N012 ( 20, 14) [002019] ---XGO----- * JTRUE void N011 ( 18, 12) [003754] J--XGO-N--- \--* AND int N004 ( 8, 6) [002018] N--X---N-U- +--* NE int N002 ( 3, 3) [002016] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002028] N---GO-N-U- \--* GE int N005 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N009 ( 4, 3) [002062] n---GO----- \--* IND int N008 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB177 [584..585), preds={BB176} succs={BB178} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N001 ( 0, 0) [003755] ----------- * NOP void ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] n---GO----- | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002043] n---GO----- | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002056] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N012 ( 20, 14) [002079] ---XGO----- * JTRUE void N011 ( 18, 12) [003756] J--XGO-N--- \--* AND int N004 ( 8, 6) [002078] N--X---N-U- +--* NE int N002 ( 3, 3) [002076] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002088] N---GO-N-U- \--* GE int N005 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N009 ( 4, 3) [002122] n---GO----- \--* IND int N008 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB183 [598..599), preds={BB182} succs={BB184} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N001 ( 0, 0) [003757] ----------- * NOP void ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] n---GO----- | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002103] n---GO----- | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002116] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N012 ( 20, 14) [002139] ---XGO----- * JTRUE void N011 ( 18, 12) [003758] J--XGO-N--- \--* AND int N004 ( 8, 6) [002138] N--X---N-U- +--* NE int N002 ( 3, 3) [002136] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002148] N---GO-N-U- \--* GE int N005 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N009 ( 4, 3) [002182] n---GO----- \--* IND int N008 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB188 [5A9..5AA), preds={BB187} succs={BB189} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N001 ( 0, 0) [003759] ----------- * NOP void ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] n---GO----- | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002163] n---GO----- | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002176] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N003 ( 1, 3) [002225] -A--G---R-- * ASG ushort $bec N002 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N001 ( 1, 1) [003629] ----------- \--* LCL_VAR int V172 cse1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002194] N---GO-N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] n---GO----- \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] n---GO----- | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002212] n---GO----- | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002222] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N014 ( 14, 16) [000791] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000790] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003633] -A-XG------ +--* COMMA int N009 ( 9, 10) [003631] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003630] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000788] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000787] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003632] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec N003 ( 3, 3) [000801] N---G--N-U- \--* NE int N001 ( 1, 1) [003634] ----------- +--* LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N014 ( 14, 16) [000775] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000774] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003638] -A-XG------ +--* COMMA int N009 ( 9, 10) [003636] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003635] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000772] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000771] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003637] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N018 ( 24, 20) [000289] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003760] JA-XG--N--- \--* AND int N003 ( 6, 3) [000288] -------N--- +--* GE int $94d N001 ( 1, 1) [000283] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [000299] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003666] -A-XG------ +--* COMMA int N012 ( 9, 10) [003664] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N010 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N009 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N004 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N008 ( 4, 6) [000295] ----------- | | \--* LSH long $3e6 N006 ( 2, 3) [000292] ----------- | | +--* CAST long <- int $3e5 N005 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N007 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB201 [626..634), preds={BB200} succs={BB202} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N001 ( 0, 0) [003761] ----------- * NOP void ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N003 ( 1, 3) [002283] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N001 ( 1, 1) [003667] ----------- \--* LCL_VAR int V176 cse5 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002252] N---GO-N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] n---GO----- \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] n---GO----- | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002270] n---GO----- | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002280] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N014 ( 14, 16) [000575] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000574] NA-XG--N-U- \--* EQ int N011 ( 10, 11) [003671] -A-XG------ +--* COMMA int N009 ( 9, 10) [003669] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003668] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000572] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000571] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003670] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003703] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N026 ( 34, 33) [000548] -A-XG------ * JTRUE void $87a N025 ( 32, 31) [003762] JA-XG--N--- \--* AND int N013 ( 15, 14) [000547] NA-XG--N-U- +--* NE int N011 ( 10, 11) [003675] -A-XG------ | +--* COMMA int N009 ( 9, 10) [003673] -A-XG---R-- | | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | | | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- | \--* CNS_INT int 43 $d9 N024 ( 16, 16) [000560] N--XG--N-U- \--* NE int N022 ( 11, 13) [000558] ---XG------ +--* IND ushort N021 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N014 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N020 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N018 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N017 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N015 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N016 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N019 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N023 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB210 [694..6A3), preds={BB209} succs={BB211} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N001 ( 0, 0) [003763] ----------- * NOP void ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a N003 ( 3, 4) [000456] N---G--N-U- \--* NE int N001 ( 1, 1) [003676] ----------- +--* LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002310] N---GO-N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] n---GO----- \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] n---GO----- | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002327] n---GO----- | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002337] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A--GO--R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ----GO----- \--* SUB int N004 ( 4, 3) [000513] n---GO----- +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002357] N---GO-N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] n---GO----- \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] n---GO----- | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002374] n---GO----- | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002384] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N014 ( 14, 16) [000353] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000352] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003660] -A-XG------ +--* COMMA int N009 ( 9, 10) [003658] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003657] D------N--- | | +--* LCL_VAR int V175 cse4 d:1 $VN.Void N007 ( 9, 10) [000350] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000349] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003659] ----------- | \--* LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a N003 ( 3, 4) [000417] N---G--N-U- \--* NE int N001 ( 1, 1) [003661] ----------- +--* LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N003 ( 1, 3) [002435] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N001 ( 1, 1) [003662] ----------- \--* LCL_VAR int V175 cse4 u:1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002404] N---GO-N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] n---GO----- \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] n---GO----- | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002422] n---GO----- | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002432] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N003 ( 1, 3) [002481] -A--G---R-- * ASG ushort $c02 N002 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N001 ( 1, 1) [003639] ----------- \--* LCL_VAR int V173 cse2 u:1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002450] N---GO-N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] n---GO----- \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] n---GO----- | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002468] n---GO----- | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002478] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N014 ( 14, 16) [000389] -A-XG------ * JTRUE void $c02 N013 ( 12, 14) [000388] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003643] -A-XG------ +--* COMMA int N009 ( 9, 10) [003641] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003640] D------N--- | | +--* LCL_VAR int V173 cse2 d:1 $VN.Void N007 ( 9, 10) [000386] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000385] -------N--- | | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003642] ----------- | \--* LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002500] N---GO-N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] n---GO----- \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] n---GO----- | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002517] n---GO----- | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002527] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB215,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N011 ( 19, 14) [000219] ----GO----- * JTRUE void $301 N010 ( 17, 12) [003764] J---GO-N--- \--* AND int N006 ( 10, 7) [000218] ----GO-N--- +--* EQ int N004 ( 5, 4) [000216] n---GO----- | +--* IND bool N003 ( 3, 4) [003148] -------N--- | | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000223] -------N--- \--* NE int $733 N007 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1), preds={BB248} succs={BB250} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N001 ( 0, 0) [003765] ----------- * NOP void ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N014 ( 21, 15) [000229] ---XGO----- * JTRUE void $301 N013 ( 19, 13) [003766] J--XGO-N--- \--* AND int N006 ( 9, 6) [000228] ----GO-N--- +--* NE int N004 ( 4, 3) [000226] n---GO----- | +--* IND int N003 ( 3, 4) [003150] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- | \--* CNS_INT int 0 $c0 N012 ( 9, 6) [000234] ---XG--N--- \--* LE int N010 ( 4, 3) [002539] ---XG------ +--* IND int N009 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N007 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N008 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N011 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2), preds={BB250} succs={BB252} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N001 ( 0, 0) [003767] ----------- * NOP void ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB250,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE If conversion Conditionally executing BB86 and BB87 inside BB85 ------------ BB85 [34D..355) -> BB87 (cond), preds={BB83,BB84} succs={BB86,BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N004 ( 7, 6) [000994] ----------- * JTRUE void $VN.Void N003 ( 5, 4) [000993] J------N--- \--* GT int $71b N001 ( 1, 1) [000991] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- \--* LCL_VAR int V31 loc27 u:1 $71a ------------ BB86 [355..359) -> BB88 (always), preds={BB85} succs={BB88} ***** BB86 STMT00235 ( 0x355[E-] ... 0x357 ) N003 ( 7, 5) [001089] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N001 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ------------ BB87 [359..35A), preds={BB85} succs={BB88} ***** BB87 STMT00216 ( 0x359[E-] ... 0x359 ) N003 ( 5, 4) [000997] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000996] D------N--- +--* LCL_VAR int V67 tmp27 d:2 $VN.Void N001 ( 1, 1) [000995] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 After if conversion ------------ BB85 [34D..355) -> BB87 (always), preds={BB83,BB84} succs={BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N001 ( 0, 0) [003769] ----------- * NOP void ***** BB85 STMT00235 ( 0x355[E-] ... 0x357 ) N008 ( 14, 11) [001089] -A------R-- * ASG int $VN.Void N007 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N006 ( 10, 8) [003768] ----------- \--* SELECT int N003 ( 5, 4) [000993] J------N--- +--* GT int $71b N001 ( 1, 1) [000991] ----------- | +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- | \--* LCL_VAR int V31 loc27 u:1 $71a N004 ( 1, 1) [000995] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ***** BB85 STMT00216 ( 0x359[E-] ... 0x359 ) N001 ( 0, 0) [003770] ----------- * NOP void ------------ BB86 [355..359) -> BB88 (always), preds={} succs={BB88} ------------ BB87 [359..35A), preds={BB85} succs={BB88} Conditionally executing BB75 and BB76 inside BB74 ------------ BB74 [2D0..2D9) -> BB76 (cond), preds={BB72} succs={BB75,BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N011 ( 15, 12) [000140] -A--GO----- * JTRUE void $301 N010 ( 13, 10) [000139] JA--GO-N--- \--* GT int N008 ( 11, 8) [003685] -A--GO----- +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB75 [2D9..2DC) -> BB77 (always), preds={BB74} succs={BB77} ***** BB75 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N003 ( 5, 4) [001106] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N001 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ***** BB76 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N003 ( 7, 5) [000144] -A--G---R-- * ASG int $301 N002 ( 3, 2) [000143] D------N--- +--* LCL_VAR int V46 tmp6 d:2 $VN.Void N001 ( 3, 2) [003686] ----------- \--* LCL_VAR int V178 cse7 u:1 After if conversion ------------ BB74 [2D0..2D9) -> BB76 (always), preds={BB72} succs={BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N001 ( 0, 0) [003772] ----------- * NOP void ***** BB74 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N015 ( 22, 17) [001106] -A--GO--R-- * ASG int $VN.Void N014 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N013 ( 18, 14) [003771] -A--GO----- \--* SELECT int N010 ( 13, 10) [000139] JA--GO-N--- +--* GT int N008 ( 11, 8) [003685] -A--GO----- | +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N011 ( 3, 2) [003686] ----------- +--* LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB74 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N001 ( 0, 0) [003773] ----------- * NOP void ------------ BB75 [2D9..2DC) -> BB77 (always), preds={} succs={BB77} ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} Conditionally executing BB70 and BB71 inside BB69 ------------ BB69 [2B8..2BD) -> BB71 (cond), preds={BB67,BB68} succs={BB70,BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N004 ( 5, 5) [000122] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000121] J------N--- \--* GT int $6b9 N001 ( 1, 1) [000119] ----------- +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB70 [2BD..2C0) -> BB72 (always), preds={BB69} succs={BB72} ***** BB70 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N003 ( 5, 5) [001116] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N001 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ***** BB71 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N005 ( 7, 6) [000127] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000126] D------N--- +--* LCL_VAR int V45 tmp5 d:2 $VN.Void N003 ( 3, 3) [000125] ----------- \--* SUB int $6ba N001 ( 1, 1) [000123] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000124] ----------- \--* LCL_VAR int V07 loc3 u:2 (last use) $285 After if conversion ------------ BB69 [2B8..2BD) -> BB71 (always), preds={BB67,BB68} succs={BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N001 ( 0, 0) [003775] ----------- * NOP void ***** BB69 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N010 ( 12, 12) [001116] -A------R-- * ASG int $VN.Void N009 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N008 ( 8, 9) [003774] ----------- \--* SELECT int N003 ( 3, 3) [000121] J------N--- +--* GT int $6b9 N001 ( 1, 1) [000119] ----------- | +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N006 ( 3, 3) [000125] ----------- +--* SUB int $6ba N004 ( 1, 1) [000123] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- | \--* LCL_VAR int V07 loc3 u:2 (last use) $285 N007 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ***** BB69 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N001 ( 0, 0) [003776] ----------- * NOP void ------------ BB70 [2BD..2C0) -> BB72 (always), preds={} succs={BB72} ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} Conditionally executing BB67 and BB68 inside BB66 ------------ BB66 [2AE..2B2) -> BB68 (cond), preds={BB60,BB61,BB65} succs={BB67,BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N004 ( 5, 5) [000109] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000108] J------N--- \--* LT int $6b7 N001 ( 1, 1) [000106] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB67 [2B2..2B5) -> BB69 (always), preds={BB66} succs={BB69} ***** BB67 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N003 ( 5, 5) [001120] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N001 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ***** BB68 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N005 ( 7, 6) [000114] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000113] D------N--- +--* LCL_VAR int V44 tmp4 d:2 $VN.Void N003 ( 3, 3) [000112] ----------- \--* SUB int $6b8 N001 ( 1, 1) [000110] ----------- +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000111] ----------- \--* LCL_VAR int V06 loc2 u:2 (last use) $284 After if conversion ------------ BB66 [2AE..2B2) -> BB68 (always), preds={BB60,BB61,BB65} succs={BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N001 ( 0, 0) [003778] ----------- * NOP void ***** BB66 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N010 ( 12, 12) [001120] -A------R-- * ASG int $VN.Void N009 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N008 ( 8, 9) [003777] ----------- \--* SELECT int N003 ( 3, 3) [000108] J------N--- +--* LT int $6b7 N001 ( 1, 1) [000106] ----------- | +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N006 ( 3, 3) [000112] ----------- +--* SUB int $6b8 N004 ( 1, 1) [000110] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- | \--* LCL_VAR int V06 loc2 u:2 (last use) $284 N007 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ***** BB66 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N001 ( 0, 0) [003779] ----------- * NOP void ------------ BB67 [2B2..2B5) -> BB69 (always), preds={} succs={BB69} ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} *************** Finishing PHASE If conversion Trees after If conversion ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 (always) i BB67 [0067] 0 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 (always) i BB70 [0070] 0 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 (always) i BB75 [0075] 0 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..31E) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 (always) i BB86 [0086] 0 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 1 BB107 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 5 BB103,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB126,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB162,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 3 BB248,BB250,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] n---GO----- | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N015 ( 16, 16) [002563] -A--------- * COMMA void $VN.Void N007 ( 8, 8) [002559] -A------R-- +--* ASG byref $VN.Void N006 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N005 ( 4, 5) [003711] -A--------- | \--* COMMA byref $246 N003 ( 3, 4) [003709] -A------R-- | +--* ASG byref $VN.Void N002 ( 1, 1) [003708] D------N--- | | +--* LCL_VAR byref V180 cse9 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 1, 1) [003710] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N014 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N013 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N012 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N010 ( 3, 4) [003689] -A------R-- +--* ASG int $VN.Void N009 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N008 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N011 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 N006 ( 7, 7) [001475] J---GO-N--- \--* NE int N004 ( 5, 4) [001473] n---GO----- +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 1, 3) [002606] -A--------- * COMMA void $580 N003 ( 1, 3) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 1, 1) [003712] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 1, 1) [003623] ----------- * COMMA void N001 ( 1, 1) [003692] ----------- +--* LCL_VAR int V179 cse8 u:1 $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N008 ( 15, 11) [001398] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003726] J------N--- \--* AND int N003 ( 6, 4) [001397] -------N--- +--* LE int $691 N001 ( 1, 1) [001395] ----------- | +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [001401] -------N--- \--* GE int $690 N004 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..109), preds={BB23} succs={BB25} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N001 ( 0, 0) [003727] ----------- * NOP void ------------ BB25 [109..10E) -> BB29 (cond), preds={BB24} succs={BB26,BB29} ***** BB25 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB25} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB25,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB33} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N018 ( 24, 20) [001441] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003728] JA-XG--N--- \--* AND int N003 ( 6, 3) [001440] -------N--- +--* GE int $8b7 N001 ( 1, 1) [001435] ----------- | +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001451] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003627] -A-XG------ +--* COMMA int N012 ( 9, 10) [003625] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N010 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N009 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N004 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N008 ( 4, 6) [001447] ----------- | | \--* LSH long $3df N006 ( 2, 3) [001444] ----------- | | +--* CAST long <- int $3de N005 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N007 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB32 [150..15E), preds={BB31} succs={BB33} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N001 ( 0, 0) [003729] ----------- * NOP void ------------ BB33 [15E..170) -> BB31 (cond), preds={BB32} succs={BB34,BB31} ***** BB33 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB33 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB33 STMT00313 ( ??? ... 0x16E ) N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 N003 ( 3, 3) [001470] N---G--N-U- \--* NE int N001 ( 1, 1) [003628] ----------- +--* LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB33} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N018 ( 24, 20) [001240] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003730] JA-XG--N--- \--* AND int N003 ( 6, 3) [001239] -------N--- +--* GE int $36c N001 ( 1, 1) [001234] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001250] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003647] -A-XG------ +--* COMMA int N012 ( 9, 10) [003645] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N010 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N009 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N004 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N008 ( 4, 6) [001246] ----------- | | \--* LSH long $3c9 N006 ( 2, 3) [001243] ----------- | | +--* CAST long <- int $3c8 N005 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N007 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N015 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB36 [183..18E), preds={BB35} succs={BB37} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N001 ( 0, 0) [003731] ----------- * NOP void ------------ BB37 [18E..196) -> BB47 (always), preds={BB36} succs={BB47} ***** BB37 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N014 ( 14, 16) [001351] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001350] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003651] -A-XG------ +--* COMMA int N009 ( 9, 10) [003649] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003648] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001348] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001347] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003650] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003696] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N014 ( 14, 16) [001287] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001286] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003655] -A-XG------ +--* COMMA int N009 ( 9, 10) [003653] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003652] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001284] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001283] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003654] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 N003 ( 3, 4) [001339] N---G--N-U- \--* NE int N001 ( 1, 1) [003656] ----------- +--* LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB37,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A--GO--R-- * ASG int $301 N006 ( 3, 2) [001135] n---GO-N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ----GO----- \--* ADD int N002 ( 3, 2) [001132] n---GO----- +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A--GO--R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ----GO----- \--* SUB int N006 ( 6, 5) [001174] ----GO----- +--* ADD int N004 ( 4, 3) [001172] n---GO----- | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 21, 20) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 21, 20) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 4, 5) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 1, 1) [003713] ----------- ofs 0 | +--* LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000100] J---GO-N--- \--* EQ int N004 ( 5, 4) [000098] n---GO----- +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A--GO----- * ASG bool $301 N004 ( 5, 4) [001124] n---GO-N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A--GO----- * ASG int $301 N004 ( 4, 3) [000104] n---GO-N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2B2) -> BB68 (always), preds={BB60,BB61,BB65} succs={BB68} ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N001 ( 0, 0) [003778] ----------- * NOP void ***** BB66 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N010 ( 12, 12) [001120] -A------R-- * ASG int $VN.Void N009 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N008 ( 8, 9) [003777] ----------- \--* SELECT int N003 ( 3, 3) [000108] J------N--- +--* LT int $6b7 N001 ( 1, 1) [000106] ----------- | +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N006 ( 3, 3) [000112] ----------- +--* SUB int $6b8 N004 ( 1, 1) [000110] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- | \--* LCL_VAR int V06 loc2 u:2 (last use) $284 N007 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ***** BB66 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N001 ( 0, 0) [003779] ----------- * NOP void ------------ BB67 [2B2..2B5) -> BB69 (always), preds={} succs={BB69} ------------ BB68 [2B5..2B8), preds={BB66} succs={BB69} ------------ BB69 [2B8..2BD) -> BB71 (always), preds={BB67,BB68} succs={BB71} ***** BB69 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB69 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB69 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N001 ( 0, 0) [003775] ----------- * NOP void ***** BB69 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N010 ( 12, 12) [001116] -A------R-- * ASG int $VN.Void N009 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N008 ( 8, 9) [003774] ----------- \--* SELECT int N003 ( 3, 3) [000121] J------N--- +--* GT int $6b9 N001 ( 1, 1) [000119] ----------- | +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N006 ( 3, 3) [000125] ----------- +--* SUB int $6ba N004 ( 1, 1) [000123] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- | \--* LCL_VAR int V07 loc3 u:2 (last use) $285 N007 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ***** BB69 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N001 ( 0, 0) [003776] ----------- * NOP void ------------ BB70 [2BD..2C0) -> BB72 (always), preds={} succs={BB72} ------------ BB71 [2C0..2C3), preds={BB69} succs={BB72} ------------ BB72 [2C3..2C8) -> BB74 (cond), preds={BB70,BB71} succs={BB73,BB74} ***** BB72 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB72 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB72 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB72} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2D9) -> BB76 (always), preds={BB72} succs={BB76} ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N001 ( 0, 0) [003772] ----------- * NOP void ***** BB74 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N015 ( 22, 17) [001106] -A--GO--R-- * ASG int $VN.Void N014 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N013 ( 18, 14) [003771] -A--GO----- \--* SELECT int N010 ( 13, 10) [000139] JA--GO-N--- +--* GT int N008 ( 11, 8) [003685] -A--GO----- | +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N011 ( 3, 2) [003686] ----------- +--* LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB74 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N001 ( 0, 0) [003773] ----------- * NOP void ------------ BB75 [2D9..2DC) -> BB77 (always), preds={} succs={BB77} ------------ BB76 [2DC..2E2), preds={BB74} succs={BB77} ------------ BB77 [2E2..2EE), preds={BB75,BB76} succs={BB78} ***** BB77 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB77 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB77 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N005 ( 5, 4) [000154] -A--G---R-- * ASG int $301 N004 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N003 ( 5, 4) [000152] ----G------ \--* SUB int N001 ( 3, 2) [003687] ----------- +--* LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB77} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 2) [003720] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N012 ( 20, 15) [000181] ---XG------ * JTRUE void $VN.Void N011 ( 18, 13) [003732] J--XG--N--- \--* AND int N007 ( 11, 8) [000946] ---XG--N--- +--* LE int N005 ( 6, 5) [000944] ---XG------ | +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | | \--* IND ref N003 ( 3, 4) [002656] -------N--- | | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- | \--* CNS_INT int 0 $c0 N010 ( 6, 4) [000180] -------N--- \--* EQ int $70a N008 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..31E), preds={BB78} succs={BB80} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N001 ( 0, 0) [003733] ----------- * NOP void ------------ BB80 [31E..336) -> BB82 (cond), preds={BB79} succs={BB81,BB82} ***** BB80 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A--GO--R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] n---GO----- \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB80 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB80 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB80 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB80} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N009 ( 4, 3) [001103] -A--GO--R-- * ASG int N008 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N007 ( 4, 3) [002670] ----GO-N--- \--* COMMA int N001 ( 0, 0) [002662] ----------- +--* NOP void N006 ( 4, 3) [002671] n---GO----- \--* IND int N005 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N004 ( 1, 1) [002667] -------N--- \--* ADD byref N002 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N003 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB80,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..355) -> BB87 (always), preds={BB83,BB84} succs={BB87} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N001 ( 0, 0) [003769] ----------- * NOP void ***** BB85 STMT00235 ( 0x355[E-] ... 0x357 ) N008 ( 14, 11) [001089] -A------R-- * ASG int $VN.Void N007 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N006 ( 10, 8) [003768] ----------- \--* SELECT int N003 ( 5, 4) [000993] J------N--- +--* GT int $71b N001 ( 1, 1) [000991] ----------- | +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- | \--* LCL_VAR int V31 loc27 u:1 $71a N004 ( 1, 1) [000995] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ***** BB85 STMT00216 ( 0x359[E-] ... 0x359 ) N001 ( 0, 0) [003770] ----------- * NOP void ------------ BB86 [355..359) -> BB88 (always), preds={} succs={BB88} ------------ BB87 [359..35A), preds={BB85} succs={BB88} ------------ BB88 [35A..35E) -> BB103 (cond), preds={BB86,BB87} succs={BB89,BB103} ***** BB88 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB88 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB88 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB88,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} ***** BB91 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB91 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ***** BB91 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB91 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ***** BB91 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB91 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..392), preds={BB91} succs={BB100} ***** BB95 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB95 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB95 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB95 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB95 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ***** BB95 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB95 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ***** BB95 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB88,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N011 ( 19, 14) [000186] ----GO----- * JTRUE void $301 N010 ( 17, 12) [003734] J---GO-N--- \--* AND int N006 ( 10, 7) [000185] ----GO-N--- +--* EQ int N004 ( 5, 4) [000183] n---GO----- | +--* IND bool N003 ( 3, 4) [002744] -------N--- | | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000929] -------N--- \--* NE int $733 N007 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3D4), preds={BB103} succs={BB105} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N001 ( 0, 0) [003735] ----------- * NOP void ------------ BB105 [3D4..3DC) -> BB112 (cond), preds={BB104} succs={BB106,BB112} ***** BB105 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000934] J---GO-N--- \--* EQ int N004 ( 4, 3) [000932] n---GO----- +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB105} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N012 ( 22, 15) [001743] ---XGO----- * JTRUE void N011 ( 20, 13) [003736] J--XGO-N--- \--* AND int N004 ( 8, 6) [001742] N--X---N-U- +--* NE int N002 ( 3, 3) [001740] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- | \--* CNS_INT int 1 $c1 N010 ( 11, 6) [001752] N---GO-N-U- \--* GE int N005 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N009 ( 4, 3) [001786] n---GO----- \--* IND int N008 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N006 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB108 [3DC..3DD), preds={BB107} succs={BB109} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N001 ( 0, 0) [003737] ----------- * NOP void ------------ BB109 [3DC..3DD) -> BB112 (always), preds={BB108} succs={BB112} ***** BB109 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB109 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N023 ( 30, 29) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N022 ( 5, 4) [002775] ----GO-N--- \--* COMMA ushort N016 ( 0, 0) [002768] ----------- +--* NOP void N021 ( 5, 4) [002777] n---GO----- \--* IND ushort N020 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N019 ( 1, 1) [002772] -------N--- \--* ADD byref N017 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N018 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB109 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001780] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB110 [000..000) (throw), preds={BB91} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------ BB111 [3DC..3DD), preds={BB107} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB112 [3E8..401) -> BB245 (always), preds={BB103,BB105,BB106,BB109,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 1, 3) [002788] -A--------- * COMMA void $588 N003 ( 1, 3) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 1, 1) [003714] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N008 ( 15, 11) [000824] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003738] J------N--- \--* AND int N003 ( 6, 4) [000823] -------N--- +--* EQ int N001 ( 1, 1) [000821] ----------- | +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- | \--* CNS_INT int 35 $ea N006 ( 6, 4) [000921] -------N--- \--* EQ int N004 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB115 [40C..412), preds={BB114} succs={BB116} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N001 ( 0, 0) [003739] ----------- * NOP void ------------ BB116 [412..418) -> BB135 (cond), preds={BB115} succs={BB117,BB135} ***** BB116 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB116} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N009 ( 9, 9) [000834] -A-XG------ * JTRUE void $c1a N008 ( 7, 7) [000833] JA-XG--N--- \--* NE int N006 ( 5, 4) [003680] -A-XG------ +--* COMMA int N004 ( 4, 3) [003678] -A-XG---R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003677] D------N--- | | +--* LCL_VAR int V177 cse6 d:1 $VN.Void N002 ( 4, 3) [000831] ---XG------ | | \--* IND ubyte N001 ( 1, 1) [000830] ----------- | | \--* LCL_VAR long V36 loc32 u:7 $904 N005 ( 1, 1) [003679] ----------- | \--* LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N003 ( 1, 3) [000855] -A--G---R-- * ASG int $c1a N002 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N001 ( 1, 1) [003681] ----------- \--* LCL_VAR int V177 cse6 u:1 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001805] N---GO-N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] n---GO----- \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] n---GO----- | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001823] n---GO----- | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001833] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N008 ( 15, 11) [000863] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003740] J------N--- \--* AND int N003 ( 6, 4) [000862] -------N--- +--* EQ int $70a N001 ( 1, 1) [000860] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000876] -------N--- \--* LE int $d03 N004 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB125 [435..43A), preds={BB124} succs={BB126} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N001 ( 0, 0) [003741] ----------- * NOP void ------------ BB126 [43A..43F) -> BB134 (cond), preds={BB125} succs={BB127,BB134} ***** BB126 STMT00189 ( 0x43A[E-] ... 0x43D ) N020 ( 30, 30) [000881] ---XGO----- * JTRUE void $VN.Void N019 ( 28, 28) [003742] J--XGO-N--- \--* AND int N015 ( 21, 23) [000900] N--XGO-N-U- +--* NE int N013 ( 16, 21) [000899] ---XGO----- | +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- | \--* LCL_VAR int V08 loc4 u:5 $b15 N018 ( 6, 4) [000880] -------N--- \--* LT int $d04 N016 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..44F), preds={BB126} succs={BB128} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N001 ( 0, 0) [003743] ----------- * NOP void ------------ BB128 [44F..461) -> BB133 (cond), preds={BB127} succs={BB129,BB133} ***** BB128 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB128 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB128} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N016 ( 21, 15) [001856] -A-XGO----- * JTRUE void N015 ( 19, 13) [003744] JA-XGO-N--- \--* AND int N008 ( 9, 7) [001855] NA-X---N-U- +--* NE int N006 ( 4, 4) [003718] -A-X------- | +--* COMMA int N004 ( 3, 3) [003716] -A-X----R-- | | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- | \--* CNS_INT int 1 $c1 N014 ( 9, 5) [001865] N---GO-N-U- \--* GE int N009 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N013 ( 4, 3) [001899] n---GO----- \--* IND int N012 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N010 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N011 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB130 [44F..450), preds={BB129} succs={BB131} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N001 ( 0, 0) [003745] ----------- * NOP void ------------ BB131 [44F..450) -> BB133 (always), preds={BB130} succs={BB133} ***** BB131 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB131 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] n---GO----- | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001880] n---GO----- | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB131 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001893] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB128,BB131,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB126,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB116,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001911] N---GO-N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] n---GO----- \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] n---GO----- | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001928] n---GO----- | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001938] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N008 ( 15, 11) [000680] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003746] J------N--- \--* AND int N003 ( 6, 4) [000679] -------N--- +--* EQ int $70a N001 ( 1, 1) [000677] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000683] -------N--- \--* LE int $a93 N004 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB161 [52D..532), preds={BB160} succs={BB162} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N001 ( 0, 0) [003747] ----------- * NOP void ------------ BB162 [532..537) -> BB170 (cond), preds={BB161} succs={BB163,BB170} ***** BB162 STMT00152 ( 0x532[E-] ... 0x535 ) N020 ( 30, 30) [000688] ---XGO----- * JTRUE void $VN.Void N019 ( 28, 28) [003748] J--XGO-N--- \--* AND int N015 ( 21, 23) [000707] N--XGO-N-U- +--* NE int N013 ( 16, 21) [000706] ---XGO----- | +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- | \--* LCL_VAR int V08 loc4 u:3 $2b5 N018 ( 6, 4) [000687] -------N--- \--* LT int $a94 N016 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..547), preds={BB162} succs={BB164} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N001 ( 0, 0) [003749] ----------- * NOP void ------------ BB164 [547..559) -> BB169 (cond), preds={BB163} succs={BB165,BB169} ***** BB164 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB164 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB164} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N012 ( 20, 14) [001959] ---XGO----- * JTRUE void N011 ( 18, 12) [003750] J--XGO-N--- \--* AND int N004 ( 8, 6) [001958] N--X---N-U- +--* NE int N002 ( 3, 3) [001956] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [001968] N---GO-N-U- \--* GE int N005 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N009 ( 4, 3) [002002] n---GO----- \--* IND int N008 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N006 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB166 [547..548), preds={BB165} succs={BB167} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N001 ( 0, 0) [003751] ----------- * NOP void ------------ BB167 [547..548) -> BB169 (always), preds={BB166} succs={BB169} ***** BB167 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB167 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] n---GO----- | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001983] n---GO----- | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB167 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001996] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB164,BB167,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB162,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB175 (cond), preds={BB171} succs={BB173,BB175} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N009 ( 18, 12) [000628] ---XG------ * JTRUE void $VN.Void N008 ( 16, 10) [003752] J--XG--N--- \--* AND int N003 ( 6, 3) [000627] -------N--- +--* GE int $abe N001 ( 1, 1) [000625] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 9, 6) [000632] ---XG--N--- \--* EQ int N005 ( 4, 3) [000630] ---XG------ +--* IND ubyte N004 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N006 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB174 [57C..584), preds={BB173} succs={BB175} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N001 ( 0, 0) [003753] ----------- * NOP void ------------ BB175 [584..598) -> BB180 (cond), preds={BB172,BB174} succs={BB176,BB180} ***** BB175 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB175 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB175} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N012 ( 20, 14) [002019] ---XGO----- * JTRUE void N011 ( 18, 12) [003754] J--XGO-N--- \--* AND int N004 ( 8, 6) [002018] N--X---N-U- +--* NE int N002 ( 3, 3) [002016] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002028] N---GO-N-U- \--* GE int N005 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N009 ( 4, 3) [002062] n---GO----- \--* IND int N008 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB177 [584..585), preds={BB176} succs={BB178} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N001 ( 0, 0) [003755] ----------- * NOP void ------------ BB178 [584..585) -> BB180 (always), preds={BB177} succs={BB180} ***** BB178 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB178 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] n---GO----- | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002043] n---GO----- | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB178 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002056] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB175,BB178,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N012 ( 20, 14) [002079] ---XGO----- * JTRUE void N011 ( 18, 12) [003756] J--XGO-N--- \--* AND int N004 ( 8, 6) [002078] N--X---N-U- +--* NE int N002 ( 3, 3) [002076] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002088] N---GO-N-U- \--* GE int N005 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N009 ( 4, 3) [002122] n---GO----- \--* IND int N008 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB183 [598..599), preds={BB182} succs={BB184} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N001 ( 0, 0) [003757] ----------- * NOP void ------------ BB184 [598..599) -> BB245 (always), preds={BB183} succs={BB245} ***** BB184 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB184 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] n---GO----- | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002103] n---GO----- | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB184 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002116] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N012 ( 20, 14) [002139] ---XGO----- * JTRUE void N011 ( 18, 12) [003758] J--XGO-N--- \--* AND int N004 ( 8, 6) [002138] N--X---N-U- +--* NE int N002 ( 3, 3) [002136] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002148] N---GO-N-U- \--* GE int N005 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N009 ( 4, 3) [002182] n---GO----- \--* IND int N008 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB188 [5A9..5AA), preds={BB187} succs={BB189} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N001 ( 0, 0) [003759] ----------- * NOP void ------------ BB189 [5A9..5AA) -> BB245 (always), preds={BB188} succs={BB245} ***** BB189 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB189 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] n---GO----- | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002163] n---GO----- | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB189 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002176] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N003 ( 1, 3) [002225] -A--G---R-- * ASG ushort $bec N002 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N001 ( 1, 1) [003629] ----------- \--* LCL_VAR int V172 cse1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002194] N---GO-N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] n---GO----- \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] n---GO----- | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002212] n---GO----- | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002222] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N014 ( 14, 16) [000791] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000790] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003633] -A-XG------ +--* COMMA int N009 ( 9, 10) [003631] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003630] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000788] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000787] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003632] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec N003 ( 3, 3) [000801] N---G--N-U- \--* NE int N001 ( 1, 1) [003634] ----------- +--* LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N014 ( 14, 16) [000775] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000774] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003638] -A-XG------ +--* COMMA int N009 ( 9, 10) [003636] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003635] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000772] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000771] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003637] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N018 ( 24, 20) [000289] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003760] JA-XG--N--- \--* AND int N003 ( 6, 3) [000288] -------N--- +--* GE int $94d N001 ( 1, 1) [000283] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [000299] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003666] -A-XG------ +--* COMMA int N012 ( 9, 10) [003664] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N010 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N009 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N004 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N008 ( 4, 6) [000295] ----------- | | \--* LSH long $3e6 N006 ( 2, 3) [000292] ----------- | | +--* CAST long <- int $3e5 N005 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N007 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB201 [626..634), preds={BB200} succs={BB202} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N001 ( 0, 0) [003761] ----------- * NOP void ------------ BB202 [000..64D) -> BB204 (cond), preds={BB201} succs={BB203,BB204} ***** BB202 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB202 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB202 STMT00458 ( ??? ... ??? ) N003 ( 1, 3) [002283] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N001 ( 1, 1) [003667] ----------- \--* LCL_VAR int V176 cse5 ***** BB202 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB202 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002252] N---GO-N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] n---GO----- \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] n---GO----- | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002270] n---GO----- | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002280] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB202} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N014 ( 14, 16) [000575] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000574] NA-XG--N-U- \--* EQ int N011 ( 10, 11) [003671] -A-XG------ +--* COMMA int N009 ( 9, 10) [003669] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003668] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000572] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000571] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003670] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003703] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N026 ( 34, 33) [000548] -A-XG------ * JTRUE void $87a N025 ( 32, 31) [003762] JA-XG--N--- \--* AND int N013 ( 15, 14) [000547] NA-XG--N-U- +--* NE int N011 ( 10, 11) [003675] -A-XG------ | +--* COMMA int N009 ( 9, 10) [003673] -A-XG---R-- | | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | | | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- | \--* CNS_INT int 43 $d9 N024 ( 16, 16) [000560] N--XG--N-U- \--* NE int N022 ( 11, 13) [000558] ---XG------ +--* IND ushort N021 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N014 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N020 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N018 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N017 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N015 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N016 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N019 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N023 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB210 [694..6A3), preds={BB209} succs={BB211} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N001 ( 0, 0) [003763] ----------- * NOP void ------------ BB211 [6A3..6A8) -> BB219 (always), preds={BB210} succs={BB219} ***** BB211 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a N003 ( 3, 4) [000456] N---G--N-U- \--* NE int N001 ( 1, 1) [003676] ----------- +--* LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002310] N---GO-N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] n---GO----- \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] n---GO----- | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002327] n---GO----- | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002337] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB211,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A--GO--R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ----GO----- \--* SUB int N004 ( 4, 3) [000513] n---GO----- +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002357] N---GO-N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] n---GO----- \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] n---GO----- | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002374] n---GO----- | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002384] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N014 ( 14, 16) [000353] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000352] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003660] -A-XG------ +--* COMMA int N009 ( 9, 10) [003658] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003657] D------N--- | | +--* LCL_VAR int V175 cse4 d:1 $VN.Void N007 ( 9, 10) [000350] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000349] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003659] ----------- | \--* LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a N003 ( 3, 4) [000417] N---G--N-U- \--* NE int N001 ( 1, 1) [003661] ----------- +--* LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N003 ( 1, 3) [002435] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N001 ( 1, 1) [003662] ----------- \--* LCL_VAR int V175 cse4 u:1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002404] N---GO-N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] n---GO----- \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] n---GO----- | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002422] n---GO----- | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002432] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N003 ( 1, 3) [002481] -A--G---R-- * ASG ushort $c02 N002 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N001 ( 1, 1) [003639] ----------- \--* LCL_VAR int V173 cse2 u:1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002450] N---GO-N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] n---GO----- \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] n---GO----- | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002468] n---GO----- | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002478] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N014 ( 14, 16) [000389] -A-XG------ * JTRUE void $c02 N013 ( 12, 14) [000388] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003643] -A-XG------ +--* COMMA int N009 ( 9, 10) [003641] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003640] D------N--- | | +--* LCL_VAR int V173 cse2 d:1 $VN.Void N007 ( 9, 10) [000386] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000385] -------N--- | | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003642] ----------- | \--* LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002500] N---GO-N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] n---GO----- \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] n---GO----- | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002517] n---GO----- | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002527] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3), preds={BB215,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N011 ( 19, 14) [000219] ----GO----- * JTRUE void $301 N010 ( 17, 12) [003764] J---GO-N--- \--* AND int N006 ( 10, 7) [000218] ----GO-N--- +--* EQ int N004 ( 5, 4) [000216] n---GO----- | +--* IND bool N003 ( 3, 4) [003148] -------N--- | | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000223] -------N--- \--* NE int $733 N007 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E1), preds={BB248} succs={BB250} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N001 ( 0, 0) [003765] ----------- * NOP void ------------ BB250 [7E1..7E9) -> BB253 (cond), preds={BB249} succs={BB251,BB253} ***** BB250 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N014 ( 21, 15) [000229] ---XGO----- * JTRUE void $301 N013 ( 19, 13) [003766] J--XGO-N--- \--* AND int N006 ( 9, 6) [000228] ----GO-N--- +--* NE int N004 ( 4, 3) [000226] n---GO----- | +--* IND int N003 ( 3, 4) [003150] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- | \--* CNS_INT int 0 $c0 N012 ( 9, 6) [000234] ---XG--N--- \--* LE int N010 ( 4, 3) [002539] ---XG------ +--* IND int N009 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N007 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N008 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N011 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7F2), preds={BB250} succs={BB252} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N001 ( 0, 0) [003767] ----------- * NOP void ------------ BB252 [7F2..7FF), preds={BB251} succs={BB253} ***** BB252 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB250,BB252} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Optimize layout *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..109) i bwd BB25 [0024] 1 BB24 8 1 [109..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB25 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB25,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB33 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..15E) i bwd BB33 [0033] 1 BB32 64 1 [15E..170)-> BB31 ( cond ) i bwd bwd-src BB34 [0034] 1 BB33 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..18E) i bwd BB37 [0037] 1 BB36 8 1 [18E..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB37,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2B2)-> BB68 (always) i BB67 [0067] 0 0.50 [2B2..2B5)-> BB69 (always) i BB68 [0068] 1 BB66 0.50 [2B5..2B8) i BB69 [0069] 2 BB67,BB68 1 [2B8..2BD)-> BB71 (always) i BB70 [0070] 0 0.50 [2BD..2C0)-> BB72 (always) i BB71 [0071] 1 BB69 0.50 [2C0..2C3) i BB72 [0072] 2 BB70,BB71 1 [2C3..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB72 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB72 0.50 [2D0..2D9)-> BB76 (always) i BB75 [0075] 0 0.50 [2D9..2DC)-> BB77 (always) i BB76 [0076] 1 BB74 0.50 [2DC..2E2) i BB77 [0077] 2 BB75,BB76 0.50 [2E2..2EE) i BB78 [0078] 2 BB73,BB77 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..31E) i idxlen BB80 [0080] 1 BB79 0.50 [31E..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB80 0.50 [336..33D) i idxlen BB82 [0082] 2 BB80,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..355)-> BB87 (always) i BB86 [0086] 0 0.50 [355..359)-> BB88 (always) i BB87 [0087] 1 BB85 0.50 [359..35A) i BB88 [0088] 2 BB86,BB87 0.50 [35A..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB88,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB88,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3D4) i BB105 [0098] 1 BB104 0.50 [3D4..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB105 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD) i BB109 [0254] 1 BB108 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 1 BB107 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 5 BB103,BB105,BB106,BB109,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..412) i bwd BB116 [0104] 1 BB115 2 3 [412..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB116 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43A) i bwd BB126 [0111] 1 BB125 8 3 [43A..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB126 8 3 [43F..44F) i bwd BB128 [0113] 1 BB127 8 3 [44F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB128 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450) i bwd BB131 [0269] 1 BB130 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB128,BB131,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB126,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB116,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..532) i bwd BB162 [0139] 1 BB161 2 3 [532..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB162 2 3 [537..547) i bwd BB164 [0141] 1 BB163 2 3 [547..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB164 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548) i bwd BB167 [0283] 1 BB166 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB164,BB167,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB162,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB175 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 1 BB173 2 3 [57C..584) i bwd BB175 [0147] 2 BB172,BB174 2 3 [584..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB175 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585) i bwd BB178 [0292] 1 BB177 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB175,BB178,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599) i bwd BB184 [0301] 1 BB183 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA) i bwd BB189 [0310] 1 BB188 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [626..634) i bwd BB202 [0159] 1 BB201 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB202 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB202 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A3) i bwd BB211 [0167] 1 BB210 2 3 [6A3..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB211,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB184,BB185,BB186,BB189,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E1) i BB250 [0195] 1 BB249 0.50 [7E1..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB250 0.50 [7E9..7F2) i BB252 [0197] 1 BB251 0.50 [7F2..7FF) i hascall gcsafe BB253 [0198] 3 BB248,BB250,BB252 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB24 and BB25: *************** In fgDebugCheckBBlist Compacting blocks BB32 and BB33: *************** In fgDebugCheckBBlist Compacting blocks BB36 and BB37: *************** In fgDebugCheckBBlist fgRemoveBlock BB67, unreachable=true Removing unreachable BB67 Compacting blocks BB68 and BB69: *************** In fgDebugCheckBBlist fgRemoveBlock BB70, unreachable=true Removing unreachable BB70 Compacting blocks BB71 and BB72: *************** In fgDebugCheckBBlist fgRemoveBlock BB75, unreachable=true Removing unreachable BB75 Compacting blocks BB76 and BB77: *************** In fgDebugCheckBBlist Compacting blocks BB79 and BB80: *************** In fgDebugCheckBBlist fgRemoveBlock BB86, unreachable=true Removing unreachable BB86 Compacting blocks BB87 and BB88: *************** In fgDebugCheckBBlist Compacting blocks BB104 and BB105: *************** In fgDebugCheckBBlist Compacting blocks BB108 and BB109: *************** In fgDebugCheckBBlist Compacting blocks BB115 and BB116: *************** In fgDebugCheckBBlist Compacting blocks BB125 and BB126: *************** In fgDebugCheckBBlist Compacting blocks BB127 and BB128: *************** In fgDebugCheckBBlist Compacting blocks BB130 and BB131: *************** In fgDebugCheckBBlist Compacting blocks BB161 and BB162: *************** In fgDebugCheckBBlist Compacting blocks BB163 and BB164: *************** In fgDebugCheckBBlist Compacting blocks BB166 and BB167: *************** In fgDebugCheckBBlist Compacting blocks BB174 and BB175: Second block has multiple incoming edges Setting edge weights for BB172 -> BB174 to [0 .. 3.402823e+38] *************** In fgDebugCheckBBlist Compacting blocks BB177 and BB178: *************** In fgDebugCheckBBlist Compacting blocks BB183 and BB184: *************** In fgDebugCheckBBlist Compacting blocks BB188 and BB189: *************** In fgDebugCheckBBlist Compacting blocks BB201 and BB202: *************** In fgDebugCheckBBlist Compacting blocks BB210 and BB211: *************** In fgDebugCheckBBlist Compacting blocks BB249 and BB250: *************** In fgDebugCheckBBlist Compacting blocks BB251 and BB252: *************** In fgDebugCheckBBlist Compacting blocks BB66 and BB68: *************** In fgDebugCheckBBlist Compacting blocks BB66 and BB71: *************** In fgDebugCheckBBlist Compacting blocks BB74 and BB76: *************** In fgDebugCheckBBlist Compacting blocks BB85 and BB87: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB66 0.50 [2D0..2EE) i BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 1 BB107 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB66 0.50 [2D0..2EE) i BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i idxlen nullcheck BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 1 BB107 0.50 [3DC..3DD) i hascall gcsafe BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401)-> BB245 (always) i BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Decided to straighten unconditional branch at block BB108 branch to BB112 since it is succeeded by a rarely run block Relocated hot block BB112 Relocated block [BB112..BB112] inserted after BB108 Changed an unconditional jump from BB108 to the next block BB112 into a BBJ_NONE block Block BB111 ended with a BBJ_NONE, Changed to an unconditional jump to BB112 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB66 0.50 [2D0..2EE) i BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401)-> BB245 (always) i BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3) i hascall gcsafe bwd BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- Decided to straighten unconditional branch at block BB112 branch to BB245 since it is succeeded by a rarely run block Relocated hot blocks (BB245 .. BB253) Relocated blocks [BB245..BB253] inserted after BB112 Changed an unconditional jump from BB112 to the next block BB245 into a BBJ_NONE block Block BB244 ended with a BBJ_NONE, Changed to an unconditional jump to BB245 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB66 0.50 [2D0..2EE) i BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- Decided to relocate block(s) after block BB253 since they are rarely run block(s) Relocated rarely run block BB110 Relocated block [BB110..BB110] inserted after BB244 at the end of method After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB66 0.50 [2D0..2EE) i BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB66 0.50 [2D0..2EE) i BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout Trees after Optimize layout ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd BB28 [0027] 1 BB26 8 1 [11E..121) i bwd BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd BB51 [0051] 1 BB50 2 0 [233..235) i bwd BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i BB64 [0064] 1 BB63 0.50 [2A0..2A7) i BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i BB74 [0074] 1 BB66 0.50 [2D0..2EE) i BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i BB84 [0084] 1 BB82 0.50 [34B..34D) i BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd BB120 [0108] 1 BB118 8 3 [424..42C) i bwd BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd BB154 [0134] 1 BB150 2 3 [513..51B) i bwd BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd BB222 [0176] 1 BB221 2 3 [707..70B) i bwd BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [000000] ----------- this in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x400000000046ac80 ftn $42 ***** BB01 STMT00001 ( 0x006[E-] ... ??? ) N003 ( 1, 3) [000004] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000003] D------N--- +--* LCL_VAR int V11 loc7 d:1 $VN.Void N001 ( 1, 2) [000002] ----------- \--* CNS_INT int 0 $c0 ***** BB01 STMT00320 ( INL01 @ 0x000[E-] ... ??? ) <- INLRT @ 0x009[E-] N005 ( 3, 4) [001500] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001499] D------N--- +--* LCL_VAR byref V76 tmp36 d:1 $VN.Void N003 ( 3, 4) [002548] -----O----- \--* ADD byref $240 N001 ( 1, 1) [002546] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- \--* CNS_INT long 16 $200 ***** BB01 STMT00003 ( 0x009[E-] ... ??? ) N015 ( 13, 15) [000009] -A-XGO--R-- * ASG long N014 ( 1, 1) [000008] D------N--- +--* LCL_VAR long V17 loc13 d:1 $VN.Void N013 ( 13, 15) [002554] -A-XGO----- \--* COMMA long N011 ( 12, 14) [002551] -A-XGO--R-- +--* ASG long N010 ( 1, 1) [002550] D------N--- | +--* LCL_VAR long V167 tmp127 d:1 $VN.Void N009 ( 12, 14) [001507] ---XGO----- | \--* COMMA byref N006 ( 9, 12) [001504] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 2) [001497] ----------- | | +--* CNS_INT int 0 $c0 N005 ( 4, 3) [001503] ---XG------ | | \--* IND int N004 ( 3, 4) [002556] -------N--- | | \--* ADD byref $241 N002 ( 1, 1) [001502] ----------- | | +--* LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- | | \--* CNS_INT long 8 $201 N008 ( 3, 2) [001505] n---GO----- | \--* IND byref N007 ( 1, 1) [001501] ----------- | \--* LCL_VAR byref V76 tmp36 u:1 (last use) $240 N012 ( 1, 1) [002552] ----------- \--* LCL_VAR long V167 tmp127 u:1 ***** BB01 STMT00005 ( ??? ... 0x015 ) N015 ( 16, 16) [002563] -A--------- * COMMA void $VN.Void N007 ( 8, 8) [002559] -A------R-- +--* ASG byref $VN.Void N006 ( 3, 2) [002557] D------N--- | +--* LCL_VAR byref V147 tmp107 d:1 $VN.Void N005 ( 4, 5) [003711] -A--------- | \--* COMMA byref $246 N003 ( 3, 4) [003709] -A------R-- | +--* ASG byref $VN.Void N002 ( 1, 1) [003708] D------N--- | | +--* LCL_VAR byref V180 cse9 d:1 $VN.Void N001 ( 3, 4) [002558] ----------- | | \--* LCL_FLD byref V02 arg2 u:1[+0] $246 N004 ( 1, 1) [003710] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N014 ( 8, 8) [002562] -A------R-- \--* ASG int $VN.Void N013 ( 3, 2) [002560] D------N--- +--* LCL_VAR int V148 tmp108 d:1 $VN.Void N012 ( 4, 5) [003691] -A--------- \--* COMMA int $342 N010 ( 3, 4) [003689] -A------R-- +--* ASG int $VN.Void N009 ( 1, 1) [003688] D------N--- | +--* LCL_VAR int V179 cse8 d:1 $VN.Void N008 ( 3, 4) [002561] ----------- | \--* LCL_FLD int V02 arg2 u:1[+8] $342 N011 ( 1, 1) [003690] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ***** BB01 STMT00004 ( 0x011[E-] ... 0x015 ) N005 ( 8, 8) [000015] ---XG------ * JTRUE void N004 ( 6, 6) [000014] J--XG--N--- \--* EQ int N002 ( 4, 3) [000012] ---XG------ +--* IND ubyte N001 ( 1, 1) [000011] ----------- | \--* LCL_VAR long V17 loc13 u:1 (last use) N003 ( 1, 2) [000013] ----------- \--* CNS_INT int 0 $c0 ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00315 ( ??? ... 0x01D ) N007 ( 14, 10) [002570] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002566] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002564] D------N--- | +--* LCL_VAR byref V155 tmp115 d:1 $VN.Void N001 ( 3, 2) [002565] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002569] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002567] D------N--- +--* LCL_VAR int V156 tmp116 d:1 $VN.Void N004 ( 3, 2) [002568] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB02 STMT00314 ( ??? ... 0x01D ) N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 N006 ( 7, 7) [001475] J---GO-N--- \--* NE int N004 ( 5, 4) [001473] n---GO----- +--* IND bool N003 ( 3, 4) [002572] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001472] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001474] ----------- \--* CNS_INT int 0 $c0 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ***** BB03 STMT00318 ( ??? ... 0x020 ) N007 ( 14, 10) [002579] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002575] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002573] D------N--- | +--* LCL_VAR byref V149 tmp109 d:4 $VN.Void N001 ( 3, 2) [002574] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002578] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002576] D------N--- +--* LCL_VAR int V150 tmp110 d:4 $VN.Void N004 ( 3, 2) [002577] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB03 STMT00319 ( ??? ... ??? ) N003 ( 5, 5) [001494] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001493] D------N--- +--* LCL_VAR int V43 tmp3 d:4 $VN.Void N001 ( 1, 2) [001489] ----------- \--* CNS_INT int 0 $c0 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ***** BB04 STMT00316 ( ??? ... 0x023 ) N007 ( 14, 10) [002586] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002582] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002580] D------N--- | +--* LCL_VAR byref V149 tmp109 d:3 $VN.Void N001 ( 3, 2) [002581] ----------- | \--* LCL_VAR byref V155 tmp115 u:1 (last use) $246 N006 ( 7, 5) [002585] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002583] D------N--- +--* LCL_VAR int V150 tmp110 d:3 $VN.Void N004 ( 3, 2) [002584] ----------- \--* LCL_VAR int V156 tmp116 u:1 (last use) $342 ***** BB04 STMT00317 ( ??? ... ??? ) N003 ( 5, 5) [001487] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001486] D------N--- +--* LCL_VAR int V43 tmp3 d:3 $VN.Void N001 ( 1, 2) [001482] ----------- \--* CNS_INT int 1 $c1 ------------ BB05 [025..026), preds={BB01} succs={BB06} ***** BB05 STMT00006 ( ??? ... 0x025 ) N007 ( 14, 10) [002593] -A--------- * COMMA void $VN.Void N003 ( 7, 5) [002589] -A------R-- +--* ASG byref $VN.Void N002 ( 3, 2) [002587] D------N--- | +--* LCL_VAR byref V149 tmp109 d:2 $VN.Void N001 ( 3, 2) [002588] ----------- | \--* LCL_VAR byref V147 tmp107 u:1 (last use) $246 N006 ( 7, 5) [002592] -A------R-- \--* ASG int $VN.Void N005 ( 3, 2) [002590] D------N--- +--* LCL_VAR int V150 tmp110 d:2 $VN.Void N004 ( 3, 2) [002591] ----------- \--* LCL_VAR int V148 tmp108 u:1 (last use) $342 ***** BB05 STMT00007 ( ??? ... ??? ) N003 ( 5, 5) [000026] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000025] D------N--- +--* LCL_VAR int V43 tmp3 d:2 $VN.Void N001 ( 1, 2) [000021] ----------- \--* CNS_INT int 2 $c2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ***** BB06 STMT00587 ( ??? ... ??? ) N006 ( 0, 0) [003414] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003412] D------N--- +--* LCL_VAR int V150 tmp110 d:1 $VN.Void N004 ( 0, 0) [003413] ----------- \--* PHI int $342 N001 ( 0, 0) [003618] ----------- pred BB03 +--* PHI_ARG int V150 tmp110 u:4 $342 N002 ( 0, 0) [003615] ----------- pred BB04 +--* PHI_ARG int V150 tmp110 u:3 $342 N003 ( 0, 0) [003612] ----------- pred BB05 \--* PHI_ARG int V150 tmp110 u:2 $342 ***** BB06 STMT00586 ( ??? ... ??? ) N006 ( 0, 0) [003411] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003409] D------N--- +--* LCL_VAR int V43 tmp3 d:1 $VN.Void N004 ( 0, 0) [003410] ----------- \--* PHI int $281 N001 ( 0, 0) [003619] ----------- pred BB03 +--* PHI_ARG int V43 tmp3 u:4 $c0 N002 ( 0, 0) [003616] ----------- pred BB04 +--* PHI_ARG int V43 tmp3 u:3 $c1 N003 ( 0, 0) [003613] ----------- pred BB05 \--* PHI_ARG int V43 tmp3 u:2 $c2 ***** BB06 STMT00585 ( ??? ... ??? ) N006 ( 0, 0) [003408] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003406] D------N--- +--* LCL_VAR byref V149 tmp109 d:1 $VN.Void N004 ( 0, 0) [003407] ----------- \--* PHI byref $246 N001 ( 0, 0) [003620] ----------- pred BB03 +--* PHI_ARG byref V149 tmp109 u:4 $246 N002 ( 0, 0) [003617] ----------- pred BB04 +--* PHI_ARG byref V149 tmp109 u:3 $246 N003 ( 0, 0) [003614] ----------- pred BB05 \--* PHI_ARG byref V149 tmp109 u:2 $246 ***** BB06 STMT00008 ( ??? ... 0x02B ) N008 ( 25, 19) [000034] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [000033] D------N--- +--* LCL_VAR int V15 loc11 d:1 $VN.Void N006 ( 25, 19) [000030] --CXG------ \--* CALL r2r_ind int $2c1 N003 ( 6, 4) [002595] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $141 N001 ( 3, 2) [002596] ----------- ofs 0 | +--* LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- ofs 8 | \--* LCL_VAR int V150 tmp110 u:1 (last use) $342 N004 ( 3, 2) [000029] ----------- arg2 in x2 +--* LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x40000000005401e8 ftn $43 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ***** BB07 STMT00575 ( ??? ... ??? ) N005 ( 0, 0) [003378] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003376] D------N--- +--* LCL_VAR int V11 loc7 d:2 $VN.Void N003 ( 0, 0) [003377] ----------- \--* PHI int $282 N001 ( 0, 0) [003571] ----------- pred BB62 +--* PHI_ARG int V11 loc7 u:3 N002 ( 0, 0) [003415] ----------- pred BB06 \--* PHI_ARG int V11 loc7 u:1 $c0 ***** BB07 STMT00503 ( ??? ... ??? ) N005 ( 0, 0) [003162] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003160] D------N--- +--* LCL_VAR int V15 loc11 d:2 $VN.Void N003 ( 0, 0) [003161] ----------- \--* PHI int $283 N001 ( 0, 0) [003572] ----------- pred BB62 +--* PHI_ARG int V15 loc11 u:3 N002 ( 0, 0) [003416] ----------- pred BB06 \--* PHI_ARG int V15 loc11 u:1 $2c1 ***** BB07 STMT00009 ( 0x02D[E-] ... 0x02E ) N003 ( 1, 3) [000037] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000036] D------N--- +--* LCL_VAR int V04 loc0 d:1 $VN.Void N001 ( 1, 2) [000035] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00010 ( 0x02F[E-] ... 0x030 ) N003 ( 1, 3) [000040] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000039] D------N--- +--* LCL_VAR int V05 loc1 d:1 $VN.Void N001 ( 1, 2) [000038] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00011 ( 0x031[E-] ... 0x036 ) N003 ( 1, 4) [000043] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000042] D------N--- +--* LCL_VAR int V06 loc2 d:1 $VN.Void N001 ( 1, 4) [000041] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ***** BB07 STMT00012 ( 0x037[E-] ... 0x038 ) N003 ( 1, 3) [000046] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000045] D------N--- +--* LCL_VAR int V07 loc3 d:1 $VN.Void N001 ( 1, 2) [000044] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00013 ( 0x039[E-] ... 0x03A ) N003 ( 1, 3) [000049] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000048] D------N--- +--* LCL_VAR int V09 loc5 d:1 $VN.Void N001 ( 1, 2) [002598] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00014 ( 0x03C[E-] ... 0x03D ) N003 ( 1, 3) [000052] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000051] D------N--- +--* LCL_VAR int V10 loc6 d:1 $VN.Void N001 ( 1, 2) [000050] ----------- \--* CNS_INT int -1 $c4 ***** BB07 STMT00015 ( 0x03F[E-] ... 0x040 ) N003 ( 1, 3) [000055] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000054] D------N--- +--* LCL_VAR int V12 loc8 d:1 $VN.Void N001 ( 1, 2) [002599] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00016 ( 0x042[E-] ... 0x043 ) N003 ( 1, 3) [000058] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000057] D------N--- +--* LCL_VAR int V13 loc9 d:1 $VN.Void N001 ( 1, 2) [000056] ----------- \--* CNS_INT int 0 $c0 ***** BB07 STMT00017 ( 0x045[E-] ... 0x047 ) N003 ( 1, 3) [000061] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000060] D------N--- +--* LCL_VAR int V16 loc12 d:1 $VN.Void N001 ( 1, 1) [000059] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB07 STMT00321 ( 0x049[E-] ... ??? ) N005 ( 1, 3) [002606] -A--------- * COMMA void $580 N003 ( 1, 3) [002602] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002600] D------N--- | +--* LCL_VAR byref V157 tmp117 d:1 $VN.Void N001 ( 1, 1) [003712] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002605] ----------- \--* NOP void $580 ***** BB07 STMT00019 ( 0x049[E-] ... ??? ) N003 ( 1, 3) [000068] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000067] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 1) [001512] ----------- \--* LCL_VAR byref V157 tmp117 u:1 $246 ***** BB07 STMT00020 ( 0x051[E-] ... 0x054 ) N007 ( 2, 4) [000072] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000071] D------N--- +--* LCL_VAR long V22 loc18 d:1 $VN.Void N005 ( 2, 4) [002611] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002608] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002607] D------N--- | +--* LCL_VAR long V168 tmp128 d:1 $VN.Void N001 ( 1, 1) [000069] ----------- | \--* LCL_VAR byref V157 tmp117 u:1 (last use) $246 N004 ( 1, 1) [002609] ----------- \--* LCL_VAR long V168 tmp128 u:1 (last use) $3c4 ***** BB07 STMT00588 ( ??? ... ??? ) N003 ( 1, 1) [003623] ----------- * COMMA void N001 ( 1, 1) [003692] ----------- +--* LCL_VAR int V179 cse8 u:1 $342 N002 ( 0, 0) [003622] ----------- \--* NOP void ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ***** BB08 STMT00266 ( 0x05B[E-] ... 0x05F ) N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001228] N------N-U- \--* GT int N001 ( 1, 1) [001226] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- \--* CNS_INT int 69 $d2 ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} ***** BB09 STMT00289 ( 0x061[E-] ... 0x066 ) N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001363] ----------- \--* ADD int N001 ( 1, 1) [001361] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- \--* CNS_INT int -34 $d6 ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} ***** BB10 STMT00290 ( 0x083[E-] ... 0x088 ) N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [001367] ----------- \--* ADD int N001 ( 1, 1) [001365] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- \--* CNS_INT int -44 $d7 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ***** BB11 STMT00291 ( 0x0A1[E-] ... 0x0A5 ) N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001371] J------N--- \--* EQ int N001 ( 1, 1) [001369] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- \--* CNS_INT int 69 $d2 ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ***** BB13 STMT00267 ( 0x0AF[E-] ... 0x0B3 ) N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001232] J------N--- \--* EQ int N001 ( 1, 1) [001230] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- \--* CNS_INT int 92 $d3 ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ***** BB14 STMT00272 ( 0x0B8[E-] ... 0x0BC ) N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001259] J------N--- \--* EQ int N001 ( 1, 1) [001257] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- \--* CNS_INT int 101 $d4 ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ***** BB15 STMT00287 ( 0x0C1[E-] ... 0x0C8 ) N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001354] J------N--- \--* NE int N001 ( 1, 1) [001352] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ***** BB16 STMT00288 ( 0x137[E-] ... 0x13B ) N005 ( 3, 4) [001360] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001359] D------N--- +--* LCL_VAR int V13 loc9 d:5 $VN.Void N003 ( 3, 4) [001358] ----------- \--* ADD int $376 N001 ( 1, 1) [001356] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- \--* CNS_INT int 3 $c3 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} ***** BB17 STMT00307 ( 0x0CF[E-] ... 0x0D2 ) N005 ( 3, 4) [001434] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001433] D------N--- +--* LCL_VAR int V04 loc0 d:3 $VN.Void N003 ( 3, 4) [001432] ----------- \--* ADD int $68f N001 ( 1, 1) [001430] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- \--* CNS_INT int 1 $c1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} ***** BB18 STMT00292 ( 0x0D8[E-] ... 0x0DE ) N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [001375] N------N-U- \--* NE int $68e N001 ( 1, 1) [001373] ----------- +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- \--* CNS_INT int 0x7FFFFFFF $c9 ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} ***** BB19 STMT00295 ( 0x0E0[E-] ... 0x0E1 ) N003 ( 1, 3) [001387] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001386] D------N--- +--* LCL_VAR int V06 loc2 d:5 $VN.Void N001 ( 1, 1) [001385] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ***** BB20 STMT00581 ( ??? ... ??? ) N005 ( 0, 0) [003396] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003394] D------N--- +--* LCL_VAR int V06 loc2 d:4 $VN.Void N003 ( 0, 0) [003395] ----------- \--* PHI int $28c N001 ( 0, 0) [003611] ----------- pred BB19 +--* PHI_ARG int V06 loc2 u:5 $28a N002 ( 0, 0) [003607] ----------- pred BB18 \--* PHI_ARG int V06 loc2 u:2 $284 ***** BB20 STMT00293 ( 0x0E2[E-] ... 0x0E5 ) N005 ( 3, 4) [001381] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001380] D------N--- +--* LCL_VAR int V04 loc0 d:4 $VN.Void N003 ( 3, 4) [001379] ----------- \--* ADD int $68f N001 ( 1, 1) [001377] ----------- +--* LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- \--* CNS_INT int 1 $c1 ***** BB20 STMT00294 ( 0x0E6[E-] ... 0x0E7 ) N003 ( 1, 3) [001384] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001383] D------N--- +--* LCL_VAR int V07 loc3 d:4 $VN.Void N001 ( 1, 1) [001382] ----------- \--* LCL_VAR int V04 loc0 u:4 $68f ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} ***** BB21 STMT00296 ( 0x0ED[E-] ... 0x0EF ) N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001390] J------N--- \--* GE int $690 N001 ( 1, 1) [001388] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- \--* CNS_INT int 0 $c0 ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ***** BB22 STMT00297 ( 0x0F4[E-] ... 0x0F5 ) N003 ( 1, 3) [001394] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001393] D------N--- +--* LCL_VAR int V05 loc1 d:5 $VN.Void N001 ( 1, 1) [001392] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} ***** BB23 STMT00298 ( 0x0FB[E-] ... 0x0FD ) N008 ( 15, 11) [001398] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003726] J------N--- \--* AND int N003 ( 6, 4) [001397] -------N--- +--* LE int $691 N001 ( 1, 1) [001395] ----------- | +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [001401] -------N--- \--* GE int $690 N004 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] ----------- \--* CNS_INT int 0 $c0 ------------ BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} ***** BB24 STMT00299 ( 0x102[E-] ... 0x104 ) N001 ( 0, 0) [003727] ----------- * NOP void ***** BB24 STMT00300 ( 0x109[E-] ... 0x10C ) N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001405] J------N--- \--* LT int $692 N001 ( 1, 1) [001403] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- \--* CNS_INT int 0 $c0 ------------ BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} ***** BB26 STMT00303 ( 0x10E[E-] ... 0x111 ) N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001415] N------N-U- \--* NE int $693 N001 ( 1, 1) [001413] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ***** BB27 STMT00305 ( 0x113[E-] ... 0x117 ) N005 ( 3, 4) [001424] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001423] D------N--- +--* LCL_VAR int V11 loc7 d:5 $VN.Void N003 ( 3, 4) [001422] ----------- \--* ADD int $694 N001 ( 1, 1) [001420] ----------- +--* LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- \--* CNS_INT int 1 $c1 ------------ BB28 [11E..121), preds={BB26} succs={BB29} ***** BB28 STMT00304 ( 0x11E[E-] ... 0x11F ) N003 ( 1, 3) [001419] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001418] D------N--- +--* LCL_VAR int V12 loc8 d:6 $VN.Void N001 ( 1, 2) [002612] ----------- \--* CNS_INT int 1 $c1 ------------ BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} ***** BB29 STMT00577 ( ??? ... ??? ) N005 ( 0, 0) [003384] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003382] D------N--- +--* LCL_VAR bool V12 loc8 d:5 $VN.Void N003 ( 0, 0) [003383] ----------- \--* PHI bool $4c3 N001 ( 0, 0) [003604] ----------- pred BB28 +--* PHI_ARG bool V12 loc8 u:6 $c1 N002 ( 0, 0) [003600] ----------- pred BB25 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB29 STMT00301 ( 0x121[E-] ... 0x122 ) N003 ( 1, 3) [001409] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001408] D------N--- +--* LCL_VAR int V10 loc6 d:3 $VN.Void N001 ( 1, 1) [001407] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ***** BB29 STMT00302 ( 0x124[E-] ... 0x125 ) N003 ( 1, 3) [001412] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001411] D------N--- +--* LCL_VAR int V11 loc7 d:4 $VN.Void N001 ( 1, 2) [001410] ----------- \--* CNS_INT int 1 $c1 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} ***** BB30 STMT00306 ( 0x12C[E-] ... 0x130 ) N005 ( 3, 4) [001429] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001428] D------N--- +--* LCL_VAR int V13 loc9 d:6 $VN.Void N003 ( 3, 4) [001427] ----------- \--* ADD int $695 N001 ( 1, 1) [001425] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- \--* CNS_INT int 2 $c2 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB32} succs={BB32,BB47} ***** BB31 STMT00570 ( ??? ... ??? ) N005 ( 0, 0) [003363] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003361] D------N--- +--* LCL_VAR int V16 loc12 d:21 $VN.Void N003 ( 0, 0) [003362] ----------- \--* PHI int $2b1 N001 ( 0, 0) [003596] ----------- pred BB33 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003594] ----------- pred BB09 \--* PHI_ARG int V16 loc12 u:17 $361 ***** BB31 STMT00309 ( 0x142[E-] ... ??? ) N018 ( 24, 20) [001441] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003728] JA-XG--N--- \--* AND int N003 ( 6, 3) [001440] -------N--- +--* GE int $8b7 N001 ( 1, 1) [001435] ----------- | +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001451] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003627] -A-XG------ +--* COMMA int N012 ( 9, 10) [003625] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003624] D------N--- | | +--* LCL_VAR int V171 cse0 d:1 $VN.Void N010 ( 9, 10) [001449] ---XG------ | | \--* IND ushort N009 ( 6, 8) [001448] -------N--- | | \--* ADD long $3e0 N004 ( 1, 1) [001442] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N008 ( 4, 6) [001447] ----------- | | \--* LSH long $3df N006 ( 2, 3) [001444] ----------- | | +--* CAST long <- int $3de N005 ( 1, 1) [001443] ----------- | | | \--* LCL_VAR int V16 loc12 u:21 $2b1 N007 ( 1, 2) [001446] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003626] ----------- | \--* LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] ----------- \--* CNS_INT int 0 $c0 ------------ BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} ***** BB32 STMT00310 ( 0x150[E-] ... 0x159 ) N001 ( 0, 0) [003729] ----------- * NOP void ***** BB32 STMT00312 ( 0x15E[E-] ... 0x165 ) N003 ( 1, 3) [001461] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001460] D------N--- +--* LCL_VAR int V74 tmp34 d:1 $VN.Void N001 ( 1, 1) [001454] ----------- \--* LCL_VAR int V16 loc12 u:21 $2b1 ***** BB32 STMT00311 ( 0x15E[E-] ... ??? ) N005 ( 3, 4) [001459] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001458] D------N--- +--* LCL_VAR int V16 loc12 d:22 $VN.Void N003 ( 3, 4) [001457] ----------- \--* ADD int $8bc N001 ( 1, 1) [001455] ----------- +--* LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- \--* CNS_INT int 1 $c1 ***** BB32 STMT00313 ( ??? ... 0x16E ) N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 N003 ( 3, 3) [001470] N---G--N-U- \--* NE int N001 ( 1, 1) [003628] ----------- +--* LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- \--* LCL_VAR int V18 loc14 u:5 ------------ BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ***** BB35 STMT00269 ( 0x175[E-] ... ??? ) N018 ( 24, 20) [001240] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003730] JA-XG--N--- \--* AND int N003 ( 6, 3) [001239] -------N--- +--* GE int $36c N001 ( 1, 1) [001234] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001250] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003647] -A-XG------ +--* COMMA int N012 ( 9, 10) [003645] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003644] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N010 ( 9, 10) [001248] ---XG------ | | \--* IND ushort N009 ( 6, 8) [001247] -------N--- | | \--* ADD long $3ca N004 ( 1, 1) [001241] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N008 ( 4, 6) [001246] ----------- | | \--* LSH long $3c9 N006 ( 2, 3) [001243] ----------- | | +--* CAST long <- int $3c8 N005 ( 1, 1) [001242] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N007 ( 1, 2) [001245] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003646] ----------- | \--* LCL_VAR int V174 cse3 N015 ( 1, 2) [001249] ----------- \--* CNS_INT int 0 $c0 ------------ BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} ***** BB36 STMT00270 ( 0x183[E-] ... 0x18C ) N001 ( 0, 0) [003731] ----------- * NOP void ***** BB36 STMT00271 ( 0x18E[E-] ... 0x192 ) N005 ( 3, 4) [001256] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001255] D------N--- +--* LCL_VAR int V16 loc12 d:20 $VN.Void N003 ( 3, 4) [001254] ----------- \--* ADD int $371 N001 ( 1, 1) [001252] ----------- +--* LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- \--* CNS_INT int 1 $c1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ***** BB38 STMT00274 ( 0x196[E-] ... ??? ) N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001266] J------N--- \--* GE int $36c N001 ( 1, 1) [001261] ----------- +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ***** BB39 STMT00286 ( 0x1A1[E-] ... 0x1AC ) N014 ( 14, 16) [001351] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001350] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003651] -A-XG------ +--* COMMA int N009 ( 9, 10) [003649] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003648] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001348] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001347] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001341] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001346] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001343] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001342] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001345] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003650] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- \--* CNS_INT int 48 $d8 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ***** BB40 STMT00276 ( 0x1AE[E-] ... ??? ) N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001275] J------N--- \--* GE int $681 N003 ( 3, 4) [001270] ----------- +--* ADD int $371 N001 ( 1, 1) [001268] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003696] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ***** BB41 STMT00277 ( 0x1BB[E-] ... 0x1C6 ) N014 ( 14, 16) [001287] -A-XG------ * JTRUE void $311 N013 ( 12, 14) [001286] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003655] -A-XG------ +--* COMMA int N009 ( 9, 10) [003653] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003652] D------N--- | | +--* LCL_VAR int V174 cse3 $VN.Void N007 ( 9, 10) [001284] ---XG------ | | \--* IND ushort N006 ( 6, 8) [001283] -------N--- | | \--* ADD long $3ca N001 ( 1, 1) [001277] ----------- | | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001282] ----------- | | \--* LSH long $3c9 N003 ( 2, 3) [001279] ----------- | | +--* CAST long <- int $3c8 N002 ( 1, 1) [001278] ----------- | | | \--* LCL_VAR int V16 loc12 u:17 $361 N004 ( 1, 2) [001281] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003654] ----------- | \--* LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- \--* CNS_INT int 43 $d9 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ***** BB42 STMT00285 ( 0x1C8[E-] ... 0x1D3 ) N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 N003 ( 3, 4) [001339] N---G--N-U- \--* NE int N001 ( 1, 1) [003656] ----------- +--* LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- \--* CNS_INT int 45 $da ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ***** BB43 STMT00278 ( 0x1D5[E-] ... 0x1E2 ) N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 N011 ( 13, 16) [001299] N--XG--N-U- \--* NE int N009 ( 11, 13) [001297] ---XG------ +--* IND ushort N008 ( 8, 11) [001296] -------N--- | \--* ADD long $3cd N001 ( 1, 1) [001288] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N007 ( 6, 9) [001295] ----------- | \--* LSH long $3cc N005 ( 4, 6) [001292] ----------- | +--* CAST long <- int $3cb N004 ( 3, 4) [001291] ----------- | | \--* ADD int $371 N002 ( 1, 1) [001289] ----------- | | +--* LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [001294] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [001298] ----------- \--* CNS_INT int 48 $d8 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ***** BB44 STMT00584 ( ??? ... ??? ) N005 ( 0, 0) [003405] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003403] D------N--- +--* LCL_VAR int V16 loc12 d:18 $VN.Void N003 ( 0, 0) [003404] ----------- \--* PHI int $2b2 N001 ( 0, 0) [003591] ----------- pred BB43 +--* PHI_ARG int V16 loc12 u:17 $361 N002 ( 0, 0) [003588] ----------- pred BB45 \--* PHI_ARG int V16 loc12 u:19 ***** BB44 STMT00279 ( 0x1E4[E-] ... 0x1E9 ) N005 ( 3, 4) [001305] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001304] D------N--- +--* LCL_VAR int V73 tmp33 d:1 $VN.Void N003 ( 3, 4) [001303] ----------- \--* ADD int $942 N001 ( 1, 1) [001301] ----------- +--* LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- \--* CNS_INT int 1 $c1 ***** BB44 STMT00280 ( ??? ... ??? ) N003 ( 1, 3) [001309] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001308] D------N--- +--* LCL_VAR int V16 loc12 d:19 $VN.Void N001 ( 1, 1) [001307] ----------- \--* LCL_VAR int V73 tmp33 u:1 $942 ***** BB44 STMT00282 ( ??? ... ??? ) N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001314] J------N--- \--* GE int $943 N001 ( 1, 1) [001306] ----------- +--* LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ***** BB45 STMT00284 ( 0x1F4[E-] ... 0x1FF ) N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 N009 ( 11, 13) [001328] J--XG--N--- \--* EQ int N007 ( 9, 10) [001326] ---XG------ +--* IND ushort N006 ( 6, 8) [001325] -------N--- | \--* ADD long $3e3 N001 ( 1, 1) [001319] ----------- | +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001324] ----------- | \--* LSH long $3e2 N003 ( 2, 3) [001321] ----------- | +--* CAST long <- int $3e1 N002 ( 1, 1) [001320] ----------- | | \--* LCL_VAR int V16 loc12 u:19 $942 N004 ( 1, 2) [001323] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [001327] ----------- \--* CNS_INT int 48 $d8 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} ***** BB46 STMT00283 ( 0x201[E-] ... 0x202 ) N003 ( 1, 3) [001318] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001317] D------N--- +--* LCL_VAR int V09 loc5 d:5 $VN.Void N001 ( 1, 2) [002613] ----------- \--* CNS_INT int 1 $c1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46} succs={BB48,BB50} ***** BB47 STMT00583 ( ??? ... ??? ) N006 ( 0, 0) [003402] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003400] D------N--- +--* LCL_VAR bool V09 loc5 d:2 $VN.Void N004 ( 0, 0) [003401] ----------- \--* PHI bool $4c1 N001 ( 0, 0) [003589] ----------- pred BB40 +--* PHI_ARG bool V09 loc5 u:2 N002 ( 0, 0) [003578] ----------- pred BB46 +--* PHI_ARG bool V09 loc5 u:5 N003 ( 0, 0) [003417] ----------- pred BB07 \--* PHI_ARG bool V09 loc5 u:1 $c0 ***** BB47 STMT00582 ( ??? ... ??? ) N006 ( 0, 0) [003399] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003397] D------N--- +--* LCL_VAR int V06 loc2 d:2 $VN.Void N004 ( 0, 0) [003398] ----------- \--* PHI int $284 N001 ( 0, 0) [003608] ----------- pred BB20 +--* PHI_ARG int V06 loc2 u:4 N002 ( 0, 0) [003579] ----------- pred BB46 +--* PHI_ARG int V06 loc2 u:2 N003 ( 0, 0) [003418] ----------- pred BB07 \--* PHI_ARG int V06 loc2 u:1 $c9 ***** BB47 STMT00580 ( ??? ... ??? ) N006 ( 0, 0) [003393] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003391] D------N--- +--* LCL_VAR int V07 loc3 d:2 $VN.Void N004 ( 0, 0) [003392] ----------- \--* PHI int $285 N001 ( 0, 0) [003609] ----------- pred BB20 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [003580] ----------- pred BB46 +--* PHI_ARG int V07 loc3 u:2 N003 ( 0, 0) [003419] ----------- pred BB07 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB47 STMT00579 ( ??? ... ??? ) N006 ( 0, 0) [003390] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003388] D------N--- +--* LCL_VAR int V05 loc1 d:2 $VN.Void N004 ( 0, 0) [003389] ----------- \--* PHI int $286 N001 ( 0, 0) [003606] ----------- pred BB22 +--* PHI_ARG int V05 loc1 u:5 N002 ( 0, 0) [003581] ----------- pred BB46 +--* PHI_ARG int V05 loc1 u:2 N003 ( 0, 0) [003420] ----------- pred BB07 \--* PHI_ARG int V05 loc1 u:1 $c4 ***** BB47 STMT00578 ( ??? ... ??? ) N006 ( 0, 0) [003387] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003385] D------N--- +--* LCL_VAR bool V12 loc8 d:2 $VN.Void N004 ( 0, 0) [003386] ----------- \--* PHI bool $4c2 N001 ( 0, 0) [003601] ----------- pred BB29 +--* PHI_ARG bool V12 loc8 u:5 N002 ( 0, 0) [003582] ----------- pred BB46 +--* PHI_ARG bool V12 loc8 u:2 N003 ( 0, 0) [003421] ----------- pred BB07 \--* PHI_ARG bool V12 loc8 u:1 $c0 ***** BB47 STMT00576 ( ??? ... ??? ) N006 ( 0, 0) [003381] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003379] D------N--- +--* LCL_VAR int V10 loc6 d:2 $VN.Void N004 ( 0, 0) [003380] ----------- \--* PHI int $287 N001 ( 0, 0) [003602] ----------- pred BB29 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [003583] ----------- pred BB46 +--* PHI_ARG int V10 loc6 u:2 N003 ( 0, 0) [003422] ----------- pred BB07 \--* PHI_ARG int V10 loc6 u:1 $c4 ***** BB47 STMT00574 ( ??? ... ??? ) N007 ( 0, 0) [003375] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003373] D------N--- +--* LCL_VAR int V11 loc7 d:3 $VN.Void N005 ( 0, 0) [003374] ----------- \--* PHI int $288 N001 ( 0, 0) [003605] ----------- pred BB27 +--* PHI_ARG int V11 loc7 u:5 N002 ( 0, 0) [003603] ----------- pred BB29 +--* PHI_ARG int V11 loc7 u:4 N003 ( 0, 0) [003584] ----------- pred BB46 +--* PHI_ARG int V11 loc7 u:3 N004 ( 0, 0) [003423] ----------- pred BB07 \--* PHI_ARG int V11 loc7 u:2 $282 ***** BB47 STMT00573 ( ??? ... ??? ) N007 ( 0, 0) [003372] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003370] D------N--- +--* LCL_VAR int V13 loc9 d:2 $VN.Void N005 ( 0, 0) [003371] ----------- \--* PHI int $289 N001 ( 0, 0) [003598] ----------- pred BB30 +--* PHI_ARG int V13 loc9 u:6 N002 ( 0, 0) [003593] ----------- pred BB16 +--* PHI_ARG int V13 loc9 u:5 N003 ( 0, 0) [003585] ----------- pred BB46 +--* PHI_ARG int V13 loc9 u:2 N004 ( 0, 0) [003424] ----------- pred BB07 \--* PHI_ARG int V13 loc9 u:1 $c0 ***** BB47 STMT00572 ( ??? ... ??? ) N007 ( 0, 0) [003369] -A------R-- * ASG int $VN.Void N006 ( 0, 0) [003367] D------N--- +--* LCL_VAR int V04 loc0 d:2 $VN.Void N005 ( 0, 0) [003368] ----------- \--* PHI int $28a N001 ( 0, 0) [003610] ----------- pred BB20 +--* PHI_ARG int V04 loc0 u:4 N002 ( 0, 0) [003599] ----------- pred BB17 +--* PHI_ARG int V04 loc0 u:3 N003 ( 0, 0) [003586] ----------- pred BB46 +--* PHI_ARG int V04 loc0 u:2 N004 ( 0, 0) [003425] ----------- pred BB07 \--* PHI_ARG int V04 loc0 u:1 $c0 ***** BB47 STMT00571 ( ??? ... ??? ) N009 ( 0, 0) [003366] -A------R-- * ASG int $VN.Void N008 ( 0, 0) [003364] D------N--- +--* LCL_VAR int V16 loc12 d:2 $VN.Void N007 ( 0, 0) [003365] ----------- \--* PHI int $28b N001 ( 0, 0) [003597] ----------- pred BB34 +--* PHI_ARG int V16 loc12 u:22 N002 ( 0, 0) [003595] ----------- pred BB31 +--* PHI_ARG int V16 loc12 u:21 N003 ( 0, 0) [003592] ----------- pred BB37 +--* PHI_ARG int V16 loc12 u:20 N004 ( 0, 0) [003590] ----------- pred BB40 +--* PHI_ARG int V16 loc12 u:17 N005 ( 0, 0) [003587] ----------- pred BB46 +--* PHI_ARG int V16 loc12 u:19 N006 ( 0, 0) [003426] ----------- pred BB07 \--* PHI_ARG int V16 loc12 u:1 $283 ***** BB47 STMT00022 ( 0x204[E-] ... ??? ) N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000078] J------N--- \--* GE int $360 N001 ( 1, 1) [000073] ----------- +--* LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ***** BB48 STMT00261 ( 0x20F[E-] ... 0x216 ) N003 ( 1, 3) [001205] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001204] D------N--- +--* LCL_VAR int V71 tmp31 d:1 $VN.Void N001 ( 1, 1) [001198] ----------- \--* LCL_VAR int V16 loc12 u:2 $28b ***** BB48 STMT00260 ( 0x20F[E-] ... ??? ) N005 ( 3, 4) [001203] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001202] D------N--- +--* LCL_VAR int V16 loc12 d:17 $VN.Void N003 ( 3, 4) [001201] ----------- \--* ADD int $361 N001 ( 1, 1) [001199] ----------- +--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- \--* CNS_INT int 1 $c1 ***** BB48 STMT00262 ( ??? ... 0x21E ) N009 ( 9, 10) [001214] -A-XG---R-- * ASG int $30f N008 ( 1, 1) [001213] D------N--- +--* LCL_VAR int V72 tmp32 d:1 $VN.Void N007 ( 9, 10) [001212] ---XG------ \--* IND ushort N006 ( 6, 8) [001211] -------N--- \--* ADD long $3c7 N001 ( 1, 1) [001197] ----------- +--* LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 4, 6) [001210] ----------- \--* LSH long $3c6 N003 ( 2, 3) [001207] ----------- +--* CAST long <- int $3c5 N002 ( 1, 1) [001206] ----------- | \--* LCL_VAR int V71 tmp31 u:1 (last use) $28b N004 ( 1, 2) [001209] ----------- \--* CNS_INT long 1 $204 ***** BB48 STMT00263 ( ??? ... ??? ) N003 ( 1, 3) [001218] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001217] D------N--- +--* LCL_VAR int V18 loc14 d:5 $VN.Void N001 ( 1, 1) [001216] ----------- \--* LCL_VAR int V72 tmp32 u:1 ***** BB48 STMT00264 ( ??? ... 0x220 ) N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001220] J------N--- \--* EQ int N001 ( 1, 1) [001215] ----------- +--* LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- \--* CNS_INT int 0 $c0 ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ***** BB49 STMT00265 ( 0x222[E-] ... 0x226 ) N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001224] N------N-U- \--* NE int N001 ( 1, 1) [001222] ----------- +--* LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- \--* CNS_INT int 59 $d1 ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ***** BB50 STMT00023 ( 0x22B[E-] ... 0x22D ) N003 ( 1, 3) [000083] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000082] D------N--- +--* LCL_VAR byref V23 loc19 $VN.Void N001 ( 1, 2) [000081] ----------- \--* CNS_INT long 0 $205 ***** BB50 STMT00024 ( 0x22F[E-] ... 0x231 ) N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000086] J------N--- \--* GE int $690 N001 ( 1, 1) [000084] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- \--* CNS_INT int 0 $c0 ------------ BB51 [233..235), preds={BB50} succs={BB52} ***** BB51 STMT00259 ( 0x233[E-] ... 0x234 ) N003 ( 1, 3) [001196] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001195] D------N--- +--* LCL_VAR int V05 loc1 d:4 $VN.Void N001 ( 1, 1) [001194] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ***** BB52 STMT00569 ( ??? ... ??? ) N005 ( 0, 0) [003360] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003358] D------N--- +--* LCL_VAR int V05 loc1 d:3 $VN.Void N003 ( 0, 0) [003359] ----------- \--* PHI int $28d N001 ( 0, 0) [003577] ----------- pred BB51 +--* PHI_ARG int V05 loc1 u:4 $28a N002 ( 0, 0) [003427] ----------- pred BB50 \--* PHI_ARG int V05 loc1 u:2 $286 ***** BB52 STMT00025 ( 0x235[E-] ... 0x238 ) N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000090] J------N--- \--* LT int $692 N001 ( 1, 1) [000088] ----------- +--* LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- \--* CNS_INT int 0 $c0 ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ***** BB53 STMT00256 ( 0x23A[E-] ... 0x23D ) N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001182] N------N-U- \--* NE int $696 N001 ( 1, 1) [001180] ----------- +--* LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ***** BB54 STMT00258 ( 0x23F[E-] ... 0x246 ) N007 ( 8, 8) [001193] -A------R-- * ASG int $VN.Void N006 ( 1, 1) [001192] D------N--- +--* LCL_VAR int V13 loc9 d:4 $VN.Void N005 ( 8, 8) [001191] ----------- \--* SUB int $698 N001 ( 1, 1) [001187] ----------- +--* LCL_VAR int V13 loc9 u:2 (last use) $289 N004 ( 6, 6) [001190] ----------- \--* MUL int $697 N002 ( 1, 1) [001188] ----------- +--* LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- \--* CNS_INT int 3 $c3 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} ***** BB55 STMT00257 ( 0x24A[E-] ... 0x24B ) N003 ( 1, 3) [001186] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001185] D------N--- +--* LCL_VAR int V12 loc8 d:4 $VN.Void N001 ( 1, 2) [002615] ----------- \--* CNS_INT int 1 $c1 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ***** BB56 STMT00568 ( ??? ... ??? ) N005 ( 0, 0) [003357] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003355] D------N--- +--* LCL_VAR bool V12 loc8 d:3 $VN.Void N003 ( 0, 0) [003356] ----------- \--* PHI bool $4c4 N001 ( 0, 0) [003575] ----------- pred BB55 +--* PHI_ARG bool V12 loc8 u:4 $c1 N002 ( 0, 0) [003428] ----------- pred BB52 \--* PHI_ARG bool V12 loc8 u:2 $4c2 ***** BB56 STMT00567 ( ??? ... ??? ) N005 ( 0, 0) [003354] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003352] D------N--- +--* LCL_VAR int V13 loc9 d:3 $VN.Void N003 ( 0, 0) [003353] ----------- \--* PHI int $28e N001 ( 0, 0) [003576] ----------- pred BB54 +--* PHI_ARG int V13 loc9 u:4 $698 N002 ( 0, 0) [003429] ----------- pred BB52 \--* PHI_ARG int V13 loc9 u:2 $289 ***** BB56 STMT00026 ( 0x24D[E-] ... 0x250 ) N005 ( 8, 8) [000096] ---XG------ * JTRUE void N004 ( 6, 6) [000095] J--XG--N--- \--* EQ int N002 ( 4, 3) [000093] ---XG------ +--* IND ubyte N001 ( 1, 1) [000092] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000094] ----------- \--* CNS_INT int 0 $c0 ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ***** BB57 STMT00245 ( 0x252[E-] ... 0x25D ) N005 ( 3, 4) [001129] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001128] D------N--- +--* LCL_VAR byref V69 tmp29 d:1 $VN.Void N003 ( 3, 4) [002620] -----O----- \--* ADD byref $24a N001 ( 1, 1) [002618] -----O----- +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- \--* CNS_INT long 4 $207 ***** BB57 STMT00246 ( ??? ... ??? ) N007 ( 9, 7) [001136] -A--GO--R-- * ASG int $301 N006 ( 3, 2) [001135] n---GO-N--- +--* IND int $301 N005 ( 1, 1) [001130] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 (last use) $24a N004 ( 5, 4) [001134] ----GO----- \--* ADD int N002 ( 3, 2) [001132] n---GO----- +--* IND int N001 ( 1, 1) [001131] ----------- | \--* LCL_VAR byref V69 tmp29 u:1 $24a N003 ( 1, 1) [001133] ----------- \--* LCL_VAR int V13 loc9 u:3 (last use) $28e ***** BB57 STMT00247 ( 0x25E[E-] ... 0x260 ) N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001139] J------N--- \--* NE int $6a7 N001 ( 1, 1) [001137] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- \--* CNS_INT int 0 $c0 ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ***** BB58 STMT00255 ( 0x262[E-] ... 0x26C ) N010 ( 8, 7) [001178] -A--GO--R-- * ASG int $301 N009 ( 1, 1) [001177] D------N--- +--* LCL_VAR int V70 tmp30 d:3 $VN.Void N008 ( 8, 7) [001176] ----GO----- \--* SUB int N006 ( 6, 5) [001174] ----GO----- +--* ADD int N004 ( 4, 3) [001172] n---GO----- | +--* IND int N003 ( 3, 4) [002623] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [001171] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 1) [001173] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 1, 1) [001175] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB59 [26E..26F), preds={BB57} succs={BB60} ***** BB59 STMT00248 ( 0x26E[E-] ... 0x26E ) N003 ( 1, 3) [001143] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001142] D------N--- +--* LCL_VAR int V70 tmp30 d:2 $VN.Void N001 ( 1, 1) [001141] ----------- \--* LCL_VAR int V04 loc0 u:2 $28a ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ***** BB60 STMT00566 ( ??? ... ??? ) N005 ( 0, 0) [003351] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003349] D------N--- +--* LCL_VAR int V70 tmp30 d:1 $VN.Void N003 ( 0, 0) [003350] ----------- \--* PHI int $291 N001 ( 0, 0) [003574] ----------- pred BB58 +--* PHI_ARG int V70 tmp30 u:3 N002 ( 0, 0) [003573] ----------- pred BB59 \--* PHI_ARG int V70 tmp30 u:2 $28a ***** BB60 STMT00250 ( 0x271[E-] ... 0x27D ) N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001145] ----------- arg2 in x1 +--* LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- arg1 in x0 +--* LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- arg3 in x2 \--* CNS_INT int 0 $c0 ***** BB60 STMT00251 ( 0x27A[E-] ... ??? ) N005 ( 8, 8) [001156] ---XG------ * JTRUE void N004 ( 6, 6) [001155] J--XG--N--- \--* NE int N002 ( 4, 3) [001153] ---XG------ +--* IND ubyte N001 ( 1, 1) [001152] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [001154] ----------- \--* CNS_INT int 0 $c0 ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ***** BB61 STMT00252 ( 0x27F[E-] ... 0x286 ) N008 ( 21, 20) [001163] -ACXG---R-- * ASG int $VN.Void N007 ( 1, 1) [001162] D------N--- +--* LCL_VAR int V16 loc12 d:16 $VN.Void N006 ( 21, 20) [001159] --CXG------ \--* CALL r2r_ind int $2c4 N003 ( 4, 5) [002626] -c--------- arg1 x0,x1 +--* FIELD_LIST struct $142 N001 ( 1, 1) [003713] ----------- ofs 0 | +--* LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- ofs 8 | \--* LCL_FLD long V02 arg2 u:1[+8] $3ce N004 ( 2, 8) [002625] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- arg2 in x2 \--* CNS_INT int 2 $c2 ***** BB61 STMT00253 ( 0x288[E-] ... 0x28C ) N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001166] J------N--- \--* EQ int $6b6 N001 ( 1, 1) [001164] ----------- +--* LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ***** BB62 STMT00254 ( 0x28E[E-] ... 0x290 ) N003 ( 1, 3) [001170] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001169] D------N--- +--* LCL_VAR int V15 loc11 d:3 $VN.Void N001 ( 1, 1) [001168] ----------- \--* LCL_VAR int V16 loc12 u:16 (last use) $2c4 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ***** BB63 STMT00027 ( 0x297[E-] ... 0x29E ) N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 N006 ( 7, 7) [000100] J---GO-N--- \--* EQ int N004 ( 5, 4) [000098] n---GO----- +--* IND ubyte N003 ( 3, 4) [002630] -------N--- | \--* ADD byref $249 N001 ( 1, 1) [000097] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- | \--* CNS_INT long 10 $206 N005 ( 1, 2) [000099] ----------- \--* CNS_INT int 3 $c3 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} ***** BB64 STMT00244 ( 0x2A0[E-] ... 0x2A2 ) N006 ( 7, 7) [001125] -A--GO----- * ASG bool $301 N004 ( 5, 4) [001124] n---GO-N--- +--* IND bool $301 N003 ( 3, 4) [002632] -------N--- | \--* ADD byref $247 N001 ( 1, 1) [001122] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- | \--* CNS_INT long 8 $201 N005 ( 1, 2) [001123] ----------- \--* CNS_INT int 0 $c0 ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ***** BB65 STMT00028 ( 0x2A7[E-] ... 0x2A9 ) N006 ( 6, 6) [000105] -A--GO----- * ASG int $301 N004 ( 4, 3) [000104] n---GO-N--- +--* IND int $301 N003 ( 3, 4) [002634] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000102] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000103] ----------- \--* CNS_INT int 0 $c0 ------------ BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} ***** BB66 STMT00565 ( ??? ... ??? ) N005 ( 0, 0) [003348] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003346] D------N--- +--* LCL_VAR int V44 tmp4 d:1 $VN.Void N003 ( 0, 0) [003347] ----------- \--* PHI int $292 N001 ( 0, 0) [003570] ----------- pred BB67 +--* PHI_ARG int V44 tmp4 u:3 $c0 N002 ( 0, 0) [003569] ----------- pred BB68 \--* PHI_ARG int V44 tmp4 u:2 $6b8 ***** BB66 STMT00564 ( ??? ... ??? ) N005 ( 0, 0) [003345] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003343] D------N--- +--* LCL_VAR int V45 tmp5 d:1 $VN.Void N003 ( 0, 0) [003344] ----------- \--* PHI int $293 N001 ( 0, 0) [003568] ----------- pred BB70 +--* PHI_ARG int V45 tmp5 u:3 $c0 N002 ( 0, 0) [003567] ----------- pred BB71 \--* PHI_ARG int V45 tmp5 u:2 $6ba ***** BB66 STMT00029 ( 0x2AE[E-] ... 0x2B0 ) N001 ( 0, 0) [003778] ----------- * NOP void ***** BB66 STMT00243 ( 0x2B2[E-] ... 0x2B3 ) N010 ( 12, 12) [001120] -A------R-- * ASG int $VN.Void N009 ( 3, 2) [001119] D------N--- +--* LCL_VAR int V44 tmp4 d:3 $VN.Void N008 ( 8, 9) [003777] ----------- \--* SELECT int N003 ( 3, 3) [000108] J------N--- +--* LT int $6b7 N001 ( 1, 1) [000106] ----------- | +--* LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N006 ( 3, 3) [000112] ----------- +--* SUB int $6b8 N004 ( 1, 1) [000110] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- | \--* LCL_VAR int V06 loc2 u:2 (last use) $284 N007 ( 1, 2) [001118] ----------- \--* CNS_INT int 0 $c0 ***** BB66 STMT00030 ( 0x2B5[E-] ... 0x2B7 ) N001 ( 0, 0) [003779] ----------- * NOP void ***** BB66 STMT00031 ( ??? ... 0x2B8 ) N003 ( 3, 3) [000118] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000117] D------N--- +--* LCL_VAR int V06 loc2 d:3 $VN.Void N001 ( 3, 2) [000116] ----------- \--* LCL_VAR int V44 tmp4 u:1 (last use) $292 ***** BB66 STMT00032 ( 0x2B9[E-] ... 0x2BB ) N001 ( 0, 0) [003775] ----------- * NOP void ***** BB66 STMT00242 ( 0x2BD[E-] ... 0x2BE ) N010 ( 12, 12) [001116] -A------R-- * ASG int $VN.Void N009 ( 3, 2) [001115] D------N--- +--* LCL_VAR int V45 tmp5 d:3 $VN.Void N008 ( 8, 9) [003774] ----------- \--* SELECT int N003 ( 3, 3) [000121] J------N--- +--* GT int $6b9 N001 ( 1, 1) [000119] ----------- | +--* LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N006 ( 3, 3) [000125] ----------- +--* SUB int $6ba N004 ( 1, 1) [000123] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- | \--* LCL_VAR int V07 loc3 u:2 (last use) $285 N007 ( 1, 2) [001114] ----------- \--* CNS_INT int 0 $c0 ***** BB66 STMT00033 ( 0x2C0[E-] ... 0x2C2 ) N001 ( 0, 0) [003776] ----------- * NOP void ***** BB66 STMT00034 ( ??? ... 0x2C3 ) N003 ( 3, 3) [000131] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000130] D------N--- +--* LCL_VAR int V07 loc3 d:3 $VN.Void N001 ( 3, 2) [000129] ----------- \--* LCL_VAR int V45 tmp5 u:1 (last use) $293 ***** BB66 STMT00035 ( 0x2C4[E-] ... 0x2C6 ) N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000134] J------N--- \--* EQ int $6bb N001 ( 1, 1) [000132] ----------- +--* LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- \--* CNS_INT int 0 $c0 ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} ***** BB73 STMT00240 ( 0x2C8[E-] ... 0x2C9 ) N003 ( 1, 3) [001110] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001109] D------N--- +--* LCL_VAR int V08 loc4 d:8 $VN.Void N001 ( 1, 1) [001108] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB73 STMT00241 ( 0x2CB[E-] ... 0x2CC ) N003 ( 1, 3) [001113] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001112] D------N--- +--* LCL_VAR int V14 loc10 d:9 $VN.Void N001 ( 1, 2) [001111] ----------- \--* CNS_INT int 0 $c0 ------------ BB74 [2D0..2EE), preds={BB66} succs={BB78} ***** BB74 STMT00563 ( ??? ... ??? ) N005 ( 0, 0) [003342] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003340] D------N--- +--* LCL_VAR int V46 tmp6 d:1 $VN.Void N003 ( 0, 0) [003341] ----------- \--* PHI int $295 N001 ( 0, 0) [003564] ----------- pred BB75 +--* PHI_ARG int V46 tmp6 u:3 $28d N002 ( 0, 0) [003563] ----------- pred BB76 \--* PHI_ARG int V46 tmp6 u:2 ***** BB74 STMT00036 ( 0x2D0[E-] ... 0x2D7 ) N001 ( 0, 0) [003772] ----------- * NOP void ***** BB74 STMT00239 ( 0x2D9[E-] ... 0x2DA ) N015 ( 22, 17) [001106] -A--GO--R-- * ASG int $VN.Void N014 ( 3, 2) [001105] D------N--- +--* LCL_VAR int V46 tmp6 d:3 $VN.Void N013 ( 18, 14) [003771] -A--GO----- \--* SELECT int N010 ( 13, 10) [000139] JA--GO-N--- +--* GT int N008 ( 11, 8) [003685] -A--GO----- | +--* COMMA int N006 ( 8, 6) [003683] -A--GO--R-- | | +--* ASG int $VN.Void N005 ( 3, 2) [003682] D------N--- | | | +--* LCL_VAR int V178 cse7 d:1 $VN.Void N004 ( 4, 3) [000137] n---GO----- | | | \--* IND int N003 ( 3, 4) [002636] -------N--- | | | \--* ADD byref $24a N001 ( 1, 1) [000136] ----------- | | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- | | | \--* CNS_INT long 4 $207 N007 ( 3, 2) [003684] ----------- | | \--* LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- | \--* LCL_VAR int V05 loc1 u:3 $28d N011 ( 3, 2) [003686] ----------- +--* LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ***** BB74 STMT00037 ( 0x2DC[E-] ... 0x2DD ) N001 ( 0, 0) [003773] ----------- * NOP void ***** BB74 STMT00038 ( ??? ... 0x2E2 ) N003 ( 3, 3) [000148] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000147] D------N--- +--* LCL_VAR int V08 loc4 d:7 $VN.Void N001 ( 3, 2) [000146] ----------- \--* LCL_VAR int V46 tmp6 u:1 (last use) $295 ***** BB74 STMT00039 ( 0x2E4[E-] ... 0x2EC ) N005 ( 5, 4) [000154] -A--G---R-- * ASG int $301 N004 ( 1, 1) [000153] D------N--- +--* LCL_VAR int V14 loc10 d:8 $VN.Void N003 ( 5, 4) [000152] ----G------ \--* SUB int N001 ( 3, 2) [003687] ----------- +--* LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB74} succs={BB79,BB103} ***** BB78 STMT00562 ( ??? ... ??? ) N005 ( 0, 0) [003339] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003337] D------N--- +--* LCL_VAR int V14 loc10 d:1 $VN.Void N003 ( 0, 0) [003338] ----------- \--* PHI int $296 N001 ( 0, 0) [003565] ----------- pred BB73 +--* PHI_ARG int V14 loc10 u:9 $c0 N002 ( 0, 0) [003561] ----------- pred BB77 \--* PHI_ARG int V14 loc10 u:8 ***** BB78 STMT00561 ( ??? ... ??? ) N005 ( 0, 0) [003336] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003334] D------N--- +--* LCL_VAR int V08 loc4 d:1 $VN.Void N003 ( 0, 0) [003335] ----------- \--* PHI int $297 N001 ( 0, 0) [003566] ----------- pred BB73 +--* PHI_ARG int V08 loc4 u:8 $28d N002 ( 0, 0) [003562] ----------- pred BB77 \--* PHI_ARG int V08 loc4 u:7 $295 ***** BB78 STMT00040 ( 0x2EE[E-] ... 0x2F0 ) N003 ( 1, 3) [000157] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000156] D------N--- +--* LCL_VAR int V16 loc12 d:3 $VN.Void N001 ( 1, 1) [000155] ----------- \--* LCL_VAR int V15 loc11 u:2 $283 ***** BB78 STMT00041 ( 0x2F2[E-] ... 0x2FD ) N003 ( 0, 0) [002647] ----------- * COMMA void $582 N001 ( 0, 0) [002643] ----------- +--* NOP void $581 N002 ( 0, 0) [002646] ----------- \--* NOP void $582 ***** BB78 STMT00324 ( INL09 @ 0x01F[E-] ... ??? ) <- INLRT @ ??? N003 ( 3, 3) [001553] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [001552] D------N--- +--* LCL_VAR byref V151 tmp111 d:1 $VN.Void N001 ( 3, 3) [001550] ----------- \--* LCL_VAR_ADDR long V47 tmp7 $740 ***** BB78 STMT00325 ( INL09 @ 0x026[E-] ... ??? ) <- INLRT @ ??? N003 ( 1, 3) [001558] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001557] D------N--- +--* LCL_VAR int V152 tmp112 d:1 $VN.Void N001 ( 1, 2) [001556] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00044 ( 0x2FF[E-] ... 0x301 ) N007 ( 2, 6) [002654] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002650] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002648] D------N--- | +--* LCL_VAR byref V143 tmp103 d:1 $VN.Void N001 ( 1, 1) [002649] ----------- | \--* LCL_VAR byref V151 tmp111 u:1 (last use) $24b N006 ( 1, 3) [002653] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002651] D------N--- +--* LCL_VAR int V144 tmp104 d:1 $VN.Void N004 ( 1, 2) [003720] ----------- \--* CNS_INT int 4 $c8 ***** BB78 STMT00045 ( 0x303[E-] ... 0x304 ) N003 ( 1, 3) [000177] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000176] D------N--- +--* LCL_VAR int V20 loc16 d:1 $VN.Void N001 ( 1, 2) [000175] ----------- \--* CNS_INT int -1 $c4 ***** BB78 STMT00046 ( 0x306[E-] ... 0x308 ) N012 ( 20, 15) [000181] ---XG------ * JTRUE void $VN.Void N011 ( 18, 13) [003732] J--XG--N--- \--* AND int N007 ( 11, 8) [000946] ---XG--N--- +--* LE int N005 ( 6, 5) [000944] ---XG------ | +--* ARR_LENGTH int N004 ( 4, 3) [001570] ---XG------ | | \--* IND ref N003 ( 3, 4) [002656] -------N--- | | \--* ADD byref $24c N001 ( 1, 1) [000941] ----------- | | +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- | | \--* CNS_INT long 56 Fseq[] $209 N006 ( 1, 2) [000945] ----------- | \--* CNS_INT int 0 $c0 N010 ( 6, 4) [000180] -------N--- \--* EQ int $70a N008 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] ----------- \--* CNS_INT int 0 $c0 ------------ BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} ***** BB79 STMT00203 ( 0x30D[E-] ... ??? ) N001 ( 0, 0) [003733] ----------- * NOP void ***** BB79 STMT00204 ( 0x31E[E-] ... 0x324 ) N006 ( 4, 3) [000951] -A--GO--R-- * ASG ref $321 N005 ( 1, 1) [000950] D------N--- +--* LCL_VAR ref V26 loc22 d:1 $VN.Void N004 ( 4, 3) [000949] n---GO----- \--* IND ref N003 ( 3, 4) [002658] -------N--- \--* ADD byref $24d N001 ( 1, 1) [000948] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- \--* CNS_INT long 8 Fseq[] $201 ***** BB79 STMT00205 ( 0x326[E-] ... 0x327 ) N003 ( 1, 3) [000954] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000953] D------N--- +--* LCL_VAR int V27 loc23 d:1 $VN.Void N001 ( 1, 2) [000952] ----------- \--* CNS_INT int 0 $c0 ***** BB79 STMT00206 ( 0x329[E-] ... 0x32A ) N003 ( 1, 3) [000957] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000956] D------N--- +--* LCL_VAR int V28 loc24 d:1 $VN.Void N001 ( 1, 2) [000955] ----------- \--* CNS_INT int 0 $c0 ***** BB79 STMT00207 ( 0x32C[E-] ... 0x330 ) N004 ( 3, 3) [000961] -A-X----R-- * ASG int N003 ( 1, 1) [000960] D------N--- +--* LCL_VAR int V29 loc25 d:1 $VN.Void N002 ( 3, 3) [000959] ---X------- \--* ARR_LENGTH int N001 ( 1, 1) [000958] ----------- \--* LCL_VAR ref V26 loc22 u:1 ***** BB79 STMT00208 ( 0x332[E-] ... 0x334 ) N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000964] J------N--- \--* EQ int N001 ( 1, 1) [000962] ----------- +--* LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- \--* CNS_INT int 0 $c0 ------------ BB81 [336..33D), preds={BB79} succs={BB82} ***** BB81 STMT00238 ( 0x336[E-] ... 0x33B ) N009 ( 4, 3) [001103] -A--GO--R-- * ASG int N008 ( 1, 1) [001102] D------N--- +--* LCL_VAR int V28 loc24 d:5 $VN.Void N007 ( 4, 3) [002670] ----GO-N--- \--* COMMA int N001 ( 0, 0) [002662] ----------- +--* NOP void N006 ( 4, 3) [002671] n---GO----- \--* IND int N005 ( 1, 1) [002669] -----O----- \--* ARR_ADDR byref int[] $82 N004 ( 1, 1) [002667] -------N--- \--* ADD byref N002 ( 1, 1) [002659] ----------- +--* LCL_VAR ref V26 loc22 u:1 N003 ( 1, 2) [002666] ----------- \--* CNS_INT long 16 $200 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} ***** BB82 STMT00560 ( ??? ... ??? ) N005 ( 0, 0) [003333] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003331] D------N--- +--* LCL_VAR int V28 loc24 d:2 $VN.Void N003 ( 0, 0) [003332] ----------- \--* PHI int $298 N001 ( 0, 0) [003560] ----------- pred BB81 +--* PHI_ARG int V28 loc24 u:5 N002 ( 0, 0) [003519] ----------- pred BB80 \--* PHI_ARG int V28 loc24 u:1 $c0 ***** BB82 STMT00209 ( 0x33D[E-] ... 0x33F ) N003 ( 1, 3) [000968] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000967] D------N--- +--* LCL_VAR int V30 loc26 d:1 $VN.Void N001 ( 1, 1) [000966] ----------- \--* LCL_VAR int V28 loc24 u:2 $298 ***** BB82 STMT00211 ( ??? ... 0x346 ) N003 ( 5, 4) [000975] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000974] D------N--- +--* LCL_VAR int V64 tmp24 d:1 $VN.Void N001 ( 1, 1) [000969] ----------- \--* LCL_VAR int V08 loc4 u:1 $297 ***** BB82 STMT00210 ( 0x341[E-] ... 0x346 ) N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000972] J------N--- \--* LT int $719 N001 ( 1, 1) [000970] ----------- +--* LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- \--* CNS_INT int 0 $c0 ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ***** BB83 STMT00236 ( ??? ... 0x349 ) N003 ( 7, 5) [001093] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001092] D------N--- +--* LCL_VAR int V65 tmp25 d:3 $VN.Void N001 ( 3, 2) [000977] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB83 STMT00237 ( ??? ... ??? ) N003 ( 5, 5) [001096] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [001095] D------N--- +--* LCL_VAR int V66 tmp26 d:3 $VN.Void N001 ( 1, 2) [001091] ----------- \--* CNS_INT int 0 $c0 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} ***** BB84 STMT00212 ( ??? ... 0x34B ) N003 ( 7, 5) [000981] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000980] D------N--- +--* LCL_VAR int V65 tmp25 d:2 $VN.Void N001 ( 3, 2) [000978] ----------- \--* LCL_VAR int V64 tmp24 u:1 (last use) $297 ***** BB84 STMT00213 ( ??? ... ??? ) N003 ( 5, 4) [000984] -A------R-- * ASG int $VN.Void N002 ( 3, 2) [000983] D------N--- +--* LCL_VAR int V66 tmp26 d:2 $VN.Void N001 ( 1, 1) [000979] ----------- \--* LCL_VAR int V14 loc10 u:1 $296 ------------ BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} ***** BB85 STMT00559 ( ??? ... ??? ) N005 ( 0, 0) [003330] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003328] D------N--- +--* LCL_VAR int V66 tmp26 d:1 $VN.Void N003 ( 0, 0) [003329] ----------- \--* PHI int $299 N001 ( 0, 0) [003558] ----------- pred BB83 +--* PHI_ARG int V66 tmp26 u:3 $c0 N002 ( 0, 0) [003556] ----------- pred BB84 \--* PHI_ARG int V66 tmp26 u:2 $296 ***** BB85 STMT00558 ( ??? ... ??? ) N005 ( 0, 0) [003327] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003325] D------N--- +--* LCL_VAR int V65 tmp25 d:1 $VN.Void N003 ( 0, 0) [003326] ----------- \--* PHI int $297 N001 ( 0, 0) [003559] ----------- pred BB83 +--* PHI_ARG int V65 tmp25 u:3 $297 N002 ( 0, 0) [003557] ----------- pred BB84 \--* PHI_ARG int V65 tmp25 u:2 $297 ***** BB85 STMT00557 ( ??? ... ??? ) N005 ( 0, 0) [003324] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003322] D------N--- +--* LCL_VAR int V67 tmp27 d:1 $VN.Void N003 ( 0, 0) [003323] ----------- \--* PHI int $29a N001 ( 0, 0) [003555] ----------- pred BB86 +--* PHI_ARG int V67 tmp27 u:3 $71a N002 ( 0, 0) [003554] ----------- pred BB87 \--* PHI_ARG int V67 tmp27 u:2 $292 ***** BB85 STMT00214 ( ??? ... 0x34E ) N005 ( 11, 8) [000990] -A------R-- * ASG int $VN.Void N004 ( 3, 2) [000989] D------N--- +--* LCL_VAR int V31 loc27 d:1 $VN.Void N003 ( 7, 5) [000988] ----------- \--* ADD int $71a N001 ( 3, 2) [000986] ----------- +--* LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- \--* LCL_VAR int V66 tmp26 u:1 (last use) $299 ***** BB85 STMT00215 ( 0x350[E-] ... 0x353 ) N001 ( 0, 0) [003769] ----------- * NOP void ***** BB85 STMT00235 ( 0x355[E-] ... 0x357 ) N008 ( 14, 11) [001089] -A------R-- * ASG int $VN.Void N007 ( 3, 2) [001088] D------N--- +--* LCL_VAR int V67 tmp27 d:3 $VN.Void N006 ( 10, 8) [003768] ----------- \--* SELECT int N003 ( 5, 4) [000993] J------N--- +--* GT int $71b N001 ( 1, 1) [000991] ----------- | +--* LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- | \--* LCL_VAR int V31 loc27 u:1 $71a N004 ( 1, 1) [000995] ----------- +--* LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- \--* LCL_VAR int V31 loc27 u:1 (last use) $71a ***** BB85 STMT00216 ( 0x359[E-] ... 0x359 ) N001 ( 0, 0) [003770] ----------- * NOP void ***** BB85 STMT00217 ( ??? ... 0x35A ) N003 ( 3, 3) [001001] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [001000] D------N--- +--* LCL_VAR int V32 loc28 d:1 $VN.Void N001 ( 3, 2) [000999] ----------- \--* LCL_VAR int V67 tmp27 u:1 (last use) $29a ***** BB85 STMT00502 ( 0x3C2[E-] ... ??? ) N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [003157] J------N--- \--* LE int $71c N001 ( 1, 1) [003158] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- \--* LCL_VAR int V30 loc26 u:1 $298 ------------ BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} ***** BB89 STMT00556 ( ??? ... ??? ) N005 ( 0, 0) [003321] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003319] D------N--- +--* LCL_VAR int V20 loc16 d:10 $VN.Void N003 ( 0, 0) [003320] ----------- \--* PHI int $29b N001 ( 0, 0) [003536] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 N002 ( 0, 0) [003520] ----------- pred BB88 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB89 STMT00550 ( ??? ... ??? ) N005 ( 0, 0) [003303] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003301] D------N--- +--* LCL_VAR byref V143 tmp103 d:3 $VN.Void N003 ( 0, 0) [003302] ----------- \--* PHI byref $381 N001 ( 0, 0) [003537] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 N002 ( 0, 0) [003521] ----------- pred BB88 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB89 STMT00547 ( ??? ... ??? ) N005 ( 0, 0) [003294] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003292] D------N--- +--* LCL_VAR int V144 tmp104 d:3 $VN.Void N003 ( 0, 0) [003293] ----------- \--* PHI int $29c N001 ( 0, 0) [003538] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 N002 ( 0, 0) [003522] ----------- pred BB88 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB89 STMT00544 ( ??? ... ??? ) N005 ( 0, 0) [003285] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003283] D------N--- +--* LCL_VAR int V30 loc26 d:2 $VN.Void N003 ( 0, 0) [003284] ----------- \--* PHI int $29d N001 ( 0, 0) [003539] ----------- pred BB102 +--* PHI_ARG int V30 loc26 u:3 N002 ( 0, 0) [003523] ----------- pred BB88 \--* PHI_ARG int V30 loc26 u:1 $298 ***** BB89 STMT00542 ( ??? ... ??? ) N005 ( 0, 0) [003279] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003277] D------N--- +--* LCL_VAR int V27 loc23 d:2 $VN.Void N003 ( 0, 0) [003278] ----------- \--* PHI int $29e N001 ( 0, 0) [003540] ----------- pred BB102 +--* PHI_ARG int V27 loc23 u:3 N002 ( 0, 0) [003524] ----------- pred BB88 \--* PHI_ARG int V27 loc23 u:1 $c0 ***** BB89 STMT00540 ( ??? ... ??? ) N005 ( 0, 0) [003273] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003271] D------N--- +--* LCL_VAR int V28 loc24 d:3 $VN.Void N003 ( 0, 0) [003272] ----------- \--* PHI int $29f N001 ( 0, 0) [003541] ----------- pred BB102 +--* PHI_ARG int V28 loc24 u:4 N002 ( 0, 0) [003525] ----------- pred BB88 \--* PHI_ARG int V28 loc24 u:2 $298 ***** BB89 STMT00219 ( 0x35E[E-] ... 0x360 ) N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001008] J------N--- \--* EQ int $71e N001 ( 1, 1) [001006] ----------- +--* LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- \--* CNS_INT int 0 $c0 ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ***** BB90 STMT00220 ( 0x362[E-] ... 0x366 ) N005 ( 3, 4) [001014] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001013] D------N--- +--* LCL_VAR int V20 loc16 d:11 $VN.Void N003 ( 3, 4) [001012] ----------- \--* ADD int $71f N001 ( 1, 1) [001010] ----------- +--* LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- \--* CNS_INT int 1 $c1 ***** BB90 STMT00222 ( 0x368[E-] ... ??? ) N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001020] J------N--- \--* LT int $720 N001 ( 1, 1) [001015] ----------- +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- \--* LCL_VAR int V144 tmp104 u:3 $29c ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} ***** BB91 STMT00554 ( ??? ... ??? ) N005 ( 0, 0) [003315] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003313] D------N--- +--* LCL_VAR byref V159 tmp119 d:1 $VN.Void N003 ( 0, 0) [003314] ----------- \--* PHI byref $382 N001 ( 0, 0) [003552] ----------- pred BB92 +--* PHI_ARG byref V159 tmp119 u:3 $VN.Null N002 ( 0, 0) [003550] ----------- pred BB93 \--* PHI_ARG byref V159 tmp119 u:2 $253 ***** BB91 STMT00553 ( ??? ... ??? ) N005 ( 0, 0) [003312] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003310] D------N--- +--* LCL_VAR int V160 tmp120 d:1 $VN.Void N003 ( 0, 0) [003311] ----------- \--* PHI int $2a0 N001 ( 0, 0) [003553] ----------- pred BB92 +--* PHI_ARG int V160 tmp120 u:3 $c0 N002 ( 0, 0) [003551] ----------- pred BB93 \--* PHI_ARG int V160 tmp120 u:2 $2cc ***** BB91 STMT00229 ( 0x373[E-] ... ??? ) N008 ( 20, 18) [001070] -ACXG---R-- * ASG ref $331 N007 ( 1, 1) [001069] D------N--- +--* LCL_VAR ref V33 loc29 d:1 $VN.Void N006 ( 20, 18) [001068] --CXG------ \--* CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 N004 ( 4, 6) [001067] ----------- arg1 in x0 +--* CAST long <- int $3cf N003 ( 3, 4) [001066] ----------- | \--* LSH int $721 N001 ( 1, 1) [001578] ----------- | +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- | \--* CNS_INT int 1 $c1 N005 ( 2, 8) [002672] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000421858 ftn $49 ***** BB91 STMT00327 ( INL14 @ 0x000[E-] ... ??? ) <- INLRT @ 0x383[E-] N003 ( 0, 0) [002679] ----------- * COMMA void $584 N001 ( 0, 0) [002675] ----------- +--* NOP void $583 N002 ( 0, 0) [002678] ----------- \--* NOP void $584 ***** BB91 STMT00331 ( INL15 @ 0x038[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N005 ( 3, 4) [001604] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001603] D------N--- +--* LCL_VAR byref V159 tmp119 d:2 $VN.Void N003 ( 3, 4) [002691] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002689] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB91 STMT00332 ( INL15 @ 0x044[E-] ... ??? ) <- INL14 @ ??? <- INLRT @ 0x383[E-] N004 ( 3, 3) [001610] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001609] D------N--- +--* LCL_VAR int V160 tmp120 d:2 $VN.Void N002 ( 3, 3) [001608] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001607] ----------- \--* LCL_VAR ref V33 loc29 u:1 $800 ***** BB91 STMT00339 ( ??? ... ??? ) N005 ( 1, 3) [002699] -A--------- * COMMA void $585 N003 ( 1, 3) [002695] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002693] D------N--- | +--* LCL_VAR byref V161 tmp121 d:1 $VN.Void N001 ( 1, 1) [002694] ----------- | \--* LCL_VAR byref V159 tmp119 u:1 (last use) $382 N004 ( 0, 0) [002698] ----------- \--* NOP void $585 ***** BB91 STMT00336 ( INL17 @ ??? ... ??? ) <- INLRT @ ??? N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001628] N------N-U- \--* GT int $722 N001 ( 1, 1) [001620] ----------- +--* LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- \--* LCL_VAR int V160 tmp120 u:1 (last use) $2a0 ------------ BB95 [000..392), preds={BB91} succs={BB100} ***** BB95 STMT00552 ( ??? ... ??? ) N005 ( 0, 0) [003309] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003307] D------N--- +--* LCL_VAR int V164 tmp124 d:1 $VN.Void N003 ( 0, 0) [003308] ----------- \--* PHI int $2a1 N001 ( 0, 0) [003548] ----------- pred BB97 +--* PHI_ARG int V164 tmp124 u:3 $c0 N002 ( 0, 0) [003546] ----------- pred BB98 \--* PHI_ARG int V164 tmp124 u:2 $2cc ***** BB95 STMT00551 ( ??? ... ??? ) N005 ( 0, 0) [003306] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003304] D------N--- +--* LCL_VAR byref V163 tmp123 d:1 $VN.Void N003 ( 0, 0) [003305] ----------- \--* PHI byref $383 N001 ( 0, 0) [003549] ----------- pred BB97 +--* PHI_ARG byref V163 tmp123 u:3 $VN.Null N002 ( 0, 0) [003547] ----------- pred BB98 \--* PHI_ARG byref V163 tmp123 u:2 $253 ***** BB95 STMT00346 ( INL17 @ 0x00F[E-] ... ??? ) <- INLRT @ ??? N004 ( 2, 3) [001673] -A------R-- * ASG long $VN.Void N003 ( 1, 1) [001672] D------N--- +--* LCL_VAR long V83 tmp43 d:1 $VN.Void N002 ( 2, 3) [001640] ---------U- \--* CAST long <- ulong <- uint $3d0 N001 ( 1, 1) [001639] ----------- \--* LCL_VAR int V144 tmp104 u:3 (last use) $29c ***** BB95 STMT00343 ( INL19 @ 0x007[E-] ... ??? ) <- INL17 @ 0x00F[E-] <- INLRT @ ??? N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void N003 ( 3, 4) [001666] ----------- arg3 in x2 +--* LSH long $3d1 N001 ( 1, 1) [001663] ----------- | +--* LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- | \--* CNS_INT long 2 $20a N004 ( 1, 1) [001661] ----------- arg1 in x0 +--* LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- arg2 in x1 +--* LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000420490 ftn $4b ***** BB95 STMT00351 ( INL22 @ 0x000[E-] ... ??? ) <- INLRT @ 0x391[E-] N003 ( 0, 0) [002708] ----------- * COMMA void $587 N001 ( 0, 0) [002704] ----------- +--* NOP void $586 N002 ( 0, 0) [002707] ----------- \--* NOP void $587 ***** BB95 STMT00355 ( INL23 @ 0x038[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N005 ( 3, 4) [001716] -A---O--R-- * ASG byref $VN.Void N004 ( 1, 1) [001715] D------N--- +--* LCL_VAR byref V163 tmp123 d:2 $VN.Void N003 ( 3, 4) [002720] -----O----- \--* ADD byref $253 N001 ( 1, 1) [002718] -----O----- +--* LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- \--* CNS_INT long 16 Fseq[] $200 ***** BB95 STMT00356 ( INL23 @ 0x044[E-] ... ??? ) <- INL22 @ ??? <- INLRT @ 0x391[E-] N004 ( 3, 3) [001722] -A-X----R-- * ASG int $VN.Void N003 ( 1, 1) [001721] D------N--- +--* LCL_VAR int V164 tmp124 d:2 $VN.Void N002 ( 3, 3) [001720] ---X------- \--* ARR_LENGTH int $2cc N001 ( 1, 1) [001719] ----------- \--* LCL_VAR ref V33 loc29 u:1 (last use) $800 ***** BB95 STMT00234 ( 0x391[E-] ... ??? ) N007 ( 2, 6) [002728] -A--------- * COMMA void $VN.Void N003 ( 1, 3) [002724] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002722] D------N--- | +--* LCL_VAR byref V143 tmp103 d:5 $VN.Void N001 ( 1, 1) [002723] ----------- | \--* LCL_VAR byref V163 tmp123 u:1 (last use) $383 N006 ( 1, 3) [002727] -A------R-- \--* ASG int $VN.Void N005 ( 1, 1) [002725] D------N--- +--* LCL_VAR int V144 tmp104 d:5 $VN.Void N004 ( 1, 1) [002726] ----------- \--* LCL_VAR int V164 tmp124 u:1 (last use) $2a1 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} ***** BB100 STMT00548 ( ??? ... ??? ) N005 ( 0, 0) [003297] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003295] D------N--- +--* LCL_VAR byref V143 tmp103 d:4 $VN.Void N003 ( 0, 0) [003296] ----------- \--* PHI byref $384 N001 ( 0, 0) [003544] ----------- pred BB99 +--* PHI_ARG byref V143 tmp103 u:5 $383 N002 ( 0, 0) [003529] ----------- pred BB90 \--* PHI_ARG byref V143 tmp103 u:3 $381 ***** BB100 STMT00545 ( ??? ... ??? ) N005 ( 0, 0) [003288] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003286] D------N--- +--* LCL_VAR int V144 tmp104 d:4 $VN.Void N003 ( 0, 0) [003287] ----------- \--* PHI int $2a2 N001 ( 0, 0) [003545] ----------- pred BB99 +--* PHI_ARG int V144 tmp104 u:5 $2a1 N002 ( 0, 0) [003530] ----------- pred BB90 \--* PHI_ARG int V144 tmp104 u:3 $29c ***** BB100 STMT00223 ( 0x39A[E-] ... 0x3A5 ) N013 ( 16, 20) [001038] -A-XGO----- * ASG int $338 N011 ( 14, 18) [001035] ---XGO-N--- +--* COMMA int $338 N003 ( 6, 9) [001029] ---X-O----- | +--* BOUNDS_CHECK_Rng void $334 N001 ( 1, 1) [001024] ----------- | | +--* LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- | | \--* LCL_VAR int V144 tmp104 u:4 $2a2 N010 ( 8, 9) [002729] D--XGO-N--- | \--* IND int $336 N009 ( 6, 8) [001034] -----O-N--- | \--* ADD byref $255 N004 ( 1, 1) [001033] ----------- | +--* LCL_VAR byref V143 tmp103 u:4 $384 N008 ( 4, 6) [001032] ----------- | \--* LSH long $3d3 N006 ( 2, 3) [001030] ---------U- | +--* CAST long <- uint $3d2 N005 ( 1, 1) [001025] ----------- | | \--* LCL_VAR int V20 loc16 u:11 $71f N007 ( 1, 2) [001031] ----------- | \--* CNS_INT long 2 $20a N012 ( 1, 1) [001036] ----------- \--* LCL_VAR int V28 loc24 u:3 $29f ***** BB100 STMT00224 ( 0x3A6[E-] ... 0x3AC ) N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [001043] J------N--- \--* GE int N001 ( 1, 1) [001039] ----------- +--* LCL_VAR int V27 loc23 u:2 $29e N004 ( 3, 4) [001042] ----------- \--* ADD int N002 ( 1, 1) [001040] ----------- +--* LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- \--* CNS_INT int -1 $c4 ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} ***** BB101 STMT00226 ( 0x3AE[E-] ... 0x3B2 ) N005 ( 3, 4) [001054] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001053] D------N--- +--* LCL_VAR int V27 loc23 d:4 $VN.Void N003 ( 3, 4) [001052] ----------- \--* ADD int $727 N001 ( 1, 1) [001050] ----------- +--* LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- \--* CNS_INT int 1 $c1 ***** BB101 STMT00227 ( 0x3B4[E-] ... 0x3B9 ) N017 ( 18, 23) [001060] -A-XGO--R-- * ASG int N016 ( 1, 1) [001059] D------N--- +--* LCL_VAR int V30 loc26 d:4 $VN.Void N015 ( 18, 23) [002741] ---XGO----- \--* COMMA int N004 ( 8, 11) [002733] ---X-O----- +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001056] ----------- | +--* LCL_VAR int V27 loc23 u:4 $727 N003 ( 3, 3) [002732] ---X------- | \--* ARR_LENGTH int N002 ( 1, 1) [001055] ----------- | \--* LCL_VAR ref V26 loc22 u:1 N014 ( 10, 12) [002742] n---GO----- \--* IND int N013 ( 7, 10) [002740] -----O----- \--* ARR_ADDR byref int[] $83 N012 ( 7, 10) [002739] -------N--- \--* ADD byref N007 ( 3, 4) [002738] ----------- +--* ADD byref N005 ( 1, 1) [002730] ----------- | +--* LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- | \--* CNS_INT long 16 $200 N011 ( 4, 6) [002736] ----------- \--* LSH long $3d5 N009 ( 2, 3) [002734] ---------U- +--* CAST long <- uint $3d4 N008 ( 1, 1) [002731] ----------- | \--* LCL_VAR int V27 loc23 u:4 $727 N010 ( 1, 2) [002735] -------N--- \--* CNS_INT long 2 $20a ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ***** BB102 STMT00543 ( ??? ... ??? ) N005 ( 0, 0) [003282] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003280] D------N--- +--* LCL_VAR int V30 loc26 d:3 $VN.Void N003 ( 0, 0) [003281] ----------- \--* PHI int $2a3 N001 ( 0, 0) [003542] ----------- pred BB101 +--* PHI_ARG int V30 loc26 u:4 N002 ( 0, 0) [003531] ----------- pred BB100 \--* PHI_ARG int V30 loc26 u:2 $29d ***** BB102 STMT00541 ( ??? ... ??? ) N005 ( 0, 0) [003276] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003274] D------N--- +--* LCL_VAR int V27 loc23 d:3 $VN.Void N003 ( 0, 0) [003275] ----------- \--* PHI int $2a4 N001 ( 0, 0) [003543] ----------- pred BB101 +--* PHI_ARG int V27 loc23 u:4 $727 N002 ( 0, 0) [003532] ----------- pred BB100 \--* PHI_ARG int V27 loc23 u:2 $29e ***** BB102 STMT00225 ( 0x3BB[E-] ... 0x3C0 ) N005 ( 3, 3) [001049] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [001048] D------N--- +--* LCL_VAR int V28 loc24 d:4 $VN.Void N003 ( 3, 3) [001047] ----------- \--* ADD int $72b N001 ( 1, 1) [001045] ----------- +--* LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- \--* LCL_VAR int V30 loc26 u:3 $2a3 ***** BB102 STMT00218 ( 0x3C2[E-] ... 0x3C6 ) N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [001004] J------N--- \--* GT int $72c N001 ( 1, 1) [001002] ----------- +--* LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- \--* LCL_VAR int V28 loc24 u:4 $72b ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB85,BB89,BB102} succs={BB104,BB112} ***** BB103 STMT00555 ( ??? ... ??? ) N006 ( 0, 0) [003318] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003316] D------N--- +--* LCL_VAR int V20 loc16 d:2 $VN.Void N004 ( 0, 0) [003317] ----------- \--* PHI int $2a5 N001 ( 0, 0) [003533] ----------- pred BB102 +--* PHI_ARG int V20 loc16 u:11 $71f N002 ( 0, 0) [003526] ----------- pred BB89 +--* PHI_ARG int V20 loc16 u:10 $29b N003 ( 0, 0) [003430] ----------- pred BB78 \--* PHI_ARG int V20 loc16 u:1 $c4 ***** BB103 STMT00549 ( ??? ... ??? ) N006 ( 0, 0) [003300] -A------R-- * ASG byref $VN.Void N005 ( 0, 0) [003298] D------N--- +--* LCL_VAR byref V143 tmp103 d:2 $VN.Void N004 ( 0, 0) [003299] ----------- \--* PHI byref $385 N001 ( 0, 0) [003534] ----------- pred BB102 +--* PHI_ARG byref V143 tmp103 u:4 $384 N002 ( 0, 0) [003527] ----------- pred BB89 +--* PHI_ARG byref V143 tmp103 u:3 $381 N003 ( 0, 0) [003431] ----------- pred BB78 \--* PHI_ARG byref V143 tmp103 u:1 $24b ***** BB103 STMT00546 ( ??? ... ??? ) N006 ( 0, 0) [003291] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003289] D------N--- +--* LCL_VAR int V144 tmp104 d:2 $VN.Void N004 ( 0, 0) [003290] ----------- \--* PHI int $2a6 N001 ( 0, 0) [003535] ----------- pred BB102 +--* PHI_ARG int V144 tmp104 u:4 $2a2 N002 ( 0, 0) [003528] ----------- pred BB89 +--* PHI_ARG int V144 tmp104 u:3 $29c N003 ( 0, 0) [003432] ----------- pred BB78 \--* PHI_ARG int V144 tmp104 u:1 $c8 ***** BB103 STMT00047 ( 0x3C8[E-] ... 0x3CE ) N011 ( 19, 14) [000186] ----GO----- * JTRUE void $301 N010 ( 17, 12) [003734] J---GO-N--- \--* AND int N006 ( 10, 7) [000185] ----GO-N--- +--* EQ int N004 ( 5, 4) [000183] n---GO----- | +--* IND bool N003 ( 3, 4) [002744] -------N--- | | \--* ADD byref $247 N001 ( 1, 1) [000182] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- | | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000184] ----------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000929] -------N--- \--* NE int $733 N007 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] ----------- \--* CNS_INT int 0 $c0 ------------ BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} ***** BB104 STMT00198 ( 0x3D0[E-] ... 0x3D2 ) N001 ( 0, 0) [003735] ----------- * NOP void ***** BB104 STMT00199 ( 0x3D4[E-] ... 0x3DA ) N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 N006 ( 6, 6) [000934] J---GO-N--- \--* EQ int N004 ( 4, 3) [000932] n---GO----- +--* IND int N003 ( 3, 4) [002746] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000931] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000933] ----------- \--* CNS_INT int 0 $c0 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} ***** BB106 STMT00367 ( 0x3DC[E-] ... ??? ) N006 ( 4, 3) [001783] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001782] D------N--- +--* LCL_VAR ref V86 tmp46 d:1 $VN.Void N004 ( 4, 3) [001730] ---XG------ \--* IND ref N003 ( 3, 4) [002748] -------N--- \--* ADD byref $259 N001 ( 1, 1) [000937] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- \--* CNS_INT long 40 Fseq[] $20b ***** BB106 STMT00358 ( INL26 @ 0x000[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001734] J------N--- \--* EQ int N001 ( 1, 1) [001732] ----------- +--* LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- \--* CNS_INT ref null $VN.Null ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ***** BB107 STMT00359 ( INL26 @ 0x004[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N006 ( 8, 6) [001738] -A-XG---R-- * ASG int $845 N005 ( 3, 2) [001737] D------N--- +--* LCL_VAR int V87 tmp47 d:1 $VN.Void N004 ( 4, 3) [001736] ---XG------ \--* IND int N003 ( 3, 4) [002750] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000936] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- \--* CNS_INT long 8 $201 ***** BB107 STMT00360 ( INL26 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N012 ( 22, 15) [001743] ---XGO----- * JTRUE void N011 ( 20, 13) [003736] J--XGO-N--- \--* AND int N004 ( 8, 6) [001742] N--X---N-U- +--* NE int N002 ( 3, 3) [001740] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [001739] ----------- | | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] ----------- | \--* CNS_INT int 1 $c1 N010 ( 11, 6) [001752] N---GO-N-U- \--* GE int N005 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N009 ( 4, 3) [001786] n---GO----- \--* IND int N008 ( 3, 4) [002754] -------N--- \--* ADD byref $25b N006 ( 1, 1) [001748] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002753] ----------- \--* CNS_INT long 24 $20c ------------ BB108 [3DC..3DD), preds={BB107} succs={BB112} ***** BB108 STMT00363 ( INL26 @ 0x014[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N001 ( 0, 0) [003737] ----------- * NOP void ***** BB108 STMT00364 ( INL26 @ 0x022[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N005 ( 3, 4) [001759] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001758] D------N--- +--* LCL_VAR byref V88 tmp48 d:1 $VN.Void N003 ( 3, 4) [002760] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002758] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- \--* CNS_INT long 16 $200 ***** BB108 STMT00365 ( INL26 @ ??? ... ??? ) <- INLRT @ 0x3DC[E-] N023 ( 30, 29) [001775] -A-XGO----- * ASG short N015 ( 24, 24) [001769] ---XGO-N--- +--* COMMA short N006 ( 11, 12) [001763] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 3, 2) [001756] ----------- | | +--* LCL_VAR int V87 tmp47 u:1 N005 ( 4, 3) [001762] n---GO----- | | \--* IND int N004 ( 3, 4) [002763] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001761] ----------- | | +--* LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- | | \--* CNS_INT long 8 $201 N014 ( 13, 12) [002764] D--XGO-N--- | \--* IND short N013 ( 10, 10) [001768] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001767] n---GO----- | +--* IND byref N007 ( 1, 1) [001760] ----------- | | \--* LCL_VAR byref V88 tmp48 u:1 (last use) $25c N012 ( 6, 7) [001766] ----------- | \--* LSH long N010 ( 4, 4) [001764] ---------U- | +--* CAST long <- uint N009 ( 3, 2) [001757] ----------- | | \--* LCL_VAR int V87 tmp47 u:1 N011 ( 1, 2) [001765] ----------- | \--* CNS_INT long 1 $204 N022 ( 5, 4) [002775] ----GO-N--- \--* COMMA ushort N016 ( 0, 0) [002768] ----------- +--* NOP void N021 ( 5, 4) [002777] n---GO----- \--* IND ushort N020 ( 1, 1) [002774] -----O----- \--* ARR_ADDR byref ushort[] $84 N019 ( 1, 1) [002772] -------N--- \--* ADD byref N017 ( 1, 1) [002765] ----------- +--* LCL_VAR ref V86 tmp46 u:1 (last use) N018 ( 1, 2) [002771] ----------- \--* CNS_INT long 12 $20d ***** BB108 STMT00366 ( INL26 @ 0x036[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N008 ( 10, 9) [001781] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001780] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002779] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001776] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- | \--* CNS_INT long 8 $201 N003 ( 5, 5) [001779] ----------- \--* ADD int N001 ( 3, 2) [001777] ----------- +--* LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- \--* CNS_INT int 1 $c1 ------------ BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} ***** BB112 STMT00048 ( 0x3E8[E-] ... 0x3E9 ) N003 ( 1, 3) [000189] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000188] D------N--- +--* LCL_VAR int V21 loc17 d:1 $VN.Void N001 ( 1, 2) [002781] ----------- \--* CNS_INT int 0 $c0 ***** BB112 STMT00369 ( 0x3EB[E-] ... ??? ) N005 ( 1, 3) [002788] -A--------- * COMMA void $588 N003 ( 1, 3) [002784] -A------R-- +--* ASG byref $VN.Void N002 ( 1, 1) [002782] D------N--- | +--* LCL_VAR byref V165 tmp125 d:1 $VN.Void N001 ( 1, 1) [003714] ----------- | \--* LCL_VAR byref V180 cse9 u:1 $246 N004 ( 0, 0) [002787] ----------- \--* NOP void $588 ***** BB112 STMT00050 ( 0x3EB[E-] ... ??? ) N003 ( 5, 4) [000196] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000195] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 1) [001792] ----------- \--* LCL_VAR byref V165 tmp125 u:1 $246 ***** BB112 STMT00051 ( 0x3F3[E-] ... 0x3F6 ) N007 ( 2, 4) [000200] -A------R-- * ASG long $VN.Void N006 ( 1, 1) [000199] D------N--- +--* LCL_VAR long V34 loc30 d:1 $VN.Void N005 ( 2, 4) [002793] -A--------- \--* COMMA long $3c4 N003 ( 1, 3) [002790] -A------R-- +--* ASG long $VN.Void N002 ( 1, 1) [002789] D------N--- | +--* LCL_VAR long V169 tmp129 d:1 $VN.Void N001 ( 1, 1) [000197] ----------- | \--* LCL_VAR byref V165 tmp125 u:1 (last use) $246 N004 ( 1, 1) [002791] ----------- \--* LCL_VAR long V169 tmp129 u:1 (last use) $3c4 ***** BB112 STMT00052 ( 0x3F8[E-] ... 0x3FA ) N003 ( 1, 3) [000203] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000202] D------N--- +--* LCL_VAR long V36 loc32 d:1 $VN.Void N001 ( 1, 1) [000201] ----------- \--* LCL_VAR long V17 loc13 u:1 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} ***** BB245 STMT00518 ( ??? ... ??? ) N006 ( 0, 0) [003207] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003205] D------N--- +--* LCL_VAR bool V09 loc5 d:3 $VN.Void N004 ( 0, 0) [003206] ----------- \--* PHI bool $4c6 N001 ( 0, 0) [003456] ----------- pred BB226 +--* PHI_ARG bool V09 loc5 u:4 N002 ( 0, 0) [003444] ----------- pred BB244 +--* PHI_ARG bool V09 loc5 u:3 N003 ( 0, 0) [003433] ----------- pred BB112 \--* PHI_ARG bool V09 loc5 u:2 $4c1 ***** BB245 STMT00517 ( ??? ... ??? ) N006 ( 0, 0) [003204] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003202] D------N--- +--* LCL_VAR bool V21 loc17 d:2 $VN.Void N004 ( 0, 0) [003203] ----------- \--* PHI bool $4c7 N001 ( 0, 0) [003498] ----------- pred BB180 +--* PHI_ARG bool V21 loc17 u:3 N002 ( 0, 0) [003445] ----------- pred BB244 +--* PHI_ARG bool V21 loc17 u:2 N003 ( 0, 0) [003434] ----------- pred BB112 \--* PHI_ARG bool V21 loc17 u:1 $c0 ***** BB245 STMT00516 ( ??? ... ??? ) N006 ( 0, 0) [003201] -A------R-- * ASG long $VN.Void N005 ( 0, 0) [003199] D------N--- +--* LCL_VAR long V36 loc32 d:2 $VN.Void N004 ( 0, 0) [003200] ----------- \--* PHI long $900 N001 ( 0, 0) [003480] ----------- pred BB170 +--* PHI_ARG long V36 loc32 u:4 N002 ( 0, 0) [003446] ----------- pred BB244 +--* PHI_ARG long V36 loc32 u:3 N003 ( 0, 0) [003435] ----------- pred BB112 \--* PHI_ARG long V36 loc32 u:1 ***** BB245 STMT00512 ( ??? ... ??? ) N006 ( 0, 0) [003189] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003187] D------N--- +--* LCL_VAR int V14 loc10 d:2 $VN.Void N004 ( 0, 0) [003188] ----------- \--* PHI int $2ab N001 ( 0, 0) [003481] ----------- pred BB170 +--* PHI_ARG int V14 loc10 u:4 N002 ( 0, 0) [003447] ----------- pred BB244 +--* PHI_ARG int V14 loc10 u:3 N003 ( 0, 0) [003436] ----------- pred BB112 \--* PHI_ARG int V14 loc10 u:1 $296 ***** BB245 STMT00508 ( ??? ... ??? ) N006 ( 0, 0) [003177] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003175] D------N--- +--* LCL_VAR int V20 loc16 d:3 $VN.Void N004 ( 0, 0) [003176] ----------- \--* PHI int $2ac N001 ( 0, 0) [003482] ----------- pred BB170 +--* PHI_ARG int V20 loc16 u:5 N002 ( 0, 0) [003448] ----------- pred BB244 +--* PHI_ARG int V20 loc16 u:4 N003 ( 0, 0) [003437] ----------- pred BB112 \--* PHI_ARG int V20 loc16 u:2 $2a5 ***** BB245 STMT00506 ( ??? ... ??? ) N006 ( 0, 0) [003171] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003169] D------N--- +--* LCL_VAR int V08 loc4 d:2 $VN.Void N004 ( 0, 0) [003170] ----------- \--* PHI int $2ad N001 ( 0, 0) [003483] ----------- pred BB170 +--* PHI_ARG int V08 loc4 u:4 N002 ( 0, 0) [003449] ----------- pred BB244 +--* PHI_ARG int V08 loc4 u:3 N003 ( 0, 0) [003438] ----------- pred BB112 \--* PHI_ARG int V08 loc4 u:1 $297 ***** BB245 STMT00504 ( ??? ... ??? ) N010 ( 0, 0) [003165] -A------R-- * ASG int $VN.Void N009 ( 0, 0) [003163] D------N--- +--* LCL_VAR int V16 loc12 d:4 $VN.Void N008 ( 0, 0) [003164] ----------- \--* PHI int $2ae N001 ( 0, 0) [003477] ----------- pred BB199 +--* PHI_ARG int V16 loc12 u:14 N002 ( 0, 0) [003476] ----------- pred BB197 +--* PHI_ARG int V16 loc12 u:13 N003 ( 0, 0) [003474] ----------- pred BB204 +--* PHI_ARG int V16 loc12 u:12 N004 ( 0, 0) [003457] ----------- pred BB226 +--* PHI_ARG int V16 loc12 u:10 N005 ( 0, 0) [003451] ----------- pred BB239 +--* PHI_ARG int V16 loc12 u:6 N006 ( 0, 0) [003450] ----------- pred BB244 +--* PHI_ARG int V16 loc12 u:5 N007 ( 0, 0) [003439] ----------- pred BB112 \--* PHI_ARG int V16 loc12 u:3 $283 ***** BB245 STMT00054 ( 0x7AA[E-] ... ??? ) N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000209] J------N--- \--* GE int $897 N001 ( 1, 1) [000204] ----------- +--* LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ***** BB246 STMT00065 ( 0x7B5[E-] ... 0x7BC ) N003 ( 1, 3) [000250] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000249] D------N--- +--* LCL_VAR int V49 tmp9 d:1 $VN.Void N001 ( 1, 1) [000243] ----------- \--* LCL_VAR int V16 loc12 u:4 $2ae ***** BB246 STMT00064 ( 0x7B5[E-] ... ??? ) N005 ( 3, 4) [000248] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000247] D------N--- +--* LCL_VAR int V16 loc12 d:5 $VN.Void N003 ( 3, 4) [000246] ----------- \--* ADD int $898 N001 ( 1, 1) [000244] ----------- +--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- \--* CNS_INT int 1 $c1 ***** BB246 STMT00066 ( ??? ... 0x7C4 ) N009 ( 9, 10) [000259] -A-XG---R-- * ASG int $871 N008 ( 1, 1) [000258] D------N--- +--* LCL_VAR int V50 tmp10 d:1 $VN.Void N007 ( 9, 10) [000257] ---XG------ \--* IND ushort N006 ( 6, 8) [000256] -------N--- \--* ADD long $3dd N001 ( 1, 1) [000242] ----------- +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000255] ----------- \--* LSH long $3dc N003 ( 2, 3) [000252] ----------- +--* CAST long <- int $3db N002 ( 1, 1) [000251] ----------- | \--* LCL_VAR int V49 tmp9 u:1 (last use) $2ae N004 ( 1, 2) [000254] ----------- \--* CNS_INT long 1 $204 ***** BB246 STMT00067 ( ??? ... ??? ) N003 ( 1, 3) [000263] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000262] D------N--- +--* LCL_VAR int V18 loc14 d:1 $VN.Void N001 ( 1, 1) [000261] ----------- \--* LCL_VAR int V50 tmp10 u:1 ***** BB246 STMT00068 ( ??? ... 0x7C6 ) N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000265] J------N--- \--* EQ int N001 ( 1, 1) [000260] ----------- +--* LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- \--* CNS_INT int 0 $c0 ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ***** BB247 STMT00069 ( 0x7C8[E-] ... 0x7CC ) N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000269] N------N-U- \--* NE int N001 ( 1, 1) [000267] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- \--* CNS_INT int 59 $d1 ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ***** BB248 STMT00055 ( 0x7D1[E-] ... 0x7D3 ) N003 ( 5, 5) [000214] -A------R-- * ASG byref $VN.Void N002 ( 3, 2) [000213] D------N--- +--* LCL_VAR byref V35 loc31 $VN.Void N001 ( 1, 2) [000212] ----------- \--* CNS_INT long 0 $205 ***** BB248 STMT00056 ( 0x7D5[E-] ... 0x7DB ) N011 ( 19, 14) [000219] ----GO----- * JTRUE void $301 N010 ( 17, 12) [003764] J---GO-N--- \--* AND int N006 ( 10, 7) [000218] ----GO-N--- +--* EQ int N004 ( 5, 4) [000216] n---GO----- | +--* IND bool N003 ( 3, 4) [003148] -------N--- | | \--* ADD byref $247 N001 ( 1, 1) [000215] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- | | \--* CNS_INT long 8 $201 N005 ( 1, 2) [000217] ----------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000223] -------N--- \--* NE int $733 N007 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] ----------- \--* CNS_INT int 0 $c0 ------------ BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} ***** BB249 STMT00058 ( 0x7DD[E-] ... 0x7DF ) N001 ( 0, 0) [003765] ----------- * NOP void ***** BB249 STMT00059 ( 0x7E1[E-] ... 0x7E7 ) N014 ( 21, 15) [000229] ---XGO----- * JTRUE void $301 N013 ( 19, 13) [003766] J--XGO-N--- \--* AND int N006 ( 9, 6) [000228] ----GO-N--- +--* NE int N004 ( 4, 3) [000226] n---GO----- | +--* IND int N003 ( 3, 4) [003150] -------N--- | | \--* ADD byref $24a N001 ( 1, 1) [000225] ----------- | | +--* LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- | | \--* CNS_INT long 4 $207 N005 ( 1, 2) [000227] ----------- | \--* CNS_INT int 0 $c0 N012 ( 9, 6) [000234] ---XG--N--- \--* LE int N010 ( 4, 3) [002539] ---XG------ +--* IND int N009 ( 3, 4) [003152] -------N--- | \--* ADD byref $25a N007 ( 1, 1) [000230] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N008 ( 1, 2) [003151] ----------- | \--* CNS_INT long 8 $201 N011 ( 1, 2) [000233] ----------- \--* CNS_INT int 0 $c0 ------------ BB251 [7E9..7FF), preds={BB249} succs={BB253} ***** BB251 STMT00061 ( 0x7E9[E-] ... ??? ) N001 ( 0, 0) [003767] ----------- * NOP void ***** BB251 STMT00063 ( 0x7F2[E-] ... ??? ) N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void N004 ( 4, 3) [002541] ---XG------ arg3 in x2 +--* IND ref N003 ( 3, 4) [003155] -------N--- | \--* ADD byref $259 N001 ( 1, 1) [000238] ----------- | +--* LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- | \--* CNS_INT long 40 Fseq[] $20b N005 ( 1, 1) [000236] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- r2r cell in x11 +--* CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- arg2 in x1 \--* CNS_INT int 0 $c0 ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} ***** BB253 STMT00057 ( 0x7FF[E-] ... 0x7FF ) N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ------------ BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} ***** BB111 STMT00361 ( INL26 @ 0x040[E-] ... ??? ) <- INLRT @ 0x3DC[E-] N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001744] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- arg2 in x1 +--* LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ***** BB113 STMT00070 ( 0x401[E-] ... 0x404 ) N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000273] J------N--- \--* LE int $89f N001 ( 1, 1) [000271] ----------- +--* LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- \--* CNS_INT int 0 $c0 ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ***** BB114 STMT00176 ( 0x406[E-] ... 0x40A ) N008 ( 15, 11) [000824] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003738] J------N--- \--* AND int N003 ( 6, 4) [000823] -------N--- +--* EQ int N001 ( 1, 1) [000821] ----------- | +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- | \--* CNS_INT int 35 $ea N006 ( 6, 4) [000921] -------N--- \--* EQ int N004 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb ------------ BB115 [40C..418) -> BB135 (cond), preds={BB114} succs={BB117,BB135} ***** BB115 STMT00196 ( 0x40C[E-] ... 0x410 ) N001 ( 0, 0) [003739] ----------- * NOP void ***** BB115 STMT00197 ( 0x412[E-] ... 0x416 ) N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000925] J------N--- \--* EQ int N001 ( 1, 1) [000923] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- \--* CNS_INT int 48 $d8 ------------ BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ***** BB118 STMT00179 ( ??? ... 0x41E ) N003 ( 1, 3) [000836] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000835] D------N--- +--* LCL_VAR byref V60 tmp20 d:1 $VN.Void N001 ( 1, 1) [000829] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 ***** BB118 STMT00178 ( 0x41A[E-] ... 0x41E ) N009 ( 9, 9) [000834] -A-XG------ * JTRUE void $c1a N008 ( 7, 7) [000833] JA-XG--N--- \--* NE int N006 ( 5, 4) [003680] -A-XG------ +--* COMMA int N004 ( 4, 3) [003678] -A-XG---R-- | +--* ASG int $VN.Void N003 ( 1, 1) [003677] D------N--- | | +--* LCL_VAR int V177 cse6 d:1 $VN.Void N002 ( 4, 3) [000831] ---XG------ | | \--* IND ubyte N001 ( 1, 1) [000830] ----------- | | \--* LCL_VAR long V36 loc32 u:7 $904 N005 ( 1, 1) [003679] ----------- | \--* LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- \--* CNS_INT int 0 $c0 ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ***** BB119 STMT00194 ( ??? ... 0x422 ) N003 ( 1, 3) [000914] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000913] D------N--- +--* LCL_VAR byref V62 tmp22 d:3 $VN.Void N001 ( 1, 1) [000838] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB119 STMT00195 ( ??? ... ??? ) N003 ( 1, 3) [000917] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000916] D------N--- +--* LCL_VAR int V63 tmp23 d:3 $VN.Void N001 ( 1, 2) [000912] ----------- \--* CNS_INT int 48 $d8 ------------ BB120 [424..42C), preds={BB118} succs={BB121} ***** BB120 STMT00181 ( ??? ... 0x429 ) N003 ( 1, 3) [000848] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000847] D------N--- +--* LCL_VAR long V61 tmp21 d:1 $VN.Void N001 ( 1, 1) [000840] ----------- \--* LCL_VAR long V36 loc32 u:7 $904 ***** BB120 STMT00180 ( ??? ... ??? ) N005 ( 3, 4) [000846] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000845] D------N--- +--* LCL_VAR long V36 loc32 d:9 $VN.Void N003 ( 3, 4) [000844] ----------- \--* ADD long $adc N001 ( 1, 1) [000841] ----------- +--* LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- \--* CNS_INT long 1 $204 ***** BB120 STMT00182 ( ??? ... 0x42B ) N003 ( 1, 3) [000852] -A------R-- * ASG byref $VN.Void N002 ( 1, 1) [000851] D------N--- +--* LCL_VAR byref V62 tmp22 d:2 $VN.Void N001 ( 1, 1) [000839] ----------- \--* LCL_VAR byref V00 arg0 u:1 (last use) $100 ***** BB120 STMT00183 ( ??? ... ??? ) N003 ( 1, 3) [000855] -A--G---R-- * ASG int $c1a N002 ( 1, 1) [000854] D------N--- +--* LCL_VAR int V63 tmp23 d:2 $VN.Void N001 ( 1, 1) [003681] ----------- \--* LCL_VAR int V177 cse6 u:1 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ***** BB121 STMT00537 ( ??? ... ??? ) N005 ( 0, 0) [003264] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003262] D------N--- +--* LCL_VAR long V36 loc32 d:8 $VN.Void N003 ( 0, 0) [003263] ----------- \--* PHI long $905 N001 ( 0, 0) [003516] ----------- pred BB119 +--* PHI_ARG long V36 loc32 u:7 $904 N002 ( 0, 0) [003513] ----------- pred BB120 \--* PHI_ARG long V36 loc32 u:9 $adc ***** BB121 STMT00536 ( ??? ... ??? ) N005 ( 0, 0) [003261] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003259] D------N--- +--* LCL_VAR int V63 tmp23 d:1 $VN.Void N003 ( 0, 0) [003260] ----------- \--* PHI int $b16 N001 ( 0, 0) [003517] ----------- pred BB119 +--* PHI_ARG int V63 tmp23 u:3 $d8 N002 ( 0, 0) [003514] ----------- pred BB120 \--* PHI_ARG int V63 tmp23 u:2 ***** BB121 STMT00535 ( ??? ... ??? ) N005 ( 0, 0) [003258] -A------R-- * ASG byref $VN.Void N004 ( 0, 0) [003256] D------N--- +--* LCL_VAR byref V62 tmp22 d:1 $VN.Void N003 ( 0, 0) [003257] ----------- \--* PHI byref $100 N001 ( 0, 0) [003518] ----------- pred BB119 +--* PHI_ARG byref V62 tmp22 u:3 $100 N002 ( 0, 0) [003515] ----------- pred BB120 \--* PHI_ARG byref V62 tmp22 u:2 $100 ***** BB121 STMT00377 ( ??? ... ??? ) N004 ( 2, 3) [001836] -A------R-- * ASG ushort $VN.Void N003 ( 1, 1) [001835] D------N--- +--* LCL_VAR int V92 tmp52 d:1 $VN.Void N002 ( 2, 3) [001796] ----------- \--* CAST int <- ushort <- int $c75 N001 ( 1, 1) [000858] ----------- \--* LCL_VAR int V63 tmp23 u:1 (last use) $b16 ***** BB121 STMT00370 ( INL29 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [001799] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001798] D------N--- +--* LCL_VAR int V91 tmp51 d:1 $VN.Void N004 ( 4, 3) [001797] ---XG------ \--* IND int N003 ( 3, 4) [002795] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000857] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- \--* CNS_INT long 8 $201 ***** BB121 STMT00372 ( INL29 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001805] N---GO-N-U- \--* GE int N001 ( 1, 1) [001800] ----------- +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001839] n---GO----- \--* IND int N004 ( 3, 4) [002799] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001801] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- \--* CNS_INT long 24 $20c ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ***** BB122 STMT00374 ( INL29 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [001815] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001814] D------N--- +--* LCL_VAR byref V93 tmp53 d:1 $VN.Void N003 ( 3, 4) [002805] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002803] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- \--* CNS_INT long 16 $200 ***** BB122 STMT00375 ( INL29 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [001828] -A-XGO----- * ASG short N015 ( 20, 22) [001825] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001819] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001812] ----------- | | +--* LCL_VAR int V91 tmp51 u:1 N005 ( 4, 3) [001818] n---GO----- | | \--* IND int N004 ( 3, 4) [002808] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001817] ----------- | | +--* LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002809] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001824] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001823] n---GO----- | +--* IND byref N007 ( 1, 1) [001816] ----------- | | \--* LCL_VAR byref V93 tmp53 u:1 (last use) $25c N012 ( 4, 6) [001822] ----------- | \--* LSH long N010 ( 2, 3) [001820] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001813] ----------- | | \--* LCL_VAR int V91 tmp51 u:1 N011 ( 1, 2) [001821] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001826] ----------- \--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 ***** BB122 STMT00376 ( INL29 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [001834] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001833] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002811] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001829] ----------- | +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001832] ----------- \--* ADD int N001 ( 1, 1) [001830] ----------- +--* LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- \--* CNS_INT int 1 $c1 ------------ BB123 [000..000), preds={BB121} succs={BB124} ***** BB123 STMT00373 ( INL29 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001807] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- arg2 in x1 +--* LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ***** BB124 STMT00185 ( 0x431[E-] ... ??? ) N008 ( 15, 11) [000863] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003740] J------N--- \--* AND int N003 ( 6, 4) [000862] -------N--- +--* EQ int $70a N001 ( 1, 1) [000860] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000876] -------N--- \--* LE int $d03 N004 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] ----------- \--* CNS_INT int 1 $c1 ------------ BB125 [435..43F) -> BB134 (cond), preds={BB124} succs={BB127,BB134} ***** BB125 STMT00188 ( 0x435[E-] ... 0x438 ) N001 ( 0, 0) [003741] ----------- * NOP void ***** BB125 STMT00189 ( 0x43A[E-] ... 0x43D ) N020 ( 30, 30) [000881] ---XGO----- * JTRUE void $VN.Void N019 ( 28, 28) [003742] J--XGO-N--- \--* AND int N015 ( 21, 23) [000900] N--XGO-N-U- +--* NE int N013 ( 16, 21) [000899] ---XGO----- | +--* ADD int N011 ( 14, 18) [000896] ---XGO----- | | +--* COMMA int N003 ( 6, 9) [000890] ---X-O----- | | | +--* BOUNDS_CHECK_Rng void $c31 N001 ( 1, 1) [000885] ----------- | | | | +--* LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- | | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002813] ---XGO----- | | | \--* IND int N009 ( 6, 8) [000895] -----O-N--- | | | \--* ADD byref $a6b N004 ( 1, 1) [000894] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] ----------- | | | \--* LSH long $ae3 N006 ( 2, 3) [000891] ---------U- | | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] ----------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] ----------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- | \--* LCL_VAR int V08 loc4 u:5 $b15 N018 ( 6, 4) [000880] -------N--- \--* LT int $d04 N016 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] ----------- \--* CNS_INT int 0 $c0 ------------ BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} ***** BB127 STMT00190 ( 0x43F[E-] ... 0x44D ) N001 ( 0, 0) [003743] ----------- * NOP void ***** BB127 STMT00388 ( 0x44F[E-] ... ??? ) N006 ( 4, 3) [001896] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001895] D------N--- +--* LCL_VAR ref V95 tmp55 d:1 $VN.Void N004 ( 4, 3) [001843] ---XG------ \--* IND ref N003 ( 3, 4) [002815] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000903] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB127 STMT00379 ( INL32 @ 0x000[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001847] J------N--- \--* EQ int N001 ( 1, 1) [001845] ----------- +--* LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- \--* CNS_INT ref null $VN.Null ------------ BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} ***** BB129 STMT00380 ( INL32 @ 0x004[E-] ... ??? ) <- INLRT @ 0x44F[E-] N006 ( 4, 3) [001851] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001850] D------N--- +--* LCL_VAR int V96 tmp56 d:1 $VN.Void N004 ( 4, 3) [001849] n---GO----- \--* IND int N003 ( 3, 4) [002817] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000902] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- \--* CNS_INT long 8 $201 ***** BB129 STMT00381 ( INL32 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x44F[E-] N016 ( 21, 15) [001856] -A-XGO----- * JTRUE void N015 ( 19, 13) [003744] JA-XGO-N--- \--* AND int N008 ( 9, 7) [001855] NA-X---N-U- +--* NE int N006 ( 4, 4) [003718] -A-X------- | +--* COMMA int N004 ( 3, 3) [003716] -A-X----R-- | | +--* ASG int $VN.Void N003 ( 1, 1) [003715] D------N--- | | | +--* LCL_VAR int V181 cse10 d:1 $VN.Void N002 ( 3, 3) [001853] ---X------- | | | \--* ARR_LENGTH int N001 ( 1, 1) [001852] ----------- | | | \--* LCL_VAR ref V95 tmp55 u:1 N005 ( 1, 1) [003717] ----------- | | \--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- | \--* CNS_INT int 1 $c1 N014 ( 9, 5) [001865] N---GO-N-U- \--* GE int N009 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N013 ( 4, 3) [001899] n---GO----- \--* IND int N012 ( 3, 4) [002821] -------N--- \--* ADD byref $25b N010 ( 1, 1) [001861] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N011 ( 1, 2) [002820] ----------- \--* CNS_INT long 24 $20c ------------ BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} ***** BB130 STMT00384 ( INL32 @ 0x014[E-] ... ??? ) <- INLRT @ 0x44F[E-] N001 ( 0, 0) [003745] ----------- * NOP void ***** BB130 STMT00385 ( INL32 @ 0x022[E-] ... ??? ) <- INLRT @ 0x44F[E-] N005 ( 3, 4) [001872] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001871] D------N--- +--* LCL_VAR byref V97 tmp57 d:1 $VN.Void N003 ( 3, 4) [002827] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002825] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- \--* CNS_INT long 16 $200 ***** BB130 STMT00386 ( INL32 @ ??? ... ??? ) <- INLRT @ 0x44F[E-] N025 ( 32, 37) [001888] -A-XGO----- * ASG short N015 ( 20, 22) [001882] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001876] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001869] ----------- | | +--* LCL_VAR int V96 tmp56 u:1 N005 ( 4, 3) [001875] n---GO----- | | \--* IND int N004 ( 3, 4) [002830] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001874] ----------- | | +--* LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002831] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001881] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001880] n---GO----- | +--* IND byref N007 ( 1, 1) [001873] ----------- | | \--* LCL_VAR byref V97 tmp57 u:1 (last use) $25c N012 ( 4, 6) [001879] ----------- | \--* LSH long N010 ( 2, 3) [001877] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001870] ----------- | | \--* LCL_VAR int V96 tmp56 u:1 N011 ( 1, 2) [001878] ----------- | \--* CNS_INT long 1 $204 N024 ( 11, 14) [002842] ---XGO----- \--* COMMA ushort N018 ( 6, 10) [002835] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001884] ----------- | +--* CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- | \--* LCL_VAR int V181 cse10 u:1 N023 ( 5, 4) [002844] n---GO----- \--* IND ushort N022 ( 1, 1) [002841] -----O----- \--* ARR_ADDR byref ushort[] $89 N021 ( 1, 1) [002839] -------N--- \--* ADD byref N019 ( 1, 1) [002832] ----------- +--* LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- \--* CNS_INT long 12 $20d ***** BB130 STMT00387 ( INL32 @ 0x036[E-] ... ??? ) <- INLRT @ 0x44F[E-] N008 ( 8, 8) [001894] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001893] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002846] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001889] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001892] ----------- \--* ADD int N001 ( 1, 1) [001890] ----------- +--* LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- \--* CNS_INT int 1 $c1 ------------ BB132 [44F..450), preds={BB129} succs={BB133} ***** BB132 STMT00382 ( INL32 @ 0x040[E-] ... ??? ) <- INLRT @ 0x44F[E-] N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001857] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- arg2 in x1 +--* LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} ***** BB133 STMT00193 ( 0x45B[E-] ... ??? ) N005 ( 3, 4) [000911] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000910] D------N--- +--* LCL_VAR int V20 loc16 d:9 $VN.Void N003 ( 3, 4) [000909] ----------- \--* ADD int $d27 N001 ( 1, 1) [000907] ----------- +--* LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- \--* CNS_INT int -1 $c4 ------------ BB134 [461..46D), preds={BB124,BB125,BB133} succs={BB135} ***** BB134 STMT00532 ( ??? ... ??? ) N005 ( 0, 0) [003249] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003247] D------N--- +--* LCL_VAR int V20 loc16 d:8 $VN.Void N003 ( 0, 0) [003248] ----------- \--* PHI int $b1e N001 ( 0, 0) [003512] ----------- pred BB133 +--* PHI_ARG int V20 loc16 u:9 $d27 N002 ( 0, 0) [003507] ----------- pred BB124 \--* PHI_ARG int V20 loc16 u:7 $b13 ***** BB134 STMT00186 ( 0x461[E-] ... 0x465 ) N005 ( 3, 4) [000868] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000867] D------N--- +--* LCL_VAR int V08 loc4 d:6 $VN.Void N003 ( 3, 4) [000866] ----------- \--* ADD int $d29 N001 ( 1, 1) [000864] ----------- +--* LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- \--* CNS_INT int -1 $c4 ***** BB134 STMT00187 ( 0x467[E-] ... 0x46B ) N005 ( 3, 4) [000873] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000872] D------N--- +--* LCL_VAR int V14 loc10 d:7 $VN.Void N003 ( 3, 4) [000871] ----------- \--* ADD int $d2a N001 ( 1, 1) [000869] ----------- +--* LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- \--* CNS_INT int -1 $c4 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB134} succs={BB136,BB118} ***** BB135 STMT00538 ( ??? ... ??? ) N005 ( 0, 0) [003267] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003265] D------N--- +--* LCL_VAR long V36 loc32 d:7 $VN.Void N003 ( 0, 0) [003266] ----------- \--* PHI long $904 N001 ( 0, 0) [003508] ----------- pred BB134 +--* PHI_ARG long V36 loc32 u:8 N002 ( 0, 0) [003499] ----------- pred BB114 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB135 STMT00533 ( ??? ... ??? ) N005 ( 0, 0) [003252] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003250] D------N--- +--* LCL_VAR int V20 loc16 d:7 $VN.Void N003 ( 0, 0) [003251] ----------- \--* PHI int $b13 N001 ( 0, 0) [003509] ----------- pred BB134 +--* PHI_ARG int V20 loc16 u:8 N002 ( 0, 0) [003500] ----------- pred BB114 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB135 STMT00530 ( ??? ... ??? ) N005 ( 0, 0) [003243] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003241] D------N--- +--* LCL_VAR int V14 loc10 d:6 $VN.Void N003 ( 0, 0) [003242] ----------- \--* PHI int $b14 N001 ( 0, 0) [003510] ----------- pred BB134 +--* PHI_ARG int V14 loc10 u:7 N002 ( 0, 0) [003501] ----------- pred BB114 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB135 STMT00528 ( ??? ... ??? ) N005 ( 0, 0) [003237] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003235] D------N--- +--* LCL_VAR int V08 loc4 d:5 $VN.Void N003 ( 0, 0) [003236] ----------- \--* PHI int $b15 N001 ( 0, 0) [003511] ----------- pred BB134 +--* PHI_ARG int V08 loc4 u:6 N002 ( 0, 0) [003502] ----------- pred BB114 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB135 STMT00177 ( 0x46D[E-] ... 0x470 ) N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000827] J------N--- \--* GT int $c6e N001 ( 1, 1) [000825] ----------- +--* LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- \--* CNS_INT int 0 $c0 ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ***** BB136 STMT00539 ( ??? ... ??? ) N005 ( 0, 0) [003270] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003268] D------N--- +--* LCL_VAR long V36 loc32 d:3 $VN.Void N003 ( 0, 0) [003269] ----------- \--* PHI long $901 N001 ( 0, 0) [003503] ----------- pred BB135 +--* PHI_ARG long V36 loc32 u:7 N002 ( 0, 0) [003440] ----------- pred BB113 \--* PHI_ARG long V36 loc32 u:2 $900 ***** BB136 STMT00534 ( ??? ... ??? ) N005 ( 0, 0) [003255] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003253] D------N--- +--* LCL_VAR int V20 loc16 d:4 $VN.Void N003 ( 0, 0) [003254] ----------- \--* PHI int $2b3 N001 ( 0, 0) [003504] ----------- pred BB135 +--* PHI_ARG int V20 loc16 u:7 N002 ( 0, 0) [003441] ----------- pred BB113 \--* PHI_ARG int V20 loc16 u:3 $2ac ***** BB136 STMT00531 ( ??? ... ??? ) N005 ( 0, 0) [003246] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003244] D------N--- +--* LCL_VAR int V14 loc10 d:3 $VN.Void N003 ( 0, 0) [003245] ----------- \--* PHI int $2b4 N001 ( 0, 0) [003505] ----------- pred BB135 +--* PHI_ARG int V14 loc10 u:6 N002 ( 0, 0) [003442] ----------- pred BB113 \--* PHI_ARG int V14 loc10 u:2 $2ab ***** BB136 STMT00529 ( ??? ... ??? ) N005 ( 0, 0) [003240] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003238] D------N--- +--* LCL_VAR int V08 loc4 d:3 $VN.Void N003 ( 0, 0) [003239] ----------- \--* PHI int $2b5 N001 ( 0, 0) [003506] ----------- pred BB135 +--* PHI_ARG int V08 loc4 u:5 N002 ( 0, 0) [003443] ----------- pred BB113 \--* PHI_ARG int V08 loc4 u:2 $2ad ***** BB136 STMT00071 ( 0x472[E-] ... 0x476 ) N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000277] N------N-U- \--* GT int N001 ( 1, 1) [000275] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- \--* CNS_INT int 69 $d2 ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} ***** BB137 STMT00129 ( 0x478[E-] ... 0x47D ) N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000595] ----------- \--* ADD int N001 ( 1, 1) [000593] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- \--* CNS_INT int -34 $d6 ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} ***** BB138 STMT00130 ( 0x49A[E-] ... 0x49F ) N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void N003 ( 3, 4) [000599] ----------- \--* ADD int N001 ( 1, 1) [000597] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- \--* CNS_INT int -44 $d7 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ***** BB139 STMT00131 ( 0x4B8[E-] ... 0x4BC ) N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000603] J------N--- \--* EQ int N001 ( 1, 1) [000601] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- \--* CNS_INT int 69 $d2 ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ***** BB141 STMT00072 ( 0x4C6[E-] ... 0x4CA ) N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000281] J------N--- \--* EQ int N001 ( 1, 1) [000279] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- \--* CNS_INT int 92 $d3 ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ***** BB142 STMT00079 ( 0x4CF[E-] ... 0x4D3 ) N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000321] J------N--- \--* EQ int N001 ( 1, 1) [000319] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- \--* CNS_INT int 101 $d4 ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ***** BB143 STMT00125 ( 0x4D8[E-] ... 0x4DF ) N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void N003 ( 3, 6) [000583] J------N--- \--* NE int N001 ( 1, 1) [000581] ----------- +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- \--* CNS_INT int 0x2030 $d5 ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ***** BB144 STMT00429 ( 0x598[E-] ... ??? ) N006 ( 4, 3) [002119] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002118] D------N--- +--* LCL_VAR ref V110 tmp70 d:1 $VN.Void N004 ( 4, 3) [002066] ---XG------ \--* IND ref N003 ( 3, 4) [002849] -------N--- \--* ADD byref $26c N001 ( 1, 1) [000586] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- \--* CNS_INT long 136 Fseq[] $20e ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} ***** BB145 STMT00141 ( 0x4E9[E-] ... 0x4EC ) N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000641] J------N--- \--* GE int $9ff N001 ( 1, 1) [000639] ----------- +--* LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- \--* CNS_INT int 0 $c0 ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ***** BB146 STMT00160 ( 0x4EE[E-] ... 0x4F2 ) N005 ( 3, 4) [000735] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000734] D------N--- +--* LCL_VAR int V14 loc10 d:5 $VN.Void N003 ( 3, 4) [000733] ----------- \--* ADD int $a88 N001 ( 1, 1) [000731] ----------- +--* LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- \--* CNS_INT int 1 $c1 ***** BB146 STMT00161 ( 0x4F4[E-] ... 0x4F7 ) N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000738] J------N--- \--* LE int $a89 N001 ( 1, 1) [000736] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- \--* LCL_VAR int V06 loc2 u:3 $292 ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ***** BB147 STMT00164 ( 0x4F9[E-] ... 0x4FA ) N003 ( 1, 3) [000749] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000748] D------N--- +--* LCL_VAR int V58 tmp18 d:3 $VN.Void N001 ( 1, 2) [000747] ----------- \--* CNS_INT int 0 $c0 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} ***** BB148 STMT00162 ( 0x4FC[E-] ... 0x4FC ) N003 ( 1, 3) [000742] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000741] D------N--- +--* LCL_VAR int V58 tmp18 d:2 $VN.Void N001 ( 1, 2) [000740] ----------- \--* CNS_INT int 48 $d8 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ***** BB149 STMT00510 ( ??? ... ??? ) N005 ( 0, 0) [003183] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003181] D------N--- +--* LCL_VAR int V58 tmp18 d:1 $VN.Void N003 ( 0, 0) [003182] ----------- \--* PHI int $2bd N001 ( 0, 0) [003497] ----------- pred BB147 +--* PHI_ARG int V58 tmp18 u:3 $c0 N002 ( 0, 0) [003496] ----------- pred BB148 \--* PHI_ARG int V58 tmp18 u:2 $d8 ***** BB149 STMT00163 ( ??? ... 0x4FE ) N004 ( 2, 3) [000746] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000745] D------N--- +--* LCL_VAR int V18 loc14 d:4 $VN.Void N002 ( 2, 3) [002850] ----------- \--* CAST int <- ushort <- int $a8a N001 ( 1, 1) [000744] ----------- \--* LCL_VAR int V58 tmp18 u:1 (last use) $2bd ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ***** BB150 STMT00142 ( 0x502[E-] ... 0x505 ) N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 N004 ( 6, 6) [000646] J--XG--N--- \--* NE int N002 ( 4, 3) [000644] ---XG------ +--* IND ubyte N001 ( 1, 1) [000643] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N003 ( 1, 2) [000645] ----------- \--* CNS_INT int 0 $c0 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ***** BB151 STMT00157 ( 0x507[E-] ... 0x50A ) N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000721] J------N--- \--* GT int $a86 N001 ( 1, 1) [000719] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- \--* LCL_VAR int V07 loc3 u:3 $293 ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ***** BB152 STMT00159 ( 0x50C[E-] ... 0x50D ) N003 ( 1, 3) [000729] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000728] D------N--- +--* LCL_VAR int V57 tmp17 d:4 $VN.Void N001 ( 1, 2) [000727] ----------- \--* CNS_INT int 0 $c0 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ***** BB153 STMT00158 ( 0x50F[E-] ... 0x511 ) N003 ( 1, 3) [000725] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000724] D------N--- +--* LCL_VAR int V57 tmp17 d:3 $VN.Void N001 ( 1, 2) [000723] ----------- \--* CNS_INT int 48 $d8 ------------ BB154 [513..51B), preds={BB150} succs={BB155} ***** BB154 STMT00144 ( 0x513[E-] ... 0x518 ) N003 ( 1, 3) [000656] -A------R-- * ASG long $VN.Void N002 ( 1, 1) [000655] D------N--- +--* LCL_VAR long V56 tmp16 d:1 $VN.Void N001 ( 1, 1) [000648] ----------- \--* LCL_VAR long V36 loc32 u:3 $901 ***** BB154 STMT00143 ( 0x513[E-] ... ??? ) N005 ( 3, 4) [000654] -A------R-- * ASG long $VN.Void N004 ( 1, 1) [000653] D------N--- +--* LCL_VAR long V36 loc32 d:6 $VN.Void N003 ( 3, 4) [000652] ----------- \--* ADD long $3fb N001 ( 1, 1) [000649] ----------- +--* LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- \--* CNS_INT long 1 $204 ***** BB154 STMT00145 ( ??? ... 0x51A ) N004 ( 4, 3) [000660] -A-XG---R-- * ASG int $a27 N003 ( 1, 1) [000659] D------N--- +--* LCL_VAR int V57 tmp17 d:2 $VN.Void N002 ( 4, 3) [000658] ---XG------ \--* IND ubyte N001 ( 1, 1) [000657] ----------- \--* LCL_VAR long V56 tmp16 u:1 (last use) $901 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ***** BB155 STMT00514 ( ??? ... ??? ) N005 ( 0, 0) [003195] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003193] D------N--- +--* LCL_VAR long V36 loc32 d:5 $VN.Void N003 ( 0, 0) [003194] ----------- \--* PHI long $902 N001 ( 0, 0) [003490] ----------- pred BB153 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003488] ----------- pred BB154 \--* PHI_ARG long V36 loc32 u:6 $3fb ***** BB155 STMT00513 ( ??? ... ??? ) N006 ( 0, 0) [003192] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003190] D------N--- +--* LCL_VAR int V57 tmp17 d:1 $VN.Void N004 ( 0, 0) [003191] ----------- \--* PHI int $2bc N001 ( 0, 0) [003492] ----------- pred BB152 +--* PHI_ARG int V57 tmp17 u:4 $c0 N002 ( 0, 0) [003491] ----------- pred BB153 +--* PHI_ARG int V57 tmp17 u:3 $d8 N003 ( 0, 0) [003489] ----------- pred BB154 \--* PHI_ARG int V57 tmp17 u:2 ***** BB155 STMT00146 ( ??? ... 0x51B ) N004 ( 2, 3) [000664] -A------R-- * ASG int $VN.Void N003 ( 1, 1) [000663] D------N--- +--* LCL_VAR int V18 loc14 d:3 $VN.Void N002 ( 2, 3) [002851] ----------- \--* CAST int <- ushort <- int $a87 N001 ( 1, 1) [000662] ----------- \--* LCL_VAR int V57 tmp17 u:1 (last use) $2bc ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ***** BB156 STMT00515 ( ??? ... ??? ) N005 ( 0, 0) [003198] -A------R-- * ASG long $VN.Void N004 ( 0, 0) [003196] D------N--- +--* LCL_VAR long V36 loc32 d:4 $VN.Void N003 ( 0, 0) [003197] ----------- \--* PHI long $903 N001 ( 0, 0) [003493] ----------- pred BB149 +--* PHI_ARG long V36 loc32 u:3 $901 N002 ( 0, 0) [003485] ----------- pred BB155 \--* PHI_ARG long V36 loc32 u:5 $902 ***** BB156 STMT00511 ( ??? ... ??? ) N005 ( 0, 0) [003186] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003184] D------N--- +--* LCL_VAR int V14 loc10 d:4 $VN.Void N003 ( 0, 0) [003185] ----------- \--* PHI int $2be N001 ( 0, 0) [003494] ----------- pred BB149 +--* PHI_ARG int V14 loc10 u:5 $a88 N002 ( 0, 0) [003486] ----------- pred BB155 \--* PHI_ARG int V14 loc10 u:3 $2b4 ***** BB156 STMT00509 ( ??? ... ??? ) N005 ( 0, 0) [003180] -A------R-- * ASG ushort $VN.Void N004 ( 0, 0) [003178] D------N--- +--* LCL_VAR ushort V18 loc14 d:2 $VN.Void N003 ( 0, 0) [003179] ----------- \--* PHI ushort $5c9 N001 ( 0, 0) [003495] ----------- pred BB149 +--* PHI_ARG ushort V18 loc14 u:4 $a8a N002 ( 0, 0) [003487] ----------- pred BB155 \--* PHI_ARG ushort V18 loc14 u:3 $a87 ***** BB156 STMT00147 ( 0x51D[E-] ... 0x51F ) N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000667] J------N--- \--* EQ int $a8b N001 ( 1, 1) [000665] ----------- +--* LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- \--* CNS_INT int 0 $c0 ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ***** BB157 STMT00390 ( INL34 @ 0x000[E-] ... ??? ) <- INLRT @ 0x521[E-] N006 ( 4, 3) [001905] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [001904] D------N--- +--* LCL_VAR int V99 tmp59 d:1 $VN.Void N004 ( 4, 3) [001903] ---XG------ \--* IND int N003 ( 3, 4) [002853] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000674] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- \--* CNS_INT long 8 $201 ***** BB157 STMT00392 ( INL34 @ 0x007[E-] ... ??? ) <- INLRT @ 0x521[E-] N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 N006 ( 6, 5) [001911] N---GO-N-U- \--* GE int N001 ( 1, 1) [001906] ----------- +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001942] n---GO----- \--* IND int N004 ( 3, 4) [002857] -------N--- \--* ADD byref $25b N002 ( 1, 1) [001907] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- \--* CNS_INT long 24 $20c ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ***** BB158 STMT00394 ( INL34 @ 0x015[E-] ... ??? ) <- INLRT @ 0x521[E-] N005 ( 3, 4) [001920] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001919] D------N--- +--* LCL_VAR byref V100 tmp60 d:1 $VN.Void N003 ( 3, 4) [002863] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002861] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- \--* CNS_INT long 16 $200 ***** BB158 STMT00395 ( INL34 @ ??? ... ??? ) <- INLRT @ 0x521[E-] N017 ( 22, 24) [001933] -A-XGO----- * ASG short N015 ( 20, 22) [001930] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001924] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001917] ----------- | | +--* LCL_VAR int V99 tmp59 u:1 N005 ( 4, 3) [001923] n---GO----- | | \--* IND int N004 ( 3, 4) [002866] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001922] ----------- | | +--* LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002867] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001929] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001928] n---GO----- | +--* IND byref N007 ( 1, 1) [001921] ----------- | | \--* LCL_VAR byref V100 tmp60 u:1 (last use) $25c N012 ( 4, 6) [001927] ----------- | \--* LSH long N010 ( 2, 3) [001925] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001918] ----------- | | \--* LCL_VAR int V99 tmp59 u:1 N011 ( 1, 2) [001926] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [001931] ----------- \--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 ***** BB158 STMT00396 ( INL34 @ 0x023[E-] ... ??? ) <- INLRT @ 0x521[E-] N008 ( 8, 8) [001939] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001938] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002869] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001934] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001937] ----------- \--* ADD int N001 ( 1, 1) [001935] ----------- +--* LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- \--* CNS_INT int 1 $c1 ------------ BB159 [521..522), preds={BB157} succs={BB160} ***** BB159 STMT00393 ( INL34 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x521[E-] N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [001913] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ***** BB160 STMT00150 ( 0x529[E-] ... ??? ) N008 ( 15, 11) [000680] ----------- * JTRUE void $VN.Void N007 ( 13, 9) [003746] J------N--- \--* AND int N003 ( 6, 4) [000679] -------N--- +--* EQ int $70a N001 ( 1, 1) [000677] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000683] -------N--- \--* LE int $a93 N004 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] ----------- \--* CNS_INT int 1 $c1 ------------ BB161 [52D..537) -> BB170 (cond), preds={BB160} succs={BB163,BB170} ***** BB161 STMT00151 ( 0x52D[E-] ... 0x530 ) N001 ( 0, 0) [003747] ----------- * NOP void ***** BB161 STMT00152 ( 0x532[E-] ... 0x535 ) N020 ( 30, 30) [000688] ---XGO----- * JTRUE void $VN.Void N019 ( 28, 28) [003748] J--XGO-N--- \--* AND int N015 ( 21, 23) [000707] N--XGO-N-U- +--* NE int N013 ( 16, 21) [000706] ---XGO----- | +--* ADD int N011 ( 14, 18) [000703] ---XGO----- | | +--* COMMA int N003 ( 6, 9) [000697] ---X-O----- | | | +--* BOUNDS_CHECK_Rng void $a34 N001 ( 1, 1) [000692] ----------- | | | | +--* LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- | | | | \--* LCL_VAR int V144 tmp104 u:2 $2a6 N010 ( 8, 9) [002871] ---XGO----- | | | \--* IND int N009 ( 6, 8) [000702] -----O-N--- | | | \--* ADD byref $a44 N004 ( 1, 1) [000701] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] ----------- | | | \--* LSH long $ac1 N006 ( 2, 3) [000698] ---------U- | | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] ----------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] ----------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- | \--* LCL_VAR int V08 loc4 u:3 $2b5 N018 ( 6, 4) [000687] -------N--- \--* LT int $a94 N016 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] ----------- \--* CNS_INT int 0 $c0 ------------ BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} ***** BB163 STMT00153 ( 0x537[E-] ... 0x545 ) N001 ( 0, 0) [003749] ----------- * NOP void ***** BB163 STMT00407 ( 0x547[E-] ... ??? ) N006 ( 4, 3) [001999] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [001998] D------N--- +--* LCL_VAR ref V102 tmp62 d:1 $VN.Void N004 ( 4, 3) [001946] ---XG------ \--* IND ref N003 ( 3, 4) [002873] -------N--- \--* ADD byref $24c N001 ( 1, 1) [000710] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- \--* CNS_INT long 56 Fseq[] $209 ***** BB163 STMT00398 ( INL37 @ 0x000[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [001950] J------N--- \--* EQ int N001 ( 1, 1) [001948] ----------- +--* LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- \--* CNS_INT ref null $VN.Null ------------ BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} ***** BB165 STMT00399 ( INL37 @ 0x004[E-] ... ??? ) <- INLRT @ 0x547[E-] N006 ( 4, 3) [001954] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [001953] D------N--- +--* LCL_VAR int V103 tmp63 d:1 $VN.Void N004 ( 4, 3) [001952] n---GO----- \--* IND int N003 ( 3, 4) [002875] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000709] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- \--* CNS_INT long 8 $201 ***** BB165 STMT00400 ( INL37 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x547[E-] N012 ( 20, 14) [001959] ---XGO----- * JTRUE void N011 ( 18, 12) [003750] J--XGO-N--- \--* AND int N004 ( 8, 6) [001958] N--X---N-U- +--* NE int N002 ( 3, 3) [001956] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [001955] ----------- | | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [001968] N---GO-N-U- \--* GE int N005 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N009 ( 4, 3) [002002] n---GO----- \--* IND int N008 ( 3, 4) [002879] -------N--- \--* ADD byref $25b N006 ( 1, 1) [001964] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002878] ----------- \--* CNS_INT long 24 $20c ------------ BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} ***** BB166 STMT00403 ( INL37 @ 0x014[E-] ... ??? ) <- INLRT @ 0x547[E-] N001 ( 0, 0) [003751] ----------- * NOP void ***** BB166 STMT00404 ( INL37 @ 0x022[E-] ... ??? ) <- INLRT @ 0x547[E-] N005 ( 3, 4) [001975] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [001974] D------N--- +--* LCL_VAR byref V104 tmp64 d:1 $VN.Void N003 ( 3, 4) [002885] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002883] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- \--* CNS_INT long 16 $200 ***** BB166 STMT00405 ( INL37 @ ??? ... ??? ) <- INLRT @ 0x547[E-] N026 ( 34, 39) [001991] -A-XGO----- * ASG short N015 ( 20, 22) [001985] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [001979] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [001972] ----------- | | +--* LCL_VAR int V103 tmp63 u:1 N005 ( 4, 3) [001978] n---GO----- | | \--* IND int N004 ( 3, 4) [002888] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [001977] ----------- | | +--* LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002889] D--XGO-N--- | \--* IND short N013 ( 8, 9) [001984] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [001983] n---GO----- | +--* IND byref N007 ( 1, 1) [001976] ----------- | | \--* LCL_VAR byref V104 tmp64 u:1 (last use) $25c N012 ( 4, 6) [001982] ----------- | \--* LSH long N010 ( 2, 3) [001980] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [001973] ----------- | | \--* LCL_VAR int V103 tmp63 u:1 N011 ( 1, 2) [001981] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002900] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002893] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [001987] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002892] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [001986] ----------- | \--* LCL_VAR ref V102 tmp62 u:1 N024 ( 5, 4) [002902] n---GO----- \--* IND ushort N023 ( 1, 1) [002899] -----O----- \--* ARR_ADDR byref ushort[] $86 N022 ( 1, 1) [002897] -------N--- \--* ADD byref N020 ( 1, 1) [002890] ----------- +--* LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- \--* CNS_INT long 12 $20d ***** BB166 STMT00406 ( INL37 @ 0x036[E-] ... ??? ) <- INLRT @ 0x547[E-] N008 ( 8, 8) [001997] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [001996] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002904] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [001992] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [001995] ----------- \--* ADD int N001 ( 1, 1) [001993] ----------- +--* LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- \--* CNS_INT int 1 $c1 ------------ BB168 [547..548), preds={BB165} succs={BB169} ***** BB168 STMT00401 ( INL37 @ 0x040[E-] ... ??? ) <- INLRT @ 0x547[E-] N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [001960] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- arg2 in x1 +--* LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} ***** BB169 STMT00156 ( 0x553[E-] ... ??? ) N005 ( 3, 4) [000718] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000717] D------N--- +--* LCL_VAR int V20 loc16 d:6 $VN.Void N003 ( 3, 4) [000716] ----------- \--* ADD int $ab7 N001 ( 1, 1) [000714] ----------- +--* LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- \--* CNS_INT int -1 $c4 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB169} succs={BB245} ***** BB170 STMT00507 ( ??? ... ??? ) N005 ( 0, 0) [003174] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003172] D------N--- +--* LCL_VAR int V20 loc16 d:5 $VN.Void N003 ( 0, 0) [003173] ----------- \--* PHI int $b03 N001 ( 0, 0) [003484] ----------- pred BB169 +--* PHI_ARG int V20 loc16 u:6 $ab7 N002 ( 0, 0) [003479] ----------- pred BB156 \--* PHI_ARG int V20 loc16 u:4 $2b3 ***** BB170 STMT00148 ( 0x559[E-] ... 0x55D ) N005 ( 3, 4) [000673] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000672] D------N--- +--* LCL_VAR int V08 loc4 d:4 $VN.Void N003 ( 3, 4) [000671] ----------- \--* ADD int $ab9 N001 ( 1, 1) [000669] ----------- +--* LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- \--* CNS_INT int -1 $c4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} ***** BB171 STMT00132 ( 0x564[E-] ... 0x56C ) N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void N007 ( 10, 9) [000611] J------N--- \--* NE int $abc N005 ( 8, 6) [000609] ----------- +--* OR int $abb N003 ( 6, 4) [000607] ----------- | +--* NE int $aba N001 ( 1, 1) [000605] ----------- | | +--* LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- | | \--* CNS_INT int 0 $c0 N004 ( 1, 1) [000608] ----------- | \--* LCL_VAR int V21 loc17 u:2 $4c7 N006 ( 1, 2) [000610] ----------- \--* CNS_INT int 0 $c0 ------------ BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ***** BB172 STMT00133 ( 0x571[E-] ... 0x573 ) N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000615] J------N--- \--* LT int $abd N001 ( 1, 1) [000613] ----------- +--* LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- \--* CNS_INT int 0 $c0 ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ***** BB173 STMT00137 ( 0x575[E-] ... 0x577 ) N009 ( 18, 12) [000628] ---XG------ * JTRUE void $VN.Void N008 ( 16, 10) [003752] J--XG--N--- \--* AND int N003 ( 6, 3) [000627] -------N--- +--* GE int $abe N001 ( 1, 1) [000625] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 9, 6) [000632] ---XG--N--- \--* EQ int N005 ( 4, 3) [000630] ---XG------ +--* IND ubyte N004 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N006 ( 1, 2) [000631] ----------- \--* CNS_INT int 0 $c0 ------------ BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} ***** BB174 STMT00138 ( 0x57C[E-] ... 0x57F ) N001 ( 0, 0) [003753] ----------- * NOP void ***** BB174 STMT00418 ( 0x584[E-] ... ??? ) N006 ( 4, 3) [002059] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002058] D------N--- +--* LCL_VAR ref V106 tmp66 d:1 $VN.Void N004 ( 4, 3) [002006] ---XG------ \--* IND ref N003 ( 3, 4) [002907] -------N--- \--* ADD byref $a4d N001 ( 1, 1) [000618] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- \--* CNS_INT long 48 Fseq[] $20f ***** BB174 STMT00409 ( INL40 @ 0x000[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002010] J------N--- \--* EQ int N001 ( 1, 1) [002008] ----------- +--* LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- \--* CNS_INT ref null $VN.Null ------------ BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} ***** BB176 STMT00410 ( INL40 @ 0x004[E-] ... ??? ) <- INLRT @ 0x584[E-] N006 ( 4, 3) [002014] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002013] D------N--- +--* LCL_VAR int V107 tmp67 d:1 $VN.Void N004 ( 4, 3) [002012] ---XG------ \--* IND int N003 ( 3, 4) [002909] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000617] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- \--* CNS_INT long 8 $201 ***** BB176 STMT00411 ( INL40 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x584[E-] N012 ( 20, 14) [002019] ---XGO----- * JTRUE void N011 ( 18, 12) [003754] J--XGO-N--- \--* AND int N004 ( 8, 6) [002018] N--X---N-U- +--* NE int N002 ( 3, 3) [002016] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002015] ----------- | | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002028] N---GO-N-U- \--* GE int N005 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N009 ( 4, 3) [002062] n---GO----- \--* IND int N008 ( 3, 4) [002913] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002024] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002912] ----------- \--* CNS_INT long 24 $20c ------------ BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} ***** BB177 STMT00414 ( INL40 @ 0x014[E-] ... ??? ) <- INLRT @ 0x584[E-] N001 ( 0, 0) [003755] ----------- * NOP void ***** BB177 STMT00415 ( INL40 @ 0x022[E-] ... ??? ) <- INLRT @ 0x584[E-] N005 ( 3, 4) [002035] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002034] D------N--- +--* LCL_VAR byref V108 tmp68 d:1 $VN.Void N003 ( 3, 4) [002919] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002917] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- \--* CNS_INT long 16 $200 ***** BB177 STMT00416 ( INL40 @ ??? ... ??? ) <- INLRT @ 0x584[E-] N026 ( 34, 39) [002051] -A-XGO----- * ASG short N015 ( 20, 22) [002045] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002039] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002032] ----------- | | +--* LCL_VAR int V107 tmp67 u:1 N005 ( 4, 3) [002038] n---GO----- | | \--* IND int N004 ( 3, 4) [002922] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002037] ----------- | | +--* LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002923] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002044] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002043] n---GO----- | +--* IND byref N007 ( 1, 1) [002036] ----------- | | \--* LCL_VAR byref V108 tmp68 u:1 (last use) $25c N012 ( 4, 6) [002042] ----------- | \--* LSH long N010 ( 2, 3) [002040] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002033] ----------- | | \--* LCL_VAR int V107 tmp67 u:1 N011 ( 1, 2) [002041] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002934] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002927] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002047] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002926] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002046] ----------- | \--* LCL_VAR ref V106 tmp66 u:1 N024 ( 5, 4) [002936] n---GO----- \--* IND ushort N023 ( 1, 1) [002933] -----O----- \--* ARR_ADDR byref ushort[] $87 N022 ( 1, 1) [002931] -------N--- \--* ADD byref N020 ( 1, 1) [002924] ----------- +--* LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- \--* CNS_INT long 12 $20d ***** BB177 STMT00417 ( INL40 @ 0x036[E-] ... ??? ) <- INLRT @ 0x584[E-] N008 ( 8, 8) [002057] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002056] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002938] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002052] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002055] ----------- \--* ADD int N001 ( 1, 1) [002053] ----------- +--* LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- \--* CNS_INT int 1 $c1 ------------ BB179 [584..585), preds={BB176} succs={BB180} ***** BB179 STMT00412 ( INL40 @ 0x040[E-] ... ??? ) <- INLRT @ 0x584[E-] N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002020] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- arg2 in x1 +--* LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} ***** BB180 STMT00136 ( 0x590[E-] ... ??? ) N003 ( 1, 3) [000624] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000623] D------N--- +--* LCL_VAR int V21 loc17 d:3 $VN.Void N001 ( 1, 2) [002940] ----------- \--* CNS_INT int 1 $c1 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ***** BB181 STMT00420 ( INL43 @ 0x000[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002070] J------N--- \--* EQ int N001 ( 1, 1) [002068] ----------- +--* LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- \--* CNS_INT ref null $VN.Null ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ***** BB182 STMT00421 ( INL43 @ 0x004[E-] ... ??? ) <- INLRT @ 0x598[E-] N006 ( 4, 3) [002074] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002073] D------N--- +--* LCL_VAR int V111 tmp71 d:1 $VN.Void N004 ( 4, 3) [002072] ---XG------ \--* IND int N003 ( 3, 4) [002942] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000585] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- \--* CNS_INT long 8 $201 ***** BB182 STMT00422 ( INL43 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x598[E-] N012 ( 20, 14) [002079] ---XGO----- * JTRUE void N011 ( 18, 12) [003756] J--XGO-N--- \--* AND int N004 ( 8, 6) [002078] N--X---N-U- +--* NE int N002 ( 3, 3) [002076] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002075] ----------- | | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002088] N---GO-N-U- \--* GE int N005 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N009 ( 4, 3) [002122] n---GO----- \--* IND int N008 ( 3, 4) [002946] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002084] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002945] ----------- \--* CNS_INT long 24 $20c ------------ BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ***** BB183 STMT00425 ( INL43 @ 0x014[E-] ... ??? ) <- INLRT @ 0x598[E-] N001 ( 0, 0) [003757] ----------- * NOP void ***** BB183 STMT00426 ( INL43 @ 0x022[E-] ... ??? ) <- INLRT @ 0x598[E-] N005 ( 3, 4) [002095] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002094] D------N--- +--* LCL_VAR byref V112 tmp72 d:1 $VN.Void N003 ( 3, 4) [002952] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002950] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- \--* CNS_INT long 16 $200 ***** BB183 STMT00427 ( INL43 @ ??? ... ??? ) <- INLRT @ 0x598[E-] N026 ( 34, 39) [002111] -A-XGO----- * ASG short N015 ( 20, 22) [002105] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002099] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002092] ----------- | | +--* LCL_VAR int V111 tmp71 u:1 N005 ( 4, 3) [002098] n---GO----- | | \--* IND int N004 ( 3, 4) [002955] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002097] ----------- | | +--* LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002956] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002104] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002103] n---GO----- | +--* IND byref N007 ( 1, 1) [002096] ----------- | | \--* LCL_VAR byref V112 tmp72 u:1 (last use) $25c N012 ( 4, 6) [002102] ----------- | \--* LSH long N010 ( 2, 3) [002100] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002093] ----------- | | \--* LCL_VAR int V111 tmp71 u:1 N011 ( 1, 2) [002101] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [002967] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002960] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002107] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002959] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002106] ----------- | \--* LCL_VAR ref V110 tmp70 u:1 N024 ( 5, 4) [002969] n---GO----- \--* IND ushort N023 ( 1, 1) [002966] -----O----- \--* ARR_ADDR byref ushort[] $85 N022 ( 1, 1) [002964] -------N--- \--* ADD byref N020 ( 1, 1) [002957] ----------- +--* LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- \--* CNS_INT long 12 $20d ***** BB183 STMT00428 ( INL43 @ 0x036[E-] ... ??? ) <- INLRT @ 0x598[E-] N008 ( 8, 8) [002117] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002116] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [002971] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002112] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002115] ----------- \--* ADD int N001 ( 1, 1) [002113] ----------- +--* LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- \--* CNS_INT int 1 $c1 ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ***** BB185 STMT00423 ( INL43 @ 0x040[E-] ... ??? ) <- INLRT @ 0x598[E-] N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002080] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- arg2 in x1 +--* LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} ***** BB186 STMT00440 ( 0x5A9[E-] ... ??? ) N006 ( 4, 3) [002179] -A-XG---R-- * ASG ref $321 N005 ( 1, 1) [002178] D------N--- +--* LCL_VAR ref V114 tmp74 d:1 $VN.Void N004 ( 4, 3) [002126] ---XG------ \--* IND ref N003 ( 3, 4) [002974] -------N--- \--* ADD byref $a53 N001 ( 1, 1) [000635] ----------- +--* LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- \--* CNS_INT long 128 Fseq[] $210 ***** BB186 STMT00431 ( INL46 @ 0x000[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [002130] J------N--- \--* EQ int N001 ( 1, 1) [002128] ----------- +--* LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- \--* CNS_INT ref null $VN.Null ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ***** BB187 STMT00432 ( INL46 @ 0x004[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N006 ( 4, 3) [002134] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002133] D------N--- +--* LCL_VAR int V115 tmp75 d:1 $VN.Void N004 ( 4, 3) [002132] ---XG------ \--* IND int N003 ( 3, 4) [002976] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000634] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- \--* CNS_INT long 8 $201 ***** BB187 STMT00433 ( INL46 @ 0x00B[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N012 ( 20, 14) [002139] ---XGO----- * JTRUE void N011 ( 18, 12) [003758] J--XGO-N--- \--* AND int N004 ( 8, 6) [002138] N--X---N-U- +--* NE int N002 ( 3, 3) [002136] ---X------- | +--* ARR_LENGTH int N001 ( 1, 1) [002135] ----------- | | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] ----------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002148] N---GO-N-U- \--* GE int N005 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N009 ( 4, 3) [002182] n---GO----- \--* IND int N008 ( 3, 4) [002980] -------N--- \--* ADD byref $25b N006 ( 1, 1) [002144] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002979] ----------- \--* CNS_INT long 24 $20c ------------ BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ***** BB188 STMT00436 ( INL46 @ 0x014[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N001 ( 0, 0) [003759] ----------- * NOP void ***** BB188 STMT00437 ( INL46 @ 0x022[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N005 ( 3, 4) [002155] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002154] D------N--- +--* LCL_VAR byref V116 tmp76 d:1 $VN.Void N003 ( 3, 4) [002986] -----O----- \--* ADD byref $25c N001 ( 1, 1) [002984] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- \--* CNS_INT long 16 $200 ***** BB188 STMT00438 ( INL46 @ ??? ... ??? ) <- INLRT @ 0x5A9[E-] N026 ( 34, 39) [002171] -A-XGO----- * ASG short N015 ( 20, 22) [002165] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002159] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002152] ----------- | | +--* LCL_VAR int V115 tmp75 u:1 N005 ( 4, 3) [002158] n---GO----- | | \--* IND int N004 ( 3, 4) [002989] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002157] ----------- | | +--* LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [002990] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002164] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002163] n---GO----- | +--* IND byref N007 ( 1, 1) [002156] ----------- | | \--* LCL_VAR byref V116 tmp76 u:1 (last use) $25c N012 ( 4, 6) [002162] ----------- | \--* LSH long N010 ( 2, 3) [002160] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002153] ----------- | | \--* LCL_VAR int V115 tmp75 u:1 N011 ( 1, 2) [002161] ----------- | \--* CNS_INT long 1 $204 N025 ( 13, 16) [003001] ---XGO----- \--* COMMA ushort N019 ( 8, 12) [002994] ---X-O----- +--* BOUNDS_CHECK_Rng void N016 ( 1, 2) [002167] ----------- | +--* CNS_INT int 0 $c0 N018 ( 3, 3) [002993] ---X------- | \--* ARR_LENGTH int N017 ( 1, 1) [002166] ----------- | \--* LCL_VAR ref V114 tmp74 u:1 N024 ( 5, 4) [003003] n---GO----- \--* IND ushort N023 ( 1, 1) [003000] -----O----- \--* ARR_ADDR byref ushort[] $88 N022 ( 1, 1) [002998] -------N--- \--* ADD byref N020 ( 1, 1) [002991] ----------- +--* LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- \--* CNS_INT long 12 $20d ***** BB188 STMT00439 ( INL46 @ 0x036[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N008 ( 8, 8) [002177] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002176] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003005] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002172] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002175] ----------- \--* ADD int N001 ( 1, 1) [002173] ----------- +--* LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- \--* CNS_INT int 1 $c1 ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ***** BB190 STMT00434 ( INL46 @ 0x040[E-] ... ??? ) <- INLRT @ 0x5A9[E-] N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void N001 ( 1, 1) [002140] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- arg2 in x1 +--* LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000431d58 ftn $4f ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ***** BB191 STMT00174 ( 0x5BA[E-] ... 0x5C2 ) N003 ( 1, 3) [000812] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000811] D------N--- +--* LCL_VAR int V59 tmp19 d:1 $VN.Void N001 ( 1, 1) [000805] ----------- \--* LCL_VAR int V16 loc12 u:13 $b04 ***** BB191 STMT00173 ( 0x5BA[E-] ... ??? ) N005 ( 3, 4) [000810] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000809] D------N--- +--* LCL_VAR int V16 loc12 d:15 $VN.Void N003 ( 3, 4) [000808] ----------- \--* ADD int $bad N001 ( 1, 1) [000806] ----------- +--* LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- \--* CNS_INT int 1 $c1 ***** BB191 STMT00449 ( ??? ... ??? ) N003 ( 1, 3) [002225] -A--G---R-- * ASG ushort $bec N002 ( 1, 1) [002224] D------N--- +--* LCL_VAR int V119 tmp79 d:1 $VN.Void N001 ( 1, 1) [003629] ----------- \--* LCL_VAR int V172 cse1 ***** BB191 STMT00442 ( INL48 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002188] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002187] D------N--- +--* LCL_VAR int V118 tmp78 d:1 $VN.Void N004 ( 4, 3) [002186] ---XG------ \--* IND int N003 ( 3, 4) [003008] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000803] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- \--* CNS_INT long 8 $201 ***** BB191 STMT00444 ( INL48 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002194] N---GO-N-U- \--* GE int N001 ( 1, 1) [002189] ----------- +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002228] n---GO----- \--* IND int N004 ( 3, 4) [003012] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002190] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- \--* CNS_INT long 24 $20c ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ***** BB192 STMT00446 ( INL48 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002204] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002203] D------N--- +--* LCL_VAR byref V120 tmp80 d:1 $VN.Void N003 ( 3, 4) [003018] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003016] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- \--* CNS_INT long 16 $200 ***** BB192 STMT00447 ( INL48 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002217] -A-XGO----- * ASG short N015 ( 20, 22) [002214] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002208] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002201] ----------- | | +--* LCL_VAR int V118 tmp78 u:1 N005 ( 4, 3) [002207] n---GO----- | | \--* IND int N004 ( 3, 4) [003021] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002206] ----------- | | +--* LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003022] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002213] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002212] n---GO----- | +--* IND byref N007 ( 1, 1) [002205] ----------- | | \--* LCL_VAR byref V120 tmp80 u:1 (last use) $25c N012 ( 4, 6) [002211] ----------- | \--* LSH long N010 ( 2, 3) [002209] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002202] ----------- | | \--* LCL_VAR int V118 tmp78 u:1 N011 ( 1, 2) [002210] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002215] ----------- \--* LCL_VAR int V119 tmp79 u:1 (last use) ***** BB192 STMT00448 ( INL48 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002223] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002222] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003024] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002218] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002221] ----------- \--* ADD int N001 ( 1, 1) [002219] ----------- +--* LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- \--* CNS_INT int 1 $c1 ------------ BB193 [000..000), preds={BB191} succs={BB194} ***** BB193 STMT00445 ( INL48 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002196] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- arg2 in x1 +--* LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} ***** BB194 STMT00505 ( ??? ... ??? ) N005 ( 0, 0) [003168] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003166] D------N--- +--* LCL_VAR int V16 loc12 d:13 $VN.Void N003 ( 0, 0) [003167] ----------- \--* PHI int $b04 N001 ( 0, 0) [003478] ----------- pred BB193 +--* PHI_ARG int V16 loc12 u:15 N002 ( 0, 0) [003475] ----------- pred BB137 \--* PHI_ARG int V16 loc12 u:5 $898 ***** BB194 STMT00166 ( 0x5CE[E-] ... ??? ) N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000756] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000751] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ***** BB195 STMT00171 ( 0x5D9[E-] ... 0x5E2 ) N014 ( 14, 16) [000791] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000790] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003633] -A-XG------ +--* COMMA int N009 ( 9, 10) [003631] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003630] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000788] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000787] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000781] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000786] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000783] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000782] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000785] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003632] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- \--* CNS_INT int 0 $c0 ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ***** BB196 STMT00172 ( 0x5E4[E-] ... 0x5EF ) N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec N003 ( 3, 3) [000801] N---G--N-U- \--* NE int N001 ( 1, 1) [003634] ----------- +--* LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- \--* LCL_VAR int V18 loc14 u:1 ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ***** BB197 STMT00168 ( 0x5F1[E-] ... ??? ) N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000763] J------N--- \--* GE int $ba4 N001 ( 1, 1) [000758] ----------- +--* LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ***** BB198 STMT00169 ( 0x5FF[E-] ... 0x608 ) N014 ( 14, 16) [000775] -A-XG------ * JTRUE void $bec N013 ( 12, 14) [000774] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003638] -A-XG------ +--* COMMA int N009 ( 9, 10) [003636] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003635] D------N--- | | +--* LCL_VAR int V172 cse1 $VN.Void N007 ( 9, 10) [000772] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000771] -------N--- | | \--* ADD long $acc N001 ( 1, 1) [000765] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000770] ----------- | | \--* LSH long $acb N003 ( 2, 3) [000767] ----------- | | +--* CAST long <- int $aca N002 ( 1, 1) [000766] ----------- | | | \--* LCL_VAR int V16 loc12 u:13 $b04 N004 ( 1, 2) [000769] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003637] ----------- | \--* LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- \--* CNS_INT int 0 $c0 ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ***** BB199 STMT00170 ( 0x60D[E-] ... 0x611 ) N005 ( 3, 4) [000780] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000779] D------N--- +--* LCL_VAR int V16 loc12 d:14 $VN.Void N003 ( 3, 4) [000778] ----------- \--* ADD int $bad N001 ( 1, 1) [000776] ----------- +--* LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- \--* CNS_INT int 1 $c1 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ***** BB200 STMT00074 ( 0x618[E-] ... ??? ) N018 ( 24, 20) [000289] -A-XG------ * JTRUE void $VN.Void N017 ( 22, 18) [003760] JA-XG--N--- \--* AND int N003 ( 6, 3) [000288] -------N--- +--* GE int $94d N001 ( 1, 1) [000283] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [000299] -A-XG--N--- \--* EQ int N014 ( 10, 11) [003666] -A-XG------ +--* COMMA int N012 ( 9, 10) [003664] -A-XG---R-- | +--* ASG int $VN.Void N011 ( 1, 1) [003663] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N010 ( 9, 10) [000297] ---XG------ | | \--* IND ushort N009 ( 6, 8) [000296] -------N--- | | \--* ADD long $3e7 N004 ( 1, 1) [000290] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N008 ( 4, 6) [000295] ----------- | | \--* LSH long $3e6 N006 ( 2, 3) [000292] ----------- | | +--* CAST long <- int $3e5 N005 ( 1, 1) [000291] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N007 ( 1, 2) [000294] ----------- | | \--* CNS_INT long 1 $204 N013 ( 1, 1) [003665] ----------- | \--* LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] ----------- \--* CNS_INT int 0 $c0 ------------ BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} ***** BB201 STMT00075 ( 0x626[E-] ... 0x62F ) N001 ( 0, 0) [003761] ----------- * NOP void ***** BB201 STMT00077 ( 0x634[E-] ... 0x63C ) N003 ( 1, 3) [000310] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000309] D------N--- +--* LCL_VAR int V51 tmp11 d:1 $VN.Void N001 ( 1, 1) [000303] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB201 STMT00076 ( 0x634[E-] ... ??? ) N005 ( 3, 4) [000308] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000307] D------N--- +--* LCL_VAR int V16 loc12 d:12 $VN.Void N003 ( 3, 4) [000306] ----------- \--* ADD int $952 N001 ( 1, 1) [000304] ----------- +--* LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- \--* CNS_INT int 1 $c1 ***** BB201 STMT00458 ( ??? ... ??? ) N003 ( 1, 3) [002283] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002282] D------N--- +--* LCL_VAR int V123 tmp83 d:1 $VN.Void N001 ( 1, 1) [003667] ----------- \--* LCL_VAR int V176 cse5 ***** BB201 STMT00451 ( INL53 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002246] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002245] D------N--- +--* LCL_VAR int V122 tmp82 d:1 $VN.Void N004 ( 4, 3) [002244] ---XG------ \--* IND int N003 ( 3, 4) [003027] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000301] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- \--* CNS_INT long 8 $201 ***** BB201 STMT00453 ( INL53 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002252] N---GO-N-U- \--* GE int N001 ( 1, 1) [002247] ----------- +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002286] n---GO----- \--* IND int N004 ( 3, 4) [003031] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002248] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- \--* CNS_INT long 24 $20c ------------ BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} ***** BB203 STMT00455 ( INL53 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002262] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002261] D------N--- +--* LCL_VAR byref V124 tmp84 d:1 $VN.Void N003 ( 3, 4) [003037] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003035] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- \--* CNS_INT long 16 $200 ***** BB203 STMT00456 ( INL53 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002275] -A-XGO----- * ASG short N015 ( 20, 22) [002272] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002266] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002259] ----------- | | +--* LCL_VAR int V122 tmp82 u:1 N005 ( 4, 3) [002265] n---GO----- | | \--* IND int N004 ( 3, 4) [003040] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002264] ----------- | | +--* LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003041] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002271] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002270] n---GO----- | +--* IND byref N007 ( 1, 1) [002263] ----------- | | \--* LCL_VAR byref V124 tmp84 u:1 (last use) $25c N012 ( 4, 6) [002269] ----------- | \--* LSH long N010 ( 2, 3) [002267] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002260] ----------- | | \--* LCL_VAR int V122 tmp82 u:1 N011 ( 1, 2) [002268] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002273] ----------- \--* LCL_VAR int V123 tmp83 u:1 (last use) ***** BB203 STMT00457 ( INL53 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002281] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002280] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003043] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002276] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002279] ----------- \--* ADD int N001 ( 1, 1) [002277] ----------- +--* LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- \--* CNS_INT int 1 $c1 ------------ BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} ***** BB204 STMT00454 ( INL53 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002254] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- arg2 in x1 +--* LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ***** BB205 STMT00080 ( 0x64D[E-] ... 0x64E ) N003 ( 1, 3) [000325] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000324] D------N--- +--* LCL_VAR int V37 loc33 d:1 $VN.Void N001 ( 1, 2) [003045] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00081 ( 0x650[E-] ... 0x651 ) N003 ( 1, 3) [000328] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000327] D------N--- +--* LCL_VAR int V38 loc34 d:1 $VN.Void N001 ( 1, 2) [000326] ----------- \--* CNS_INT int 0 $c0 ***** BB205 STMT00082 ( 0x653[E-] ... 0x655 ) N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000331] J------N--- \--* EQ int $97d N001 ( 1, 1) [000329] ----------- +--* LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- \--* CNS_INT int 0 $c0 ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ***** BB206 STMT00098 ( 0x65A[E-] ... ??? ) N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000424] J------N--- \--* GE int $94d N001 ( 1, 1) [000419] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ***** BB207 STMT00123 ( 0x665[E-] ... 0x670 ) N014 ( 14, 16) [000575] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000574] NA-XG--N-U- \--* EQ int N011 ( 10, 11) [003671] -A-XG------ +--* COMMA int N009 ( 9, 10) [003669] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003668] D------N--- | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000572] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000571] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000565] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000570] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000567] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000566] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000569] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003670] ----------- | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- \--* CNS_INT int 48 $d8 ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} ***** BB208 STMT00100 ( 0x67A[E-] ... ??? ) N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void N005 ( 5, 6) [000433] J------N--- \--* GE int $9e2 N003 ( 3, 4) [000428] ----------- +--* ADD int $952 N001 ( 1, 1) [000426] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- | \--* CNS_INT int 1 $c1 N004 ( 1, 1) [003703] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ***** BB209 STMT00120 ( 0x687[E-] ... 0x692 ) N026 ( 34, 33) [000548] -A-XG------ * JTRUE void $87a N025 ( 32, 31) [003762] JA-XG--N--- \--* AND int N013 ( 15, 14) [000547] NA-XG--N-U- +--* NE int N011 ( 10, 11) [003675] -A-XG------ | +--* COMMA int N009 ( 9, 10) [003673] -A-XG---R-- | | +--* ASG int $VN.Void N008 ( 1, 1) [003672] D------N--- | | | +--* LCL_VAR int V176 cse5 $VN.Void N007 ( 9, 10) [000545] ---XG------ | | | \--* IND ushort N006 ( 6, 8) [000544] -------N--- | | | \--* ADD long $3e7 N001 ( 1, 1) [000538] ----------- | | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000543] ----------- | | | \--* LSH long $3e6 N003 ( 2, 3) [000540] ----------- | | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000539] ----------- | | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000542] ----------- | | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003674] ----------- | | \--* LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- | \--* CNS_INT int 43 $d9 N024 ( 16, 16) [000560] N--XG--N-U- \--* NE int N022 ( 11, 13) [000558] ---XG------ +--* IND ushort N021 ( 8, 11) [000557] -------N--- | \--* ADD long $3f6 N014 ( 1, 1) [000549] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N020 ( 6, 9) [000556] ----------- | \--* LSH long $3f5 N018 ( 4, 6) [000553] ----------- | +--* CAST long <- int $3f4 N017 ( 3, 4) [000552] ----------- | | \--* ADD int $952 N015 ( 1, 1) [000550] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N016 ( 1, 2) [000551] ----------- | | \--* CNS_INT int 1 $c1 N019 ( 1, 2) [000555] ----------- | \--* CNS_INT long 1 $204 N023 ( 1, 2) [000559] ----------- \--* CNS_INT int 48 $d8 ------------ BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} ***** BB210 STMT00121 ( 0x694[E-] ... 0x6A1 ) N001 ( 0, 0) [003763] ----------- * NOP void ***** BB210 STMT00122 ( 0x6A3[E-] ... 0x6A4 ) N003 ( 1, 3) [000564] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000563] D------N--- +--* LCL_VAR int V37 loc33 d:4 $VN.Void N001 ( 1, 2) [003046] ----------- \--* CNS_INT int 1 $c1 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} ***** BB213 STMT00104 ( 0x6B5[E-] ... 0x6C0 ) N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a N003 ( 3, 4) [000456] N---G--N-U- \--* NE int N001 ( 1, 1) [003676] ----------- +--* LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- \--* CNS_INT int 45 $da ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ***** BB214 STMT00105 ( 0x6C2[E-] ... 0x6CF ) N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 N011 ( 13, 16) [000469] J--XG--N--- \--* EQ int N009 ( 11, 13) [000467] ---XG------ +--* IND ushort N008 ( 8, 11) [000466] -------N--- | \--* ADD long $3f6 N001 ( 1, 1) [000458] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N007 ( 6, 9) [000465] ----------- | \--* LSH long $3f5 N005 ( 4, 6) [000462] ----------- | +--* CAST long <- int $3f4 N004 ( 3, 4) [000461] ----------- | | \--* ADD int $952 N002 ( 1, 1) [000459] ----------- | | +--* LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- | | \--* CNS_INT int 1 $c1 N006 ( 1, 2) [000464] ----------- | \--* CNS_INT long 1 $204 N010 ( 1, 2) [000468] ----------- \--* CNS_INT int 48 $d8 ------------ BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} ***** BB215 STMT00460 ( INL58 @ 0x000[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N006 ( 4, 3) [002304] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002303] D------N--- +--* LCL_VAR int V126 tmp86 d:1 $VN.Void N004 ( 4, 3) [002302] ---XG------ \--* IND int N003 ( 3, 4) [003048] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000444] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- \--* CNS_INT long 8 $201 ***** BB215 STMT00462 ( INL58 @ 0x007[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002310] N---GO-N-U- \--* GE int N001 ( 1, 1) [002305] ----------- +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002341] n---GO----- \--* IND int N004 ( 3, 4) [003052] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002306] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- \--* CNS_INT long 24 $20c ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ***** BB216 STMT00464 ( INL58 @ 0x015[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N005 ( 3, 4) [002319] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002318] D------N--- +--* LCL_VAR byref V127 tmp87 d:1 $VN.Void N003 ( 3, 4) [003058] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003056] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- \--* CNS_INT long 16 $200 ***** BB216 STMT00465 ( INL58 @ ??? ... ??? ) <- INLRT @ 0x6D1[E-] N017 ( 22, 24) [002332] -A-XGO----- * ASG short N015 ( 20, 22) [002329] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002323] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002316] ----------- | | +--* LCL_VAR int V126 tmp86 u:1 N005 ( 4, 3) [002322] n---GO----- | | \--* IND int N004 ( 3, 4) [003061] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002321] ----------- | | +--* LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003062] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002328] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002327] n---GO----- | +--* IND byref N007 ( 1, 1) [002320] ----------- | | \--* LCL_VAR byref V127 tmp87 u:1 (last use) $25c N012 ( 4, 6) [002326] ----------- | \--* LSH long N010 ( 2, 3) [002324] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002317] ----------- | | \--* LCL_VAR int V126 tmp86 u:1 N011 ( 1, 2) [002325] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002330] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB216 STMT00466 ( INL58 @ 0x023[E-] ... ??? ) <- INLRT @ 0x6D1[E-] N008 ( 8, 8) [002338] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002337] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003064] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002333] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002336] ----------- \--* ADD int N001 ( 1, 1) [002334] ----------- +--* LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- \--* CNS_INT int 1 $c1 ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ***** BB218 STMT00526 ( ??? ... ??? ) N005 ( 0, 0) [003231] -A------R-- * ASG bool $VN.Void N004 ( 0, 0) [003229] D------N--- +--* LCL_VAR bool V37 loc33 d:3 $VN.Void N003 ( 0, 0) [003230] ----------- \--* PHI bool $4c9 N001 ( 0, 0) [003471] ----------- pred BB207 +--* PHI_ARG bool V37 loc33 u:1 $c0 N002 ( 0, 0) [003461] ----------- pred BB220 \--* PHI_ARG bool V37 loc33 u:2 ***** BB218 STMT00523 ( ??? ... ??? ) N005 ( 0, 0) [003222] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003220] D------N--- +--* LCL_VAR int V16 loc12 d:11 $VN.Void N003 ( 0, 0) [003221] ----------- \--* PHI int $b0c N001 ( 0, 0) [003472] ----------- pred BB207 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003462] ----------- pred BB220 \--* PHI_ARG int V16 loc12 u:10 ***** BB218 STMT00522 ( ??? ... ??? ) N005 ( 0, 0) [003219] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003217] D------N--- +--* LCL_VAR int V38 loc34 d:5 $VN.Void N003 ( 0, 0) [003218] ----------- \--* PHI int $b0d N001 ( 0, 0) [003473] ----------- pred BB207 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003463] ----------- pred BB220 \--* PHI_ARG int V38 loc34 u:2 ***** BB218 STMT00119 ( 0x6DE[E-] ... 0x6E2 ) N005 ( 3, 4) [000537] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000536] D------N--- +--* LCL_VAR int V38 loc34 d:6 $VN.Void N003 ( 3, 4) [000535] ----------- \--* ADD int $c59 N001 ( 1, 1) [000533] ----------- +--* LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- \--* CNS_INT int 1 $c1 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} ***** BB219 STMT00525 ( ??? ... ??? ) N006 ( 0, 0) [003228] -A------R-- * ASG bool $VN.Void N005 ( 0, 0) [003226] D------N--- +--* LCL_VAR bool V37 loc33 d:2 $VN.Void N004 ( 0, 0) [003227] ----------- \--* PHI bool $4ca N001 ( 0, 0) [003470] ----------- pred BB211 +--* PHI_ARG bool V37 loc33 u:4 $c1 N002 ( 0, 0) [003467] ----------- pred BB214 +--* PHI_ARG bool V37 loc33 u:1 $c0 N003 ( 0, 0) [003464] ----------- pred BB218 \--* PHI_ARG bool V37 loc33 u:3 $4c9 ***** BB219 STMT00524 ( ??? ... ??? ) N005 ( 0, 0) [003225] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003223] D------N--- +--* LCL_VAR int V16 loc12 d:9 $VN.Void N003 ( 0, 0) [003224] ----------- \--* PHI int $b0e N001 ( 0, 0) [003468] ----------- pred BB214 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003465] ----------- pred BB218 \--* PHI_ARG int V16 loc12 u:11 $b0c ***** BB219 STMT00521 ( ??? ... ??? ) N005 ( 0, 0) [003216] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003214] D------N--- +--* LCL_VAR int V38 loc34 d:2 $VN.Void N003 ( 0, 0) [003215] ----------- \--* PHI int $b0f N001 ( 0, 0) [003469] ----------- pred BB214 +--* PHI_ARG int V38 loc34 u:1 $c0 N002 ( 0, 0) [003466] ----------- pred BB218 \--* PHI_ARG int V38 loc34 u:6 $c59 ***** BB219 STMT00106 ( 0x6E4[E-] ... 0x6E9 ) N005 ( 3, 4) [000475] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000474] D------N--- +--* LCL_VAR int V54 tmp14 d:1 $VN.Void N003 ( 3, 4) [000473] ----------- \--* ADD int $c5c N001 ( 1, 1) [000471] ----------- +--* LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- \--* CNS_INT int 1 $c1 ***** BB219 STMT00107 ( ??? ... ??? ) N003 ( 1, 3) [000479] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000478] D------N--- +--* LCL_VAR int V16 loc12 d:10 $VN.Void N001 ( 1, 1) [000477] ----------- \--* LCL_VAR int V54 tmp14 u:1 $c5c ***** BB219 STMT00109 ( ??? ... ??? ) N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000484] J------N--- \--* GE int $c5d N001 ( 1, 1) [000476] ----------- +--* LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ***** BB220 STMT00118 ( 0x6F4[E-] ... 0x6FF ) N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 N009 ( 11, 13) [000531] J--XG--N--- \--* EQ int N007 ( 9, 10) [000529] ---XG------ +--* IND ushort N006 ( 6, 8) [000528] -------N--- | \--* ADD long $ada N001 ( 1, 1) [000522] ----------- | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000527] ----------- | \--* LSH long $ad9 N003 ( 2, 3) [000524] ----------- | +--* CAST long <- int $ad8 N002 ( 1, 1) [000523] ----------- | | \--* LCL_VAR int V16 loc12 u:10 $c5c N004 ( 1, 2) [000526] ----------- | \--* CNS_INT long 1 $204 N008 ( 1, 2) [000530] ----------- \--* CNS_INT int 48 $d8 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ***** BB221 STMT00110 ( 0x701[E-] ... 0x705 ) N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void N003 ( 3, 4) [000488] J------N--- \--* LE int $c62 N001 ( 1, 1) [000486] ----------- +--* LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- \--* CNS_INT int 10 $e4 ------------ BB222 [707..70B), preds={BB221} succs={BB223} ***** BB222 STMT00117 ( 0x707[E-] ... 0x709 ) N003 ( 1, 3) [000521] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000520] D------N--- +--* LCL_VAR int V38 loc34 d:4 $VN.Void N001 ( 1, 2) [000519] ----------- \--* CNS_INT int 10 $e4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ***** BB223 STMT00520 ( ??? ... ??? ) N005 ( 0, 0) [003213] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003211] D------N--- +--* LCL_VAR int V38 loc34 d:3 $VN.Void N003 ( 0, 0) [003212] ----------- \--* PHI int $b10 N001 ( 0, 0) [003460] ----------- pred BB222 +--* PHI_ARG int V38 loc34 u:4 $e4 N002 ( 0, 0) [003455] ----------- pred BB221 \--* PHI_ARG int V38 loc34 u:2 $b0f ***** BB223 STMT00111 ( 0x70B[E-] ... 0x70E ) N005 ( 8, 8) [000494] ---XG------ * JTRUE void N004 ( 6, 6) [000493] J--XG--N--- \--* EQ int N002 ( 4, 3) [000491] ---XG------ +--* IND ubyte N001 ( 1, 1) [000490] ----------- | \--* LCL_VAR long V17 loc13 u:1 N003 ( 1, 2) [000492] ----------- \--* CNS_INT int 0 $c0 ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ***** BB224 STMT00116 ( 0x710[E-] ... 0x718 ) N008 ( 6, 5) [000517] -A--GO--R-- * ASG int $301 N007 ( 1, 1) [000516] D------N--- +--* LCL_VAR int V55 tmp15 d:3 $VN.Void N006 ( 6, 5) [000515] ----GO----- \--* SUB int N004 ( 4, 3) [000513] n---GO----- +--* IND int N003 ( 3, 4) [003067] -------N--- | \--* ADD byref $24a N001 ( 1, 1) [000512] ----------- | +--* LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- | \--* CNS_INT long 4 $207 N005 ( 1, 1) [000514] ----------- \--* LCL_VAR int V05 loc1 u:3 $28d ------------ BB225 [71A..71B), preds={BB223} succs={BB226} ***** BB225 STMT00112 ( 0x71A[E-] ... 0x71A ) N003 ( 1, 3) [000497] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000496] D------N--- +--* LCL_VAR int V55 tmp15 d:2 $VN.Void N001 ( 1, 2) [000495] ----------- \--* CNS_INT int 0 $c0 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ***** BB226 STMT00519 ( ??? ... ??? ) N005 ( 0, 0) [003210] -A------R-- * ASG int $VN.Void N004 ( 0, 0) [003208] D------N--- +--* LCL_VAR int V55 tmp15 d:1 $VN.Void N003 ( 0, 0) [003209] ----------- \--* PHI int $b12 N001 ( 0, 0) [003459] ----------- pred BB224 +--* PHI_ARG int V55 tmp15 u:3 N002 ( 0, 0) [003458] ----------- pred BB225 \--* PHI_ARG int V55 tmp15 u:2 $c0 ***** BB226 STMT00114 ( 0x71D[E-] ... 0x72D ) N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void N001 ( 1, 1) [000507] ----------- arg6 in x5 +--* LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- arg1 in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- arg2 in x1 +--* LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- arg3 in x2 +--* LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- arg4 in x3 +--* LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- arg5 in x4 +--* LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000540240 ftn $5e ***** BB226 STMT00115 ( 0x72C[E-] ... ??? ) N003 ( 1, 3) [000511] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000510] D------N--- +--* LCL_VAR int V09 loc5 d:4 $VN.Void N001 ( 1, 2) [003069] ----------- \--* CNS_INT int 0 $c0 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ***** BB227 STMT00468 ( INL61 @ 0x000[E-] ... ??? ) <- INLRT @ 0x731[E-] N006 ( 4, 3) [002351] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002350] D------N--- +--* LCL_VAR int V129 tmp89 d:1 $VN.Void N004 ( 4, 3) [002349] ---XG------ \--* IND int N003 ( 3, 4) [003071] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000333] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- \--* CNS_INT long 8 $201 ***** BB227 STMT00470 ( INL61 @ 0x007[E-] ... ??? ) <- INLRT @ 0x731[E-] N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002357] N---GO-N-U- \--* GE int N001 ( 1, 1) [002352] ----------- +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002388] n---GO----- \--* IND int N004 ( 3, 4) [003075] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002353] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- \--* CNS_INT long 24 $20c ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ***** BB228 STMT00472 ( INL61 @ 0x015[E-] ... ??? ) <- INLRT @ 0x731[E-] N005 ( 3, 4) [002366] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002365] D------N--- +--* LCL_VAR byref V130 tmp90 d:1 $VN.Void N003 ( 3, 4) [003081] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003079] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- \--* CNS_INT long 16 $200 ***** BB228 STMT00473 ( INL61 @ ??? ... ??? ) <- INLRT @ 0x731[E-] N017 ( 22, 24) [002379] -A-XGO----- * ASG short N015 ( 20, 22) [002376] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002370] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002363] ----------- | | +--* LCL_VAR int V129 tmp89 u:1 N005 ( 4, 3) [002369] n---GO----- | | \--* IND int N004 ( 3, 4) [003084] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002368] ----------- | | +--* LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003085] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002375] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002374] n---GO----- | +--* IND byref N007 ( 1, 1) [002367] ----------- | | \--* LCL_VAR byref V130 tmp90 u:1 (last use) $25c N012 ( 4, 6) [002373] ----------- | \--* LSH long N010 ( 2, 3) [002371] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002364] ----------- | | \--* LCL_VAR int V129 tmp89 u:1 N011 ( 1, 2) [002372] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002377] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB228 STMT00474 ( INL61 @ 0x023[E-] ... ??? ) <- INLRT @ 0x731[E-] N008 ( 8, 8) [002385] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002384] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003087] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002380] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002383] ----------- \--* ADD int N001 ( 1, 1) [002381] ----------- +--* LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- \--* CNS_INT int 1 $c1 ------------ BB229 [731..732), preds={BB227} succs={BB230} ***** BB229 STMT00471 ( INL61 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x731[E-] N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002359] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ***** BB230 STMT00085 ( 0x739[E-] ... ??? ) N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000341] J------N--- \--* GE int $94d N001 ( 1, 1) [000336] ----------- +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ***** BB231 STMT00086 ( 0x744[E-] ... 0x74F ) N014 ( 14, 16) [000353] -A-XG------ * JTRUE void $87a N013 ( 12, 14) [000352] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003660] -A-XG------ +--* COMMA int N009 ( 9, 10) [003658] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003657] D------N--- | | +--* LCL_VAR int V175 cse4 d:1 $VN.Void N007 ( 9, 10) [000350] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000349] -------N--- | | \--* ADD long $3e7 N001 ( 1, 1) [000343] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000348] ----------- | | \--* LSH long $3e6 N003 ( 2, 3) [000345] ----------- | | +--* CAST long <- int $3e5 N002 ( 1, 1) [000344] ----------- | | | \--* LCL_VAR int V16 loc12 u:5 $898 N004 ( 1, 2) [000347] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003659] ----------- | \--* LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- \--* CNS_INT int 43 $d9 ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ***** BB232 STMT00096 ( 0x751[E-] ... 0x75C ) N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a N003 ( 3, 4) [000417] N---G--N-U- \--* NE int N001 ( 1, 1) [003661] ----------- +--* LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- \--* CNS_INT int 45 $da ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ***** BB233 STMT00088 ( 0x75E[E-] ... 0x766 ) N003 ( 1, 3) [000363] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000362] D------N--- +--* LCL_VAR int V52 tmp12 d:1 $VN.Void N001 ( 1, 1) [000356] ----------- \--* LCL_VAR int V16 loc12 u:5 $898 ***** BB233 STMT00087 ( 0x75E[E-] ... ??? ) N005 ( 3, 4) [000361] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000360] D------N--- +--* LCL_VAR int V16 loc12 d:8 $VN.Void N003 ( 3, 4) [000359] ----------- \--* ADD int $952 N001 ( 1, 1) [000357] ----------- +--* LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- \--* CNS_INT int 1 $c1 ***** BB233 STMT00483 ( ??? ... ??? ) N003 ( 1, 3) [002435] -A--G---R-- * ASG ushort $87a N002 ( 1, 1) [002434] D------N--- +--* LCL_VAR int V133 tmp93 d:1 $VN.Void N001 ( 1, 1) [003662] ----------- \--* LCL_VAR int V175 cse4 u:1 ***** BB233 STMT00476 ( INL64 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002398] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002397] D------N--- +--* LCL_VAR int V132 tmp92 d:1 $VN.Void N004 ( 4, 3) [002396] n---GO----- \--* IND int N003 ( 3, 4) [003090] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000354] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- \--* CNS_INT long 8 $201 ***** BB233 STMT00478 ( INL64 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002404] N---GO-N-U- \--* GE int N001 ( 1, 1) [002399] ----------- +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002438] n---GO----- \--* IND int N004 ( 3, 4) [003094] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002400] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- \--* CNS_INT long 24 $20c ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB234 STMT00480 ( INL64 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002414] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002413] D------N--- +--* LCL_VAR byref V134 tmp94 d:1 $VN.Void N003 ( 3, 4) [003100] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003098] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- \--* CNS_INT long 16 $200 ***** BB234 STMT00481 ( INL64 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002427] -A-XGO----- * ASG short N015 ( 20, 22) [002424] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002418] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002411] ----------- | | +--* LCL_VAR int V132 tmp92 u:1 N005 ( 4, 3) [002417] n---GO----- | | \--* IND int N004 ( 3, 4) [003103] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002416] ----------- | | +--* LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003104] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002423] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002422] n---GO----- | +--* IND byref N007 ( 1, 1) [002415] ----------- | | \--* LCL_VAR byref V134 tmp94 u:1 (last use) $25c N012 ( 4, 6) [002421] ----------- | \--* LSH long N010 ( 2, 3) [002419] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002412] ----------- | | \--* LCL_VAR int V132 tmp92 u:1 N011 ( 1, 2) [002420] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002425] ----------- \--* LCL_VAR int V133 tmp93 u:1 (last use) ***** BB234 STMT00482 ( INL64 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002433] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002432] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003106] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002428] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002431] ----------- \--* ADD int N001 ( 1, 1) [002429] ----------- +--* LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- \--* CNS_INT int 1 $c1 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ***** BB235 STMT00479 ( INL64 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002406] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- arg2 in x1 +--* LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ***** BB236 STMT00094 ( 0x774[E-] ... 0x77C ) N003 ( 1, 3) [000399] -A------R-- * ASG int $VN.Void N002 ( 1, 1) [000398] D------N--- +--* LCL_VAR int V53 tmp13 d:1 $VN.Void N001 ( 1, 1) [000392] ----------- \--* LCL_VAR int V16 loc12 u:6 $b08 ***** BB236 STMT00093 ( 0x774[E-] ... ??? ) N005 ( 3, 4) [000397] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000396] D------N--- +--* LCL_VAR int V16 loc12 d:7 $VN.Void N003 ( 3, 4) [000395] ----------- \--* ADD int $c47 N001 ( 1, 1) [000393] ----------- +--* LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- \--* CNS_INT int 1 $c1 ***** BB236 STMT00492 ( ??? ... ??? ) N003 ( 1, 3) [002481] -A--G---R-- * ASG ushort $c02 N002 ( 1, 1) [002480] D------N--- +--* LCL_VAR int V137 tmp97 d:1 $VN.Void N001 ( 1, 1) [003639] ----------- \--* LCL_VAR int V173 cse2 u:1 ***** BB236 STMT00485 ( INL66 @ 0x000[E-] ... ??? ) <- INLRT @ ??? N006 ( 4, 3) [002444] -A--GO--R-- * ASG int $845 N005 ( 1, 1) [002443] D------N--- +--* LCL_VAR int V136 tmp96 d:1 $VN.Void N004 ( 4, 3) [002442] n---GO----- \--* IND int N003 ( 3, 4) [003109] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000390] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- \--* CNS_INT long 8 $201 ***** BB236 STMT00487 ( INL66 @ 0x007[E-] ... ??? ) <- INLRT @ ??? N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002450] N---GO-N-U- \--* GE int N001 ( 1, 1) [002445] ----------- +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002484] n---GO----- \--* IND int N004 ( 3, 4) [003113] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002446] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- \--* CNS_INT long 24 $20c ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ***** BB237 STMT00489 ( INL66 @ 0x015[E-] ... ??? ) <- INLRT @ ??? N005 ( 3, 4) [002460] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002459] D------N--- +--* LCL_VAR byref V138 tmp98 d:1 $VN.Void N003 ( 3, 4) [003119] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003117] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- \--* CNS_INT long 16 $200 ***** BB237 STMT00490 ( INL66 @ ??? ... ??? ) <- INLRT @ ??? N017 ( 22, 24) [002473] -A-XGO----- * ASG short N015 ( 20, 22) [002470] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002464] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002457] ----------- | | +--* LCL_VAR int V136 tmp96 u:1 N005 ( 4, 3) [002463] n---GO----- | | \--* IND int N004 ( 3, 4) [003122] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002462] ----------- | | +--* LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003123] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002469] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002468] n---GO----- | +--* IND byref N007 ( 1, 1) [002461] ----------- | | \--* LCL_VAR byref V138 tmp98 u:1 (last use) $25c N012 ( 4, 6) [002467] ----------- | \--* LSH long N010 ( 2, 3) [002465] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002458] ----------- | | \--* LCL_VAR int V136 tmp96 u:1 N011 ( 1, 2) [002466] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002471] ----------- \--* LCL_VAR int V137 tmp97 u:1 (last use) ***** BB237 STMT00491 ( INL66 @ 0x023[E-] ... ??? ) <- INLRT @ ??? N008 ( 8, 8) [002479] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002478] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003125] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002474] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002477] ----------- \--* ADD int N001 ( 1, 1) [002475] ----------- +--* LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- \--* CNS_INT int 1 $c1 ------------ BB238 [000..000), preds={BB236} succs={BB239} ***** BB238 STMT00488 ( INL66 @ 0x02D[E-] ... ??? ) <- INLRT @ ??? N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002452] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- arg2 in x1 +--* LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ***** BB239 STMT00527 ( ??? ... ??? ) N006 ( 0, 0) [003234] -A------R-- * ASG int $VN.Void N005 ( 0, 0) [003232] D------N--- +--* LCL_VAR int V16 loc12 d:6 $VN.Void N004 ( 0, 0) [003233] ----------- \--* PHI int $b08 N001 ( 0, 0) [003454] ----------- pred BB232 +--* PHI_ARG int V16 loc12 u:5 $898 N002 ( 0, 0) [003453] ----------- pred BB235 +--* PHI_ARG int V16 loc12 u:8 $952 N003 ( 0, 0) [003452] ----------- pred BB238 \--* PHI_ARG int V16 loc12 u:7 ***** BB239 STMT00091 ( 0x788[E-] ... ??? ) N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void N003 ( 3, 3) [000377] J------N--- \--* GE int $c42 N001 ( 1, 1) [000372] ----------- +--* LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- \--* LCL_VAR int V179 cse8 u:1 $342 ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ***** BB240 STMT00092 ( 0x793[E-] ... 0x79E ) N014 ( 14, 16) [000389] -A-XG------ * JTRUE void $c02 N013 ( 12, 14) [000388] JA-XG--N--- \--* EQ int N011 ( 10, 11) [003643] -A-XG------ +--* COMMA int N009 ( 9, 10) [003641] -A-XG---R-- | +--* ASG int $VN.Void N008 ( 1, 1) [003640] D------N--- | | +--* LCL_VAR int V173 cse2 d:1 $VN.Void N007 ( 9, 10) [000386] ---XG------ | | \--* IND ushort N006 ( 6, 8) [000385] -------N--- | | \--* ADD long $ad3 N001 ( 1, 1) [000379] ----------- | | +--* LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 4, 6) [000384] ----------- | | \--* LSH long $ad2 N003 ( 2, 3) [000381] ----------- | | +--* CAST long <- int $ad1 N002 ( 1, 1) [000380] ----------- | | | \--* LCL_VAR int V16 loc12 u:6 $b08 N004 ( 1, 2) [000383] ----------- | | \--* CNS_INT long 1 $204 N010 ( 1, 1) [003642] ----------- | \--* LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- \--* CNS_INT int 48 $d8 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} ***** BB242 STMT00494 ( INL69 @ 0x000[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N006 ( 4, 3) [002494] -A-XG---R-- * ASG int $845 N005 ( 1, 1) [002493] D------N--- +--* LCL_VAR int V140 tmp100 d:1 $VN.Void N004 ( 4, 3) [002492] ---XG------ \--* IND int N003 ( 3, 4) [003128] -------N--- \--* ADD byref $25a N001 ( 1, 1) [000590] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- \--* CNS_INT long 8 $201 ***** BB242 STMT00496 ( INL69 @ 0x007[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 N006 ( 6, 5) [002500] N---GO-N-U- \--* GE int N001 ( 1, 1) [002495] ----------- +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002531] n---GO----- \--* IND int N004 ( 3, 4) [003132] -------N--- \--* ADD byref $25b N002 ( 1, 1) [002496] ----------- +--* LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- \--* CNS_INT long 24 $20c ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ***** BB243 STMT00498 ( INL69 @ 0x015[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N005 ( 3, 4) [002509] -A--GO--R-- * ASG byref $VN.Void N004 ( 1, 1) [002508] D------N--- +--* LCL_VAR byref V141 tmp101 d:1 $VN.Void N003 ( 3, 4) [003138] -----O----- \--* ADD byref $25c N001 ( 1, 1) [003136] -----O----- +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- \--* CNS_INT long 16 $200 ***** BB243 STMT00499 ( INL69 @ ??? ... ??? ) <- INLRT @ 0x7A2[E-] N017 ( 22, 24) [002522] -A-XGO----- * ASG short N015 ( 20, 22) [002519] ---XGO-N--- +--* COMMA short N006 ( 9, 11) [002513] ---XGO----- | +--* BOUNDS_CHECK_Rng void N001 ( 1, 1) [002506] ----------- | | +--* LCL_VAR int V140 tmp100 u:1 N005 ( 4, 3) [002512] n---GO----- | | \--* IND int N004 ( 3, 4) [003141] -------N--- | | \--* ADD byref $25d N002 ( 1, 1) [002511] ----------- | | +--* LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- | | \--* CNS_INT long 8 $201 N014 ( 11, 11) [003142] D--XGO-N--- | \--* IND short N013 ( 8, 9) [002518] ----GO-N--- | \--* ADD byref N008 ( 3, 2) [002517] n---GO----- | +--* IND byref N007 ( 1, 1) [002510] ----------- | | \--* LCL_VAR byref V141 tmp101 u:1 (last use) $25c N012 ( 4, 6) [002516] ----------- | \--* LSH long N010 ( 2, 3) [002514] ---------U- | +--* CAST long <- uint N009 ( 1, 1) [002507] ----------- | | \--* LCL_VAR int V140 tmp100 u:1 N011 ( 1, 2) [002515] ----------- | \--* CNS_INT long 1 $204 N016 ( 1, 1) [002520] ----------- \--* LCL_VAR int V18 loc14 u:1 (last use) ***** BB243 STMT00500 ( INL69 @ 0x023[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N008 ( 8, 8) [002528] -A--GO--R-- * ASG int $845 N007 ( 4, 3) [002527] n---GO-N--- +--* IND int $845 N006 ( 3, 4) [003144] -------N--- | \--* ADD byref $25a N004 ( 1, 1) [002523] ----------- | +--* LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- | \--* CNS_INT long 8 $201 N003 ( 3, 4) [002526] ----------- \--* ADD int N001 ( 1, 1) [002524] ----------- +--* LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- \--* CNS_INT int 1 $c1 ------------ BB244 [7A2..7A3) -> BB245 (always), preds={BB215,BB242} succs={BB245} ***** BB244 STMT00497 ( INL69 @ 0x02D[E-] ... ??? ) <- INLRT @ 0x7A2[E-] N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void N001 ( 1, 1) [002502] ----------- this in x0 +--* LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- arg2 in x1 +--* LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000435c58 ftn $53 ------------ BB110 [000..000) (throw), preds={BB91} succs={} ***** BB110 STMT00337 ( INL17 @ 0x029[E-] ... ??? ) <- INLRT @ ??? N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void N001 ( 2, 8) [002701] H---------- r2r cell in x11 \--* CNS_INT(h) long 0x4000000000424a20 ftn $4a ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Determine first cold block No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block [no changes] *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N011 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N015 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N014 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 25, 19) [000034] DACXG------ * STORE_LCL_VAR int V15 loc11 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 21, 20) [001163] DACXG------ * STORE_LCL_VAR int V16 loc12 d:16 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N015 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001558] DA--------- * STORE_LCL_VAR int V152 tmp112 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [000951] DA--GO----- * STORE_LCL_VAR ref V26 loc22 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000961] DA-X------- * STORE_LCL_VAR int V29 loc25 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [001001] DA--------- * STORE_LCL_VAR int V32 loc28 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 20, 18) [001070] DACXG------ * STORE_LCL_VAR ref V33 loc29 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N017 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000836] DA--------- * STORE_LCL_VAR byref V60 tmp20 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000914] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000852] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd LIR BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd LIR BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd LIR BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd LIR BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd LIR BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd LIR BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd LIR BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd LIR BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i LIR BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd LIR BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd LIR BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src LIR BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd LIR BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd LIR BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd LIR BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd LIR BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd LIR BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src LIR BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} [003780] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn $42 /--* t0 byref this in x0 +--* t2543 long r2r cell in x11 N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void [003781] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 1, 2) [000002] ----------- t2 = CNS_INT int 0 $c0 /--* t2 int N003 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 [003782] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] N001 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- t2547 = CNS_INT long 16 $200 /--* t2546 byref +--* t2547 long N003 ( 3, 4) [002548] -----O----- t2548 = * ADD byref $240 /--* t2548 byref N005 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 [003783] ----------- IL_OFFSET void INLRT @ 0x009[E-] N001 ( 1, 2) [001497] ----------- t1497 = CNS_INT int 0 $c0 N002 ( 1, 1) [001502] ----------- t1502 = LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- t2555 = CNS_INT long 8 $201 /--* t1502 byref +--* t2555 long N004 ( 3, 4) [002556] -------N--- t2556 = * ADD byref $241 /--* t2556 byref N005 ( 4, 3) [001503] ---XG------ t1503 = * IND int /--* t1497 int +--* t1503 int N006 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 (last use) $240 /--* t1501 byref N008 ( 3, 2) [001505] n---GO----- t1505 = * IND byref /--* t1505 byref N011 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 N012 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 /--* t2552 long N015 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 N001 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] $246 /--* t2558 byref N003 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 N004 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3710 byref N007 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 N008 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] $342 /--* t2561 int N010 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 N011 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 $342 /--* t3690 int N014 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 [003784] ----------- IL_OFFSET void INLRT @ 0x011[E-] N001 ( 1, 1) [000011] ----------- t11 = LCL_VAR long V17 loc13 u:1 (last use) /--* t11 long N002 ( 4, 3) [000012] ---XG------ t12 = * IND ubyte N003 ( 1, 2) [000013] ----------- t13 = CNS_INT int 0 $c0 /--* t12 ubyte +--* t13 int N004 ( 6, 6) [000014] J--XG--N--- t14 = * EQ int /--* t14 int N005 ( 8, 8) [000015] ---XG------ * JTRUE void ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2565 byref N003 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 N004 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2568 int N006 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 N001 ( 1, 1) [001472] ----------- t1472 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- t2571 = CNS_INT long 8 $201 /--* t1472 byref +--* t2571 long N003 ( 3, 4) [002572] -------N--- t2572 = * ADD byref $247 /--* t2572 byref N004 ( 5, 4) [001473] n---GO----- t1473 = * IND bool N005 ( 1, 2) [001474] ----------- t1474 = CNS_INT int 0 $c0 /--* t1473 bool +--* t1474 int N006 ( 7, 7) [001475] J---GO-N--- t1475 = * NE int /--* t1475 int N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} N001 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2574 byref N003 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 N004 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2577 int N006 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 N001 ( 1, 2) [001489] ----------- t1489 = CNS_INT int 0 $c0 /--* t1489 int N003 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} N001 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2581 byref N003 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 N004 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2584 int N006 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 N001 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 $c1 /--* t1482 int N003 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 ------------ BB05 [025..026), preds={BB01} succs={BB06} N001 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2588 byref N003 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 N004 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2591 int N006 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 N001 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 $c2 /--* t21 int N003 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} N001 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 (last use) $342 /--* t2596 byref +--* t2597 int N003 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct $141 N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2595 struct arg1 x0,x1 +--* t29 int arg2 in x2 +--* t2594 long r2r cell in x11 N006 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int $2c1 /--* t30 int N008 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} [003785] ----------- IL_OFFSET void INLRT @ 0x02D[E-] N001 ( 1, 2) [000035] ----------- t35 = CNS_INT int 0 $c0 /--* t35 int N003 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 [003786] ----------- IL_OFFSET void INLRT @ 0x02F[E-] N001 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 $c4 /--* t38 int N003 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 [003787] ----------- IL_OFFSET void INLRT @ 0x031[E-] N001 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF $c9 /--* t41 int N003 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 [003788] ----------- IL_OFFSET void INLRT @ 0x037[E-] N001 ( 1, 2) [000044] ----------- t44 = CNS_INT int 0 $c0 /--* t44 int N003 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 [003789] ----------- IL_OFFSET void INLRT @ 0x039[E-] N001 ( 1, 2) [002598] ----------- t2598 = CNS_INT int 0 $c0 /--* t2598 int N003 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 [003790] ----------- IL_OFFSET void INLRT @ 0x03C[E-] N001 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 $c4 /--* t50 int N003 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 [003791] ----------- IL_OFFSET void INLRT @ 0x03F[E-] N001 ( 1, 2) [002599] ----------- t2599 = CNS_INT int 0 $c0 /--* t2599 int N003 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 [003792] ----------- IL_OFFSET void INLRT @ 0x042[E-] N001 ( 1, 2) [000056] ----------- t56 = CNS_INT int 0 $c0 /--* t56 int N003 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 [003793] ----------- IL_OFFSET void INLRT @ 0x045[E-] N001 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 $283 /--* t59 int N003 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 [003794] ----------- IL_OFFSET void INLRT @ 0x049[E-] N001 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3712 byref N003 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 [003795] ----------- IL_OFFSET void INLRT @ 0x049[E-] N001 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 $246 /--* t1512 byref N003 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 [003796] ----------- IL_OFFSET void INLRT @ 0x051[E-] N001 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 (last use) $246 /--* t69 byref N003 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 N004 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 (last use) $3c4 /--* t2609 long N007 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} [003797] ----------- IL_OFFSET void INLRT @ 0x05B[E-] N001 ( 1, 1) [001226] ----------- t1226 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- t1227 = CNS_INT int 69 $d2 /--* t1226 int +--* t1227 int N003 ( 3, 4) [001228] N------N-U- t1228 = * GT int /--* t1228 int N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} [003798] ----------- IL_OFFSET void INLRT @ 0x061[E-] N001 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- t1362 = CNS_INT int -34 $d6 /--* t1361 int +--* t1362 int N003 ( 3, 4) [001363] ----------- t1363 = * ADD int /--* t1363 int N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} [003799] ----------- IL_OFFSET void INLRT @ 0x083[E-] N001 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- t1366 = CNS_INT int -44 $d7 /--* t1365 int +--* t1366 int N003 ( 3, 4) [001367] ----------- t1367 = * ADD int /--* t1367 int N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} [003800] ----------- IL_OFFSET void INLRT @ 0x0A1[E-] N001 ( 1, 1) [001369] ----------- t1369 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- t1370 = CNS_INT int 69 $d2 /--* t1369 int +--* t1370 int N003 ( 3, 4) [001371] J------N--- t1371 = * EQ int /--* t1371 int N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} [003801] ----------- IL_OFFSET void INLRT @ 0x0AF[E-] N001 ( 1, 1) [001230] ----------- t1230 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- t1231 = CNS_INT int 92 $d3 /--* t1230 int +--* t1231 int N003 ( 3, 4) [001232] J------N--- t1232 = * EQ int /--* t1232 int N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} [003802] ----------- IL_OFFSET void INLRT @ 0x0B8[E-] N001 ( 1, 1) [001257] ----------- t1257 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- t1258 = CNS_INT int 101 $d4 /--* t1257 int +--* t1258 int N003 ( 3, 4) [001259] J------N--- t1259 = * EQ int /--* t1259 int N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} [003803] ----------- IL_OFFSET void INLRT @ 0x0C1[E-] N001 ( 1, 1) [001352] ----------- t1352 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- t1353 = CNS_INT int 0x2030 $d5 /--* t1352 int +--* t1353 int N003 ( 3, 6) [001354] J------N--- t1354 = * NE int /--* t1354 int N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} [003804] ----------- IL_OFFSET void INLRT @ 0x137[E-] N001 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- t1357 = CNS_INT int 3 $c3 /--* t1356 int +--* t1357 int N003 ( 3, 4) [001358] ----------- t1358 = * ADD int $376 /--* t1358 int N005 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} [003805] ----------- IL_OFFSET void INLRT @ 0x0CF[E-] N001 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- t1431 = CNS_INT int 1 $c1 /--* t1430 int +--* t1431 int N003 ( 3, 4) [001432] ----------- t1432 = * ADD int $68f /--* t1432 int N005 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} [003806] ----------- IL_OFFSET void INLRT @ 0x0D8[E-] N001 ( 1, 1) [001373] ----------- t1373 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- t1374 = CNS_INT int 0x7FFFFFFF $c9 /--* t1373 int +--* t1374 int N003 ( 3, 6) [001375] N------N-U- t1375 = * NE int $68e /--* t1375 int N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} [003807] ----------- IL_OFFSET void INLRT @ 0x0E0[E-] N001 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 $28a /--* t1385 int N003 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} [003808] ----------- IL_OFFSET void INLRT @ 0x0E2[E-] N001 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- t1378 = CNS_INT int 1 $c1 /--* t1377 int +--* t1378 int N003 ( 3, 4) [001379] ----------- t1379 = * ADD int $68f /--* t1379 int N005 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 [003809] ----------- IL_OFFSET void INLRT @ 0x0E6[E-] N001 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 $68f /--* t1382 int N003 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} [003810] ----------- IL_OFFSET void INLRT @ 0x0ED[E-] N001 ( 1, 1) [001388] ----------- t1388 = LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- t1389 = CNS_INT int 0 $c0 /--* t1388 int +--* t1389 int N003 ( 3, 4) [001390] J------N--- t1390 = * GE int $690 /--* t1390 int N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} [003811] ----------- IL_OFFSET void INLRT @ 0x0F4[E-] N001 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 $28a /--* t1392 int N003 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} [003812] ----------- IL_OFFSET void INLRT @ 0x0FB[E-] N001 ( 1, 1) [001395] ----------- t1395 = LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- t1396 = CNS_INT int 0 $c0 /--* t1395 int +--* t1396 int N003 ( 6, 4) [001397] -------N--- t1397 = * LE int $691 N004 ( 1, 1) [001399] ----------- t1399 = LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] ----------- t1400 = CNS_INT int 0 $c0 /--* t1399 int +--* t1400 int N006 ( 6, 4) [001401] -------N--- t1401 = * GE int $690 /--* t1397 int +--* t1401 int N007 ( 13, 9) [003726] J------N--- t3726 = * AND int /--* t3726 int N008 ( 15, 11) [001398] ----------- * JTRUE void $VN.Void ------------ BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} [003813] ----------- IL_OFFSET void INLRT @ 0x102[E-] N001 ( 0, 0) [003727] ----------- NOP void [003814] ----------- IL_OFFSET void INLRT @ 0x109[E-] N001 ( 1, 1) [001403] ----------- t1403 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- t1404 = CNS_INT int 0 $c0 /--* t1403 int +--* t1404 int N003 ( 3, 4) [001405] J------N--- t1405 = * LT int $692 /--* t1405 int N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void ------------ BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} [003815] ----------- IL_OFFSET void INLRT @ 0x10E[E-] N001 ( 1, 1) [001413] ----------- t1413 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- t1414 = LCL_VAR int V04 loc0 u:2 $28a /--* t1413 int +--* t1414 int N003 ( 3, 3) [001415] N------N-U- t1415 = * NE int $693 /--* t1415 int N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} [003816] ----------- IL_OFFSET void INLRT @ 0x113[E-] N001 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- t1421 = CNS_INT int 1 $c1 /--* t1420 int +--* t1421 int N003 ( 3, 4) [001422] ----------- t1422 = * ADD int $694 /--* t1422 int N005 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 ------------ BB28 [11E..121), preds={BB26} succs={BB29} [003817] ----------- IL_OFFSET void INLRT @ 0x11E[E-] N001 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 $c1 /--* t2612 int N003 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 ------------ BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} [003818] ----------- IL_OFFSET void INLRT @ 0x121[E-] N001 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 $28a /--* t1407 int N003 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 [003819] ----------- IL_OFFSET void INLRT @ 0x124[E-] N001 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 $c1 /--* t1410 int N003 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} [003820] ----------- IL_OFFSET void INLRT @ 0x12C[E-] N001 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- t1426 = CNS_INT int 2 $c2 /--* t1425 int +--* t1426 int N003 ( 3, 4) [001427] ----------- t1427 = * ADD int $695 /--* t1427 int N005 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB32} succs={BB32,BB47} [003821] ----------- IL_OFFSET void INLRT @ 0x142[E-] N001 ( 1, 1) [001435] ----------- t1435 = LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- t3693 = LCL_VAR int V179 cse8 u:1 $342 /--* t1435 int +--* t3693 int N003 ( 6, 3) [001440] -------N--- t1440 = * GE int $8b7 N004 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1443 int N006 ( 2, 3) [001444] ----------- t1444 = * CAST long <- int $3de N007 ( 1, 2) [001446] ----------- t1446 = CNS_INT long 1 $204 /--* t1444 long +--* t1446 long N008 ( 4, 6) [001447] ----------- t1447 = * LSH long $3df /--* t1442 long +--* t1447 long N009 ( 6, 8) [001448] -------N--- t1448 = * ADD long $3e0 /--* t1448 long N010 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort /--* t1449 ushort N012 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 N013 ( 1, 1) [003626] ----------- t3626 = LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] ----------- t1450 = CNS_INT int 0 $c0 /--* t3626 int +--* t1450 int N016 ( 15, 14) [001451] ---XG--N--- t1451 = * EQ int /--* t1440 int +--* t1451 int N017 ( 22, 18) [003728] J--XG--N--- t3728 = * AND int /--* t3728 int N018 ( 24, 20) [001441] ---XG------ * JTRUE void $VN.Void ------------ BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} [003822] ----------- IL_OFFSET void INLRT @ 0x150[E-] N001 ( 0, 0) [003729] ----------- NOP void [003823] ----------- IL_OFFSET void INLRT @ 0x15E[E-] N001 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1454 int N003 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 [003824] ----------- IL_OFFSET void INLRT @ 0x15E[E-] N001 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- t1456 = CNS_INT int 1 $c1 /--* t1455 int +--* t1456 int N003 ( 3, 4) [001457] ----------- t1457 = * ADD int $8bc /--* t1457 int N005 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 N001 ( 1, 1) [003628] ----------- t3628 = LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- t1469 = LCL_VAR int V18 loc14 u:5 /--* t3628 int +--* t1469 int N003 ( 3, 3) [001470] N---G--N-U- t1470 = * NE int /--* t1470 int N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 ------------ BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} [003825] ----------- IL_OFFSET void INLRT @ 0x175[E-] N001 ( 1, 1) [001234] ----------- t1234 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- t3694 = LCL_VAR int V179 cse8 u:1 $342 /--* t1234 int +--* t3694 int N003 ( 6, 3) [001239] -------N--- t1239 = * GE int $36c N004 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 $361 /--* t1242 int N006 ( 2, 3) [001243] ----------- t1243 = * CAST long <- int $3c8 N007 ( 1, 2) [001245] ----------- t1245 = CNS_INT long 1 $204 /--* t1243 long +--* t1245 long N008 ( 4, 6) [001246] ----------- t1246 = * LSH long $3c9 /--* t1241 long +--* t1246 long N009 ( 6, 8) [001247] -------N--- t1247 = * ADD long $3ca /--* t1247 long N010 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort /--* t1248 ushort N012 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 N013 ( 1, 1) [003646] ----------- t3646 = LCL_VAR int V174 cse3 N015 ( 1, 2) [001249] ----------- t1249 = CNS_INT int 0 $c0 /--* t3646 int +--* t1249 int N016 ( 15, 14) [001250] ---XG--N--- t1250 = * EQ int /--* t1239 int +--* t1250 int N017 ( 22, 18) [003730] J--XG--N--- t3730 = * AND int /--* t3730 int N018 ( 24, 20) [001240] ---XG------ * JTRUE void $VN.Void ------------ BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} [003826] ----------- IL_OFFSET void INLRT @ 0x183[E-] N001 ( 0, 0) [003731] ----------- NOP void [003827] ----------- IL_OFFSET void INLRT @ 0x18E[E-] N001 ( 1, 1) [001252] ----------- t1252 = LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- t1253 = CNS_INT int 1 $c1 /--* t1252 int +--* t1253 int N003 ( 3, 4) [001254] ----------- t1254 = * ADD int $371 /--* t1254 int N005 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} [003828] ----------- IL_OFFSET void INLRT @ 0x196[E-] N001 ( 1, 1) [001261] ----------- t1261 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- t3695 = LCL_VAR int V179 cse8 u:1 $342 /--* t1261 int +--* t3695 int N003 ( 3, 3) [001266] J------N--- t1266 = * GE int $36c /--* t1266 int N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} [003829] ----------- IL_OFFSET void INLRT @ 0x1A1[E-] N001 ( 1, 1) [001341] ----------- t1341 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001342] ----------- t1342 = LCL_VAR int V16 loc12 u:17 $361 /--* t1342 int N003 ( 2, 3) [001343] ----------- t1343 = * CAST long <- int $3c8 N004 ( 1, 2) [001345] ----------- t1345 = CNS_INT long 1 $204 /--* t1343 long +--* t1345 long N005 ( 4, 6) [001346] ----------- t1346 = * LSH long $3c9 /--* t1341 long +--* t1346 long N006 ( 6, 8) [001347] -------N--- t1347 = * ADD long $3ca /--* t1347 long N007 ( 9, 10) [001348] ---XG------ t1348 = * IND ushort /--* t1348 ushort N009 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 N010 ( 1, 1) [003650] ----------- t3650 = LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- t1349 = CNS_INT int 48 $d8 /--* t3650 int +--* t1349 int N013 ( 12, 14) [001350] J--XG--N--- t1350 = * EQ int /--* t1350 int N014 ( 14, 16) [001351] ---XG------ * JTRUE void $311 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} [003830] ----------- IL_OFFSET void INLRT @ 0x1AE[E-] N001 ( 1, 1) [001268] ----------- t1268 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- t1269 = CNS_INT int 1 $c1 /--* t1268 int +--* t1269 int N003 ( 3, 4) [001270] ----------- t1270 = * ADD int $371 N004 ( 1, 1) [003696] ----------- t3696 = LCL_VAR int V179 cse8 u:1 $342 /--* t1270 int +--* t3696 int N005 ( 5, 6) [001275] J------N--- t1275 = * GE int $681 /--* t1275 int N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} [003831] ----------- IL_OFFSET void INLRT @ 0x1BB[E-] N001 ( 1, 1) [001277] ----------- t1277 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001278] ----------- t1278 = LCL_VAR int V16 loc12 u:17 $361 /--* t1278 int N003 ( 2, 3) [001279] ----------- t1279 = * CAST long <- int $3c8 N004 ( 1, 2) [001281] ----------- t1281 = CNS_INT long 1 $204 /--* t1279 long +--* t1281 long N005 ( 4, 6) [001282] ----------- t1282 = * LSH long $3c9 /--* t1277 long +--* t1282 long N006 ( 6, 8) [001283] -------N--- t1283 = * ADD long $3ca /--* t1283 long N007 ( 9, 10) [001284] ---XG------ t1284 = * IND ushort /--* t1284 ushort N009 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 N010 ( 1, 1) [003654] ----------- t3654 = LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- t1285 = CNS_INT int 43 $d9 /--* t3654 int +--* t1285 int N013 ( 12, 14) [001286] J--XG--N--- t1286 = * EQ int /--* t1286 int N014 ( 14, 16) [001287] ---XG------ * JTRUE void $311 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} [003832] ----------- IL_OFFSET void INLRT @ 0x1C8[E-] N001 ( 1, 1) [003656] ----------- t3656 = LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- t1338 = CNS_INT int 45 $da /--* t3656 int +--* t1338 int N003 ( 3, 4) [001339] N---G--N-U- t1339 = * NE int /--* t1339 int N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} [003833] ----------- IL_OFFSET void INLRT @ 0x1D5[E-] N001 ( 1, 1) [001288] ----------- t1288 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001289] ----------- t1289 = LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- t1290 = CNS_INT int 1 $c1 /--* t1289 int +--* t1290 int N004 ( 3, 4) [001291] ----------- t1291 = * ADD int $371 /--* t1291 int N005 ( 4, 6) [001292] ----------- t1292 = * CAST long <- int $3cb N006 ( 1, 2) [001294] ----------- t1294 = CNS_INT long 1 $204 /--* t1292 long +--* t1294 long N007 ( 6, 9) [001295] ----------- t1295 = * LSH long $3cc /--* t1288 long +--* t1295 long N008 ( 8, 11) [001296] -------N--- t1296 = * ADD long $3cd /--* t1296 long N009 ( 11, 13) [001297] ---XG------ t1297 = * IND ushort N010 ( 1, 2) [001298] ----------- t1298 = CNS_INT int 48 $d8 /--* t1297 ushort +--* t1298 int N011 ( 13, 16) [001299] N--XG--N-U- t1299 = * NE int /--* t1299 int N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} [003834] ----------- IL_OFFSET void INLRT @ 0x1E4[E-] N001 ( 1, 1) [001301] ----------- t1301 = LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- t1302 = CNS_INT int 1 $c1 /--* t1301 int +--* t1302 int N003 ( 3, 4) [001303] ----------- t1303 = * ADD int $942 /--* t1303 int N005 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 N001 ( 1, 1) [001307] ----------- t1307 = LCL_VAR int V73 tmp33 u:1 $942 /--* t1307 int N003 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 N001 ( 1, 1) [001306] ----------- t1306 = LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- t3697 = LCL_VAR int V179 cse8 u:1 $342 /--* t1306 int +--* t3697 int N003 ( 3, 3) [001314] J------N--- t1314 = * GE int $943 /--* t1314 int N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} [003835] ----------- IL_OFFSET void INLRT @ 0x1F4[E-] N001 ( 1, 1) [001319] ----------- t1319 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001320] ----------- t1320 = LCL_VAR int V16 loc12 u:19 $942 /--* t1320 int N003 ( 2, 3) [001321] ----------- t1321 = * CAST long <- int $3e1 N004 ( 1, 2) [001323] ----------- t1323 = CNS_INT long 1 $204 /--* t1321 long +--* t1323 long N005 ( 4, 6) [001324] ----------- t1324 = * LSH long $3e2 /--* t1319 long +--* t1324 long N006 ( 6, 8) [001325] -------N--- t1325 = * ADD long $3e3 /--* t1325 long N007 ( 9, 10) [001326] ---XG------ t1326 = * IND ushort N008 ( 1, 2) [001327] ----------- t1327 = CNS_INT int 48 $d8 /--* t1326 ushort +--* t1327 int N009 ( 11, 13) [001328] J--XG--N--- t1328 = * EQ int /--* t1328 int N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} [003836] ----------- IL_OFFSET void INLRT @ 0x201[E-] N001 ( 1, 2) [002613] ----------- t2613 = CNS_INT int 1 $c1 /--* t2613 int N003 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46} succs={BB48,BB50} [003837] ----------- IL_OFFSET void INLRT @ 0x204[E-] N001 ( 1, 1) [000073] ----------- t73 = LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- t3698 = LCL_VAR int V179 cse8 u:1 $342 /--* t73 int +--* t3698 int N003 ( 3, 3) [000078] J------N--- t78 = * GE int $360 /--* t78 int N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} [003838] ----------- IL_OFFSET void INLRT @ 0x20F[E-] N001 ( 1, 1) [001198] ----------- t1198 = LCL_VAR int V16 loc12 u:2 $28b /--* t1198 int N003 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 [003839] ----------- IL_OFFSET void INLRT @ 0x20F[E-] N001 ( 1, 1) [001199] ----------- t1199 = LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- t1200 = CNS_INT int 1 $c1 /--* t1199 int +--* t1200 int N003 ( 3, 4) [001201] ----------- t1201 = * ADD int $361 /--* t1201 int N005 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 N001 ( 1, 1) [001197] ----------- t1197 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001206] ----------- t1206 = LCL_VAR int V71 tmp31 u:1 (last use) $28b /--* t1206 int N003 ( 2, 3) [001207] ----------- t1207 = * CAST long <- int $3c5 N004 ( 1, 2) [001209] ----------- t1209 = CNS_INT long 1 $204 /--* t1207 long +--* t1209 long N005 ( 4, 6) [001210] ----------- t1210 = * LSH long $3c6 /--* t1197 long +--* t1210 long N006 ( 6, 8) [001211] -------N--- t1211 = * ADD long $3c7 /--* t1211 long N007 ( 9, 10) [001212] ---XG------ t1212 = * IND ushort /--* t1212 ushort N009 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 N001 ( 1, 1) [001216] ----------- t1216 = LCL_VAR int V72 tmp32 u:1 /--* t1216 int N003 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 N001 ( 1, 1) [001215] ----------- t1215 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- t1219 = CNS_INT int 0 $c0 /--* t1215 int +--* t1219 int N003 ( 3, 4) [001220] J------N--- t1220 = * EQ int /--* t1220 int N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} [003840] ----------- IL_OFFSET void INLRT @ 0x222[E-] N001 ( 1, 1) [001222] ----------- t1222 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- t1223 = CNS_INT int 59 $d1 /--* t1222 int +--* t1223 int N003 ( 3, 4) [001224] N------N-U- t1224 = * NE int /--* t1224 int N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} [003841] ----------- IL_OFFSET void INLRT @ 0x22B[E-] N001 ( 1, 2) [000081] ----------- t81 = CNS_INT long 0 $205 /--* t81 long N003 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 [003842] ----------- IL_OFFSET void INLRT @ 0x22F[E-] N001 ( 1, 1) [000084] ----------- t84 = LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- t85 = CNS_INT int 0 $c0 /--* t84 int +--* t85 int N003 ( 3, 4) [000086] J------N--- t86 = * GE int $690 /--* t86 int N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void ------------ BB51 [233..235), preds={BB50} succs={BB52} [003843] ----------- IL_OFFSET void INLRT @ 0x233[E-] N001 ( 1, 1) [001194] ----------- t1194 = LCL_VAR int V04 loc0 u:2 $28a /--* t1194 int N003 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} [003844] ----------- IL_OFFSET void INLRT @ 0x235[E-] N001 ( 1, 1) [000088] ----------- t88 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- t89 = CNS_INT int 0 $c0 /--* t88 int +--* t89 int N003 ( 3, 4) [000090] J------N--- t90 = * LT int $692 /--* t90 int N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} [003845] ----------- IL_OFFSET void INLRT @ 0x23A[E-] N001 ( 1, 1) [001180] ----------- t1180 = LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- t1181 = LCL_VAR int V05 loc1 u:3 $28d /--* t1180 int +--* t1181 int N003 ( 3, 3) [001182] N------N-U- t1182 = * NE int $696 /--* t1182 int N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} [003846] ----------- IL_OFFSET void INLRT @ 0x23F[E-] N001 ( 1, 1) [001187] ----------- t1187 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 1) [001188] ----------- t1188 = LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- t1189 = CNS_INT int 3 $c3 /--* t1188 int +--* t1189 int N004 ( 6, 6) [001190] ----------- t1190 = * MUL int $697 /--* t1187 int +--* t1190 int N005 ( 8, 8) [001191] ----------- t1191 = * SUB int $698 /--* t1191 int N007 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} [003847] ----------- IL_OFFSET void INLRT @ 0x24A[E-] N001 ( 1, 2) [002615] ----------- t2615 = CNS_INT int 1 $c1 /--* t2615 int N003 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} [003848] ----------- IL_OFFSET void INLRT @ 0x24D[E-] N001 ( 1, 1) [000092] ----------- t92 = LCL_VAR long V17 loc13 u:1 /--* t92 long N002 ( 4, 3) [000093] ---XG------ t93 = * IND ubyte N003 ( 1, 2) [000094] ----------- t94 = CNS_INT int 0 $c0 /--* t93 ubyte +--* t94 int N004 ( 6, 6) [000095] J--XG--N--- t95 = * EQ int /--* t95 int N005 ( 8, 8) [000096] ---XG------ * JTRUE void ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} [003849] ----------- IL_OFFSET void INLRT @ 0x252[E-] N001 ( 1, 1) [002618] ----------- t2618 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- t2619 = CNS_INT long 4 $207 /--* t2618 byref +--* t2619 long N003 ( 3, 4) [002620] -----O----- t2620 = * ADD byref $24a /--* t2620 byref N005 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 N001 ( 1, 1) [001131] ----------- t1131 = LCL_VAR byref V69 tmp29 u:1 $24a /--* t1131 byref N002 ( 3, 2) [001132] n---GO----- t1132 = * IND int N003 ( 1, 1) [001133] ----------- t1133 = LCL_VAR int V13 loc9 u:3 (last use) $28e /--* t1132 int +--* t1133 int N004 ( 5, 4) [001134] ----GO----- t1134 = * ADD int N005 ( 1, 1) [001130] ----------- t1130 = LCL_VAR byref V69 tmp29 u:1 (last use) $24a /--* t1130 byref +--* t1134 int [003850] -A--GO----- * STOREIND int [003851] ----------- IL_OFFSET void INLRT @ 0x25E[E-] N001 ( 1, 1) [001137] ----------- t1137 = LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- t1138 = CNS_INT int 0 $c0 /--* t1137 int +--* t1138 int N003 ( 3, 4) [001139] J------N--- t1139 = * NE int $6a7 /--* t1139 int N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} [003852] ----------- IL_OFFSET void INLRT @ 0x262[E-] N001 ( 1, 1) [001171] ----------- t1171 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- t2622 = CNS_INT long 4 $207 /--* t1171 byref +--* t2622 long N003 ( 3, 4) [002623] -------N--- t2623 = * ADD byref $24a /--* t2623 byref N004 ( 4, 3) [001172] n---GO----- t1172 = * IND int N005 ( 1, 1) [001173] ----------- t1173 = LCL_VAR int V04 loc0 u:2 $28a /--* t1172 int +--* t1173 int N006 ( 6, 5) [001174] ----GO----- t1174 = * ADD int N007 ( 1, 1) [001175] ----------- t1175 = LCL_VAR int V05 loc1 u:3 $28d /--* t1174 int +--* t1175 int N008 ( 8, 7) [001176] ----GO----- t1176 = * SUB int /--* t1176 int N010 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} [003853] ----------- IL_OFFSET void INLRT @ 0x26E[E-] N001 ( 1, 1) [001141] ----------- t1141 = LCL_VAR int V04 loc0 u:2 $28a /--* t1141 int N003 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} [003854] ----------- IL_OFFSET void INLRT @ 0x271[E-] N001 ( 1, 1) [001145] ----------- t1145 = LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- t1148 = LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- t2624 = CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- t1150 = CNS_INT int 0 $c0 /--* t1145 int arg2 in x1 +--* t1148 byref arg1 in x0 +--* t2624 long r2r cell in x11 +--* t1150 int arg3 in x2 N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void [003855] ----------- IL_OFFSET void INLRT @ 0x27A[E-] N001 ( 1, 1) [001152] ----------- t1152 = LCL_VAR long V17 loc13 u:1 /--* t1152 long N002 ( 4, 3) [001153] ---XG------ t1153 = * IND ubyte N003 ( 1, 2) [001154] ----------- t1154 = CNS_INT int 0 $c0 /--* t1153 ubyte +--* t1154 int N004 ( 6, 6) [001155] J--XG--N--- t1155 = * NE int /--* t1155 int N005 ( 8, 8) [001156] ---XG------ * JTRUE void ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} [003856] ----------- IL_OFFSET void INLRT @ 0x27F[E-] N001 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] $3ce /--* t3713 byref +--* t2628 long N003 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct $142 N004 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 $c2 /--* t2626 struct arg1 x0,x1 +--* t2625 long r2r cell in x11 +--* t1158 int arg2 in x2 N006 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int $2c4 /--* t1159 int N008 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 [003857] ----------- IL_OFFSET void INLRT @ 0x288[E-] N001 ( 1, 1) [001164] ----------- t1164 = LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- t1165 = LCL_VAR int V15 loc11 u:2 $283 /--* t1164 int +--* t1165 int N003 ( 3, 3) [001166] J------N--- t1166 = * EQ int $6b6 /--* t1166 int N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} [003858] ----------- IL_OFFSET void INLRT @ 0x28E[E-] N001 ( 1, 1) [001168] ----------- t1168 = LCL_VAR int V16 loc12 u:16 (last use) $2c4 /--* t1168 int N003 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} [003859] ----------- IL_OFFSET void INLRT @ 0x297[E-] N001 ( 1, 1) [000097] ----------- t97 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- t2629 = CNS_INT long 10 $206 /--* t97 byref +--* t2629 long N003 ( 3, 4) [002630] -------N--- t2630 = * ADD byref $249 /--* t2630 byref N004 ( 5, 4) [000098] n---GO----- t98 = * IND ubyte N005 ( 1, 2) [000099] ----------- t99 = CNS_INT int 3 $c3 /--* t98 ubyte +--* t99 int N006 ( 7, 7) [000100] J---GO-N--- t100 = * EQ int /--* t100 int N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} [003860] ----------- IL_OFFSET void INLRT @ 0x2A0[E-] N001 ( 1, 1) [001122] ----------- t1122 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- t2631 = CNS_INT long 8 $201 /--* t1122 byref +--* t2631 long N003 ( 3, 4) [002632] -------N--- t2632 = * ADD byref $247 N005 ( 1, 2) [001123] ----------- t1123 = CNS_INT int 0 $c0 /--* t2632 byref +--* t1123 int [003861] -A--GO----- * STOREIND bool ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} [003862] ----------- IL_OFFSET void INLRT @ 0x2A7[E-] N001 ( 1, 1) [000102] ----------- t102 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- t2633 = CNS_INT long 4 $207 /--* t102 byref +--* t2633 long N003 ( 3, 4) [002634] -------N--- t2634 = * ADD byref $24a N005 ( 1, 2) [000103] ----------- t103 = CNS_INT int 0 $c0 /--* t2634 byref +--* t103 int [003863] -A--GO----- * STOREIND int ------------ BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} [003864] ----------- IL_OFFSET void INLRT @ 0x2AE[E-] N001 ( 0, 0) [003778] ----------- NOP void [003865] ----------- IL_OFFSET void INLRT @ 0x2B2[E-] N001 ( 1, 1) [000106] ----------- t106 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- t107 = LCL_VAR int V05 loc1 u:3 $28d /--* t106 int +--* t107 int N003 ( 3, 3) [000108] J------N--- t108 = * LT int $6b7 N004 ( 1, 1) [000110] ----------- t110 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- t111 = LCL_VAR int V06 loc2 u:2 (last use) $284 /--* t110 int +--* t111 int N006 ( 3, 3) [000112] ----------- t112 = * SUB int $6b8 N007 ( 1, 2) [001118] ----------- t1118 = CNS_INT int 0 $c0 /--* t108 int +--* t112 int +--* t1118 int N008 ( 8, 9) [003777] ----------- t3777 = * SELECT int /--* t3777 int N010 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 [003866] ----------- IL_OFFSET void INLRT @ 0x2B5[E-] N001 ( 0, 0) [003779] ----------- NOP void N001 ( 3, 2) [000116] ----------- t116 = LCL_VAR int V44 tmp4 u:1 (last use) $292 /--* t116 int N003 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 [003867] ----------- IL_OFFSET void INLRT @ 0x2B9[E-] N001 ( 0, 0) [003775] ----------- NOP void [003868] ----------- IL_OFFSET void INLRT @ 0x2BD[E-] N001 ( 1, 1) [000119] ----------- t119 = LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- t120 = LCL_VAR int V05 loc1 u:3 $28d /--* t119 int +--* t120 int N003 ( 3, 3) [000121] J------N--- t121 = * GT int $6b9 N004 ( 1, 1) [000123] ----------- t123 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- t124 = LCL_VAR int V07 loc3 u:2 (last use) $285 /--* t123 int +--* t124 int N006 ( 3, 3) [000125] ----------- t125 = * SUB int $6ba N007 ( 1, 2) [001114] ----------- t1114 = CNS_INT int 0 $c0 /--* t121 int +--* t125 int +--* t1114 int N008 ( 8, 9) [003774] ----------- t3774 = * SELECT int /--* t3774 int N010 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 [003869] ----------- IL_OFFSET void INLRT @ 0x2C0[E-] N001 ( 0, 0) [003776] ----------- NOP void N001 ( 3, 2) [000129] ----------- t129 = LCL_VAR int V45 tmp5 u:1 (last use) $293 /--* t129 int N003 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 [003870] ----------- IL_OFFSET void INLRT @ 0x2C4[E-] N001 ( 1, 1) [000132] ----------- t132 = LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- t133 = CNS_INT int 0 $c0 /--* t132 int +--* t133 int N003 ( 3, 4) [000134] J------N--- t134 = * EQ int $6bb /--* t134 int N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} [003871] ----------- IL_OFFSET void INLRT @ 0x2C8[E-] N001 ( 1, 1) [001108] ----------- t1108 = LCL_VAR int V05 loc1 u:3 $28d /--* t1108 int N003 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 [003872] ----------- IL_OFFSET void INLRT @ 0x2CB[E-] N001 ( 1, 2) [001111] ----------- t1111 = CNS_INT int 0 $c0 /--* t1111 int N003 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 ------------ BB74 [2D0..2EE), preds={BB66} succs={BB78} [003873] ----------- IL_OFFSET void INLRT @ 0x2D0[E-] N001 ( 0, 0) [003772] ----------- NOP void [003874] ----------- IL_OFFSET void INLRT @ 0x2D9[E-] N001 ( 1, 1) [000136] ----------- t136 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- t2635 = CNS_INT long 4 $207 /--* t136 byref +--* t2635 long N003 ( 3, 4) [002636] -------N--- t2636 = * ADD byref $24a /--* t2636 byref N004 ( 4, 3) [000137] n---GO----- t137 = * IND int /--* t137 int N006 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 N007 ( 3, 2) [003684] ----------- t3684 = LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- t138 = LCL_VAR int V05 loc1 u:3 $28d /--* t3684 int +--* t138 int N010 ( 13, 10) [000139] J---GO-N--- t139 = * GT int N011 ( 3, 2) [003686] ----------- t3686 = LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- t1104 = LCL_VAR int V05 loc1 u:3 $28d /--* t139 int +--* t3686 int +--* t1104 int N013 ( 18, 14) [003771] ----GO----- t3771 = * SELECT int /--* t3771 int N015 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 [003875] ----------- IL_OFFSET void INLRT @ 0x2DC[E-] N001 ( 0, 0) [003773] ----------- NOP void N001 ( 3, 2) [000146] ----------- t146 = LCL_VAR int V46 tmp6 u:1 (last use) $295 /--* t146 int N003 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 [003876] ----------- IL_OFFSET void INLRT @ 0x2E4[E-] N001 ( 3, 2) [003687] ----------- t3687 = LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- t151 = LCL_VAR int V05 loc1 u:3 $28d /--* t3687 int +--* t151 int N003 ( 5, 4) [000152] ----G------ t152 = * SUB int /--* t152 int N005 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB74} succs={BB79,BB103} [003877] ----------- IL_OFFSET void INLRT @ 0x2EE[E-] N001 ( 1, 1) [000155] ----------- t155 = LCL_VAR int V15 loc11 u:2 $283 /--* t155 int N003 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 [003878] ----------- IL_OFFSET void INLRT @ 0x2F2[E-] [003879] ----------- IL_OFFSET void INL09 @ 0x01F[E-] <- INLRT @ ??? N001 ( 3, 3) [001550] ----------- t1550 = LCL_VAR_ADDR long V47 tmp7 $740 /--* t1550 long N003 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 [003880] ----------- IL_OFFSET void INL09 @ 0x026[E-] <- INLRT @ ??? N001 ( 1, 2) [001556] ----------- t1556 = CNS_INT int 4 $c8 /--* t1556 int N003 ( 1, 3) [001558] DA--------- * STORE_LCL_VAR int V152 tmp112 d:1 [003881] ----------- IL_OFFSET void INLRT @ 0x2FF[E-] N001 ( 1, 1) [002649] ----------- t2649 = LCL_VAR byref V151 tmp111 u:1 (last use) $24b /--* t2649 byref N003 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 N004 ( 1, 2) [003720] ----------- t3720 = CNS_INT int 4 $c8 /--* t3720 int N006 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 [003882] ----------- IL_OFFSET void INLRT @ 0x303[E-] N001 ( 1, 2) [000175] ----------- t175 = CNS_INT int -1 $c4 /--* t175 int N003 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 [003883] ----------- IL_OFFSET void INLRT @ 0x306[E-] N001 ( 1, 1) [000941] ----------- t941 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- t2655 = CNS_INT long 56 Fseq[] $209 /--* t941 ref +--* t2655 long N003 ( 3, 4) [002656] -------N--- t2656 = * ADD byref $24c /--* t2656 byref N004 ( 4, 3) [001570] ---XG------ t1570 = * IND ref /--* t1570 ref N005 ( 6, 5) [000944] ---XG------ t944 = * ARR_LENGTH int N006 ( 1, 2) [000945] ----------- t945 = CNS_INT int 0 $c0 /--* t944 int +--* t945 int N007 ( 11, 8) [000946] ---XG--N--- t946 = * LE int N008 ( 1, 1) [000178] ----------- t178 = LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] ----------- t179 = CNS_INT int 0 $c0 /--* t178 int +--* t179 int N010 ( 6, 4) [000180] -------N--- t180 = * EQ int $70a /--* t946 int +--* t180 int N011 ( 18, 13) [003732] J--XG--N--- t3732 = * AND int /--* t3732 int N012 ( 20, 15) [000181] ---XG------ * JTRUE void $VN.Void ------------ BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} [003884] ----------- IL_OFFSET void INLRT @ 0x30D[E-] N001 ( 0, 0) [003733] ----------- NOP void [003885] ----------- IL_OFFSET void INLRT @ 0x31E[E-] N001 ( 1, 1) [000948] ----------- t948 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- t2657 = CNS_INT long 8 Fseq[] $201 /--* t948 ref +--* t2657 long N003 ( 3, 4) [002658] -------N--- t2658 = * ADD byref $24d /--* t2658 byref N004 ( 4, 3) [000949] n---GO----- t949 = * IND ref /--* t949 ref N006 ( 4, 3) [000951] DA--GO----- * STORE_LCL_VAR ref V26 loc22 d:1 [003886] ----------- IL_OFFSET void INLRT @ 0x326[E-] N001 ( 1, 2) [000952] ----------- t952 = CNS_INT int 0 $c0 /--* t952 int N003 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 [003887] ----------- IL_OFFSET void INLRT @ 0x329[E-] N001 ( 1, 2) [000955] ----------- t955 = CNS_INT int 0 $c0 /--* t955 int N003 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 [003888] ----------- IL_OFFSET void INLRT @ 0x32C[E-] N001 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 /--* t958 ref N002 ( 3, 3) [000959] ---X------- t959 = * ARR_LENGTH int /--* t959 int N004 ( 3, 3) [000961] DA-X------- * STORE_LCL_VAR int V29 loc25 d:1 [003889] ----------- IL_OFFSET void INLRT @ 0x332[E-] N001 ( 1, 1) [000962] ----------- t962 = LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- t963 = CNS_INT int 0 $c0 /--* t962 int +--* t963 int N003 ( 3, 4) [000964] J------N--- t964 = * EQ int /--* t964 int N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void ------------ BB81 [336..33D), preds={BB79} succs={BB82} [003890] ----------- IL_OFFSET void INLRT @ 0x336[E-] N002 ( 1, 1) [002659] ----------- t2659 = LCL_VAR ref V26 loc22 u:1 N003 ( 1, 2) [002666] ----------- t2666 = CNS_INT long 16 $200 /--* t2659 ref +--* t2666 long N004 ( 1, 1) [002667] -------N--- t2667 = * ADD byref /--* t2667 byref N006 ( 4, 3) [002671] n---GO----- t2671 = * IND int /--* t2671 int N009 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} [003891] ----------- IL_OFFSET void INLRT @ 0x33D[E-] N001 ( 1, 1) [000966] ----------- t966 = LCL_VAR int V28 loc24 u:2 $298 /--* t966 int N003 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 N001 ( 1, 1) [000969] ----------- t969 = LCL_VAR int V08 loc4 u:1 $297 /--* t969 int N003 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 [003892] ----------- IL_OFFSET void INLRT @ 0x341[E-] N001 ( 1, 1) [000970] ----------- t970 = LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- t971 = CNS_INT int 0 $c0 /--* t970 int +--* t971 int N003 ( 3, 4) [000972] J------N--- t972 = * LT int $719 /--* t972 int N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} N001 ( 3, 2) [000977] ----------- t977 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t977 int N003 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 N001 ( 1, 2) [001091] ----------- t1091 = CNS_INT int 0 $c0 /--* t1091 int N003 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} N001 ( 3, 2) [000978] ----------- t978 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t978 int N003 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 N001 ( 1, 1) [000979] ----------- t979 = LCL_VAR int V14 loc10 u:1 $296 /--* t979 int N003 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 ------------ BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} N001 ( 3, 2) [000986] ----------- t986 = LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- t987 = LCL_VAR int V66 tmp26 u:1 (last use) $299 /--* t986 int +--* t987 int N003 ( 7, 5) [000988] ----------- t988 = * ADD int $71a /--* t988 int N005 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 [003893] ----------- IL_OFFSET void INLRT @ 0x350[E-] N001 ( 0, 0) [003769] ----------- NOP void [003894] ----------- IL_OFFSET void INLRT @ 0x355[E-] N001 ( 1, 1) [000991] ----------- t991 = LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- t992 = LCL_VAR int V31 loc27 u:1 $71a /--* t991 int +--* t992 int N003 ( 5, 4) [000993] J------N--- t993 = * GT int $71b N004 ( 1, 1) [000995] ----------- t995 = LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- t1087 = LCL_VAR int V31 loc27 u:1 (last use) $71a /--* t993 int +--* t995 int +--* t1087 int N006 ( 10, 8) [003768] ----------- t3768 = * SELECT int /--* t3768 int N008 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 [003895] ----------- IL_OFFSET void INLRT @ 0x359[E-] N001 ( 0, 0) [003770] ----------- NOP void N001 ( 3, 2) [000999] ----------- t999 = LCL_VAR int V67 tmp27 u:1 (last use) $29a /--* t999 int N003 ( 3, 3) [001001] DA--------- * STORE_LCL_VAR int V32 loc28 d:1 [003896] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] N001 ( 1, 1) [003158] ----------- t3158 = LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- t3159 = LCL_VAR int V30 loc26 u:1 $298 /--* t3158 int +--* t3159 int N003 ( 3, 3) [003157] J------N--- t3157 = * LE int $71c /--* t3157 int N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void ------------ BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} [003897] ----------- IL_OFFSET void INLRT @ 0x35E[E-] N001 ( 1, 1) [001006] ----------- t1006 = LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- t1007 = CNS_INT int 0 $c0 /--* t1006 int +--* t1007 int N003 ( 3, 4) [001008] J------N--- t1008 = * EQ int $71e /--* t1008 int N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} [003898] ----------- IL_OFFSET void INLRT @ 0x362[E-] N001 ( 1, 1) [001010] ----------- t1010 = LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- t1011 = CNS_INT int 1 $c1 /--* t1010 int +--* t1011 int N003 ( 3, 4) [001012] ----------- t1012 = * ADD int $71f /--* t1012 int N005 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 [003899] ----------- IL_OFFSET void INLRT @ 0x368[E-] N001 ( 1, 1) [001015] ----------- t1015 = LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- t1574 = LCL_VAR int V144 tmp104 u:3 $29c /--* t1015 int +--* t1574 int N003 ( 3, 3) [001020] J------N--- t1020 = * LT int $720 /--* t1020 int N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} [003900] ----------- IL_OFFSET void INLRT @ 0x373[E-] N001 ( 1, 1) [001578] ----------- t1578 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- t1065 = CNS_INT int 1 $c1 /--* t1578 int +--* t1065 int N003 ( 3, 4) [001066] ----------- t1066 = * LSH int $721 /--* t1066 int N004 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int $3cf N005 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn $49 /--* t1067 long arg1 in x0 +--* t2672 long r2r cell in x11 N006 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 /--* t1068 ref N008 ( 20, 18) [001070] DA-XG------ * STORE_LCL_VAR ref V33 loc29 d:1 [003901] ----------- IL_OFFSET void INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] [003902] ----------- IL_OFFSET void INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001 ( 1, 1) [002689] ----------- t2689 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- t2690 = CNS_INT long 16 Fseq[] $200 /--* t2689 ref +--* t2690 long N003 ( 3, 4) [002691] -----O----- t2691 = * ADD byref $253 /--* t2691 byref N005 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 [003903] ----------- IL_OFFSET void INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001 ( 1, 1) [001607] ----------- t1607 = LCL_VAR ref V33 loc29 u:1 $800 /--* t1607 ref N002 ( 3, 3) [001608] ---X------- t1608 = * ARR_LENGTH int $2cc /--* t1608 int N004 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 N001 ( 1, 1) [002694] ----------- t2694 = LCL_VAR byref V159 tmp119 u:1 (last use) $382 /--* t2694 byref N003 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 N001 ( 1, 1) [001620] ----------- t1620 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- t1647 = LCL_VAR int V160 tmp120 u:1 (last use) $2a0 /--* t1620 int +--* t1647 int N003 ( 3, 3) [001628] N------N-U- t1628 = * GT int $722 /--* t1628 int N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void ------------ BB95 [000..392), preds={BB91} succs={BB100} [003904] ----------- IL_OFFSET void INL17 @ 0x00F[E-] <- INLRT @ ??? N001 ( 1, 1) [001639] ----------- t1639 = LCL_VAR int V144 tmp104 u:3 (last use) $29c /--* t1639 int N002 ( 2, 3) [001640] ---------U- t1640 = * CAST long <- ulong <- uint $3d0 /--* t1640 long N004 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 [003905] ----------- IL_OFFSET void INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? N001 ( 1, 1) [001663] ----------- t1663 = LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- t1665 = CNS_INT long 2 $20a /--* t1663 long +--* t1665 long N003 ( 3, 4) [001666] ----------- t1666 = * LSH long $3d1 N004 ( 1, 1) [001661] ----------- t1661 = LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- t1662 = LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- t2700 = CNS_INT(h) long 0x4000000000420490 ftn $4b /--* t1666 long arg3 in x2 +--* t1661 byref arg1 in x0 +--* t1662 byref arg2 in x1 +--* t2700 long r2r cell in x11 N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void [003906] ----------- IL_OFFSET void INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] [003907] ----------- IL_OFFSET void INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001 ( 1, 1) [002718] ----------- t2718 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- t2719 = CNS_INT long 16 Fseq[] $200 /--* t2718 ref +--* t2719 long N003 ( 3, 4) [002720] -----O----- t2720 = * ADD byref $253 /--* t2720 byref N005 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 [003908] ----------- IL_OFFSET void INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 (last use) $800 /--* t1719 ref N002 ( 3, 3) [001720] ---X------- t1720 = * ARR_LENGTH int $2cc /--* t1720 int N004 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 [003909] ----------- IL_OFFSET void INLRT @ 0x391[E-] N001 ( 1, 1) [002723] ----------- t2723 = LCL_VAR byref V163 tmp123 u:1 (last use) $383 /--* t2723 byref N003 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 N004 ( 1, 1) [002726] ----------- t2726 = LCL_VAR int V164 tmp124 u:1 (last use) $2a1 /--* t2726 int N006 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} [003910] ----------- IL_OFFSET void INLRT @ 0x39A[E-] N001 ( 1, 1) [001024] ----------- t1024 = LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- t1028 = LCL_VAR int V144 tmp104 u:4 $2a2 /--* t1024 int +--* t1028 int N003 ( 6, 9) [001029] ---X-O----- * BOUNDS_CHECK_Rng void $334 N004 ( 1, 1) [001033] ----------- t1033 = LCL_VAR byref V143 tmp103 u:4 $384 N005 ( 1, 1) [001025] ----------- t1025 = LCL_VAR int V20 loc16 u:11 $71f /--* t1025 int N006 ( 2, 3) [001030] ---------U- t1030 = * CAST long <- uint $3d2 N007 ( 1, 2) [001031] ----------- t1031 = CNS_INT long 2 $20a /--* t1030 long +--* t1031 long N008 ( 4, 6) [001032] ----------- t1032 = * LSH long $3d3 /--* t1033 byref +--* t1032 long N009 ( 6, 8) [001034] -----O-N--- t1034 = * ADD byref $255 N012 ( 1, 1) [001036] ----------- t1036 = LCL_VAR int V28 loc24 u:3 $29f /--* t1034 byref +--* t1036 int [003911] -A-XGO----- * STOREIND int [003912] ----------- IL_OFFSET void INLRT @ 0x3A6[E-] N001 ( 1, 1) [001039] ----------- t1039 = LCL_VAR int V27 loc23 u:2 $29e N002 ( 1, 1) [001040] ----------- t1040 = LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- t1041 = CNS_INT int -1 $c4 /--* t1040 int +--* t1041 int N004 ( 3, 4) [001042] ----------- t1042 = * ADD int /--* t1039 int +--* t1042 int N005 ( 5, 6) [001043] J------N--- t1043 = * GE int /--* t1043 int N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} [003913] ----------- IL_OFFSET void INLRT @ 0x3AE[E-] N001 ( 1, 1) [001050] ----------- t1050 = LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- t1051 = CNS_INT int 1 $c1 /--* t1050 int +--* t1051 int N003 ( 3, 4) [001052] ----------- t1052 = * ADD int $727 /--* t1052 int N005 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 [003914] ----------- IL_OFFSET void INLRT @ 0x3B4[E-] N001 ( 1, 1) [001056] ----------- t1056 = LCL_VAR int V27 loc23 u:4 $727 N002 ( 1, 1) [001055] ----------- t1055 = LCL_VAR ref V26 loc22 u:1 /--* t1055 ref N003 ( 3, 3) [002732] ---X------- t2732 = * ARR_LENGTH int /--* t1056 int +--* t2732 int N004 ( 8, 11) [002733] ---X-O----- * BOUNDS_CHECK_Rng void N005 ( 1, 1) [002730] ----------- t2730 = LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- t2737 = CNS_INT long 16 $200 /--* t2730 ref +--* t2737 long N007 ( 3, 4) [002738] ----------- t2738 = * ADD byref N008 ( 1, 1) [002731] ----------- t2731 = LCL_VAR int V27 loc23 u:4 $727 /--* t2731 int N009 ( 2, 3) [002734] ---------U- t2734 = * CAST long <- uint $3d4 N010 ( 1, 2) [002735] -------N--- t2735 = CNS_INT long 2 $20a /--* t2734 long +--* t2735 long N011 ( 4, 6) [002736] ----------- t2736 = * LSH long $3d5 /--* t2738 byref +--* t2736 long N012 ( 7, 10) [002739] -------N--- t2739 = * ADD byref /--* t2739 byref N014 ( 10, 12) [002742] n---GO----- t2742 = * IND int /--* t2742 int N017 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} [003915] ----------- IL_OFFSET void INLRT @ 0x3BB[E-] N001 ( 1, 1) [001045] ----------- t1045 = LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- t1046 = LCL_VAR int V30 loc26 u:3 $2a3 /--* t1045 int +--* t1046 int N003 ( 3, 3) [001047] ----------- t1047 = * ADD int $72b /--* t1047 int N005 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 [003916] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] N001 ( 1, 1) [001002] ----------- t1002 = LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- t1003 = LCL_VAR int V28 loc24 u:4 $72b /--* t1002 int +--* t1003 int N003 ( 3, 3) [001004] J------N--- t1004 = * GT int $72c /--* t1004 int N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB85,BB89,BB102} succs={BB104,BB112} [003917] ----------- IL_OFFSET void INLRT @ 0x3C8[E-] N001 ( 1, 1) [000182] ----------- t182 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- t2743 = CNS_INT long 8 $201 /--* t182 byref +--* t2743 long N003 ( 3, 4) [002744] -------N--- t2744 = * ADD byref $247 /--* t2744 byref N004 ( 5, 4) [000183] n---GO----- t183 = * IND bool N005 ( 1, 2) [000184] ----------- t184 = CNS_INT int 0 $c0 /--* t183 bool +--* t184 int N006 ( 10, 7) [000185] ----GO-N--- t185 = * EQ int N007 ( 1, 1) [000927] ----------- t927 = LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] ----------- t928 = CNS_INT int 0 $c0 /--* t927 int +--* t928 int N009 ( 6, 4) [000929] -------N--- t929 = * NE int $733 /--* t185 int +--* t929 int N010 ( 17, 12) [003734] J---GO-N--- t3734 = * AND int /--* t3734 int N011 ( 19, 14) [000186] ----GO----- * JTRUE void $301 ------------ BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} [003918] ----------- IL_OFFSET void INLRT @ 0x3D0[E-] N001 ( 0, 0) [003735] ----------- NOP void [003919] ----------- IL_OFFSET void INLRT @ 0x3D4[E-] N001 ( 1, 1) [000931] ----------- t931 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- t2745 = CNS_INT long 4 $207 /--* t931 byref +--* t2745 long N003 ( 3, 4) [002746] -------N--- t2746 = * ADD byref $24a /--* t2746 byref N004 ( 4, 3) [000932] n---GO----- t932 = * IND int N005 ( 1, 2) [000933] ----------- t933 = CNS_INT int 0 $c0 /--* t932 int +--* t933 int N006 ( 6, 6) [000934] J---GO-N--- t934 = * EQ int /--* t934 int N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} [003920] ----------- IL_OFFSET void INLRT @ 0x3DC[E-] N001 ( 1, 1) [000937] ----------- t937 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- t2747 = CNS_INT long 40 Fseq[] $20b /--* t937 ref +--* t2747 long N003 ( 3, 4) [002748] -------N--- t2748 = * ADD byref $259 /--* t2748 byref N004 ( 4, 3) [001730] ---XG------ t1730 = * IND ref /--* t1730 ref N006 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 [003921] ----------- IL_OFFSET void INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001732] ----------- t1732 = LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- t1733 = CNS_INT ref null $VN.Null /--* t1732 ref +--* t1733 ref N003 ( 3, 4) [001734] J------N--- t1734 = * EQ int /--* t1734 int N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} [003922] ----------- IL_OFFSET void INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [000936] ----------- t936 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- t2749 = CNS_INT long 8 $201 /--* t936 byref +--* t2749 long N003 ( 3, 4) [002750] -------N--- t2750 = * ADD byref $25a /--* t2750 byref N004 ( 4, 3) [001736] ---XG------ t1736 = * IND int /--* t1736 int N006 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 [003923] ----------- IL_OFFSET void INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001739] ----------- t1739 = LCL_VAR ref V86 tmp46 u:1 /--* t1739 ref N002 ( 3, 3) [001740] ---X------- t1740 = * ARR_LENGTH int N003 ( 1, 2) [001741] ----------- t1741 = CNS_INT int 1 $c1 /--* t1740 int +--* t1741 int N004 ( 8, 6) [001742] N--X---N-U- t1742 = * NE int N005 ( 3, 2) [001747] ----------- t1747 = LCL_VAR int V87 tmp47 u:1 N006 ( 1, 1) [001748] ----------- t1748 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002753] ----------- t2753 = CNS_INT long 24 $20c /--* t1748 byref +--* t2753 long N008 ( 3, 4) [002754] -------N--- t2754 = * ADD byref $25b /--* t2754 byref N009 ( 4, 3) [001786] n---GO----- t1786 = * IND int /--* t1747 int +--* t1786 int N010 ( 11, 6) [001752] N---GO-N-U- t1752 = * GE int /--* t1742 int +--* t1752 int N011 ( 20, 13) [003736] J--XGO-N--- t3736 = * AND int /--* t3736 int N012 ( 22, 15) [001743] ---XGO----- * JTRUE void ------------ BB108 [3DC..3DD), preds={BB107} succs={BB112} [003924] ----------- IL_OFFSET void INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] N001 ( 0, 0) [003737] ----------- NOP void [003925] ----------- IL_OFFSET void INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [002758] ----------- t2758 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- t2759 = CNS_INT long 16 $200 /--* t2758 byref +--* t2759 long N003 ( 3, 4) [002760] -----O----- t2760 = * ADD byref $25c /--* t2760 byref N005 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 [003926] ----------- IL_OFFSET void INL26 @ ??? <- INLRT @ 0x3DC[E-] N001 ( 3, 2) [001756] ----------- t1756 = LCL_VAR int V87 tmp47 u:1 N002 ( 1, 1) [001761] ----------- t1761 = LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- t2762 = CNS_INT long 8 $201 /--* t1761 byref +--* t2762 long N004 ( 3, 4) [002763] -------N--- t2763 = * ADD byref $25d /--* t2763 byref N005 ( 4, 3) [001762] n---GO----- t1762 = * IND int /--* t1756 int +--* t1762 int N006 ( 11, 12) [001763] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [001760] ----------- t1760 = LCL_VAR byref V88 tmp48 u:1 (last use) $25c /--* t1760 byref N008 ( 3, 2) [001767] n---GO----- t1767 = * IND byref N009 ( 3, 2) [001757] ----------- t1757 = LCL_VAR int V87 tmp47 u:1 /--* t1757 int N010 ( 4, 4) [001764] ---------U- t1764 = * CAST long <- uint N011 ( 1, 2) [001765] ----------- t1765 = CNS_INT long 1 $204 /--* t1764 long +--* t1765 long N012 ( 6, 7) [001766] ----------- t1766 = * LSH long /--* t1767 byref +--* t1766 long N013 ( 10, 10) [001768] ----GO-N--- t1768 = * ADD byref N017 ( 1, 1) [002765] ----------- t2765 = LCL_VAR ref V86 tmp46 u:1 (last use) N018 ( 1, 2) [002771] ----------- t2771 = CNS_INT long 12 $20d /--* t2765 ref +--* t2771 long N019 ( 1, 1) [002772] -------N--- t2772 = * ADD byref /--* t2772 byref N021 ( 5, 4) [002777] n---GO----- t2777 = * IND ushort /--* t1768 byref +--* t2777 ushort [003927] -A-XGO----- * STOREIND short [003928] ----------- IL_OFFSET void INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] N001 ( 3, 2) [001777] ----------- t1777 = LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- t1778 = CNS_INT int 1 $c1 /--* t1777 int +--* t1778 int N003 ( 5, 5) [001779] ----------- t1779 = * ADD int N004 ( 1, 1) [001776] ----------- t1776 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- t2778 = CNS_INT long 8 $201 /--* t1776 byref +--* t2778 long N006 ( 3, 4) [002779] -------N--- t2779 = * ADD byref $25a /--* t2779 byref +--* t1779 int [003929] -A--GO----- * STOREIND int ------------ BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} [003930] ----------- IL_OFFSET void INLRT @ 0x3E8[E-] N001 ( 1, 2) [002781] ----------- t2781 = CNS_INT int 0 $c0 /--* t2781 int N003 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 [003931] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] N001 ( 1, 1) [003714] ----------- t3714 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3714 byref N003 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 [003932] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] N001 ( 1, 1) [001792] ----------- t1792 = LCL_VAR byref V165 tmp125 u:1 $246 /--* t1792 byref N003 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 [003933] ----------- IL_OFFSET void INLRT @ 0x3F3[E-] N001 ( 1, 1) [000197] ----------- t197 = LCL_VAR byref V165 tmp125 u:1 (last use) $246 /--* t197 byref N003 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 N004 ( 1, 1) [002791] ----------- t2791 = LCL_VAR long V169 tmp129 u:1 (last use) $3c4 /--* t2791 long N007 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 [003934] ----------- IL_OFFSET void INLRT @ 0x3F8[E-] N001 ( 1, 1) [000201] ----------- t201 = LCL_VAR long V17 loc13 u:1 /--* t201 long N003 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} [003935] ----------- IL_OFFSET void INLRT @ 0x7AA[E-] N001 ( 1, 1) [000204] ----------- t204 = LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- t3707 = LCL_VAR int V179 cse8 u:1 $342 /--* t204 int +--* t3707 int N003 ( 3, 3) [000209] J------N--- t209 = * GE int $897 /--* t209 int N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} [003936] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] N001 ( 1, 1) [000243] ----------- t243 = LCL_VAR int V16 loc12 u:4 $2ae /--* t243 int N003 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 [003937] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] N001 ( 1, 1) [000244] ----------- t244 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- t245 = CNS_INT int 1 $c1 /--* t244 int +--* t245 int N003 ( 3, 4) [000246] ----------- t246 = * ADD int $898 /--* t246 int N005 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 N001 ( 1, 1) [000242] ----------- t242 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000251] ----------- t251 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae /--* t251 int N003 ( 2, 3) [000252] ----------- t252 = * CAST long <- int $3db N004 ( 1, 2) [000254] ----------- t254 = CNS_INT long 1 $204 /--* t252 long +--* t254 long N005 ( 4, 6) [000255] ----------- t255 = * LSH long $3dc /--* t242 long +--* t255 long N006 ( 6, 8) [000256] -------N--- t256 = * ADD long $3dd /--* t256 long N007 ( 9, 10) [000257] ---XG------ t257 = * IND ushort /--* t257 ushort N009 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 N001 ( 1, 1) [000261] ----------- t261 = LCL_VAR int V50 tmp10 u:1 /--* t261 int N003 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 N001 ( 1, 1) [000260] ----------- t260 = LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- t264 = CNS_INT int 0 $c0 /--* t260 int +--* t264 int N003 ( 3, 4) [000265] J------N--- t265 = * EQ int /--* t265 int N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} [003938] ----------- IL_OFFSET void INLRT @ 0x7C8[E-] N001 ( 1, 1) [000267] ----------- t267 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- t268 = CNS_INT int 59 $d1 /--* t267 int +--* t268 int N003 ( 3, 4) [000269] N------N-U- t269 = * NE int /--* t269 int N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} [003939] ----------- IL_OFFSET void INLRT @ 0x7D1[E-] N001 ( 1, 2) [000212] ----------- t212 = CNS_INT long 0 $205 /--* t212 long N003 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 [003940] ----------- IL_OFFSET void INLRT @ 0x7D5[E-] N001 ( 1, 1) [000215] ----------- t215 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- t3147 = CNS_INT long 8 $201 /--* t215 byref +--* t3147 long N003 ( 3, 4) [003148] -------N--- t3148 = * ADD byref $247 /--* t3148 byref N004 ( 5, 4) [000216] n---GO----- t216 = * IND bool N005 ( 1, 2) [000217] ----------- t217 = CNS_INT int 0 $c0 /--* t216 bool +--* t217 int N006 ( 10, 7) [000218] ----GO-N--- t218 = * EQ int N007 ( 1, 1) [000221] ----------- t221 = LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] ----------- t222 = CNS_INT int 0 $c0 /--* t221 int +--* t222 int N009 ( 6, 4) [000223] -------N--- t223 = * NE int $733 /--* t218 int +--* t223 int N010 ( 17, 12) [003764] J---GO-N--- t3764 = * AND int /--* t3764 int N011 ( 19, 14) [000219] ----GO----- * JTRUE void $301 ------------ BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} [003941] ----------- IL_OFFSET void INLRT @ 0x7DD[E-] N001 ( 0, 0) [003765] ----------- NOP void [003942] ----------- IL_OFFSET void INLRT @ 0x7E1[E-] N001 ( 1, 1) [000225] ----------- t225 = LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- t3149 = CNS_INT long 4 $207 /--* t225 byref +--* t3149 long N003 ( 3, 4) [003150] -------N--- t3150 = * ADD byref $24a /--* t3150 byref N004 ( 4, 3) [000226] n---GO----- t226 = * IND int N005 ( 1, 2) [000227] ----------- t227 = CNS_INT int 0 $c0 /--* t226 int +--* t227 int N006 ( 9, 6) [000228] ----GO-N--- t228 = * NE int N007 ( 1, 1) [000230] ----------- t230 = LCL_VAR byref V00 arg0 u:1 $100 N008 ( 1, 2) [003151] ----------- t3151 = CNS_INT long 8 $201 /--* t230 byref +--* t3151 long N009 ( 3, 4) [003152] -------N--- t3152 = * ADD byref $25a /--* t3152 byref N010 ( 4, 3) [002539] ---XG------ t2539 = * IND int N011 ( 1, 2) [000233] ----------- t233 = CNS_INT int 0 $c0 /--* t2539 int +--* t233 int N012 ( 9, 6) [000234] ---XG--N--- t234 = * LE int /--* t228 int +--* t234 int N013 ( 19, 13) [003766] J--XGO-N--- t3766 = * AND int /--* t3766 int N014 ( 21, 15) [000229] ---XGO----- * JTRUE void $301 ------------ BB251 [7E9..7FF), preds={BB249} succs={BB253} [003943] ----------- IL_OFFSET void INLRT @ 0x7E9[E-] N001 ( 0, 0) [003767] ----------- NOP void [003944] ----------- IL_OFFSET void INLRT @ 0x7F2[E-] N001 ( 1, 1) [000238] ----------- t238 = LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- t3154 = CNS_INT long 40 Fseq[] $20b /--* t238 ref +--* t3154 long N003 ( 3, 4) [003155] -------N--- t3155 = * ADD byref $259 /--* t3155 byref N004 ( 4, 3) [002541] ---XG------ t2541 = * IND ref N005 ( 1, 1) [000236] ----------- t236 = LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- t3153 = CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- t237 = CNS_INT int 0 $c0 /--* t2541 ref arg3 in x2 +--* t236 byref this in x0 +--* t3153 long r2r cell in x11 +--* t237 int arg2 in x1 N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} [003945] ----------- IL_OFFSET void INLRT @ 0x7FF[E-] N001 ( 0, 0) [000220] ----------- RETURN void $VN.Void ------------ BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} [003946] ----------- IL_OFFSET void INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001744] ----------- t1744 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- t1745 = LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- t2780 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1744 byref this in x0 +--* t1745 ref arg2 in x1 +--* t2780 long r2r cell in x11 N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} [003947] ----------- IL_OFFSET void INLRT @ 0x401[E-] N001 ( 1, 1) [000271] ----------- t271 = LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- t272 = CNS_INT int 0 $c0 /--* t271 int +--* t272 int N003 ( 3, 4) [000273] J------N--- t273 = * LE int $89f /--* t273 int N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} [003948] ----------- IL_OFFSET void INLRT @ 0x406[E-] N001 ( 1, 1) [000821] ----------- t821 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- t822 = CNS_INT int 35 $ea /--* t821 int +--* t822 int N003 ( 6, 4) [000823] -------N--- t823 = * EQ int N004 ( 1, 1) [000919] ----------- t919 = LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- t920 = CNS_INT int 46 $eb /--* t919 int +--* t920 int N006 ( 6, 4) [000921] -------N--- t921 = * EQ int /--* t823 int +--* t921 int N007 ( 13, 9) [003738] J------N--- t3738 = * AND int /--* t3738 int N008 ( 15, 11) [000824] ----------- * JTRUE void $VN.Void ------------ BB115 [40C..418) -> BB135 (cond), preds={BB114} succs={BB117,BB135} [003949] ----------- IL_OFFSET void INLRT @ 0x40C[E-] N001 ( 0, 0) [003739] ----------- NOP void [003950] ----------- IL_OFFSET void INLRT @ 0x412[E-] N001 ( 1, 1) [000923] ----------- t923 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- t924 = CNS_INT int 48 $d8 /--* t923 int +--* t924 int N003 ( 3, 4) [000925] J------N--- t925 = * EQ int /--* t925 int N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void ------------ BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} N001 ( 1, 1) [000829] ----------- t829 = LCL_VAR byref V00 arg0 u:1 $100 /--* t829 byref N003 ( 1, 3) [000836] DA--------- * STORE_LCL_VAR byref V60 tmp20 d:1 [003951] ----------- IL_OFFSET void INLRT @ 0x41A[E-] N001 ( 1, 1) [000830] ----------- t830 = LCL_VAR long V36 loc32 u:7 $904 /--* t830 long N002 ( 4, 3) [000831] ---XG------ t831 = * IND ubyte /--* t831 ubyte N004 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 N005 ( 1, 1) [003679] ----------- t3679 = LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- t832 = CNS_INT int 0 $c0 /--* t3679 int +--* t832 int N008 ( 7, 7) [000833] J--XG--N--- t833 = * NE int /--* t833 int N009 ( 9, 9) [000834] ---XG------ * JTRUE void $c1a ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} N001 ( 1, 1) [000838] ----------- t838 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t838 byref N003 ( 1, 3) [000914] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:3 N001 ( 1, 2) [000912] ----------- t912 = CNS_INT int 48 $d8 /--* t912 int N003 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 ------------ BB120 [424..42C), preds={BB118} succs={BB121} N001 ( 1, 1) [000840] ----------- t840 = LCL_VAR long V36 loc32 u:7 $904 /--* t840 long N003 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 N001 ( 1, 1) [000841] ----------- t841 = LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- t843 = CNS_INT long 1 $204 /--* t841 long +--* t843 long N003 ( 3, 4) [000844] ----------- t844 = * ADD long $adc /--* t844 long N005 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 N001 ( 1, 1) [000839] ----------- t839 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t839 byref N003 ( 1, 3) [000852] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:2 N001 ( 1, 1) [003681] ----------- t3681 = LCL_VAR int V177 cse6 u:1 /--* t3681 int N003 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} N001 ( 1, 1) [000858] ----------- t858 = LCL_VAR int V63 tmp23 u:1 (last use) $b16 /--* t858 int N002 ( 2, 3) [001796] ----------- t1796 = * CAST int <- ushort <- int $c75 /--* t1796 int N004 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 [003952] ----------- IL_OFFSET void INL29 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000857] ----------- t857 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- t2794 = CNS_INT long 8 $201 /--* t857 byref +--* t2794 long N003 ( 3, 4) [002795] -------N--- t2795 = * ADD byref $25a /--* t2795 byref N004 ( 4, 3) [001797] ---XG------ t1797 = * IND int /--* t1797 int N006 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 [003953] ----------- IL_OFFSET void INL29 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [001800] ----------- t1800 = LCL_VAR int V91 tmp51 u:1 N002 ( 1, 1) [001801] ----------- t1801 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- t2798 = CNS_INT long 24 $20c /--* t1801 byref +--* t2798 long N004 ( 3, 4) [002799] -------N--- t2799 = * ADD byref $25b /--* t2799 byref N005 ( 4, 3) [001839] n---GO----- t1839 = * IND int /--* t1800 int +--* t1839 int N006 ( 6, 5) [001805] N---GO-N-U- t1805 = * GE int /--* t1805 int N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} [003954] ----------- IL_OFFSET void INL29 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [002803] ----------- t2803 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- t2804 = CNS_INT long 16 $200 /--* t2803 byref +--* t2804 long N003 ( 3, 4) [002805] -----O----- t2805 = * ADD byref $25c /--* t2805 byref N005 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 N001 ( 1, 1) [001812] ----------- t1812 = LCL_VAR int V91 tmp51 u:1 N002 ( 1, 1) [001817] ----------- t1817 = LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- t2807 = CNS_INT long 8 $201 /--* t1817 byref +--* t2807 long N004 ( 3, 4) [002808] -------N--- t2808 = * ADD byref $25d /--* t2808 byref N005 ( 4, 3) [001818] n---GO----- t1818 = * IND int /--* t1812 int +--* t1818 int N006 ( 9, 11) [001819] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [001816] ----------- t1816 = LCL_VAR byref V93 tmp53 u:1 (last use) $25c /--* t1816 byref N008 ( 3, 2) [001823] n---GO----- t1823 = * IND byref N009 ( 1, 1) [001813] ----------- t1813 = LCL_VAR int V91 tmp51 u:1 /--* t1813 int N010 ( 2, 3) [001820] ---------U- t1820 = * CAST long <- uint N011 ( 1, 2) [001821] ----------- t1821 = CNS_INT long 1 $204 /--* t1820 long +--* t1821 long N012 ( 4, 6) [001822] ----------- t1822 = * LSH long /--* t1823 byref +--* t1822 long N013 ( 8, 9) [001824] ----GO-N--- t1824 = * ADD byref N016 ( 1, 1) [001826] ----------- t1826 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 /--* t1824 byref +--* t1826 int [003955] -A-XGO----- * STOREIND short [003956] ----------- IL_OFFSET void INL29 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [001830] ----------- t1830 = LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- t1831 = CNS_INT int 1 $c1 /--* t1830 int +--* t1831 int N003 ( 3, 4) [001832] ----------- t1832 = * ADD int N004 ( 1, 1) [001829] ----------- t1829 = LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- t2810 = CNS_INT long 8 $201 /--* t1829 byref +--* t2810 long N006 ( 3, 4) [002811] -------N--- t2811 = * ADD byref $25a /--* t2811 byref +--* t1832 int [003957] -A--GO----- * STOREIND int ------------ BB123 [000..000), preds={BB121} succs={BB124} [003958] ----------- IL_OFFSET void INL29 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [001807] ----------- t1807 = LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- t1808 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- t2812 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t1807 byref this in x0 +--* t1808 int arg2 in x1 +--* t2812 long r2r cell in x11 N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} [003959] ----------- IL_OFFSET void INLRT @ 0x431[E-] N001 ( 1, 1) [000860] ----------- t860 = LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- t861 = CNS_INT int 0 $c0 /--* t860 int +--* t861 int N003 ( 6, 4) [000862] -------N--- t862 = * EQ int $70a N004 ( 1, 1) [000874] ----------- t874 = LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] ----------- t875 = CNS_INT int 1 $c1 /--* t874 int +--* t875 int N006 ( 6, 4) [000876] -------N--- t876 = * LE int $d03 /--* t862 int +--* t876 int N007 ( 13, 9) [003740] J------N--- t3740 = * AND int /--* t3740 int N008 ( 15, 11) [000863] ----------- * JTRUE void $VN.Void ------------ BB125 [435..43F) -> BB134 (cond), preds={BB124} succs={BB127,BB134} [003960] ----------- IL_OFFSET void INLRT @ 0x435[E-] N001 ( 0, 0) [003741] ----------- NOP void [003961] ----------- IL_OFFSET void INLRT @ 0x43A[E-] N001 ( 1, 1) [000885] ----------- t885 = LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- t889 = LCL_VAR int V144 tmp104 u:2 $2a6 /--* t885 int +--* t889 int N003 ( 6, 9) [000890] ---X-O----- * BOUNDS_CHECK_Rng void $c31 N004 ( 1, 1) [000894] ----------- t894 = LCL_VAR byref V143 tmp103 u:2 $385 N005 ( 1, 1) [000886] ----------- t886 = LCL_VAR int V20 loc16 u:7 $b13 /--* t886 int N006 ( 2, 3) [000891] ---------U- t891 = * CAST long <- uint $ae2 N007 ( 1, 2) [000892] ----------- t892 = CNS_INT long 2 $20a /--* t891 long +--* t892 long N008 ( 4, 6) [000893] ----------- t893 = * LSH long $ae3 /--* t894 byref +--* t893 long N009 ( 6, 8) [000895] -----O-N--- t895 = * ADD byref $a6b /--* t895 byref N010 ( 8, 9) [002813] ---XGO----- t2813 = * IND int N012 ( 1, 2) [000898] ----------- t898 = CNS_INT int 1 $c1 /--* t2813 int +--* t898 int N013 ( 16, 21) [000899] ---XGO----- t899 = * ADD int N014 ( 1, 1) [000882] ----------- t882 = LCL_VAR int V08 loc4 u:5 $b15 /--* t899 int +--* t882 int N015 ( 21, 23) [000900] N--XGO-N-U- t900 = * NE int N016 ( 1, 1) [000878] ----------- t878 = LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] ----------- t879 = CNS_INT int 0 $c0 /--* t878 int +--* t879 int N018 ( 6, 4) [000880] -------N--- t880 = * LT int $d04 /--* t900 int +--* t880 int N019 ( 28, 28) [003742] J--XGO-N--- t3742 = * AND int /--* t3742 int N020 ( 30, 30) [000881] ---XGO----- * JTRUE void $VN.Void ------------ BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} [003962] ----------- IL_OFFSET void INLRT @ 0x43F[E-] N001 ( 0, 0) [003743] ----------- NOP void [003963] ----------- IL_OFFSET void INLRT @ 0x44F[E-] N001 ( 1, 1) [000903] ----------- t903 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- t2814 = CNS_INT long 56 Fseq[] $209 /--* t903 ref +--* t2814 long N003 ( 3, 4) [002815] -------N--- t2815 = * ADD byref $24c /--* t2815 byref N004 ( 4, 3) [001843] ---XG------ t1843 = * IND ref /--* t1843 ref N006 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 [003964] ----------- IL_OFFSET void INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001845] ----------- t1845 = LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- t1846 = CNS_INT ref null $VN.Null /--* t1845 ref +--* t1846 ref N003 ( 3, 4) [001847] J------N--- t1847 = * EQ int /--* t1847 int N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void ------------ BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} [003965] ----------- IL_OFFSET void INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [000902] ----------- t902 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- t2816 = CNS_INT long 8 $201 /--* t902 byref +--* t2816 long N003 ( 3, 4) [002817] -------N--- t2817 = * ADD byref $25a /--* t2817 byref N004 ( 4, 3) [001849] n---GO----- t1849 = * IND int /--* t1849 int N006 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 [003966] ----------- IL_OFFSET void INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 /--* t1852 ref N002 ( 3, 3) [001853] ---X------- t1853 = * ARR_LENGTH int /--* t1853 int N004 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 N005 ( 1, 1) [003717] ----------- t3717 = LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- t1854 = CNS_INT int 1 $c1 /--* t3717 int +--* t1854 int N008 ( 9, 7) [001855] N--X---N-U- t1855 = * NE int N009 ( 1, 1) [001860] ----------- t1860 = LCL_VAR int V96 tmp56 u:1 N010 ( 1, 1) [001861] ----------- t1861 = LCL_VAR byref V00 arg0 u:1 $100 N011 ( 1, 2) [002820] ----------- t2820 = CNS_INT long 24 $20c /--* t1861 byref +--* t2820 long N012 ( 3, 4) [002821] -------N--- t2821 = * ADD byref $25b /--* t2821 byref N013 ( 4, 3) [001899] n---GO----- t1899 = * IND int /--* t1860 int +--* t1899 int N014 ( 9, 5) [001865] N---GO-N-U- t1865 = * GE int /--* t1855 int +--* t1865 int N015 ( 19, 13) [003744] J--XGO-N--- t3744 = * AND int /--* t3744 int N016 ( 21, 15) [001856] ---XGO----- * JTRUE void ------------ BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} [003967] ----------- IL_OFFSET void INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] N001 ( 0, 0) [003745] ----------- NOP void [003968] ----------- IL_OFFSET void INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [002825] ----------- t2825 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- t2826 = CNS_INT long 16 $200 /--* t2825 byref +--* t2826 long N003 ( 3, 4) [002827] -----O----- t2827 = * ADD byref $25c /--* t2827 byref N005 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 [003969] ----------- IL_OFFSET void INL32 @ ??? <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001869] ----------- t1869 = LCL_VAR int V96 tmp56 u:1 N002 ( 1, 1) [001874] ----------- t1874 = LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- t2829 = CNS_INT long 8 $201 /--* t1874 byref +--* t2829 long N004 ( 3, 4) [002830] -------N--- t2830 = * ADD byref $25d /--* t2830 byref N005 ( 4, 3) [001875] n---GO----- t1875 = * IND int /--* t1869 int +--* t1875 int N006 ( 9, 11) [001876] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [001873] ----------- t1873 = LCL_VAR byref V97 tmp57 u:1 (last use) $25c /--* t1873 byref N008 ( 3, 2) [001880] n---GO----- t1880 = * IND byref N009 ( 1, 1) [001870] ----------- t1870 = LCL_VAR int V96 tmp56 u:1 /--* t1870 int N010 ( 2, 3) [001877] ---------U- t1877 = * CAST long <- uint N011 ( 1, 2) [001878] ----------- t1878 = CNS_INT long 1 $204 /--* t1877 long +--* t1878 long N012 ( 4, 6) [001879] ----------- t1879 = * LSH long /--* t1880 byref +--* t1879 long N013 ( 8, 9) [001881] ----GO-N--- t1881 = * ADD byref N016 ( 1, 2) [001884] ----------- t1884 = CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- t3719 = LCL_VAR int V181 cse10 u:1 /--* t1884 int +--* t3719 int N018 ( 6, 10) [002835] ---X-O----- * BOUNDS_CHECK_Rng void N019 ( 1, 1) [002832] ----------- t2832 = LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- t2838 = CNS_INT long 12 $20d /--* t2832 ref +--* t2838 long N021 ( 1, 1) [002839] -------N--- t2839 = * ADD byref /--* t2839 byref N023 ( 5, 4) [002844] n---GO----- t2844 = * IND ushort /--* t1881 byref +--* t2844 ushort [003970] -A-XGO----- * STOREIND short [003971] ----------- IL_OFFSET void INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001890] ----------- t1890 = LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- t1891 = CNS_INT int 1 $c1 /--* t1890 int +--* t1891 int N003 ( 3, 4) [001892] ----------- t1892 = * ADD int N004 ( 1, 1) [001889] ----------- t1889 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- t2845 = CNS_INT long 8 $201 /--* t1889 byref +--* t2845 long N006 ( 3, 4) [002846] -------N--- t2846 = * ADD byref $25a /--* t2846 byref +--* t1892 int [003972] -A--GO----- * STOREIND int ------------ BB132 [44F..450), preds={BB129} succs={BB133} [003973] ----------- IL_OFFSET void INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001857] ----------- t1857 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- t1858 = LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- t2847 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1857 byref this in x0 +--* t1858 ref arg2 in x1 +--* t2847 long r2r cell in x11 N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} [003974] ----------- IL_OFFSET void INLRT @ 0x45B[E-] N001 ( 1, 1) [000907] ----------- t907 = LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- t908 = CNS_INT int -1 $c4 /--* t907 int +--* t908 int N003 ( 3, 4) [000909] ----------- t909 = * ADD int $d27 /--* t909 int N005 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 ------------ BB134 [461..46D), preds={BB124,BB125,BB133} succs={BB135} [003975] ----------- IL_OFFSET void INLRT @ 0x461[E-] N001 ( 1, 1) [000864] ----------- t864 = LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- t865 = CNS_INT int -1 $c4 /--* t864 int +--* t865 int N003 ( 3, 4) [000866] ----------- t866 = * ADD int $d29 /--* t866 int N005 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 [003976] ----------- IL_OFFSET void INLRT @ 0x467[E-] N001 ( 1, 1) [000869] ----------- t869 = LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- t870 = CNS_INT int -1 $c4 /--* t869 int +--* t870 int N003 ( 3, 4) [000871] ----------- t871 = * ADD int $d2a /--* t871 int N005 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB134} succs={BB136,BB118} [003977] ----------- IL_OFFSET void INLRT @ 0x46D[E-] N001 ( 1, 1) [000825] ----------- t825 = LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- t826 = CNS_INT int 0 $c0 /--* t825 int +--* t826 int N003 ( 3, 4) [000827] J------N--- t827 = * GT int $c6e /--* t827 int N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} [003978] ----------- IL_OFFSET void INLRT @ 0x472[E-] N001 ( 1, 1) [000275] ----------- t275 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- t276 = CNS_INT int 69 $d2 /--* t275 int +--* t276 int N003 ( 3, 4) [000277] N------N-U- t277 = * GT int /--* t277 int N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} [003979] ----------- IL_OFFSET void INLRT @ 0x478[E-] N001 ( 1, 1) [000593] ----------- t593 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- t594 = CNS_INT int -34 $d6 /--* t593 int +--* t594 int N003 ( 3, 4) [000595] ----------- t595 = * ADD int /--* t595 int N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} [003980] ----------- IL_OFFSET void INLRT @ 0x49A[E-] N001 ( 1, 1) [000597] ----------- t597 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- t598 = CNS_INT int -44 $d7 /--* t597 int +--* t598 int N003 ( 3, 4) [000599] ----------- t599 = * ADD int /--* t599 int N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} [003981] ----------- IL_OFFSET void INLRT @ 0x4B8[E-] N001 ( 1, 1) [000601] ----------- t601 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- t602 = CNS_INT int 69 $d2 /--* t601 int +--* t602 int N003 ( 3, 4) [000603] J------N--- t603 = * EQ int /--* t603 int N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} [003982] ----------- IL_OFFSET void INLRT @ 0x4C6[E-] N001 ( 1, 1) [000279] ----------- t279 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- t280 = CNS_INT int 92 $d3 /--* t279 int +--* t280 int N003 ( 3, 4) [000281] J------N--- t281 = * EQ int /--* t281 int N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} [003983] ----------- IL_OFFSET void INLRT @ 0x4CF[E-] N001 ( 1, 1) [000319] ----------- t319 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- t320 = CNS_INT int 101 $d4 /--* t319 int +--* t320 int N003 ( 3, 4) [000321] J------N--- t321 = * EQ int /--* t321 int N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} [003984] ----------- IL_OFFSET void INLRT @ 0x4D8[E-] N001 ( 1, 1) [000581] ----------- t581 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- t582 = CNS_INT int 0x2030 $d5 /--* t581 int +--* t582 int N003 ( 3, 6) [000583] J------N--- t583 = * NE int /--* t583 int N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} [003985] ----------- IL_OFFSET void INLRT @ 0x598[E-] N001 ( 1, 1) [000586] ----------- t586 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- t2848 = CNS_INT long 136 Fseq[] $20e /--* t586 ref +--* t2848 long N003 ( 3, 4) [002849] -------N--- t2849 = * ADD byref $26c /--* t2849 byref N004 ( 4, 3) [002066] ---XG------ t2066 = * IND ref /--* t2066 ref N006 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} [003986] ----------- IL_OFFSET void INLRT @ 0x4E9[E-] N001 ( 1, 1) [000639] ----------- t639 = LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- t640 = CNS_INT int 0 $c0 /--* t639 int +--* t640 int N003 ( 3, 4) [000641] J------N--- t641 = * GE int $9ff /--* t641 int N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} [003987] ----------- IL_OFFSET void INLRT @ 0x4EE[E-] N001 ( 1, 1) [000731] ----------- t731 = LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- t732 = CNS_INT int 1 $c1 /--* t731 int +--* t732 int N003 ( 3, 4) [000733] ----------- t733 = * ADD int $a88 /--* t733 int N005 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 [003988] ----------- IL_OFFSET void INLRT @ 0x4F4[E-] N001 ( 1, 1) [000736] ----------- t736 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- t737 = LCL_VAR int V06 loc2 u:3 $292 /--* t736 int +--* t737 int N003 ( 3, 3) [000738] J------N--- t738 = * LE int $a89 /--* t738 int N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} [003989] ----------- IL_OFFSET void INLRT @ 0x4F9[E-] N001 ( 1, 2) [000747] ----------- t747 = CNS_INT int 0 $c0 /--* t747 int N003 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} [003990] ----------- IL_OFFSET void INLRT @ 0x4FC[E-] N001 ( 1, 2) [000740] ----------- t740 = CNS_INT int 48 $d8 /--* t740 int N003 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} N001 ( 1, 1) [000744] ----------- t744 = LCL_VAR int V58 tmp18 u:1 (last use) $2bd /--* t744 int N002 ( 2, 3) [002850] ----------- t2850 = * CAST int <- ushort <- int $a8a /--* t2850 int N004 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} [003991] ----------- IL_OFFSET void INLRT @ 0x502[E-] N001 ( 1, 1) [000643] ----------- t643 = LCL_VAR long V36 loc32 u:3 $901 /--* t643 long N002 ( 4, 3) [000644] ---XG------ t644 = * IND ubyte N003 ( 1, 2) [000645] ----------- t645 = CNS_INT int 0 $c0 /--* t644 ubyte +--* t645 int N004 ( 6, 6) [000646] J--XG--N--- t646 = * NE int /--* t646 int N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} [003992] ----------- IL_OFFSET void INLRT @ 0x507[E-] N001 ( 1, 1) [000719] ----------- t719 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- t720 = LCL_VAR int V07 loc3 u:3 $293 /--* t719 int +--* t720 int N003 ( 3, 3) [000721] J------N--- t721 = * GT int $a86 /--* t721 int N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} [003993] ----------- IL_OFFSET void INLRT @ 0x50C[E-] N001 ( 1, 2) [000727] ----------- t727 = CNS_INT int 0 $c0 /--* t727 int N003 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} [003994] ----------- IL_OFFSET void INLRT @ 0x50F[E-] N001 ( 1, 2) [000723] ----------- t723 = CNS_INT int 48 $d8 /--* t723 int N003 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 ------------ BB154 [513..51B), preds={BB150} succs={BB155} [003995] ----------- IL_OFFSET void INLRT @ 0x513[E-] N001 ( 1, 1) [000648] ----------- t648 = LCL_VAR long V36 loc32 u:3 $901 /--* t648 long N003 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 [003996] ----------- IL_OFFSET void INLRT @ 0x513[E-] N001 ( 1, 1) [000649] ----------- t649 = LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- t651 = CNS_INT long 1 $204 /--* t649 long +--* t651 long N003 ( 3, 4) [000652] ----------- t652 = * ADD long $3fb /--* t652 long N005 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 N001 ( 1, 1) [000657] ----------- t657 = LCL_VAR long V56 tmp16 u:1 (last use) $901 /--* t657 long N002 ( 4, 3) [000658] ---XG------ t658 = * IND ubyte /--* t658 ubyte N004 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} N001 ( 1, 1) [000662] ----------- t662 = LCL_VAR int V57 tmp17 u:1 (last use) $2bc /--* t662 int N002 ( 2, 3) [002851] ----------- t2851 = * CAST int <- ushort <- int $a87 /--* t2851 int N004 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} [003997] ----------- IL_OFFSET void INLRT @ 0x51D[E-] N001 ( 1, 1) [000665] ----------- t665 = LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- t666 = CNS_INT int 0 $c0 /--* t665 int +--* t666 int N003 ( 3, 4) [000667] J------N--- t667 = * EQ int $a8b /--* t667 int N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} [003998] ----------- IL_OFFSET void INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [000674] ----------- t674 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- t2852 = CNS_INT long 8 $201 /--* t674 byref +--* t2852 long N003 ( 3, 4) [002853] -------N--- t2853 = * ADD byref $25a /--* t2853 byref N004 ( 4, 3) [001903] ---XG------ t1903 = * IND int /--* t1903 int N006 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 [003999] ----------- IL_OFFSET void INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001906] ----------- t1906 = LCL_VAR int V99 tmp59 u:1 N002 ( 1, 1) [001907] ----------- t1907 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- t2856 = CNS_INT long 24 $20c /--* t1907 byref +--* t2856 long N004 ( 3, 4) [002857] -------N--- t2857 = * ADD byref $25b /--* t2857 byref N005 ( 4, 3) [001942] n---GO----- t1942 = * IND int /--* t1906 int +--* t1942 int N006 ( 6, 5) [001911] N---GO-N-U- t1911 = * GE int /--* t1911 int N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} [004000] ----------- IL_OFFSET void INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [002861] ----------- t2861 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- t2862 = CNS_INT long 16 $200 /--* t2861 byref +--* t2862 long N003 ( 3, 4) [002863] -----O----- t2863 = * ADD byref $25c /--* t2863 byref N005 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 [004001] ----------- IL_OFFSET void INL34 @ ??? <- INLRT @ 0x521[E-] N001 ( 1, 1) [001917] ----------- t1917 = LCL_VAR int V99 tmp59 u:1 N002 ( 1, 1) [001922] ----------- t1922 = LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- t2865 = CNS_INT long 8 $201 /--* t1922 byref +--* t2865 long N004 ( 3, 4) [002866] -------N--- t2866 = * ADD byref $25d /--* t2866 byref N005 ( 4, 3) [001923] n---GO----- t1923 = * IND int /--* t1917 int +--* t1923 int N006 ( 9, 11) [001924] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [001921] ----------- t1921 = LCL_VAR byref V100 tmp60 u:1 (last use) $25c /--* t1921 byref N008 ( 3, 2) [001928] n---GO----- t1928 = * IND byref N009 ( 1, 1) [001918] ----------- t1918 = LCL_VAR int V99 tmp59 u:1 /--* t1918 int N010 ( 2, 3) [001925] ---------U- t1925 = * CAST long <- uint N011 ( 1, 2) [001926] ----------- t1926 = CNS_INT long 1 $204 /--* t1925 long +--* t1926 long N012 ( 4, 6) [001927] ----------- t1927 = * LSH long /--* t1928 byref +--* t1927 long N013 ( 8, 9) [001929] ----GO-N--- t1929 = * ADD byref N016 ( 1, 1) [001931] ----------- t1931 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 /--* t1929 byref +--* t1931 int [004002] -A-XGO----- * STOREIND short [004003] ----------- IL_OFFSET void INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001935] ----------- t1935 = LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- t1936 = CNS_INT int 1 $c1 /--* t1935 int +--* t1936 int N003 ( 3, 4) [001937] ----------- t1937 = * ADD int N004 ( 1, 1) [001934] ----------- t1934 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- t2868 = CNS_INT long 8 $201 /--* t1934 byref +--* t2868 long N006 ( 3, 4) [002869] -------N--- t2869 = * ADD byref $25a /--* t2869 byref +--* t1937 int [004004] -A--GO----- * STOREIND int ------------ BB159 [521..522), preds={BB157} succs={BB160} [004005] ----------- IL_OFFSET void INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001913] ----------- t1913 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- t675 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- t2870 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t1913 byref this in x0 +--* t675 int arg2 in x1 +--* t2870 long r2r cell in x11 N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} [004006] ----------- IL_OFFSET void INLRT @ 0x529[E-] N001 ( 1, 1) [000677] ----------- t677 = LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- t678 = CNS_INT int 0 $c0 /--* t677 int +--* t678 int N003 ( 6, 4) [000679] -------N--- t679 = * EQ int $70a N004 ( 1, 1) [000681] ----------- t681 = LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] ----------- t682 = CNS_INT int 1 $c1 /--* t681 int +--* t682 int N006 ( 6, 4) [000683] -------N--- t683 = * LE int $a93 /--* t679 int +--* t683 int N007 ( 13, 9) [003746] J------N--- t3746 = * AND int /--* t3746 int N008 ( 15, 11) [000680] ----------- * JTRUE void $VN.Void ------------ BB161 [52D..537) -> BB170 (cond), preds={BB160} succs={BB163,BB170} [004007] ----------- IL_OFFSET void INLRT @ 0x52D[E-] N001 ( 0, 0) [003747] ----------- NOP void [004008] ----------- IL_OFFSET void INLRT @ 0x532[E-] N001 ( 1, 1) [000692] ----------- t692 = LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- t696 = LCL_VAR int V144 tmp104 u:2 $2a6 /--* t692 int +--* t696 int N003 ( 6, 9) [000697] ---X-O----- * BOUNDS_CHECK_Rng void $a34 N004 ( 1, 1) [000701] ----------- t701 = LCL_VAR byref V143 tmp103 u:2 $385 N005 ( 1, 1) [000693] ----------- t693 = LCL_VAR int V20 loc16 u:4 $2b3 /--* t693 int N006 ( 2, 3) [000698] ---------U- t698 = * CAST long <- uint $ac0 N007 ( 1, 2) [000699] ----------- t699 = CNS_INT long 2 $20a /--* t698 long +--* t699 long N008 ( 4, 6) [000700] ----------- t700 = * LSH long $ac1 /--* t701 byref +--* t700 long N009 ( 6, 8) [000702] -----O-N--- t702 = * ADD byref $a44 /--* t702 byref N010 ( 8, 9) [002871] ---XGO----- t2871 = * IND int N012 ( 1, 2) [000705] ----------- t705 = CNS_INT int 1 $c1 /--* t2871 int +--* t705 int N013 ( 16, 21) [000706] ---XGO----- t706 = * ADD int N014 ( 1, 1) [000689] ----------- t689 = LCL_VAR int V08 loc4 u:3 $2b5 /--* t706 int +--* t689 int N015 ( 21, 23) [000707] N--XGO-N-U- t707 = * NE int N016 ( 1, 1) [000685] ----------- t685 = LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] ----------- t686 = CNS_INT int 0 $c0 /--* t685 int +--* t686 int N018 ( 6, 4) [000687] -------N--- t687 = * LT int $a94 /--* t707 int +--* t687 int N019 ( 28, 28) [003748] J--XGO-N--- t3748 = * AND int /--* t3748 int N020 ( 30, 30) [000688] ---XGO----- * JTRUE void $VN.Void ------------ BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} [004009] ----------- IL_OFFSET void INLRT @ 0x537[E-] N001 ( 0, 0) [003749] ----------- NOP void [004010] ----------- IL_OFFSET void INLRT @ 0x547[E-] N001 ( 1, 1) [000710] ----------- t710 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- t2872 = CNS_INT long 56 Fseq[] $209 /--* t710 ref +--* t2872 long N003 ( 3, 4) [002873] -------N--- t2873 = * ADD byref $24c /--* t2873 byref N004 ( 4, 3) [001946] ---XG------ t1946 = * IND ref /--* t1946 ref N006 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 [004011] ----------- IL_OFFSET void INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001948] ----------- t1948 = LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- t1949 = CNS_INT ref null $VN.Null /--* t1948 ref +--* t1949 ref N003 ( 3, 4) [001950] J------N--- t1950 = * EQ int /--* t1950 int N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void ------------ BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} [004012] ----------- IL_OFFSET void INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [000709] ----------- t709 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- t2874 = CNS_INT long 8 $201 /--* t709 byref +--* t2874 long N003 ( 3, 4) [002875] -------N--- t2875 = * ADD byref $25a /--* t2875 byref N004 ( 4, 3) [001952] n---GO----- t1952 = * IND int /--* t1952 int N006 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 [004013] ----------- IL_OFFSET void INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001955] ----------- t1955 = LCL_VAR ref V102 tmp62 u:1 /--* t1955 ref N002 ( 3, 3) [001956] ---X------- t1956 = * ARR_LENGTH int N003 ( 1, 2) [001957] ----------- t1957 = CNS_INT int 1 $c1 /--* t1956 int +--* t1957 int N004 ( 8, 6) [001958] N--X---N-U- t1958 = * NE int N005 ( 1, 1) [001963] ----------- t1963 = LCL_VAR int V103 tmp63 u:1 N006 ( 1, 1) [001964] ----------- t1964 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002878] ----------- t2878 = CNS_INT long 24 $20c /--* t1964 byref +--* t2878 long N008 ( 3, 4) [002879] -------N--- t2879 = * ADD byref $25b /--* t2879 byref N009 ( 4, 3) [002002] n---GO----- t2002 = * IND int /--* t1963 int +--* t2002 int N010 ( 9, 5) [001968] N---GO-N-U- t1968 = * GE int /--* t1958 int +--* t1968 int N011 ( 18, 12) [003750] J--XGO-N--- t3750 = * AND int /--* t3750 int N012 ( 20, 14) [001959] ---XGO----- * JTRUE void ------------ BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} [004014] ----------- IL_OFFSET void INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] N001 ( 0, 0) [003751] ----------- NOP void [004015] ----------- IL_OFFSET void INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [002883] ----------- t2883 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- t2884 = CNS_INT long 16 $200 /--* t2883 byref +--* t2884 long N003 ( 3, 4) [002885] -----O----- t2885 = * ADD byref $25c /--* t2885 byref N005 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 [004016] ----------- IL_OFFSET void INL37 @ ??? <- INLRT @ 0x547[E-] N001 ( 1, 1) [001972] ----------- t1972 = LCL_VAR int V103 tmp63 u:1 N002 ( 1, 1) [001977] ----------- t1977 = LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- t2887 = CNS_INT long 8 $201 /--* t1977 byref +--* t2887 long N004 ( 3, 4) [002888] -------N--- t2888 = * ADD byref $25d /--* t2888 byref N005 ( 4, 3) [001978] n---GO----- t1978 = * IND int /--* t1972 int +--* t1978 int N006 ( 9, 11) [001979] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [001976] ----------- t1976 = LCL_VAR byref V104 tmp64 u:1 (last use) $25c /--* t1976 byref N008 ( 3, 2) [001983] n---GO----- t1983 = * IND byref N009 ( 1, 1) [001973] ----------- t1973 = LCL_VAR int V103 tmp63 u:1 /--* t1973 int N010 ( 2, 3) [001980] ---------U- t1980 = * CAST long <- uint N011 ( 1, 2) [001981] ----------- t1981 = CNS_INT long 1 $204 /--* t1980 long +--* t1981 long N012 ( 4, 6) [001982] ----------- t1982 = * LSH long /--* t1983 byref +--* t1982 long N013 ( 8, 9) [001984] ----GO-N--- t1984 = * ADD byref N016 ( 1, 2) [001987] ----------- t1987 = CNS_INT int 0 $c0 N017 ( 1, 1) [001986] ----------- t1986 = LCL_VAR ref V102 tmp62 u:1 /--* t1986 ref N018 ( 3, 3) [002892] ---X------- t2892 = * ARR_LENGTH int /--* t1987 int +--* t2892 int N019 ( 8, 12) [002893] ---X-O----- * BOUNDS_CHECK_Rng void N020 ( 1, 1) [002890] ----------- t2890 = LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- t2896 = CNS_INT long 12 $20d /--* t2890 ref +--* t2896 long N022 ( 1, 1) [002897] -------N--- t2897 = * ADD byref /--* t2897 byref N024 ( 5, 4) [002902] n---GO----- t2902 = * IND ushort /--* t1984 byref +--* t2902 ushort [004017] -A-XGO----- * STOREIND short [004018] ----------- IL_OFFSET void INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001993] ----------- t1993 = LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- t1994 = CNS_INT int 1 $c1 /--* t1993 int +--* t1994 int N003 ( 3, 4) [001995] ----------- t1995 = * ADD int N004 ( 1, 1) [001992] ----------- t1992 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- t2903 = CNS_INT long 8 $201 /--* t1992 byref +--* t2903 long N006 ( 3, 4) [002904] -------N--- t2904 = * ADD byref $25a /--* t2904 byref +--* t1995 int [004019] -A--GO----- * STOREIND int ------------ BB168 [547..548), preds={BB165} succs={BB169} [004020] ----------- IL_OFFSET void INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001960] ----------- t1960 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- t1961 = LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- t2905 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1960 byref this in x0 +--* t1961 ref arg2 in x1 +--* t2905 long r2r cell in x11 N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} [004021] ----------- IL_OFFSET void INLRT @ 0x553[E-] N001 ( 1, 1) [000714] ----------- t714 = LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- t715 = CNS_INT int -1 $c4 /--* t714 int +--* t715 int N003 ( 3, 4) [000716] ----------- t716 = * ADD int $ab7 /--* t716 int N005 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB169} succs={BB245} [004022] ----------- IL_OFFSET void INLRT @ 0x559[E-] N001 ( 1, 1) [000669] ----------- t669 = LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- t670 = CNS_INT int -1 $c4 /--* t669 int +--* t670 int N003 ( 3, 4) [000671] ----------- t671 = * ADD int $ab9 /--* t671 int N005 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} [004023] ----------- IL_OFFSET void INLRT @ 0x564[E-] N001 ( 1, 1) [000605] ----------- t605 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- t606 = CNS_INT int 0 $c0 /--* t605 int +--* t606 int N003 ( 6, 4) [000607] ----------- t607 = * NE int $aba N004 ( 1, 1) [000608] ----------- t608 = LCL_VAR int V21 loc17 u:2 $4c7 /--* t607 int +--* t608 int N005 ( 8, 6) [000609] ----------- t609 = * OR int $abb N006 ( 1, 2) [000610] ----------- t610 = CNS_INT int 0 $c0 /--* t609 int +--* t610 int N007 ( 10, 9) [000611] J------N--- t611 = * NE int $abc /--* t611 int N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void ------------ BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} [004024] ----------- IL_OFFSET void INLRT @ 0x571[E-] N001 ( 1, 1) [000613] ----------- t613 = LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- t614 = CNS_INT int 0 $c0 /--* t613 int +--* t614 int N003 ( 3, 4) [000615] J------N--- t615 = * LT int $abd /--* t615 int N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} [004025] ----------- IL_OFFSET void INLRT @ 0x575[E-] N001 ( 1, 1) [000625] ----------- t625 = LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- t626 = LCL_VAR int V04 loc0 u:2 $28a /--* t625 int +--* t626 int N003 ( 6, 3) [000627] -------N--- t627 = * GE int $abe N004 ( 1, 1) [000629] ----------- t629 = LCL_VAR long V36 loc32 u:3 $901 /--* t629 long N005 ( 4, 3) [000630] ---XG------ t630 = * IND ubyte N006 ( 1, 2) [000631] ----------- t631 = CNS_INT int 0 $c0 /--* t630 ubyte +--* t631 int N007 ( 9, 6) [000632] ---XG--N--- t632 = * EQ int /--* t627 int +--* t632 int N008 ( 16, 10) [003752] J--XG--N--- t3752 = * AND int /--* t3752 int N009 ( 18, 12) [000628] ---XG------ * JTRUE void $VN.Void ------------ BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} [004026] ----------- IL_OFFSET void INLRT @ 0x57C[E-] N001 ( 0, 0) [003753] ----------- NOP void [004027] ----------- IL_OFFSET void INLRT @ 0x584[E-] N001 ( 1, 1) [000618] ----------- t618 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- t2906 = CNS_INT long 48 Fseq[] $20f /--* t618 ref +--* t2906 long N003 ( 3, 4) [002907] -------N--- t2907 = * ADD byref $a4d /--* t2907 byref N004 ( 4, 3) [002006] ---XG------ t2006 = * IND ref /--* t2006 ref N006 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 [004028] ----------- IL_OFFSET void INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002008] ----------- t2008 = LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- t2009 = CNS_INT ref null $VN.Null /--* t2008 ref +--* t2009 ref N003 ( 3, 4) [002010] J------N--- t2010 = * EQ int /--* t2010 int N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void ------------ BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} [004029] ----------- IL_OFFSET void INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [000617] ----------- t617 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- t2908 = CNS_INT long 8 $201 /--* t617 byref +--* t2908 long N003 ( 3, 4) [002909] -------N--- t2909 = * ADD byref $25a /--* t2909 byref N004 ( 4, 3) [002012] ---XG------ t2012 = * IND int /--* t2012 int N006 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 [004030] ----------- IL_OFFSET void INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002015] ----------- t2015 = LCL_VAR ref V106 tmp66 u:1 /--* t2015 ref N002 ( 3, 3) [002016] ---X------- t2016 = * ARR_LENGTH int N003 ( 1, 2) [002017] ----------- t2017 = CNS_INT int 1 $c1 /--* t2016 int +--* t2017 int N004 ( 8, 6) [002018] N--X---N-U- t2018 = * NE int N005 ( 1, 1) [002023] ----------- t2023 = LCL_VAR int V107 tmp67 u:1 N006 ( 1, 1) [002024] ----------- t2024 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002912] ----------- t2912 = CNS_INT long 24 $20c /--* t2024 byref +--* t2912 long N008 ( 3, 4) [002913] -------N--- t2913 = * ADD byref $25b /--* t2913 byref N009 ( 4, 3) [002062] n---GO----- t2062 = * IND int /--* t2023 int +--* t2062 int N010 ( 9, 5) [002028] N---GO-N-U- t2028 = * GE int /--* t2018 int +--* t2028 int N011 ( 18, 12) [003754] J--XGO-N--- t3754 = * AND int /--* t3754 int N012 ( 20, 14) [002019] ---XGO----- * JTRUE void ------------ BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} [004031] ----------- IL_OFFSET void INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] N001 ( 0, 0) [003755] ----------- NOP void [004032] ----------- IL_OFFSET void INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002917] ----------- t2917 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- t2918 = CNS_INT long 16 $200 /--* t2917 byref +--* t2918 long N003 ( 3, 4) [002919] -----O----- t2919 = * ADD byref $25c /--* t2919 byref N005 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 [004033] ----------- IL_OFFSET void INL40 @ ??? <- INLRT @ 0x584[E-] N001 ( 1, 1) [002032] ----------- t2032 = LCL_VAR int V107 tmp67 u:1 N002 ( 1, 1) [002037] ----------- t2037 = LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- t2921 = CNS_INT long 8 $201 /--* t2037 byref +--* t2921 long N004 ( 3, 4) [002922] -------N--- t2922 = * ADD byref $25d /--* t2922 byref N005 ( 4, 3) [002038] n---GO----- t2038 = * IND int /--* t2032 int +--* t2038 int N006 ( 9, 11) [002039] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002036] ----------- t2036 = LCL_VAR byref V108 tmp68 u:1 (last use) $25c /--* t2036 byref N008 ( 3, 2) [002043] n---GO----- t2043 = * IND byref N009 ( 1, 1) [002033] ----------- t2033 = LCL_VAR int V107 tmp67 u:1 /--* t2033 int N010 ( 2, 3) [002040] ---------U- t2040 = * CAST long <- uint N011 ( 1, 2) [002041] ----------- t2041 = CNS_INT long 1 $204 /--* t2040 long +--* t2041 long N012 ( 4, 6) [002042] ----------- t2042 = * LSH long /--* t2043 byref +--* t2042 long N013 ( 8, 9) [002044] ----GO-N--- t2044 = * ADD byref N016 ( 1, 2) [002047] ----------- t2047 = CNS_INT int 0 $c0 N017 ( 1, 1) [002046] ----------- t2046 = LCL_VAR ref V106 tmp66 u:1 /--* t2046 ref N018 ( 3, 3) [002926] ---X------- t2926 = * ARR_LENGTH int /--* t2047 int +--* t2926 int N019 ( 8, 12) [002927] ---X-O----- * BOUNDS_CHECK_Rng void N020 ( 1, 1) [002924] ----------- t2924 = LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- t2930 = CNS_INT long 12 $20d /--* t2924 ref +--* t2930 long N022 ( 1, 1) [002931] -------N--- t2931 = * ADD byref /--* t2931 byref N024 ( 5, 4) [002936] n---GO----- t2936 = * IND ushort /--* t2044 byref +--* t2936 ushort [004034] -A-XGO----- * STOREIND short [004035] ----------- IL_OFFSET void INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002053] ----------- t2053 = LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- t2054 = CNS_INT int 1 $c1 /--* t2053 int +--* t2054 int N003 ( 3, 4) [002055] ----------- t2055 = * ADD int N004 ( 1, 1) [002052] ----------- t2052 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- t2937 = CNS_INT long 8 $201 /--* t2052 byref +--* t2937 long N006 ( 3, 4) [002938] -------N--- t2938 = * ADD byref $25a /--* t2938 byref +--* t2055 int [004036] -A--GO----- * STOREIND int ------------ BB179 [584..585), preds={BB176} succs={BB180} [004037] ----------- IL_OFFSET void INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002020] ----------- t2020 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- t2021 = LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- t2939 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2020 byref this in x0 +--* t2021 ref arg2 in x1 +--* t2939 long r2r cell in x11 N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} [004038] ----------- IL_OFFSET void INLRT @ 0x590[E-] N001 ( 1, 2) [002940] ----------- t2940 = CNS_INT int 1 $c1 /--* t2940 int N003 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} [004039] ----------- IL_OFFSET void INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002068] ----------- t2068 = LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- t2069 = CNS_INT ref null $VN.Null /--* t2068 ref +--* t2069 ref N003 ( 3, 4) [002070] J------N--- t2070 = * EQ int /--* t2070 int N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} [004040] ----------- IL_OFFSET void INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [000585] ----------- t585 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- t2941 = CNS_INT long 8 $201 /--* t585 byref +--* t2941 long N003 ( 3, 4) [002942] -------N--- t2942 = * ADD byref $25a /--* t2942 byref N004 ( 4, 3) [002072] ---XG------ t2072 = * IND int /--* t2072 int N006 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 [004041] ----------- IL_OFFSET void INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002075] ----------- t2075 = LCL_VAR ref V110 tmp70 u:1 /--* t2075 ref N002 ( 3, 3) [002076] ---X------- t2076 = * ARR_LENGTH int N003 ( 1, 2) [002077] ----------- t2077 = CNS_INT int 1 $c1 /--* t2076 int +--* t2077 int N004 ( 8, 6) [002078] N--X---N-U- t2078 = * NE int N005 ( 1, 1) [002083] ----------- t2083 = LCL_VAR int V111 tmp71 u:1 N006 ( 1, 1) [002084] ----------- t2084 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002945] ----------- t2945 = CNS_INT long 24 $20c /--* t2084 byref +--* t2945 long N008 ( 3, 4) [002946] -------N--- t2946 = * ADD byref $25b /--* t2946 byref N009 ( 4, 3) [002122] n---GO----- t2122 = * IND int /--* t2083 int +--* t2122 int N010 ( 9, 5) [002088] N---GO-N-U- t2088 = * GE int /--* t2078 int +--* t2088 int N011 ( 18, 12) [003756] J--XGO-N--- t3756 = * AND int /--* t3756 int N012 ( 20, 14) [002079] ---XGO----- * JTRUE void ------------ BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} [004042] ----------- IL_OFFSET void INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] N001 ( 0, 0) [003757] ----------- NOP void [004043] ----------- IL_OFFSET void INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002950] ----------- t2950 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- t2951 = CNS_INT long 16 $200 /--* t2950 byref +--* t2951 long N003 ( 3, 4) [002952] -----O----- t2952 = * ADD byref $25c /--* t2952 byref N005 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 [004044] ----------- IL_OFFSET void INL43 @ ??? <- INLRT @ 0x598[E-] N001 ( 1, 1) [002092] ----------- t2092 = LCL_VAR int V111 tmp71 u:1 N002 ( 1, 1) [002097] ----------- t2097 = LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- t2954 = CNS_INT long 8 $201 /--* t2097 byref +--* t2954 long N004 ( 3, 4) [002955] -------N--- t2955 = * ADD byref $25d /--* t2955 byref N005 ( 4, 3) [002098] n---GO----- t2098 = * IND int /--* t2092 int +--* t2098 int N006 ( 9, 11) [002099] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002096] ----------- t2096 = LCL_VAR byref V112 tmp72 u:1 (last use) $25c /--* t2096 byref N008 ( 3, 2) [002103] n---GO----- t2103 = * IND byref N009 ( 1, 1) [002093] ----------- t2093 = LCL_VAR int V111 tmp71 u:1 /--* t2093 int N010 ( 2, 3) [002100] ---------U- t2100 = * CAST long <- uint N011 ( 1, 2) [002101] ----------- t2101 = CNS_INT long 1 $204 /--* t2100 long +--* t2101 long N012 ( 4, 6) [002102] ----------- t2102 = * LSH long /--* t2103 byref +--* t2102 long N013 ( 8, 9) [002104] ----GO-N--- t2104 = * ADD byref N016 ( 1, 2) [002107] ----------- t2107 = CNS_INT int 0 $c0 N017 ( 1, 1) [002106] ----------- t2106 = LCL_VAR ref V110 tmp70 u:1 /--* t2106 ref N018 ( 3, 3) [002959] ---X------- t2959 = * ARR_LENGTH int /--* t2107 int +--* t2959 int N019 ( 8, 12) [002960] ---X-O----- * BOUNDS_CHECK_Rng void N020 ( 1, 1) [002957] ----------- t2957 = LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- t2963 = CNS_INT long 12 $20d /--* t2957 ref +--* t2963 long N022 ( 1, 1) [002964] -------N--- t2964 = * ADD byref /--* t2964 byref N024 ( 5, 4) [002969] n---GO----- t2969 = * IND ushort /--* t2104 byref +--* t2969 ushort [004045] -A-XGO----- * STOREIND short [004046] ----------- IL_OFFSET void INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002113] ----------- t2113 = LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- t2114 = CNS_INT int 1 $c1 /--* t2113 int +--* t2114 int N003 ( 3, 4) [002115] ----------- t2115 = * ADD int N004 ( 1, 1) [002112] ----------- t2112 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- t2970 = CNS_INT long 8 $201 /--* t2112 byref +--* t2970 long N006 ( 3, 4) [002971] -------N--- t2971 = * ADD byref $25a /--* t2971 byref +--* t2115 int [004047] -A--GO----- * STOREIND int ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} [004048] ----------- IL_OFFSET void INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002080] ----------- t2080 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- t2081 = LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- t2972 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2080 byref this in x0 +--* t2081 ref arg2 in x1 +--* t2972 long r2r cell in x11 N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} [004049] ----------- IL_OFFSET void INLRT @ 0x5A9[E-] N001 ( 1, 1) [000635] ----------- t635 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- t2973 = CNS_INT long 128 Fseq[] $210 /--* t635 ref +--* t2973 long N003 ( 3, 4) [002974] -------N--- t2974 = * ADD byref $a53 /--* t2974 byref N004 ( 4, 3) [002126] ---XG------ t2126 = * IND ref /--* t2126 ref N006 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 [004050] ----------- IL_OFFSET void INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002128] ----------- t2128 = LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- t2129 = CNS_INT ref null $VN.Null /--* t2128 ref +--* t2129 ref N003 ( 3, 4) [002130] J------N--- t2130 = * EQ int /--* t2130 int N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} [004051] ----------- IL_OFFSET void INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [000634] ----------- t634 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- t2975 = CNS_INT long 8 $201 /--* t634 byref +--* t2975 long N003 ( 3, 4) [002976] -------N--- t2976 = * ADD byref $25a /--* t2976 byref N004 ( 4, 3) [002132] ---XG------ t2132 = * IND int /--* t2132 int N006 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 [004052] ----------- IL_OFFSET void INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002135] ----------- t2135 = LCL_VAR ref V114 tmp74 u:1 /--* t2135 ref N002 ( 3, 3) [002136] ---X------- t2136 = * ARR_LENGTH int N003 ( 1, 2) [002137] ----------- t2137 = CNS_INT int 1 $c1 /--* t2136 int +--* t2137 int N004 ( 8, 6) [002138] N--X---N-U- t2138 = * NE int N005 ( 1, 1) [002143] ----------- t2143 = LCL_VAR int V115 tmp75 u:1 N006 ( 1, 1) [002144] ----------- t2144 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002979] ----------- t2979 = CNS_INT long 24 $20c /--* t2144 byref +--* t2979 long N008 ( 3, 4) [002980] -------N--- t2980 = * ADD byref $25b /--* t2980 byref N009 ( 4, 3) [002182] n---GO----- t2182 = * IND int /--* t2143 int +--* t2182 int N010 ( 9, 5) [002148] N---GO-N-U- t2148 = * GE int /--* t2138 int +--* t2148 int N011 ( 18, 12) [003758] J--XGO-N--- t3758 = * AND int /--* t3758 int N012 ( 20, 14) [002139] ---XGO----- * JTRUE void ------------ BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} [004053] ----------- IL_OFFSET void INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] N001 ( 0, 0) [003759] ----------- NOP void [004054] ----------- IL_OFFSET void INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002984] ----------- t2984 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- t2985 = CNS_INT long 16 $200 /--* t2984 byref +--* t2985 long N003 ( 3, 4) [002986] -----O----- t2986 = * ADD byref $25c /--* t2986 byref N005 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 [004055] ----------- IL_OFFSET void INL46 @ ??? <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002152] ----------- t2152 = LCL_VAR int V115 tmp75 u:1 N002 ( 1, 1) [002157] ----------- t2157 = LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- t2988 = CNS_INT long 8 $201 /--* t2157 byref +--* t2988 long N004 ( 3, 4) [002989] -------N--- t2989 = * ADD byref $25d /--* t2989 byref N005 ( 4, 3) [002158] n---GO----- t2158 = * IND int /--* t2152 int +--* t2158 int N006 ( 9, 11) [002159] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002156] ----------- t2156 = LCL_VAR byref V116 tmp76 u:1 (last use) $25c /--* t2156 byref N008 ( 3, 2) [002163] n---GO----- t2163 = * IND byref N009 ( 1, 1) [002153] ----------- t2153 = LCL_VAR int V115 tmp75 u:1 /--* t2153 int N010 ( 2, 3) [002160] ---------U- t2160 = * CAST long <- uint N011 ( 1, 2) [002161] ----------- t2161 = CNS_INT long 1 $204 /--* t2160 long +--* t2161 long N012 ( 4, 6) [002162] ----------- t2162 = * LSH long /--* t2163 byref +--* t2162 long N013 ( 8, 9) [002164] ----GO-N--- t2164 = * ADD byref N016 ( 1, 2) [002167] ----------- t2167 = CNS_INT int 0 $c0 N017 ( 1, 1) [002166] ----------- t2166 = LCL_VAR ref V114 tmp74 u:1 /--* t2166 ref N018 ( 3, 3) [002993] ---X------- t2993 = * ARR_LENGTH int /--* t2167 int +--* t2993 int N019 ( 8, 12) [002994] ---X-O----- * BOUNDS_CHECK_Rng void N020 ( 1, 1) [002991] ----------- t2991 = LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- t2997 = CNS_INT long 12 $20d /--* t2991 ref +--* t2997 long N022 ( 1, 1) [002998] -------N--- t2998 = * ADD byref /--* t2998 byref N024 ( 5, 4) [003003] n---GO----- t3003 = * IND ushort /--* t2164 byref +--* t3003 ushort [004056] -A-XGO----- * STOREIND short [004057] ----------- IL_OFFSET void INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002173] ----------- t2173 = LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- t2174 = CNS_INT int 1 $c1 /--* t2173 int +--* t2174 int N003 ( 3, 4) [002175] ----------- t2175 = * ADD int N004 ( 1, 1) [002172] ----------- t2172 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- t3004 = CNS_INT long 8 $201 /--* t2172 byref +--* t3004 long N006 ( 3, 4) [003005] -------N--- t3005 = * ADD byref $25a /--* t3005 byref +--* t2175 int [004058] -A--GO----- * STOREIND int ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} [004059] ----------- IL_OFFSET void INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002140] ----------- t2140 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- t2141 = LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- t3006 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2140 byref this in x0 +--* t2141 ref arg2 in x1 +--* t3006 long r2r cell in x11 N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} [004060] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] N001 ( 1, 1) [000805] ----------- t805 = LCL_VAR int V16 loc12 u:13 $b04 /--* t805 int N003 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 [004061] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] N001 ( 1, 1) [000806] ----------- t806 = LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- t807 = CNS_INT int 1 $c1 /--* t806 int +--* t807 int N003 ( 3, 4) [000808] ----------- t808 = * ADD int $bad /--* t808 int N005 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 N001 ( 1, 1) [003629] ----------- t3629 = LCL_VAR int V172 cse1 /--* t3629 int N003 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 [004062] ----------- IL_OFFSET void INL48 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000803] ----------- t803 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- t3007 = CNS_INT long 8 $201 /--* t803 byref +--* t3007 long N003 ( 3, 4) [003008] -------N--- t3008 = * ADD byref $25a /--* t3008 byref N004 ( 4, 3) [002186] ---XG------ t2186 = * IND int /--* t2186 int N006 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 [004063] ----------- IL_OFFSET void INL48 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002189] ----------- t2189 = LCL_VAR int V118 tmp78 u:1 N002 ( 1, 1) [002190] ----------- t2190 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- t3011 = CNS_INT long 24 $20c /--* t2190 byref +--* t3011 long N004 ( 3, 4) [003012] -------N--- t3012 = * ADD byref $25b /--* t3012 byref N005 ( 4, 3) [002228] n---GO----- t2228 = * IND int /--* t2189 int +--* t2228 int N006 ( 6, 5) [002194] N---GO-N-U- t2194 = * GE int /--* t2194 int N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} [004064] ----------- IL_OFFSET void INL48 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003016] ----------- t3016 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- t3017 = CNS_INT long 16 $200 /--* t3016 byref +--* t3017 long N003 ( 3, 4) [003018] -----O----- t3018 = * ADD byref $25c /--* t3018 byref N005 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 N001 ( 1, 1) [002201] ----------- t2201 = LCL_VAR int V118 tmp78 u:1 N002 ( 1, 1) [002206] ----------- t2206 = LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- t3020 = CNS_INT long 8 $201 /--* t2206 byref +--* t3020 long N004 ( 3, 4) [003021] -------N--- t3021 = * ADD byref $25d /--* t3021 byref N005 ( 4, 3) [002207] n---GO----- t2207 = * IND int /--* t2201 int +--* t2207 int N006 ( 9, 11) [002208] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002205] ----------- t2205 = LCL_VAR byref V120 tmp80 u:1 (last use) $25c /--* t2205 byref N008 ( 3, 2) [002212] n---GO----- t2212 = * IND byref N009 ( 1, 1) [002202] ----------- t2202 = LCL_VAR int V118 tmp78 u:1 /--* t2202 int N010 ( 2, 3) [002209] ---------U- t2209 = * CAST long <- uint N011 ( 1, 2) [002210] ----------- t2210 = CNS_INT long 1 $204 /--* t2209 long +--* t2210 long N012 ( 4, 6) [002211] ----------- t2211 = * LSH long /--* t2212 byref +--* t2211 long N013 ( 8, 9) [002213] ----GO-N--- t2213 = * ADD byref N016 ( 1, 1) [002215] ----------- t2215 = LCL_VAR int V119 tmp79 u:1 (last use) /--* t2213 byref +--* t2215 int [004065] -A-XGO----- * STOREIND short [004066] ----------- IL_OFFSET void INL48 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002219] ----------- t2219 = LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- t2220 = CNS_INT int 1 $c1 /--* t2219 int +--* t2220 int N003 ( 3, 4) [002221] ----------- t2221 = * ADD int N004 ( 1, 1) [002218] ----------- t2218 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- t3023 = CNS_INT long 8 $201 /--* t2218 byref +--* t3023 long N006 ( 3, 4) [003024] -------N--- t3024 = * ADD byref $25a /--* t3024 byref +--* t2221 int [004067] -A--GO----- * STOREIND int ------------ BB193 [000..000), preds={BB191} succs={BB194} [004068] ----------- IL_OFFSET void INL48 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002196] ----------- t2196 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- t2197 = LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- t3025 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2196 byref this in x0 +--* t2197 int arg2 in x1 +--* t3025 long r2r cell in x11 N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} [004069] ----------- IL_OFFSET void INLRT @ 0x5CE[E-] N001 ( 1, 1) [000751] ----------- t751 = LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- t3699 = LCL_VAR int V179 cse8 u:1 $342 /--* t751 int +--* t3699 int N003 ( 3, 3) [000756] J------N--- t756 = * GE int $ba4 /--* t756 int N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} [004070] ----------- IL_OFFSET void INLRT @ 0x5D9[E-] N001 ( 1, 1) [000781] ----------- t781 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000782] ----------- t782 = LCL_VAR int V16 loc12 u:13 $b04 /--* t782 int N003 ( 2, 3) [000783] ----------- t783 = * CAST long <- int $aca N004 ( 1, 2) [000785] ----------- t785 = CNS_INT long 1 $204 /--* t783 long +--* t785 long N005 ( 4, 6) [000786] ----------- t786 = * LSH long $acb /--* t781 long +--* t786 long N006 ( 6, 8) [000787] -------N--- t787 = * ADD long $acc /--* t787 long N007 ( 9, 10) [000788] ---XG------ t788 = * IND ushort /--* t788 ushort N009 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 N010 ( 1, 1) [003632] ----------- t3632 = LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- t789 = CNS_INT int 0 $c0 /--* t3632 int +--* t789 int N013 ( 12, 14) [000790] J--XG--N--- t790 = * EQ int /--* t790 int N014 ( 14, 16) [000791] ---XG------ * JTRUE void $bec ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} [004071] ----------- IL_OFFSET void INLRT @ 0x5E4[E-] N001 ( 1, 1) [003634] ----------- t3634 = LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- t800 = LCL_VAR int V18 loc14 u:1 /--* t3634 int +--* t800 int N003 ( 3, 3) [000801] N---G--N-U- t801 = * NE int /--* t801 int N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} [004072] ----------- IL_OFFSET void INLRT @ 0x5F1[E-] N001 ( 1, 1) [000758] ----------- t758 = LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- t3700 = LCL_VAR int V179 cse8 u:1 $342 /--* t758 int +--* t3700 int N003 ( 3, 3) [000763] J------N--- t763 = * GE int $ba4 /--* t763 int N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} [004073] ----------- IL_OFFSET void INLRT @ 0x5FF[E-] N001 ( 1, 1) [000765] ----------- t765 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000766] ----------- t766 = LCL_VAR int V16 loc12 u:13 $b04 /--* t766 int N003 ( 2, 3) [000767] ----------- t767 = * CAST long <- int $aca N004 ( 1, 2) [000769] ----------- t769 = CNS_INT long 1 $204 /--* t767 long +--* t769 long N005 ( 4, 6) [000770] ----------- t770 = * LSH long $acb /--* t765 long +--* t770 long N006 ( 6, 8) [000771] -------N--- t771 = * ADD long $acc /--* t771 long N007 ( 9, 10) [000772] ---XG------ t772 = * IND ushort /--* t772 ushort N009 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 N010 ( 1, 1) [003637] ----------- t3637 = LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- t773 = CNS_INT int 0 $c0 /--* t3637 int +--* t773 int N013 ( 12, 14) [000774] J--XG--N--- t774 = * EQ int /--* t774 int N014 ( 14, 16) [000775] ---XG------ * JTRUE void $bec ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} [004074] ----------- IL_OFFSET void INLRT @ 0x60D[E-] N001 ( 1, 1) [000776] ----------- t776 = LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- t777 = CNS_INT int 1 $c1 /--* t776 int +--* t777 int N003 ( 3, 4) [000778] ----------- t778 = * ADD int $bad /--* t778 int N005 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} [004075] ----------- IL_OFFSET void INLRT @ 0x618[E-] N001 ( 1, 1) [000283] ----------- t283 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- t3701 = LCL_VAR int V179 cse8 u:1 $342 /--* t283 int +--* t3701 int N003 ( 6, 3) [000288] -------N--- t288 = * GE int $94d N004 ( 1, 1) [000290] ----------- t290 = LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 1, 1) [000291] ----------- t291 = LCL_VAR int V16 loc12 u:5 $898 /--* t291 int N006 ( 2, 3) [000292] ----------- t292 = * CAST long <- int $3e5 N007 ( 1, 2) [000294] ----------- t294 = CNS_INT long 1 $204 /--* t292 long +--* t294 long N008 ( 4, 6) [000295] ----------- t295 = * LSH long $3e6 /--* t290 long +--* t295 long N009 ( 6, 8) [000296] -------N--- t296 = * ADD long $3e7 /--* t296 long N010 ( 9, 10) [000297] ---XG------ t297 = * IND ushort /--* t297 ushort N012 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 N013 ( 1, 1) [003665] ----------- t3665 = LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] ----------- t298 = CNS_INT int 0 $c0 /--* t3665 int +--* t298 int N016 ( 15, 14) [000299] ---XG--N--- t299 = * EQ int /--* t288 int +--* t299 int N017 ( 22, 18) [003760] J--XG--N--- t3760 = * AND int /--* t3760 int N018 ( 24, 20) [000289] ---XG------ * JTRUE void $VN.Void ------------ BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} [004076] ----------- IL_OFFSET void INLRT @ 0x626[E-] N001 ( 0, 0) [003761] ----------- NOP void [004077] ----------- IL_OFFSET void INLRT @ 0x634[E-] N001 ( 1, 1) [000303] ----------- t303 = LCL_VAR int V16 loc12 u:5 $898 /--* t303 int N003 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 [004078] ----------- IL_OFFSET void INLRT @ 0x634[E-] N001 ( 1, 1) [000304] ----------- t304 = LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- t305 = CNS_INT int 1 $c1 /--* t304 int +--* t305 int N003 ( 3, 4) [000306] ----------- t306 = * ADD int $952 /--* t306 int N005 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 N001 ( 1, 1) [003667] ----------- t3667 = LCL_VAR int V176 cse5 /--* t3667 int N003 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 [004079] ----------- IL_OFFSET void INL53 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000301] ----------- t301 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- t3026 = CNS_INT long 8 $201 /--* t301 byref +--* t3026 long N003 ( 3, 4) [003027] -------N--- t3027 = * ADD byref $25a /--* t3027 byref N004 ( 4, 3) [002244] ---XG------ t2244 = * IND int /--* t2244 int N006 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 [004080] ----------- IL_OFFSET void INL53 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002247] ----------- t2247 = LCL_VAR int V122 tmp82 u:1 N002 ( 1, 1) [002248] ----------- t2248 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- t3030 = CNS_INT long 24 $20c /--* t2248 byref +--* t3030 long N004 ( 3, 4) [003031] -------N--- t3031 = * ADD byref $25b /--* t3031 byref N005 ( 4, 3) [002286] n---GO----- t2286 = * IND int /--* t2247 int +--* t2286 int N006 ( 6, 5) [002252] N---GO-N-U- t2252 = * GE int /--* t2252 int N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 ------------ BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} [004081] ----------- IL_OFFSET void INL53 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003035] ----------- t3035 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- t3036 = CNS_INT long 16 $200 /--* t3035 byref +--* t3036 long N003 ( 3, 4) [003037] -----O----- t3037 = * ADD byref $25c /--* t3037 byref N005 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 N001 ( 1, 1) [002259] ----------- t2259 = LCL_VAR int V122 tmp82 u:1 N002 ( 1, 1) [002264] ----------- t2264 = LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- t3039 = CNS_INT long 8 $201 /--* t2264 byref +--* t3039 long N004 ( 3, 4) [003040] -------N--- t3040 = * ADD byref $25d /--* t3040 byref N005 ( 4, 3) [002265] n---GO----- t2265 = * IND int /--* t2259 int +--* t2265 int N006 ( 9, 11) [002266] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002263] ----------- t2263 = LCL_VAR byref V124 tmp84 u:1 (last use) $25c /--* t2263 byref N008 ( 3, 2) [002270] n---GO----- t2270 = * IND byref N009 ( 1, 1) [002260] ----------- t2260 = LCL_VAR int V122 tmp82 u:1 /--* t2260 int N010 ( 2, 3) [002267] ---------U- t2267 = * CAST long <- uint N011 ( 1, 2) [002268] ----------- t2268 = CNS_INT long 1 $204 /--* t2267 long +--* t2268 long N012 ( 4, 6) [002269] ----------- t2269 = * LSH long /--* t2270 byref +--* t2269 long N013 ( 8, 9) [002271] ----GO-N--- t2271 = * ADD byref N016 ( 1, 1) [002273] ----------- t2273 = LCL_VAR int V123 tmp83 u:1 (last use) /--* t2271 byref +--* t2273 int [004082] -A-XGO----- * STOREIND short [004083] ----------- IL_OFFSET void INL53 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002277] ----------- t2277 = LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- t2278 = CNS_INT int 1 $c1 /--* t2277 int +--* t2278 int N003 ( 3, 4) [002279] ----------- t2279 = * ADD int N004 ( 1, 1) [002276] ----------- t2276 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- t3042 = CNS_INT long 8 $201 /--* t2276 byref +--* t3042 long N006 ( 3, 4) [003043] -------N--- t3043 = * ADD byref $25a /--* t3043 byref +--* t2279 int [004084] -A--GO----- * STOREIND int ------------ BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} [004085] ----------- IL_OFFSET void INL53 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002254] ----------- t2254 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- t2255 = LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- t3044 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2254 byref this in x0 +--* t2255 int arg2 in x1 +--* t3044 long r2r cell in x11 N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} [004086] ----------- IL_OFFSET void INLRT @ 0x64D[E-] N001 ( 1, 2) [003045] ----------- t3045 = CNS_INT int 0 $c0 /--* t3045 int N003 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 [004087] ----------- IL_OFFSET void INLRT @ 0x650[E-] N001 ( 1, 2) [000326] ----------- t326 = CNS_INT int 0 $c0 /--* t326 int N003 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 [004088] ----------- IL_OFFSET void INLRT @ 0x653[E-] N001 ( 1, 1) [000329] ----------- t329 = LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- t330 = CNS_INT int 0 $c0 /--* t329 int +--* t330 int N003 ( 3, 4) [000331] J------N--- t331 = * EQ int $97d /--* t331 int N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} [004089] ----------- IL_OFFSET void INLRT @ 0x65A[E-] N001 ( 1, 1) [000419] ----------- t419 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- t3702 = LCL_VAR int V179 cse8 u:1 $342 /--* t419 int +--* t3702 int N003 ( 3, 3) [000424] J------N--- t424 = * GE int $94d /--* t424 int N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} [004090] ----------- IL_OFFSET void INLRT @ 0x665[E-] N001 ( 1, 1) [000565] ----------- t565 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000566] ----------- t566 = LCL_VAR int V16 loc12 u:5 $898 /--* t566 int N003 ( 2, 3) [000567] ----------- t567 = * CAST long <- int $3e5 N004 ( 1, 2) [000569] ----------- t569 = CNS_INT long 1 $204 /--* t567 long +--* t569 long N005 ( 4, 6) [000570] ----------- t570 = * LSH long $3e6 /--* t565 long +--* t570 long N006 ( 6, 8) [000571] -------N--- t571 = * ADD long $3e7 /--* t571 long N007 ( 9, 10) [000572] ---XG------ t572 = * IND ushort /--* t572 ushort N009 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 N010 ( 1, 1) [003670] ----------- t3670 = LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- t573 = CNS_INT int 48 $d8 /--* t3670 int +--* t573 int N013 ( 12, 14) [000574] N--XG--N-U- t574 = * EQ int /--* t574 int N014 ( 14, 16) [000575] ---XG------ * JTRUE void $87a ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} [004091] ----------- IL_OFFSET void INLRT @ 0x67A[E-] N001 ( 1, 1) [000426] ----------- t426 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- t427 = CNS_INT int 1 $c1 /--* t426 int +--* t427 int N003 ( 3, 4) [000428] ----------- t428 = * ADD int $952 N004 ( 1, 1) [003703] ----------- t3703 = LCL_VAR int V179 cse8 u:1 $342 /--* t428 int +--* t3703 int N005 ( 5, 6) [000433] J------N--- t433 = * GE int $9e2 /--* t433 int N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} [004092] ----------- IL_OFFSET void INLRT @ 0x687[E-] N001 ( 1, 1) [000538] ----------- t538 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000539] ----------- t539 = LCL_VAR int V16 loc12 u:5 $898 /--* t539 int N003 ( 2, 3) [000540] ----------- t540 = * CAST long <- int $3e5 N004 ( 1, 2) [000542] ----------- t542 = CNS_INT long 1 $204 /--* t540 long +--* t542 long N005 ( 4, 6) [000543] ----------- t543 = * LSH long $3e6 /--* t538 long +--* t543 long N006 ( 6, 8) [000544] -------N--- t544 = * ADD long $3e7 /--* t544 long N007 ( 9, 10) [000545] ---XG------ t545 = * IND ushort /--* t545 ushort N009 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 N010 ( 1, 1) [003674] ----------- t3674 = LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- t546 = CNS_INT int 43 $d9 /--* t3674 int +--* t546 int N013 ( 15, 14) [000547] N--XG--N-U- t547 = * NE int N014 ( 1, 1) [000549] ----------- t549 = LCL_VAR long V34 loc30 u:1 $3c4 N015 ( 1, 1) [000550] ----------- t550 = LCL_VAR int V16 loc12 u:5 $898 N016 ( 1, 2) [000551] ----------- t551 = CNS_INT int 1 $c1 /--* t550 int +--* t551 int N017 ( 3, 4) [000552] ----------- t552 = * ADD int $952 /--* t552 int N018 ( 4, 6) [000553] ----------- t553 = * CAST long <- int $3f4 N019 ( 1, 2) [000555] ----------- t555 = CNS_INT long 1 $204 /--* t553 long +--* t555 long N020 ( 6, 9) [000556] ----------- t556 = * LSH long $3f5 /--* t549 long +--* t556 long N021 ( 8, 11) [000557] -------N--- t557 = * ADD long $3f6 /--* t557 long N022 ( 11, 13) [000558] ---XG------ t558 = * IND ushort N023 ( 1, 2) [000559] ----------- t559 = CNS_INT int 48 $d8 /--* t558 ushort +--* t559 int N024 ( 16, 16) [000560] N--XG--N-U- t560 = * NE int /--* t547 int +--* t560 int N025 ( 32, 31) [003762] J--XG--N--- t3762 = * AND int /--* t3762 int N026 ( 34, 33) [000548] ---XG------ * JTRUE void $87a ------------ BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} [004093] ----------- IL_OFFSET void INLRT @ 0x694[E-] N001 ( 0, 0) [003763] ----------- NOP void [004094] ----------- IL_OFFSET void INLRT @ 0x6A3[E-] N001 ( 1, 2) [003046] ----------- t3046 = CNS_INT int 1 $c1 /--* t3046 int N003 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} [004095] ----------- IL_OFFSET void INLRT @ 0x6B5[E-] N001 ( 1, 1) [003676] ----------- t3676 = LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- t455 = CNS_INT int 45 $da /--* t3676 int +--* t455 int N003 ( 3, 4) [000456] N---G--N-U- t456 = * NE int /--* t456 int N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} [004096] ----------- IL_OFFSET void INLRT @ 0x6C2[E-] N001 ( 1, 1) [000458] ----------- t458 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000459] ----------- t459 = LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- t460 = CNS_INT int 1 $c1 /--* t459 int +--* t460 int N004 ( 3, 4) [000461] ----------- t461 = * ADD int $952 /--* t461 int N005 ( 4, 6) [000462] ----------- t462 = * CAST long <- int $3f4 N006 ( 1, 2) [000464] ----------- t464 = CNS_INT long 1 $204 /--* t462 long +--* t464 long N007 ( 6, 9) [000465] ----------- t465 = * LSH long $3f5 /--* t458 long +--* t465 long N008 ( 8, 11) [000466] -------N--- t466 = * ADD long $3f6 /--* t466 long N009 ( 11, 13) [000467] ---XG------ t467 = * IND ushort N010 ( 1, 2) [000468] ----------- t468 = CNS_INT int 48 $d8 /--* t467 ushort +--* t468 int N011 ( 13, 16) [000469] J--XG--N--- t469 = * EQ int /--* t469 int N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 ------------ BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} [004097] ----------- IL_OFFSET void INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [000444] ----------- t444 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- t3047 = CNS_INT long 8 $201 /--* t444 byref +--* t3047 long N003 ( 3, 4) [003048] -------N--- t3048 = * ADD byref $25a /--* t3048 byref N004 ( 4, 3) [002302] ---XG------ t2302 = * IND int /--* t2302 int N006 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 [004098] ----------- IL_OFFSET void INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002305] ----------- t2305 = LCL_VAR int V126 tmp86 u:1 N002 ( 1, 1) [002306] ----------- t2306 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- t3051 = CNS_INT long 24 $20c /--* t2306 byref +--* t3051 long N004 ( 3, 4) [003052] -------N--- t3052 = * ADD byref $25b /--* t3052 byref N005 ( 4, 3) [002341] n---GO----- t2341 = * IND int /--* t2305 int +--* t2341 int N006 ( 6, 5) [002310] N---GO-N-U- t2310 = * GE int /--* t2310 int N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} [004099] ----------- IL_OFFSET void INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [003056] ----------- t3056 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- t3057 = CNS_INT long 16 $200 /--* t3056 byref +--* t3057 long N003 ( 3, 4) [003058] -----O----- t3058 = * ADD byref $25c /--* t3058 byref N005 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 [004100] ----------- IL_OFFSET void INL58 @ ??? <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002316] ----------- t2316 = LCL_VAR int V126 tmp86 u:1 N002 ( 1, 1) [002321] ----------- t2321 = LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- t3060 = CNS_INT long 8 $201 /--* t2321 byref +--* t3060 long N004 ( 3, 4) [003061] -------N--- t3061 = * ADD byref $25d /--* t3061 byref N005 ( 4, 3) [002322] n---GO----- t2322 = * IND int /--* t2316 int +--* t2322 int N006 ( 9, 11) [002323] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002320] ----------- t2320 = LCL_VAR byref V127 tmp87 u:1 (last use) $25c /--* t2320 byref N008 ( 3, 2) [002327] n---GO----- t2327 = * IND byref N009 ( 1, 1) [002317] ----------- t2317 = LCL_VAR int V126 tmp86 u:1 /--* t2317 int N010 ( 2, 3) [002324] ---------U- t2324 = * CAST long <- uint N011 ( 1, 2) [002325] ----------- t2325 = CNS_INT long 1 $204 /--* t2324 long +--* t2325 long N012 ( 4, 6) [002326] ----------- t2326 = * LSH long /--* t2327 byref +--* t2326 long N013 ( 8, 9) [002328] ----GO-N--- t2328 = * ADD byref N016 ( 1, 1) [002330] ----------- t2330 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2328 byref +--* t2330 int [004101] -A-XGO----- * STOREIND short [004102] ----------- IL_OFFSET void INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002334] ----------- t2334 = LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- t2335 = CNS_INT int 1 $c1 /--* t2334 int +--* t2335 int N003 ( 3, 4) [002336] ----------- t2336 = * ADD int N004 ( 1, 1) [002333] ----------- t2333 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- t3063 = CNS_INT long 8 $201 /--* t2333 byref +--* t3063 long N006 ( 3, 4) [003064] -------N--- t3064 = * ADD byref $25a /--* t3064 byref +--* t2336 int [004103] -A--GO----- * STOREIND int ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} [004104] ----------- IL_OFFSET void INLRT @ 0x6DE[E-] N001 ( 1, 1) [000533] ----------- t533 = LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- t534 = CNS_INT int 1 $c1 /--* t533 int +--* t534 int N003 ( 3, 4) [000535] ----------- t535 = * ADD int $c59 /--* t535 int N005 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} [004105] ----------- IL_OFFSET void INLRT @ 0x6E4[E-] N001 ( 1, 1) [000471] ----------- t471 = LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- t472 = CNS_INT int 1 $c1 /--* t471 int +--* t472 int N003 ( 3, 4) [000473] ----------- t473 = * ADD int $c5c /--* t473 int N005 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 N001 ( 1, 1) [000477] ----------- t477 = LCL_VAR int V54 tmp14 u:1 $c5c /--* t477 int N003 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 N001 ( 1, 1) [000476] ----------- t476 = LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- t3704 = LCL_VAR int V179 cse8 u:1 $342 /--* t476 int +--* t3704 int N003 ( 3, 3) [000484] J------N--- t484 = * GE int $c5d /--* t484 int N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} [004106] ----------- IL_OFFSET void INLRT @ 0x6F4[E-] N001 ( 1, 1) [000522] ----------- t522 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000523] ----------- t523 = LCL_VAR int V16 loc12 u:10 $c5c /--* t523 int N003 ( 2, 3) [000524] ----------- t524 = * CAST long <- int $ad8 N004 ( 1, 2) [000526] ----------- t526 = CNS_INT long 1 $204 /--* t524 long +--* t526 long N005 ( 4, 6) [000527] ----------- t527 = * LSH long $ad9 /--* t522 long +--* t527 long N006 ( 6, 8) [000528] -------N--- t528 = * ADD long $ada /--* t528 long N007 ( 9, 10) [000529] ---XG------ t529 = * IND ushort N008 ( 1, 2) [000530] ----------- t530 = CNS_INT int 48 $d8 /--* t529 ushort +--* t530 int N009 ( 11, 13) [000531] J--XG--N--- t531 = * EQ int /--* t531 int N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} [004107] ----------- IL_OFFSET void INLRT @ 0x701[E-] N001 ( 1, 1) [000486] ----------- t486 = LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- t487 = CNS_INT int 10 $e4 /--* t486 int +--* t487 int N003 ( 3, 4) [000488] J------N--- t488 = * LE int $c62 /--* t488 int N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void ------------ BB222 [707..70B), preds={BB221} succs={BB223} [004108] ----------- IL_OFFSET void INLRT @ 0x707[E-] N001 ( 1, 2) [000519] ----------- t519 = CNS_INT int 10 $e4 /--* t519 int N003 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} [004109] ----------- IL_OFFSET void INLRT @ 0x70B[E-] N001 ( 1, 1) [000490] ----------- t490 = LCL_VAR long V17 loc13 u:1 /--* t490 long N002 ( 4, 3) [000491] ---XG------ t491 = * IND ubyte N003 ( 1, 2) [000492] ----------- t492 = CNS_INT int 0 $c0 /--* t491 ubyte +--* t492 int N004 ( 6, 6) [000493] J--XG--N--- t493 = * EQ int /--* t493 int N005 ( 8, 8) [000494] ---XG------ * JTRUE void ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} [004110] ----------- IL_OFFSET void INLRT @ 0x710[E-] N001 ( 1, 1) [000512] ----------- t512 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- t3066 = CNS_INT long 4 $207 /--* t512 byref +--* t3066 long N003 ( 3, 4) [003067] -------N--- t3067 = * ADD byref $24a /--* t3067 byref N004 ( 4, 3) [000513] n---GO----- t513 = * IND int N005 ( 1, 1) [000514] ----------- t514 = LCL_VAR int V05 loc1 u:3 $28d /--* t513 int +--* t514 int N006 ( 6, 5) [000515] ----GO----- t515 = * SUB int /--* t515 int N008 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} [004111] ----------- IL_OFFSET void INLRT @ 0x71A[E-] N001 ( 1, 2) [000495] ----------- t495 = CNS_INT int 0 $c0 /--* t495 int N003 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} [004112] ----------- IL_OFFSET void INLRT @ 0x71D[E-] N001 ( 1, 1) [000507] ----------- t507 = LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- t502 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- t503 = LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- t499 = LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- t505 = LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- t506 = LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- t3068 = CNS_INT(h) long 0x4000000000540240 ftn $5e /--* t507 int arg6 in x5 +--* t502 byref arg1 in x0 +--* t503 ref arg2 in x1 +--* t499 int arg3 in x2 +--* t505 int arg4 in x3 +--* t506 int arg5 in x4 +--* t3068 long r2r cell in x11 N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void [004113] ----------- IL_OFFSET void INLRT @ 0x72C[E-] N001 ( 1, 2) [003069] ----------- t3069 = CNS_INT int 0 $c0 /--* t3069 int N003 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} [004114] ----------- IL_OFFSET void INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [000333] ----------- t333 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- t3070 = CNS_INT long 8 $201 /--* t333 byref +--* t3070 long N003 ( 3, 4) [003071] -------N--- t3071 = * ADD byref $25a /--* t3071 byref N004 ( 4, 3) [002349] ---XG------ t2349 = * IND int /--* t2349 int N006 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 [004115] ----------- IL_OFFSET void INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002352] ----------- t2352 = LCL_VAR int V129 tmp89 u:1 N002 ( 1, 1) [002353] ----------- t2353 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- t3074 = CNS_INT long 24 $20c /--* t2353 byref +--* t3074 long N004 ( 3, 4) [003075] -------N--- t3075 = * ADD byref $25b /--* t3075 byref N005 ( 4, 3) [002388] n---GO----- t2388 = * IND int /--* t2352 int +--* t2388 int N006 ( 6, 5) [002357] N---GO-N-U- t2357 = * GE int /--* t2357 int N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} [004116] ----------- IL_OFFSET void INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [003079] ----------- t3079 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- t3080 = CNS_INT long 16 $200 /--* t3079 byref +--* t3080 long N003 ( 3, 4) [003081] -----O----- t3081 = * ADD byref $25c /--* t3081 byref N005 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 [004117] ----------- IL_OFFSET void INL61 @ ??? <- INLRT @ 0x731[E-] N001 ( 1, 1) [002363] ----------- t2363 = LCL_VAR int V129 tmp89 u:1 N002 ( 1, 1) [002368] ----------- t2368 = LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- t3083 = CNS_INT long 8 $201 /--* t2368 byref +--* t3083 long N004 ( 3, 4) [003084] -------N--- t3084 = * ADD byref $25d /--* t3084 byref N005 ( 4, 3) [002369] n---GO----- t2369 = * IND int /--* t2363 int +--* t2369 int N006 ( 9, 11) [002370] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002367] ----------- t2367 = LCL_VAR byref V130 tmp90 u:1 (last use) $25c /--* t2367 byref N008 ( 3, 2) [002374] n---GO----- t2374 = * IND byref N009 ( 1, 1) [002364] ----------- t2364 = LCL_VAR int V129 tmp89 u:1 /--* t2364 int N010 ( 2, 3) [002371] ---------U- t2371 = * CAST long <- uint N011 ( 1, 2) [002372] ----------- t2372 = CNS_INT long 1 $204 /--* t2371 long +--* t2372 long N012 ( 4, 6) [002373] ----------- t2373 = * LSH long /--* t2374 byref +--* t2373 long N013 ( 8, 9) [002375] ----GO-N--- t2375 = * ADD byref N016 ( 1, 1) [002377] ----------- t2377 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2375 byref +--* t2377 int [004118] -A-XGO----- * STOREIND short [004119] ----------- IL_OFFSET void INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002381] ----------- t2381 = LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- t2382 = CNS_INT int 1 $c1 /--* t2381 int +--* t2382 int N003 ( 3, 4) [002383] ----------- t2383 = * ADD int N004 ( 1, 1) [002380] ----------- t2380 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- t3086 = CNS_INT long 8 $201 /--* t2380 byref +--* t3086 long N006 ( 3, 4) [003087] -------N--- t3087 = * ADD byref $25a /--* t3087 byref +--* t2383 int [004120] -A--GO----- * STOREIND int ------------ BB229 [731..732), preds={BB227} succs={BB230} [004121] ----------- IL_OFFSET void INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002359] ----------- t2359 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- t334 = LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- t3088 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2359 byref this in x0 +--* t334 int arg2 in x1 +--* t3088 long r2r cell in x11 N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} [004122] ----------- IL_OFFSET void INLRT @ 0x739[E-] N001 ( 1, 1) [000336] ----------- t336 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- t3705 = LCL_VAR int V179 cse8 u:1 $342 /--* t336 int +--* t3705 int N003 ( 3, 3) [000341] J------N--- t341 = * GE int $94d /--* t341 int N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} [004123] ----------- IL_OFFSET void INLRT @ 0x744[E-] N001 ( 1, 1) [000343] ----------- t343 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000344] ----------- t344 = LCL_VAR int V16 loc12 u:5 $898 /--* t344 int N003 ( 2, 3) [000345] ----------- t345 = * CAST long <- int $3e5 N004 ( 1, 2) [000347] ----------- t347 = CNS_INT long 1 $204 /--* t345 long +--* t347 long N005 ( 4, 6) [000348] ----------- t348 = * LSH long $3e6 /--* t343 long +--* t348 long N006 ( 6, 8) [000349] -------N--- t349 = * ADD long $3e7 /--* t349 long N007 ( 9, 10) [000350] ---XG------ t350 = * IND ushort /--* t350 ushort N009 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 N010 ( 1, 1) [003659] ----------- t3659 = LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- t351 = CNS_INT int 43 $d9 /--* t3659 int +--* t351 int N013 ( 12, 14) [000352] J--XG--N--- t352 = * EQ int /--* t352 int N014 ( 14, 16) [000353] ---XG------ * JTRUE void $87a ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} [004124] ----------- IL_OFFSET void INLRT @ 0x751[E-] N001 ( 1, 1) [003661] ----------- t3661 = LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- t416 = CNS_INT int 45 $da /--* t3661 int +--* t416 int N003 ( 3, 4) [000417] N---G--N-U- t417 = * NE int /--* t417 int N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} [004125] ----------- IL_OFFSET void INLRT @ 0x75E[E-] N001 ( 1, 1) [000356] ----------- t356 = LCL_VAR int V16 loc12 u:5 $898 /--* t356 int N003 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 [004126] ----------- IL_OFFSET void INLRT @ 0x75E[E-] N001 ( 1, 1) [000357] ----------- t357 = LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- t358 = CNS_INT int 1 $c1 /--* t357 int +--* t358 int N003 ( 3, 4) [000359] ----------- t359 = * ADD int $952 /--* t359 int N005 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 N001 ( 1, 1) [003662] ----------- t3662 = LCL_VAR int V175 cse4 u:1 /--* t3662 int N003 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 [004127] ----------- IL_OFFSET void INL64 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000354] ----------- t354 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- t3089 = CNS_INT long 8 $201 /--* t354 byref +--* t3089 long N003 ( 3, 4) [003090] -------N--- t3090 = * ADD byref $25a /--* t3090 byref N004 ( 4, 3) [002396] n---GO----- t2396 = * IND int /--* t2396 int N006 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 [004128] ----------- IL_OFFSET void INL64 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002399] ----------- t2399 = LCL_VAR int V132 tmp92 u:1 N002 ( 1, 1) [002400] ----------- t2400 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- t3093 = CNS_INT long 24 $20c /--* t2400 byref +--* t3093 long N004 ( 3, 4) [003094] -------N--- t3094 = * ADD byref $25b /--* t3094 byref N005 ( 4, 3) [002438] n---GO----- t2438 = * IND int /--* t2399 int +--* t2438 int N006 ( 6, 5) [002404] N---GO-N-U- t2404 = * GE int /--* t2404 int N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} [004129] ----------- IL_OFFSET void INL64 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003098] ----------- t3098 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- t3099 = CNS_INT long 16 $200 /--* t3098 byref +--* t3099 long N003 ( 3, 4) [003100] -----O----- t3100 = * ADD byref $25c /--* t3100 byref N005 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 N001 ( 1, 1) [002411] ----------- t2411 = LCL_VAR int V132 tmp92 u:1 N002 ( 1, 1) [002416] ----------- t2416 = LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- t3102 = CNS_INT long 8 $201 /--* t2416 byref +--* t3102 long N004 ( 3, 4) [003103] -------N--- t3103 = * ADD byref $25d /--* t3103 byref N005 ( 4, 3) [002417] n---GO----- t2417 = * IND int /--* t2411 int +--* t2417 int N006 ( 9, 11) [002418] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002415] ----------- t2415 = LCL_VAR byref V134 tmp94 u:1 (last use) $25c /--* t2415 byref N008 ( 3, 2) [002422] n---GO----- t2422 = * IND byref N009 ( 1, 1) [002412] ----------- t2412 = LCL_VAR int V132 tmp92 u:1 /--* t2412 int N010 ( 2, 3) [002419] ---------U- t2419 = * CAST long <- uint N011 ( 1, 2) [002420] ----------- t2420 = CNS_INT long 1 $204 /--* t2419 long +--* t2420 long N012 ( 4, 6) [002421] ----------- t2421 = * LSH long /--* t2422 byref +--* t2421 long N013 ( 8, 9) [002423] ----GO-N--- t2423 = * ADD byref N016 ( 1, 1) [002425] ----------- t2425 = LCL_VAR int V133 tmp93 u:1 (last use) /--* t2423 byref +--* t2425 int [004130] -A-XGO----- * STOREIND short [004131] ----------- IL_OFFSET void INL64 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002429] ----------- t2429 = LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- t2430 = CNS_INT int 1 $c1 /--* t2429 int +--* t2430 int N003 ( 3, 4) [002431] ----------- t2431 = * ADD int N004 ( 1, 1) [002428] ----------- t2428 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- t3105 = CNS_INT long 8 $201 /--* t2428 byref +--* t3105 long N006 ( 3, 4) [003106] -------N--- t3106 = * ADD byref $25a /--* t3106 byref +--* t2431 int [004132] -A--GO----- * STOREIND int ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} [004133] ----------- IL_OFFSET void INL64 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002406] ----------- t2406 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- t2407 = LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- t3107 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2406 byref this in x0 +--* t2407 int arg2 in x1 +--* t3107 long r2r cell in x11 N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} [004134] ----------- IL_OFFSET void INLRT @ 0x774[E-] N001 ( 1, 1) [000392] ----------- t392 = LCL_VAR int V16 loc12 u:6 $b08 /--* t392 int N003 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 [004135] ----------- IL_OFFSET void INLRT @ 0x774[E-] N001 ( 1, 1) [000393] ----------- t393 = LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- t394 = CNS_INT int 1 $c1 /--* t393 int +--* t394 int N003 ( 3, 4) [000395] ----------- t395 = * ADD int $c47 /--* t395 int N005 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 N001 ( 1, 1) [003639] ----------- t3639 = LCL_VAR int V173 cse2 u:1 /--* t3639 int N003 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 [004136] ----------- IL_OFFSET void INL66 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000390] ----------- t390 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- t3108 = CNS_INT long 8 $201 /--* t390 byref +--* t3108 long N003 ( 3, 4) [003109] -------N--- t3109 = * ADD byref $25a /--* t3109 byref N004 ( 4, 3) [002442] n---GO----- t2442 = * IND int /--* t2442 int N006 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 [004137] ----------- IL_OFFSET void INL66 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002445] ----------- t2445 = LCL_VAR int V136 tmp96 u:1 N002 ( 1, 1) [002446] ----------- t2446 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- t3112 = CNS_INT long 24 $20c /--* t2446 byref +--* t3112 long N004 ( 3, 4) [003113] -------N--- t3113 = * ADD byref $25b /--* t3113 byref N005 ( 4, 3) [002484] n---GO----- t2484 = * IND int /--* t2445 int +--* t2484 int N006 ( 6, 5) [002450] N---GO-N-U- t2450 = * GE int /--* t2450 int N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} [004138] ----------- IL_OFFSET void INL66 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003117] ----------- t3117 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- t3118 = CNS_INT long 16 $200 /--* t3117 byref +--* t3118 long N003 ( 3, 4) [003119] -----O----- t3119 = * ADD byref $25c /--* t3119 byref N005 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 N001 ( 1, 1) [002457] ----------- t2457 = LCL_VAR int V136 tmp96 u:1 N002 ( 1, 1) [002462] ----------- t2462 = LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- t3121 = CNS_INT long 8 $201 /--* t2462 byref +--* t3121 long N004 ( 3, 4) [003122] -------N--- t3122 = * ADD byref $25d /--* t3122 byref N005 ( 4, 3) [002463] n---GO----- t2463 = * IND int /--* t2457 int +--* t2463 int N006 ( 9, 11) [002464] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002461] ----------- t2461 = LCL_VAR byref V138 tmp98 u:1 (last use) $25c /--* t2461 byref N008 ( 3, 2) [002468] n---GO----- t2468 = * IND byref N009 ( 1, 1) [002458] ----------- t2458 = LCL_VAR int V136 tmp96 u:1 /--* t2458 int N010 ( 2, 3) [002465] ---------U- t2465 = * CAST long <- uint N011 ( 1, 2) [002466] ----------- t2466 = CNS_INT long 1 $204 /--* t2465 long +--* t2466 long N012 ( 4, 6) [002467] ----------- t2467 = * LSH long /--* t2468 byref +--* t2467 long N013 ( 8, 9) [002469] ----GO-N--- t2469 = * ADD byref N016 ( 1, 1) [002471] ----------- t2471 = LCL_VAR int V137 tmp97 u:1 (last use) /--* t2469 byref +--* t2471 int [004139] -A-XGO----- * STOREIND short [004140] ----------- IL_OFFSET void INL66 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002475] ----------- t2475 = LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- t2476 = CNS_INT int 1 $c1 /--* t2475 int +--* t2476 int N003 ( 3, 4) [002477] ----------- t2477 = * ADD int N004 ( 1, 1) [002474] ----------- t2474 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- t3124 = CNS_INT long 8 $201 /--* t2474 byref +--* t3124 long N006 ( 3, 4) [003125] -------N--- t3125 = * ADD byref $25a /--* t3125 byref +--* t2477 int [004141] -A--GO----- * STOREIND int ------------ BB238 [000..000), preds={BB236} succs={BB239} [004142] ----------- IL_OFFSET void INL66 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002452] ----------- t2452 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- t2453 = LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- t3126 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2452 byref this in x0 +--* t2453 int arg2 in x1 +--* t3126 long r2r cell in x11 N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} [004143] ----------- IL_OFFSET void INLRT @ 0x788[E-] N001 ( 1, 1) [000372] ----------- t372 = LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- t3706 = LCL_VAR int V179 cse8 u:1 $342 /--* t372 int +--* t3706 int N003 ( 3, 3) [000377] J------N--- t377 = * GE int $c42 /--* t377 int N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} [004144] ----------- IL_OFFSET void INLRT @ 0x793[E-] N001 ( 1, 1) [000379] ----------- t379 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000380] ----------- t380 = LCL_VAR int V16 loc12 u:6 $b08 /--* t380 int N003 ( 2, 3) [000381] ----------- t381 = * CAST long <- int $ad1 N004 ( 1, 2) [000383] ----------- t383 = CNS_INT long 1 $204 /--* t381 long +--* t383 long N005 ( 4, 6) [000384] ----------- t384 = * LSH long $ad2 /--* t379 long +--* t384 long N006 ( 6, 8) [000385] -------N--- t385 = * ADD long $ad3 /--* t385 long N007 ( 9, 10) [000386] ---XG------ t386 = * IND ushort /--* t386 ushort N009 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 N010 ( 1, 1) [003642] ----------- t3642 = LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- t387 = CNS_INT int 48 $d8 /--* t3642 int +--* t387 int N013 ( 12, 14) [000388] J--XG--N--- t388 = * EQ int /--* t388 int N014 ( 14, 16) [000389] ---XG------ * JTRUE void $c02 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} [004145] ----------- IL_OFFSET void INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [000590] ----------- t590 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- t3127 = CNS_INT long 8 $201 /--* t590 byref +--* t3127 long N003 ( 3, 4) [003128] -------N--- t3128 = * ADD byref $25a /--* t3128 byref N004 ( 4, 3) [002492] ---XG------ t2492 = * IND int /--* t2492 int N006 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 [004146] ----------- IL_OFFSET void INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002495] ----------- t2495 = LCL_VAR int V140 tmp100 u:1 N002 ( 1, 1) [002496] ----------- t2496 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- t3131 = CNS_INT long 24 $20c /--* t2496 byref +--* t3131 long N004 ( 3, 4) [003132] -------N--- t3132 = * ADD byref $25b /--* t3132 byref N005 ( 4, 3) [002531] n---GO----- t2531 = * IND int /--* t2495 int +--* t2531 int N006 ( 6, 5) [002500] N---GO-N-U- t2500 = * GE int /--* t2500 int N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} [004147] ----------- IL_OFFSET void INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [003136] ----------- t3136 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- t3137 = CNS_INT long 16 $200 /--* t3136 byref +--* t3137 long N003 ( 3, 4) [003138] -----O----- t3138 = * ADD byref $25c /--* t3138 byref N005 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 [004148] ----------- IL_OFFSET void INL69 @ ??? <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002506] ----------- t2506 = LCL_VAR int V140 tmp100 u:1 N002 ( 1, 1) [002511] ----------- t2511 = LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- t3140 = CNS_INT long 8 $201 /--* t2511 byref +--* t3140 long N004 ( 3, 4) [003141] -------N--- t3141 = * ADD byref $25d /--* t3141 byref N005 ( 4, 3) [002512] n---GO----- t2512 = * IND int /--* t2506 int +--* t2512 int N006 ( 9, 11) [002513] ---XGO----- * BOUNDS_CHECK_Rng void N007 ( 1, 1) [002510] ----------- t2510 = LCL_VAR byref V141 tmp101 u:1 (last use) $25c /--* t2510 byref N008 ( 3, 2) [002517] n---GO----- t2517 = * IND byref N009 ( 1, 1) [002507] ----------- t2507 = LCL_VAR int V140 tmp100 u:1 /--* t2507 int N010 ( 2, 3) [002514] ---------U- t2514 = * CAST long <- uint N011 ( 1, 2) [002515] ----------- t2515 = CNS_INT long 1 $204 /--* t2514 long +--* t2515 long N012 ( 4, 6) [002516] ----------- t2516 = * LSH long /--* t2517 byref +--* t2516 long N013 ( 8, 9) [002518] ----GO-N--- t2518 = * ADD byref N016 ( 1, 1) [002520] ----------- t2520 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2518 byref +--* t2520 int [004149] -A-XGO----- * STOREIND short [004150] ----------- IL_OFFSET void INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002524] ----------- t2524 = LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- t2525 = CNS_INT int 1 $c1 /--* t2524 int +--* t2525 int N003 ( 3, 4) [002526] ----------- t2526 = * ADD int N004 ( 1, 1) [002523] ----------- t2523 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- t3143 = CNS_INT long 8 $201 /--* t2523 byref +--* t3143 long N006 ( 3, 4) [003144] -------N--- t3144 = * ADD byref $25a /--* t3144 byref +--* t2526 int [004151] -A--GO----- * STOREIND int ------------ BB244 [7A2..7A3) -> BB245 (always), preds={BB215,BB242} succs={BB245} [004152] ----------- IL_OFFSET void INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002502] ----------- t2502 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- t591 = LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- t3145 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2502 byref this in x0 +--* t591 int arg2 in x1 +--* t3145 long r2r cell in x11 N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB110 [000..000) (throw), preds={BB91} succs={} [004153] ----------- IL_OFFSET void INL17 @ 0x029[E-] <- INLRT @ ??? N001 ( 2, 8) [002701] H---------- t2701 = CNS_INT(h) long 0x4000000000424a20 ftn $4a /--* t2701 long r2r cell in x11 N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Do 'simple' lowering outgoingArgSpaceSize 0 sufficient for call [000001], which needs 0 *** Computing fgRngChkTarget for block BB01 fgNewBBinRegion(jumpKind=3, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB110 New Basic Block BB254 [0363] created. fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB254 [0363] Initializing arg info for 4154.CALL: Args for call [004154] CALL after AddFinalArgsAndDetermineABIInfo: Morphing args for 4154.CALL: Args for [004154].CALL after fgMorphArgs: OutgoingArgsStackSize is 0 outgoingArgSpaceSize 0 sufficient for call [000030], which needs 0 outgoingArgSpaceSize 0 sufficient for call [001151], which needs 0 outgoingArgSpaceSize 0 sufficient for call [001159], which needs 0 Lower ARR_LENGTH: /--* t2656 byref N004 ( 4, 3) [001570] ---XG------ t1570 = * IND ref /--* t1570 ref N005 ( 6, 5) [000944] ---XG------ t944 = * ARR_LENGTH int After Lower IND: /--* t2656 byref N004 ( 4, 3) [001570] ---XG------ t1570 = * IND ref [004155] ----------- t4155 = CNS_INT long 8 /--* t1570 ref +--* t4155 long [004156] ---XG------ t4156 = * ADD byref /--* t4156 byref N005 ( 6, 5) [000944] ---XG------ t944 = * IND int Lower ARR_LENGTH: N001 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 /--* t958 ref N002 ( 3, 3) [000959] ---X------- t959 = * ARR_LENGTH int After Lower IND: N001 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 [004157] ----------- t4157 = CNS_INT long 8 /--* t958 ref +--* t4157 long [004158] ----------- t4158 = * ADD byref /--* t4158 byref N002 ( 3, 3) [000959] ---X------- t959 = * IND int outgoingArgSpaceSize 0 sufficient for call [001068], which needs 0 Lower ARR_LENGTH: N001 ( 1, 1) [001607] ----------- t1607 = LCL_VAR ref V33 loc29 u:1 $800 /--* t1607 ref N002 ( 3, 3) [001608] ---X------- t1608 = * ARR_LENGTH int $2cc After Lower IND: N001 ( 1, 1) [001607] ----------- t1607 = LCL_VAR ref V33 loc29 u:1 $800 [004159] ----------- t4159 = CNS_INT long 8 /--* t1607 ref +--* t4159 long [004160] ----------- t4160 = * ADD byref /--* t4160 byref N002 ( 3, 3) [001608] ---X------- t1608 = * IND int $2cc outgoingArgSpaceSize 0 sufficient for call [001667], which needs 0 Lower ARR_LENGTH: N001 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 (last use) $800 /--* t1719 ref N002 ( 3, 3) [001720] ---X------- t1720 = * ARR_LENGTH int $2cc After Lower IND: N001 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 (last use) $800 [004161] ----------- t4161 = CNS_INT long 8 /--* t1719 ref +--* t4161 long [004162] ----------- t4162 = * ADD byref /--* t4162 byref N002 ( 3, 3) [001720] ---X------- t1720 = * IND int $2cc *** Computing fgRngChkTarget for block BB100 Lower ARR_LENGTH: N002 ( 1, 1) [001055] ----------- t1055 = LCL_VAR ref V26 loc22 u:1 /--* t1055 ref N003 ( 3, 3) [002732] ---X------- t2732 = * ARR_LENGTH int After Lower IND: N002 ( 1, 1) [001055] ----------- t1055 = LCL_VAR ref V26 loc22 u:1 [004163] ----------- t4163 = CNS_INT long 8 /--* t1055 ref +--* t4163 long [004164] ----------- t4164 = * ADD byref /--* t4164 byref N003 ( 3, 3) [002732] ---X------- t2732 = * IND int *** Computing fgRngChkTarget for block BB101 Lower ARR_LENGTH: N001 ( 1, 1) [001739] ----------- t1739 = LCL_VAR ref V86 tmp46 u:1 /--* t1739 ref N002 ( 3, 3) [001740] ---X------- t1740 = * ARR_LENGTH int After Lower IND: N001 ( 1, 1) [001739] ----------- t1739 = LCL_VAR ref V86 tmp46 u:1 [004165] ----------- t4165 = CNS_INT long 8 /--* t1739 ref +--* t4165 long [004166] ----------- t4166 = * ADD byref /--* t4166 byref N002 ( 3, 3) [001740] ---X------- t1740 = * IND int *** Computing fgRngChkTarget for block BB108 outgoingArgSpaceSize 0 sufficient for call [000241], which needs 0 outgoingArgSpaceSize 0 sufficient for call [001746], which needs 0 *** Computing fgRngChkTarget for block BB122 outgoingArgSpaceSize 0 sufficient for call [001809], which needs 0 *** Computing fgRngChkTarget for block BB125 Lower ARR_LENGTH: N001 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 /--* t1852 ref N002 ( 3, 3) [001853] ---X------- t1853 = * ARR_LENGTH int After Lower IND: N001 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 [004167] ----------- t4167 = CNS_INT long 8 /--* t1852 ref +--* t4167 long [004168] ----------- t4168 = * ADD byref /--* t4168 byref N002 ( 3, 3) [001853] ---X------- t1853 = * IND int *** Computing fgRngChkTarget for block BB130 *** Computing fgRngChkTarget for block BB130 outgoingArgSpaceSize 0 sufficient for call [001859], which needs 0 *** Computing fgRngChkTarget for block BB158 outgoingArgSpaceSize 0 sufficient for call [001914], which needs 0 *** Computing fgRngChkTarget for block BB161 Lower ARR_LENGTH: N001 ( 1, 1) [001955] ----------- t1955 = LCL_VAR ref V102 tmp62 u:1 /--* t1955 ref N002 ( 3, 3) [001956] ---X------- t1956 = * ARR_LENGTH int After Lower IND: N001 ( 1, 1) [001955] ----------- t1955 = LCL_VAR ref V102 tmp62 u:1 [004169] ----------- t4169 = CNS_INT long 8 /--* t1955 ref +--* t4169 long [004170] ----------- t4170 = * ADD byref /--* t4170 byref N002 ( 3, 3) [001956] ---X------- t1956 = * IND int *** Computing fgRngChkTarget for block BB166 Lower ARR_LENGTH: N017 ( 1, 1) [001986] ----------- t1986 = LCL_VAR ref V102 tmp62 u:1 /--* t1986 ref N018 ( 3, 3) [002892] ---X------- t2892 = * ARR_LENGTH int After Lower IND: N017 ( 1, 1) [001986] ----------- t1986 = LCL_VAR ref V102 tmp62 u:1 [004171] ----------- t4171 = CNS_INT long 8 /--* t1986 ref +--* t4171 long [004172] ----------- t4172 = * ADD byref /--* t4172 byref N018 ( 3, 3) [002892] ---X------- t2892 = * IND int *** Computing fgRngChkTarget for block BB166 outgoingArgSpaceSize 0 sufficient for call [001962], which needs 0 Lower ARR_LENGTH: N001 ( 1, 1) [002015] ----------- t2015 = LCL_VAR ref V106 tmp66 u:1 /--* t2015 ref N002 ( 3, 3) [002016] ---X------- t2016 = * ARR_LENGTH int After Lower IND: N001 ( 1, 1) [002015] ----------- t2015 = LCL_VAR ref V106 tmp66 u:1 [004173] ----------- t4173 = CNS_INT long 8 /--* t2015 ref +--* t4173 long [004174] ----------- t4174 = * ADD byref /--* t4174 byref N002 ( 3, 3) [002016] ---X------- t2016 = * IND int *** Computing fgRngChkTarget for block BB177 Lower ARR_LENGTH: N017 ( 1, 1) [002046] ----------- t2046 = LCL_VAR ref V106 tmp66 u:1 /--* t2046 ref N018 ( 3, 3) [002926] ---X------- t2926 = * ARR_LENGTH int After Lower IND: N017 ( 1, 1) [002046] ----------- t2046 = LCL_VAR ref V106 tmp66 u:1 [004175] ----------- t4175 = CNS_INT long 8 /--* t2046 ref +--* t4175 long [004176] ----------- t4176 = * ADD byref /--* t4176 byref N018 ( 3, 3) [002926] ---X------- t2926 = * IND int *** Computing fgRngChkTarget for block BB177 outgoingArgSpaceSize 0 sufficient for call [002022], which needs 0 Lower ARR_LENGTH: N001 ( 1, 1) [002075] ----------- t2075 = LCL_VAR ref V110 tmp70 u:1 /--* t2075 ref N002 ( 3, 3) [002076] ---X------- t2076 = * ARR_LENGTH int After Lower IND: N001 ( 1, 1) [002075] ----------- t2075 = LCL_VAR ref V110 tmp70 u:1 [004177] ----------- t4177 = CNS_INT long 8 /--* t2075 ref +--* t4177 long [004178] ----------- t4178 = * ADD byref /--* t4178 byref N002 ( 3, 3) [002076] ---X------- t2076 = * IND int *** Computing fgRngChkTarget for block BB183 Lower ARR_LENGTH: N017 ( 1, 1) [002106] ----------- t2106 = LCL_VAR ref V110 tmp70 u:1 /--* t2106 ref N018 ( 3, 3) [002959] ---X------- t2959 = * ARR_LENGTH int After Lower IND: N017 ( 1, 1) [002106] ----------- t2106 = LCL_VAR ref V110 tmp70 u:1 [004179] ----------- t4179 = CNS_INT long 8 /--* t2106 ref +--* t4179 long [004180] ----------- t4180 = * ADD byref /--* t4180 byref N018 ( 3, 3) [002959] ---X------- t2959 = * IND int *** Computing fgRngChkTarget for block BB183 outgoingArgSpaceSize 0 sufficient for call [002082], which needs 0 Lower ARR_LENGTH: N001 ( 1, 1) [002135] ----------- t2135 = LCL_VAR ref V114 tmp74 u:1 /--* t2135 ref N002 ( 3, 3) [002136] ---X------- t2136 = * ARR_LENGTH int After Lower IND: N001 ( 1, 1) [002135] ----------- t2135 = LCL_VAR ref V114 tmp74 u:1 [004181] ----------- t4181 = CNS_INT long 8 /--* t2135 ref +--* t4181 long [004182] ----------- t4182 = * ADD byref /--* t4182 byref N002 ( 3, 3) [002136] ---X------- t2136 = * IND int *** Computing fgRngChkTarget for block BB188 Lower ARR_LENGTH: N017 ( 1, 1) [002166] ----------- t2166 = LCL_VAR ref V114 tmp74 u:1 /--* t2166 ref N018 ( 3, 3) [002993] ---X------- t2993 = * ARR_LENGTH int After Lower IND: N017 ( 1, 1) [002166] ----------- t2166 = LCL_VAR ref V114 tmp74 u:1 [004183] ----------- t4183 = CNS_INT long 8 /--* t2166 ref +--* t4183 long [004184] ----------- t4184 = * ADD byref /--* t4184 byref N018 ( 3, 3) [002993] ---X------- t2993 = * IND int *** Computing fgRngChkTarget for block BB188 outgoingArgSpaceSize 0 sufficient for call [002142], which needs 0 *** Computing fgRngChkTarget for block BB192 outgoingArgSpaceSize 0 sufficient for call [002198], which needs 0 *** Computing fgRngChkTarget for block BB203 outgoingArgSpaceSize 0 sufficient for call [002256], which needs 0 *** Computing fgRngChkTarget for block BB216 outgoingArgSpaceSize 0 sufficient for call [000508], which needs 0 *** Computing fgRngChkTarget for block BB228 outgoingArgSpaceSize 0 sufficient for call [002360], which needs 0 *** Computing fgRngChkTarget for block BB234 outgoingArgSpaceSize 0 sufficient for call [002408], which needs 0 *** Computing fgRngChkTarget for block BB237 outgoingArgSpaceSize 0 sufficient for call [002454], which needs 0 *** Computing fgRngChkTarget for block BB243 outgoingArgSpaceSize 0 sufficient for call [002503], which needs 0 outgoingArgSpaceSize 0 sufficient for call [001630], which needs 0 outgoingArgSpaceSize 0 sufficient for call [004154], which needs 0 *************** Finishing PHASE Do 'simple' lowering Trees after Do 'simple' lowering ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch) i bwd LIR BB10 [0009] 1 BB09 8 1 [083..0A1)-> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch) i bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB09 8 1 [0CF..0D8)-> BB47 (always) i bwd LIR BB18 [0017] 1 BB10 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd LIR BB21 [0020] 1 BB10 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB10 8 1 [0FB..102)-> BB47 ( cond ) i bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd LIR BB30 [0029] 1 BB09 8 1 [12C..137)-> BB47 (always) i bwd LIR BB31 [0031] 3 BB09(2),BB32 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd LIR BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd LIR BB47 [0047] 24 BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46 64 1 [204..20F)-> BB50 ( cond ) i bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd LIR BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i LIR BB245 [0190] 25 BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd LIR BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd LIR BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src LIR BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd LIR BB137 [0117] 1 BB136 2 3 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch) i bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB137,BB138 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd LIR BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd LIR BB171 [0143] 1 BB138 2 3 [564..571)-> BB245 ( cond ) i bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd LIR BB186 [0149] 1 BB137 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd LIR BB194 [0151] 4 BB137(2),BB192,BB193 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src LIR BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB137(2),BB138(2),BB140,BB143 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd LIR BB254 [0363] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} [003780] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn $42 /--* t0 byref this in x0 +--* t2543 long r2r cell in x11 N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void [003781] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 1, 2) [000002] ----------- t2 = CNS_INT int 0 $c0 /--* t2 int N003 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 [003782] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] N001 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] ----------- t2547 = CNS_INT long 16 $200 /--* t2546 byref +--* t2547 long N003 ( 3, 4) [002548] -----O----- t2548 = * ADD byref $240 /--* t2548 byref N005 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 [003783] ----------- IL_OFFSET void INLRT @ 0x009[E-] N001 ( 1, 2) [001497] ----------- t1497 = CNS_INT int 0 $c0 N002 ( 1, 1) [001502] ----------- t1502 = LCL_VAR byref V76 tmp36 u:1 $240 N003 ( 1, 2) [002555] ----------- t2555 = CNS_INT long 8 $201 /--* t1502 byref +--* t2555 long N004 ( 3, 4) [002556] -------N--- t2556 = * ADD byref $241 /--* t2556 byref N005 ( 4, 3) [001503] ---XG------ t1503 = * IND int /--* t1497 int +--* t1503 int N006 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 (last use) $240 /--* t1501 byref N008 ( 3, 2) [001505] n---GO----- t1505 = * IND byref /--* t1505 byref N011 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 N012 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 /--* t2552 long N015 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 N001 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] $246 /--* t2558 byref N003 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 N004 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3710 byref N007 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 N008 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] $342 /--* t2561 int N010 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 N011 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 $342 /--* t3690 int N014 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 [003784] ----------- IL_OFFSET void INLRT @ 0x011[E-] N001 ( 1, 1) [000011] ----------- t11 = LCL_VAR long V17 loc13 u:1 (last use) /--* t11 long N002 ( 4, 3) [000012] ---XG------ t12 = * IND ubyte N003 ( 1, 2) [000013] ----------- t13 = CNS_INT int 0 $c0 /--* t12 ubyte +--* t13 int N004 ( 6, 6) [000014] J--XG--N--- t14 = * EQ int /--* t14 int N005 ( 8, 8) [000015] ---XG------ * JTRUE void ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2565 byref N003 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 N004 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2568 int N006 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 N001 ( 1, 1) [001472] ----------- t1472 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002571] ----------- t2571 = CNS_INT long 8 $201 /--* t1472 byref +--* t2571 long N003 ( 3, 4) [002572] -------N--- t2572 = * ADD byref $247 /--* t2572 byref N004 ( 5, 4) [001473] n---GO----- t1473 = * IND bool N005 ( 1, 2) [001474] ----------- t1474 = CNS_INT int 0 $c0 /--* t1473 bool +--* t1474 int N006 ( 7, 7) [001475] J---GO-N--- t1475 = * NE int /--* t1475 int N007 ( 9, 9) [001476] ----GO----- * JTRUE void $301 ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} N001 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2574 byref N003 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 N004 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2577 int N006 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 N001 ( 1, 2) [001489] ----------- t1489 = CNS_INT int 0 $c0 /--* t1489 int N003 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} N001 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2581 byref N003 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 N004 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2584 int N006 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 N001 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 $c1 /--* t1482 int N003 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 ------------ BB05 [025..026), preds={BB01} succs={BB06} N001 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2588 byref N003 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 N004 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2591 int N006 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 N001 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 $c2 /--* t21 int N003 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} N001 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 (last use) $342 /--* t2596 byref +--* t2597 int N003 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct $141 N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2595 struct arg1 x0,x1 +--* t29 int arg2 in x2 +--* t2594 long r2r cell in x11 N006 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int $2c1 /--* t30 int N008 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} [003785] ----------- IL_OFFSET void INLRT @ 0x02D[E-] N001 ( 1, 2) [000035] ----------- t35 = CNS_INT int 0 $c0 /--* t35 int N003 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 [003786] ----------- IL_OFFSET void INLRT @ 0x02F[E-] N001 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 $c4 /--* t38 int N003 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 [003787] ----------- IL_OFFSET void INLRT @ 0x031[E-] N001 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF $c9 /--* t41 int N003 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 [003788] ----------- IL_OFFSET void INLRT @ 0x037[E-] N001 ( 1, 2) [000044] ----------- t44 = CNS_INT int 0 $c0 /--* t44 int N003 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 [003789] ----------- IL_OFFSET void INLRT @ 0x039[E-] N001 ( 1, 2) [002598] ----------- t2598 = CNS_INT int 0 $c0 /--* t2598 int N003 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 [003790] ----------- IL_OFFSET void INLRT @ 0x03C[E-] N001 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 $c4 /--* t50 int N003 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 [003791] ----------- IL_OFFSET void INLRT @ 0x03F[E-] N001 ( 1, 2) [002599] ----------- t2599 = CNS_INT int 0 $c0 /--* t2599 int N003 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 [003792] ----------- IL_OFFSET void INLRT @ 0x042[E-] N001 ( 1, 2) [000056] ----------- t56 = CNS_INT int 0 $c0 /--* t56 int N003 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 [003793] ----------- IL_OFFSET void INLRT @ 0x045[E-] N001 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 $283 /--* t59 int N003 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 [003794] ----------- IL_OFFSET void INLRT @ 0x049[E-] N001 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3712 byref N003 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 [003795] ----------- IL_OFFSET void INLRT @ 0x049[E-] N001 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 $246 /--* t1512 byref N003 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 [003796] ----------- IL_OFFSET void INLRT @ 0x051[E-] N001 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 (last use) $246 /--* t69 byref N003 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 N004 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 (last use) $3c4 /--* t2609 long N007 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} [003797] ----------- IL_OFFSET void INLRT @ 0x05B[E-] N001 ( 1, 1) [001226] ----------- t1226 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] ----------- t1227 = CNS_INT int 69 $d2 /--* t1226 int +--* t1227 int N003 ( 3, 4) [001228] N------N-U- t1228 = * GT int /--* t1228 int N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void ------------ BB09 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31,BB10[def] (switch), preds={BB08} succs={BB10,BB17,BB30,BB31,BB47} [003798] ----------- IL_OFFSET void INLRT @ 0x061[E-] N001 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] ----------- t1362 = CNS_INT int -34 $d6 /--* t1361 int +--* t1362 int N003 ( 3, 4) [001363] ----------- t1363 = * ADD int /--* t1363 int N004 ( 13, 9) [001364] ----------- * SWITCH void $VN.Void ------------ BB10 [083..0A1) -> BB23,BB47,BB21,BB47,BB18,BB11[def] (switch), preds={BB09} succs={BB11,BB18,BB21,BB23,BB47} [003799] ----------- IL_OFFSET void INLRT @ 0x083[E-] N001 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] ----------- t1366 = CNS_INT int -44 $d7 /--* t1365 int +--* t1366 int N003 ( 3, 4) [001367] ----------- t1367 = * ADD int /--* t1367 int N004 ( 13, 9) [001368] ----------- * SWITCH void $VN.Void ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} [003800] ----------- IL_OFFSET void INLRT @ 0x0A1[E-] N001 ( 1, 1) [001369] ----------- t1369 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] ----------- t1370 = CNS_INT int 69 $d2 /--* t1369 int +--* t1370 int N003 ( 3, 4) [001371] J------N--- t1371 = * EQ int /--* t1371 int N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} [003801] ----------- IL_OFFSET void INLRT @ 0x0AF[E-] N001 ( 1, 1) [001230] ----------- t1230 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] ----------- t1231 = CNS_INT int 92 $d3 /--* t1230 int +--* t1231 int N003 ( 3, 4) [001232] J------N--- t1232 = * EQ int /--* t1232 int N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} [003802] ----------- IL_OFFSET void INLRT @ 0x0B8[E-] N001 ( 1, 1) [001257] ----------- t1257 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] ----------- t1258 = CNS_INT int 101 $d4 /--* t1257 int +--* t1258 int N003 ( 3, 4) [001259] J------N--- t1259 = * EQ int /--* t1259 int N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} [003803] ----------- IL_OFFSET void INLRT @ 0x0C1[E-] N001 ( 1, 1) [001352] ----------- t1352 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- t1353 = CNS_INT int 0x2030 $d5 /--* t1352 int +--* t1353 int N003 ( 3, 6) [001354] J------N--- t1354 = * NE int /--* t1354 int N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} [003804] ----------- IL_OFFSET void INLRT @ 0x137[E-] N001 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] ----------- t1357 = CNS_INT int 3 $c3 /--* t1356 int +--* t1357 int N003 ( 3, 4) [001358] ----------- t1358 = * ADD int $376 /--* t1358 int N005 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB09} succs={BB47} [003805] ----------- IL_OFFSET void INLRT @ 0x0CF[E-] N001 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] ----------- t1431 = CNS_INT int 1 $c1 /--* t1430 int +--* t1431 int N003 ( 3, 4) [001432] ----------- t1432 = * ADD int $68f /--* t1432 int N005 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB10} succs={BB19,BB20} [003806] ----------- IL_OFFSET void INLRT @ 0x0D8[E-] N001 ( 1, 1) [001373] ----------- t1373 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- t1374 = CNS_INT int 0x7FFFFFFF $c9 /--* t1373 int +--* t1374 int N003 ( 3, 6) [001375] N------N-U- t1375 = * NE int $68e /--* t1375 int N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} [003807] ----------- IL_OFFSET void INLRT @ 0x0E0[E-] N001 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 $28a /--* t1385 int N003 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} [003808] ----------- IL_OFFSET void INLRT @ 0x0E2[E-] N001 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] ----------- t1378 = CNS_INT int 1 $c1 /--* t1377 int +--* t1378 int N003 ( 3, 4) [001379] ----------- t1379 = * ADD int $68f /--* t1379 int N005 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 [003809] ----------- IL_OFFSET void INLRT @ 0x0E6[E-] N001 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 $68f /--* t1382 int N003 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB10} succs={BB22,BB47} [003810] ----------- IL_OFFSET void INLRT @ 0x0ED[E-] N001 ( 1, 1) [001388] ----------- t1388 = LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] ----------- t1389 = CNS_INT int 0 $c0 /--* t1388 int +--* t1389 int N003 ( 3, 4) [001390] J------N--- t1390 = * GE int $690 /--* t1390 int N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} [003811] ----------- IL_OFFSET void INLRT @ 0x0F4[E-] N001 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 $28a /--* t1392 int N003 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB10} succs={BB24,BB47} [003812] ----------- IL_OFFSET void INLRT @ 0x0FB[E-] N001 ( 1, 1) [001395] ----------- t1395 = LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] ----------- t1396 = CNS_INT int 0 $c0 /--* t1395 int +--* t1396 int N003 ( 6, 4) [001397] -------N--- t1397 = * LE int $691 N004 ( 1, 1) [001399] ----------- t1399 = LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] ----------- t1400 = CNS_INT int 0 $c0 /--* t1399 int +--* t1400 int N006 ( 6, 4) [001401] -------N--- t1401 = * GE int $690 /--* t1397 int +--* t1401 int N007 ( 13, 9) [003726] J------N--- t3726 = * AND int /--* t3726 int N008 ( 15, 11) [001398] ----------- * JTRUE void $VN.Void ------------ BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} [003813] ----------- IL_OFFSET void INLRT @ 0x102[E-] N001 ( 0, 0) [003727] ----------- NOP void [003814] ----------- IL_OFFSET void INLRT @ 0x109[E-] N001 ( 1, 1) [001403] ----------- t1403 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] ----------- t1404 = CNS_INT int 0 $c0 /--* t1403 int +--* t1404 int N003 ( 3, 4) [001405] J------N--- t1405 = * LT int $692 /--* t1405 int N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void ------------ BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} [003815] ----------- IL_OFFSET void INLRT @ 0x10E[E-] N001 ( 1, 1) [001413] ----------- t1413 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- t1414 = LCL_VAR int V04 loc0 u:2 $28a /--* t1413 int +--* t1414 int N003 ( 3, 3) [001415] N------N-U- t1415 = * NE int $693 /--* t1415 int N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} [003816] ----------- IL_OFFSET void INLRT @ 0x113[E-] N001 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] ----------- t1421 = CNS_INT int 1 $c1 /--* t1420 int +--* t1421 int N003 ( 3, 4) [001422] ----------- t1422 = * ADD int $694 /--* t1422 int N005 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 ------------ BB28 [11E..121), preds={BB26} succs={BB29} [003817] ----------- IL_OFFSET void INLRT @ 0x11E[E-] N001 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 $c1 /--* t2612 int N003 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 ------------ BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} [003818] ----------- IL_OFFSET void INLRT @ 0x121[E-] N001 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 $28a /--* t1407 int N003 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 [003819] ----------- IL_OFFSET void INLRT @ 0x124[E-] N001 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 $c1 /--* t1410 int N003 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 ------------ BB30 [12C..137) -> BB47 (always), preds={BB09} succs={BB47} [003820] ----------- IL_OFFSET void INLRT @ 0x12C[E-] N001 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] ----------- t1426 = CNS_INT int 2 $c2 /--* t1425 int +--* t1426 int N003 ( 3, 4) [001427] ----------- t1427 = * ADD int $695 /--* t1427 int N005 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 ------------ BB31 [142..150) -> BB47 (cond), preds={BB09(2),BB32} succs={BB32,BB47} [003821] ----------- IL_OFFSET void INLRT @ 0x142[E-] N001 ( 1, 1) [001435] ----------- t1435 = LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- t3693 = LCL_VAR int V179 cse8 u:1 $342 /--* t1435 int +--* t3693 int N003 ( 6, 3) [001440] -------N--- t1440 = * GE int $8b7 N004 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1443 int N006 ( 2, 3) [001444] ----------- t1444 = * CAST long <- int $3de N007 ( 1, 2) [001446] ----------- t1446 = CNS_INT long 1 $204 /--* t1444 long +--* t1446 long N008 ( 4, 6) [001447] ----------- t1447 = * LSH long $3df /--* t1442 long +--* t1447 long N009 ( 6, 8) [001448] -------N--- t1448 = * ADD long $3e0 /--* t1448 long N010 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort /--* t1449 ushort N012 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 N013 ( 1, 1) [003626] ----------- t3626 = LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] ----------- t1450 = CNS_INT int 0 $c0 /--* t3626 int +--* t1450 int N016 ( 15, 14) [001451] ---XG--N--- t1451 = * EQ int /--* t1440 int +--* t1451 int N017 ( 22, 18) [003728] J--XG--N--- t3728 = * AND int /--* t3728 int N018 ( 24, 20) [001441] ---XG------ * JTRUE void $VN.Void ------------ BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} [003822] ----------- IL_OFFSET void INLRT @ 0x150[E-] N001 ( 0, 0) [003729] ----------- NOP void [003823] ----------- IL_OFFSET void INLRT @ 0x15E[E-] N001 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1454 int N003 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 [003824] ----------- IL_OFFSET void INLRT @ 0x15E[E-] N001 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] ----------- t1456 = CNS_INT int 1 $c1 /--* t1455 int +--* t1456 int N003 ( 3, 4) [001457] ----------- t1457 = * ADD int $8bc /--* t1457 int N005 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 N001 ( 1, 1) [003628] ----------- t3628 = LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- t1469 = LCL_VAR int V18 loc14 u:5 /--* t3628 int +--* t1469 int N003 ( 3, 3) [001470] N---G--N-U- t1470 = * NE int /--* t1470 int N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 ------------ BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} [003825] ----------- IL_OFFSET void INLRT @ 0x175[E-] N001 ( 1, 1) [001234] ----------- t1234 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- t3694 = LCL_VAR int V179 cse8 u:1 $342 /--* t1234 int +--* t3694 int N003 ( 6, 3) [001239] -------N--- t1239 = * GE int $36c N004 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 $361 /--* t1242 int N006 ( 2, 3) [001243] ----------- t1243 = * CAST long <- int $3c8 N007 ( 1, 2) [001245] ----------- t1245 = CNS_INT long 1 $204 /--* t1243 long +--* t1245 long N008 ( 4, 6) [001246] ----------- t1246 = * LSH long $3c9 /--* t1241 long +--* t1246 long N009 ( 6, 8) [001247] -------N--- t1247 = * ADD long $3ca /--* t1247 long N010 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort /--* t1248 ushort N012 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 N013 ( 1, 1) [003646] ----------- t3646 = LCL_VAR int V174 cse3 N015 ( 1, 2) [001249] ----------- t1249 = CNS_INT int 0 $c0 /--* t3646 int +--* t1249 int N016 ( 15, 14) [001250] ---XG--N--- t1250 = * EQ int /--* t1239 int +--* t1250 int N017 ( 22, 18) [003730] J--XG--N--- t3730 = * AND int /--* t3730 int N018 ( 24, 20) [001240] ---XG------ * JTRUE void $VN.Void ------------ BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} [003826] ----------- IL_OFFSET void INLRT @ 0x183[E-] N001 ( 0, 0) [003731] ----------- NOP void [003827] ----------- IL_OFFSET void INLRT @ 0x18E[E-] N001 ( 1, 1) [001252] ----------- t1252 = LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] ----------- t1253 = CNS_INT int 1 $c1 /--* t1252 int +--* t1253 int N003 ( 3, 4) [001254] ----------- t1254 = * ADD int $371 /--* t1254 int N005 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} [003828] ----------- IL_OFFSET void INLRT @ 0x196[E-] N001 ( 1, 1) [001261] ----------- t1261 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- t3695 = LCL_VAR int V179 cse8 u:1 $342 /--* t1261 int +--* t3695 int N003 ( 3, 3) [001266] J------N--- t1266 = * GE int $36c /--* t1266 int N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} [003829] ----------- IL_OFFSET void INLRT @ 0x1A1[E-] N001 ( 1, 1) [001341] ----------- t1341 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001342] ----------- t1342 = LCL_VAR int V16 loc12 u:17 $361 /--* t1342 int N003 ( 2, 3) [001343] ----------- t1343 = * CAST long <- int $3c8 N004 ( 1, 2) [001345] ----------- t1345 = CNS_INT long 1 $204 /--* t1343 long +--* t1345 long N005 ( 4, 6) [001346] ----------- t1346 = * LSH long $3c9 /--* t1341 long +--* t1346 long N006 ( 6, 8) [001347] -------N--- t1347 = * ADD long $3ca /--* t1347 long N007 ( 9, 10) [001348] ---XG------ t1348 = * IND ushort /--* t1348 ushort N009 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 N010 ( 1, 1) [003650] ----------- t3650 = LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] ----------- t1349 = CNS_INT int 48 $d8 /--* t3650 int +--* t1349 int N013 ( 12, 14) [001350] J--XG--N--- t1350 = * EQ int /--* t1350 int N014 ( 14, 16) [001351] ---XG------ * JTRUE void $311 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} [003830] ----------- IL_OFFSET void INLRT @ 0x1AE[E-] N001 ( 1, 1) [001268] ----------- t1268 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] ----------- t1269 = CNS_INT int 1 $c1 /--* t1268 int +--* t1269 int N003 ( 3, 4) [001270] ----------- t1270 = * ADD int $371 N004 ( 1, 1) [003696] ----------- t3696 = LCL_VAR int V179 cse8 u:1 $342 /--* t1270 int +--* t3696 int N005 ( 5, 6) [001275] J------N--- t1275 = * GE int $681 /--* t1275 int N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} [003831] ----------- IL_OFFSET void INLRT @ 0x1BB[E-] N001 ( 1, 1) [001277] ----------- t1277 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001278] ----------- t1278 = LCL_VAR int V16 loc12 u:17 $361 /--* t1278 int N003 ( 2, 3) [001279] ----------- t1279 = * CAST long <- int $3c8 N004 ( 1, 2) [001281] ----------- t1281 = CNS_INT long 1 $204 /--* t1279 long +--* t1281 long N005 ( 4, 6) [001282] ----------- t1282 = * LSH long $3c9 /--* t1277 long +--* t1282 long N006 ( 6, 8) [001283] -------N--- t1283 = * ADD long $3ca /--* t1283 long N007 ( 9, 10) [001284] ---XG------ t1284 = * IND ushort /--* t1284 ushort N009 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 N010 ( 1, 1) [003654] ----------- t3654 = LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] ----------- t1285 = CNS_INT int 43 $d9 /--* t3654 int +--* t1285 int N013 ( 12, 14) [001286] J--XG--N--- t1286 = * EQ int /--* t1286 int N014 ( 14, 16) [001287] ---XG------ * JTRUE void $311 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} [003832] ----------- IL_OFFSET void INLRT @ 0x1C8[E-] N001 ( 1, 1) [003656] ----------- t3656 = LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] ----------- t1338 = CNS_INT int 45 $da /--* t3656 int +--* t1338 int N003 ( 3, 4) [001339] N---G--N-U- t1339 = * NE int /--* t1339 int N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} [003833] ----------- IL_OFFSET void INLRT @ 0x1D5[E-] N001 ( 1, 1) [001288] ----------- t1288 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001289] ----------- t1289 = LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] ----------- t1290 = CNS_INT int 1 $c1 /--* t1289 int +--* t1290 int N004 ( 3, 4) [001291] ----------- t1291 = * ADD int $371 /--* t1291 int N005 ( 4, 6) [001292] ----------- t1292 = * CAST long <- int $3cb N006 ( 1, 2) [001294] ----------- t1294 = CNS_INT long 1 $204 /--* t1292 long +--* t1294 long N007 ( 6, 9) [001295] ----------- t1295 = * LSH long $3cc /--* t1288 long +--* t1295 long N008 ( 8, 11) [001296] -------N--- t1296 = * ADD long $3cd /--* t1296 long N009 ( 11, 13) [001297] ---XG------ t1297 = * IND ushort N010 ( 1, 2) [001298] ----------- t1298 = CNS_INT int 48 $d8 /--* t1297 ushort +--* t1298 int N011 ( 13, 16) [001299] N--XG--N-U- t1299 = * NE int /--* t1299 int N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} [003834] ----------- IL_OFFSET void INLRT @ 0x1E4[E-] N001 ( 1, 1) [001301] ----------- t1301 = LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] ----------- t1302 = CNS_INT int 1 $c1 /--* t1301 int +--* t1302 int N003 ( 3, 4) [001303] ----------- t1303 = * ADD int $942 /--* t1303 int N005 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 N001 ( 1, 1) [001307] ----------- t1307 = LCL_VAR int V73 tmp33 u:1 $942 /--* t1307 int N003 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 N001 ( 1, 1) [001306] ----------- t1306 = LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- t3697 = LCL_VAR int V179 cse8 u:1 $342 /--* t1306 int +--* t3697 int N003 ( 3, 3) [001314] J------N--- t1314 = * GE int $943 /--* t1314 int N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} [003835] ----------- IL_OFFSET void INLRT @ 0x1F4[E-] N001 ( 1, 1) [001319] ----------- t1319 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001320] ----------- t1320 = LCL_VAR int V16 loc12 u:19 $942 /--* t1320 int N003 ( 2, 3) [001321] ----------- t1321 = * CAST long <- int $3e1 N004 ( 1, 2) [001323] ----------- t1323 = CNS_INT long 1 $204 /--* t1321 long +--* t1323 long N005 ( 4, 6) [001324] ----------- t1324 = * LSH long $3e2 /--* t1319 long +--* t1324 long N006 ( 6, 8) [001325] -------N--- t1325 = * ADD long $3e3 /--* t1325 long N007 ( 9, 10) [001326] ---XG------ t1326 = * IND ushort N008 ( 1, 2) [001327] ----------- t1327 = CNS_INT int 48 $d8 /--* t1326 ushort +--* t1327 int N009 ( 11, 13) [001328] J--XG--N--- t1328 = * EQ int /--* t1328 int N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} [003836] ----------- IL_OFFSET void INLRT @ 0x201[E-] N001 ( 1, 2) [002613] ----------- t2613 = CNS_INT int 1 $c1 /--* t2613 int N003 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB09(2),BB10(2),BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46} succs={BB48,BB50} [003837] ----------- IL_OFFSET void INLRT @ 0x204[E-] N001 ( 1, 1) [000073] ----------- t73 = LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- t3698 = LCL_VAR int V179 cse8 u:1 $342 /--* t73 int +--* t3698 int N003 ( 3, 3) [000078] J------N--- t78 = * GE int $360 /--* t78 int N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} [003838] ----------- IL_OFFSET void INLRT @ 0x20F[E-] N001 ( 1, 1) [001198] ----------- t1198 = LCL_VAR int V16 loc12 u:2 $28b /--* t1198 int N003 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 [003839] ----------- IL_OFFSET void INLRT @ 0x20F[E-] N001 ( 1, 1) [001199] ----------- t1199 = LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] ----------- t1200 = CNS_INT int 1 $c1 /--* t1199 int +--* t1200 int N003 ( 3, 4) [001201] ----------- t1201 = * ADD int $361 /--* t1201 int N005 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 N001 ( 1, 1) [001197] ----------- t1197 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001206] ----------- t1206 = LCL_VAR int V71 tmp31 u:1 (last use) $28b /--* t1206 int N003 ( 2, 3) [001207] ----------- t1207 = * CAST long <- int $3c5 N004 ( 1, 2) [001209] ----------- t1209 = CNS_INT long 1 $204 /--* t1207 long +--* t1209 long N005 ( 4, 6) [001210] ----------- t1210 = * LSH long $3c6 /--* t1197 long +--* t1210 long N006 ( 6, 8) [001211] -------N--- t1211 = * ADD long $3c7 /--* t1211 long N007 ( 9, 10) [001212] ---XG------ t1212 = * IND ushort /--* t1212 ushort N009 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 N001 ( 1, 1) [001216] ----------- t1216 = LCL_VAR int V72 tmp32 u:1 /--* t1216 int N003 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 N001 ( 1, 1) [001215] ----------- t1215 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] ----------- t1219 = CNS_INT int 0 $c0 /--* t1215 int +--* t1219 int N003 ( 3, 4) [001220] J------N--- t1220 = * EQ int /--* t1220 int N004 ( 5, 6) [001221] ----------- * JTRUE void $VN.Void ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} [003840] ----------- IL_OFFSET void INLRT @ 0x222[E-] N001 ( 1, 1) [001222] ----------- t1222 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] ----------- t1223 = CNS_INT int 59 $d1 /--* t1222 int +--* t1223 int N003 ( 3, 4) [001224] N------N-U- t1224 = * NE int /--* t1224 int N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} [003841] ----------- IL_OFFSET void INLRT @ 0x22B[E-] N001 ( 1, 2) [000081] ----------- t81 = CNS_INT long 0 $205 /--* t81 long N003 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 [003842] ----------- IL_OFFSET void INLRT @ 0x22F[E-] N001 ( 1, 1) [000084] ----------- t84 = LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] ----------- t85 = CNS_INT int 0 $c0 /--* t84 int +--* t85 int N003 ( 3, 4) [000086] J------N--- t86 = * GE int $690 /--* t86 int N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void ------------ BB51 [233..235), preds={BB50} succs={BB52} [003843] ----------- IL_OFFSET void INLRT @ 0x233[E-] N001 ( 1, 1) [001194] ----------- t1194 = LCL_VAR int V04 loc0 u:2 $28a /--* t1194 int N003 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} [003844] ----------- IL_OFFSET void INLRT @ 0x235[E-] N001 ( 1, 1) [000088] ----------- t88 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] ----------- t89 = CNS_INT int 0 $c0 /--* t88 int +--* t89 int N003 ( 3, 4) [000090] J------N--- t90 = * LT int $692 /--* t90 int N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} [003845] ----------- IL_OFFSET void INLRT @ 0x23A[E-] N001 ( 1, 1) [001180] ----------- t1180 = LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- t1181 = LCL_VAR int V05 loc1 u:3 $28d /--* t1180 int +--* t1181 int N003 ( 3, 3) [001182] N------N-U- t1182 = * NE int $696 /--* t1182 int N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} [003846] ----------- IL_OFFSET void INLRT @ 0x23F[E-] N001 ( 1, 1) [001187] ----------- t1187 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 1) [001188] ----------- t1188 = LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- t1189 = CNS_INT int 3 $c3 /--* t1188 int +--* t1189 int N004 ( 6, 6) [001190] ----------- t1190 = * MUL int $697 /--* t1187 int +--* t1190 int N005 ( 8, 8) [001191] ----------- t1191 = * SUB int $698 /--* t1191 int N007 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} [003847] ----------- IL_OFFSET void INLRT @ 0x24A[E-] N001 ( 1, 2) [002615] ----------- t2615 = CNS_INT int 1 $c1 /--* t2615 int N003 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} [003848] ----------- IL_OFFSET void INLRT @ 0x24D[E-] N001 ( 1, 1) [000092] ----------- t92 = LCL_VAR long V17 loc13 u:1 /--* t92 long N002 ( 4, 3) [000093] ---XG------ t93 = * IND ubyte N003 ( 1, 2) [000094] ----------- t94 = CNS_INT int 0 $c0 /--* t93 ubyte +--* t94 int N004 ( 6, 6) [000095] J--XG--N--- t95 = * EQ int /--* t95 int N005 ( 8, 8) [000096] ---XG------ * JTRUE void ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} [003849] ----------- IL_OFFSET void INLRT @ 0x252[E-] N001 ( 1, 1) [002618] ----------- t2618 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] ----------- t2619 = CNS_INT long 4 $207 /--* t2618 byref +--* t2619 long N003 ( 3, 4) [002620] -----O----- t2620 = * ADD byref $24a /--* t2620 byref N005 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 N001 ( 1, 1) [001131] ----------- t1131 = LCL_VAR byref V69 tmp29 u:1 $24a /--* t1131 byref N002 ( 3, 2) [001132] n---GO----- t1132 = * IND int N003 ( 1, 1) [001133] ----------- t1133 = LCL_VAR int V13 loc9 u:3 (last use) $28e /--* t1132 int +--* t1133 int N004 ( 5, 4) [001134] ----GO----- t1134 = * ADD int N005 ( 1, 1) [001130] ----------- t1130 = LCL_VAR byref V69 tmp29 u:1 (last use) $24a /--* t1130 byref +--* t1134 int [003850] -A--GO----- * STOREIND int [003851] ----------- IL_OFFSET void INLRT @ 0x25E[E-] N001 ( 1, 1) [001137] ----------- t1137 = LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] ----------- t1138 = CNS_INT int 0 $c0 /--* t1137 int +--* t1138 int N003 ( 3, 4) [001139] J------N--- t1139 = * NE int $6a7 /--* t1139 int N004 ( 5, 6) [001140] ----------- * JTRUE void $VN.Void ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} [003852] ----------- IL_OFFSET void INLRT @ 0x262[E-] N001 ( 1, 1) [001171] ----------- t1171 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002622] ----------- t2622 = CNS_INT long 4 $207 /--* t1171 byref +--* t2622 long N003 ( 3, 4) [002623] -------N--- t2623 = * ADD byref $24a /--* t2623 byref N004 ( 4, 3) [001172] n---GO----- t1172 = * IND int N005 ( 1, 1) [001173] ----------- t1173 = LCL_VAR int V04 loc0 u:2 $28a /--* t1172 int +--* t1173 int N006 ( 6, 5) [001174] ----GO----- t1174 = * ADD int N007 ( 1, 1) [001175] ----------- t1175 = LCL_VAR int V05 loc1 u:3 $28d /--* t1174 int +--* t1175 int N008 ( 8, 7) [001176] ----GO----- t1176 = * SUB int /--* t1176 int N010 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} [003853] ----------- IL_OFFSET void INLRT @ 0x26E[E-] N001 ( 1, 1) [001141] ----------- t1141 = LCL_VAR int V04 loc0 u:2 $28a /--* t1141 int N003 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} [003854] ----------- IL_OFFSET void INLRT @ 0x271[E-] N001 ( 1, 1) [001145] ----------- t1145 = LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- t1148 = LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- t2624 = CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- t1150 = CNS_INT int 0 $c0 /--* t1145 int arg2 in x1 +--* t1148 byref arg1 in x0 +--* t2624 long r2r cell in x11 +--* t1150 int arg3 in x2 N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void [003855] ----------- IL_OFFSET void INLRT @ 0x27A[E-] N001 ( 1, 1) [001152] ----------- t1152 = LCL_VAR long V17 loc13 u:1 /--* t1152 long N002 ( 4, 3) [001153] ---XG------ t1153 = * IND ubyte N003 ( 1, 2) [001154] ----------- t1154 = CNS_INT int 0 $c0 /--* t1153 ubyte +--* t1154 int N004 ( 6, 6) [001155] J--XG--N--- t1155 = * NE int /--* t1155 int N005 ( 8, 8) [001156] ---XG------ * JTRUE void ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} [003856] ----------- IL_OFFSET void INLRT @ 0x27F[E-] N001 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] $3ce /--* t3713 byref +--* t2628 long N003 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct $142 N004 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 $c2 /--* t2626 struct arg1 x0,x1 +--* t2625 long r2r cell in x11 +--* t1158 int arg2 in x2 N006 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int $2c4 /--* t1159 int N008 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 [003857] ----------- IL_OFFSET void INLRT @ 0x288[E-] N001 ( 1, 1) [001164] ----------- t1164 = LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- t1165 = LCL_VAR int V15 loc11 u:2 $283 /--* t1164 int +--* t1165 int N003 ( 3, 3) [001166] J------N--- t1166 = * EQ int $6b6 /--* t1166 int N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} [003858] ----------- IL_OFFSET void INLRT @ 0x28E[E-] N001 ( 1, 1) [001168] ----------- t1168 = LCL_VAR int V16 loc12 u:16 (last use) $2c4 /--* t1168 int N003 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} [003859] ----------- IL_OFFSET void INLRT @ 0x297[E-] N001 ( 1, 1) [000097] ----------- t97 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002629] ----------- t2629 = CNS_INT long 10 $206 /--* t97 byref +--* t2629 long N003 ( 3, 4) [002630] -------N--- t2630 = * ADD byref $249 /--* t2630 byref N004 ( 5, 4) [000098] n---GO----- t98 = * IND ubyte N005 ( 1, 2) [000099] ----------- t99 = CNS_INT int 3 $c3 /--* t98 ubyte +--* t99 int N006 ( 7, 7) [000100] J---GO-N--- t100 = * EQ int /--* t100 int N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} [003860] ----------- IL_OFFSET void INLRT @ 0x2A0[E-] N001 ( 1, 1) [001122] ----------- t1122 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002631] ----------- t2631 = CNS_INT long 8 $201 /--* t1122 byref +--* t2631 long N003 ( 3, 4) [002632] -------N--- t2632 = * ADD byref $247 N005 ( 1, 2) [001123] ----------- t1123 = CNS_INT int 0 $c0 /--* t2632 byref +--* t1123 int [003861] -A--GO----- * STOREIND bool ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} [003862] ----------- IL_OFFSET void INLRT @ 0x2A7[E-] N001 ( 1, 1) [000102] ----------- t102 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002633] ----------- t2633 = CNS_INT long 4 $207 /--* t102 byref +--* t2633 long N003 ( 3, 4) [002634] -------N--- t2634 = * ADD byref $24a N005 ( 1, 2) [000103] ----------- t103 = CNS_INT int 0 $c0 /--* t2634 byref +--* t103 int [003863] -A--GO----- * STOREIND int ------------ BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} [003864] ----------- IL_OFFSET void INLRT @ 0x2AE[E-] N001 ( 0, 0) [003778] ----------- NOP void [003865] ----------- IL_OFFSET void INLRT @ 0x2B2[E-] N001 ( 1, 1) [000106] ----------- t106 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- t107 = LCL_VAR int V05 loc1 u:3 $28d /--* t106 int +--* t107 int N003 ( 3, 3) [000108] J------N--- t108 = * LT int $6b7 N004 ( 1, 1) [000110] ----------- t110 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- t111 = LCL_VAR int V06 loc2 u:2 (last use) $284 /--* t110 int +--* t111 int N006 ( 3, 3) [000112] ----------- t112 = * SUB int $6b8 N007 ( 1, 2) [001118] ----------- t1118 = CNS_INT int 0 $c0 /--* t108 int +--* t112 int +--* t1118 int N008 ( 8, 9) [003777] ----------- t3777 = * SELECT int /--* t3777 int N010 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 [003866] ----------- IL_OFFSET void INLRT @ 0x2B5[E-] N001 ( 0, 0) [003779] ----------- NOP void N001 ( 3, 2) [000116] ----------- t116 = LCL_VAR int V44 tmp4 u:1 (last use) $292 /--* t116 int N003 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 [003867] ----------- IL_OFFSET void INLRT @ 0x2B9[E-] N001 ( 0, 0) [003775] ----------- NOP void [003868] ----------- IL_OFFSET void INLRT @ 0x2BD[E-] N001 ( 1, 1) [000119] ----------- t119 = LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- t120 = LCL_VAR int V05 loc1 u:3 $28d /--* t119 int +--* t120 int N003 ( 3, 3) [000121] J------N--- t121 = * GT int $6b9 N004 ( 1, 1) [000123] ----------- t123 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- t124 = LCL_VAR int V07 loc3 u:2 (last use) $285 /--* t123 int +--* t124 int N006 ( 3, 3) [000125] ----------- t125 = * SUB int $6ba N007 ( 1, 2) [001114] ----------- t1114 = CNS_INT int 0 $c0 /--* t121 int +--* t125 int +--* t1114 int N008 ( 8, 9) [003774] ----------- t3774 = * SELECT int /--* t3774 int N010 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 [003869] ----------- IL_OFFSET void INLRT @ 0x2C0[E-] N001 ( 0, 0) [003776] ----------- NOP void N001 ( 3, 2) [000129] ----------- t129 = LCL_VAR int V45 tmp5 u:1 (last use) $293 /--* t129 int N003 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 [003870] ----------- IL_OFFSET void INLRT @ 0x2C4[E-] N001 ( 1, 1) [000132] ----------- t132 = LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] ----------- t133 = CNS_INT int 0 $c0 /--* t132 int +--* t133 int N003 ( 3, 4) [000134] J------N--- t134 = * EQ int $6bb /--* t134 int N004 ( 5, 6) [000135] ----------- * JTRUE void $VN.Void ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} [003871] ----------- IL_OFFSET void INLRT @ 0x2C8[E-] N001 ( 1, 1) [001108] ----------- t1108 = LCL_VAR int V05 loc1 u:3 $28d /--* t1108 int N003 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 [003872] ----------- IL_OFFSET void INLRT @ 0x2CB[E-] N001 ( 1, 2) [001111] ----------- t1111 = CNS_INT int 0 $c0 /--* t1111 int N003 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 ------------ BB74 [2D0..2EE), preds={BB66} succs={BB78} [003873] ----------- IL_OFFSET void INLRT @ 0x2D0[E-] N001 ( 0, 0) [003772] ----------- NOP void [003874] ----------- IL_OFFSET void INLRT @ 0x2D9[E-] N001 ( 1, 1) [000136] ----------- t136 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002635] ----------- t2635 = CNS_INT long 4 $207 /--* t136 byref +--* t2635 long N003 ( 3, 4) [002636] -------N--- t2636 = * ADD byref $24a /--* t2636 byref N004 ( 4, 3) [000137] n---GO----- t137 = * IND int /--* t137 int N006 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 N007 ( 3, 2) [003684] ----------- t3684 = LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- t138 = LCL_VAR int V05 loc1 u:3 $28d /--* t3684 int +--* t138 int N010 ( 13, 10) [000139] J---GO-N--- t139 = * GT int N011 ( 3, 2) [003686] ----------- t3686 = LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- t1104 = LCL_VAR int V05 loc1 u:3 $28d /--* t139 int +--* t3686 int +--* t1104 int N013 ( 18, 14) [003771] ----GO----- t3771 = * SELECT int /--* t3771 int N015 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 [003875] ----------- IL_OFFSET void INLRT @ 0x2DC[E-] N001 ( 0, 0) [003773] ----------- NOP void N001 ( 3, 2) [000146] ----------- t146 = LCL_VAR int V46 tmp6 u:1 (last use) $295 /--* t146 int N003 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 [003876] ----------- IL_OFFSET void INLRT @ 0x2E4[E-] N001 ( 3, 2) [003687] ----------- t3687 = LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- t151 = LCL_VAR int V05 loc1 u:3 $28d /--* t3687 int +--* t151 int N003 ( 5, 4) [000152] ----G------ t152 = * SUB int /--* t152 int N005 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB74} succs={BB79,BB103} [003877] ----------- IL_OFFSET void INLRT @ 0x2EE[E-] N001 ( 1, 1) [000155] ----------- t155 = LCL_VAR int V15 loc11 u:2 $283 /--* t155 int N003 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 [003878] ----------- IL_OFFSET void INLRT @ 0x2F2[E-] [003879] ----------- IL_OFFSET void INL09 @ 0x01F[E-] <- INLRT @ ??? N001 ( 3, 3) [001550] ----------- t1550 = LCL_VAR_ADDR long V47 tmp7 $740 /--* t1550 long N003 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 [003880] ----------- IL_OFFSET void INL09 @ 0x026[E-] <- INLRT @ ??? N001 ( 1, 2) [001556] ----------- t1556 = CNS_INT int 4 $c8 /--* t1556 int N003 ( 1, 3) [001558] DA--------- * STORE_LCL_VAR int V152 tmp112 d:1 [003881] ----------- IL_OFFSET void INLRT @ 0x2FF[E-] N001 ( 1, 1) [002649] ----------- t2649 = LCL_VAR byref V151 tmp111 u:1 (last use) $24b /--* t2649 byref N003 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 N004 ( 1, 2) [003720] ----------- t3720 = CNS_INT int 4 $c8 /--* t3720 int N006 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 [003882] ----------- IL_OFFSET void INLRT @ 0x303[E-] N001 ( 1, 2) [000175] ----------- t175 = CNS_INT int -1 $c4 /--* t175 int N003 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 [003883] ----------- IL_OFFSET void INLRT @ 0x306[E-] N001 ( 1, 1) [000941] ----------- t941 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002655] ----------- t2655 = CNS_INT long 56 Fseq[] $209 /--* t941 ref +--* t2655 long N003 ( 3, 4) [002656] -------N--- t2656 = * ADD byref $24c /--* t2656 byref N004 ( 4, 3) [001570] ---XG------ t1570 = * IND ref [004155] ----------- t4155 = CNS_INT long 8 /--* t1570 ref +--* t4155 long [004156] ---XG------ t4156 = * ADD byref /--* t4156 byref N005 ( 6, 5) [000944] ---XG------ t944 = * IND int N006 ( 1, 2) [000945] ----------- t945 = CNS_INT int 0 $c0 /--* t944 int +--* t945 int N007 ( 11, 8) [000946] ---XG--N--- t946 = * LE int N008 ( 1, 1) [000178] ----------- t178 = LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] ----------- t179 = CNS_INT int 0 $c0 /--* t178 int +--* t179 int N010 ( 6, 4) [000180] -------N--- t180 = * EQ int $70a /--* t946 int +--* t180 int N011 ( 18, 13) [003732] J--XG--N--- t3732 = * AND int /--* t3732 int N012 ( 20, 15) [000181] ---XG------ * JTRUE void $VN.Void ------------ BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} [003884] ----------- IL_OFFSET void INLRT @ 0x30D[E-] N001 ( 0, 0) [003733] ----------- NOP void [003885] ----------- IL_OFFSET void INLRT @ 0x31E[E-] N001 ( 1, 1) [000948] ----------- t948 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002657] ----------- t2657 = CNS_INT long 8 Fseq[] $201 /--* t948 ref +--* t2657 long N003 ( 3, 4) [002658] -------N--- t2658 = * ADD byref $24d /--* t2658 byref N004 ( 4, 3) [000949] n---GO----- t949 = * IND ref /--* t949 ref N006 ( 4, 3) [000951] DA--GO----- * STORE_LCL_VAR ref V26 loc22 d:1 [003886] ----------- IL_OFFSET void INLRT @ 0x326[E-] N001 ( 1, 2) [000952] ----------- t952 = CNS_INT int 0 $c0 /--* t952 int N003 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 [003887] ----------- IL_OFFSET void INLRT @ 0x329[E-] N001 ( 1, 2) [000955] ----------- t955 = CNS_INT int 0 $c0 /--* t955 int N003 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 [003888] ----------- IL_OFFSET void INLRT @ 0x32C[E-] N001 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 [004157] ----------- t4157 = CNS_INT long 8 /--* t958 ref +--* t4157 long [004158] ----------- t4158 = * ADD byref /--* t4158 byref N002 ( 3, 3) [000959] ---X------- t959 = * IND int /--* t959 int N004 ( 3, 3) [000961] DA-X------- * STORE_LCL_VAR int V29 loc25 d:1 [003889] ----------- IL_OFFSET void INLRT @ 0x332[E-] N001 ( 1, 1) [000962] ----------- t962 = LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] ----------- t963 = CNS_INT int 0 $c0 /--* t962 int +--* t963 int N003 ( 3, 4) [000964] J------N--- t964 = * EQ int /--* t964 int N004 ( 5, 6) [000965] ----------- * JTRUE void $VN.Void ------------ BB81 [336..33D), preds={BB79} succs={BB82} [003890] ----------- IL_OFFSET void INLRT @ 0x336[E-] N002 ( 1, 1) [002659] ----------- t2659 = LCL_VAR ref V26 loc22 u:1 N003 ( 1, 2) [002666] ----------- t2666 = CNS_INT long 16 $200 /--* t2659 ref +--* t2666 long N004 ( 1, 1) [002667] -------N--- t2667 = * ADD byref /--* t2667 byref N006 ( 4, 3) [002671] n---GO----- t2671 = * IND int /--* t2671 int N009 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} [003891] ----------- IL_OFFSET void INLRT @ 0x33D[E-] N001 ( 1, 1) [000966] ----------- t966 = LCL_VAR int V28 loc24 u:2 $298 /--* t966 int N003 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 N001 ( 1, 1) [000969] ----------- t969 = LCL_VAR int V08 loc4 u:1 $297 /--* t969 int N003 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 [003892] ----------- IL_OFFSET void INLRT @ 0x341[E-] N001 ( 1, 1) [000970] ----------- t970 = LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] ----------- t971 = CNS_INT int 0 $c0 /--* t970 int +--* t971 int N003 ( 3, 4) [000972] J------N--- t972 = * LT int $719 /--* t972 int N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} N001 ( 3, 2) [000977] ----------- t977 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t977 int N003 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 N001 ( 1, 2) [001091] ----------- t1091 = CNS_INT int 0 $c0 /--* t1091 int N003 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} N001 ( 3, 2) [000978] ----------- t978 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t978 int N003 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 N001 ( 1, 1) [000979] ----------- t979 = LCL_VAR int V14 loc10 u:1 $296 /--* t979 int N003 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 ------------ BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} N001 ( 3, 2) [000986] ----------- t986 = LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- t987 = LCL_VAR int V66 tmp26 u:1 (last use) $299 /--* t986 int +--* t987 int N003 ( 7, 5) [000988] ----------- t988 = * ADD int $71a /--* t988 int N005 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 [003893] ----------- IL_OFFSET void INLRT @ 0x350[E-] N001 ( 0, 0) [003769] ----------- NOP void [003894] ----------- IL_OFFSET void INLRT @ 0x355[E-] N001 ( 1, 1) [000991] ----------- t991 = LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- t992 = LCL_VAR int V31 loc27 u:1 $71a /--* t991 int +--* t992 int N003 ( 5, 4) [000993] J------N--- t993 = * GT int $71b N004 ( 1, 1) [000995] ----------- t995 = LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- t1087 = LCL_VAR int V31 loc27 u:1 (last use) $71a /--* t993 int +--* t995 int +--* t1087 int N006 ( 10, 8) [003768] ----------- t3768 = * SELECT int /--* t3768 int N008 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 [003895] ----------- IL_OFFSET void INLRT @ 0x359[E-] N001 ( 0, 0) [003770] ----------- NOP void N001 ( 3, 2) [000999] ----------- t999 = LCL_VAR int V67 tmp27 u:1 (last use) $29a /--* t999 int N003 ( 3, 3) [001001] DA--------- * STORE_LCL_VAR int V32 loc28 d:1 [003896] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] N001 ( 1, 1) [003158] ----------- t3158 = LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- t3159 = LCL_VAR int V30 loc26 u:1 $298 /--* t3158 int +--* t3159 int N003 ( 3, 3) [003157] J------N--- t3157 = * LE int $71c /--* t3157 int N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void ------------ BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} [003897] ----------- IL_OFFSET void INLRT @ 0x35E[E-] N001 ( 1, 1) [001006] ----------- t1006 = LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] ----------- t1007 = CNS_INT int 0 $c0 /--* t1006 int +--* t1007 int N003 ( 3, 4) [001008] J------N--- t1008 = * EQ int $71e /--* t1008 int N004 ( 5, 6) [001009] ----------- * JTRUE void $VN.Void ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} [003898] ----------- IL_OFFSET void INLRT @ 0x362[E-] N001 ( 1, 1) [001010] ----------- t1010 = LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] ----------- t1011 = CNS_INT int 1 $c1 /--* t1010 int +--* t1011 int N003 ( 3, 4) [001012] ----------- t1012 = * ADD int $71f /--* t1012 int N005 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 [003899] ----------- IL_OFFSET void INLRT @ 0x368[E-] N001 ( 1, 1) [001015] ----------- t1015 = LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- t1574 = LCL_VAR int V144 tmp104 u:3 $29c /--* t1015 int +--* t1574 int N003 ( 3, 3) [001020] J------N--- t1020 = * LT int $720 /--* t1020 int N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} [003900] ----------- IL_OFFSET void INLRT @ 0x373[E-] N001 ( 1, 1) [001578] ----------- t1578 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] ----------- t1065 = CNS_INT int 1 $c1 /--* t1578 int +--* t1065 int N003 ( 3, 4) [001066] ----------- t1066 = * LSH int $721 /--* t1066 int N004 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int $3cf N005 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn $49 /--* t1067 long arg1 in x0 +--* t2672 long r2r cell in x11 N006 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 /--* t1068 ref N008 ( 20, 18) [001070] DA-XG------ * STORE_LCL_VAR ref V33 loc29 d:1 [003901] ----------- IL_OFFSET void INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] [003902] ----------- IL_OFFSET void INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001 ( 1, 1) [002689] ----------- t2689 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] ----------- t2690 = CNS_INT long 16 Fseq[] $200 /--* t2689 ref +--* t2690 long N003 ( 3, 4) [002691] -----O----- t2691 = * ADD byref $253 /--* t2691 byref N005 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 [003903] ----------- IL_OFFSET void INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001 ( 1, 1) [001607] ----------- t1607 = LCL_VAR ref V33 loc29 u:1 $800 [004159] ----------- t4159 = CNS_INT long 8 /--* t1607 ref +--* t4159 long [004160] ----------- t4160 = * ADD byref /--* t4160 byref N002 ( 3, 3) [001608] ---X------- t1608 = * IND int $2cc /--* t1608 int N004 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 N001 ( 1, 1) [002694] ----------- t2694 = LCL_VAR byref V159 tmp119 u:1 (last use) $382 /--* t2694 byref N003 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 N001 ( 1, 1) [001620] ----------- t1620 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- t1647 = LCL_VAR int V160 tmp120 u:1 (last use) $2a0 /--* t1620 int +--* t1647 int N003 ( 3, 3) [001628] N------N-U- t1628 = * GT int $722 /--* t1628 int N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void ------------ BB95 [000..392), preds={BB91} succs={BB100} [003904] ----------- IL_OFFSET void INL17 @ 0x00F[E-] <- INLRT @ ??? N001 ( 1, 1) [001639] ----------- t1639 = LCL_VAR int V144 tmp104 u:3 (last use) $29c /--* t1639 int N002 ( 2, 3) [001640] ---------U- t1640 = * CAST long <- ulong <- uint $3d0 /--* t1640 long N004 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 [003905] ----------- IL_OFFSET void INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? N001 ( 1, 1) [001663] ----------- t1663 = LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] ----------- t1665 = CNS_INT long 2 $20a /--* t1663 long +--* t1665 long N003 ( 3, 4) [001666] ----------- t1666 = * LSH long $3d1 N004 ( 1, 1) [001661] ----------- t1661 = LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- t1662 = LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- t2700 = CNS_INT(h) long 0x4000000000420490 ftn $4b /--* t1666 long arg3 in x2 +--* t1661 byref arg1 in x0 +--* t1662 byref arg2 in x1 +--* t2700 long r2r cell in x11 N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void [003906] ----------- IL_OFFSET void INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] [003907] ----------- IL_OFFSET void INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001 ( 1, 1) [002718] ----------- t2718 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] ----------- t2719 = CNS_INT long 16 Fseq[] $200 /--* t2718 ref +--* t2719 long N003 ( 3, 4) [002720] -----O----- t2720 = * ADD byref $253 /--* t2720 byref N005 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 [003908] ----------- IL_OFFSET void INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 (last use) $800 [004161] ----------- t4161 = CNS_INT long 8 /--* t1719 ref +--* t4161 long [004162] ----------- t4162 = * ADD byref /--* t4162 byref N002 ( 3, 3) [001720] ---X------- t1720 = * IND int $2cc /--* t1720 int N004 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 [003909] ----------- IL_OFFSET void INLRT @ 0x391[E-] N001 ( 1, 1) [002723] ----------- t2723 = LCL_VAR byref V163 tmp123 u:1 (last use) $383 /--* t2723 byref N003 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 N004 ( 1, 1) [002726] ----------- t2726 = LCL_VAR int V164 tmp124 u:1 (last use) $2a1 /--* t2726 int N006 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} [003910] ----------- IL_OFFSET void INLRT @ 0x39A[E-] N001 ( 1, 1) [001024] ----------- t1024 = LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- t1028 = LCL_VAR int V144 tmp104 u:4 $2a2 /--* t1024 int +--* t1028 int N003 ( 6, 9) [001029] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $334 N004 ( 1, 1) [001033] ----------- t1033 = LCL_VAR byref V143 tmp103 u:4 $384 N005 ( 1, 1) [001025] ----------- t1025 = LCL_VAR int V20 loc16 u:11 $71f /--* t1025 int N006 ( 2, 3) [001030] ---------U- t1030 = * CAST long <- uint $3d2 N007 ( 1, 2) [001031] ----------- t1031 = CNS_INT long 2 $20a /--* t1030 long +--* t1031 long N008 ( 4, 6) [001032] ----------- t1032 = * LSH long $3d3 /--* t1033 byref +--* t1032 long N009 ( 6, 8) [001034] -----O-N--- t1034 = * ADD byref $255 N012 ( 1, 1) [001036] ----------- t1036 = LCL_VAR int V28 loc24 u:3 $29f /--* t1034 byref +--* t1036 int [003911] -A-XGO----- * STOREIND int [003912] ----------- IL_OFFSET void INLRT @ 0x3A6[E-] N001 ( 1, 1) [001039] ----------- t1039 = LCL_VAR int V27 loc23 u:2 $29e N002 ( 1, 1) [001040] ----------- t1040 = LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] ----------- t1041 = CNS_INT int -1 $c4 /--* t1040 int +--* t1041 int N004 ( 3, 4) [001042] ----------- t1042 = * ADD int /--* t1039 int +--* t1042 int N005 ( 5, 6) [001043] J------N--- t1043 = * GE int /--* t1043 int N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} [003913] ----------- IL_OFFSET void INLRT @ 0x3AE[E-] N001 ( 1, 1) [001050] ----------- t1050 = LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] ----------- t1051 = CNS_INT int 1 $c1 /--* t1050 int +--* t1051 int N003 ( 3, 4) [001052] ----------- t1052 = * ADD int $727 /--* t1052 int N005 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 [003914] ----------- IL_OFFSET void INLRT @ 0x3B4[E-] N001 ( 1, 1) [001056] ----------- t1056 = LCL_VAR int V27 loc23 u:4 $727 N002 ( 1, 1) [001055] ----------- t1055 = LCL_VAR ref V26 loc22 u:1 [004163] ----------- t4163 = CNS_INT long 8 /--* t1055 ref +--* t4163 long [004164] ----------- t4164 = * ADD byref /--* t4164 byref N003 ( 3, 3) [002732] ---X------- t2732 = * IND int /--* t1056 int +--* t2732 int N004 ( 8, 11) [002733] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N005 ( 1, 1) [002730] ----------- t2730 = LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] ----------- t2737 = CNS_INT long 16 $200 /--* t2730 ref +--* t2737 long N007 ( 3, 4) [002738] ----------- t2738 = * ADD byref N008 ( 1, 1) [002731] ----------- t2731 = LCL_VAR int V27 loc23 u:4 $727 /--* t2731 int N009 ( 2, 3) [002734] ---------U- t2734 = * CAST long <- uint $3d4 N010 ( 1, 2) [002735] -------N--- t2735 = CNS_INT long 2 $20a /--* t2734 long +--* t2735 long N011 ( 4, 6) [002736] ----------- t2736 = * LSH long $3d5 /--* t2738 byref +--* t2736 long N012 ( 7, 10) [002739] -------N--- t2739 = * ADD byref /--* t2739 byref N014 ( 10, 12) [002742] n---GO----- t2742 = * IND int /--* t2742 int N017 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} [003915] ----------- IL_OFFSET void INLRT @ 0x3BB[E-] N001 ( 1, 1) [001045] ----------- t1045 = LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- t1046 = LCL_VAR int V30 loc26 u:3 $2a3 /--* t1045 int +--* t1046 int N003 ( 3, 3) [001047] ----------- t1047 = * ADD int $72b /--* t1047 int N005 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 [003916] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] N001 ( 1, 1) [001002] ----------- t1002 = LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- t1003 = LCL_VAR int V28 loc24 u:4 $72b /--* t1002 int +--* t1003 int N003 ( 3, 3) [001004] J------N--- t1004 = * GT int $72c /--* t1004 int N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB85,BB89,BB102} succs={BB104,BB112} [003917] ----------- IL_OFFSET void INLRT @ 0x3C8[E-] N001 ( 1, 1) [000182] ----------- t182 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002743] ----------- t2743 = CNS_INT long 8 $201 /--* t182 byref +--* t2743 long N003 ( 3, 4) [002744] -------N--- t2744 = * ADD byref $247 /--* t2744 byref N004 ( 5, 4) [000183] n---GO----- t183 = * IND bool N005 ( 1, 2) [000184] ----------- t184 = CNS_INT int 0 $c0 /--* t183 bool +--* t184 int N006 ( 10, 7) [000185] ----GO-N--- t185 = * EQ int N007 ( 1, 1) [000927] ----------- t927 = LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] ----------- t928 = CNS_INT int 0 $c0 /--* t927 int +--* t928 int N009 ( 6, 4) [000929] -------N--- t929 = * NE int $733 /--* t185 int +--* t929 int N010 ( 17, 12) [003734] J---GO-N--- t3734 = * AND int /--* t3734 int N011 ( 19, 14) [000186] ----GO----- * JTRUE void $301 ------------ BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} [003918] ----------- IL_OFFSET void INLRT @ 0x3D0[E-] N001 ( 0, 0) [003735] ----------- NOP void [003919] ----------- IL_OFFSET void INLRT @ 0x3D4[E-] N001 ( 1, 1) [000931] ----------- t931 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002745] ----------- t2745 = CNS_INT long 4 $207 /--* t931 byref +--* t2745 long N003 ( 3, 4) [002746] -------N--- t2746 = * ADD byref $24a /--* t2746 byref N004 ( 4, 3) [000932] n---GO----- t932 = * IND int N005 ( 1, 2) [000933] ----------- t933 = CNS_INT int 0 $c0 /--* t932 int +--* t933 int N006 ( 6, 6) [000934] J---GO-N--- t934 = * EQ int /--* t934 int N007 ( 8, 8) [000935] ----GO----- * JTRUE void $301 ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} [003920] ----------- IL_OFFSET void INLRT @ 0x3DC[E-] N001 ( 1, 1) [000937] ----------- t937 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002747] ----------- t2747 = CNS_INT long 40 Fseq[] $20b /--* t937 ref +--* t2747 long N003 ( 3, 4) [002748] -------N--- t2748 = * ADD byref $259 /--* t2748 byref N004 ( 4, 3) [001730] ---XG------ t1730 = * IND ref /--* t1730 ref N006 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 [003921] ----------- IL_OFFSET void INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001732] ----------- t1732 = LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] ----------- t1733 = CNS_INT ref null $VN.Null /--* t1732 ref +--* t1733 ref N003 ( 3, 4) [001734] J------N--- t1734 = * EQ int /--* t1734 int N004 ( 5, 6) [001735] ----------- * JTRUE void $VN.Void ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} [003922] ----------- IL_OFFSET void INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [000936] ----------- t936 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002749] ----------- t2749 = CNS_INT long 8 $201 /--* t936 byref +--* t2749 long N003 ( 3, 4) [002750] -------N--- t2750 = * ADD byref $25a /--* t2750 byref N004 ( 4, 3) [001736] ---XG------ t1736 = * IND int /--* t1736 int N006 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 [003923] ----------- IL_OFFSET void INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001739] ----------- t1739 = LCL_VAR ref V86 tmp46 u:1 [004165] ----------- t4165 = CNS_INT long 8 /--* t1739 ref +--* t4165 long [004166] ----------- t4166 = * ADD byref /--* t4166 byref N002 ( 3, 3) [001740] ---X------- t1740 = * IND int N003 ( 1, 2) [001741] ----------- t1741 = CNS_INT int 1 $c1 /--* t1740 int +--* t1741 int N004 ( 8, 6) [001742] N--X---N-U- t1742 = * NE int N005 ( 3, 2) [001747] ----------- t1747 = LCL_VAR int V87 tmp47 u:1 N006 ( 1, 1) [001748] ----------- t1748 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002753] ----------- t2753 = CNS_INT long 24 $20c /--* t1748 byref +--* t2753 long N008 ( 3, 4) [002754] -------N--- t2754 = * ADD byref $25b /--* t2754 byref N009 ( 4, 3) [001786] n---GO----- t1786 = * IND int /--* t1747 int +--* t1786 int N010 ( 11, 6) [001752] N---GO-N-U- t1752 = * GE int /--* t1742 int +--* t1752 int N011 ( 20, 13) [003736] J--XGO-N--- t3736 = * AND int /--* t3736 int N012 ( 22, 15) [001743] ---XGO----- * JTRUE void ------------ BB108 [3DC..3DD), preds={BB107} succs={BB112} [003924] ----------- IL_OFFSET void INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] N001 ( 0, 0) [003737] ----------- NOP void [003925] ----------- IL_OFFSET void INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [002758] ----------- t2758 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] ----------- t2759 = CNS_INT long 16 $200 /--* t2758 byref +--* t2759 long N003 ( 3, 4) [002760] -----O----- t2760 = * ADD byref $25c /--* t2760 byref N005 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 [003926] ----------- IL_OFFSET void INL26 @ ??? <- INLRT @ 0x3DC[E-] N001 ( 3, 2) [001756] ----------- t1756 = LCL_VAR int V87 tmp47 u:1 N002 ( 1, 1) [001761] ----------- t1761 = LCL_VAR byref V88 tmp48 u:1 $25c N003 ( 1, 2) [002762] ----------- t2762 = CNS_INT long 8 $201 /--* t1761 byref +--* t2762 long N004 ( 3, 4) [002763] -------N--- t2763 = * ADD byref $25d /--* t2763 byref N005 ( 4, 3) [001762] n---GO----- t1762 = * IND int /--* t1756 int +--* t1762 int N006 ( 11, 12) [001763] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001760] ----------- t1760 = LCL_VAR byref V88 tmp48 u:1 (last use) $25c /--* t1760 byref N008 ( 3, 2) [001767] n---GO----- t1767 = * IND byref N009 ( 3, 2) [001757] ----------- t1757 = LCL_VAR int V87 tmp47 u:1 /--* t1757 int N010 ( 4, 4) [001764] ---------U- t1764 = * CAST long <- uint N011 ( 1, 2) [001765] ----------- t1765 = CNS_INT long 1 $204 /--* t1764 long +--* t1765 long N012 ( 6, 7) [001766] ----------- t1766 = * LSH long /--* t1767 byref +--* t1766 long N013 ( 10, 10) [001768] ----GO-N--- t1768 = * ADD byref N017 ( 1, 1) [002765] ----------- t2765 = LCL_VAR ref V86 tmp46 u:1 (last use) N018 ( 1, 2) [002771] ----------- t2771 = CNS_INT long 12 $20d /--* t2765 ref +--* t2771 long N019 ( 1, 1) [002772] -------N--- t2772 = * ADD byref /--* t2772 byref N021 ( 5, 4) [002777] n---GO----- t2777 = * IND ushort /--* t1768 byref +--* t2777 ushort [003927] -A-XGO----- * STOREIND short [003928] ----------- IL_OFFSET void INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] N001 ( 3, 2) [001777] ----------- t1777 = LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] ----------- t1778 = CNS_INT int 1 $c1 /--* t1777 int +--* t1778 int N003 ( 5, 5) [001779] ----------- t1779 = * ADD int N004 ( 1, 1) [001776] ----------- t1776 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002778] ----------- t2778 = CNS_INT long 8 $201 /--* t1776 byref +--* t2778 long N006 ( 3, 4) [002779] -------N--- t2779 = * ADD byref $25a /--* t2779 byref +--* t1779 int [003929] -A--GO----- * STOREIND int ------------ BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} [003930] ----------- IL_OFFSET void INLRT @ 0x3E8[E-] N001 ( 1, 2) [002781] ----------- t2781 = CNS_INT int 0 $c0 /--* t2781 int N003 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 [003931] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] N001 ( 1, 1) [003714] ----------- t3714 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3714 byref N003 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 [003932] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] N001 ( 1, 1) [001792] ----------- t1792 = LCL_VAR byref V165 tmp125 u:1 $246 /--* t1792 byref N003 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 [003933] ----------- IL_OFFSET void INLRT @ 0x3F3[E-] N001 ( 1, 1) [000197] ----------- t197 = LCL_VAR byref V165 tmp125 u:1 (last use) $246 /--* t197 byref N003 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 N004 ( 1, 1) [002791] ----------- t2791 = LCL_VAR long V169 tmp129 u:1 (last use) $3c4 /--* t2791 long N007 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 [003934] ----------- IL_OFFSET void INLRT @ 0x3F8[E-] N001 ( 1, 1) [000201] ----------- t201 = LCL_VAR long V17 loc13 u:1 /--* t201 long N003 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB138,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244} succs={BB246,BB248} [003935] ----------- IL_OFFSET void INLRT @ 0x7AA[E-] N001 ( 1, 1) [000204] ----------- t204 = LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- t3707 = LCL_VAR int V179 cse8 u:1 $342 /--* t204 int +--* t3707 int N003 ( 3, 3) [000209] J------N--- t209 = * GE int $897 /--* t209 int N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} [003936] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] N001 ( 1, 1) [000243] ----------- t243 = LCL_VAR int V16 loc12 u:4 $2ae /--* t243 int N003 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 [003937] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] N001 ( 1, 1) [000244] ----------- t244 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] ----------- t245 = CNS_INT int 1 $c1 /--* t244 int +--* t245 int N003 ( 3, 4) [000246] ----------- t246 = * ADD int $898 /--* t246 int N005 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 N001 ( 1, 1) [000242] ----------- t242 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000251] ----------- t251 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae /--* t251 int N003 ( 2, 3) [000252] ----------- t252 = * CAST long <- int $3db N004 ( 1, 2) [000254] ----------- t254 = CNS_INT long 1 $204 /--* t252 long +--* t254 long N005 ( 4, 6) [000255] ----------- t255 = * LSH long $3dc /--* t242 long +--* t255 long N006 ( 6, 8) [000256] -------N--- t256 = * ADD long $3dd /--* t256 long N007 ( 9, 10) [000257] ---XG------ t257 = * IND ushort /--* t257 ushort N009 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 N001 ( 1, 1) [000261] ----------- t261 = LCL_VAR int V50 tmp10 u:1 /--* t261 int N003 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 N001 ( 1, 1) [000260] ----------- t260 = LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] ----------- t264 = CNS_INT int 0 $c0 /--* t260 int +--* t264 int N003 ( 3, 4) [000265] J------N--- t265 = * EQ int /--* t265 int N004 ( 5, 6) [000266] ----------- * JTRUE void $VN.Void ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} [003938] ----------- IL_OFFSET void INLRT @ 0x7C8[E-] N001 ( 1, 1) [000267] ----------- t267 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] ----------- t268 = CNS_INT int 59 $d1 /--* t267 int +--* t268 int N003 ( 3, 4) [000269] N------N-U- t269 = * NE int /--* t269 int N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} [003939] ----------- IL_OFFSET void INLRT @ 0x7D1[E-] N001 ( 1, 2) [000212] ----------- t212 = CNS_INT long 0 $205 /--* t212 long N003 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 [003940] ----------- IL_OFFSET void INLRT @ 0x7D5[E-] N001 ( 1, 1) [000215] ----------- t215 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003147] ----------- t3147 = CNS_INT long 8 $201 /--* t215 byref +--* t3147 long N003 ( 3, 4) [003148] -------N--- t3148 = * ADD byref $247 /--* t3148 byref N004 ( 5, 4) [000216] n---GO----- t216 = * IND bool N005 ( 1, 2) [000217] ----------- t217 = CNS_INT int 0 $c0 /--* t216 bool +--* t217 int N006 ( 10, 7) [000218] ----GO-N--- t218 = * EQ int N007 ( 1, 1) [000221] ----------- t221 = LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] ----------- t222 = CNS_INT int 0 $c0 /--* t221 int +--* t222 int N009 ( 6, 4) [000223] -------N--- t223 = * NE int $733 /--* t218 int +--* t223 int N010 ( 17, 12) [003764] J---GO-N--- t3764 = * AND int /--* t3764 int N011 ( 19, 14) [000219] ----GO----- * JTRUE void $301 ------------ BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} [003941] ----------- IL_OFFSET void INLRT @ 0x7DD[E-] N001 ( 0, 0) [003765] ----------- NOP void [003942] ----------- IL_OFFSET void INLRT @ 0x7E1[E-] N001 ( 1, 1) [000225] ----------- t225 = LCL_VAR byref V01 arg1 u:1 (last use) $101 N002 ( 1, 2) [003149] ----------- t3149 = CNS_INT long 4 $207 /--* t225 byref +--* t3149 long N003 ( 3, 4) [003150] -------N--- t3150 = * ADD byref $24a /--* t3150 byref N004 ( 4, 3) [000226] n---GO----- t226 = * IND int N005 ( 1, 2) [000227] ----------- t227 = CNS_INT int 0 $c0 /--* t226 int +--* t227 int N006 ( 9, 6) [000228] ----GO-N--- t228 = * NE int N007 ( 1, 1) [000230] ----------- t230 = LCL_VAR byref V00 arg0 u:1 $100 N008 ( 1, 2) [003151] ----------- t3151 = CNS_INT long 8 $201 /--* t230 byref +--* t3151 long N009 ( 3, 4) [003152] -------N--- t3152 = * ADD byref $25a /--* t3152 byref N010 ( 4, 3) [002539] ---XG------ t2539 = * IND int N011 ( 1, 2) [000233] ----------- t233 = CNS_INT int 0 $c0 /--* t2539 int +--* t233 int N012 ( 9, 6) [000234] ---XG--N--- t234 = * LE int /--* t228 int +--* t234 int N013 ( 19, 13) [003766] J--XGO-N--- t3766 = * AND int /--* t3766 int N014 ( 21, 15) [000229] ---XGO----- * JTRUE void $301 ------------ BB251 [7E9..7FF), preds={BB249} succs={BB253} [003943] ----------- IL_OFFSET void INLRT @ 0x7E9[E-] N001 ( 0, 0) [003767] ----------- NOP void [003944] ----------- IL_OFFSET void INLRT @ 0x7F2[E-] N001 ( 1, 1) [000238] ----------- t238 = LCL_VAR ref V03 arg3 u:1 (last use) $180 N002 ( 1, 2) [003154] ----------- t3154 = CNS_INT long 40 Fseq[] $20b /--* t238 ref +--* t3154 long N003 ( 3, 4) [003155] -------N--- t3155 = * ADD byref $259 /--* t3155 byref N004 ( 4, 3) [002541] ---XG------ t2541 = * IND ref N005 ( 1, 1) [000236] ----------- t236 = LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- t3153 = CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- t237 = CNS_INT int 0 $c0 /--* t2541 ref arg3 in x2 +--* t236 byref this in x0 +--* t3153 long r2r cell in x11 +--* t237 int arg2 in x1 N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} [003945] ----------- IL_OFFSET void INLRT @ 0x7FF[E-] N001 ( 0, 0) [000220] ----------- RETURN void $VN.Void ------------ BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} [003946] ----------- IL_OFFSET void INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001744] ----------- t1744 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- t1745 = LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- t2780 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1744 byref this in x0 +--* t1745 ref arg2 in x1 +--* t2780 long r2r cell in x11 N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} [003947] ----------- IL_OFFSET void INLRT @ 0x401[E-] N001 ( 1, 1) [000271] ----------- t271 = LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] ----------- t272 = CNS_INT int 0 $c0 /--* t271 int +--* t272 int N003 ( 3, 4) [000273] J------N--- t273 = * LE int $89f /--* t273 int N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} [003948] ----------- IL_OFFSET void INLRT @ 0x406[E-] N001 ( 1, 1) [000821] ----------- t821 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] ----------- t822 = CNS_INT int 35 $ea /--* t821 int +--* t822 int N003 ( 6, 4) [000823] -------N--- t823 = * EQ int N004 ( 1, 1) [000919] ----------- t919 = LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- t920 = CNS_INT int 46 $eb /--* t919 int +--* t920 int N006 ( 6, 4) [000921] -------N--- t921 = * EQ int /--* t823 int +--* t921 int N007 ( 13, 9) [003738] J------N--- t3738 = * AND int /--* t3738 int N008 ( 15, 11) [000824] ----------- * JTRUE void $VN.Void ------------ BB115 [40C..418) -> BB135 (cond), preds={BB114} succs={BB117,BB135} [003949] ----------- IL_OFFSET void INLRT @ 0x40C[E-] N001 ( 0, 0) [003739] ----------- NOP void [003950] ----------- IL_OFFSET void INLRT @ 0x412[E-] N001 ( 1, 1) [000923] ----------- t923 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] ----------- t924 = CNS_INT int 48 $d8 /--* t923 int +--* t924 int N003 ( 3, 4) [000925] J------N--- t925 = * EQ int /--* t925 int N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void ------------ BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} N001 ( 1, 1) [000829] ----------- t829 = LCL_VAR byref V00 arg0 u:1 $100 /--* t829 byref N003 ( 1, 3) [000836] DA--------- * STORE_LCL_VAR byref V60 tmp20 d:1 [003951] ----------- IL_OFFSET void INLRT @ 0x41A[E-] N001 ( 1, 1) [000830] ----------- t830 = LCL_VAR long V36 loc32 u:7 $904 /--* t830 long N002 ( 4, 3) [000831] ---XG------ t831 = * IND ubyte /--* t831 ubyte N004 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 N005 ( 1, 1) [003679] ----------- t3679 = LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] ----------- t832 = CNS_INT int 0 $c0 /--* t3679 int +--* t832 int N008 ( 7, 7) [000833] J--XG--N--- t833 = * NE int /--* t833 int N009 ( 9, 9) [000834] ---XG------ * JTRUE void $c1a ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} N001 ( 1, 1) [000838] ----------- t838 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t838 byref N003 ( 1, 3) [000914] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:3 N001 ( 1, 2) [000912] ----------- t912 = CNS_INT int 48 $d8 /--* t912 int N003 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 ------------ BB120 [424..42C), preds={BB118} succs={BB121} N001 ( 1, 1) [000840] ----------- t840 = LCL_VAR long V36 loc32 u:7 $904 /--* t840 long N003 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 N001 ( 1, 1) [000841] ----------- t841 = LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] ----------- t843 = CNS_INT long 1 $204 /--* t841 long +--* t843 long N003 ( 3, 4) [000844] ----------- t844 = * ADD long $adc /--* t844 long N005 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 N001 ( 1, 1) [000839] ----------- t839 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t839 byref N003 ( 1, 3) [000852] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:2 N001 ( 1, 1) [003681] ----------- t3681 = LCL_VAR int V177 cse6 u:1 /--* t3681 int N003 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} N001 ( 1, 1) [000858] ----------- t858 = LCL_VAR int V63 tmp23 u:1 (last use) $b16 /--* t858 int N002 ( 2, 3) [001796] ----------- t1796 = * CAST int <- ushort <- int $c75 /--* t1796 int N004 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 [003952] ----------- IL_OFFSET void INL29 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000857] ----------- t857 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002794] ----------- t2794 = CNS_INT long 8 $201 /--* t857 byref +--* t2794 long N003 ( 3, 4) [002795] -------N--- t2795 = * ADD byref $25a /--* t2795 byref N004 ( 4, 3) [001797] ---XG------ t1797 = * IND int /--* t1797 int N006 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 [003953] ----------- IL_OFFSET void INL29 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [001800] ----------- t1800 = LCL_VAR int V91 tmp51 u:1 N002 ( 1, 1) [001801] ----------- t1801 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002798] ----------- t2798 = CNS_INT long 24 $20c /--* t1801 byref +--* t2798 long N004 ( 3, 4) [002799] -------N--- t2799 = * ADD byref $25b /--* t2799 byref N005 ( 4, 3) [001839] n---GO----- t1839 = * IND int /--* t1800 int +--* t1839 int N006 ( 6, 5) [001805] N---GO-N-U- t1805 = * GE int /--* t1805 int N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} [003954] ----------- IL_OFFSET void INL29 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [002803] ----------- t2803 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] ----------- t2804 = CNS_INT long 16 $200 /--* t2803 byref +--* t2804 long N003 ( 3, 4) [002805] -----O----- t2805 = * ADD byref $25c /--* t2805 byref N005 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 N001 ( 1, 1) [001812] ----------- t1812 = LCL_VAR int V91 tmp51 u:1 N002 ( 1, 1) [001817] ----------- t1817 = LCL_VAR byref V93 tmp53 u:1 $25c N003 ( 1, 2) [002807] ----------- t2807 = CNS_INT long 8 $201 /--* t1817 byref +--* t2807 long N004 ( 3, 4) [002808] -------N--- t2808 = * ADD byref $25d /--* t2808 byref N005 ( 4, 3) [001818] n---GO----- t1818 = * IND int /--* t1812 int +--* t1818 int N006 ( 9, 11) [001819] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001816] ----------- t1816 = LCL_VAR byref V93 tmp53 u:1 (last use) $25c /--* t1816 byref N008 ( 3, 2) [001823] n---GO----- t1823 = * IND byref N009 ( 1, 1) [001813] ----------- t1813 = LCL_VAR int V91 tmp51 u:1 /--* t1813 int N010 ( 2, 3) [001820] ---------U- t1820 = * CAST long <- uint N011 ( 1, 2) [001821] ----------- t1821 = CNS_INT long 1 $204 /--* t1820 long +--* t1821 long N012 ( 4, 6) [001822] ----------- t1822 = * LSH long /--* t1823 byref +--* t1822 long N013 ( 8, 9) [001824] ----GO-N--- t1824 = * ADD byref N016 ( 1, 1) [001826] ----------- t1826 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 /--* t1824 byref +--* t1826 int [003955] -A-XGO----- * STOREIND short [003956] ----------- IL_OFFSET void INL29 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [001830] ----------- t1830 = LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] ----------- t1831 = CNS_INT int 1 $c1 /--* t1830 int +--* t1831 int N003 ( 3, 4) [001832] ----------- t1832 = * ADD int N004 ( 1, 1) [001829] ----------- t1829 = LCL_VAR byref V00 arg0 u:1 (last use) $100 N005 ( 1, 2) [002810] ----------- t2810 = CNS_INT long 8 $201 /--* t1829 byref +--* t2810 long N006 ( 3, 4) [002811] -------N--- t2811 = * ADD byref $25a /--* t2811 byref +--* t1832 int [003957] -A--GO----- * STOREIND int ------------ BB123 [000..000), preds={BB121} succs={BB124} [003958] ----------- IL_OFFSET void INL29 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [001807] ----------- t1807 = LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- t1808 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- t2812 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t1807 byref this in x0 +--* t1808 int arg2 in x1 +--* t2812 long r2r cell in x11 N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} [003959] ----------- IL_OFFSET void INLRT @ 0x431[E-] N001 ( 1, 1) [000860] ----------- t860 = LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] ----------- t861 = CNS_INT int 0 $c0 /--* t860 int +--* t861 int N003 ( 6, 4) [000862] -------N--- t862 = * EQ int $70a N004 ( 1, 1) [000874] ----------- t874 = LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] ----------- t875 = CNS_INT int 1 $c1 /--* t874 int +--* t875 int N006 ( 6, 4) [000876] -------N--- t876 = * LE int $d03 /--* t862 int +--* t876 int N007 ( 13, 9) [003740] J------N--- t3740 = * AND int /--* t3740 int N008 ( 15, 11) [000863] ----------- * JTRUE void $VN.Void ------------ BB125 [435..43F) -> BB134 (cond), preds={BB124} succs={BB127,BB134} [003960] ----------- IL_OFFSET void INLRT @ 0x435[E-] N001 ( 0, 0) [003741] ----------- NOP void [003961] ----------- IL_OFFSET void INLRT @ 0x43A[E-] N001 ( 1, 1) [000885] ----------- t885 = LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- t889 = LCL_VAR int V144 tmp104 u:2 $2a6 /--* t885 int +--* t889 int N003 ( 6, 9) [000890] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $c31 N004 ( 1, 1) [000894] ----------- t894 = LCL_VAR byref V143 tmp103 u:2 $385 N005 ( 1, 1) [000886] ----------- t886 = LCL_VAR int V20 loc16 u:7 $b13 /--* t886 int N006 ( 2, 3) [000891] ---------U- t891 = * CAST long <- uint $ae2 N007 ( 1, 2) [000892] ----------- t892 = CNS_INT long 2 $20a /--* t891 long +--* t892 long N008 ( 4, 6) [000893] ----------- t893 = * LSH long $ae3 /--* t894 byref +--* t893 long N009 ( 6, 8) [000895] -----O-N--- t895 = * ADD byref $a6b /--* t895 byref N010 ( 8, 9) [002813] ---XGO----- t2813 = * IND int N012 ( 1, 2) [000898] ----------- t898 = CNS_INT int 1 $c1 /--* t2813 int +--* t898 int N013 ( 16, 21) [000899] ---XGO----- t899 = * ADD int N014 ( 1, 1) [000882] ----------- t882 = LCL_VAR int V08 loc4 u:5 $b15 /--* t899 int +--* t882 int N015 ( 21, 23) [000900] N--XGO-N-U- t900 = * NE int N016 ( 1, 1) [000878] ----------- t878 = LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] ----------- t879 = CNS_INT int 0 $c0 /--* t878 int +--* t879 int N018 ( 6, 4) [000880] -------N--- t880 = * LT int $d04 /--* t900 int +--* t880 int N019 ( 28, 28) [003742] J--XGO-N--- t3742 = * AND int /--* t3742 int N020 ( 30, 30) [000881] ---XGO----- * JTRUE void $VN.Void ------------ BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} [003962] ----------- IL_OFFSET void INLRT @ 0x43F[E-] N001 ( 0, 0) [003743] ----------- NOP void [003963] ----------- IL_OFFSET void INLRT @ 0x44F[E-] N001 ( 1, 1) [000903] ----------- t903 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002814] ----------- t2814 = CNS_INT long 56 Fseq[] $209 /--* t903 ref +--* t2814 long N003 ( 3, 4) [002815] -------N--- t2815 = * ADD byref $24c /--* t2815 byref N004 ( 4, 3) [001843] ---XG------ t1843 = * IND ref /--* t1843 ref N006 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 [003964] ----------- IL_OFFSET void INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001845] ----------- t1845 = LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] ----------- t1846 = CNS_INT ref null $VN.Null /--* t1845 ref +--* t1846 ref N003 ( 3, 4) [001847] J------N--- t1847 = * EQ int /--* t1847 int N004 ( 5, 6) [001848] ----------- * JTRUE void $VN.Void ------------ BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} [003965] ----------- IL_OFFSET void INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [000902] ----------- t902 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002816] ----------- t2816 = CNS_INT long 8 $201 /--* t902 byref +--* t2816 long N003 ( 3, 4) [002817] -------N--- t2817 = * ADD byref $25a /--* t2817 byref N004 ( 4, 3) [001849] n---GO----- t1849 = * IND int /--* t1849 int N006 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 [003966] ----------- IL_OFFSET void INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 [004167] ----------- t4167 = CNS_INT long 8 /--* t1852 ref +--* t4167 long [004168] ----------- t4168 = * ADD byref /--* t4168 byref N002 ( 3, 3) [001853] ---X------- t1853 = * IND int /--* t1853 int N004 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 N005 ( 1, 1) [003717] ----------- t3717 = LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] ----------- t1854 = CNS_INT int 1 $c1 /--* t3717 int +--* t1854 int N008 ( 9, 7) [001855] N--X---N-U- t1855 = * NE int N009 ( 1, 1) [001860] ----------- t1860 = LCL_VAR int V96 tmp56 u:1 N010 ( 1, 1) [001861] ----------- t1861 = LCL_VAR byref V00 arg0 u:1 $100 N011 ( 1, 2) [002820] ----------- t2820 = CNS_INT long 24 $20c /--* t1861 byref +--* t2820 long N012 ( 3, 4) [002821] -------N--- t2821 = * ADD byref $25b /--* t2821 byref N013 ( 4, 3) [001899] n---GO----- t1899 = * IND int /--* t1860 int +--* t1899 int N014 ( 9, 5) [001865] N---GO-N-U- t1865 = * GE int /--* t1855 int +--* t1865 int N015 ( 19, 13) [003744] J--XGO-N--- t3744 = * AND int /--* t3744 int N016 ( 21, 15) [001856] ---XGO----- * JTRUE void ------------ BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} [003967] ----------- IL_OFFSET void INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] N001 ( 0, 0) [003745] ----------- NOP void [003968] ----------- IL_OFFSET void INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [002825] ----------- t2825 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] ----------- t2826 = CNS_INT long 16 $200 /--* t2825 byref +--* t2826 long N003 ( 3, 4) [002827] -----O----- t2827 = * ADD byref $25c /--* t2827 byref N005 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 [003969] ----------- IL_OFFSET void INL32 @ ??? <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001869] ----------- t1869 = LCL_VAR int V96 tmp56 u:1 N002 ( 1, 1) [001874] ----------- t1874 = LCL_VAR byref V97 tmp57 u:1 $25c N003 ( 1, 2) [002829] ----------- t2829 = CNS_INT long 8 $201 /--* t1874 byref +--* t2829 long N004 ( 3, 4) [002830] -------N--- t2830 = * ADD byref $25d /--* t2830 byref N005 ( 4, 3) [001875] n---GO----- t1875 = * IND int /--* t1869 int +--* t1875 int N006 ( 9, 11) [001876] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001873] ----------- t1873 = LCL_VAR byref V97 tmp57 u:1 (last use) $25c /--* t1873 byref N008 ( 3, 2) [001880] n---GO----- t1880 = * IND byref N009 ( 1, 1) [001870] ----------- t1870 = LCL_VAR int V96 tmp56 u:1 /--* t1870 int N010 ( 2, 3) [001877] ---------U- t1877 = * CAST long <- uint N011 ( 1, 2) [001878] ----------- t1878 = CNS_INT long 1 $204 /--* t1877 long +--* t1878 long N012 ( 4, 6) [001879] ----------- t1879 = * LSH long /--* t1880 byref +--* t1879 long N013 ( 8, 9) [001881] ----GO-N--- t1881 = * ADD byref N016 ( 1, 2) [001884] ----------- t1884 = CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- t3719 = LCL_VAR int V181 cse10 u:1 /--* t1884 int +--* t3719 int N018 ( 6, 10) [002835] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N019 ( 1, 1) [002832] ----------- t2832 = LCL_VAR ref V95 tmp55 u:1 (last use) N020 ( 1, 2) [002838] ----------- t2838 = CNS_INT long 12 $20d /--* t2832 ref +--* t2838 long N021 ( 1, 1) [002839] -------N--- t2839 = * ADD byref /--* t2839 byref N023 ( 5, 4) [002844] n---GO----- t2844 = * IND ushort /--* t1881 byref +--* t2844 ushort [003970] -A-XGO----- * STOREIND short [003971] ----------- IL_OFFSET void INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001890] ----------- t1890 = LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] ----------- t1891 = CNS_INT int 1 $c1 /--* t1890 int +--* t1891 int N003 ( 3, 4) [001892] ----------- t1892 = * ADD int N004 ( 1, 1) [001889] ----------- t1889 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002845] ----------- t2845 = CNS_INT long 8 $201 /--* t1889 byref +--* t2845 long N006 ( 3, 4) [002846] -------N--- t2846 = * ADD byref $25a /--* t2846 byref +--* t1892 int [003972] -A--GO----- * STOREIND int ------------ BB132 [44F..450), preds={BB129} succs={BB133} [003973] ----------- IL_OFFSET void INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001857] ----------- t1857 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- t1858 = LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- t2847 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1857 byref this in x0 +--* t1858 ref arg2 in x1 +--* t2847 long r2r cell in x11 N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} [003974] ----------- IL_OFFSET void INLRT @ 0x45B[E-] N001 ( 1, 1) [000907] ----------- t907 = LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] ----------- t908 = CNS_INT int -1 $c4 /--* t907 int +--* t908 int N003 ( 3, 4) [000909] ----------- t909 = * ADD int $d27 /--* t909 int N005 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 ------------ BB134 [461..46D), preds={BB124,BB125,BB133} succs={BB135} [003975] ----------- IL_OFFSET void INLRT @ 0x461[E-] N001 ( 1, 1) [000864] ----------- t864 = LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] ----------- t865 = CNS_INT int -1 $c4 /--* t864 int +--* t865 int N003 ( 3, 4) [000866] ----------- t866 = * ADD int $d29 /--* t866 int N005 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 [003976] ----------- IL_OFFSET void INLRT @ 0x467[E-] N001 ( 1, 1) [000869] ----------- t869 = LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] ----------- t870 = CNS_INT int -1 $c4 /--* t869 int +--* t870 int N003 ( 3, 4) [000871] ----------- t871 = * ADD int $d2a /--* t871 int N005 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB134} succs={BB136,BB118} [003977] ----------- IL_OFFSET void INLRT @ 0x46D[E-] N001 ( 1, 1) [000825] ----------- t825 = LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] ----------- t826 = CNS_INT int 0 $c0 /--* t825 int +--* t826 int N003 ( 3, 4) [000827] J------N--- t827 = * GT int $c6e /--* t827 int N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} [003978] ----------- IL_OFFSET void INLRT @ 0x472[E-] N001 ( 1, 1) [000275] ----------- t275 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] ----------- t276 = CNS_INT int 69 $d2 /--* t275 int +--* t276 int N003 ( 3, 4) [000277] N------N-U- t277 = * GT int /--* t277 int N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void ------------ BB137 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194,BB138[def] (switch), preds={BB136} succs={BB138,BB145,BB186,BB194,BB242} [003979] ----------- IL_OFFSET void INLRT @ 0x478[E-] N001 ( 1, 1) [000593] ----------- t593 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] ----------- t594 = CNS_INT int -34 $d6 /--* t593 int +--* t594 int N003 ( 3, 4) [000595] ----------- t595 = * ADD int /--* t595 int N004 ( 13, 9) [000596] ----------- * SWITCH void $VN.Void ------------ BB138 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145,BB139[def] (switch), preds={BB137} succs={BB139,BB145,BB171,BB242,BB245} [003980] ----------- IL_OFFSET void INLRT @ 0x49A[E-] N001 ( 1, 1) [000597] ----------- t597 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] ----------- t598 = CNS_INT int -44 $d7 /--* t597 int +--* t598 int N003 ( 3, 4) [000599] ----------- t599 = * ADD int /--* t599 int N004 ( 13, 9) [000600] ----------- * SWITCH void $VN.Void ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} [003981] ----------- IL_OFFSET void INLRT @ 0x4B8[E-] N001 ( 1, 1) [000601] ----------- t601 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] ----------- t602 = CNS_INT int 69 $d2 /--* t601 int +--* t602 int N003 ( 3, 4) [000603] J------N--- t603 = * EQ int /--* t603 int N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} [003982] ----------- IL_OFFSET void INLRT @ 0x4C6[E-] N001 ( 1, 1) [000279] ----------- t279 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] ----------- t280 = CNS_INT int 92 $d3 /--* t279 int +--* t280 int N003 ( 3, 4) [000281] J------N--- t281 = * EQ int /--* t281 int N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} [003983] ----------- IL_OFFSET void INLRT @ 0x4CF[E-] N001 ( 1, 1) [000319] ----------- t319 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] ----------- t320 = CNS_INT int 101 $d4 /--* t319 int +--* t320 int N003 ( 3, 4) [000321] J------N--- t321 = * EQ int /--* t321 int N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} [003984] ----------- IL_OFFSET void INLRT @ 0x4D8[E-] N001 ( 1, 1) [000581] ----------- t581 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- t582 = CNS_INT int 0x2030 $d5 /--* t581 int +--* t582 int N003 ( 3, 6) [000583] J------N--- t583 = * NE int /--* t583 int N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} [003985] ----------- IL_OFFSET void INLRT @ 0x598[E-] N001 ( 1, 1) [000586] ----------- t586 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002848] ----------- t2848 = CNS_INT long 136 Fseq[] $20e /--* t586 ref +--* t2848 long N003 ( 3, 4) [002849] -------N--- t2849 = * ADD byref $26c /--* t2849 byref N004 ( 4, 3) [002066] ---XG------ t2066 = * IND ref /--* t2066 ref N006 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB137,BB138} succs={BB146,BB150} [003986] ----------- IL_OFFSET void INLRT @ 0x4E9[E-] N001 ( 1, 1) [000639] ----------- t639 = LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] ----------- t640 = CNS_INT int 0 $c0 /--* t639 int +--* t640 int N003 ( 3, 4) [000641] J------N--- t641 = * GE int $9ff /--* t641 int N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} [003987] ----------- IL_OFFSET void INLRT @ 0x4EE[E-] N001 ( 1, 1) [000731] ----------- t731 = LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] ----------- t732 = CNS_INT int 1 $c1 /--* t731 int +--* t732 int N003 ( 3, 4) [000733] ----------- t733 = * ADD int $a88 /--* t733 int N005 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 [003988] ----------- IL_OFFSET void INLRT @ 0x4F4[E-] N001 ( 1, 1) [000736] ----------- t736 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- t737 = LCL_VAR int V06 loc2 u:3 $292 /--* t736 int +--* t737 int N003 ( 3, 3) [000738] J------N--- t738 = * LE int $a89 /--* t738 int N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} [003989] ----------- IL_OFFSET void INLRT @ 0x4F9[E-] N001 ( 1, 2) [000747] ----------- t747 = CNS_INT int 0 $c0 /--* t747 int N003 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} [003990] ----------- IL_OFFSET void INLRT @ 0x4FC[E-] N001 ( 1, 2) [000740] ----------- t740 = CNS_INT int 48 $d8 /--* t740 int N003 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} N001 ( 1, 1) [000744] ----------- t744 = LCL_VAR int V58 tmp18 u:1 (last use) $2bd /--* t744 int N002 ( 2, 3) [002850] ----------- t2850 = * CAST int <- ushort <- int $a8a /--* t2850 int N004 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} [003991] ----------- IL_OFFSET void INLRT @ 0x502[E-] N001 ( 1, 1) [000643] ----------- t643 = LCL_VAR long V36 loc32 u:3 $901 /--* t643 long N002 ( 4, 3) [000644] ---XG------ t644 = * IND ubyte N003 ( 1, 2) [000645] ----------- t645 = CNS_INT int 0 $c0 /--* t644 ubyte +--* t645 int N004 ( 6, 6) [000646] J--XG--N--- t646 = * NE int /--* t646 int N005 ( 8, 8) [000647] ---XG------ * JTRUE void $a27 ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} [003992] ----------- IL_OFFSET void INLRT @ 0x507[E-] N001 ( 1, 1) [000719] ----------- t719 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- t720 = LCL_VAR int V07 loc3 u:3 $293 /--* t719 int +--* t720 int N003 ( 3, 3) [000721] J------N--- t721 = * GT int $a86 /--* t721 int N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} [003993] ----------- IL_OFFSET void INLRT @ 0x50C[E-] N001 ( 1, 2) [000727] ----------- t727 = CNS_INT int 0 $c0 /--* t727 int N003 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} [003994] ----------- IL_OFFSET void INLRT @ 0x50F[E-] N001 ( 1, 2) [000723] ----------- t723 = CNS_INT int 48 $d8 /--* t723 int N003 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 ------------ BB154 [513..51B), preds={BB150} succs={BB155} [003995] ----------- IL_OFFSET void INLRT @ 0x513[E-] N001 ( 1, 1) [000648] ----------- t648 = LCL_VAR long V36 loc32 u:3 $901 /--* t648 long N003 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 [003996] ----------- IL_OFFSET void INLRT @ 0x513[E-] N001 ( 1, 1) [000649] ----------- t649 = LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] ----------- t651 = CNS_INT long 1 $204 /--* t649 long +--* t651 long N003 ( 3, 4) [000652] ----------- t652 = * ADD long $3fb /--* t652 long N005 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 N001 ( 1, 1) [000657] ----------- t657 = LCL_VAR long V56 tmp16 u:1 (last use) $901 /--* t657 long N002 ( 4, 3) [000658] ---XG------ t658 = * IND ubyte /--* t658 ubyte N004 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} N001 ( 1, 1) [000662] ----------- t662 = LCL_VAR int V57 tmp17 u:1 (last use) $2bc /--* t662 int N002 ( 2, 3) [002851] ----------- t2851 = * CAST int <- ushort <- int $a87 /--* t2851 int N004 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} [003997] ----------- IL_OFFSET void INLRT @ 0x51D[E-] N001 ( 1, 1) [000665] ----------- t665 = LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] ----------- t666 = CNS_INT int 0 $c0 /--* t665 int +--* t666 int N003 ( 3, 4) [000667] J------N--- t667 = * EQ int $a8b /--* t667 int N004 ( 5, 6) [000668] ----------- * JTRUE void $VN.Void ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} [003998] ----------- IL_OFFSET void INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [000674] ----------- t674 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002852] ----------- t2852 = CNS_INT long 8 $201 /--* t674 byref +--* t2852 long N003 ( 3, 4) [002853] -------N--- t2853 = * ADD byref $25a /--* t2853 byref N004 ( 4, 3) [001903] ---XG------ t1903 = * IND int /--* t1903 int N006 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 [003999] ----------- IL_OFFSET void INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001906] ----------- t1906 = LCL_VAR int V99 tmp59 u:1 N002 ( 1, 1) [001907] ----------- t1907 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [002856] ----------- t2856 = CNS_INT long 24 $20c /--* t1907 byref +--* t2856 long N004 ( 3, 4) [002857] -------N--- t2857 = * ADD byref $25b /--* t2857 byref N005 ( 4, 3) [001942] n---GO----- t1942 = * IND int /--* t1906 int +--* t1942 int N006 ( 6, 5) [001911] N---GO-N-U- t1911 = * GE int /--* t1911 int N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} [004000] ----------- IL_OFFSET void INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [002861] ----------- t2861 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] ----------- t2862 = CNS_INT long 16 $200 /--* t2861 byref +--* t2862 long N003 ( 3, 4) [002863] -----O----- t2863 = * ADD byref $25c /--* t2863 byref N005 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 [004001] ----------- IL_OFFSET void INL34 @ ??? <- INLRT @ 0x521[E-] N001 ( 1, 1) [001917] ----------- t1917 = LCL_VAR int V99 tmp59 u:1 N002 ( 1, 1) [001922] ----------- t1922 = LCL_VAR byref V100 tmp60 u:1 $25c N003 ( 1, 2) [002865] ----------- t2865 = CNS_INT long 8 $201 /--* t1922 byref +--* t2865 long N004 ( 3, 4) [002866] -------N--- t2866 = * ADD byref $25d /--* t2866 byref N005 ( 4, 3) [001923] n---GO----- t1923 = * IND int /--* t1917 int +--* t1923 int N006 ( 9, 11) [001924] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001921] ----------- t1921 = LCL_VAR byref V100 tmp60 u:1 (last use) $25c /--* t1921 byref N008 ( 3, 2) [001928] n---GO----- t1928 = * IND byref N009 ( 1, 1) [001918] ----------- t1918 = LCL_VAR int V99 tmp59 u:1 /--* t1918 int N010 ( 2, 3) [001925] ---------U- t1925 = * CAST long <- uint N011 ( 1, 2) [001926] ----------- t1926 = CNS_INT long 1 $204 /--* t1925 long +--* t1926 long N012 ( 4, 6) [001927] ----------- t1927 = * LSH long /--* t1928 byref +--* t1927 long N013 ( 8, 9) [001929] ----GO-N--- t1929 = * ADD byref N016 ( 1, 1) [001931] ----------- t1931 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 /--* t1929 byref +--* t1931 int [004002] -A-XGO----- * STOREIND short [004003] ----------- IL_OFFSET void INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001935] ----------- t1935 = LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] ----------- t1936 = CNS_INT int 1 $c1 /--* t1935 int +--* t1936 int N003 ( 3, 4) [001937] ----------- t1937 = * ADD int N004 ( 1, 1) [001934] ----------- t1934 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002868] ----------- t2868 = CNS_INT long 8 $201 /--* t1934 byref +--* t2868 long N006 ( 3, 4) [002869] -------N--- t2869 = * ADD byref $25a /--* t2869 byref +--* t1937 int [004004] -A--GO----- * STOREIND int ------------ BB159 [521..522), preds={BB157} succs={BB160} [004005] ----------- IL_OFFSET void INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001913] ----------- t1913 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- t675 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- t2870 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t1913 byref this in x0 +--* t675 int arg2 in x1 +--* t2870 long r2r cell in x11 N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} [004006] ----------- IL_OFFSET void INLRT @ 0x529[E-] N001 ( 1, 1) [000677] ----------- t677 = LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] ----------- t678 = CNS_INT int 0 $c0 /--* t677 int +--* t678 int N003 ( 6, 4) [000679] -------N--- t679 = * EQ int $70a N004 ( 1, 1) [000681] ----------- t681 = LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] ----------- t682 = CNS_INT int 1 $c1 /--* t681 int +--* t682 int N006 ( 6, 4) [000683] -------N--- t683 = * LE int $a93 /--* t679 int +--* t683 int N007 ( 13, 9) [003746] J------N--- t3746 = * AND int /--* t3746 int N008 ( 15, 11) [000680] ----------- * JTRUE void $VN.Void ------------ BB161 [52D..537) -> BB170 (cond), preds={BB160} succs={BB163,BB170} [004007] ----------- IL_OFFSET void INLRT @ 0x52D[E-] N001 ( 0, 0) [003747] ----------- NOP void [004008] ----------- IL_OFFSET void INLRT @ 0x532[E-] N001 ( 1, 1) [000692] ----------- t692 = LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- t696 = LCL_VAR int V144 tmp104 u:2 $2a6 /--* t692 int +--* t696 int N003 ( 6, 9) [000697] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $a34 N004 ( 1, 1) [000701] ----------- t701 = LCL_VAR byref V143 tmp103 u:2 $385 N005 ( 1, 1) [000693] ----------- t693 = LCL_VAR int V20 loc16 u:4 $2b3 /--* t693 int N006 ( 2, 3) [000698] ---------U- t698 = * CAST long <- uint $ac0 N007 ( 1, 2) [000699] ----------- t699 = CNS_INT long 2 $20a /--* t698 long +--* t699 long N008 ( 4, 6) [000700] ----------- t700 = * LSH long $ac1 /--* t701 byref +--* t700 long N009 ( 6, 8) [000702] -----O-N--- t702 = * ADD byref $a44 /--* t702 byref N010 ( 8, 9) [002871] ---XGO----- t2871 = * IND int N012 ( 1, 2) [000705] ----------- t705 = CNS_INT int 1 $c1 /--* t2871 int +--* t705 int N013 ( 16, 21) [000706] ---XGO----- t706 = * ADD int N014 ( 1, 1) [000689] ----------- t689 = LCL_VAR int V08 loc4 u:3 $2b5 /--* t706 int +--* t689 int N015 ( 21, 23) [000707] N--XGO-N-U- t707 = * NE int N016 ( 1, 1) [000685] ----------- t685 = LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] ----------- t686 = CNS_INT int 0 $c0 /--* t685 int +--* t686 int N018 ( 6, 4) [000687] -------N--- t687 = * LT int $a94 /--* t707 int +--* t687 int N019 ( 28, 28) [003748] J--XGO-N--- t3748 = * AND int /--* t3748 int N020 ( 30, 30) [000688] ---XGO----- * JTRUE void $VN.Void ------------ BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} [004009] ----------- IL_OFFSET void INLRT @ 0x537[E-] N001 ( 0, 0) [003749] ----------- NOP void [004010] ----------- IL_OFFSET void INLRT @ 0x547[E-] N001 ( 1, 1) [000710] ----------- t710 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002872] ----------- t2872 = CNS_INT long 56 Fseq[] $209 /--* t710 ref +--* t2872 long N003 ( 3, 4) [002873] -------N--- t2873 = * ADD byref $24c /--* t2873 byref N004 ( 4, 3) [001946] ---XG------ t1946 = * IND ref /--* t1946 ref N006 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 [004011] ----------- IL_OFFSET void INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001948] ----------- t1948 = LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] ----------- t1949 = CNS_INT ref null $VN.Null /--* t1948 ref +--* t1949 ref N003 ( 3, 4) [001950] J------N--- t1950 = * EQ int /--* t1950 int N004 ( 5, 6) [001951] ----------- * JTRUE void $VN.Void ------------ BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} [004012] ----------- IL_OFFSET void INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [000709] ----------- t709 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002874] ----------- t2874 = CNS_INT long 8 $201 /--* t709 byref +--* t2874 long N003 ( 3, 4) [002875] -------N--- t2875 = * ADD byref $25a /--* t2875 byref N004 ( 4, 3) [001952] n---GO----- t1952 = * IND int /--* t1952 int N006 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 [004013] ----------- IL_OFFSET void INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001955] ----------- t1955 = LCL_VAR ref V102 tmp62 u:1 [004169] ----------- t4169 = CNS_INT long 8 /--* t1955 ref +--* t4169 long [004170] ----------- t4170 = * ADD byref /--* t4170 byref N002 ( 3, 3) [001956] ---X------- t1956 = * IND int N003 ( 1, 2) [001957] ----------- t1957 = CNS_INT int 1 $c1 /--* t1956 int +--* t1957 int N004 ( 8, 6) [001958] N--X---N-U- t1958 = * NE int N005 ( 1, 1) [001963] ----------- t1963 = LCL_VAR int V103 tmp63 u:1 N006 ( 1, 1) [001964] ----------- t1964 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002878] ----------- t2878 = CNS_INT long 24 $20c /--* t1964 byref +--* t2878 long N008 ( 3, 4) [002879] -------N--- t2879 = * ADD byref $25b /--* t2879 byref N009 ( 4, 3) [002002] n---GO----- t2002 = * IND int /--* t1963 int +--* t2002 int N010 ( 9, 5) [001968] N---GO-N-U- t1968 = * GE int /--* t1958 int +--* t1968 int N011 ( 18, 12) [003750] J--XGO-N--- t3750 = * AND int /--* t3750 int N012 ( 20, 14) [001959] ---XGO----- * JTRUE void ------------ BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} [004014] ----------- IL_OFFSET void INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] N001 ( 0, 0) [003751] ----------- NOP void [004015] ----------- IL_OFFSET void INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [002883] ----------- t2883 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] ----------- t2884 = CNS_INT long 16 $200 /--* t2883 byref +--* t2884 long N003 ( 3, 4) [002885] -----O----- t2885 = * ADD byref $25c /--* t2885 byref N005 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 [004016] ----------- IL_OFFSET void INL37 @ ??? <- INLRT @ 0x547[E-] N001 ( 1, 1) [001972] ----------- t1972 = LCL_VAR int V103 tmp63 u:1 N002 ( 1, 1) [001977] ----------- t1977 = LCL_VAR byref V104 tmp64 u:1 $25c N003 ( 1, 2) [002887] ----------- t2887 = CNS_INT long 8 $201 /--* t1977 byref +--* t2887 long N004 ( 3, 4) [002888] -------N--- t2888 = * ADD byref $25d /--* t2888 byref N005 ( 4, 3) [001978] n---GO----- t1978 = * IND int /--* t1972 int +--* t1978 int N006 ( 9, 11) [001979] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001976] ----------- t1976 = LCL_VAR byref V104 tmp64 u:1 (last use) $25c /--* t1976 byref N008 ( 3, 2) [001983] n---GO----- t1983 = * IND byref N009 ( 1, 1) [001973] ----------- t1973 = LCL_VAR int V103 tmp63 u:1 /--* t1973 int N010 ( 2, 3) [001980] ---------U- t1980 = * CAST long <- uint N011 ( 1, 2) [001981] ----------- t1981 = CNS_INT long 1 $204 /--* t1980 long +--* t1981 long N012 ( 4, 6) [001982] ----------- t1982 = * LSH long /--* t1983 byref +--* t1982 long N013 ( 8, 9) [001984] ----GO-N--- t1984 = * ADD byref N016 ( 1, 2) [001987] ----------- t1987 = CNS_INT int 0 $c0 N017 ( 1, 1) [001986] ----------- t1986 = LCL_VAR ref V102 tmp62 u:1 [004171] ----------- t4171 = CNS_INT long 8 /--* t1986 ref +--* t4171 long [004172] ----------- t4172 = * ADD byref /--* t4172 byref N018 ( 3, 3) [002892] ---X------- t2892 = * IND int /--* t1987 int +--* t2892 int N019 ( 8, 12) [002893] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002890] ----------- t2890 = LCL_VAR ref V102 tmp62 u:1 (last use) N021 ( 1, 2) [002896] ----------- t2896 = CNS_INT long 12 $20d /--* t2890 ref +--* t2896 long N022 ( 1, 1) [002897] -------N--- t2897 = * ADD byref /--* t2897 byref N024 ( 5, 4) [002902] n---GO----- t2902 = * IND ushort /--* t1984 byref +--* t2902 ushort [004017] -A-XGO----- * STOREIND short [004018] ----------- IL_OFFSET void INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001993] ----------- t1993 = LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] ----------- t1994 = CNS_INT int 1 $c1 /--* t1993 int +--* t1994 int N003 ( 3, 4) [001995] ----------- t1995 = * ADD int N004 ( 1, 1) [001992] ----------- t1992 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002903] ----------- t2903 = CNS_INT long 8 $201 /--* t1992 byref +--* t2903 long N006 ( 3, 4) [002904] -------N--- t2904 = * ADD byref $25a /--* t2904 byref +--* t1995 int [004019] -A--GO----- * STOREIND int ------------ BB168 [547..548), preds={BB165} succs={BB169} [004020] ----------- IL_OFFSET void INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001960] ----------- t1960 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- t1961 = LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- t2905 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1960 byref this in x0 +--* t1961 ref arg2 in x1 +--* t2905 long r2r cell in x11 N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} [004021] ----------- IL_OFFSET void INLRT @ 0x553[E-] N001 ( 1, 1) [000714] ----------- t714 = LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] ----------- t715 = CNS_INT int -1 $c4 /--* t714 int +--* t715 int N003 ( 3, 4) [000716] ----------- t716 = * ADD int $ab7 /--* t716 int N005 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB169} succs={BB245} [004022] ----------- IL_OFFSET void INLRT @ 0x559[E-] N001 ( 1, 1) [000669] ----------- t669 = LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] ----------- t670 = CNS_INT int -1 $c4 /--* t669 int +--* t670 int N003 ( 3, 4) [000671] ----------- t671 = * ADD int $ab9 /--* t671 int N005 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB138} succs={BB172,BB245} [004023] ----------- IL_OFFSET void INLRT @ 0x564[E-] N001 ( 1, 1) [000605] ----------- t605 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] ----------- t606 = CNS_INT int 0 $c0 /--* t605 int +--* t606 int N003 ( 6, 4) [000607] ----------- t607 = * NE int $aba N004 ( 1, 1) [000608] ----------- t608 = LCL_VAR int V21 loc17 u:2 $4c7 /--* t607 int +--* t608 int N005 ( 8, 6) [000609] ----------- t609 = * OR int $abb N006 ( 1, 2) [000610] ----------- t610 = CNS_INT int 0 $c0 /--* t609 int +--* t610 int N007 ( 10, 9) [000611] J------N--- t611 = * NE int $abc /--* t611 int N008 ( 12, 11) [000612] ----------- * JTRUE void $VN.Void ------------ BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} [004024] ----------- IL_OFFSET void INLRT @ 0x571[E-] N001 ( 1, 1) [000613] ----------- t613 = LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] ----------- t614 = CNS_INT int 0 $c0 /--* t613 int +--* t614 int N003 ( 3, 4) [000615] J------N--- t615 = * LT int $abd /--* t615 int N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} [004025] ----------- IL_OFFSET void INLRT @ 0x575[E-] N001 ( 1, 1) [000625] ----------- t625 = LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- t626 = LCL_VAR int V04 loc0 u:2 $28a /--* t625 int +--* t626 int N003 ( 6, 3) [000627] -------N--- t627 = * GE int $abe N004 ( 1, 1) [000629] ----------- t629 = LCL_VAR long V36 loc32 u:3 $901 /--* t629 long N005 ( 4, 3) [000630] ---XG------ t630 = * IND ubyte N006 ( 1, 2) [000631] ----------- t631 = CNS_INT int 0 $c0 /--* t630 ubyte +--* t631 int N007 ( 9, 6) [000632] ---XG--N--- t632 = * EQ int /--* t627 int +--* t632 int N008 ( 16, 10) [003752] J--XG--N--- t3752 = * AND int /--* t3752 int N009 ( 18, 12) [000628] ---XG------ * JTRUE void $VN.Void ------------ BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} [004026] ----------- IL_OFFSET void INLRT @ 0x57C[E-] N001 ( 0, 0) [003753] ----------- NOP void [004027] ----------- IL_OFFSET void INLRT @ 0x584[E-] N001 ( 1, 1) [000618] ----------- t618 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002906] ----------- t2906 = CNS_INT long 48 Fseq[] $20f /--* t618 ref +--* t2906 long N003 ( 3, 4) [002907] -------N--- t2907 = * ADD byref $a4d /--* t2907 byref N004 ( 4, 3) [002006] ---XG------ t2006 = * IND ref /--* t2006 ref N006 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 [004028] ----------- IL_OFFSET void INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002008] ----------- t2008 = LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] ----------- t2009 = CNS_INT ref null $VN.Null /--* t2008 ref +--* t2009 ref N003 ( 3, 4) [002010] J------N--- t2010 = * EQ int /--* t2010 int N004 ( 5, 6) [002011] ----------- * JTRUE void $VN.Void ------------ BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} [004029] ----------- IL_OFFSET void INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [000617] ----------- t617 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002908] ----------- t2908 = CNS_INT long 8 $201 /--* t617 byref +--* t2908 long N003 ( 3, 4) [002909] -------N--- t2909 = * ADD byref $25a /--* t2909 byref N004 ( 4, 3) [002012] ---XG------ t2012 = * IND int /--* t2012 int N006 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 [004030] ----------- IL_OFFSET void INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002015] ----------- t2015 = LCL_VAR ref V106 tmp66 u:1 [004173] ----------- t4173 = CNS_INT long 8 /--* t2015 ref +--* t4173 long [004174] ----------- t4174 = * ADD byref /--* t4174 byref N002 ( 3, 3) [002016] ---X------- t2016 = * IND int N003 ( 1, 2) [002017] ----------- t2017 = CNS_INT int 1 $c1 /--* t2016 int +--* t2017 int N004 ( 8, 6) [002018] N--X---N-U- t2018 = * NE int N005 ( 1, 1) [002023] ----------- t2023 = LCL_VAR int V107 tmp67 u:1 N006 ( 1, 1) [002024] ----------- t2024 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002912] ----------- t2912 = CNS_INT long 24 $20c /--* t2024 byref +--* t2912 long N008 ( 3, 4) [002913] -------N--- t2913 = * ADD byref $25b /--* t2913 byref N009 ( 4, 3) [002062] n---GO----- t2062 = * IND int /--* t2023 int +--* t2062 int N010 ( 9, 5) [002028] N---GO-N-U- t2028 = * GE int /--* t2018 int +--* t2028 int N011 ( 18, 12) [003754] J--XGO-N--- t3754 = * AND int /--* t3754 int N012 ( 20, 14) [002019] ---XGO----- * JTRUE void ------------ BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} [004031] ----------- IL_OFFSET void INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] N001 ( 0, 0) [003755] ----------- NOP void [004032] ----------- IL_OFFSET void INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002917] ----------- t2917 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] ----------- t2918 = CNS_INT long 16 $200 /--* t2917 byref +--* t2918 long N003 ( 3, 4) [002919] -----O----- t2919 = * ADD byref $25c /--* t2919 byref N005 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 [004033] ----------- IL_OFFSET void INL40 @ ??? <- INLRT @ 0x584[E-] N001 ( 1, 1) [002032] ----------- t2032 = LCL_VAR int V107 tmp67 u:1 N002 ( 1, 1) [002037] ----------- t2037 = LCL_VAR byref V108 tmp68 u:1 $25c N003 ( 1, 2) [002921] ----------- t2921 = CNS_INT long 8 $201 /--* t2037 byref +--* t2921 long N004 ( 3, 4) [002922] -------N--- t2922 = * ADD byref $25d /--* t2922 byref N005 ( 4, 3) [002038] n---GO----- t2038 = * IND int /--* t2032 int +--* t2038 int N006 ( 9, 11) [002039] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002036] ----------- t2036 = LCL_VAR byref V108 tmp68 u:1 (last use) $25c /--* t2036 byref N008 ( 3, 2) [002043] n---GO----- t2043 = * IND byref N009 ( 1, 1) [002033] ----------- t2033 = LCL_VAR int V107 tmp67 u:1 /--* t2033 int N010 ( 2, 3) [002040] ---------U- t2040 = * CAST long <- uint N011 ( 1, 2) [002041] ----------- t2041 = CNS_INT long 1 $204 /--* t2040 long +--* t2041 long N012 ( 4, 6) [002042] ----------- t2042 = * LSH long /--* t2043 byref +--* t2042 long N013 ( 8, 9) [002044] ----GO-N--- t2044 = * ADD byref N016 ( 1, 2) [002047] ----------- t2047 = CNS_INT int 0 $c0 N017 ( 1, 1) [002046] ----------- t2046 = LCL_VAR ref V106 tmp66 u:1 [004175] ----------- t4175 = CNS_INT long 8 /--* t2046 ref +--* t4175 long [004176] ----------- t4176 = * ADD byref /--* t4176 byref N018 ( 3, 3) [002926] ---X------- t2926 = * IND int /--* t2047 int +--* t2926 int N019 ( 8, 12) [002927] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002924] ----------- t2924 = LCL_VAR ref V106 tmp66 u:1 (last use) N021 ( 1, 2) [002930] ----------- t2930 = CNS_INT long 12 $20d /--* t2924 ref +--* t2930 long N022 ( 1, 1) [002931] -------N--- t2931 = * ADD byref /--* t2931 byref N024 ( 5, 4) [002936] n---GO----- t2936 = * IND ushort /--* t2044 byref +--* t2936 ushort [004034] -A-XGO----- * STOREIND short [004035] ----------- IL_OFFSET void INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002053] ----------- t2053 = LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] ----------- t2054 = CNS_INT int 1 $c1 /--* t2053 int +--* t2054 int N003 ( 3, 4) [002055] ----------- t2055 = * ADD int N004 ( 1, 1) [002052] ----------- t2052 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002937] ----------- t2937 = CNS_INT long 8 $201 /--* t2052 byref +--* t2937 long N006 ( 3, 4) [002938] -------N--- t2938 = * ADD byref $25a /--* t2938 byref +--* t2055 int [004036] -A--GO----- * STOREIND int ------------ BB179 [584..585), preds={BB176} succs={BB180} [004037] ----------- IL_OFFSET void INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002020] ----------- t2020 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- t2021 = LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- t2939 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2020 byref this in x0 +--* t2021 ref arg2 in x1 +--* t2939 long r2r cell in x11 N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} [004038] ----------- IL_OFFSET void INLRT @ 0x590[E-] N001 ( 1, 2) [002940] ----------- t2940 = CNS_INT int 1 $c1 /--* t2940 int N003 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} [004039] ----------- IL_OFFSET void INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002068] ----------- t2068 = LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] ----------- t2069 = CNS_INT ref null $VN.Null /--* t2068 ref +--* t2069 ref N003 ( 3, 4) [002070] J------N--- t2070 = * EQ int /--* t2070 int N004 ( 5, 6) [002071] ----------- * JTRUE void $VN.Void ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} [004040] ----------- IL_OFFSET void INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [000585] ----------- t585 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002941] ----------- t2941 = CNS_INT long 8 $201 /--* t585 byref +--* t2941 long N003 ( 3, 4) [002942] -------N--- t2942 = * ADD byref $25a /--* t2942 byref N004 ( 4, 3) [002072] ---XG------ t2072 = * IND int /--* t2072 int N006 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 [004041] ----------- IL_OFFSET void INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002075] ----------- t2075 = LCL_VAR ref V110 tmp70 u:1 [004177] ----------- t4177 = CNS_INT long 8 /--* t2075 ref +--* t4177 long [004178] ----------- t4178 = * ADD byref /--* t4178 byref N002 ( 3, 3) [002076] ---X------- t2076 = * IND int N003 ( 1, 2) [002077] ----------- t2077 = CNS_INT int 1 $c1 /--* t2076 int +--* t2077 int N004 ( 8, 6) [002078] N--X---N-U- t2078 = * NE int N005 ( 1, 1) [002083] ----------- t2083 = LCL_VAR int V111 tmp71 u:1 N006 ( 1, 1) [002084] ----------- t2084 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002945] ----------- t2945 = CNS_INT long 24 $20c /--* t2084 byref +--* t2945 long N008 ( 3, 4) [002946] -------N--- t2946 = * ADD byref $25b /--* t2946 byref N009 ( 4, 3) [002122] n---GO----- t2122 = * IND int /--* t2083 int +--* t2122 int N010 ( 9, 5) [002088] N---GO-N-U- t2088 = * GE int /--* t2078 int +--* t2088 int N011 ( 18, 12) [003756] J--XGO-N--- t3756 = * AND int /--* t3756 int N012 ( 20, 14) [002079] ---XGO----- * JTRUE void ------------ BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} [004042] ----------- IL_OFFSET void INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] N001 ( 0, 0) [003757] ----------- NOP void [004043] ----------- IL_OFFSET void INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002950] ----------- t2950 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] ----------- t2951 = CNS_INT long 16 $200 /--* t2950 byref +--* t2951 long N003 ( 3, 4) [002952] -----O----- t2952 = * ADD byref $25c /--* t2952 byref N005 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 [004044] ----------- IL_OFFSET void INL43 @ ??? <- INLRT @ 0x598[E-] N001 ( 1, 1) [002092] ----------- t2092 = LCL_VAR int V111 tmp71 u:1 N002 ( 1, 1) [002097] ----------- t2097 = LCL_VAR byref V112 tmp72 u:1 $25c N003 ( 1, 2) [002954] ----------- t2954 = CNS_INT long 8 $201 /--* t2097 byref +--* t2954 long N004 ( 3, 4) [002955] -------N--- t2955 = * ADD byref $25d /--* t2955 byref N005 ( 4, 3) [002098] n---GO----- t2098 = * IND int /--* t2092 int +--* t2098 int N006 ( 9, 11) [002099] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002096] ----------- t2096 = LCL_VAR byref V112 tmp72 u:1 (last use) $25c /--* t2096 byref N008 ( 3, 2) [002103] n---GO----- t2103 = * IND byref N009 ( 1, 1) [002093] ----------- t2093 = LCL_VAR int V111 tmp71 u:1 /--* t2093 int N010 ( 2, 3) [002100] ---------U- t2100 = * CAST long <- uint N011 ( 1, 2) [002101] ----------- t2101 = CNS_INT long 1 $204 /--* t2100 long +--* t2101 long N012 ( 4, 6) [002102] ----------- t2102 = * LSH long /--* t2103 byref +--* t2102 long N013 ( 8, 9) [002104] ----GO-N--- t2104 = * ADD byref N016 ( 1, 2) [002107] ----------- t2107 = CNS_INT int 0 $c0 N017 ( 1, 1) [002106] ----------- t2106 = LCL_VAR ref V110 tmp70 u:1 [004179] ----------- t4179 = CNS_INT long 8 /--* t2106 ref +--* t4179 long [004180] ----------- t4180 = * ADD byref /--* t4180 byref N018 ( 3, 3) [002959] ---X------- t2959 = * IND int /--* t2107 int +--* t2959 int N019 ( 8, 12) [002960] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002957] ----------- t2957 = LCL_VAR ref V110 tmp70 u:1 (last use) N021 ( 1, 2) [002963] ----------- t2963 = CNS_INT long 12 $20d /--* t2957 ref +--* t2963 long N022 ( 1, 1) [002964] -------N--- t2964 = * ADD byref /--* t2964 byref N024 ( 5, 4) [002969] n---GO----- t2969 = * IND ushort /--* t2104 byref +--* t2969 ushort [004045] -A-XGO----- * STOREIND short [004046] ----------- IL_OFFSET void INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002113] ----------- t2113 = LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] ----------- t2114 = CNS_INT int 1 $c1 /--* t2113 int +--* t2114 int N003 ( 3, 4) [002115] ----------- t2115 = * ADD int N004 ( 1, 1) [002112] ----------- t2112 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [002970] ----------- t2970 = CNS_INT long 8 $201 /--* t2112 byref +--* t2970 long N006 ( 3, 4) [002971] -------N--- t2971 = * ADD byref $25a /--* t2971 byref +--* t2115 int [004047] -A--GO----- * STOREIND int ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} [004048] ----------- IL_OFFSET void INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002080] ----------- t2080 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- t2081 = LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- t2972 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2080 byref this in x0 +--* t2081 ref arg2 in x1 +--* t2972 long r2r cell in x11 N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB137} succs={BB187,BB245} [004049] ----------- IL_OFFSET void INLRT @ 0x5A9[E-] N001 ( 1, 1) [000635] ----------- t635 = LCL_VAR ref V03 arg3 u:1 $180 N002 ( 1, 2) [002973] ----------- t2973 = CNS_INT long 128 Fseq[] $210 /--* t635 ref +--* t2973 long N003 ( 3, 4) [002974] -------N--- t2974 = * ADD byref $a53 /--* t2974 byref N004 ( 4, 3) [002126] ---XG------ t2126 = * IND ref /--* t2126 ref N006 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 [004050] ----------- IL_OFFSET void INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002128] ----------- t2128 = LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] ----------- t2129 = CNS_INT ref null $VN.Null /--* t2128 ref +--* t2129 ref N003 ( 3, 4) [002130] J------N--- t2130 = * EQ int /--* t2130 int N004 ( 5, 6) [002131] ----------- * JTRUE void $VN.Void ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} [004051] ----------- IL_OFFSET void INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [000634] ----------- t634 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002975] ----------- t2975 = CNS_INT long 8 $201 /--* t634 byref +--* t2975 long N003 ( 3, 4) [002976] -------N--- t2976 = * ADD byref $25a /--* t2976 byref N004 ( 4, 3) [002132] ---XG------ t2132 = * IND int /--* t2132 int N006 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 [004052] ----------- IL_OFFSET void INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002135] ----------- t2135 = LCL_VAR ref V114 tmp74 u:1 [004181] ----------- t4181 = CNS_INT long 8 /--* t2135 ref +--* t4181 long [004182] ----------- t4182 = * ADD byref /--* t4182 byref N002 ( 3, 3) [002136] ---X------- t2136 = * IND int N003 ( 1, 2) [002137] ----------- t2137 = CNS_INT int 1 $c1 /--* t2136 int +--* t2137 int N004 ( 8, 6) [002138] N--X---N-U- t2138 = * NE int N005 ( 1, 1) [002143] ----------- t2143 = LCL_VAR int V115 tmp75 u:1 N006 ( 1, 1) [002144] ----------- t2144 = LCL_VAR byref V00 arg0 u:1 $100 N007 ( 1, 2) [002979] ----------- t2979 = CNS_INT long 24 $20c /--* t2144 byref +--* t2979 long N008 ( 3, 4) [002980] -------N--- t2980 = * ADD byref $25b /--* t2980 byref N009 ( 4, 3) [002182] n---GO----- t2182 = * IND int /--* t2143 int +--* t2182 int N010 ( 9, 5) [002148] N---GO-N-U- t2148 = * GE int /--* t2138 int +--* t2148 int N011 ( 18, 12) [003758] J--XGO-N--- t3758 = * AND int /--* t3758 int N012 ( 20, 14) [002139] ---XGO----- * JTRUE void ------------ BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} [004053] ----------- IL_OFFSET void INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] N001 ( 0, 0) [003759] ----------- NOP void [004054] ----------- IL_OFFSET void INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002984] ----------- t2984 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] ----------- t2985 = CNS_INT long 16 $200 /--* t2984 byref +--* t2985 long N003 ( 3, 4) [002986] -----O----- t2986 = * ADD byref $25c /--* t2986 byref N005 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 [004055] ----------- IL_OFFSET void INL46 @ ??? <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002152] ----------- t2152 = LCL_VAR int V115 tmp75 u:1 N002 ( 1, 1) [002157] ----------- t2157 = LCL_VAR byref V116 tmp76 u:1 $25c N003 ( 1, 2) [002988] ----------- t2988 = CNS_INT long 8 $201 /--* t2157 byref +--* t2988 long N004 ( 3, 4) [002989] -------N--- t2989 = * ADD byref $25d /--* t2989 byref N005 ( 4, 3) [002158] n---GO----- t2158 = * IND int /--* t2152 int +--* t2158 int N006 ( 9, 11) [002159] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002156] ----------- t2156 = LCL_VAR byref V116 tmp76 u:1 (last use) $25c /--* t2156 byref N008 ( 3, 2) [002163] n---GO----- t2163 = * IND byref N009 ( 1, 1) [002153] ----------- t2153 = LCL_VAR int V115 tmp75 u:1 /--* t2153 int N010 ( 2, 3) [002160] ---------U- t2160 = * CAST long <- uint N011 ( 1, 2) [002161] ----------- t2161 = CNS_INT long 1 $204 /--* t2160 long +--* t2161 long N012 ( 4, 6) [002162] ----------- t2162 = * LSH long /--* t2163 byref +--* t2162 long N013 ( 8, 9) [002164] ----GO-N--- t2164 = * ADD byref N016 ( 1, 2) [002167] ----------- t2167 = CNS_INT int 0 $c0 N017 ( 1, 1) [002166] ----------- t2166 = LCL_VAR ref V114 tmp74 u:1 [004183] ----------- t4183 = CNS_INT long 8 /--* t2166 ref +--* t4183 long [004184] ----------- t4184 = * ADD byref /--* t4184 byref N018 ( 3, 3) [002993] ---X------- t2993 = * IND int /--* t2167 int +--* t2993 int N019 ( 8, 12) [002994] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002991] ----------- t2991 = LCL_VAR ref V114 tmp74 u:1 (last use) N021 ( 1, 2) [002997] ----------- t2997 = CNS_INT long 12 $20d /--* t2991 ref +--* t2997 long N022 ( 1, 1) [002998] -------N--- t2998 = * ADD byref /--* t2998 byref N024 ( 5, 4) [003003] n---GO----- t3003 = * IND ushort /--* t2164 byref +--* t3003 ushort [004056] -A-XGO----- * STOREIND short [004057] ----------- IL_OFFSET void INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002173] ----------- t2173 = LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] ----------- t2174 = CNS_INT int 1 $c1 /--* t2173 int +--* t2174 int N003 ( 3, 4) [002175] ----------- t2175 = * ADD int N004 ( 1, 1) [002172] ----------- t2172 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003004] ----------- t3004 = CNS_INT long 8 $201 /--* t2172 byref +--* t3004 long N006 ( 3, 4) [003005] -------N--- t3005 = * ADD byref $25a /--* t3005 byref +--* t2175 int [004058] -A--GO----- * STOREIND int ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} [004059] ----------- IL_OFFSET void INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002140] ----------- t2140 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- t2141 = LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- t3006 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2140 byref this in x0 +--* t2141 ref arg2 in x1 +--* t3006 long r2r cell in x11 N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} [004060] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] N001 ( 1, 1) [000805] ----------- t805 = LCL_VAR int V16 loc12 u:13 $b04 /--* t805 int N003 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 [004061] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] N001 ( 1, 1) [000806] ----------- t806 = LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] ----------- t807 = CNS_INT int 1 $c1 /--* t806 int +--* t807 int N003 ( 3, 4) [000808] ----------- t808 = * ADD int $bad /--* t808 int N005 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 N001 ( 1, 1) [003629] ----------- t3629 = LCL_VAR int V172 cse1 /--* t3629 int N003 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 [004062] ----------- IL_OFFSET void INL48 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000803] ----------- t803 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003007] ----------- t3007 = CNS_INT long 8 $201 /--* t803 byref +--* t3007 long N003 ( 3, 4) [003008] -------N--- t3008 = * ADD byref $25a /--* t3008 byref N004 ( 4, 3) [002186] ---XG------ t2186 = * IND int /--* t2186 int N006 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 [004063] ----------- IL_OFFSET void INL48 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002189] ----------- t2189 = LCL_VAR int V118 tmp78 u:1 N002 ( 1, 1) [002190] ----------- t2190 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003011] ----------- t3011 = CNS_INT long 24 $20c /--* t2190 byref +--* t3011 long N004 ( 3, 4) [003012] -------N--- t3012 = * ADD byref $25b /--* t3012 byref N005 ( 4, 3) [002228] n---GO----- t2228 = * IND int /--* t2189 int +--* t2228 int N006 ( 6, 5) [002194] N---GO-N-U- t2194 = * GE int /--* t2194 int N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} [004064] ----------- IL_OFFSET void INL48 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003016] ----------- t3016 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] ----------- t3017 = CNS_INT long 16 $200 /--* t3016 byref +--* t3017 long N003 ( 3, 4) [003018] -----O----- t3018 = * ADD byref $25c /--* t3018 byref N005 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 N001 ( 1, 1) [002201] ----------- t2201 = LCL_VAR int V118 tmp78 u:1 N002 ( 1, 1) [002206] ----------- t2206 = LCL_VAR byref V120 tmp80 u:1 $25c N003 ( 1, 2) [003020] ----------- t3020 = CNS_INT long 8 $201 /--* t2206 byref +--* t3020 long N004 ( 3, 4) [003021] -------N--- t3021 = * ADD byref $25d /--* t3021 byref N005 ( 4, 3) [002207] n---GO----- t2207 = * IND int /--* t2201 int +--* t2207 int N006 ( 9, 11) [002208] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002205] ----------- t2205 = LCL_VAR byref V120 tmp80 u:1 (last use) $25c /--* t2205 byref N008 ( 3, 2) [002212] n---GO----- t2212 = * IND byref N009 ( 1, 1) [002202] ----------- t2202 = LCL_VAR int V118 tmp78 u:1 /--* t2202 int N010 ( 2, 3) [002209] ---------U- t2209 = * CAST long <- uint N011 ( 1, 2) [002210] ----------- t2210 = CNS_INT long 1 $204 /--* t2209 long +--* t2210 long N012 ( 4, 6) [002211] ----------- t2211 = * LSH long /--* t2212 byref +--* t2211 long N013 ( 8, 9) [002213] ----GO-N--- t2213 = * ADD byref N016 ( 1, 1) [002215] ----------- t2215 = LCL_VAR int V119 tmp79 u:1 (last use) /--* t2213 byref +--* t2215 int [004065] -A-XGO----- * STOREIND short [004066] ----------- IL_OFFSET void INL48 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002219] ----------- t2219 = LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] ----------- t2220 = CNS_INT int 1 $c1 /--* t2219 int +--* t2220 int N003 ( 3, 4) [002221] ----------- t2221 = * ADD int N004 ( 1, 1) [002218] ----------- t2218 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003023] ----------- t3023 = CNS_INT long 8 $201 /--* t2218 byref +--* t3023 long N006 ( 3, 4) [003024] -------N--- t3024 = * ADD byref $25a /--* t3024 byref +--* t2221 int [004067] -A--GO----- * STOREIND int ------------ BB193 [000..000), preds={BB191} succs={BB194} [004068] ----------- IL_OFFSET void INL48 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002196] ----------- t2196 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- t2197 = LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- t3025 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2196 byref this in x0 +--* t2197 int arg2 in x1 +--* t3025 long r2r cell in x11 N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB137(2),BB192,BB193} succs={BB195,BB197} [004069] ----------- IL_OFFSET void INLRT @ 0x5CE[E-] N001 ( 1, 1) [000751] ----------- t751 = LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- t3699 = LCL_VAR int V179 cse8 u:1 $342 /--* t751 int +--* t3699 int N003 ( 3, 3) [000756] J------N--- t756 = * GE int $ba4 /--* t756 int N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} [004070] ----------- IL_OFFSET void INLRT @ 0x5D9[E-] N001 ( 1, 1) [000781] ----------- t781 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000782] ----------- t782 = LCL_VAR int V16 loc12 u:13 $b04 /--* t782 int N003 ( 2, 3) [000783] ----------- t783 = * CAST long <- int $aca N004 ( 1, 2) [000785] ----------- t785 = CNS_INT long 1 $204 /--* t783 long +--* t785 long N005 ( 4, 6) [000786] ----------- t786 = * LSH long $acb /--* t781 long +--* t786 long N006 ( 6, 8) [000787] -------N--- t787 = * ADD long $acc /--* t787 long N007 ( 9, 10) [000788] ---XG------ t788 = * IND ushort /--* t788 ushort N009 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 N010 ( 1, 1) [003632] ----------- t3632 = LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] ----------- t789 = CNS_INT int 0 $c0 /--* t3632 int +--* t789 int N013 ( 12, 14) [000790] J--XG--N--- t790 = * EQ int /--* t790 int N014 ( 14, 16) [000791] ---XG------ * JTRUE void $bec ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} [004071] ----------- IL_OFFSET void INLRT @ 0x5E4[E-] N001 ( 1, 1) [003634] ----------- t3634 = LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- t800 = LCL_VAR int V18 loc14 u:1 /--* t3634 int +--* t800 int N003 ( 3, 3) [000801] N---G--N-U- t801 = * NE int /--* t801 int N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} [004072] ----------- IL_OFFSET void INLRT @ 0x5F1[E-] N001 ( 1, 1) [000758] ----------- t758 = LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- t3700 = LCL_VAR int V179 cse8 u:1 $342 /--* t758 int +--* t3700 int N003 ( 3, 3) [000763] J------N--- t763 = * GE int $ba4 /--* t763 int N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} [004073] ----------- IL_OFFSET void INLRT @ 0x5FF[E-] N001 ( 1, 1) [000765] ----------- t765 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000766] ----------- t766 = LCL_VAR int V16 loc12 u:13 $b04 /--* t766 int N003 ( 2, 3) [000767] ----------- t767 = * CAST long <- int $aca N004 ( 1, 2) [000769] ----------- t769 = CNS_INT long 1 $204 /--* t767 long +--* t769 long N005 ( 4, 6) [000770] ----------- t770 = * LSH long $acb /--* t765 long +--* t770 long N006 ( 6, 8) [000771] -------N--- t771 = * ADD long $acc /--* t771 long N007 ( 9, 10) [000772] ---XG------ t772 = * IND ushort /--* t772 ushort N009 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 N010 ( 1, 1) [003637] ----------- t3637 = LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] ----------- t773 = CNS_INT int 0 $c0 /--* t3637 int +--* t773 int N013 ( 12, 14) [000774] J--XG--N--- t774 = * EQ int /--* t774 int N014 ( 14, 16) [000775] ---XG------ * JTRUE void $bec ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} [004074] ----------- IL_OFFSET void INLRT @ 0x60D[E-] N001 ( 1, 1) [000776] ----------- t776 = LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] ----------- t777 = CNS_INT int 1 $c1 /--* t776 int +--* t777 int N003 ( 3, 4) [000778] ----------- t778 = * ADD int $bad /--* t778 int N005 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} [004075] ----------- IL_OFFSET void INLRT @ 0x618[E-] N001 ( 1, 1) [000283] ----------- t283 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- t3701 = LCL_VAR int V179 cse8 u:1 $342 /--* t283 int +--* t3701 int N003 ( 6, 3) [000288] -------N--- t288 = * GE int $94d N004 ( 1, 1) [000290] ----------- t290 = LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 1, 1) [000291] ----------- t291 = LCL_VAR int V16 loc12 u:5 $898 /--* t291 int N006 ( 2, 3) [000292] ----------- t292 = * CAST long <- int $3e5 N007 ( 1, 2) [000294] ----------- t294 = CNS_INT long 1 $204 /--* t292 long +--* t294 long N008 ( 4, 6) [000295] ----------- t295 = * LSH long $3e6 /--* t290 long +--* t295 long N009 ( 6, 8) [000296] -------N--- t296 = * ADD long $3e7 /--* t296 long N010 ( 9, 10) [000297] ---XG------ t297 = * IND ushort /--* t297 ushort N012 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 N013 ( 1, 1) [003665] ----------- t3665 = LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] ----------- t298 = CNS_INT int 0 $c0 /--* t3665 int +--* t298 int N016 ( 15, 14) [000299] ---XG--N--- t299 = * EQ int /--* t288 int +--* t299 int N017 ( 22, 18) [003760] J--XG--N--- t3760 = * AND int /--* t3760 int N018 ( 24, 20) [000289] ---XG------ * JTRUE void $VN.Void ------------ BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} [004076] ----------- IL_OFFSET void INLRT @ 0x626[E-] N001 ( 0, 0) [003761] ----------- NOP void [004077] ----------- IL_OFFSET void INLRT @ 0x634[E-] N001 ( 1, 1) [000303] ----------- t303 = LCL_VAR int V16 loc12 u:5 $898 /--* t303 int N003 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 [004078] ----------- IL_OFFSET void INLRT @ 0x634[E-] N001 ( 1, 1) [000304] ----------- t304 = LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] ----------- t305 = CNS_INT int 1 $c1 /--* t304 int +--* t305 int N003 ( 3, 4) [000306] ----------- t306 = * ADD int $952 /--* t306 int N005 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 N001 ( 1, 1) [003667] ----------- t3667 = LCL_VAR int V176 cse5 /--* t3667 int N003 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 [004079] ----------- IL_OFFSET void INL53 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000301] ----------- t301 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003026] ----------- t3026 = CNS_INT long 8 $201 /--* t301 byref +--* t3026 long N003 ( 3, 4) [003027] -------N--- t3027 = * ADD byref $25a /--* t3027 byref N004 ( 4, 3) [002244] ---XG------ t2244 = * IND int /--* t2244 int N006 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 [004080] ----------- IL_OFFSET void INL53 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002247] ----------- t2247 = LCL_VAR int V122 tmp82 u:1 N002 ( 1, 1) [002248] ----------- t2248 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003030] ----------- t3030 = CNS_INT long 24 $20c /--* t2248 byref +--* t3030 long N004 ( 3, 4) [003031] -------N--- t3031 = * ADD byref $25b /--* t3031 byref N005 ( 4, 3) [002286] n---GO----- t2286 = * IND int /--* t2247 int +--* t2286 int N006 ( 6, 5) [002252] N---GO-N-U- t2252 = * GE int /--* t2252 int N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 ------------ BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} [004081] ----------- IL_OFFSET void INL53 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003035] ----------- t3035 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] ----------- t3036 = CNS_INT long 16 $200 /--* t3035 byref +--* t3036 long N003 ( 3, 4) [003037] -----O----- t3037 = * ADD byref $25c /--* t3037 byref N005 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 N001 ( 1, 1) [002259] ----------- t2259 = LCL_VAR int V122 tmp82 u:1 N002 ( 1, 1) [002264] ----------- t2264 = LCL_VAR byref V124 tmp84 u:1 $25c N003 ( 1, 2) [003039] ----------- t3039 = CNS_INT long 8 $201 /--* t2264 byref +--* t3039 long N004 ( 3, 4) [003040] -------N--- t3040 = * ADD byref $25d /--* t3040 byref N005 ( 4, 3) [002265] n---GO----- t2265 = * IND int /--* t2259 int +--* t2265 int N006 ( 9, 11) [002266] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002263] ----------- t2263 = LCL_VAR byref V124 tmp84 u:1 (last use) $25c /--* t2263 byref N008 ( 3, 2) [002270] n---GO----- t2270 = * IND byref N009 ( 1, 1) [002260] ----------- t2260 = LCL_VAR int V122 tmp82 u:1 /--* t2260 int N010 ( 2, 3) [002267] ---------U- t2267 = * CAST long <- uint N011 ( 1, 2) [002268] ----------- t2268 = CNS_INT long 1 $204 /--* t2267 long +--* t2268 long N012 ( 4, 6) [002269] ----------- t2269 = * LSH long /--* t2270 byref +--* t2269 long N013 ( 8, 9) [002271] ----GO-N--- t2271 = * ADD byref N016 ( 1, 1) [002273] ----------- t2273 = LCL_VAR int V123 tmp83 u:1 (last use) /--* t2271 byref +--* t2273 int [004082] -A-XGO----- * STOREIND short [004083] ----------- IL_OFFSET void INL53 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002277] ----------- t2277 = LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] ----------- t2278 = CNS_INT int 1 $c1 /--* t2277 int +--* t2278 int N003 ( 3, 4) [002279] ----------- t2279 = * ADD int N004 ( 1, 1) [002276] ----------- t2276 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003042] ----------- t3042 = CNS_INT long 8 $201 /--* t2276 byref +--* t3042 long N006 ( 3, 4) [003043] -------N--- t3043 = * ADD byref $25a /--* t3043 byref +--* t2279 int [004084] -A--GO----- * STOREIND int ------------ BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} [004085] ----------- IL_OFFSET void INL53 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002254] ----------- t2254 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- t2255 = LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- t3044 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2254 byref this in x0 +--* t2255 int arg2 in x1 +--* t3044 long r2r cell in x11 N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} [004086] ----------- IL_OFFSET void INLRT @ 0x64D[E-] N001 ( 1, 2) [003045] ----------- t3045 = CNS_INT int 0 $c0 /--* t3045 int N003 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 [004087] ----------- IL_OFFSET void INLRT @ 0x650[E-] N001 ( 1, 2) [000326] ----------- t326 = CNS_INT int 0 $c0 /--* t326 int N003 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 [004088] ----------- IL_OFFSET void INLRT @ 0x653[E-] N001 ( 1, 1) [000329] ----------- t329 = LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] ----------- t330 = CNS_INT int 0 $c0 /--* t329 int +--* t330 int N003 ( 3, 4) [000331] J------N--- t331 = * EQ int $97d /--* t331 int N004 ( 5, 6) [000332] ----------- * JTRUE void $VN.Void ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} [004089] ----------- IL_OFFSET void INLRT @ 0x65A[E-] N001 ( 1, 1) [000419] ----------- t419 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- t3702 = LCL_VAR int V179 cse8 u:1 $342 /--* t419 int +--* t3702 int N003 ( 3, 3) [000424] J------N--- t424 = * GE int $94d /--* t424 int N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} [004090] ----------- IL_OFFSET void INLRT @ 0x665[E-] N001 ( 1, 1) [000565] ----------- t565 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000566] ----------- t566 = LCL_VAR int V16 loc12 u:5 $898 /--* t566 int N003 ( 2, 3) [000567] ----------- t567 = * CAST long <- int $3e5 N004 ( 1, 2) [000569] ----------- t569 = CNS_INT long 1 $204 /--* t567 long +--* t569 long N005 ( 4, 6) [000570] ----------- t570 = * LSH long $3e6 /--* t565 long +--* t570 long N006 ( 6, 8) [000571] -------N--- t571 = * ADD long $3e7 /--* t571 long N007 ( 9, 10) [000572] ---XG------ t572 = * IND ushort /--* t572 ushort N009 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 N010 ( 1, 1) [003670] ----------- t3670 = LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] ----------- t573 = CNS_INT int 48 $d8 /--* t3670 int +--* t573 int N013 ( 12, 14) [000574] N--XG--N-U- t574 = * EQ int /--* t574 int N014 ( 14, 16) [000575] ---XG------ * JTRUE void $87a ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} [004091] ----------- IL_OFFSET void INLRT @ 0x67A[E-] N001 ( 1, 1) [000426] ----------- t426 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] ----------- t427 = CNS_INT int 1 $c1 /--* t426 int +--* t427 int N003 ( 3, 4) [000428] ----------- t428 = * ADD int $952 N004 ( 1, 1) [003703] ----------- t3703 = LCL_VAR int V179 cse8 u:1 $342 /--* t428 int +--* t3703 int N005 ( 5, 6) [000433] J------N--- t433 = * GE int $9e2 /--* t433 int N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} [004092] ----------- IL_OFFSET void INLRT @ 0x687[E-] N001 ( 1, 1) [000538] ----------- t538 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000539] ----------- t539 = LCL_VAR int V16 loc12 u:5 $898 /--* t539 int N003 ( 2, 3) [000540] ----------- t540 = * CAST long <- int $3e5 N004 ( 1, 2) [000542] ----------- t542 = CNS_INT long 1 $204 /--* t540 long +--* t542 long N005 ( 4, 6) [000543] ----------- t543 = * LSH long $3e6 /--* t538 long +--* t543 long N006 ( 6, 8) [000544] -------N--- t544 = * ADD long $3e7 /--* t544 long N007 ( 9, 10) [000545] ---XG------ t545 = * IND ushort /--* t545 ushort N009 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 N010 ( 1, 1) [003674] ----------- t3674 = LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] ----------- t546 = CNS_INT int 43 $d9 /--* t3674 int +--* t546 int N013 ( 15, 14) [000547] N--XG--N-U- t547 = * NE int N014 ( 1, 1) [000549] ----------- t549 = LCL_VAR long V34 loc30 u:1 $3c4 N015 ( 1, 1) [000550] ----------- t550 = LCL_VAR int V16 loc12 u:5 $898 N016 ( 1, 2) [000551] ----------- t551 = CNS_INT int 1 $c1 /--* t550 int +--* t551 int N017 ( 3, 4) [000552] ----------- t552 = * ADD int $952 /--* t552 int N018 ( 4, 6) [000553] ----------- t553 = * CAST long <- int $3f4 N019 ( 1, 2) [000555] ----------- t555 = CNS_INT long 1 $204 /--* t553 long +--* t555 long N020 ( 6, 9) [000556] ----------- t556 = * LSH long $3f5 /--* t549 long +--* t556 long N021 ( 8, 11) [000557] -------N--- t557 = * ADD long $3f6 /--* t557 long N022 ( 11, 13) [000558] ---XG------ t558 = * IND ushort N023 ( 1, 2) [000559] ----------- t559 = CNS_INT int 48 $d8 /--* t558 ushort +--* t559 int N024 ( 16, 16) [000560] N--XG--N-U- t560 = * NE int /--* t547 int +--* t560 int N025 ( 32, 31) [003762] J--XG--N--- t3762 = * AND int /--* t3762 int N026 ( 34, 33) [000548] ---XG------ * JTRUE void $87a ------------ BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} [004093] ----------- IL_OFFSET void INLRT @ 0x694[E-] N001 ( 0, 0) [003763] ----------- NOP void [004094] ----------- IL_OFFSET void INLRT @ 0x6A3[E-] N001 ( 1, 2) [003046] ----------- t3046 = CNS_INT int 1 $c1 /--* t3046 int N003 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} [004095] ----------- IL_OFFSET void INLRT @ 0x6B5[E-] N001 ( 1, 1) [003676] ----------- t3676 = LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] ----------- t455 = CNS_INT int 45 $da /--* t3676 int +--* t455 int N003 ( 3, 4) [000456] N---G--N-U- t456 = * NE int /--* t456 int N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} [004096] ----------- IL_OFFSET void INLRT @ 0x6C2[E-] N001 ( 1, 1) [000458] ----------- t458 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000459] ----------- t459 = LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] ----------- t460 = CNS_INT int 1 $c1 /--* t459 int +--* t460 int N004 ( 3, 4) [000461] ----------- t461 = * ADD int $952 /--* t461 int N005 ( 4, 6) [000462] ----------- t462 = * CAST long <- int $3f4 N006 ( 1, 2) [000464] ----------- t464 = CNS_INT long 1 $204 /--* t462 long +--* t464 long N007 ( 6, 9) [000465] ----------- t465 = * LSH long $3f5 /--* t458 long +--* t465 long N008 ( 8, 11) [000466] -------N--- t466 = * ADD long $3f6 /--* t466 long N009 ( 11, 13) [000467] ---XG------ t467 = * IND ushort N010 ( 1, 2) [000468] ----------- t468 = CNS_INT int 48 $d8 /--* t467 ushort +--* t468 int N011 ( 13, 16) [000469] J--XG--N--- t469 = * EQ int /--* t469 int N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 ------------ BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} [004097] ----------- IL_OFFSET void INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [000444] ----------- t444 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003047] ----------- t3047 = CNS_INT long 8 $201 /--* t444 byref +--* t3047 long N003 ( 3, 4) [003048] -------N--- t3048 = * ADD byref $25a /--* t3048 byref N004 ( 4, 3) [002302] ---XG------ t2302 = * IND int /--* t2302 int N006 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 [004098] ----------- IL_OFFSET void INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002305] ----------- t2305 = LCL_VAR int V126 tmp86 u:1 N002 ( 1, 1) [002306] ----------- t2306 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003051] ----------- t3051 = CNS_INT long 24 $20c /--* t2306 byref +--* t3051 long N004 ( 3, 4) [003052] -------N--- t3052 = * ADD byref $25b /--* t3052 byref N005 ( 4, 3) [002341] n---GO----- t2341 = * IND int /--* t2305 int +--* t2341 int N006 ( 6, 5) [002310] N---GO-N-U- t2310 = * GE int /--* t2310 int N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} [004099] ----------- IL_OFFSET void INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [003056] ----------- t3056 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] ----------- t3057 = CNS_INT long 16 $200 /--* t3056 byref +--* t3057 long N003 ( 3, 4) [003058] -----O----- t3058 = * ADD byref $25c /--* t3058 byref N005 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 [004100] ----------- IL_OFFSET void INL58 @ ??? <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002316] ----------- t2316 = LCL_VAR int V126 tmp86 u:1 N002 ( 1, 1) [002321] ----------- t2321 = LCL_VAR byref V127 tmp87 u:1 $25c N003 ( 1, 2) [003060] ----------- t3060 = CNS_INT long 8 $201 /--* t2321 byref +--* t3060 long N004 ( 3, 4) [003061] -------N--- t3061 = * ADD byref $25d /--* t3061 byref N005 ( 4, 3) [002322] n---GO----- t2322 = * IND int /--* t2316 int +--* t2322 int N006 ( 9, 11) [002323] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002320] ----------- t2320 = LCL_VAR byref V127 tmp87 u:1 (last use) $25c /--* t2320 byref N008 ( 3, 2) [002327] n---GO----- t2327 = * IND byref N009 ( 1, 1) [002317] ----------- t2317 = LCL_VAR int V126 tmp86 u:1 /--* t2317 int N010 ( 2, 3) [002324] ---------U- t2324 = * CAST long <- uint N011 ( 1, 2) [002325] ----------- t2325 = CNS_INT long 1 $204 /--* t2324 long +--* t2325 long N012 ( 4, 6) [002326] ----------- t2326 = * LSH long /--* t2327 byref +--* t2326 long N013 ( 8, 9) [002328] ----GO-N--- t2328 = * ADD byref N016 ( 1, 1) [002330] ----------- t2330 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2328 byref +--* t2330 int [004101] -A-XGO----- * STOREIND short [004102] ----------- IL_OFFSET void INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002334] ----------- t2334 = LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] ----------- t2335 = CNS_INT int 1 $c1 /--* t2334 int +--* t2335 int N003 ( 3, 4) [002336] ----------- t2336 = * ADD int N004 ( 1, 1) [002333] ----------- t2333 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003063] ----------- t3063 = CNS_INT long 8 $201 /--* t2333 byref +--* t3063 long N006 ( 3, 4) [003064] -------N--- t3064 = * ADD byref $25a /--* t3064 byref +--* t2336 int [004103] -A--GO----- * STOREIND int ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} [004104] ----------- IL_OFFSET void INLRT @ 0x6DE[E-] N001 ( 1, 1) [000533] ----------- t533 = LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] ----------- t534 = CNS_INT int 1 $c1 /--* t533 int +--* t534 int N003 ( 3, 4) [000535] ----------- t535 = * ADD int $c59 /--* t535 int N005 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} [004105] ----------- IL_OFFSET void INLRT @ 0x6E4[E-] N001 ( 1, 1) [000471] ----------- t471 = LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] ----------- t472 = CNS_INT int 1 $c1 /--* t471 int +--* t472 int N003 ( 3, 4) [000473] ----------- t473 = * ADD int $c5c /--* t473 int N005 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 N001 ( 1, 1) [000477] ----------- t477 = LCL_VAR int V54 tmp14 u:1 $c5c /--* t477 int N003 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 N001 ( 1, 1) [000476] ----------- t476 = LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- t3704 = LCL_VAR int V179 cse8 u:1 $342 /--* t476 int +--* t3704 int N003 ( 3, 3) [000484] J------N--- t484 = * GE int $c5d /--* t484 int N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} [004106] ----------- IL_OFFSET void INLRT @ 0x6F4[E-] N001 ( 1, 1) [000522] ----------- t522 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000523] ----------- t523 = LCL_VAR int V16 loc12 u:10 $c5c /--* t523 int N003 ( 2, 3) [000524] ----------- t524 = * CAST long <- int $ad8 N004 ( 1, 2) [000526] ----------- t526 = CNS_INT long 1 $204 /--* t524 long +--* t526 long N005 ( 4, 6) [000527] ----------- t527 = * LSH long $ad9 /--* t522 long +--* t527 long N006 ( 6, 8) [000528] -------N--- t528 = * ADD long $ada /--* t528 long N007 ( 9, 10) [000529] ---XG------ t529 = * IND ushort N008 ( 1, 2) [000530] ----------- t530 = CNS_INT int 48 $d8 /--* t529 ushort +--* t530 int N009 ( 11, 13) [000531] J--XG--N--- t531 = * EQ int /--* t531 int N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} [004107] ----------- IL_OFFSET void INLRT @ 0x701[E-] N001 ( 1, 1) [000486] ----------- t486 = LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] ----------- t487 = CNS_INT int 10 $e4 /--* t486 int +--* t487 int N003 ( 3, 4) [000488] J------N--- t488 = * LE int $c62 /--* t488 int N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void ------------ BB222 [707..70B), preds={BB221} succs={BB223} [004108] ----------- IL_OFFSET void INLRT @ 0x707[E-] N001 ( 1, 2) [000519] ----------- t519 = CNS_INT int 10 $e4 /--* t519 int N003 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} [004109] ----------- IL_OFFSET void INLRT @ 0x70B[E-] N001 ( 1, 1) [000490] ----------- t490 = LCL_VAR long V17 loc13 u:1 /--* t490 long N002 ( 4, 3) [000491] ---XG------ t491 = * IND ubyte N003 ( 1, 2) [000492] ----------- t492 = CNS_INT int 0 $c0 /--* t491 ubyte +--* t492 int N004 ( 6, 6) [000493] J--XG--N--- t493 = * EQ int /--* t493 int N005 ( 8, 8) [000494] ---XG------ * JTRUE void ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} [004110] ----------- IL_OFFSET void INLRT @ 0x710[E-] N001 ( 1, 1) [000512] ----------- t512 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [003066] ----------- t3066 = CNS_INT long 4 $207 /--* t512 byref +--* t3066 long N003 ( 3, 4) [003067] -------N--- t3067 = * ADD byref $24a /--* t3067 byref N004 ( 4, 3) [000513] n---GO----- t513 = * IND int N005 ( 1, 1) [000514] ----------- t514 = LCL_VAR int V05 loc1 u:3 $28d /--* t513 int +--* t514 int N006 ( 6, 5) [000515] ----GO----- t515 = * SUB int /--* t515 int N008 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} [004111] ----------- IL_OFFSET void INLRT @ 0x71A[E-] N001 ( 1, 2) [000495] ----------- t495 = CNS_INT int 0 $c0 /--* t495 int N003 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} [004112] ----------- IL_OFFSET void INLRT @ 0x71D[E-] N001 ( 1, 1) [000507] ----------- t507 = LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- t502 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- t503 = LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- t499 = LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- t505 = LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- t506 = LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- t3068 = CNS_INT(h) long 0x4000000000540240 ftn $5e /--* t507 int arg6 in x5 +--* t502 byref arg1 in x0 +--* t503 ref arg2 in x1 +--* t499 int arg3 in x2 +--* t505 int arg4 in x3 +--* t506 int arg5 in x4 +--* t3068 long r2r cell in x11 N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void [004113] ----------- IL_OFFSET void INLRT @ 0x72C[E-] N001 ( 1, 2) [003069] ----------- t3069 = CNS_INT int 0 $c0 /--* t3069 int N003 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} [004114] ----------- IL_OFFSET void INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [000333] ----------- t333 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003070] ----------- t3070 = CNS_INT long 8 $201 /--* t333 byref +--* t3070 long N003 ( 3, 4) [003071] -------N--- t3071 = * ADD byref $25a /--* t3071 byref N004 ( 4, 3) [002349] ---XG------ t2349 = * IND int /--* t2349 int N006 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 [004115] ----------- IL_OFFSET void INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002352] ----------- t2352 = LCL_VAR int V129 tmp89 u:1 N002 ( 1, 1) [002353] ----------- t2353 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003074] ----------- t3074 = CNS_INT long 24 $20c /--* t2353 byref +--* t3074 long N004 ( 3, 4) [003075] -------N--- t3075 = * ADD byref $25b /--* t3075 byref N005 ( 4, 3) [002388] n---GO----- t2388 = * IND int /--* t2352 int +--* t2388 int N006 ( 6, 5) [002357] N---GO-N-U- t2357 = * GE int /--* t2357 int N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} [004116] ----------- IL_OFFSET void INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [003079] ----------- t3079 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] ----------- t3080 = CNS_INT long 16 $200 /--* t3079 byref +--* t3080 long N003 ( 3, 4) [003081] -----O----- t3081 = * ADD byref $25c /--* t3081 byref N005 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 [004117] ----------- IL_OFFSET void INL61 @ ??? <- INLRT @ 0x731[E-] N001 ( 1, 1) [002363] ----------- t2363 = LCL_VAR int V129 tmp89 u:1 N002 ( 1, 1) [002368] ----------- t2368 = LCL_VAR byref V130 tmp90 u:1 $25c N003 ( 1, 2) [003083] ----------- t3083 = CNS_INT long 8 $201 /--* t2368 byref +--* t3083 long N004 ( 3, 4) [003084] -------N--- t3084 = * ADD byref $25d /--* t3084 byref N005 ( 4, 3) [002369] n---GO----- t2369 = * IND int /--* t2363 int +--* t2369 int N006 ( 9, 11) [002370] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002367] ----------- t2367 = LCL_VAR byref V130 tmp90 u:1 (last use) $25c /--* t2367 byref N008 ( 3, 2) [002374] n---GO----- t2374 = * IND byref N009 ( 1, 1) [002364] ----------- t2364 = LCL_VAR int V129 tmp89 u:1 /--* t2364 int N010 ( 2, 3) [002371] ---------U- t2371 = * CAST long <- uint N011 ( 1, 2) [002372] ----------- t2372 = CNS_INT long 1 $204 /--* t2371 long +--* t2372 long N012 ( 4, 6) [002373] ----------- t2373 = * LSH long /--* t2374 byref +--* t2373 long N013 ( 8, 9) [002375] ----GO-N--- t2375 = * ADD byref N016 ( 1, 1) [002377] ----------- t2377 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2375 byref +--* t2377 int [004118] -A-XGO----- * STOREIND short [004119] ----------- IL_OFFSET void INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002381] ----------- t2381 = LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] ----------- t2382 = CNS_INT int 1 $c1 /--* t2381 int +--* t2382 int N003 ( 3, 4) [002383] ----------- t2383 = * ADD int N004 ( 1, 1) [002380] ----------- t2380 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003086] ----------- t3086 = CNS_INT long 8 $201 /--* t2380 byref +--* t3086 long N006 ( 3, 4) [003087] -------N--- t3087 = * ADD byref $25a /--* t3087 byref +--* t2383 int [004120] -A--GO----- * STOREIND int ------------ BB229 [731..732), preds={BB227} succs={BB230} [004121] ----------- IL_OFFSET void INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002359] ----------- t2359 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- t334 = LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- t3088 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2359 byref this in x0 +--* t334 int arg2 in x1 +--* t3088 long r2r cell in x11 N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} [004122] ----------- IL_OFFSET void INLRT @ 0x739[E-] N001 ( 1, 1) [000336] ----------- t336 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- t3705 = LCL_VAR int V179 cse8 u:1 $342 /--* t336 int +--* t3705 int N003 ( 3, 3) [000341] J------N--- t341 = * GE int $94d /--* t341 int N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} [004123] ----------- IL_OFFSET void INLRT @ 0x744[E-] N001 ( 1, 1) [000343] ----------- t343 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000344] ----------- t344 = LCL_VAR int V16 loc12 u:5 $898 /--* t344 int N003 ( 2, 3) [000345] ----------- t345 = * CAST long <- int $3e5 N004 ( 1, 2) [000347] ----------- t347 = CNS_INT long 1 $204 /--* t345 long +--* t347 long N005 ( 4, 6) [000348] ----------- t348 = * LSH long $3e6 /--* t343 long +--* t348 long N006 ( 6, 8) [000349] -------N--- t349 = * ADD long $3e7 /--* t349 long N007 ( 9, 10) [000350] ---XG------ t350 = * IND ushort /--* t350 ushort N009 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 N010 ( 1, 1) [003659] ----------- t3659 = LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] ----------- t351 = CNS_INT int 43 $d9 /--* t3659 int +--* t351 int N013 ( 12, 14) [000352] J--XG--N--- t352 = * EQ int /--* t352 int N014 ( 14, 16) [000353] ---XG------ * JTRUE void $87a ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} [004124] ----------- IL_OFFSET void INLRT @ 0x751[E-] N001 ( 1, 1) [003661] ----------- t3661 = LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] ----------- t416 = CNS_INT int 45 $da /--* t3661 int +--* t416 int N003 ( 3, 4) [000417] N---G--N-U- t417 = * NE int /--* t417 int N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} [004125] ----------- IL_OFFSET void INLRT @ 0x75E[E-] N001 ( 1, 1) [000356] ----------- t356 = LCL_VAR int V16 loc12 u:5 $898 /--* t356 int N003 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 [004126] ----------- IL_OFFSET void INLRT @ 0x75E[E-] N001 ( 1, 1) [000357] ----------- t357 = LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] ----------- t358 = CNS_INT int 1 $c1 /--* t357 int +--* t358 int N003 ( 3, 4) [000359] ----------- t359 = * ADD int $952 /--* t359 int N005 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 N001 ( 1, 1) [003662] ----------- t3662 = LCL_VAR int V175 cse4 u:1 /--* t3662 int N003 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 [004127] ----------- IL_OFFSET void INL64 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000354] ----------- t354 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003089] ----------- t3089 = CNS_INT long 8 $201 /--* t354 byref +--* t3089 long N003 ( 3, 4) [003090] -------N--- t3090 = * ADD byref $25a /--* t3090 byref N004 ( 4, 3) [002396] n---GO----- t2396 = * IND int /--* t2396 int N006 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 [004128] ----------- IL_OFFSET void INL64 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002399] ----------- t2399 = LCL_VAR int V132 tmp92 u:1 N002 ( 1, 1) [002400] ----------- t2400 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003093] ----------- t3093 = CNS_INT long 24 $20c /--* t2400 byref +--* t3093 long N004 ( 3, 4) [003094] -------N--- t3094 = * ADD byref $25b /--* t3094 byref N005 ( 4, 3) [002438] n---GO----- t2438 = * IND int /--* t2399 int +--* t2438 int N006 ( 6, 5) [002404] N---GO-N-U- t2404 = * GE int /--* t2404 int N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} [004129] ----------- IL_OFFSET void INL64 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003098] ----------- t3098 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] ----------- t3099 = CNS_INT long 16 $200 /--* t3098 byref +--* t3099 long N003 ( 3, 4) [003100] -----O----- t3100 = * ADD byref $25c /--* t3100 byref N005 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 N001 ( 1, 1) [002411] ----------- t2411 = LCL_VAR int V132 tmp92 u:1 N002 ( 1, 1) [002416] ----------- t2416 = LCL_VAR byref V134 tmp94 u:1 $25c N003 ( 1, 2) [003102] ----------- t3102 = CNS_INT long 8 $201 /--* t2416 byref +--* t3102 long N004 ( 3, 4) [003103] -------N--- t3103 = * ADD byref $25d /--* t3103 byref N005 ( 4, 3) [002417] n---GO----- t2417 = * IND int /--* t2411 int +--* t2417 int N006 ( 9, 11) [002418] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002415] ----------- t2415 = LCL_VAR byref V134 tmp94 u:1 (last use) $25c /--* t2415 byref N008 ( 3, 2) [002422] n---GO----- t2422 = * IND byref N009 ( 1, 1) [002412] ----------- t2412 = LCL_VAR int V132 tmp92 u:1 /--* t2412 int N010 ( 2, 3) [002419] ---------U- t2419 = * CAST long <- uint N011 ( 1, 2) [002420] ----------- t2420 = CNS_INT long 1 $204 /--* t2419 long +--* t2420 long N012 ( 4, 6) [002421] ----------- t2421 = * LSH long /--* t2422 byref +--* t2421 long N013 ( 8, 9) [002423] ----GO-N--- t2423 = * ADD byref N016 ( 1, 1) [002425] ----------- t2425 = LCL_VAR int V133 tmp93 u:1 (last use) /--* t2423 byref +--* t2425 int [004130] -A-XGO----- * STOREIND short [004131] ----------- IL_OFFSET void INL64 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002429] ----------- t2429 = LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] ----------- t2430 = CNS_INT int 1 $c1 /--* t2429 int +--* t2430 int N003 ( 3, 4) [002431] ----------- t2431 = * ADD int N004 ( 1, 1) [002428] ----------- t2428 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003105] ----------- t3105 = CNS_INT long 8 $201 /--* t2428 byref +--* t3105 long N006 ( 3, 4) [003106] -------N--- t3106 = * ADD byref $25a /--* t3106 byref +--* t2431 int [004132] -A--GO----- * STOREIND int ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} [004133] ----------- IL_OFFSET void INL64 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002406] ----------- t2406 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- t2407 = LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- t3107 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2406 byref this in x0 +--* t2407 int arg2 in x1 +--* t3107 long r2r cell in x11 N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} [004134] ----------- IL_OFFSET void INLRT @ 0x774[E-] N001 ( 1, 1) [000392] ----------- t392 = LCL_VAR int V16 loc12 u:6 $b08 /--* t392 int N003 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 [004135] ----------- IL_OFFSET void INLRT @ 0x774[E-] N001 ( 1, 1) [000393] ----------- t393 = LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] ----------- t394 = CNS_INT int 1 $c1 /--* t393 int +--* t394 int N003 ( 3, 4) [000395] ----------- t395 = * ADD int $c47 /--* t395 int N005 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 N001 ( 1, 1) [003639] ----------- t3639 = LCL_VAR int V173 cse2 u:1 /--* t3639 int N003 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 [004136] ----------- IL_OFFSET void INL66 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000390] ----------- t390 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003108] ----------- t3108 = CNS_INT long 8 $201 /--* t390 byref +--* t3108 long N003 ( 3, 4) [003109] -------N--- t3109 = * ADD byref $25a /--* t3109 byref N004 ( 4, 3) [002442] n---GO----- t2442 = * IND int /--* t2442 int N006 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 [004137] ----------- IL_OFFSET void INL66 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002445] ----------- t2445 = LCL_VAR int V136 tmp96 u:1 N002 ( 1, 1) [002446] ----------- t2446 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003112] ----------- t3112 = CNS_INT long 24 $20c /--* t2446 byref +--* t3112 long N004 ( 3, 4) [003113] -------N--- t3113 = * ADD byref $25b /--* t3113 byref N005 ( 4, 3) [002484] n---GO----- t2484 = * IND int /--* t2445 int +--* t2484 int N006 ( 6, 5) [002450] N---GO-N-U- t2450 = * GE int /--* t2450 int N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} [004138] ----------- IL_OFFSET void INL66 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003117] ----------- t3117 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] ----------- t3118 = CNS_INT long 16 $200 /--* t3117 byref +--* t3118 long N003 ( 3, 4) [003119] -----O----- t3119 = * ADD byref $25c /--* t3119 byref N005 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 N001 ( 1, 1) [002457] ----------- t2457 = LCL_VAR int V136 tmp96 u:1 N002 ( 1, 1) [002462] ----------- t2462 = LCL_VAR byref V138 tmp98 u:1 $25c N003 ( 1, 2) [003121] ----------- t3121 = CNS_INT long 8 $201 /--* t2462 byref +--* t3121 long N004 ( 3, 4) [003122] -------N--- t3122 = * ADD byref $25d /--* t3122 byref N005 ( 4, 3) [002463] n---GO----- t2463 = * IND int /--* t2457 int +--* t2463 int N006 ( 9, 11) [002464] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002461] ----------- t2461 = LCL_VAR byref V138 tmp98 u:1 (last use) $25c /--* t2461 byref N008 ( 3, 2) [002468] n---GO----- t2468 = * IND byref N009 ( 1, 1) [002458] ----------- t2458 = LCL_VAR int V136 tmp96 u:1 /--* t2458 int N010 ( 2, 3) [002465] ---------U- t2465 = * CAST long <- uint N011 ( 1, 2) [002466] ----------- t2466 = CNS_INT long 1 $204 /--* t2465 long +--* t2466 long N012 ( 4, 6) [002467] ----------- t2467 = * LSH long /--* t2468 byref +--* t2467 long N013 ( 8, 9) [002469] ----GO-N--- t2469 = * ADD byref N016 ( 1, 1) [002471] ----------- t2471 = LCL_VAR int V137 tmp97 u:1 (last use) /--* t2469 byref +--* t2471 int [004139] -A-XGO----- * STOREIND short [004140] ----------- IL_OFFSET void INL66 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002475] ----------- t2475 = LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] ----------- t2476 = CNS_INT int 1 $c1 /--* t2475 int +--* t2476 int N003 ( 3, 4) [002477] ----------- t2477 = * ADD int N004 ( 1, 1) [002474] ----------- t2474 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003124] ----------- t3124 = CNS_INT long 8 $201 /--* t2474 byref +--* t3124 long N006 ( 3, 4) [003125] -------N--- t3125 = * ADD byref $25a /--* t3125 byref +--* t2477 int [004141] -A--GO----- * STOREIND int ------------ BB238 [000..000), preds={BB236} succs={BB239} [004142] ----------- IL_OFFSET void INL66 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002452] ----------- t2452 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- t2453 = LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- t3126 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2452 byref this in x0 +--* t2453 int arg2 in x1 +--* t3126 long r2r cell in x11 N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} [004143] ----------- IL_OFFSET void INLRT @ 0x788[E-] N001 ( 1, 1) [000372] ----------- t372 = LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- t3706 = LCL_VAR int V179 cse8 u:1 $342 /--* t372 int +--* t3706 int N003 ( 3, 3) [000377] J------N--- t377 = * GE int $c42 /--* t377 int N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} [004144] ----------- IL_OFFSET void INLRT @ 0x793[E-] N001 ( 1, 1) [000379] ----------- t379 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000380] ----------- t380 = LCL_VAR int V16 loc12 u:6 $b08 /--* t380 int N003 ( 2, 3) [000381] ----------- t381 = * CAST long <- int $ad1 N004 ( 1, 2) [000383] ----------- t383 = CNS_INT long 1 $204 /--* t381 long +--* t383 long N005 ( 4, 6) [000384] ----------- t384 = * LSH long $ad2 /--* t379 long +--* t384 long N006 ( 6, 8) [000385] -------N--- t385 = * ADD long $ad3 /--* t385 long N007 ( 9, 10) [000386] ---XG------ t386 = * IND ushort /--* t386 ushort N009 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 N010 ( 1, 1) [003642] ----------- t3642 = LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] ----------- t387 = CNS_INT int 48 $d8 /--* t3642 int +--* t387 int N013 ( 12, 14) [000388] J--XG--N--- t388 = * EQ int /--* t388 int N014 ( 14, 16) [000389] ---XG------ * JTRUE void $c02 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB137(2),BB138(2),BB140,BB143} succs={BB243,BB244} [004145] ----------- IL_OFFSET void INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [000590] ----------- t590 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003127] ----------- t3127 = CNS_INT long 8 $201 /--* t590 byref +--* t3127 long N003 ( 3, 4) [003128] -------N--- t3128 = * ADD byref $25a /--* t3128 byref N004 ( 4, 3) [002492] ---XG------ t2492 = * IND int /--* t2492 int N006 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 [004146] ----------- IL_OFFSET void INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002495] ----------- t2495 = LCL_VAR int V140 tmp100 u:1 N002 ( 1, 1) [002496] ----------- t2496 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 2) [003131] ----------- t3131 = CNS_INT long 24 $20c /--* t2496 byref +--* t3131 long N004 ( 3, 4) [003132] -------N--- t3132 = * ADD byref $25b /--* t3132 byref N005 ( 4, 3) [002531] n---GO----- t2531 = * IND int /--* t2495 int +--* t2531 int N006 ( 6, 5) [002500] N---GO-N-U- t2500 = * GE int /--* t2500 int N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} [004147] ----------- IL_OFFSET void INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [003136] ----------- t3136 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] ----------- t3137 = CNS_INT long 16 $200 /--* t3136 byref +--* t3137 long N003 ( 3, 4) [003138] -----O----- t3138 = * ADD byref $25c /--* t3138 byref N005 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 [004148] ----------- IL_OFFSET void INL69 @ ??? <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002506] ----------- t2506 = LCL_VAR int V140 tmp100 u:1 N002 ( 1, 1) [002511] ----------- t2511 = LCL_VAR byref V141 tmp101 u:1 $25c N003 ( 1, 2) [003140] ----------- t3140 = CNS_INT long 8 $201 /--* t2511 byref +--* t3140 long N004 ( 3, 4) [003141] -------N--- t3141 = * ADD byref $25d /--* t3141 byref N005 ( 4, 3) [002512] n---GO----- t2512 = * IND int /--* t2506 int +--* t2512 int N006 ( 9, 11) [002513] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002510] ----------- t2510 = LCL_VAR byref V141 tmp101 u:1 (last use) $25c /--* t2510 byref N008 ( 3, 2) [002517] n---GO----- t2517 = * IND byref N009 ( 1, 1) [002507] ----------- t2507 = LCL_VAR int V140 tmp100 u:1 /--* t2507 int N010 ( 2, 3) [002514] ---------U- t2514 = * CAST long <- uint N011 ( 1, 2) [002515] ----------- t2515 = CNS_INT long 1 $204 /--* t2514 long +--* t2515 long N012 ( 4, 6) [002516] ----------- t2516 = * LSH long /--* t2517 byref +--* t2516 long N013 ( 8, 9) [002518] ----GO-N--- t2518 = * ADD byref N016 ( 1, 1) [002520] ----------- t2520 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2518 byref +--* t2520 int [004149] -A-XGO----- * STOREIND short [004150] ----------- IL_OFFSET void INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002524] ----------- t2524 = LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] ----------- t2525 = CNS_INT int 1 $c1 /--* t2524 int +--* t2525 int N003 ( 3, 4) [002526] ----------- t2526 = * ADD int N004 ( 1, 1) [002523] ----------- t2523 = LCL_VAR byref V00 arg0 u:1 $100 N005 ( 1, 2) [003143] ----------- t3143 = CNS_INT long 8 $201 /--* t2523 byref +--* t3143 long N006 ( 3, 4) [003144] -------N--- t3144 = * ADD byref $25a /--* t3144 byref +--* t2526 int [004151] -A--GO----- * STOREIND int ------------ BB244 [7A2..7A3) -> BB245 (always), preds={BB215,BB242} succs={BB245} [004152] ----------- IL_OFFSET void INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002502] ----------- t2502 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- t591 = LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- t3145 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2502 byref this in x0 +--* t591 int arg2 in x1 +--* t3145 long r2r cell in x11 N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB110 [000..000) (throw), preds={BB91} succs={} [004153] ----------- IL_OFFSET void INL17 @ 0x029[E-] <- INLRT @ ??? N001 ( 2, 8) [002701] H---------- t2701 = CNS_INT(h) long 0x4000000000424a20 ftn $4a /--* t2701 long r2r cell in x11 N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void ------------ BB254 [???..???) (throw), preds={} succs={} N001 ( 14, 2) [004154] --CXG------ CALL help void CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Lowering nodeinfo lowering call (before): N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn $42 /--* t0 byref this in x0 +--* t2543 long r2r cell in x11 N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [000000] ----------- * LCL_VAR byref V01 arg1 u:1 $101 new node is : [004185] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 2, 8) [002543] H---------- * CNS_INT(h) long 0x400000000046ac80 ftn $42 new node is : [004186] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 $101 /--* t0 byref [004185] ----------- t4185 = * PUTARG_REG byref REG x0 N002 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn $42 /--* t2543 long [004186] ----------- t4186 = * PUTARG_REG long REG x11 /--* t4185 byref this in x0 +--* t4186 long r2r cell in x11 N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void lowering store lcl var/field (before): N001 ( 1, 2) [000002] ----------- t2 = CNS_INT int 0 $c0 /--* t2 int N003 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000002] -c--------- t2 = CNS_INT int 0 $c0 /--* t2 int N003 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] -c--------- t2547 = CNS_INT long 16 $200 /--* t2546 byref +--* t2547 long N003 ( 3, 4) [002548] -----O----- t2548 = * ADD byref $240 /--* t2548 byref N005 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] -c--------- t2547 = CNS_INT long 16 $200 /--* t2546 byref +--* t2547 long N003 ( 3, 4) [002548] -----O----- t2548 = * ADD byref $240 /--* t2548 byref N005 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 Addressing mode: Base N002 ( 1, 1) [001502] ----------- * LCL_VAR byref V76 tmp36 u:1 $240 + 8 Removing unused node: N003 ( 1, 2) [002555] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002556] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N007 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 (last use) $240 /--* t1501 byref N008 ( 3, 2) [001505] n---GO----- t1505 = * IND byref /--* t1505 byref N011 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 lowering store lcl var/field (after): N007 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 (last use) $240 /--* t1501 byref N008 ( 3, 2) [001505] n---GO----- t1505 = * IND byref /--* t1505 byref N011 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 lowering store lcl var/field (before): N012 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 /--* t2552 long N015 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 lowering store lcl var/field (after): N012 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 /--* t2552 long N015 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 lowering store lcl var/field (before): N001 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] $246 /--* t2558 byref N003 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 lowering store lcl var/field (after): N001 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] $246 /--* t2558 byref N003 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 lowering store lcl var/field (before): N004 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3710 byref N007 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 lowering store lcl var/field (after): N004 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3710 byref N007 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 lowering store lcl var/field (before): N008 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] $342 /--* t2561 int N010 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 lowering store lcl var/field (after): N008 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] $342 /--* t2561 int N010 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 lowering store lcl var/field (before): N011 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 $342 /--* t3690 int N014 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 lowering store lcl var/field (after): N011 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 $342 /--* t3690 int N014 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 lowering store lcl var/field (before): N001 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2565 byref N003 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 lowering store lcl var/field (after): N001 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2565 byref N003 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 lowering store lcl var/field (before): N004 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2568 int N006 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 lowering store lcl var/field (after): N004 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2568 int N006 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 Addressing mode: Base N001 ( 1, 1) [001472] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 8 Removing unused node: N002 ( 1, 2) [002571] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002572] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2574 byref N003 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 lowering store lcl var/field (after): N001 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2574 byref N003 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 lowering store lcl var/field (before): N004 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2577 int N006 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 lowering store lcl var/field (after): N004 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2577 int N006 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 lowering store lcl var/field (before): N001 ( 1, 2) [001489] ----------- t1489 = CNS_INT int 0 $c0 /--* t1489 int N003 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 lowering store lcl var/field (after): N001 ( 1, 2) [001489] -c--------- t1489 = CNS_INT int 0 $c0 /--* t1489 int N003 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 lowering store lcl var/field (before): N001 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2581 byref N003 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2581 byref N003 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 lowering store lcl var/field (before): N004 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2584 int N006 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 lowering store lcl var/field (after): N004 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2584 int N006 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 lowering store lcl var/field (before): N001 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 $c1 /--* t1482 int N003 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 lowering store lcl var/field (after): N001 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 $c1 /--* t1482 int N003 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2588 byref N003 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2588 byref N003 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 lowering store lcl var/field (before): N004 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2591 int N006 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 lowering store lcl var/field (after): N004 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2591 int N006 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 lowering store lcl var/field (before): N001 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 $c2 /--* t21 int N003 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 lowering store lcl var/field (after): N001 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 $c2 /--* t21 int N003 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 lowering call (before): N001 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 (last use) $246 N002 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 (last use) $342 /--* t2596 byref +--* t2597 int N003 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct $141 N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 (last use) $281 N005 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2595 struct arg1 x0,x1 +--* t29 int arg2 in x2 +--* t2594 long r2r cell in x11 N006 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int $2c1 args: ====== late: ====== lowering arg : N003 ( 6, 4) [002595] -c--------- * FIELD_LIST struct $141 lowering arg : N004 ( 3, 2) [000029] ----------- * LCL_VAR int V43 tmp3 u:1 (last use) $281 new node is : [004189] ----------- * PUTARG_REG int REG x2 lowering arg : N005 ( 2, 8) [002594] H---------- * CNS_INT(h) long 0x40000000005401e8 ftn $43 new node is : [004190] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 (last use) $246 /--* t2596 byref [004187] ----------- t4187 = * PUTARG_REG byref REG x0 N002 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 (last use) $342 /--* t2597 int [004188] ----------- t4188 = * PUTARG_REG int REG x1 /--* t4187 byref +--* t4188 int N003 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct $141 N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 (last use) $281 /--* t29 int [004189] ----------- t4189 = * PUTARG_REG int REG x2 N005 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2594 long [004190] ----------- t4190 = * PUTARG_REG long REG x11 /--* t2595 struct arg1 x0,x1 +--* t4189 int arg2 in x2 +--* t4190 long r2r cell in x11 N006 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int $2c1 lowering store lcl var/field (before): N001 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 (last use) $246 /--* t2596 byref [004187] ----------- t4187 = * PUTARG_REG byref REG x0 N002 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 (last use) $342 /--* t2597 int [004188] ----------- t4188 = * PUTARG_REG int REG x1 /--* t4187 byref +--* t4188 int N003 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct $141 N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 (last use) $281 /--* t29 int [004189] ----------- t4189 = * PUTARG_REG int REG x2 N005 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2594 long [004190] ----------- t4190 = * PUTARG_REG long REG x11 /--* t2595 struct arg1 x0,x1 +--* t4189 int arg2 in x2 +--* t4190 long r2r cell in x11 N006 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int $2c1 /--* t30 int N008 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 lowering store lcl var/field (after): N001 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 (last use) $246 /--* t2596 byref [004187] ----------- t4187 = * PUTARG_REG byref REG x0 N002 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 (last use) $342 /--* t2597 int [004188] ----------- t4188 = * PUTARG_REG int REG x1 /--* t4187 byref +--* t4188 int N003 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct $141 N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 (last use) $281 /--* t29 int [004189] ----------- t4189 = * PUTARG_REG int REG x2 N005 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2594 long [004190] ----------- t4190 = * PUTARG_REG long REG x11 /--* t2595 struct arg1 x0,x1 +--* t4189 int arg2 in x2 +--* t4190 long r2r cell in x11 N006 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int $2c1 /--* t30 int N008 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000035] ----------- t35 = CNS_INT int 0 $c0 /--* t35 int N003 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000035] -c--------- t35 = CNS_INT int 0 $c0 /--* t35 int N003 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 $c4 /--* t38 int N003 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 $c4 /--* t38 int N003 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 lowering store lcl var/field (before): N001 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF $c9 /--* t41 int N003 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 lowering store lcl var/field (after): N001 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF $c9 /--* t41 int N003 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000044] ----------- t44 = CNS_INT int 0 $c0 /--* t44 int N003 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000044] -c--------- t44 = CNS_INT int 0 $c0 /--* t44 int N003 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [002598] ----------- t2598 = CNS_INT int 0 $c0 /--* t2598 int N003 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [002598] -c--------- t2598 = CNS_INT int 0 $c0 /--* t2598 int N003 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 $c4 /--* t50 int N003 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 $c4 /--* t50 int N003 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [002599] ----------- t2599 = CNS_INT int 0 $c0 /--* t2599 int N003 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [002599] -c--------- t2599 = CNS_INT int 0 $c0 /--* t2599 int N003 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000056] ----------- t56 = CNS_INT int 0 $c0 /--* t56 int N003 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000056] -c--------- t56 = CNS_INT int 0 $c0 /--* t56 int N003 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 $283 /--* t59 int N003 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 $283 /--* t59 int N003 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3712 byref N003 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3712 byref N003 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 $246 /--* t1512 byref N003 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 lowering store lcl var/field (after): N001 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 $246 /--* t1512 byref N003 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 lowering store lcl var/field (before): N001 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 (last use) $246 /--* t69 byref N003 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 (last use) $246 /--* t69 byref N003 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 lowering store lcl var/field (before): N004 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 (last use) $3c4 /--* t2609 long N007 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 lowering store lcl var/field (after): N004 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 (last use) $3c4 /--* t2609 long N007 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 Lowering switch BB09, 7 cases lvaGrabTemp returning 182 (V182 rat0) called for ReplaceWithLclVar is creating a new local variable. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) [004192] DA--------- * STORE_LCL_VAR int V182 rat0 ReplaceWithLclVar created store : [004192] DA--------- * STORE_LCL_VAR int V182 rat0 lowering store lcl var/field (before): N001 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] -c--------- t1362 = CNS_INT int -34 $d6 /--* t1361 int +--* t1362 int N003 ( 3, 4) [001363] ----------- t1363 = * ADD int /--* t1363 int [004192] DA--------- * STORE_LCL_VAR int V182 rat0 lowering store lcl var/field (after): N001 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] -c--------- t1362 = CNS_INT int -34 $d6 /--* t1361 int +--* t1362 int N003 ( 3, 4) [001363] ----------- t1363 = * ADD int /--* t1363 int [004192] DA--------- * STORE_LCL_VAR int V182 rat0 New Basic Block BB255 [0364] created. Setting edge weights for BB255 -> BB31 to [0 .. 3.402823e+38] Setting edge weights for BB255 -> BB17 to [0 .. 3.402823e+38] Setting edge weights for BB255 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB255 -> BB30 to [0 .. 3.402823e+38] Setting edge weights for BB255 -> BB10 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB255 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB10 to [0 .. 3.402823e+38] Lowering switch BB09: using jump table expansion LowerCast for: [004199] ---------U- * CAST long <- ulong <- uint Lowering switch BB10, 6 cases lvaGrabTemp returning 183 (V183 rat1) called for ReplaceWithLclVar is creating a new local variable. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) [004203] DA--------- * STORE_LCL_VAR int V183 rat1 ReplaceWithLclVar created store : [004203] DA--------- * STORE_LCL_VAR int V183 rat1 lowering store lcl var/field (before): N001 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] -c--------- t1366 = CNS_INT int -44 $d7 /--* t1365 int +--* t1366 int N003 ( 3, 4) [001367] ----------- t1367 = * ADD int /--* t1367 int [004203] DA--------- * STORE_LCL_VAR int V183 rat1 lowering store lcl var/field (after): N001 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] -c--------- t1366 = CNS_INT int -44 $d7 /--* t1365 int +--* t1366 int N003 ( 3, 4) [001367] ----------- t1367 = * ADD int /--* t1367 int [004203] DA--------- * STORE_LCL_VAR int V183 rat1 New Basic Block BB256 [0365] created. Setting edge weights for BB256 -> BB23 to [0 .. 3.402823e+38] Setting edge weights for BB256 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB256 -> BB21 to [0 .. 3.402823e+38] Setting edge weights for BB256 -> BB18 to [0 .. 3.402823e+38] Setting edge weights for BB256 -> BB11 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB256 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB11 to [0 .. 3.402823e+38] Lowering switch BB10: using jump table expansion LowerCast for: [004210] ---------U- * CAST long <- ulong <- uint lowering store lcl var/field (before): N001 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] -c--------- t1357 = CNS_INT int 3 $c3 /--* t1356 int +--* t1357 int N003 ( 3, 4) [001358] ----------- t1358 = * ADD int $376 /--* t1358 int N005 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] -c--------- t1357 = CNS_INT int 3 $c3 /--* t1356 int +--* t1357 int N003 ( 3, 4) [001358] ----------- t1358 = * ADD int $376 /--* t1358 int N005 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 lowering store lcl var/field (before): N001 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] -c--------- t1431 = CNS_INT int 1 $c1 /--* t1430 int +--* t1431 int N003 ( 3, 4) [001432] ----------- t1432 = * ADD int $68f /--* t1432 int N005 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] -c--------- t1431 = CNS_INT int 1 $c1 /--* t1430 int +--* t1431 int N003 ( 3, 4) [001432] ----------- t1432 = * ADD int $68f /--* t1432 int N005 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 lowering store lcl var/field (before): N001 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 $28a /--* t1385 int N003 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 $28a /--* t1385 int N003 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 lowering store lcl var/field (before): N001 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] -c--------- t1378 = CNS_INT int 1 $c1 /--* t1377 int +--* t1378 int N003 ( 3, 4) [001379] ----------- t1379 = * ADD int $68f /--* t1379 int N005 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] -c--------- t1378 = CNS_INT int 1 $c1 /--* t1377 int +--* t1378 int N003 ( 3, 4) [001379] ----------- t1379 = * ADD int $68f /--* t1379 int N005 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 $68f /--* t1382 int N003 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 $68f /--* t1382 int N003 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 $28a /--* t1392 int N003 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 $28a /--* t1392 int N003 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 Lowered `AND` chain: N007 ( 13, 9) [003726] J------N--- * AND int N003 ( 6, 4) [001397] -c-----N--- +--* LE int $691 N001 ( 1, 1) [001395] ----------- | +--* LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] -c--------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [001401] -c-----N--- \--* GE int $690 N004 ( 1, 1) [001399] ----------- +--* LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] -c--------- \--* CNS_INT int 0 $c0 lowering store lcl var/field (before): N001 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] -c--------- t1421 = CNS_INT int 1 $c1 /--* t1420 int +--* t1421 int N003 ( 3, 4) [001422] ----------- t1422 = * ADD int $694 /--* t1422 int N005 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] -c--------- t1421 = CNS_INT int 1 $c1 /--* t1420 int +--* t1421 int N003 ( 3, 4) [001422] ----------- t1422 = * ADD int $694 /--* t1422 int N005 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 lowering store lcl var/field (before): N001 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 $c1 /--* t2612 int N003 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 lowering store lcl var/field (after): N001 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 $c1 /--* t2612 int N003 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 lowering store lcl var/field (before): N001 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 $28a /--* t1407 int N003 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 $28a /--* t1407 int N003 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 lowering store lcl var/field (before): N001 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 $c1 /--* t1410 int N003 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 lowering store lcl var/field (after): N001 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 $c1 /--* t1410 int N003 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] -c--------- t1426 = CNS_INT int 2 $c2 /--* t1425 int +--* t1426 int N003 ( 3, 4) [001427] ----------- t1427 = * ADD int $695 /--* t1427 int N005 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 lowering store lcl var/field (after): N001 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] -c--------- t1426 = CNS_INT int 2 $c2 /--* t1425 int +--* t1426 int N003 ( 3, 4) [001427] ----------- t1427 = * ADD int $695 /--* t1427 int N005 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 LowerCast for: N006 ( 2, 3) [001444] ----------- * CAST long <- int $3de Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N004 ( 1, 1) [001442] ----------- * LCL_VAR long V22 loc18 u:1 $3c4 + Index * 1 + 0 N008 ( 4, 6) [001447] ----------- * BFIZ long New addressing mode node: N009 ( 6, 8) [001448] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N004 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1443 int N006 ( 2, 3) [001444] -c--------- t1444 = * CAST long <- int $3de N007 ( 1, 2) [001446] -c--------- t1446 = CNS_INT long 1 $204 /--* t1444 long +--* t1446 long N008 ( 4, 6) [001447] -c--------- t1447 = * BFIZ long /--* t1442 long +--* t1447 long N009 ( 6, 8) [001448] -c--------- t1448 = * LEA(b+(i*1)+0) long /--* t1448 long N010 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort /--* t1449 ushort N012 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 lowering store lcl var/field (after): N004 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1443 int N006 ( 2, 3) [001444] -c--------- t1444 = * CAST long <- int $3de N007 ( 1, 2) [001446] -c--------- t1446 = CNS_INT long 1 $204 /--* t1444 long +--* t1446 long N008 ( 4, 6) [001447] -c--------- t1447 = * BFIZ long /--* t1442 long +--* t1447 long N009 ( 6, 8) [001448] -c--------- t1448 = * LEA(b+(i*1)+0) long /--* t1448 long N010 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort /--* t1449 ushort N012 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 Lowered `AND` chain: N017 ( 22, 18) [003728] J--XG--N--- * AND int N003 ( 6, 3) [001440] -c-----N--- +--* GE int $8b7 N001 ( 1, 1) [001435] ----------- | +--* LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001451] -c-XG--N--- \--* EQ int N013 ( 1, 1) [003626] ----------- +--* LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] -c--------- \--* CNS_INT int 0 $c0 lowering store lcl var/field (before): N001 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1454 int N003 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1454 int N003 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] -c--------- t1456 = CNS_INT int 1 $c1 /--* t1455 int +--* t1456 int N003 ( 3, 4) [001457] ----------- t1457 = * ADD int $8bc /--* t1457 int N005 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 lowering store lcl var/field (after): N001 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] -c--------- t1456 = CNS_INT int 1 $c1 /--* t1455 int +--* t1456 int N003 ( 3, 4) [001457] ----------- t1457 = * ADD int $8bc /--* t1457 int N005 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 LowerCast for: N006 ( 2, 3) [001243] ----------- * CAST long <- int $3c8 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N004 ( 1, 1) [001241] ----------- * LCL_VAR long V22 loc18 u:1 $3c4 + Index * 1 + 0 N008 ( 4, 6) [001246] ----------- * BFIZ long New addressing mode node: N009 ( 6, 8) [001247] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N004 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 $361 /--* t1242 int N006 ( 2, 3) [001243] -c--------- t1243 = * CAST long <- int $3c8 N007 ( 1, 2) [001245] -c--------- t1245 = CNS_INT long 1 $204 /--* t1243 long +--* t1245 long N008 ( 4, 6) [001246] -c--------- t1246 = * BFIZ long /--* t1241 long +--* t1246 long N009 ( 6, 8) [001247] -c--------- t1247 = * LEA(b+(i*1)+0) long /--* t1247 long N010 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort /--* t1248 ushort N012 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 lowering store lcl var/field (after): N004 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 $361 /--* t1242 int N006 ( 2, 3) [001243] -c--------- t1243 = * CAST long <- int $3c8 N007 ( 1, 2) [001245] -c--------- t1245 = CNS_INT long 1 $204 /--* t1243 long +--* t1245 long N008 ( 4, 6) [001246] -c--------- t1246 = * BFIZ long /--* t1241 long +--* t1246 long N009 ( 6, 8) [001247] -c--------- t1247 = * LEA(b+(i*1)+0) long /--* t1247 long N010 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort /--* t1248 ushort N012 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 Lowered `AND` chain: N017 ( 22, 18) [003730] J--XG--N--- * AND int N003 ( 6, 3) [001239] -c-----N--- +--* GE int $36c N001 ( 1, 1) [001234] ----------- | +--* LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [001250] -c-XG--N--- \--* EQ int N013 ( 1, 1) [003646] ----------- +--* LCL_VAR int V174 cse3 N015 ( 1, 2) [001249] -c--------- \--* CNS_INT int 0 $c0 lowering store lcl var/field (before): N001 ( 1, 1) [001252] ----------- t1252 = LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] -c--------- t1253 = CNS_INT int 1 $c1 /--* t1252 int +--* t1253 int N003 ( 3, 4) [001254] ----------- t1254 = * ADD int $371 /--* t1254 int N005 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 lowering store lcl var/field (after): N001 ( 1, 1) [001252] ----------- t1252 = LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] -c--------- t1253 = CNS_INT int 1 $c1 /--* t1252 int +--* t1253 int N003 ( 3, 4) [001254] ----------- t1254 = * ADD int $371 /--* t1254 int N005 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 LowerCast for: N003 ( 2, 3) [001343] ----------- * CAST long <- int $3c8 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [001341] ----------- * LCL_VAR long V22 loc18 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [001346] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [001347] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [001341] ----------- t1341 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001342] ----------- t1342 = LCL_VAR int V16 loc12 u:17 $361 /--* t1342 int N003 ( 2, 3) [001343] -c--------- t1343 = * CAST long <- int $3c8 N004 ( 1, 2) [001345] -c--------- t1345 = CNS_INT long 1 $204 /--* t1343 long +--* t1345 long N005 ( 4, 6) [001346] -c--------- t1346 = * BFIZ long /--* t1341 long +--* t1346 long N006 ( 6, 8) [001347] -c--------- t1347 = * LEA(b+(i*1)+0) long /--* t1347 long N007 ( 9, 10) [001348] ---XG------ t1348 = * IND ushort /--* t1348 ushort N009 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 lowering store lcl var/field (after): N001 ( 1, 1) [001341] ----------- t1341 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001342] ----------- t1342 = LCL_VAR int V16 loc12 u:17 $361 /--* t1342 int N003 ( 2, 3) [001343] -c--------- t1343 = * CAST long <- int $3c8 N004 ( 1, 2) [001345] -c--------- t1345 = CNS_INT long 1 $204 /--* t1343 long +--* t1345 long N005 ( 4, 6) [001346] -c--------- t1346 = * BFIZ long /--* t1341 long +--* t1346 long N006 ( 6, 8) [001347] -c--------- t1347 = * LEA(b+(i*1)+0) long /--* t1347 long N007 ( 9, 10) [001348] ---XG------ t1348 = * IND ushort /--* t1348 ushort N009 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 LowerCast for: N003 ( 2, 3) [001279] ----------- * CAST long <- int $3c8 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [001277] ----------- * LCL_VAR long V22 loc18 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [001282] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [001283] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [001277] ----------- t1277 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001278] ----------- t1278 = LCL_VAR int V16 loc12 u:17 $361 /--* t1278 int N003 ( 2, 3) [001279] -c--------- t1279 = * CAST long <- int $3c8 N004 ( 1, 2) [001281] -c--------- t1281 = CNS_INT long 1 $204 /--* t1279 long +--* t1281 long N005 ( 4, 6) [001282] -c--------- t1282 = * BFIZ long /--* t1277 long +--* t1282 long N006 ( 6, 8) [001283] -c--------- t1283 = * LEA(b+(i*1)+0) long /--* t1283 long N007 ( 9, 10) [001284] ---XG------ t1284 = * IND ushort /--* t1284 ushort N009 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 lowering store lcl var/field (after): N001 ( 1, 1) [001277] ----------- t1277 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001278] ----------- t1278 = LCL_VAR int V16 loc12 u:17 $361 /--* t1278 int N003 ( 2, 3) [001279] -c--------- t1279 = * CAST long <- int $3c8 N004 ( 1, 2) [001281] -c--------- t1281 = CNS_INT long 1 $204 /--* t1279 long +--* t1281 long N005 ( 4, 6) [001282] -c--------- t1282 = * BFIZ long /--* t1277 long +--* t1282 long N006 ( 6, 8) [001283] -c--------- t1283 = * LEA(b+(i*1)+0) long /--* t1283 long N007 ( 9, 10) [001284] ---XG------ t1284 = * IND ushort /--* t1284 ushort N009 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 LowerCast for: N005 ( 4, 6) [001292] ----------- * CAST long <- int $3cb Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [001288] ----------- * LCL_VAR long V22 loc18 u:1 $3c4 + Index * 1 + 0 N007 ( 6, 9) [001295] ----------- * BFIZ long New addressing mode node: N008 ( 8, 11) [001296] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [001301] ----------- t1301 = LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] -c--------- t1302 = CNS_INT int 1 $c1 /--* t1301 int +--* t1302 int N003 ( 3, 4) [001303] ----------- t1303 = * ADD int $942 /--* t1303 int N005 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001301] ----------- t1301 = LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] -c--------- t1302 = CNS_INT int 1 $c1 /--* t1301 int +--* t1302 int N003 ( 3, 4) [001303] ----------- t1303 = * ADD int $942 /--* t1303 int N005 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001307] ----------- t1307 = LCL_VAR int V73 tmp33 u:1 $942 /--* t1307 int N003 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 lowering store lcl var/field (after): N001 ( 1, 1) [001307] ----------- t1307 = LCL_VAR int V73 tmp33 u:1 $942 /--* t1307 int N003 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 LowerCast for: N003 ( 2, 3) [001321] ----------- * CAST long <- int $3e1 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [001319] ----------- * LCL_VAR long V22 loc18 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [001324] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [001325] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 2) [002613] ----------- t2613 = CNS_INT int 1 $c1 /--* t2613 int N003 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 lowering store lcl var/field (after): N001 ( 1, 2) [002613] ----------- t2613 = CNS_INT int 1 $c1 /--* t2613 int N003 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 lowering store lcl var/field (before): N001 ( 1, 1) [001198] ----------- t1198 = LCL_VAR int V16 loc12 u:2 $28b /--* t1198 int N003 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001198] ----------- t1198 = LCL_VAR int V16 loc12 u:2 $28b /--* t1198 int N003 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001199] ----------- t1199 = LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] -c--------- t1200 = CNS_INT int 1 $c1 /--* t1199 int +--* t1200 int N003 ( 3, 4) [001201] ----------- t1201 = * ADD int $361 /--* t1201 int N005 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 lowering store lcl var/field (after): N001 ( 1, 1) [001199] ----------- t1199 = LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] -c--------- t1200 = CNS_INT int 1 $c1 /--* t1199 int +--* t1200 int N003 ( 3, 4) [001201] ----------- t1201 = * ADD int $361 /--* t1201 int N005 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 LowerCast for: N003 ( 2, 3) [001207] ----------- * CAST long <- int $3c5 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [001197] ----------- * LCL_VAR long V22 loc18 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [001210] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [001211] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [001197] ----------- t1197 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001206] ----------- t1206 = LCL_VAR int V71 tmp31 u:1 (last use) $28b /--* t1206 int N003 ( 2, 3) [001207] -c--------- t1207 = * CAST long <- int $3c5 N004 ( 1, 2) [001209] -c--------- t1209 = CNS_INT long 1 $204 /--* t1207 long +--* t1209 long N005 ( 4, 6) [001210] -c--------- t1210 = * BFIZ long /--* t1197 long +--* t1210 long N006 ( 6, 8) [001211] -c--------- t1211 = * LEA(b+(i*1)+0) long /--* t1211 long N007 ( 9, 10) [001212] ---XG------ t1212 = * IND ushort /--* t1212 ushort N009 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001197] ----------- t1197 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001206] ----------- t1206 = LCL_VAR int V71 tmp31 u:1 (last use) $28b /--* t1206 int N003 ( 2, 3) [001207] -c--------- t1207 = * CAST long <- int $3c5 N004 ( 1, 2) [001209] -c--------- t1209 = CNS_INT long 1 $204 /--* t1207 long +--* t1209 long N005 ( 4, 6) [001210] -c--------- t1210 = * BFIZ long /--* t1197 long +--* t1210 long N006 ( 6, 8) [001211] -c--------- t1211 = * LEA(b+(i*1)+0) long /--* t1211 long N007 ( 9, 10) [001212] ---XG------ t1212 = * IND ushort /--* t1212 ushort N009 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001216] ----------- t1216 = LCL_VAR int V72 tmp32 u:1 /--* t1216 int N003 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [001216] ----------- t1216 = LCL_VAR int V72 tmp32 u:1 /--* t1216 int N003 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 lowering store lcl var/field (before): N001 ( 1, 2) [000081] ----------- t81 = CNS_INT long 0 $205 /--* t81 long N003 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 lowering store lcl var/field (after): N001 ( 1, 2) [000081] -c--------- t81 = CNS_INT long 0 $205 /--* t81 long N003 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 lowering store lcl var/field (before): N001 ( 1, 1) [001194] ----------- t1194 = LCL_VAR int V04 loc0 u:2 $28a /--* t1194 int N003 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [001194] ----------- t1194 = LCL_VAR int V04 loc0 u:2 $28a /--* t1194 int N003 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [001187] ----------- t1187 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 1) [001188] ----------- t1188 = LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- t1189 = CNS_INT int 3 $c3 /--* t1188 int +--* t1189 int N004 ( 6, 6) [001190] -c--------- t1190 = * MUL int $697 /--* t1187 int +--* t1190 int N005 ( 8, 8) [001191] ----------- t1191 = * SUB int $698 /--* t1191 int N007 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [001187] ----------- t1187 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 1) [001188] ----------- t1188 = LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- t1189 = CNS_INT int 3 $c3 /--* t1188 int +--* t1189 int N004 ( 6, 6) [001190] -c--------- t1190 = * MUL int $697 /--* t1187 int +--* t1190 int N005 ( 8, 8) [001191] ----------- t1191 = * SUB int $698 /--* t1191 int N007 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 lowering store lcl var/field (before): N001 ( 1, 2) [002615] ----------- t2615 = CNS_INT int 1 $c1 /--* t2615 int N003 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 lowering store lcl var/field (after): N001 ( 1, 2) [002615] ----------- t2615 = CNS_INT int 1 $c1 /--* t2615 int N003 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [002618] ----------- t2618 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] -c--------- t2619 = CNS_INT long 4 $207 /--* t2618 byref +--* t2619 long N003 ( 3, 4) [002620] -----O----- t2620 = * ADD byref $24a /--* t2620 byref N005 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002618] ----------- t2618 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] -c--------- t2619 = CNS_INT long 4 $207 /--* t2618 byref +--* t2619 long N003 ( 3, 4) [002620] -----O----- t2620 = * ADD byref $24a /--* t2620 byref N005 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 Addressing mode: Base N001 ( 1, 1) [001171] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 4 Removing unused node: N002 ( 1, 2) [002622] -c--------- * CNS_INT long 4 $207 New addressing mode node: N003 ( 3, 4) [002623] ----------- * LEA(b+4) byref lowering store lcl var/field (before): N001 ( 1, 1) [001171] ----------- t1171 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1171 byref N003 ( 3, 4) [002623] -c--------- t2623 = * LEA(b+4) byref /--* t2623 byref N004 ( 4, 3) [001172] n---GO----- t1172 = * IND int N005 ( 1, 1) [001173] ----------- t1173 = LCL_VAR int V04 loc0 u:2 $28a /--* t1172 int +--* t1173 int N006 ( 6, 5) [001174] ----GO----- t1174 = * ADD int N007 ( 1, 1) [001175] ----------- t1175 = LCL_VAR int V05 loc1 u:3 $28d /--* t1174 int +--* t1175 int N008 ( 8, 7) [001176] ----GO----- t1176 = * SUB int /--* t1176 int N010 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [001171] ----------- t1171 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1171 byref N003 ( 3, 4) [002623] -c--------- t2623 = * LEA(b+4) byref /--* t2623 byref N004 ( 4, 3) [001172] n---GO----- t1172 = * IND int N005 ( 1, 1) [001173] ----------- t1173 = LCL_VAR int V04 loc0 u:2 $28a /--* t1172 int +--* t1173 int N006 ( 6, 5) [001174] ----GO----- t1174 = * ADD int N007 ( 1, 1) [001175] ----------- t1175 = LCL_VAR int V05 loc1 u:3 $28d /--* t1174 int +--* t1175 int N008 ( 8, 7) [001176] ----GO----- t1176 = * SUB int /--* t1176 int N010 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 lowering store lcl var/field (before): N001 ( 1, 1) [001141] ----------- t1141 = LCL_VAR int V04 loc0 u:2 $28a /--* t1141 int N003 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [001141] ----------- t1141 = LCL_VAR int V04 loc0 u:2 $28a /--* t1141 int N003 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 lowering call (before): N001 ( 1, 1) [001145] ----------- t1145 = LCL_VAR int V70 tmp30 u:1 (last use) $291 N002 ( 1, 1) [001148] ----------- t1148 = LCL_VAR byref V01 arg1 u:1 $101 N003 ( 2, 8) [002624] H---------- t2624 = CNS_INT(h) long 0x400000000046acb8 ftn $45 N004 ( 1, 2) [001150] ----------- t1150 = CNS_INT int 0 $c0 /--* t1145 int arg2 in x1 +--* t1148 byref arg1 in x0 +--* t2624 long r2r cell in x11 +--* t1150 int arg3 in x2 N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [001145] ----------- * LCL_VAR int V70 tmp30 u:1 (last use) $291 new node is : [004213] ----------- * PUTARG_REG int REG x1 lowering arg : N002 ( 1, 1) [001148] ----------- * LCL_VAR byref V01 arg1 u:1 $101 new node is : [004214] ----------- * PUTARG_REG byref REG x0 lowering arg : N003 ( 2, 8) [002624] H---------- * CNS_INT(h) long 0x400000000046acb8 ftn $45 new node is : [004215] ----------- * PUTARG_REG long REG x11 lowering arg : N004 ( 1, 2) [001150] ----------- * CNS_INT int 0 $c0 new node is : [004216] ----------- * PUTARG_REG int REG x2 lowering call (after): N001 ( 1, 1) [001145] ----------- t1145 = LCL_VAR int V70 tmp30 u:1 (last use) $291 /--* t1145 int [004213] ----------- t4213 = * PUTARG_REG int REG x1 N002 ( 1, 1) [001148] ----------- t1148 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1148 byref [004214] ----------- t4214 = * PUTARG_REG byref REG x0 N003 ( 2, 8) [002624] H---------- t2624 = CNS_INT(h) long 0x400000000046acb8 ftn $45 /--* t2624 long [004215] ----------- t4215 = * PUTARG_REG long REG x11 N004 ( 1, 2) [001150] ----------- t1150 = CNS_INT int 0 $c0 /--* t1150 int [004216] ----------- t4216 = * PUTARG_REG int REG x2 /--* t4213 int arg2 in x1 +--* t4214 byref arg1 in x0 +--* t4215 long r2r cell in x11 +--* t4216 int arg3 in x2 N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void lowering call (before): N001 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 $246 N002 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] $3ce /--* t3713 byref +--* t2628 long N003 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct $142 N004 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn $43 N005 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 $c2 /--* t2626 struct arg1 x0,x1 +--* t2625 long r2r cell in x11 +--* t1158 int arg2 in x2 N006 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int $2c4 args: ====== late: ====== lowering arg : N003 ( 4, 5) [002626] -c--------- * FIELD_LIST struct $142 lowering arg : N004 ( 2, 8) [002625] H---------- * CNS_INT(h) long 0x40000000005401e8 ftn $43 new node is : [004219] ----------- * PUTARG_REG long REG x11 lowering arg : N005 ( 1, 2) [001158] ----------- * CNS_INT int 2 $c2 new node is : [004220] ----------- * PUTARG_REG int REG x2 lowering call (after): N001 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3713 byref [004217] ----------- t4217 = * PUTARG_REG byref REG x0 N002 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] $3ce /--* t2628 long [004218] ----------- t4218 = * PUTARG_REG long REG x1 /--* t4217 byref +--* t4218 long N003 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct $142 N004 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2625 long [004219] ----------- t4219 = * PUTARG_REG long REG x11 N005 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 $c2 /--* t1158 int [004220] ----------- t4220 = * PUTARG_REG int REG x2 /--* t2626 struct arg1 x0,x1 +--* t4219 long r2r cell in x11 +--* t4220 int arg2 in x2 N006 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int $2c4 lowering store lcl var/field (before): N001 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3713 byref [004217] ----------- t4217 = * PUTARG_REG byref REG x0 N002 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] $3ce /--* t2628 long [004218] ----------- t4218 = * PUTARG_REG long REG x1 /--* t4217 byref +--* t4218 long N003 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct $142 N004 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2625 long [004219] ----------- t4219 = * PUTARG_REG long REG x11 N005 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 $c2 /--* t1158 int [004220] ----------- t4220 = * PUTARG_REG int REG x2 /--* t2626 struct arg1 x0,x1 +--* t4219 long r2r cell in x11 +--* t4220 int arg2 in x2 N006 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int $2c4 /--* t1159 int N008 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 lowering store lcl var/field (after): N001 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3713 byref [004217] ----------- t4217 = * PUTARG_REG byref REG x0 N002 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] $3ce /--* t2628 long [004218] ----------- t4218 = * PUTARG_REG long REG x1 /--* t4217 byref +--* t4218 long N003 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct $142 N004 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2625 long [004219] ----------- t4219 = * PUTARG_REG long REG x11 N005 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 $c2 /--* t1158 int [004220] ----------- t4220 = * PUTARG_REG int REG x2 /--* t2626 struct arg1 x0,x1 +--* t4219 long r2r cell in x11 +--* t4220 int arg2 in x2 N006 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int $2c4 /--* t1159 int N008 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 lowering store lcl var/field (before): N001 ( 1, 1) [001168] ----------- t1168 = LCL_VAR int V16 loc12 u:16 (last use) $2c4 /--* t1168 int N003 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [001168] ----------- t1168 = LCL_VAR int V16 loc12 u:16 (last use) $2c4 /--* t1168 int N003 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 Addressing mode: Base N001 ( 1, 1) [000097] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 10 Removing unused node: N002 ( 1, 2) [002629] -c--------- * CNS_INT long 10 $206 New addressing mode node: N003 ( 3, 4) [002630] ----------- * LEA(b+10) byref Addressing mode: Base N001 ( 1, 1) [001122] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 8 Removing unused node: N002 ( 1, 2) [002631] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002632] ----------- * LEA(b+8) byref Addressing mode: Base N001 ( 1, 1) [000102] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 4 Removing unused node: N002 ( 1, 2) [002633] -c--------- * CNS_INT long 4 $207 New addressing mode node: N003 ( 3, 4) [002634] ----------- * LEA(b+4) byref lowering store lcl var/field (before): N001 ( 1, 1) [000106] ----------- t106 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- t107 = LCL_VAR int V05 loc1 u:3 $28d /--* t106 int +--* t107 int N003 ( 3, 3) [000108] Jc-----N--- t108 = * LT int $6b7 N004 ( 1, 1) [000110] ----------- t110 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- t111 = LCL_VAR int V06 loc2 u:2 (last use) $284 /--* t110 int +--* t111 int N006 ( 3, 3) [000112] ----------- t112 = * SUB int $6b8 N007 ( 1, 2) [001118] -c--------- t1118 = CNS_INT int 0 $c0 /--* t108 int +--* t112 int +--* t1118 int N008 ( 8, 9) [003777] ----------- t3777 = * SELECT int /--* t3777 int N010 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000106] ----------- t106 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- t107 = LCL_VAR int V05 loc1 u:3 $28d /--* t106 int +--* t107 int N003 ( 3, 3) [000108] Jc-----N--- t108 = * LT int $6b7 N004 ( 1, 1) [000110] ----------- t110 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- t111 = LCL_VAR int V06 loc2 u:2 (last use) $284 /--* t110 int +--* t111 int N006 ( 3, 3) [000112] ----------- t112 = * SUB int $6b8 N007 ( 1, 2) [001118] -c--------- t1118 = CNS_INT int 0 $c0 /--* t108 int +--* t112 int +--* t1118 int N008 ( 8, 9) [003777] ----------- t3777 = * SELECT int /--* t3777 int N010 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [000116] ----------- t116 = LCL_VAR int V44 tmp4 u:1 (last use) $292 /--* t116 int N003 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [000116] ----------- t116 = LCL_VAR int V44 tmp4 u:1 (last use) $292 /--* t116 int N003 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 lowering store lcl var/field (before): N001 ( 1, 1) [000119] ----------- t119 = LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- t120 = LCL_VAR int V05 loc1 u:3 $28d /--* t119 int +--* t120 int N003 ( 3, 3) [000121] Jc-----N--- t121 = * GT int $6b9 N004 ( 1, 1) [000123] ----------- t123 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- t124 = LCL_VAR int V07 loc3 u:2 (last use) $285 /--* t123 int +--* t124 int N006 ( 3, 3) [000125] ----------- t125 = * SUB int $6ba N007 ( 1, 2) [001114] -c--------- t1114 = CNS_INT int 0 $c0 /--* t121 int +--* t125 int +--* t1114 int N008 ( 8, 9) [003774] ----------- t3774 = * SELECT int /--* t3774 int N010 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000119] ----------- t119 = LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- t120 = LCL_VAR int V05 loc1 u:3 $28d /--* t119 int +--* t120 int N003 ( 3, 3) [000121] Jc-----N--- t121 = * GT int $6b9 N004 ( 1, 1) [000123] ----------- t123 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- t124 = LCL_VAR int V07 loc3 u:2 (last use) $285 /--* t123 int +--* t124 int N006 ( 3, 3) [000125] ----------- t125 = * SUB int $6ba N007 ( 1, 2) [001114] -c--------- t1114 = CNS_INT int 0 $c0 /--* t121 int +--* t125 int +--* t1114 int N008 ( 8, 9) [003774] ----------- t3774 = * SELECT int /--* t3774 int N010 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [000129] ----------- t129 = LCL_VAR int V45 tmp5 u:1 (last use) $293 /--* t129 int N003 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [000129] ----------- t129 = LCL_VAR int V45 tmp5 u:1 (last use) $293 /--* t129 int N003 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 lowering store lcl var/field (before): N001 ( 1, 1) [001108] ----------- t1108 = LCL_VAR int V05 loc1 u:3 $28d /--* t1108 int N003 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 lowering store lcl var/field (after): N001 ( 1, 1) [001108] ----------- t1108 = LCL_VAR int V05 loc1 u:3 $28d /--* t1108 int N003 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 lowering store lcl var/field (before): N001 ( 1, 2) [001111] ----------- t1111 = CNS_INT int 0 $c0 /--* t1111 int N003 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 lowering store lcl var/field (after): N001 ( 1, 2) [001111] -c--------- t1111 = CNS_INT int 0 $c0 /--* t1111 int N003 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 Addressing mode: Base N001 ( 1, 1) [000136] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 4 Removing unused node: N002 ( 1, 2) [002635] -c--------- * CNS_INT long 4 $207 New addressing mode node: N003 ( 3, 4) [002636] ----------- * LEA(b+4) byref lowering store lcl var/field (before): N001 ( 1, 1) [000136] ----------- t136 = LCL_VAR byref V01 arg1 u:1 $101 /--* t136 byref N003 ( 3, 4) [002636] -c--------- t2636 = * LEA(b+4) byref /--* t2636 byref N004 ( 4, 3) [000137] n---GO----- t137 = * IND int /--* t137 int N006 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000136] ----------- t136 = LCL_VAR byref V01 arg1 u:1 $101 /--* t136 byref N003 ( 3, 4) [002636] -c--------- t2636 = * LEA(b+4) byref /--* t2636 byref N004 ( 4, 3) [000137] n---GO----- t137 = * IND int /--* t137 int N006 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 lowering store lcl var/field (before): N007 ( 3, 2) [003684] ----------- t3684 = LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- t138 = LCL_VAR int V05 loc1 u:3 $28d /--* t3684 int +--* t138 int N010 ( 13, 10) [000139] Jc--GO-N--- t139 = * GT int N011 ( 3, 2) [003686] ----------- t3686 = LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- t1104 = LCL_VAR int V05 loc1 u:3 $28d /--* t139 int +--* t3686 int +--* t1104 int N013 ( 18, 14) [003771] ----GO----- t3771 = * SELECT int /--* t3771 int N015 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 lowering store lcl var/field (after): N007 ( 3, 2) [003684] ----------- t3684 = LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- t138 = LCL_VAR int V05 loc1 u:3 $28d /--* t3684 int +--* t138 int N010 ( 13, 10) [000139] Jc--GO-N--- t139 = * GT int N011 ( 3, 2) [003686] ----------- t3686 = LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- t1104 = LCL_VAR int V05 loc1 u:3 $28d /--* t139 int +--* t3686 int +--* t1104 int N013 ( 18, 14) [003771] ----GO----- t3771 = * SELECT int /--* t3771 int N015 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [000146] ----------- t146 = LCL_VAR int V46 tmp6 u:1 (last use) $295 /--* t146 int N003 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 lowering store lcl var/field (after): N001 ( 3, 2) [000146] ----------- t146 = LCL_VAR int V46 tmp6 u:1 (last use) $295 /--* t146 int N003 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 lowering store lcl var/field (before): N001 ( 3, 2) [003687] ----------- t3687 = LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- t151 = LCL_VAR int V05 loc1 u:3 $28d /--* t3687 int +--* t151 int N003 ( 5, 4) [000152] ----G------ t152 = * SUB int /--* t152 int N005 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 lowering store lcl var/field (after): N001 ( 3, 2) [003687] ----------- t3687 = LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- t151 = LCL_VAR int V05 loc1 u:3 $28d /--* t3687 int +--* t151 int N003 ( 5, 4) [000152] ----G------ t152 = * SUB int /--* t152 int N005 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 lowering store lcl var/field (before): N001 ( 1, 1) [000155] ----------- t155 = LCL_VAR int V15 loc11 u:2 $283 /--* t155 int N003 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000155] ----------- t155 = LCL_VAR int V15 loc11 u:2 $283 /--* t155 int N003 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 lowering store lcl var/field (before): N001 ( 3, 3) [001550] ----------- t1550 = LCL_VAR_ADDR long V47 tmp7 $740 /--* t1550 long N003 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 lowering store lcl var/field (after): N001 ( 3, 3) [001550] ----------- t1550 = LCL_VAR_ADDR long V47 tmp7 $740 /--* t1550 long N003 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [001556] ----------- t1556 = CNS_INT int 4 $c8 /--* t1556 int N003 ( 1, 3) [001558] DA--------- * STORE_LCL_VAR int V152 tmp112 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [001556] ----------- t1556 = CNS_INT int 4 $c8 /--* t1556 int N003 ( 1, 3) [001558] DA--------- * STORE_LCL_VAR int V152 tmp112 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [002649] ----------- t2649 = LCL_VAR byref V151 tmp111 u:1 (last use) $24b /--* t2649 byref N003 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002649] ----------- t2649 = LCL_VAR byref V151 tmp111 u:1 (last use) $24b /--* t2649 byref N003 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 lowering store lcl var/field (before): N004 ( 1, 2) [003720] ----------- t3720 = CNS_INT int 4 $c8 /--* t3720 int N006 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 lowering store lcl var/field (after): N004 ( 1, 2) [003720] ----------- t3720 = CNS_INT int 4 $c8 /--* t3720 int N006 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000175] ----------- t175 = CNS_INT int -1 $c4 /--* t175 int N003 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000175] ----------- t175 = CNS_INT int -1 $c4 /--* t175 int N003 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 Addressing mode: Base N001 ( 1, 1) [000941] ----------- * LCL_VAR ref V03 arg3 u:1 $180 + 56 Removing unused node: N002 ( 1, 2) [002655] -c--------- * CNS_INT long 56 Fseq[] $209 New addressing mode node: N003 ( 3, 4) [002656] ----------- * LEA(b+56) byref Addressing mode: Base N004 ( 4, 3) [001570] ---XG------ * IND ref + 8 Removing unused node: [004155] -c--------- * CNS_INT long 8 New addressing mode node: [004156] ----------- * LEA(b+8) byref Lowered `AND` chain: N011 ( 18, 13) [003732] J--XG--N--- * AND int N007 ( 11, 8) [000946] -c-XG--N--- +--* LE int N005 ( 6, 5) [000944] ---XG------ | +--* IND int [004156] -c--------- | | \--* LEA(b+8) byref N004 ( 4, 3) [001570] ---XG------ | | \--* IND ref N003 ( 3, 4) [002656] -c--------- | | \--* LEA(b+56) byref N001 ( 1, 1) [000941] ----------- | | \--* LCL_VAR ref V03 arg3 u:1 $180 N006 ( 1, 2) [000945] -c--------- | \--* CNS_INT int 0 $c0 N010 ( 6, 4) [000180] -c-----N--- \--* EQ int $70a N008 ( 1, 1) [000178] ----------- +--* LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] -c--------- \--* CNS_INT int 0 $c0 Addressing mode: Base N001 ( 1, 1) [000948] ----------- * LCL_VAR ref V03 arg3 u:1 $180 + 8 Removing unused node: N002 ( 1, 2) [002657] -c--------- * CNS_INT long 8 Fseq[] $201 New addressing mode node: N003 ( 3, 4) [002658] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000948] ----------- t948 = LCL_VAR ref V03 arg3 u:1 $180 /--* t948 ref N003 ( 3, 4) [002658] -c--------- t2658 = * LEA(b+8) byref /--* t2658 byref N004 ( 4, 3) [000949] n---GO----- t949 = * IND ref /--* t949 ref N006 ( 4, 3) [000951] DA--GO----- * STORE_LCL_VAR ref V26 loc22 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000948] ----------- t948 = LCL_VAR ref V03 arg3 u:1 $180 /--* t948 ref N003 ( 3, 4) [002658] -c--------- t2658 = * LEA(b+8) byref /--* t2658 byref N004 ( 4, 3) [000949] n---GO----- t949 = * IND ref /--* t949 ref N006 ( 4, 3) [000951] DA--GO----- * STORE_LCL_VAR ref V26 loc22 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000952] ----------- t952 = CNS_INT int 0 $c0 /--* t952 int N003 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000952] -c--------- t952 = CNS_INT int 0 $c0 /--* t952 int N003 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000955] ----------- t955 = CNS_INT int 0 $c0 /--* t955 int N003 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000955] -c--------- t955 = CNS_INT int 0 $c0 /--* t955 int N003 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 Addressing mode: Base N001 ( 1, 1) [000958] ----------- * LCL_VAR ref V26 loc22 u:1 + 8 Removing unused node: [004157] -c--------- * CNS_INT long 8 New addressing mode node: [004158] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 /--* t958 ref [004158] -c--------- t4158 = * LEA(b+8) byref /--* t4158 byref N002 ( 3, 3) [000959] ---X------- t959 = * IND int /--* t959 int N004 ( 3, 3) [000961] DA-X------- * STORE_LCL_VAR int V29 loc25 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 /--* t958 ref [004158] -c--------- t4158 = * LEA(b+8) byref /--* t4158 byref N002 ( 3, 3) [000959] ---X------- t959 = * IND int /--* t959 int N004 ( 3, 3) [000961] DA-X------- * STORE_LCL_VAR int V29 loc25 d:1 Addressing mode: Base N002 ( 1, 1) [002659] ----------- * LCL_VAR ref V26 loc22 u:1 + 16 Removing unused node: N003 ( 1, 2) [002666] -c--------- * CNS_INT long 16 $200 New addressing mode node: N004 ( 1, 1) [002667] ----------- * LEA(b+16) byref lowering store lcl var/field (before): N002 ( 1, 1) [002659] ----------- t2659 = LCL_VAR ref V26 loc22 u:1 /--* t2659 ref N004 ( 1, 1) [002667] -c--------- t2667 = * LEA(b+16) byref /--* t2667 byref N006 ( 4, 3) [002671] n---GO----- t2671 = * IND int /--* t2671 int N009 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 lowering store lcl var/field (after): N002 ( 1, 1) [002659] ----------- t2659 = LCL_VAR ref V26 loc22 u:1 /--* t2659 ref N004 ( 1, 1) [002667] -c--------- t2667 = * LEA(b+16) byref /--* t2667 byref N006 ( 4, 3) [002671] n---GO----- t2671 = * IND int /--* t2671 int N009 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 lowering store lcl var/field (before): N001 ( 1, 1) [000966] ----------- t966 = LCL_VAR int V28 loc24 u:2 $298 /--* t966 int N003 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000966] ----------- t966 = LCL_VAR int V28 loc24 u:2 $298 /--* t966 int N003 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000969] ----------- t969 = LCL_VAR int V08 loc4 u:1 $297 /--* t969 int N003 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000969] ----------- t969 = LCL_VAR int V08 loc4 u:1 $297 /--* t969 int N003 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 lowering store lcl var/field (before): N001 ( 3, 2) [000977] ----------- t977 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t977 int N003 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [000977] ----------- t977 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t977 int N003 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 lowering store lcl var/field (before): N001 ( 1, 2) [001091] ----------- t1091 = CNS_INT int 0 $c0 /--* t1091 int N003 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 lowering store lcl var/field (after): N001 ( 1, 2) [001091] -c--------- t1091 = CNS_INT int 0 $c0 /--* t1091 int N003 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [000978] ----------- t978 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t978 int N003 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000978] ----------- t978 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t978 int N003 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000979] ----------- t979 = LCL_VAR int V14 loc10 u:1 $296 /--* t979 int N003 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000979] ----------- t979 = LCL_VAR int V14 loc10 u:1 $296 /--* t979 int N003 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 lowering store lcl var/field (before): N001 ( 3, 2) [000986] ----------- t986 = LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- t987 = LCL_VAR int V66 tmp26 u:1 (last use) $299 /--* t986 int +--* t987 int N003 ( 7, 5) [000988] ----------- t988 = * ADD int $71a /--* t988 int N005 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 lowering store lcl var/field (after): N001 ( 3, 2) [000986] ----------- t986 = LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- t987 = LCL_VAR int V66 tmp26 u:1 (last use) $299 /--* t986 int +--* t987 int N003 ( 7, 5) [000988] ----------- t988 = * ADD int $71a /--* t988 int N005 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000991] ----------- t991 = LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- t992 = LCL_VAR int V31 loc27 u:1 $71a /--* t991 int +--* t992 int N003 ( 5, 4) [000993] Jc-----N--- t993 = * GT int $71b N004 ( 1, 1) [000995] ----------- t995 = LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- t1087 = LCL_VAR int V31 loc27 u:1 (last use) $71a /--* t993 int +--* t995 int +--* t1087 int N006 ( 10, 8) [003768] ----------- t3768 = * SELECT int /--* t3768 int N008 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000991] ----------- t991 = LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- t992 = LCL_VAR int V31 loc27 u:1 $71a /--* t991 int +--* t992 int N003 ( 5, 4) [000993] Jc-----N--- t993 = * GT int $71b N004 ( 1, 1) [000995] ----------- t995 = LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- t1087 = LCL_VAR int V31 loc27 u:1 (last use) $71a /--* t993 int +--* t995 int +--* t1087 int N006 ( 10, 8) [003768] ----------- t3768 = * SELECT int /--* t3768 int N008 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [000999] ----------- t999 = LCL_VAR int V67 tmp27 u:1 (last use) $29a /--* t999 int N003 ( 3, 3) [001001] DA--------- * STORE_LCL_VAR int V32 loc28 d:1 lowering store lcl var/field (after): N001 ( 3, 2) [000999] ----------- t999 = LCL_VAR int V67 tmp27 u:1 (last use) $29a /--* t999 int N003 ( 3, 3) [001001] DA--------- * STORE_LCL_VAR int V32 loc28 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001010] ----------- t1010 = LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] -c--------- t1011 = CNS_INT int 1 $c1 /--* t1010 int +--* t1011 int N003 ( 3, 4) [001012] ----------- t1012 = * ADD int $71f /--* t1012 int N005 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 lowering store lcl var/field (after): N001 ( 1, 1) [001010] ----------- t1010 = LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] -c--------- t1011 = CNS_INT int 1 $c1 /--* t1010 int +--* t1011 int N003 ( 3, 4) [001012] ----------- t1012 = * ADD int $71f /--* t1012 int N005 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 LowerCast for: N004 ( 4, 6) [001067] ----------- * CAST long <- int $3cf lowering call (before): N001 ( 1, 1) [001578] ----------- t1578 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] -c--------- t1065 = CNS_INT int 1 $c1 /--* t1578 int +--* t1065 int N003 ( 3, 4) [001066] ----------- t1066 = * LSH int $721 /--* t1066 int N004 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int $3cf N005 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn $49 /--* t1067 long arg1 in x0 +--* t2672 long r2r cell in x11 N006 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 args: ====== late: ====== lowering arg : N004 ( 4, 6) [001067] ----------- * CAST long <- int $3cf new node is : [004221] ----------- * PUTARG_REG long REG x0 lowering arg : N005 ( 2, 8) [002672] H---------- * CNS_INT(h) long 0x4000000000421858 ftn $49 new node is : [004222] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [001578] ----------- t1578 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] -c--------- t1065 = CNS_INT int 1 $c1 /--* t1578 int +--* t1065 int N003 ( 3, 4) [001066] ----------- t1066 = * LSH int $721 /--* t1066 int N004 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int $3cf /--* t1067 long [004221] ----------- t4221 = * PUTARG_REG long REG x0 N005 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn $49 /--* t2672 long [004222] ----------- t4222 = * PUTARG_REG long REG x11 /--* t4221 long arg1 in x0 +--* t4222 long r2r cell in x11 N006 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 lowering store lcl var/field (before): N001 ( 1, 1) [001578] ----------- t1578 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] -c--------- t1065 = CNS_INT int 1 $c1 /--* t1578 int +--* t1065 int N003 ( 3, 4) [001066] ----------- t1066 = * LSH int $721 /--* t1066 int N004 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int $3cf /--* t1067 long [004221] ----------- t4221 = * PUTARG_REG long REG x0 N005 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn $49 /--* t2672 long [004222] ----------- t4222 = * PUTARG_REG long REG x11 /--* t4221 long arg1 in x0 +--* t4222 long r2r cell in x11 N006 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 /--* t1068 ref N008 ( 20, 18) [001070] DA-XG------ * STORE_LCL_VAR ref V33 loc29 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001578] ----------- t1578 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] -c--------- t1065 = CNS_INT int 1 $c1 /--* t1578 int +--* t1065 int N003 ( 3, 4) [001066] ----------- t1066 = * LSH int $721 /--* t1066 int N004 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int $3cf /--* t1067 long [004221] ----------- t4221 = * PUTARG_REG long REG x0 N005 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn $49 /--* t2672 long [004222] ----------- t4222 = * PUTARG_REG long REG x11 /--* t4221 long arg1 in x0 +--* t4222 long r2r cell in x11 N006 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 /--* t1068 ref N008 ( 20, 18) [001070] DA-XG------ * STORE_LCL_VAR ref V33 loc29 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [002689] ----------- t2689 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] -c--------- t2690 = CNS_INT long 16 Fseq[] $200 /--* t2689 ref +--* t2690 long N003 ( 3, 4) [002691] -----O----- t2691 = * ADD byref $253 /--* t2691 byref N005 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [002689] ----------- t2689 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] -c--------- t2690 = CNS_INT long 16 Fseq[] $200 /--* t2689 ref +--* t2690 long N003 ( 3, 4) [002691] -----O----- t2691 = * ADD byref $253 /--* t2691 byref N005 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 Addressing mode: Base N001 ( 1, 1) [001607] ----------- * LCL_VAR ref V33 loc29 u:1 $800 + 8 Removing unused node: [004159] -c--------- * CNS_INT long 8 New addressing mode node: [004160] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [001607] ----------- t1607 = LCL_VAR ref V33 loc29 u:1 $800 /--* t1607 ref [004160] -c--------- t4160 = * LEA(b+8) byref /--* t4160 byref N002 ( 3, 3) [001608] ---X------- t1608 = * IND int $2cc /--* t1608 int N004 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [001607] ----------- t1607 = LCL_VAR ref V33 loc29 u:1 $800 /--* t1607 ref [004160] -c--------- t4160 = * LEA(b+8) byref /--* t4160 byref N002 ( 3, 3) [001608] ---X------- t1608 = * IND int $2cc /--* t1608 int N004 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [002694] ----------- t2694 = LCL_VAR byref V159 tmp119 u:1 (last use) $382 /--* t2694 byref N003 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002694] ----------- t2694 = LCL_VAR byref V159 tmp119 u:1 (last use) $382 /--* t2694 byref N003 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 LowerCast for: N002 ( 2, 3) [001640] ---------U- * CAST long <- ulong <- uint $3d0 lowering store lcl var/field (before): N001 ( 1, 1) [001639] ----------- t1639 = LCL_VAR int V144 tmp104 u:3 (last use) $29c /--* t1639 int N002 ( 2, 3) [001640] ---------U- t1640 = * CAST long <- ulong <- uint $3d0 /--* t1640 long N004 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001639] ----------- t1639 = LCL_VAR int V144 tmp104 u:3 (last use) $29c /--* t1639 int N002 ( 2, 3) [001640] ---------U- t1640 = * CAST long <- ulong <- uint $3d0 /--* t1640 long N004 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 lowering call (before): N001 ( 1, 1) [001663] ----------- t1663 = LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] -c--------- t1665 = CNS_INT long 2 $20a /--* t1663 long +--* t1665 long N003 ( 3, 4) [001666] ----------- t1666 = * LSH long $3d1 N004 ( 1, 1) [001661] ----------- t1661 = LCL_VAR byref V161 tmp121 u:1 (last use) $382 N005 ( 1, 1) [001662] ----------- t1662 = LCL_VAR byref V143 tmp103 u:3 (last use) $381 N006 ( 2, 8) [002700] H---------- t2700 = CNS_INT(h) long 0x4000000000420490 ftn $4b /--* t1666 long arg3 in x2 +--* t1661 byref arg1 in x0 +--* t1662 byref arg2 in x1 +--* t2700 long r2r cell in x11 N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N003 ( 3, 4) [001666] ----------- * LSH long $3d1 new node is : [004223] ----------- * PUTARG_REG long REG x2 lowering arg : N004 ( 1, 1) [001661] ----------- * LCL_VAR byref V161 tmp121 u:1 (last use) $382 new node is : [004224] ----------- * PUTARG_REG byref REG x0 lowering arg : N005 ( 1, 1) [001662] ----------- * LCL_VAR byref V143 tmp103 u:3 (last use) $381 new node is : [004225] ----------- * PUTARG_REG byref REG x1 lowering arg : N006 ( 2, 8) [002700] H---------- * CNS_INT(h) long 0x4000000000420490 ftn $4b new node is : [004226] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [001663] ----------- t1663 = LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] -c--------- t1665 = CNS_INT long 2 $20a /--* t1663 long +--* t1665 long N003 ( 3, 4) [001666] ----------- t1666 = * LSH long $3d1 /--* t1666 long [004223] ----------- t4223 = * PUTARG_REG long REG x2 N004 ( 1, 1) [001661] ----------- t1661 = LCL_VAR byref V161 tmp121 u:1 (last use) $382 /--* t1661 byref [004224] ----------- t4224 = * PUTARG_REG byref REG x0 N005 ( 1, 1) [001662] ----------- t1662 = LCL_VAR byref V143 tmp103 u:3 (last use) $381 /--* t1662 byref [004225] ----------- t4225 = * PUTARG_REG byref REG x1 N006 ( 2, 8) [002700] H---------- t2700 = CNS_INT(h) long 0x4000000000420490 ftn $4b /--* t2700 long [004226] ----------- t4226 = * PUTARG_REG long REG x11 /--* t4223 long arg3 in x2 +--* t4224 byref arg1 in x0 +--* t4225 byref arg2 in x1 +--* t4226 long r2r cell in x11 N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [002718] ----------- t2718 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] -c--------- t2719 = CNS_INT long 16 Fseq[] $200 /--* t2718 ref +--* t2719 long N003 ( 3, 4) [002720] -----O----- t2720 = * ADD byref $253 /--* t2720 byref N005 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [002718] ----------- t2718 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] -c--------- t2719 = CNS_INT long 16 Fseq[] $200 /--* t2718 ref +--* t2719 long N003 ( 3, 4) [002720] -----O----- t2720 = * ADD byref $253 /--* t2720 byref N005 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 Addressing mode: Base N001 ( 1, 1) [001719] ----------- * LCL_VAR ref V33 loc29 u:1 (last use) $800 + 8 Removing unused node: [004161] -c--------- * CNS_INT long 8 New addressing mode node: [004162] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 (last use) $800 /--* t1719 ref [004162] -c--------- t4162 = * LEA(b+8) byref /--* t4162 byref N002 ( 3, 3) [001720] ---X------- t1720 = * IND int $2cc /--* t1720 int N004 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 (last use) $800 /--* t1719 ref [004162] -c--------- t4162 = * LEA(b+8) byref /--* t4162 byref N002 ( 3, 3) [001720] ---X------- t1720 = * IND int $2cc /--* t1720 int N004 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [002723] ----------- t2723 = LCL_VAR byref V163 tmp123 u:1 (last use) $383 /--* t2723 byref N003 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [002723] ----------- t2723 = LCL_VAR byref V163 tmp123 u:1 (last use) $383 /--* t2723 byref N003 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 lowering store lcl var/field (before): N004 ( 1, 1) [002726] ----------- t2726 = LCL_VAR int V164 tmp124 u:1 (last use) $2a1 /--* t2726 int N006 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 lowering store lcl var/field (after): N004 ( 1, 1) [002726] ----------- t2726 = LCL_VAR int V164 tmp124 u:1 (last use) $2a1 /--* t2726 int N006 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 LowerCast for: N006 ( 2, 3) [001030] ---------U- * CAST long <- uint $3d2 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N004 ( 1, 1) [001033] ----------- * LCL_VAR byref V143 tmp103 u:4 $384 + Index * 1 + 0 N008 ( 4, 6) [001032] ----------- * BFIZ long New addressing mode node: N009 ( 6, 8) [001034] ----------- * LEA(b+(i*1)+0) byref lowering store lcl var/field (before): N001 ( 1, 1) [001050] ----------- t1050 = LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] -c--------- t1051 = CNS_INT int 1 $c1 /--* t1050 int +--* t1051 int N003 ( 3, 4) [001052] ----------- t1052 = * ADD int $727 /--* t1052 int N005 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [001050] ----------- t1050 = LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] -c--------- t1051 = CNS_INT int 1 $c1 /--* t1050 int +--* t1051 int N003 ( 3, 4) [001052] ----------- t1052 = * ADD int $727 /--* t1052 int N005 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 Addressing mode: Base N002 ( 1, 1) [001055] ----------- * LCL_VAR ref V26 loc22 u:1 + 8 Removing unused node: [004163] -c--------- * CNS_INT long 8 New addressing mode node: [004164] ----------- * LEA(b+8) byref LowerCast for: N009 ( 2, 3) [002734] ---------U- * CAST long <- uint $3d4 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N007 ( 3, 4) [002738] ----------- * ADD byref + Index * 1 + 0 N011 ( 4, 6) [002736] ----------- * BFIZ long New addressing mode node: N012 ( 7, 10) [002739] ----------- * LEA(b+(i*1)+0) byref lowering store lcl var/field (before): N005 ( 1, 1) [002730] ----------- t2730 = LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] -c--------- t2737 = CNS_INT long 16 $200 /--* t2730 ref +--* t2737 long N007 ( 3, 4) [002738] ----------- t2738 = * ADD byref N008 ( 1, 1) [002731] ----------- t2731 = LCL_VAR int V27 loc23 u:4 $727 /--* t2731 int N009 ( 2, 3) [002734] -c-------U- t2734 = * CAST long <- uint $3d4 N010 ( 1, 2) [002735] -c-----N--- t2735 = CNS_INT long 2 $20a /--* t2734 long +--* t2735 long N011 ( 4, 6) [002736] -c--------- t2736 = * BFIZ long /--* t2738 byref +--* t2736 long N012 ( 7, 10) [002739] -c--------- t2739 = * LEA(b+(i*1)+0) byref /--* t2739 byref N014 ( 10, 12) [002742] n---GO----- t2742 = * IND int /--* t2742 int N017 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 lowering store lcl var/field (after): N005 ( 1, 1) [002730] ----------- t2730 = LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] -c--------- t2737 = CNS_INT long 16 $200 /--* t2730 ref +--* t2737 long N007 ( 3, 4) [002738] ----------- t2738 = * ADD byref N008 ( 1, 1) [002731] ----------- t2731 = LCL_VAR int V27 loc23 u:4 $727 /--* t2731 int N009 ( 2, 3) [002734] -c-------U- t2734 = * CAST long <- uint $3d4 N010 ( 1, 2) [002735] -c-----N--- t2735 = CNS_INT long 2 $20a /--* t2734 long +--* t2735 long N011 ( 4, 6) [002736] -c--------- t2736 = * BFIZ long /--* t2738 byref +--* t2736 long N012 ( 7, 10) [002739] -c--------- t2739 = * LEA(b+(i*1)+0) byref /--* t2739 byref N014 ( 10, 12) [002742] n---GO----- t2742 = * IND int /--* t2742 int N017 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 lowering store lcl var/field (before): N001 ( 1, 1) [001045] ----------- t1045 = LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- t1046 = LCL_VAR int V30 loc26 u:3 $2a3 /--* t1045 int +--* t1046 int N003 ( 3, 3) [001047] ----------- t1047 = * ADD int $72b /--* t1047 int N005 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [001045] ----------- t1045 = LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- t1046 = LCL_VAR int V30 loc26 u:3 $2a3 /--* t1045 int +--* t1046 int N003 ( 3, 3) [001047] ----------- t1047 = * ADD int $72b /--* t1047 int N005 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 Addressing mode: Base N001 ( 1, 1) [000182] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 8 Removing unused node: N002 ( 1, 2) [002743] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002744] ----------- * LEA(b+8) byref Lowered `AND` chain: N010 ( 17, 12) [003734] J---GO-N--- * AND int N006 ( 10, 7) [000185] -c--GO-N--- +--* EQ int N004 ( 5, 4) [000183] n---GO----- | +--* IND bool N003 ( 3, 4) [002744] -c--------- | | \--* LEA(b+8) byref N001 ( 1, 1) [000182] ----------- | | \--* LCL_VAR byref V01 arg1 u:1 $101 N005 ( 1, 2) [000184] -c--------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000929] -c-----N--- \--* NE int $733 N007 ( 1, 1) [000927] ----------- +--* LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] -c--------- \--* CNS_INT int 0 $c0 Addressing mode: Base N001 ( 1, 1) [000931] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 4 Removing unused node: N002 ( 1, 2) [002745] -c--------- * CNS_INT long 4 $207 New addressing mode node: N003 ( 3, 4) [002746] ----------- * LEA(b+4) byref Addressing mode: Base N001 ( 1, 1) [000937] ----------- * LCL_VAR ref V03 arg3 u:1 $180 + 40 Removing unused node: N002 ( 1, 2) [002747] -c--------- * CNS_INT long 40 Fseq[] $20b New addressing mode node: N003 ( 3, 4) [002748] ----------- * LEA(b+40) byref lowering store lcl var/field (before): N001 ( 1, 1) [000937] ----------- t937 = LCL_VAR ref V03 arg3 u:1 $180 /--* t937 ref N003 ( 3, 4) [002748] -c--------- t2748 = * LEA(b+40) byref /--* t2748 byref N004 ( 4, 3) [001730] ---XG------ t1730 = * IND ref /--* t1730 ref N006 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000937] ----------- t937 = LCL_VAR ref V03 arg3 u:1 $180 /--* t937 ref N003 ( 3, 4) [002748] -c--------- t2748 = * LEA(b+40) byref /--* t2748 byref N004 ( 4, 3) [001730] ---XG------ t1730 = * IND ref /--* t1730 ref N006 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 Addressing mode: Base N001 ( 1, 1) [000936] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [002749] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002750] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000936] ----------- t936 = LCL_VAR byref V00 arg0 u:1 $100 /--* t936 byref N003 ( 3, 4) [002750] -c--------- t2750 = * LEA(b+8) byref /--* t2750 byref N004 ( 4, 3) [001736] ---XG------ t1736 = * IND int /--* t1736 int N006 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000936] ----------- t936 = LCL_VAR byref V00 arg0 u:1 $100 /--* t936 byref N003 ( 3, 4) [002750] -c--------- t2750 = * LEA(b+8) byref /--* t2750 byref N004 ( 4, 3) [001736] ---XG------ t1736 = * IND int /--* t1736 int N006 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 Addressing mode: Base N001 ( 1, 1) [001739] ----------- * LCL_VAR ref V86 tmp46 u:1 + 8 Removing unused node: [004165] -c--------- * CNS_INT long 8 New addressing mode node: [004166] ----------- * LEA(b+8) byref Addressing mode: Base N006 ( 1, 1) [001748] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N007 ( 1, 2) [002753] -c--------- * CNS_INT long 24 $20c New addressing mode node: N008 ( 3, 4) [002754] ----------- * LEA(b+24) byref Lowered `AND` chain: N011 ( 20, 13) [003736] J--XGO-N--- * AND int N004 ( 8, 6) [001742] Nc-X---N-U- +--* NE int N002 ( 3, 3) [001740] ---X------- | +--* IND int [004166] -c--------- | | \--* LEA(b+8) byref N001 ( 1, 1) [001739] ----------- | | \--* LCL_VAR ref V86 tmp46 u:1 N003 ( 1, 2) [001741] -c--------- | \--* CNS_INT int 1 $c1 N010 ( 11, 6) [001752] Nc--GO-N-U- \--* GE int N005 ( 3, 2) [001747] ----------- +--* LCL_VAR int V87 tmp47 u:1 N009 ( 4, 3) [001786] n---GO----- \--* IND int N008 ( 3, 4) [002754] -c--------- \--* LEA(b+24) byref N006 ( 1, 1) [001748] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 lowering store lcl var/field (before): N001 ( 1, 1) [002758] ----------- t2758 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] -c--------- t2759 = CNS_INT long 16 $200 /--* t2758 byref +--* t2759 long N003 ( 3, 4) [002760] -----O----- t2760 = * ADD byref $25c /--* t2760 byref N005 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002758] ----------- t2758 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] -c--------- t2759 = CNS_INT long 16 $200 /--* t2758 byref +--* t2759 long N003 ( 3, 4) [002760] -----O----- t2760 = * ADD byref $25c /--* t2760 byref N005 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 Addressing mode: Base N002 ( 1, 1) [001761] ----------- * LCL_VAR byref V88 tmp48 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [002762] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002763] ----------- * LEA(b+8) byref LowerCast for: N010 ( 4, 4) [001764] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N017 ( 1, 1) [002765] ----------- * LCL_VAR ref V86 tmp46 u:1 (last use) + 12 Removing unused node: N018 ( 1, 2) [002771] -c--------- * CNS_INT long 12 $20d New addressing mode node: N019 ( 1, 1) [002772] ----------- * LEA(b+12) byref Addressing mode: Base N004 ( 1, 1) [001776] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [002778] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [002779] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 2) [002781] ----------- t2781 = CNS_INT int 0 $c0 /--* t2781 int N003 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [002781] -c--------- t2781 = CNS_INT int 0 $c0 /--* t2781 int N003 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [003714] ----------- t3714 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3714 byref N003 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003714] ----------- t3714 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3714 byref N003 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001792] ----------- t1792 = LCL_VAR byref V165 tmp125 u:1 $246 /--* t1792 byref N003 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 lowering store lcl var/field (after): N001 ( 1, 1) [001792] ----------- t1792 = LCL_VAR byref V165 tmp125 u:1 $246 /--* t1792 byref N003 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 lowering store lcl var/field (before): N001 ( 1, 1) [000197] ----------- t197 = LCL_VAR byref V165 tmp125 u:1 (last use) $246 /--* t197 byref N003 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000197] ----------- t197 = LCL_VAR byref V165 tmp125 u:1 (last use) $246 /--* t197 byref N003 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 lowering store lcl var/field (before): N004 ( 1, 1) [002791] ----------- t2791 = LCL_VAR long V169 tmp129 u:1 (last use) $3c4 /--* t2791 long N007 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 lowering store lcl var/field (after): N004 ( 1, 1) [002791] ----------- t2791 = LCL_VAR long V169 tmp129 u:1 (last use) $3c4 /--* t2791 long N007 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000201] ----------- t201 = LCL_VAR long V17 loc13 u:1 /--* t201 long N003 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000201] ----------- t201 = LCL_VAR long V17 loc13 u:1 /--* t201 long N003 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000243] ----------- t243 = LCL_VAR int V16 loc12 u:4 $2ae /--* t243 int N003 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000243] ----------- t243 = LCL_VAR int V16 loc12 u:4 $2ae /--* t243 int N003 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000244] ----------- t244 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] -c--------- t245 = CNS_INT int 1 $c1 /--* t244 int +--* t245 int N003 ( 3, 4) [000246] ----------- t246 = * ADD int $898 /--* t246 int N005 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [000244] ----------- t244 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] -c--------- t245 = CNS_INT int 1 $c1 /--* t244 int +--* t245 int N003 ( 3, 4) [000246] ----------- t246 = * ADD int $898 /--* t246 int N005 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 LowerCast for: N003 ( 2, 3) [000252] ----------- * CAST long <- int $3db Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000242] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [000255] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [000256] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [000242] ----------- t242 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000251] ----------- t251 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae /--* t251 int N003 ( 2, 3) [000252] -c--------- t252 = * CAST long <- int $3db N004 ( 1, 2) [000254] -c--------- t254 = CNS_INT long 1 $204 /--* t252 long +--* t254 long N005 ( 4, 6) [000255] -c--------- t255 = * BFIZ long /--* t242 long +--* t255 long N006 ( 6, 8) [000256] -c--------- t256 = * LEA(b+(i*1)+0) long /--* t256 long N007 ( 9, 10) [000257] ---XG------ t257 = * IND ushort /--* t257 ushort N009 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000242] ----------- t242 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000251] ----------- t251 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae /--* t251 int N003 ( 2, 3) [000252] -c--------- t252 = * CAST long <- int $3db N004 ( 1, 2) [000254] -c--------- t254 = CNS_INT long 1 $204 /--* t252 long +--* t254 long N005 ( 4, 6) [000255] -c--------- t255 = * BFIZ long /--* t242 long +--* t255 long N006 ( 6, 8) [000256] -c--------- t256 = * LEA(b+(i*1)+0) long /--* t256 long N007 ( 9, 10) [000257] ---XG------ t257 = * IND ushort /--* t257 ushort N009 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000261] ----------- t261 = LCL_VAR int V50 tmp10 u:1 /--* t261 int N003 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000261] ----------- t261 = LCL_VAR int V50 tmp10 u:1 /--* t261 int N003 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000212] ----------- t212 = CNS_INT long 0 $205 /--* t212 long N003 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 lowering store lcl var/field (after): N001 ( 1, 2) [000212] -c--------- t212 = CNS_INT long 0 $205 /--* t212 long N003 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 Addressing mode: Base N001 ( 1, 1) [000215] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 8 Removing unused node: N002 ( 1, 2) [003147] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [003148] ----------- * LEA(b+8) byref Lowered `AND` chain: N010 ( 17, 12) [003764] J---GO-N--- * AND int N006 ( 10, 7) [000218] -c--GO-N--- +--* EQ int N004 ( 5, 4) [000216] n---GO----- | +--* IND bool N003 ( 3, 4) [003148] -c--------- | | \--* LEA(b+8) byref N001 ( 1, 1) [000215] ----------- | | \--* LCL_VAR byref V01 arg1 u:1 $101 N005 ( 1, 2) [000217] -c--------- | \--* CNS_INT int 0 $c0 N009 ( 6, 4) [000223] -c-----N--- \--* NE int $733 N007 ( 1, 1) [000221] ----------- +--* LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] -c--------- \--* CNS_INT int 0 $c0 Addressing mode: Base N001 ( 1, 1) [000225] ----------- * LCL_VAR byref V01 arg1 u:1 (last use) $101 + 4 Removing unused node: N002 ( 1, 2) [003149] -c--------- * CNS_INT long 4 $207 New addressing mode node: N003 ( 3, 4) [003150] ----------- * LEA(b+4) byref Addressing mode: Base N007 ( 1, 1) [000230] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N008 ( 1, 2) [003151] -c--------- * CNS_INT long 8 $201 New addressing mode node: N009 ( 3, 4) [003152] ----------- * LEA(b+8) byref Addressing mode: Base N001 ( 1, 1) [000238] ----------- * LCL_VAR ref V03 arg3 u:1 (last use) $180 + 40 Removing unused node: N002 ( 1, 2) [003154] -c--------- * CNS_INT long 40 Fseq[] $20b New addressing mode node: N003 ( 3, 4) [003155] ----------- * LEA(b+40) byref lowering call (before): N001 ( 1, 1) [000238] ----------- t238 = LCL_VAR ref V03 arg3 u:1 (last use) $180 /--* t238 ref N003 ( 3, 4) [003155] -c--------- t3155 = * LEA(b+40) byref /--* t3155 byref N004 ( 4, 3) [002541] ---XG------ t2541 = * IND ref N005 ( 1, 1) [000236] ----------- t236 = LCL_VAR byref V00 arg0 u:1 (last use) $100 N006 ( 2, 8) [003153] H---------- t3153 = CNS_INT(h) long 0x4000000000540210 ftn $51 N007 ( 1, 2) [000237] ----------- t237 = CNS_INT int 0 $c0 /--* t2541 ref arg3 in x2 +--* t236 byref this in x0 +--* t3153 long r2r cell in x11 +--* t237 int arg2 in x1 N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N004 ( 4, 3) [002541] ---XG------ * IND ref new node is : [004227] ---XG------ * PUTARG_REG ref REG x2 lowering arg : N005 ( 1, 1) [000236] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 new node is : [004228] ----------- * PUTARG_REG byref REG x0 lowering arg : N006 ( 2, 8) [003153] H---------- * CNS_INT(h) long 0x4000000000540210 ftn $51 new node is : [004229] ----------- * PUTARG_REG long REG x11 lowering arg : N007 ( 1, 2) [000237] ----------- * CNS_INT int 0 $c0 new node is : [004230] ----------- * PUTARG_REG int REG x1 lowering call (after): N001 ( 1, 1) [000238] ----------- t238 = LCL_VAR ref V03 arg3 u:1 (last use) $180 /--* t238 ref N003 ( 3, 4) [003155] -c--------- t3155 = * LEA(b+40) byref /--* t3155 byref N004 ( 4, 3) [002541] ---XG------ t2541 = * IND ref /--* t2541 ref [004227] ---XG------ t4227 = * PUTARG_REG ref REG x2 N005 ( 1, 1) [000236] ----------- t236 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t236 byref [004228] ----------- t4228 = * PUTARG_REG byref REG x0 N006 ( 2, 8) [003153] H---------- t3153 = CNS_INT(h) long 0x4000000000540210 ftn $51 /--* t3153 long [004229] ----------- t4229 = * PUTARG_REG long REG x11 N007 ( 1, 2) [000237] ----------- t237 = CNS_INT int 0 $c0 /--* t237 int [004230] ----------- t4230 = * PUTARG_REG int REG x1 /--* t4227 ref arg3 in x2 +--* t4228 byref this in x0 +--* t4229 long r2r cell in x11 +--* t4230 int arg2 in x1 N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void lowering GT_RETURN N001 ( 0, 0) [000220] ----------- * RETURN void $VN.Void ============lowering call (before): N001 ( 1, 1) [001744] ----------- t1744 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001745] ----------- t1745 = LCL_VAR ref V86 tmp46 u:1 (last use) N003 ( 2, 8) [002780] H---------- t2780 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1744 byref this in x0 +--* t1745 ref arg2 in x1 +--* t2780 long r2r cell in x11 N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [001744] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004231] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [001745] ----------- * LCL_VAR ref V86 tmp46 u:1 (last use) new node is : [004232] ----------- * PUTARG_REG ref REG x1 lowering arg : N003 ( 2, 8) [002780] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn $4f new node is : [004233] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [001744] ----------- t1744 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1744 byref [004231] ----------- t4231 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001745] ----------- t1745 = LCL_VAR ref V86 tmp46 u:1 (last use) /--* t1745 ref [004232] ----------- t4232 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002780] H---------- t2780 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2780 long [004233] ----------- t4233 = * PUTARG_REG long REG x11 /--* t4231 byref this in x0 +--* t4232 ref arg2 in x1 +--* t4233 long r2r cell in x11 N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void Lowered `AND` chain: N007 ( 13, 9) [003738] J------N--- * AND int N003 ( 6, 4) [000823] -c-----N--- +--* EQ int N001 ( 1, 1) [000821] ----------- | +--* LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] -c--------- | \--* CNS_INT int 35 $ea N006 ( 6, 4) [000921] -c-----N--- \--* EQ int N004 ( 1, 1) [000919] ----------- +--* LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- \--* CNS_INT int 46 $eb lowering store lcl var/field (before): N001 ( 1, 1) [000829] ----------- t829 = LCL_VAR byref V00 arg0 u:1 $100 /--* t829 byref N003 ( 1, 3) [000836] DA--------- * STORE_LCL_VAR byref V60 tmp20 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000829] ----------- t829 = LCL_VAR byref V00 arg0 u:1 $100 /--* t829 byref N003 ( 1, 3) [000836] DA--------- * STORE_LCL_VAR byref V60 tmp20 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000830] ----------- t830 = LCL_VAR long V36 loc32 u:7 $904 /--* t830 long N002 ( 4, 3) [000831] ---XG------ t831 = * IND ubyte /--* t831 ubyte N004 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000830] ----------- t830 = LCL_VAR long V36 loc32 u:7 $904 /--* t830 long N002 ( 4, 3) [000831] ---XG------ t831 = * IND ubyte /--* t831 ubyte N004 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000838] ----------- t838 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t838 byref N003 ( 1, 3) [000914] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000838] ----------- t838 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t838 byref N003 ( 1, 3) [000914] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:3 lowering store lcl var/field (before): N001 ( 1, 2) [000912] ----------- t912 = CNS_INT int 48 $d8 /--* t912 int N003 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 lowering store lcl var/field (after): N001 ( 1, 2) [000912] ----------- t912 = CNS_INT int 48 $d8 /--* t912 int N003 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 lowering store lcl var/field (before): N001 ( 1, 1) [000840] ----------- t840 = LCL_VAR long V36 loc32 u:7 $904 /--* t840 long N003 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000840] ----------- t840 = LCL_VAR long V36 loc32 u:7 $904 /--* t840 long N003 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000841] ----------- t841 = LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] -c--------- t843 = CNS_INT long 1 $204 /--* t841 long +--* t843 long N003 ( 3, 4) [000844] ----------- t844 = * ADD long $adc /--* t844 long N005 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 lowering store lcl var/field (after): N001 ( 1, 1) [000841] ----------- t841 = LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] -c--------- t843 = CNS_INT long 1 $204 /--* t841 long +--* t843 long N003 ( 3, 4) [000844] ----------- t844 = * ADD long $adc /--* t844 long N005 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 lowering store lcl var/field (before): N001 ( 1, 1) [000839] ----------- t839 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t839 byref N003 ( 1, 3) [000852] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000839] ----------- t839 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t839 byref N003 ( 1, 3) [000852] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [003681] ----------- t3681 = LCL_VAR int V177 cse6 u:1 /--* t3681 int N003 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [003681] ----------- t3681 = LCL_VAR int V177 cse6 u:1 /--* t3681 int N003 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 LowerCast for: N002 ( 2, 3) [001796] ----------- * CAST int <- ushort <- int $c75 lowering store lcl var/field (before): N001 ( 1, 1) [000858] ----------- t858 = LCL_VAR int V63 tmp23 u:1 (last use) $b16 /--* t858 int N002 ( 2, 3) [001796] ----------- t1796 = * CAST int <- ushort <- int $c75 /--* t1796 int N004 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000858] ----------- t858 = LCL_VAR int V63 tmp23 u:1 (last use) $b16 /--* t858 int N002 ( 2, 3) [001796] ----------- t1796 = * CAST int <- ushort <- int $c75 /--* t1796 int N004 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 Addressing mode: Base N001 ( 1, 1) [000857] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [002794] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002795] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000857] ----------- t857 = LCL_VAR byref V00 arg0 u:1 $100 /--* t857 byref N003 ( 3, 4) [002795] -c--------- t2795 = * LEA(b+8) byref /--* t2795 byref N004 ( 4, 3) [001797] ---XG------ t1797 = * IND int /--* t1797 int N006 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000857] ----------- t857 = LCL_VAR byref V00 arg0 u:1 $100 /--* t857 byref N003 ( 3, 4) [002795] -c--------- t2795 = * LEA(b+8) byref /--* t2795 byref N004 ( 4, 3) [001797] ---XG------ t1797 = * IND int /--* t1797 int N006 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 Addressing mode: Base N002 ( 1, 1) [001801] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [002798] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [002799] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [002803] ----------- t2803 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] -c--------- t2804 = CNS_INT long 16 $200 /--* t2803 byref +--* t2804 long N003 ( 3, 4) [002805] -----O----- t2805 = * ADD byref $25c /--* t2805 byref N005 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002803] ----------- t2803 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] -c--------- t2804 = CNS_INT long 16 $200 /--* t2803 byref +--* t2804 long N003 ( 3, 4) [002805] -----O----- t2805 = * ADD byref $25c /--* t2805 byref N005 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 Addressing mode: Base N002 ( 1, 1) [001817] ----------- * LCL_VAR byref V93 tmp53 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [002807] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002808] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [001820] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [001823] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [001822] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [001824] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [001829] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 + 8 Removing unused node: N005 ( 1, 2) [002810] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [002811] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [001807] ----------- t1807 = LCL_VAR byref V00 arg0 u:1 (last use) $100 N002 ( 1, 1) [001808] ----------- t1808 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 N003 ( 2, 8) [002812] H---------- t2812 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t1807 byref this in x0 +--* t1808 int arg2 in x1 +--* t2812 long r2r cell in x11 N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [001807] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 new node is : [004234] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [001808] ----------- * LCL_VAR int V92 tmp52 u:1 (last use) $c75 new node is : [004235] ----------- * PUTARG_REG int REG x1 lowering arg : N003 ( 2, 8) [002812] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 new node is : [004236] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [001807] ----------- t1807 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t1807 byref [004234] ----------- t4234 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001808] ----------- t1808 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 /--* t1808 int [004235] ----------- t4235 = * PUTARG_REG int REG x1 N003 ( 2, 8) [002812] H---------- t2812 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2812 long [004236] ----------- t4236 = * PUTARG_REG long REG x11 /--* t4234 byref this in x0 +--* t4235 int arg2 in x1 +--* t4236 long r2r cell in x11 N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void Lowered `AND` chain: N007 ( 13, 9) [003740] J------N--- * AND int N003 ( 6, 4) [000862] -c-----N--- +--* EQ int $70a N001 ( 1, 1) [000860] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] -c--------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000876] -c-----N--- \--* LE int $d03 N004 ( 1, 1) [000874] ----------- +--* LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] -c--------- \--* CNS_INT int 1 $c1 LowerCast for: N006 ( 2, 3) [000891] ---------U- * CAST long <- uint $ae2 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N004 ( 1, 1) [000894] ----------- * LCL_VAR byref V143 tmp103 u:2 $385 + Index * 1 + 0 N008 ( 4, 6) [000893] ----------- * BFIZ long New addressing mode node: N009 ( 6, 8) [000895] ----------- * LEA(b+(i*1)+0) byref Lowered `AND` chain: N019 ( 28, 28) [003742] J--XGO-N--- * AND int N015 ( 21, 23) [000900] Nc-XGO-N-U- +--* NE int N013 ( 16, 21) [000899] ---XGO----- | +--* ADD int N010 ( 8, 9) [002813] ---XGO----- | | +--* IND int N009 ( 6, 8) [000895] -c--------- | | | \--* LEA(b+(i*1)+0) byref N004 ( 1, 1) [000894] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000893] -c--------- | | | \--* BFIZ long N006 ( 2, 3) [000891] -c-------U- | | | +--* CAST long <- uint $ae2 N005 ( 1, 1) [000886] ----------- | | | | \--* LCL_VAR int V20 loc16 u:7 $b13 N007 ( 1, 2) [000892] -c--------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000898] -c--------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000882] ----------- | \--* LCL_VAR int V08 loc4 u:5 $b15 N018 ( 6, 4) [000880] -c-----N--- \--* LT int $d04 N016 ( 1, 1) [000878] ----------- +--* LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] -c--------- \--* CNS_INT int 0 $c0 Addressing mode: Base N001 ( 1, 1) [000903] ----------- * LCL_VAR ref V03 arg3 u:1 $180 + 56 Removing unused node: N002 ( 1, 2) [002814] -c--------- * CNS_INT long 56 Fseq[] $209 New addressing mode node: N003 ( 3, 4) [002815] ----------- * LEA(b+56) byref lowering store lcl var/field (before): N001 ( 1, 1) [000903] ----------- t903 = LCL_VAR ref V03 arg3 u:1 $180 /--* t903 ref N003 ( 3, 4) [002815] -c--------- t2815 = * LEA(b+56) byref /--* t2815 byref N004 ( 4, 3) [001843] ---XG------ t1843 = * IND ref /--* t1843 ref N006 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000903] ----------- t903 = LCL_VAR ref V03 arg3 u:1 $180 /--* t903 ref N003 ( 3, 4) [002815] -c--------- t2815 = * LEA(b+56) byref /--* t2815 byref N004 ( 4, 3) [001843] ---XG------ t1843 = * IND ref /--* t1843 ref N006 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 Addressing mode: Base N001 ( 1, 1) [000902] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [002816] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002817] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000902] ----------- t902 = LCL_VAR byref V00 arg0 u:1 $100 /--* t902 byref N003 ( 3, 4) [002817] -c--------- t2817 = * LEA(b+8) byref /--* t2817 byref N004 ( 4, 3) [001849] n---GO----- t1849 = * IND int /--* t1849 int N006 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000902] ----------- t902 = LCL_VAR byref V00 arg0 u:1 $100 /--* t902 byref N003 ( 3, 4) [002817] -c--------- t2817 = * LEA(b+8) byref /--* t2817 byref N004 ( 4, 3) [001849] n---GO----- t1849 = * IND int /--* t1849 int N006 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 Addressing mode: Base N001 ( 1, 1) [001852] ----------- * LCL_VAR ref V95 tmp55 u:1 + 8 Removing unused node: [004167] -c--------- * CNS_INT long 8 New addressing mode node: [004168] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 /--* t1852 ref [004168] -c--------- t4168 = * LEA(b+8) byref /--* t4168 byref N002 ( 3, 3) [001853] ---X------- t1853 = * IND int /--* t1853 int N004 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 /--* t1852 ref [004168] -c--------- t4168 = * LEA(b+8) byref /--* t4168 byref N002 ( 3, 3) [001853] ---X------- t1853 = * IND int /--* t1853 int N004 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 Addressing mode: Base N010 ( 1, 1) [001861] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N011 ( 1, 2) [002820] -c--------- * CNS_INT long 24 $20c New addressing mode node: N012 ( 3, 4) [002821] ----------- * LEA(b+24) byref Lowered `AND` chain: N015 ( 19, 13) [003744] J--XGO-N--- * AND int N008 ( 9, 7) [001855] Nc-X---N-U- +--* NE int N005 ( 1, 1) [003717] ----------- | +--* LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] -c--------- | \--* CNS_INT int 1 $c1 N014 ( 9, 5) [001865] Nc--GO-N-U- \--* GE int N009 ( 1, 1) [001860] ----------- +--* LCL_VAR int V96 tmp56 u:1 N013 ( 4, 3) [001899] n---GO----- \--* IND int N012 ( 3, 4) [002821] -c--------- \--* LEA(b+24) byref N010 ( 1, 1) [001861] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 lowering store lcl var/field (before): N001 ( 1, 1) [002825] ----------- t2825 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] -c--------- t2826 = CNS_INT long 16 $200 /--* t2825 byref +--* t2826 long N003 ( 3, 4) [002827] -----O----- t2827 = * ADD byref $25c /--* t2827 byref N005 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002825] ----------- t2825 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] -c--------- t2826 = CNS_INT long 16 $200 /--* t2825 byref +--* t2826 long N003 ( 3, 4) [002827] -----O----- t2827 = * ADD byref $25c /--* t2827 byref N005 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 Addressing mode: Base N002 ( 1, 1) [001874] ----------- * LCL_VAR byref V97 tmp57 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [002829] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002830] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [001877] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N019 ( 1, 1) [002832] ----------- * LCL_VAR ref V95 tmp55 u:1 (last use) + 12 Removing unused node: N020 ( 1, 2) [002838] -c--------- * CNS_INT long 12 $20d New addressing mode node: N021 ( 1, 1) [002839] ----------- * LEA(b+12) byref Addressing mode: Base N004 ( 1, 1) [001889] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [002845] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [002846] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [001857] ----------- t1857 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001858] ----------- t1858 = LCL_VAR ref V95 tmp55 u:1 (last use) N003 ( 2, 8) [002847] H---------- t2847 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1857 byref this in x0 +--* t1858 ref arg2 in x1 +--* t2847 long r2r cell in x11 N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [001857] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004237] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [001858] ----------- * LCL_VAR ref V95 tmp55 u:1 (last use) new node is : [004238] ----------- * PUTARG_REG ref REG x1 lowering arg : N003 ( 2, 8) [002847] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn $4f new node is : [004239] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [001857] ----------- t1857 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1857 byref [004237] ----------- t4237 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001858] ----------- t1858 = LCL_VAR ref V95 tmp55 u:1 (last use) /--* t1858 ref [004238] ----------- t4238 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002847] H---------- t2847 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2847 long [004239] ----------- t4239 = * PUTARG_REG long REG x11 /--* t4237 byref this in x0 +--* t4238 ref arg2 in x1 +--* t4239 long r2r cell in x11 N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000907] ----------- t907 = LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] -c--------- t908 = CNS_INT int -1 $c4 /--* t907 int +--* t908 int N003 ( 3, 4) [000909] ----------- t909 = * ADD int $d27 /--* t909 int N005 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 lowering store lcl var/field (after): N001 ( 1, 1) [000907] ----------- t907 = LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] -c--------- t908 = CNS_INT int -1 $c4 /--* t907 int +--* t908 int N003 ( 3, 4) [000909] ----------- t909 = * ADD int $d27 /--* t909 int N005 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 lowering store lcl var/field (before): N001 ( 1, 1) [000864] ----------- t864 = LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] -c--------- t865 = CNS_INT int -1 $c4 /--* t864 int +--* t865 int N003 ( 3, 4) [000866] ----------- t866 = * ADD int $d29 /--* t866 int N005 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 lowering store lcl var/field (after): N001 ( 1, 1) [000864] ----------- t864 = LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] -c--------- t865 = CNS_INT int -1 $c4 /--* t864 int +--* t865 int N003 ( 3, 4) [000866] ----------- t866 = * ADD int $d29 /--* t866 int N005 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 lowering store lcl var/field (before): N001 ( 1, 1) [000869] ----------- t869 = LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] -c--------- t870 = CNS_INT int -1 $c4 /--* t869 int +--* t870 int N003 ( 3, 4) [000871] ----------- t871 = * ADD int $d2a /--* t871 int N005 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 lowering store lcl var/field (after): N001 ( 1, 1) [000869] ----------- t869 = LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] -c--------- t870 = CNS_INT int -1 $c4 /--* t869 int +--* t870 int N003 ( 3, 4) [000871] ----------- t871 = * ADD int $d2a /--* t871 int N005 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 Lowering switch BB137, 7 cases lvaGrabTemp returning 184 (V184 rat2) called for ReplaceWithLclVar is creating a new local variable. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) [004241] DA--------- * STORE_LCL_VAR int V184 rat2 ReplaceWithLclVar created store : [004241] DA--------- * STORE_LCL_VAR int V184 rat2 lowering store lcl var/field (before): N001 ( 1, 1) [000593] ----------- t593 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] -c--------- t594 = CNS_INT int -34 $d6 /--* t593 int +--* t594 int N003 ( 3, 4) [000595] ----------- t595 = * ADD int /--* t595 int [004241] DA--------- * STORE_LCL_VAR int V184 rat2 lowering store lcl var/field (after): N001 ( 1, 1) [000593] ----------- t593 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] -c--------- t594 = CNS_INT int -34 $d6 /--* t593 int +--* t594 int N003 ( 3, 4) [000595] ----------- t595 = * ADD int /--* t595 int [004241] DA--------- * STORE_LCL_VAR int V184 rat2 New Basic Block BB257 [0366] created. Setting edge weights for BB257 -> BB194 to [0 .. 3.402823e+38] Setting edge weights for BB257 -> BB145 to [0 .. 3.402823e+38] Setting edge weights for BB257 -> BB242 to [0 .. 3.402823e+38] Setting edge weights for BB257 -> BB186 to [0 .. 3.402823e+38] Setting edge weights for BB257 -> BB138 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB257 to [0 .. 3.402823e+38] Setting edge weights for BB137 -> BB138 to [0 .. 3.402823e+38] Lowering switch BB137: using jump table expansion LowerCast for: [004248] ---------U- * CAST long <- ulong <- uint Lowering switch BB138, 6 cases lvaGrabTemp returning 185 (V185 rat3) called for ReplaceWithLclVar is creating a new local variable. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) [004252] DA--------- * STORE_LCL_VAR int V185 rat3 ReplaceWithLclVar created store : [004252] DA--------- * STORE_LCL_VAR int V185 rat3 lowering store lcl var/field (before): N001 ( 1, 1) [000597] ----------- t597 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] -c--------- t598 = CNS_INT int -44 $d7 /--* t597 int +--* t598 int N003 ( 3, 4) [000599] ----------- t599 = * ADD int /--* t599 int [004252] DA--------- * STORE_LCL_VAR int V185 rat3 lowering store lcl var/field (after): N001 ( 1, 1) [000597] ----------- t597 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] -c--------- t598 = CNS_INT int -44 $d7 /--* t597 int +--* t598 int N003 ( 3, 4) [000599] ----------- t599 = * ADD int /--* t599 int [004252] DA--------- * STORE_LCL_VAR int V185 rat3 New Basic Block BB258 [0367] created. Setting edge weights for BB258 -> BB245 to [0 .. 3.402823e+38] Setting edge weights for BB258 -> BB242 to [0 .. 3.402823e+38] Setting edge weights for BB258 -> BB171 to [0 .. 3.402823e+38] Setting edge weights for BB258 -> BB145 to [0 .. 3.402823e+38] Setting edge weights for BB258 -> BB139 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB258 to [0 .. 3.402823e+38] Setting edge weights for BB138 -> BB139 to [0 .. 3.402823e+38] Lowering switch BB138: using jump table expansion LowerCast for: [004259] ---------U- * CAST long <- ulong <- uint Addressing mode: Base N001 ( 1, 1) [000586] ----------- * LCL_VAR ref V03 arg3 u:1 $180 + 136 Removing unused node: N002 ( 1, 2) [002848] -c--------- * CNS_INT long 136 Fseq[] $20e New addressing mode node: N003 ( 3, 4) [002849] ----------- * LEA(b+136) byref lowering store lcl var/field (before): N001 ( 1, 1) [000586] ----------- t586 = LCL_VAR ref V03 arg3 u:1 $180 /--* t586 ref N003 ( 3, 4) [002849] -c--------- t2849 = * LEA(b+136) byref /--* t2849 byref N004 ( 4, 3) [002066] ---XG------ t2066 = * IND ref /--* t2066 ref N006 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000586] ----------- t586 = LCL_VAR ref V03 arg3 u:1 $180 /--* t586 ref N003 ( 3, 4) [002849] -c--------- t2849 = * LEA(b+136) byref /--* t2849 byref N004 ( 4, 3) [002066] ---XG------ t2066 = * IND ref /--* t2066 ref N006 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000731] ----------- t731 = LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] -c--------- t732 = CNS_INT int 1 $c1 /--* t731 int +--* t732 int N003 ( 3, 4) [000733] ----------- t733 = * ADD int $a88 /--* t733 int N005 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [000731] ----------- t731 = LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] -c--------- t732 = CNS_INT int 1 $c1 /--* t731 int +--* t732 int N003 ( 3, 4) [000733] ----------- t733 = * ADD int $a88 /--* t733 int N005 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 lowering store lcl var/field (before): N001 ( 1, 2) [000747] ----------- t747 = CNS_INT int 0 $c0 /--* t747 int N003 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 lowering store lcl var/field (after): N001 ( 1, 2) [000747] -c--------- t747 = CNS_INT int 0 $c0 /--* t747 int N003 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 lowering store lcl var/field (before): N001 ( 1, 2) [000740] ----------- t740 = CNS_INT int 48 $d8 /--* t740 int N003 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 lowering store lcl var/field (after): N001 ( 1, 2) [000740] ----------- t740 = CNS_INT int 48 $d8 /--* t740 int N003 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 LowerCast for: N002 ( 2, 3) [002850] ----------- * CAST int <- ushort <- int $a8a lowering store lcl var/field (before): N001 ( 1, 1) [000744] ----------- t744 = LCL_VAR int V58 tmp18 u:1 (last use) $2bd /--* t744 int N002 ( 2, 3) [002850] ----------- t2850 = * CAST int <- ushort <- int $a8a /--* t2850 int N004 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000744] ----------- t744 = LCL_VAR int V58 tmp18 u:1 (last use) $2bd /--* t744 int N002 ( 2, 3) [002850] ----------- t2850 = * CAST int <- ushort <- int $a8a /--* t2850 int N004 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 lowering store lcl var/field (before): N001 ( 1, 2) [000727] ----------- t727 = CNS_INT int 0 $c0 /--* t727 int N003 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 lowering store lcl var/field (after): N001 ( 1, 2) [000727] -c--------- t727 = CNS_INT int 0 $c0 /--* t727 int N003 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 lowering store lcl var/field (before): N001 ( 1, 2) [000723] ----------- t723 = CNS_INT int 48 $d8 /--* t723 int N003 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 lowering store lcl var/field (after): N001 ( 1, 2) [000723] ----------- t723 = CNS_INT int 48 $d8 /--* t723 int N003 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 lowering store lcl var/field (before): N001 ( 1, 1) [000648] ----------- t648 = LCL_VAR long V36 loc32 u:3 $901 /--* t648 long N003 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000648] ----------- t648 = LCL_VAR long V36 loc32 u:3 $901 /--* t648 long N003 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000649] ----------- t649 = LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] -c--------- t651 = CNS_INT long 1 $204 /--* t649 long +--* t651 long N003 ( 3, 4) [000652] ----------- t652 = * ADD long $3fb /--* t652 long N005 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 lowering store lcl var/field (after): N001 ( 1, 1) [000649] ----------- t649 = LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] -c--------- t651 = CNS_INT long 1 $204 /--* t649 long +--* t651 long N003 ( 3, 4) [000652] ----------- t652 = * ADD long $3fb /--* t652 long N005 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 lowering store lcl var/field (before): N001 ( 1, 1) [000657] ----------- t657 = LCL_VAR long V56 tmp16 u:1 (last use) $901 /--* t657 long N002 ( 4, 3) [000658] ---XG------ t658 = * IND ubyte /--* t658 ubyte N004 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000657] ----------- t657 = LCL_VAR long V56 tmp16 u:1 (last use) $901 /--* t657 long N002 ( 4, 3) [000658] ---XG------ t658 = * IND ubyte /--* t658 ubyte N004 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 LowerCast for: N002 ( 2, 3) [002851] ----------- * CAST int <- ushort <- int $a87 lowering store lcl var/field (before): N001 ( 1, 1) [000662] ----------- t662 = LCL_VAR int V57 tmp17 u:1 (last use) $2bc /--* t662 int N002 ( 2, 3) [002851] ----------- t2851 = * CAST int <- ushort <- int $a87 /--* t2851 int N004 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000662] ----------- t662 = LCL_VAR int V57 tmp17 u:1 (last use) $2bc /--* t662 int N002 ( 2, 3) [002851] ----------- t2851 = * CAST int <- ushort <- int $a87 /--* t2851 int N004 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 Addressing mode: Base N001 ( 1, 1) [000674] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [002852] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002853] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000674] ----------- t674 = LCL_VAR byref V00 arg0 u:1 $100 /--* t674 byref N003 ( 3, 4) [002853] -c--------- t2853 = * LEA(b+8) byref /--* t2853 byref N004 ( 4, 3) [001903] ---XG------ t1903 = * IND int /--* t1903 int N006 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000674] ----------- t674 = LCL_VAR byref V00 arg0 u:1 $100 /--* t674 byref N003 ( 3, 4) [002853] -c--------- t2853 = * LEA(b+8) byref /--* t2853 byref N004 ( 4, 3) [001903] ---XG------ t1903 = * IND int /--* t1903 int N006 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 Addressing mode: Base N002 ( 1, 1) [001907] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [002856] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [002857] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [002861] ----------- t2861 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] -c--------- t2862 = CNS_INT long 16 $200 /--* t2861 byref +--* t2862 long N003 ( 3, 4) [002863] -----O----- t2863 = * ADD byref $25c /--* t2863 byref N005 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002861] ----------- t2861 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] -c--------- t2862 = CNS_INT long 16 $200 /--* t2861 byref +--* t2862 long N003 ( 3, 4) [002863] -----O----- t2863 = * ADD byref $25c /--* t2863 byref N005 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 Addressing mode: Base N002 ( 1, 1) [001922] ----------- * LCL_VAR byref V100 tmp60 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [002865] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002866] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [001925] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [001928] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [001927] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [001929] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [001934] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [002868] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [002869] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [001913] ----------- t1913 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000675] ----------- t675 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 N003 ( 2, 8) [002870] H---------- t2870 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t1913 byref this in x0 +--* t675 int arg2 in x1 +--* t2870 long r2r cell in x11 N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [001913] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004262] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [000675] ----------- * LCL_VAR int V18 loc14 u:2 (last use) $5c9 new node is : [004263] ----------- * PUTARG_REG int REG x1 lowering arg : N003 ( 2, 8) [002870] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 new node is : [004264] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [001913] ----------- t1913 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1913 byref [004262] ----------- t4262 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000675] ----------- t675 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 /--* t675 int [004263] ----------- t4263 = * PUTARG_REG int REG x1 N003 ( 2, 8) [002870] H---------- t2870 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2870 long [004264] ----------- t4264 = * PUTARG_REG long REG x11 /--* t4262 byref this in x0 +--* t4263 int arg2 in x1 +--* t4264 long r2r cell in x11 N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void Lowered `AND` chain: N007 ( 13, 9) [003746] J------N--- * AND int N003 ( 6, 4) [000679] -c-----N--- +--* EQ int $70a N001 ( 1, 1) [000677] ----------- | +--* LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] -c--------- | \--* CNS_INT int 0 $c0 N006 ( 6, 4) [000683] -c-----N--- \--* LE int $a93 N004 ( 1, 1) [000681] ----------- +--* LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] -c--------- \--* CNS_INT int 1 $c1 LowerCast for: N006 ( 2, 3) [000698] ---------U- * CAST long <- uint $ac0 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N004 ( 1, 1) [000701] ----------- * LCL_VAR byref V143 tmp103 u:2 $385 + Index * 1 + 0 N008 ( 4, 6) [000700] ----------- * BFIZ long New addressing mode node: N009 ( 6, 8) [000702] ----------- * LEA(b+(i*1)+0) byref Lowered `AND` chain: N019 ( 28, 28) [003748] J--XGO-N--- * AND int N015 ( 21, 23) [000707] Nc-XGO-N-U- +--* NE int N013 ( 16, 21) [000706] ---XGO----- | +--* ADD int N010 ( 8, 9) [002871] ---XGO----- | | +--* IND int N009 ( 6, 8) [000702] -c--------- | | | \--* LEA(b+(i*1)+0) byref N004 ( 1, 1) [000701] ----------- | | | +--* LCL_VAR byref V143 tmp103 u:2 $385 N008 ( 4, 6) [000700] -c--------- | | | \--* BFIZ long N006 ( 2, 3) [000698] -c-------U- | | | +--* CAST long <- uint $ac0 N005 ( 1, 1) [000693] ----------- | | | | \--* LCL_VAR int V20 loc16 u:4 $2b3 N007 ( 1, 2) [000699] -c--------- | | | \--* CNS_INT long 2 $20a N012 ( 1, 2) [000705] -c--------- | | \--* CNS_INT int 1 $c1 N014 ( 1, 1) [000689] ----------- | \--* LCL_VAR int V08 loc4 u:3 $2b5 N018 ( 6, 4) [000687] -c-----N--- \--* LT int $a94 N016 ( 1, 1) [000685] ----------- +--* LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] -c--------- \--* CNS_INT int 0 $c0 Addressing mode: Base N001 ( 1, 1) [000710] ----------- * LCL_VAR ref V03 arg3 u:1 $180 + 56 Removing unused node: N002 ( 1, 2) [002872] -c--------- * CNS_INT long 56 Fseq[] $209 New addressing mode node: N003 ( 3, 4) [002873] ----------- * LEA(b+56) byref lowering store lcl var/field (before): N001 ( 1, 1) [000710] ----------- t710 = LCL_VAR ref V03 arg3 u:1 $180 /--* t710 ref N003 ( 3, 4) [002873] -c--------- t2873 = * LEA(b+56) byref /--* t2873 byref N004 ( 4, 3) [001946] ---XG------ t1946 = * IND ref /--* t1946 ref N006 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000710] ----------- t710 = LCL_VAR ref V03 arg3 u:1 $180 /--* t710 ref N003 ( 3, 4) [002873] -c--------- t2873 = * LEA(b+56) byref /--* t2873 byref N004 ( 4, 3) [001946] ---XG------ t1946 = * IND ref /--* t1946 ref N006 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 Addressing mode: Base N001 ( 1, 1) [000709] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [002874] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002875] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000709] ----------- t709 = LCL_VAR byref V00 arg0 u:1 $100 /--* t709 byref N003 ( 3, 4) [002875] -c--------- t2875 = * LEA(b+8) byref /--* t2875 byref N004 ( 4, 3) [001952] n---GO----- t1952 = * IND int /--* t1952 int N006 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000709] ----------- t709 = LCL_VAR byref V00 arg0 u:1 $100 /--* t709 byref N003 ( 3, 4) [002875] -c--------- t2875 = * LEA(b+8) byref /--* t2875 byref N004 ( 4, 3) [001952] n---GO----- t1952 = * IND int /--* t1952 int N006 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 Addressing mode: Base N001 ( 1, 1) [001955] ----------- * LCL_VAR ref V102 tmp62 u:1 + 8 Removing unused node: [004169] -c--------- * CNS_INT long 8 New addressing mode node: [004170] ----------- * LEA(b+8) byref Addressing mode: Base N006 ( 1, 1) [001964] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N007 ( 1, 2) [002878] -c--------- * CNS_INT long 24 $20c New addressing mode node: N008 ( 3, 4) [002879] ----------- * LEA(b+24) byref Lowered `AND` chain: N011 ( 18, 12) [003750] J--XGO-N--- * AND int N004 ( 8, 6) [001958] Nc-X---N-U- +--* NE int N002 ( 3, 3) [001956] ---X------- | +--* IND int [004170] -c--------- | | \--* LEA(b+8) byref N001 ( 1, 1) [001955] ----------- | | \--* LCL_VAR ref V102 tmp62 u:1 N003 ( 1, 2) [001957] -c--------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [001968] Nc--GO-N-U- \--* GE int N005 ( 1, 1) [001963] ----------- +--* LCL_VAR int V103 tmp63 u:1 N009 ( 4, 3) [002002] n---GO----- \--* IND int N008 ( 3, 4) [002879] -c--------- \--* LEA(b+24) byref N006 ( 1, 1) [001964] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 lowering store lcl var/field (before): N001 ( 1, 1) [002883] ----------- t2883 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] -c--------- t2884 = CNS_INT long 16 $200 /--* t2883 byref +--* t2884 long N003 ( 3, 4) [002885] -----O----- t2885 = * ADD byref $25c /--* t2885 byref N005 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002883] ----------- t2883 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] -c--------- t2884 = CNS_INT long 16 $200 /--* t2883 byref +--* t2884 long N003 ( 3, 4) [002885] -----O----- t2885 = * ADD byref $25c /--* t2885 byref N005 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 Addressing mode: Base N002 ( 1, 1) [001977] ----------- * LCL_VAR byref V104 tmp64 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [002887] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002888] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [001980] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N017 ( 1, 1) [001986] ----------- * LCL_VAR ref V102 tmp62 u:1 + 8 Removing unused node: [004171] -c--------- * CNS_INT long 8 New addressing mode node: [004172] ----------- * LEA(b+8) byref Addressing mode: Base N020 ( 1, 1) [002890] ----------- * LCL_VAR ref V102 tmp62 u:1 (last use) + 12 Removing unused node: N021 ( 1, 2) [002896] -c--------- * CNS_INT long 12 $20d New addressing mode node: N022 ( 1, 1) [002897] ----------- * LEA(b+12) byref Addressing mode: Base N004 ( 1, 1) [001992] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [002903] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [002904] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [001960] ----------- t1960 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [001961] ----------- t1961 = LCL_VAR ref V102 tmp62 u:1 (last use) N003 ( 2, 8) [002905] H---------- t2905 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t1960 byref this in x0 +--* t1961 ref arg2 in x1 +--* t2905 long r2r cell in x11 N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [001960] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004265] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [001961] ----------- * LCL_VAR ref V102 tmp62 u:1 (last use) new node is : [004266] ----------- * PUTARG_REG ref REG x1 lowering arg : N003 ( 2, 8) [002905] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn $4f new node is : [004267] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [001960] ----------- t1960 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1960 byref [004265] ----------- t4265 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001961] ----------- t1961 = LCL_VAR ref V102 tmp62 u:1 (last use) /--* t1961 ref [004266] ----------- t4266 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002905] H---------- t2905 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2905 long [004267] ----------- t4267 = * PUTARG_REG long REG x11 /--* t4265 byref this in x0 +--* t4266 ref arg2 in x1 +--* t4267 long r2r cell in x11 N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000714] ----------- t714 = LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] -c--------- t715 = CNS_INT int -1 $c4 /--* t714 int +--* t715 int N003 ( 3, 4) [000716] ----------- t716 = * ADD int $ab7 /--* t716 int N005 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 lowering store lcl var/field (after): N001 ( 1, 1) [000714] ----------- t714 = LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] -c--------- t715 = CNS_INT int -1 $c4 /--* t714 int +--* t715 int N003 ( 3, 4) [000716] ----------- t716 = * ADD int $ab7 /--* t716 int N005 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 lowering store lcl var/field (before): N001 ( 1, 1) [000669] ----------- t669 = LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] -c--------- t670 = CNS_INT int -1 $c4 /--* t669 int +--* t670 int N003 ( 3, 4) [000671] ----------- t671 = * ADD int $ab9 /--* t671 int N005 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000669] ----------- t669 = LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] -c--------- t670 = CNS_INT int -1 $c4 /--* t669 int +--* t670 int N003 ( 3, 4) [000671] ----------- t671 = * ADD int $ab9 /--* t671 int N005 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 Lowered `AND` chain: N008 ( 16, 10) [003752] J--XG--N--- * AND int N003 ( 6, 3) [000627] -c-----N--- +--* GE int $abe N001 ( 1, 1) [000625] ----------- | +--* LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- | \--* LCL_VAR int V04 loc0 u:2 $28a N007 ( 9, 6) [000632] -c-XG--N--- \--* EQ int N005 ( 4, 3) [000630] ---XG------ +--* IND ubyte N004 ( 1, 1) [000629] ----------- | \--* LCL_VAR long V36 loc32 u:3 $901 N006 ( 1, 2) [000631] -c--------- \--* CNS_INT int 0 $c0 Addressing mode: Base N001 ( 1, 1) [000618] ----------- * LCL_VAR ref V03 arg3 u:1 $180 + 48 Removing unused node: N002 ( 1, 2) [002906] -c--------- * CNS_INT long 48 Fseq[] $20f New addressing mode node: N003 ( 3, 4) [002907] ----------- * LEA(b+48) byref lowering store lcl var/field (before): N001 ( 1, 1) [000618] ----------- t618 = LCL_VAR ref V03 arg3 u:1 $180 /--* t618 ref N003 ( 3, 4) [002907] -c--------- t2907 = * LEA(b+48) byref /--* t2907 byref N004 ( 4, 3) [002006] ---XG------ t2006 = * IND ref /--* t2006 ref N006 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000618] ----------- t618 = LCL_VAR ref V03 arg3 u:1 $180 /--* t618 ref N003 ( 3, 4) [002907] -c--------- t2907 = * LEA(b+48) byref /--* t2907 byref N004 ( 4, 3) [002006] ---XG------ t2006 = * IND ref /--* t2006 ref N006 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 Addressing mode: Base N001 ( 1, 1) [000617] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [002908] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002909] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000617] ----------- t617 = LCL_VAR byref V00 arg0 u:1 $100 /--* t617 byref N003 ( 3, 4) [002909] -c--------- t2909 = * LEA(b+8) byref /--* t2909 byref N004 ( 4, 3) [002012] ---XG------ t2012 = * IND int /--* t2012 int N006 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000617] ----------- t617 = LCL_VAR byref V00 arg0 u:1 $100 /--* t617 byref N003 ( 3, 4) [002909] -c--------- t2909 = * LEA(b+8) byref /--* t2909 byref N004 ( 4, 3) [002012] ---XG------ t2012 = * IND int /--* t2012 int N006 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 Addressing mode: Base N001 ( 1, 1) [002015] ----------- * LCL_VAR ref V106 tmp66 u:1 + 8 Removing unused node: [004173] -c--------- * CNS_INT long 8 New addressing mode node: [004174] ----------- * LEA(b+8) byref Addressing mode: Base N006 ( 1, 1) [002024] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N007 ( 1, 2) [002912] -c--------- * CNS_INT long 24 $20c New addressing mode node: N008 ( 3, 4) [002913] ----------- * LEA(b+24) byref Lowered `AND` chain: N011 ( 18, 12) [003754] J--XGO-N--- * AND int N004 ( 8, 6) [002018] Nc-X---N-U- +--* NE int N002 ( 3, 3) [002016] ---X------- | +--* IND int [004174] -c--------- | | \--* LEA(b+8) byref N001 ( 1, 1) [002015] ----------- | | \--* LCL_VAR ref V106 tmp66 u:1 N003 ( 1, 2) [002017] -c--------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002028] Nc--GO-N-U- \--* GE int N005 ( 1, 1) [002023] ----------- +--* LCL_VAR int V107 tmp67 u:1 N009 ( 4, 3) [002062] n---GO----- \--* IND int N008 ( 3, 4) [002913] -c--------- \--* LEA(b+24) byref N006 ( 1, 1) [002024] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 lowering store lcl var/field (before): N001 ( 1, 1) [002917] ----------- t2917 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] -c--------- t2918 = CNS_INT long 16 $200 /--* t2917 byref +--* t2918 long N003 ( 3, 4) [002919] -----O----- t2919 = * ADD byref $25c /--* t2919 byref N005 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002917] ----------- t2917 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] -c--------- t2918 = CNS_INT long 16 $200 /--* t2917 byref +--* t2918 long N003 ( 3, 4) [002919] -----O----- t2919 = * ADD byref $25c /--* t2919 byref N005 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 Addressing mode: Base N002 ( 1, 1) [002037] ----------- * LCL_VAR byref V108 tmp68 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [002921] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002922] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002040] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N017 ( 1, 1) [002046] ----------- * LCL_VAR ref V106 tmp66 u:1 + 8 Removing unused node: [004175] -c--------- * CNS_INT long 8 New addressing mode node: [004176] ----------- * LEA(b+8) byref Addressing mode: Base N020 ( 1, 1) [002924] ----------- * LCL_VAR ref V106 tmp66 u:1 (last use) + 12 Removing unused node: N021 ( 1, 2) [002930] -c--------- * CNS_INT long 12 $20d New addressing mode node: N022 ( 1, 1) [002931] ----------- * LEA(b+12) byref Addressing mode: Base N004 ( 1, 1) [002052] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [002937] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [002938] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002020] ----------- t2020 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002021] ----------- t2021 = LCL_VAR ref V106 tmp66 u:1 (last use) N003 ( 2, 8) [002939] H---------- t2939 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2020 byref this in x0 +--* t2021 ref arg2 in x1 +--* t2939 long r2r cell in x11 N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002020] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004268] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [002021] ----------- * LCL_VAR ref V106 tmp66 u:1 (last use) new node is : [004269] ----------- * PUTARG_REG ref REG x1 lowering arg : N003 ( 2, 8) [002939] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn $4f new node is : [004270] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002020] ----------- t2020 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2020 byref [004268] ----------- t4268 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002021] ----------- t2021 = LCL_VAR ref V106 tmp66 u:1 (last use) /--* t2021 ref [004269] ----------- t4269 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002939] H---------- t2939 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2939 long [004270] ----------- t4270 = * PUTARG_REG long REG x11 /--* t4268 byref this in x0 +--* t4269 ref arg2 in x1 +--* t4270 long r2r cell in x11 N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void lowering store lcl var/field (before): N001 ( 1, 2) [002940] ----------- t2940 = CNS_INT int 1 $c1 /--* t2940 int N003 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 lowering store lcl var/field (after): N001 ( 1, 2) [002940] ----------- t2940 = CNS_INT int 1 $c1 /--* t2940 int N003 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 Addressing mode: Base N001 ( 1, 1) [000585] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [002941] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002942] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000585] ----------- t585 = LCL_VAR byref V00 arg0 u:1 $100 /--* t585 byref N003 ( 3, 4) [002942] -c--------- t2942 = * LEA(b+8) byref /--* t2942 byref N004 ( 4, 3) [002072] ---XG------ t2072 = * IND int /--* t2072 int N006 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000585] ----------- t585 = LCL_VAR byref V00 arg0 u:1 $100 /--* t585 byref N003 ( 3, 4) [002942] -c--------- t2942 = * LEA(b+8) byref /--* t2942 byref N004 ( 4, 3) [002072] ---XG------ t2072 = * IND int /--* t2072 int N006 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 Addressing mode: Base N001 ( 1, 1) [002075] ----------- * LCL_VAR ref V110 tmp70 u:1 + 8 Removing unused node: [004177] -c--------- * CNS_INT long 8 New addressing mode node: [004178] ----------- * LEA(b+8) byref Addressing mode: Base N006 ( 1, 1) [002084] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N007 ( 1, 2) [002945] -c--------- * CNS_INT long 24 $20c New addressing mode node: N008 ( 3, 4) [002946] ----------- * LEA(b+24) byref Lowered `AND` chain: N011 ( 18, 12) [003756] J--XGO-N--- * AND int N004 ( 8, 6) [002078] Nc-X---N-U- +--* NE int N002 ( 3, 3) [002076] ---X------- | +--* IND int [004178] -c--------- | | \--* LEA(b+8) byref N001 ( 1, 1) [002075] ----------- | | \--* LCL_VAR ref V110 tmp70 u:1 N003 ( 1, 2) [002077] -c--------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002088] Nc--GO-N-U- \--* GE int N005 ( 1, 1) [002083] ----------- +--* LCL_VAR int V111 tmp71 u:1 N009 ( 4, 3) [002122] n---GO----- \--* IND int N008 ( 3, 4) [002946] -c--------- \--* LEA(b+24) byref N006 ( 1, 1) [002084] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 lowering store lcl var/field (before): N001 ( 1, 1) [002950] ----------- t2950 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] -c--------- t2951 = CNS_INT long 16 $200 /--* t2950 byref +--* t2951 long N003 ( 3, 4) [002952] -----O----- t2952 = * ADD byref $25c /--* t2952 byref N005 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002950] ----------- t2950 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] -c--------- t2951 = CNS_INT long 16 $200 /--* t2950 byref +--* t2951 long N003 ( 3, 4) [002952] -----O----- t2952 = * ADD byref $25c /--* t2952 byref N005 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 Addressing mode: Base N002 ( 1, 1) [002097] ----------- * LCL_VAR byref V112 tmp72 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [002954] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002955] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002100] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N017 ( 1, 1) [002106] ----------- * LCL_VAR ref V110 tmp70 u:1 + 8 Removing unused node: [004179] -c--------- * CNS_INT long 8 New addressing mode node: [004180] ----------- * LEA(b+8) byref Addressing mode: Base N020 ( 1, 1) [002957] ----------- * LCL_VAR ref V110 tmp70 u:1 (last use) + 12 Removing unused node: N021 ( 1, 2) [002963] -c--------- * CNS_INT long 12 $20d New addressing mode node: N022 ( 1, 1) [002964] ----------- * LEA(b+12) byref Addressing mode: Base N004 ( 1, 1) [002112] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [002970] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [002971] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002080] ----------- t2080 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002081] ----------- t2081 = LCL_VAR ref V110 tmp70 u:1 (last use) N003 ( 2, 8) [002972] H---------- t2972 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2080 byref this in x0 +--* t2081 ref arg2 in x1 +--* t2972 long r2r cell in x11 N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002080] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004271] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [002081] ----------- * LCL_VAR ref V110 tmp70 u:1 (last use) new node is : [004272] ----------- * PUTARG_REG ref REG x1 lowering arg : N003 ( 2, 8) [002972] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn $4f new node is : [004273] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002080] ----------- t2080 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2080 byref [004271] ----------- t4271 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002081] ----------- t2081 = LCL_VAR ref V110 tmp70 u:1 (last use) /--* t2081 ref [004272] ----------- t4272 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002972] H---------- t2972 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2972 long [004273] ----------- t4273 = * PUTARG_REG long REG x11 /--* t4271 byref this in x0 +--* t4272 ref arg2 in x1 +--* t4273 long r2r cell in x11 N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void Addressing mode: Base N001 ( 1, 1) [000635] ----------- * LCL_VAR ref V03 arg3 u:1 $180 + 128 Removing unused node: N002 ( 1, 2) [002973] -c--------- * CNS_INT long 128 Fseq[] $210 New addressing mode node: N003 ( 3, 4) [002974] ----------- * LEA(b+128) byref lowering store lcl var/field (before): N001 ( 1, 1) [000635] ----------- t635 = LCL_VAR ref V03 arg3 u:1 $180 /--* t635 ref N003 ( 3, 4) [002974] -c--------- t2974 = * LEA(b+128) byref /--* t2974 byref N004 ( 4, 3) [002126] ---XG------ t2126 = * IND ref /--* t2126 ref N006 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000635] ----------- t635 = LCL_VAR ref V03 arg3 u:1 $180 /--* t635 ref N003 ( 3, 4) [002974] -c--------- t2974 = * LEA(b+128) byref /--* t2974 byref N004 ( 4, 3) [002126] ---XG------ t2126 = * IND ref /--* t2126 ref N006 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 Addressing mode: Base N001 ( 1, 1) [000634] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [002975] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [002976] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000634] ----------- t634 = LCL_VAR byref V00 arg0 u:1 $100 /--* t634 byref N003 ( 3, 4) [002976] -c--------- t2976 = * LEA(b+8) byref /--* t2976 byref N004 ( 4, 3) [002132] ---XG------ t2132 = * IND int /--* t2132 int N006 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000634] ----------- t634 = LCL_VAR byref V00 arg0 u:1 $100 /--* t634 byref N003 ( 3, 4) [002976] -c--------- t2976 = * LEA(b+8) byref /--* t2976 byref N004 ( 4, 3) [002132] ---XG------ t2132 = * IND int /--* t2132 int N006 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 Addressing mode: Base N001 ( 1, 1) [002135] ----------- * LCL_VAR ref V114 tmp74 u:1 + 8 Removing unused node: [004181] -c--------- * CNS_INT long 8 New addressing mode node: [004182] ----------- * LEA(b+8) byref Addressing mode: Base N006 ( 1, 1) [002144] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N007 ( 1, 2) [002979] -c--------- * CNS_INT long 24 $20c New addressing mode node: N008 ( 3, 4) [002980] ----------- * LEA(b+24) byref Lowered `AND` chain: N011 ( 18, 12) [003758] J--XGO-N--- * AND int N004 ( 8, 6) [002138] Nc-X---N-U- +--* NE int N002 ( 3, 3) [002136] ---X------- | +--* IND int [004182] -c--------- | | \--* LEA(b+8) byref N001 ( 1, 1) [002135] ----------- | | \--* LCL_VAR ref V114 tmp74 u:1 N003 ( 1, 2) [002137] -c--------- | \--* CNS_INT int 1 $c1 N010 ( 9, 5) [002148] Nc--GO-N-U- \--* GE int N005 ( 1, 1) [002143] ----------- +--* LCL_VAR int V115 tmp75 u:1 N009 ( 4, 3) [002182] n---GO----- \--* IND int N008 ( 3, 4) [002980] -c--------- \--* LEA(b+24) byref N006 ( 1, 1) [002144] ----------- \--* LCL_VAR byref V00 arg0 u:1 $100 lowering store lcl var/field (before): N001 ( 1, 1) [002984] ----------- t2984 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] -c--------- t2985 = CNS_INT long 16 $200 /--* t2984 byref +--* t2985 long N003 ( 3, 4) [002986] -----O----- t2986 = * ADD byref $25c /--* t2986 byref N005 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [002984] ----------- t2984 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] -c--------- t2985 = CNS_INT long 16 $200 /--* t2984 byref +--* t2985 long N003 ( 3, 4) [002986] -----O----- t2986 = * ADD byref $25c /--* t2986 byref N005 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 Addressing mode: Base N002 ( 1, 1) [002157] ----------- * LCL_VAR byref V116 tmp76 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [002988] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [002989] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002160] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N017 ( 1, 1) [002166] ----------- * LCL_VAR ref V114 tmp74 u:1 + 8 Removing unused node: [004183] -c--------- * CNS_INT long 8 New addressing mode node: [004184] ----------- * LEA(b+8) byref Addressing mode: Base N020 ( 1, 1) [002991] ----------- * LCL_VAR ref V114 tmp74 u:1 (last use) + 12 Removing unused node: N021 ( 1, 2) [002997] -c--------- * CNS_INT long 12 $20d New addressing mode node: N022 ( 1, 1) [002998] ----------- * LEA(b+12) byref Addressing mode: Base N004 ( 1, 1) [002172] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [003004] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [003005] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002140] ----------- t2140 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002141] ----------- t2141 = LCL_VAR ref V114 tmp74 u:1 (last use) N003 ( 2, 8) [003006] H---------- t3006 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2140 byref this in x0 +--* t2141 ref arg2 in x1 +--* t3006 long r2r cell in x11 N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002140] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004274] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [002141] ----------- * LCL_VAR ref V114 tmp74 u:1 (last use) new node is : [004275] ----------- * PUTARG_REG ref REG x1 lowering arg : N003 ( 2, 8) [003006] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn $4f new node is : [004276] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002140] ----------- t2140 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2140 byref [004274] ----------- t4274 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002141] ----------- t2141 = LCL_VAR ref V114 tmp74 u:1 (last use) /--* t2141 ref [004275] ----------- t4275 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [003006] H---------- t3006 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t3006 long [004276] ----------- t4276 = * PUTARG_REG long REG x11 /--* t4274 byref this in x0 +--* t4275 ref arg2 in x1 +--* t4276 long r2r cell in x11 N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000805] ----------- t805 = LCL_VAR int V16 loc12 u:13 $b04 /--* t805 int N003 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000805] ----------- t805 = LCL_VAR int V16 loc12 u:13 $b04 /--* t805 int N003 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000806] ----------- t806 = LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] -c--------- t807 = CNS_INT int 1 $c1 /--* t806 int +--* t807 int N003 ( 3, 4) [000808] ----------- t808 = * ADD int $bad /--* t808 int N005 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 lowering store lcl var/field (after): N001 ( 1, 1) [000806] ----------- t806 = LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] -c--------- t807 = CNS_INT int 1 $c1 /--* t806 int +--* t807 int N003 ( 3, 4) [000808] ----------- t808 = * ADD int $bad /--* t808 int N005 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 lowering store lcl var/field (before): N001 ( 1, 1) [003629] ----------- t3629 = LCL_VAR int V172 cse1 /--* t3629 int N003 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003629] ----------- t3629 = LCL_VAR int V172 cse1 /--* t3629 int N003 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 Addressing mode: Base N001 ( 1, 1) [000803] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [003007] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [003008] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000803] ----------- t803 = LCL_VAR byref V00 arg0 u:1 $100 /--* t803 byref N003 ( 3, 4) [003008] -c--------- t3008 = * LEA(b+8) byref /--* t3008 byref N004 ( 4, 3) [002186] ---XG------ t2186 = * IND int /--* t2186 int N006 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000803] ----------- t803 = LCL_VAR byref V00 arg0 u:1 $100 /--* t803 byref N003 ( 3, 4) [003008] -c--------- t3008 = * LEA(b+8) byref /--* t3008 byref N004 ( 4, 3) [002186] ---XG------ t2186 = * IND int /--* t2186 int N006 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 Addressing mode: Base N002 ( 1, 1) [002190] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [003011] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [003012] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [003016] ----------- t3016 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] -c--------- t3017 = CNS_INT long 16 $200 /--* t3016 byref +--* t3017 long N003 ( 3, 4) [003018] -----O----- t3018 = * ADD byref $25c /--* t3018 byref N005 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003016] ----------- t3016 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] -c--------- t3017 = CNS_INT long 16 $200 /--* t3016 byref +--* t3017 long N003 ( 3, 4) [003018] -----O----- t3018 = * ADD byref $25c /--* t3018 byref N005 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 Addressing mode: Base N002 ( 1, 1) [002206] ----------- * LCL_VAR byref V120 tmp80 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [003020] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [003021] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002209] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [002212] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [002211] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [002213] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [002218] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [003023] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [003024] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002196] ----------- t2196 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002197] ----------- t2197 = LCL_VAR int V119 tmp79 u:1 (last use) N003 ( 2, 8) [003025] H---------- t3025 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2196 byref this in x0 +--* t2197 int arg2 in x1 +--* t3025 long r2r cell in x11 N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002196] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004277] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [002197] ----------- * LCL_VAR int V119 tmp79 u:1 (last use) new node is : [004278] ----------- * PUTARG_REG int REG x1 lowering arg : N003 ( 2, 8) [003025] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 new node is : [004279] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002196] ----------- t2196 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2196 byref [004277] ----------- t4277 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002197] ----------- t2197 = LCL_VAR int V119 tmp79 u:1 (last use) /--* t2197 int [004278] ----------- t4278 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003025] H---------- t3025 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3025 long [004279] ----------- t4279 = * PUTARG_REG long REG x11 /--* t4277 byref this in x0 +--* t4278 int arg2 in x1 +--* t4279 long r2r cell in x11 N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void LowerCast for: N003 ( 2, 3) [000783] ----------- * CAST long <- int $aca Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000781] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [000786] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [000787] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [000781] ----------- t781 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000782] ----------- t782 = LCL_VAR int V16 loc12 u:13 $b04 /--* t782 int N003 ( 2, 3) [000783] -c--------- t783 = * CAST long <- int $aca N004 ( 1, 2) [000785] -c--------- t785 = CNS_INT long 1 $204 /--* t783 long +--* t785 long N005 ( 4, 6) [000786] -c--------- t786 = * BFIZ long /--* t781 long +--* t786 long N006 ( 6, 8) [000787] -c--------- t787 = * LEA(b+(i*1)+0) long /--* t787 long N007 ( 9, 10) [000788] ---XG------ t788 = * IND ushort /--* t788 ushort N009 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 lowering store lcl var/field (after): N001 ( 1, 1) [000781] ----------- t781 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000782] ----------- t782 = LCL_VAR int V16 loc12 u:13 $b04 /--* t782 int N003 ( 2, 3) [000783] -c--------- t783 = * CAST long <- int $aca N004 ( 1, 2) [000785] -c--------- t785 = CNS_INT long 1 $204 /--* t783 long +--* t785 long N005 ( 4, 6) [000786] -c--------- t786 = * BFIZ long /--* t781 long +--* t786 long N006 ( 6, 8) [000787] -c--------- t787 = * LEA(b+(i*1)+0) long /--* t787 long N007 ( 9, 10) [000788] ---XG------ t788 = * IND ushort /--* t788 ushort N009 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 LowerCast for: N003 ( 2, 3) [000767] ----------- * CAST long <- int $aca Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000765] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [000770] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [000771] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [000765] ----------- t765 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000766] ----------- t766 = LCL_VAR int V16 loc12 u:13 $b04 /--* t766 int N003 ( 2, 3) [000767] -c--------- t767 = * CAST long <- int $aca N004 ( 1, 2) [000769] -c--------- t769 = CNS_INT long 1 $204 /--* t767 long +--* t769 long N005 ( 4, 6) [000770] -c--------- t770 = * BFIZ long /--* t765 long +--* t770 long N006 ( 6, 8) [000771] -c--------- t771 = * LEA(b+(i*1)+0) long /--* t771 long N007 ( 9, 10) [000772] ---XG------ t772 = * IND ushort /--* t772 ushort N009 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 lowering store lcl var/field (after): N001 ( 1, 1) [000765] ----------- t765 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000766] ----------- t766 = LCL_VAR int V16 loc12 u:13 $b04 /--* t766 int N003 ( 2, 3) [000767] -c--------- t767 = * CAST long <- int $aca N004 ( 1, 2) [000769] -c--------- t769 = CNS_INT long 1 $204 /--* t767 long +--* t769 long N005 ( 4, 6) [000770] -c--------- t770 = * BFIZ long /--* t765 long +--* t770 long N006 ( 6, 8) [000771] -c--------- t771 = * LEA(b+(i*1)+0) long /--* t771 long N007 ( 9, 10) [000772] ---XG------ t772 = * IND ushort /--* t772 ushort N009 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 lowering store lcl var/field (before): N001 ( 1, 1) [000776] ----------- t776 = LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] -c--------- t777 = CNS_INT int 1 $c1 /--* t776 int +--* t777 int N003 ( 3, 4) [000778] ----------- t778 = * ADD int $bad /--* t778 int N005 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 lowering store lcl var/field (after): N001 ( 1, 1) [000776] ----------- t776 = LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] -c--------- t777 = CNS_INT int 1 $c1 /--* t776 int +--* t777 int N003 ( 3, 4) [000778] ----------- t778 = * ADD int $bad /--* t778 int N005 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 LowerCast for: N006 ( 2, 3) [000292] ----------- * CAST long <- int $3e5 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N004 ( 1, 1) [000290] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N008 ( 4, 6) [000295] ----------- * BFIZ long New addressing mode node: N009 ( 6, 8) [000296] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N004 ( 1, 1) [000290] ----------- t290 = LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 1, 1) [000291] ----------- t291 = LCL_VAR int V16 loc12 u:5 $898 /--* t291 int N006 ( 2, 3) [000292] -c--------- t292 = * CAST long <- int $3e5 N007 ( 1, 2) [000294] -c--------- t294 = CNS_INT long 1 $204 /--* t292 long +--* t294 long N008 ( 4, 6) [000295] -c--------- t295 = * BFIZ long /--* t290 long +--* t295 long N009 ( 6, 8) [000296] -c--------- t296 = * LEA(b+(i*1)+0) long /--* t296 long N010 ( 9, 10) [000297] ---XG------ t297 = * IND ushort /--* t297 ushort N012 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 lowering store lcl var/field (after): N004 ( 1, 1) [000290] ----------- t290 = LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 1, 1) [000291] ----------- t291 = LCL_VAR int V16 loc12 u:5 $898 /--* t291 int N006 ( 2, 3) [000292] -c--------- t292 = * CAST long <- int $3e5 N007 ( 1, 2) [000294] -c--------- t294 = CNS_INT long 1 $204 /--* t292 long +--* t294 long N008 ( 4, 6) [000295] -c--------- t295 = * BFIZ long /--* t290 long +--* t295 long N009 ( 6, 8) [000296] -c--------- t296 = * LEA(b+(i*1)+0) long /--* t296 long N010 ( 9, 10) [000297] ---XG------ t297 = * IND ushort /--* t297 ushort N012 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 Lowered `AND` chain: N017 ( 22, 18) [003760] J--XG--N--- * AND int N003 ( 6, 3) [000288] -c-----N--- +--* GE int $94d N001 ( 1, 1) [000283] ----------- | +--* LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- | \--* LCL_VAR int V179 cse8 u:1 $342 N016 ( 15, 14) [000299] -c-XG--N--- \--* EQ int N013 ( 1, 1) [003665] ----------- +--* LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] -c--------- \--* CNS_INT int 0 $c0 lowering store lcl var/field (before): N001 ( 1, 1) [000303] ----------- t303 = LCL_VAR int V16 loc12 u:5 $898 /--* t303 int N003 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000303] ----------- t303 = LCL_VAR int V16 loc12 u:5 $898 /--* t303 int N003 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000304] ----------- t304 = LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] -c--------- t305 = CNS_INT int 1 $c1 /--* t304 int +--* t305 int N003 ( 3, 4) [000306] ----------- t306 = * ADD int $952 /--* t306 int N005 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 lowering store lcl var/field (after): N001 ( 1, 1) [000304] ----------- t304 = LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] -c--------- t305 = CNS_INT int 1 $c1 /--* t304 int +--* t305 int N003 ( 3, 4) [000306] ----------- t306 = * ADD int $952 /--* t306 int N005 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 lowering store lcl var/field (before): N001 ( 1, 1) [003667] ----------- t3667 = LCL_VAR int V176 cse5 /--* t3667 int N003 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003667] ----------- t3667 = LCL_VAR int V176 cse5 /--* t3667 int N003 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 Addressing mode: Base N001 ( 1, 1) [000301] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [003026] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [003027] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000301] ----------- t301 = LCL_VAR byref V00 arg0 u:1 $100 /--* t301 byref N003 ( 3, 4) [003027] -c--------- t3027 = * LEA(b+8) byref /--* t3027 byref N004 ( 4, 3) [002244] ---XG------ t2244 = * IND int /--* t2244 int N006 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000301] ----------- t301 = LCL_VAR byref V00 arg0 u:1 $100 /--* t301 byref N003 ( 3, 4) [003027] -c--------- t3027 = * LEA(b+8) byref /--* t3027 byref N004 ( 4, 3) [002244] ---XG------ t2244 = * IND int /--* t2244 int N006 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 Addressing mode: Base N002 ( 1, 1) [002248] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [003030] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [003031] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [003035] ----------- t3035 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] -c--------- t3036 = CNS_INT long 16 $200 /--* t3035 byref +--* t3036 long N003 ( 3, 4) [003037] -----O----- t3037 = * ADD byref $25c /--* t3037 byref N005 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003035] ----------- t3035 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] -c--------- t3036 = CNS_INT long 16 $200 /--* t3035 byref +--* t3036 long N003 ( 3, 4) [003037] -----O----- t3037 = * ADD byref $25c /--* t3037 byref N005 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 Addressing mode: Base N002 ( 1, 1) [002264] ----------- * LCL_VAR byref V124 tmp84 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [003039] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [003040] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002267] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [002270] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [002269] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [002271] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [002276] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [003042] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [003043] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002254] ----------- t2254 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002255] ----------- t2255 = LCL_VAR int V123 tmp83 u:1 (last use) N003 ( 2, 8) [003044] H---------- t3044 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2254 byref this in x0 +--* t2255 int arg2 in x1 +--* t3044 long r2r cell in x11 N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002254] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004280] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [002255] ----------- * LCL_VAR int V123 tmp83 u:1 (last use) new node is : [004281] ----------- * PUTARG_REG int REG x1 lowering arg : N003 ( 2, 8) [003044] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 new node is : [004282] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002254] ----------- t2254 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2254 byref [004280] ----------- t4280 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002255] ----------- t2255 = LCL_VAR int V123 tmp83 u:1 (last use) /--* t2255 int [004281] ----------- t4281 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003044] H---------- t3044 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3044 long [004282] ----------- t4282 = * PUTARG_REG long REG x11 /--* t4280 byref this in x0 +--* t4281 int arg2 in x1 +--* t4282 long r2r cell in x11 N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void lowering store lcl var/field (before): N001 ( 1, 2) [003045] ----------- t3045 = CNS_INT int 0 $c0 /--* t3045 int N003 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [003045] -c--------- t3045 = CNS_INT int 0 $c0 /--* t3045 int N003 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 lowering store lcl var/field (before): N001 ( 1, 2) [000326] ----------- t326 = CNS_INT int 0 $c0 /--* t326 int N003 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 lowering store lcl var/field (after): N001 ( 1, 2) [000326] -c--------- t326 = CNS_INT int 0 $c0 /--* t326 int N003 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 LowerCast for: N003 ( 2, 3) [000567] ----------- * CAST long <- int $3e5 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000565] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [000570] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [000571] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [000565] ----------- t565 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000566] ----------- t566 = LCL_VAR int V16 loc12 u:5 $898 /--* t566 int N003 ( 2, 3) [000567] -c--------- t567 = * CAST long <- int $3e5 N004 ( 1, 2) [000569] -c--------- t569 = CNS_INT long 1 $204 /--* t567 long +--* t569 long N005 ( 4, 6) [000570] -c--------- t570 = * BFIZ long /--* t565 long +--* t570 long N006 ( 6, 8) [000571] -c--------- t571 = * LEA(b+(i*1)+0) long /--* t571 long N007 ( 9, 10) [000572] ---XG------ t572 = * IND ushort /--* t572 ushort N009 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 lowering store lcl var/field (after): N001 ( 1, 1) [000565] ----------- t565 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000566] ----------- t566 = LCL_VAR int V16 loc12 u:5 $898 /--* t566 int N003 ( 2, 3) [000567] -c--------- t567 = * CAST long <- int $3e5 N004 ( 1, 2) [000569] -c--------- t569 = CNS_INT long 1 $204 /--* t567 long +--* t569 long N005 ( 4, 6) [000570] -c--------- t570 = * BFIZ long /--* t565 long +--* t570 long N006 ( 6, 8) [000571] -c--------- t571 = * LEA(b+(i*1)+0) long /--* t571 long N007 ( 9, 10) [000572] ---XG------ t572 = * IND ushort /--* t572 ushort N009 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 LowerCast for: N003 ( 2, 3) [000540] ----------- * CAST long <- int $3e5 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000538] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [000543] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [000544] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [000538] ----------- t538 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000539] ----------- t539 = LCL_VAR int V16 loc12 u:5 $898 /--* t539 int N003 ( 2, 3) [000540] -c--------- t540 = * CAST long <- int $3e5 N004 ( 1, 2) [000542] -c--------- t542 = CNS_INT long 1 $204 /--* t540 long +--* t542 long N005 ( 4, 6) [000543] -c--------- t543 = * BFIZ long /--* t538 long +--* t543 long N006 ( 6, 8) [000544] -c--------- t544 = * LEA(b+(i*1)+0) long /--* t544 long N007 ( 9, 10) [000545] ---XG------ t545 = * IND ushort /--* t545 ushort N009 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 lowering store lcl var/field (after): N001 ( 1, 1) [000538] ----------- t538 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000539] ----------- t539 = LCL_VAR int V16 loc12 u:5 $898 /--* t539 int N003 ( 2, 3) [000540] -c--------- t540 = * CAST long <- int $3e5 N004 ( 1, 2) [000542] -c--------- t542 = CNS_INT long 1 $204 /--* t540 long +--* t542 long N005 ( 4, 6) [000543] -c--------- t543 = * BFIZ long /--* t538 long +--* t543 long N006 ( 6, 8) [000544] -c--------- t544 = * LEA(b+(i*1)+0) long /--* t544 long N007 ( 9, 10) [000545] ---XG------ t545 = * IND ushort /--* t545 ushort N009 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 LowerCast for: N018 ( 4, 6) [000553] ----------- * CAST long <- int $3f4 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N014 ( 1, 1) [000549] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N020 ( 6, 9) [000556] ----------- * BFIZ long New addressing mode node: N021 ( 8, 11) [000557] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 2) [003046] ----------- t3046 = CNS_INT int 1 $c1 /--* t3046 int N003 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 lowering store lcl var/field (after): N001 ( 1, 2) [003046] ----------- t3046 = CNS_INT int 1 $c1 /--* t3046 int N003 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 LowerCast for: N005 ( 4, 6) [000462] ----------- * CAST long <- int $3f4 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000458] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N007 ( 6, 9) [000465] ----------- * BFIZ long New addressing mode node: N008 ( 8, 11) [000466] ----------- * LEA(b+(i*1)+0) long Addressing mode: Base N001 ( 1, 1) [000444] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [003047] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [003048] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000444] ----------- t444 = LCL_VAR byref V00 arg0 u:1 $100 /--* t444 byref N003 ( 3, 4) [003048] -c--------- t3048 = * LEA(b+8) byref /--* t3048 byref N004 ( 4, 3) [002302] ---XG------ t2302 = * IND int /--* t2302 int N006 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000444] ----------- t444 = LCL_VAR byref V00 arg0 u:1 $100 /--* t444 byref N003 ( 3, 4) [003048] -c--------- t3048 = * LEA(b+8) byref /--* t3048 byref N004 ( 4, 3) [002302] ---XG------ t2302 = * IND int /--* t2302 int N006 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 Addressing mode: Base N002 ( 1, 1) [002306] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [003051] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [003052] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [003056] ----------- t3056 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] -c--------- t3057 = CNS_INT long 16 $200 /--* t3056 byref +--* t3057 long N003 ( 3, 4) [003058] -----O----- t3058 = * ADD byref $25c /--* t3058 byref N005 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003056] ----------- t3056 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] -c--------- t3057 = CNS_INT long 16 $200 /--* t3056 byref +--* t3057 long N003 ( 3, 4) [003058] -----O----- t3058 = * ADD byref $25c /--* t3058 byref N005 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 Addressing mode: Base N002 ( 1, 1) [002321] ----------- * LCL_VAR byref V127 tmp87 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [003060] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [003061] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002324] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [002327] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [002326] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [002328] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [002333] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [003063] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [003064] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000533] ----------- t533 = LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] -c--------- t534 = CNS_INT int 1 $c1 /--* t533 int +--* t534 int N003 ( 3, 4) [000535] ----------- t535 = * ADD int $c59 /--* t535 int N005 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 lowering store lcl var/field (after): N001 ( 1, 1) [000533] ----------- t533 = LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] -c--------- t534 = CNS_INT int 1 $c1 /--* t533 int +--* t534 int N003 ( 3, 4) [000535] ----------- t535 = * ADD int $c59 /--* t535 int N005 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 lowering store lcl var/field (before): N001 ( 1, 1) [000471] ----------- t471 = LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] -c--------- t472 = CNS_INT int 1 $c1 /--* t471 int +--* t472 int N003 ( 3, 4) [000473] ----------- t473 = * ADD int $c5c /--* t473 int N005 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000471] ----------- t471 = LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] -c--------- t472 = CNS_INT int 1 $c1 /--* t471 int +--* t472 int N003 ( 3, 4) [000473] ----------- t473 = * ADD int $c5c /--* t473 int N005 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000477] ----------- t477 = LCL_VAR int V54 tmp14 u:1 $c5c /--* t477 int N003 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 lowering store lcl var/field (after): N001 ( 1, 1) [000477] ----------- t477 = LCL_VAR int V54 tmp14 u:1 $c5c /--* t477 int N003 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 LowerCast for: N003 ( 2, 3) [000524] ----------- * CAST long <- int $ad8 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000522] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [000527] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [000528] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 2) [000519] ----------- t519 = CNS_INT int 10 $e4 /--* t519 int N003 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 lowering store lcl var/field (after): N001 ( 1, 2) [000519] ----------- t519 = CNS_INT int 10 $e4 /--* t519 int N003 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 Addressing mode: Base N001 ( 1, 1) [000512] ----------- * LCL_VAR byref V01 arg1 u:1 $101 + 4 Removing unused node: N002 ( 1, 2) [003066] -c--------- * CNS_INT long 4 $207 New addressing mode node: N003 ( 3, 4) [003067] ----------- * LEA(b+4) byref lowering store lcl var/field (before): N001 ( 1, 1) [000512] ----------- t512 = LCL_VAR byref V01 arg1 u:1 $101 /--* t512 byref N003 ( 3, 4) [003067] -c--------- t3067 = * LEA(b+4) byref /--* t3067 byref N004 ( 4, 3) [000513] n---GO----- t513 = * IND int N005 ( 1, 1) [000514] ----------- t514 = LCL_VAR int V05 loc1 u:3 $28d /--* t513 int +--* t514 int N006 ( 6, 5) [000515] ----GO----- t515 = * SUB int /--* t515 int N008 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000512] ----------- t512 = LCL_VAR byref V01 arg1 u:1 $101 /--* t512 byref N003 ( 3, 4) [003067] -c--------- t3067 = * LEA(b+4) byref /--* t3067 byref N004 ( 4, 3) [000513] n---GO----- t513 = * IND int N005 ( 1, 1) [000514] ----------- t514 = LCL_VAR int V05 loc1 u:3 $28d /--* t513 int +--* t514 int N006 ( 6, 5) [000515] ----GO----- t515 = * SUB int /--* t515 int N008 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 lowering store lcl var/field (before): N001 ( 1, 2) [000495] ----------- t495 = CNS_INT int 0 $c0 /--* t495 int N003 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 lowering store lcl var/field (after): N001 ( 1, 2) [000495] -c--------- t495 = CNS_INT int 0 $c0 /--* t495 int N003 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 lowering call (before): N001 ( 1, 1) [000507] ----------- t507 = LCL_VAR int V37 loc33 u:2 (last use) $4ca N002 ( 1, 1) [000502] ----------- t502 = LCL_VAR byref V00 arg0 u:1 $100 N003 ( 1, 1) [000503] ----------- t503 = LCL_VAR ref V03 arg3 u:1 $180 N004 ( 1, 1) [000499] ----------- t499 = LCL_VAR int V55 tmp15 u:1 (last use) $b12 N005 ( 1, 1) [000505] ----------- t505 = LCL_VAR int V18 loc14 u:1 (last use) N006 ( 1, 1) [000506] ----------- t506 = LCL_VAR int V38 loc34 u:3 (last use) $b10 N007 ( 2, 8) [003068] H---------- t3068 = CNS_INT(h) long 0x4000000000540240 ftn $5e /--* t507 int arg6 in x5 +--* t502 byref arg1 in x0 +--* t503 ref arg2 in x1 +--* t499 int arg3 in x2 +--* t505 int arg4 in x3 +--* t506 int arg5 in x4 +--* t3068 long r2r cell in x11 N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [000507] ----------- * LCL_VAR int V37 loc33 u:2 (last use) $4ca new node is : [004283] ----------- * PUTARG_REG int REG x5 lowering arg : N002 ( 1, 1) [000502] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004284] ----------- * PUTARG_REG byref REG x0 lowering arg : N003 ( 1, 1) [000503] ----------- * LCL_VAR ref V03 arg3 u:1 $180 new node is : [004285] ----------- * PUTARG_REG ref REG x1 lowering arg : N004 ( 1, 1) [000499] ----------- * LCL_VAR int V55 tmp15 u:1 (last use) $b12 new node is : [004286] ----------- * PUTARG_REG int REG x2 lowering arg : N005 ( 1, 1) [000505] ----------- * LCL_VAR int V18 loc14 u:1 (last use) new node is : [004287] ----------- * PUTARG_REG int REG x3 lowering arg : N006 ( 1, 1) [000506] ----------- * LCL_VAR int V38 loc34 u:3 (last use) $b10 new node is : [004288] ----------- * PUTARG_REG int REG x4 lowering arg : N007 ( 2, 8) [003068] H---------- * CNS_INT(h) long 0x4000000000540240 ftn $5e new node is : [004289] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [000507] ----------- t507 = LCL_VAR int V37 loc33 u:2 (last use) $4ca /--* t507 int [004283] ----------- t4283 = * PUTARG_REG int REG x5 N002 ( 1, 1) [000502] ----------- t502 = LCL_VAR byref V00 arg0 u:1 $100 /--* t502 byref [004284] ----------- t4284 = * PUTARG_REG byref REG x0 N003 ( 1, 1) [000503] ----------- t503 = LCL_VAR ref V03 arg3 u:1 $180 /--* t503 ref [004285] ----------- t4285 = * PUTARG_REG ref REG x1 N004 ( 1, 1) [000499] ----------- t499 = LCL_VAR int V55 tmp15 u:1 (last use) $b12 /--* t499 int [004286] ----------- t4286 = * PUTARG_REG int REG x2 N005 ( 1, 1) [000505] ----------- t505 = LCL_VAR int V18 loc14 u:1 (last use) /--* t505 int [004287] ----------- t4287 = * PUTARG_REG int REG x3 N006 ( 1, 1) [000506] ----------- t506 = LCL_VAR int V38 loc34 u:3 (last use) $b10 /--* t506 int [004288] ----------- t4288 = * PUTARG_REG int REG x4 N007 ( 2, 8) [003068] H---------- t3068 = CNS_INT(h) long 0x4000000000540240 ftn $5e /--* t3068 long [004289] ----------- t4289 = * PUTARG_REG long REG x11 /--* t4283 int arg6 in x5 +--* t4284 byref arg1 in x0 +--* t4285 ref arg2 in x1 +--* t4286 int arg3 in x2 +--* t4287 int arg4 in x3 +--* t4288 int arg5 in x4 +--* t4289 long r2r cell in x11 N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void lowering store lcl var/field (before): N001 ( 1, 2) [003069] ----------- t3069 = CNS_INT int 0 $c0 /--* t3069 int N003 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 lowering store lcl var/field (after): N001 ( 1, 2) [003069] -c--------- t3069 = CNS_INT int 0 $c0 /--* t3069 int N003 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 Addressing mode: Base N001 ( 1, 1) [000333] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [003070] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [003071] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000333] ----------- t333 = LCL_VAR byref V00 arg0 u:1 $100 /--* t333 byref N003 ( 3, 4) [003071] -c--------- t3071 = * LEA(b+8) byref /--* t3071 byref N004 ( 4, 3) [002349] ---XG------ t2349 = * IND int /--* t2349 int N006 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000333] ----------- t333 = LCL_VAR byref V00 arg0 u:1 $100 /--* t333 byref N003 ( 3, 4) [003071] -c--------- t3071 = * LEA(b+8) byref /--* t3071 byref N004 ( 4, 3) [002349] ---XG------ t2349 = * IND int /--* t2349 int N006 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 Addressing mode: Base N002 ( 1, 1) [002353] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [003074] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [003075] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [003079] ----------- t3079 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] -c--------- t3080 = CNS_INT long 16 $200 /--* t3079 byref +--* t3080 long N003 ( 3, 4) [003081] -----O----- t3081 = * ADD byref $25c /--* t3081 byref N005 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003079] ----------- t3079 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] -c--------- t3080 = CNS_INT long 16 $200 /--* t3079 byref +--* t3080 long N003 ( 3, 4) [003081] -----O----- t3081 = * ADD byref $25c /--* t3081 byref N005 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 Addressing mode: Base N002 ( 1, 1) [002368] ----------- * LCL_VAR byref V130 tmp90 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [003083] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [003084] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002371] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [002374] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [002373] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [002375] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [002380] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [003086] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [003087] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002359] ----------- t2359 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000334] ----------- t334 = LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003088] H---------- t3088 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2359 byref this in x0 +--* t334 int arg2 in x1 +--* t3088 long r2r cell in x11 N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002359] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004290] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [000334] ----------- * LCL_VAR int V18 loc14 u:1 (last use) new node is : [004291] ----------- * PUTARG_REG int REG x1 lowering arg : N003 ( 2, 8) [003088] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 new node is : [004292] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002359] ----------- t2359 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2359 byref [004290] ----------- t4290 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000334] ----------- t334 = LCL_VAR int V18 loc14 u:1 (last use) /--* t334 int [004291] ----------- t4291 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003088] H---------- t3088 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3088 long [004292] ----------- t4292 = * PUTARG_REG long REG x11 /--* t4290 byref this in x0 +--* t4291 int arg2 in x1 +--* t4292 long r2r cell in x11 N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void LowerCast for: N003 ( 2, 3) [000345] ----------- * CAST long <- int $3e5 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000343] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [000348] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [000349] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [000343] ----------- t343 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000344] ----------- t344 = LCL_VAR int V16 loc12 u:5 $898 /--* t344 int N003 ( 2, 3) [000345] -c--------- t345 = * CAST long <- int $3e5 N004 ( 1, 2) [000347] -c--------- t347 = CNS_INT long 1 $204 /--* t345 long +--* t347 long N005 ( 4, 6) [000348] -c--------- t348 = * BFIZ long /--* t343 long +--* t348 long N006 ( 6, 8) [000349] -c--------- t349 = * LEA(b+(i*1)+0) long /--* t349 long N007 ( 9, 10) [000350] ---XG------ t350 = * IND ushort /--* t350 ushort N009 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000343] ----------- t343 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000344] ----------- t344 = LCL_VAR int V16 loc12 u:5 $898 /--* t344 int N003 ( 2, 3) [000345] -c--------- t345 = * CAST long <- int $3e5 N004 ( 1, 2) [000347] -c--------- t347 = CNS_INT long 1 $204 /--* t345 long +--* t347 long N005 ( 4, 6) [000348] -c--------- t348 = * BFIZ long /--* t343 long +--* t348 long N006 ( 6, 8) [000349] -c--------- t349 = * LEA(b+(i*1)+0) long /--* t349 long N007 ( 9, 10) [000350] ---XG------ t350 = * IND ushort /--* t350 ushort N009 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000356] ----------- t356 = LCL_VAR int V16 loc12 u:5 $898 /--* t356 int N003 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000356] ----------- t356 = LCL_VAR int V16 loc12 u:5 $898 /--* t356 int N003 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000357] ----------- t357 = LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] -c--------- t358 = CNS_INT int 1 $c1 /--* t357 int +--* t358 int N003 ( 3, 4) [000359] ----------- t359 = * ADD int $952 /--* t359 int N005 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 lowering store lcl var/field (after): N001 ( 1, 1) [000357] ----------- t357 = LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] -c--------- t358 = CNS_INT int 1 $c1 /--* t357 int +--* t358 int N003 ( 3, 4) [000359] ----------- t359 = * ADD int $952 /--* t359 int N005 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 lowering store lcl var/field (before): N001 ( 1, 1) [003662] ----------- t3662 = LCL_VAR int V175 cse4 u:1 /--* t3662 int N003 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003662] ----------- t3662 = LCL_VAR int V175 cse4 u:1 /--* t3662 int N003 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 Addressing mode: Base N001 ( 1, 1) [000354] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [003089] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [003090] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000354] ----------- t354 = LCL_VAR byref V00 arg0 u:1 $100 /--* t354 byref N003 ( 3, 4) [003090] -c--------- t3090 = * LEA(b+8) byref /--* t3090 byref N004 ( 4, 3) [002396] n---GO----- t2396 = * IND int /--* t2396 int N006 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000354] ----------- t354 = LCL_VAR byref V00 arg0 u:1 $100 /--* t354 byref N003 ( 3, 4) [003090] -c--------- t3090 = * LEA(b+8) byref /--* t3090 byref N004 ( 4, 3) [002396] n---GO----- t2396 = * IND int /--* t2396 int N006 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 Addressing mode: Base N002 ( 1, 1) [002400] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [003093] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [003094] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [003098] ----------- t3098 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] -c--------- t3099 = CNS_INT long 16 $200 /--* t3098 byref +--* t3099 long N003 ( 3, 4) [003100] -----O----- t3100 = * ADD byref $25c /--* t3100 byref N005 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003098] ----------- t3098 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] -c--------- t3099 = CNS_INT long 16 $200 /--* t3098 byref +--* t3099 long N003 ( 3, 4) [003100] -----O----- t3100 = * ADD byref $25c /--* t3100 byref N005 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 Addressing mode: Base N002 ( 1, 1) [002416] ----------- * LCL_VAR byref V134 tmp94 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [003102] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [003103] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002419] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [002422] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [002421] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [002423] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [002428] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [003105] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [003106] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002406] ----------- t2406 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002407] ----------- t2407 = LCL_VAR int V133 tmp93 u:1 (last use) N003 ( 2, 8) [003107] H---------- t3107 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2406 byref this in x0 +--* t2407 int arg2 in x1 +--* t3107 long r2r cell in x11 N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002406] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004293] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [002407] ----------- * LCL_VAR int V133 tmp93 u:1 (last use) new node is : [004294] ----------- * PUTARG_REG int REG x1 lowering arg : N003 ( 2, 8) [003107] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 new node is : [004295] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002406] ----------- t2406 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2406 byref [004293] ----------- t4293 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002407] ----------- t2407 = LCL_VAR int V133 tmp93 u:1 (last use) /--* t2407 int [004294] ----------- t4294 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003107] H---------- t3107 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3107 long [004295] ----------- t4295 = * PUTARG_REG long REG x11 /--* t4293 byref this in x0 +--* t4294 int arg2 in x1 +--* t4295 long r2r cell in x11 N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000392] ----------- t392 = LCL_VAR int V16 loc12 u:6 $b08 /--* t392 int N003 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000392] ----------- t392 = LCL_VAR int V16 loc12 u:6 $b08 /--* t392 int N003 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000393] ----------- t393 = LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] -c--------- t394 = CNS_INT int 1 $c1 /--* t393 int +--* t394 int N003 ( 3, 4) [000395] ----------- t395 = * ADD int $c47 /--* t395 int N005 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 lowering store lcl var/field (after): N001 ( 1, 1) [000393] ----------- t393 = LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] -c--------- t394 = CNS_INT int 1 $c1 /--* t393 int +--* t394 int N003 ( 3, 4) [000395] ----------- t395 = * ADD int $c47 /--* t395 int N005 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 lowering store lcl var/field (before): N001 ( 1, 1) [003639] ----------- t3639 = LCL_VAR int V173 cse2 u:1 /--* t3639 int N003 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003639] ----------- t3639 = LCL_VAR int V173 cse2 u:1 /--* t3639 int N003 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 Addressing mode: Base N001 ( 1, 1) [000390] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [003108] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [003109] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000390] ----------- t390 = LCL_VAR byref V00 arg0 u:1 $100 /--* t390 byref N003 ( 3, 4) [003109] -c--------- t3109 = * LEA(b+8) byref /--* t3109 byref N004 ( 4, 3) [002442] n---GO----- t2442 = * IND int /--* t2442 int N006 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000390] ----------- t390 = LCL_VAR byref V00 arg0 u:1 $100 /--* t390 byref N003 ( 3, 4) [003109] -c--------- t3109 = * LEA(b+8) byref /--* t3109 byref N004 ( 4, 3) [002442] n---GO----- t2442 = * IND int /--* t2442 int N006 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 Addressing mode: Base N002 ( 1, 1) [002446] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [003112] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [003113] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [003117] ----------- t3117 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] -c--------- t3118 = CNS_INT long 16 $200 /--* t3117 byref +--* t3118 long N003 ( 3, 4) [003119] -----O----- t3119 = * ADD byref $25c /--* t3119 byref N005 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003117] ----------- t3117 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] -c--------- t3118 = CNS_INT long 16 $200 /--* t3117 byref +--* t3118 long N003 ( 3, 4) [003119] -----O----- t3119 = * ADD byref $25c /--* t3119 byref N005 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 Addressing mode: Base N002 ( 1, 1) [002462] ----------- * LCL_VAR byref V138 tmp98 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [003121] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [003122] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002465] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [002468] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [002467] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [002469] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [002474] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [003124] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [003125] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002452] ----------- t2452 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [002453] ----------- t2453 = LCL_VAR int V137 tmp97 u:1 (last use) N003 ( 2, 8) [003126] H---------- t3126 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2452 byref this in x0 +--* t2453 int arg2 in x1 +--* t3126 long r2r cell in x11 N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002452] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004296] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [002453] ----------- * LCL_VAR int V137 tmp97 u:1 (last use) new node is : [004297] ----------- * PUTARG_REG int REG x1 lowering arg : N003 ( 2, 8) [003126] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 new node is : [004298] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002452] ----------- t2452 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2452 byref [004296] ----------- t4296 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002453] ----------- t2453 = LCL_VAR int V137 tmp97 u:1 (last use) /--* t2453 int [004297] ----------- t4297 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003126] H---------- t3126 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3126 long [004298] ----------- t4298 = * PUTARG_REG long REG x11 /--* t4296 byref this in x0 +--* t4297 int arg2 in x1 +--* t4298 long r2r cell in x11 N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void LowerCast for: N003 ( 2, 3) [000381] ----------- * CAST long <- int $ad1 Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N001 ( 1, 1) [000379] ----------- * LCL_VAR long V34 loc30 u:1 $3c4 + Index * 1 + 0 N005 ( 4, 6) [000384] ----------- * BFIZ long New addressing mode node: N006 ( 6, 8) [000385] ----------- * LEA(b+(i*1)+0) long lowering store lcl var/field (before): N001 ( 1, 1) [000379] ----------- t379 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000380] ----------- t380 = LCL_VAR int V16 loc12 u:6 $b08 /--* t380 int N003 ( 2, 3) [000381] -c--------- t381 = * CAST long <- int $ad1 N004 ( 1, 2) [000383] -c--------- t383 = CNS_INT long 1 $204 /--* t381 long +--* t383 long N005 ( 4, 6) [000384] -c--------- t384 = * BFIZ long /--* t379 long +--* t384 long N006 ( 6, 8) [000385] -c--------- t385 = * LEA(b+(i*1)+0) long /--* t385 long N007 ( 9, 10) [000386] ---XG------ t386 = * IND ushort /--* t386 ushort N009 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000379] ----------- t379 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000380] ----------- t380 = LCL_VAR int V16 loc12 u:6 $b08 /--* t380 int N003 ( 2, 3) [000381] -c--------- t381 = * CAST long <- int $ad1 N004 ( 1, 2) [000383] -c--------- t383 = CNS_INT long 1 $204 /--* t381 long +--* t383 long N005 ( 4, 6) [000384] -c--------- t384 = * BFIZ long /--* t379 long +--* t384 long N006 ( 6, 8) [000385] -c--------- t385 = * LEA(b+(i*1)+0) long /--* t385 long N007 ( 9, 10) [000386] ---XG------ t386 = * IND ushort /--* t386 ushort N009 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 Addressing mode: Base N001 ( 1, 1) [000590] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N002 ( 1, 2) [003127] -c--------- * CNS_INT long 8 $201 New addressing mode node: N003 ( 3, 4) [003128] ----------- * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000590] ----------- t590 = LCL_VAR byref V00 arg0 u:1 $100 /--* t590 byref N003 ( 3, 4) [003128] -c--------- t3128 = * LEA(b+8) byref /--* t3128 byref N004 ( 4, 3) [002492] ---XG------ t2492 = * IND int /--* t2492 int N006 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000590] ----------- t590 = LCL_VAR byref V00 arg0 u:1 $100 /--* t590 byref N003 ( 3, 4) [003128] -c--------- t3128 = * LEA(b+8) byref /--* t3128 byref N004 ( 4, 3) [002492] ---XG------ t2492 = * IND int /--* t2492 int N006 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 Addressing mode: Base N002 ( 1, 1) [002496] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 24 Removing unused node: N003 ( 1, 2) [003131] -c--------- * CNS_INT long 24 $20c New addressing mode node: N004 ( 3, 4) [003132] ----------- * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [003136] ----------- t3136 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] -c--------- t3137 = CNS_INT long 16 $200 /--* t3136 byref +--* t3137 long N003 ( 3, 4) [003138] -----O----- t3138 = * ADD byref $25c /--* t3138 byref N005 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [003136] ----------- t3136 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] -c--------- t3137 = CNS_INT long 16 $200 /--* t3136 byref +--* t3137 long N003 ( 3, 4) [003138] -----O----- t3138 = * ADD byref $25c /--* t3138 byref N005 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 Addressing mode: Base N002 ( 1, 1) [002511] ----------- * LCL_VAR byref V141 tmp101 u:1 $25c + 8 Removing unused node: N003 ( 1, 2) [003140] -c--------- * CNS_INT long 8 $201 New addressing mode node: N004 ( 3, 4) [003141] ----------- * LEA(b+8) byref LowerCast for: N010 ( 2, 3) [002514] ---------U- * CAST long <- uint Recognized ubfix/sbfix pattern in LSH(CAST, CNS). Changing op to GT_BFIZAddressing mode: Base N008 ( 3, 2) [002517] n---GO----- * IND byref + Index * 1 + 0 N012 ( 4, 6) [002516] ----------- * BFIZ long New addressing mode node: N013 ( 8, 9) [002518] ----------- * LEA(b+(i*1)+0) byref Addressing mode: Base N004 ( 1, 1) [002523] ----------- * LCL_VAR byref V00 arg0 u:1 $100 + 8 Removing unused node: N005 ( 1, 2) [003143] -c--------- * CNS_INT long 8 $201 New addressing mode node: N006 ( 3, 4) [003144] ----------- * LEA(b+8) byref lowering call (before): N001 ( 1, 1) [002502] ----------- t2502 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 1) [000591] ----------- t591 = LCL_VAR int V18 loc14 u:1 (last use) N003 ( 2, 8) [003145] H---------- t3145 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2502 byref this in x0 +--* t591 int arg2 in x1 +--* t3145 long r2r cell in x11 N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [002502] ----------- * LCL_VAR byref V00 arg0 u:1 $100 new node is : [004299] ----------- * PUTARG_REG byref REG x0 lowering arg : N002 ( 1, 1) [000591] ----------- * LCL_VAR int V18 loc14 u:1 (last use) new node is : [004300] ----------- * PUTARG_REG int REG x1 lowering arg : N003 ( 2, 8) [003145] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn $53 new node is : [004301] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 1, 1) [002502] ----------- t2502 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2502 byref [004299] ----------- t4299 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000591] ----------- t591 = LCL_VAR int V18 loc14 u:1 (last use) /--* t591 int [004300] ----------- t4300 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003145] H---------- t3145 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3145 long [004301] ----------- t4301 = * PUTARG_REG long REG x11 /--* t4299 byref this in x0 +--* t4300 int arg2 in x1 +--* t4301 long r2r cell in x11 N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void lowering call (before): N001 ( 2, 8) [002701] H---------- t2701 = CNS_INT(h) long 0x4000000000424a20 ftn $4a /--* t2701 long r2r cell in x11 N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void args: ====== late: ====== lowering arg : N001 ( 2, 8) [002701] H---------- * CNS_INT(h) long 0x4000000000424a20 ftn $4a new node is : [004302] ----------- * PUTARG_REG long REG x11 lowering call (after): N001 ( 2, 8) [002701] H---------- t2701 = CNS_INT(h) long 0x4000000000424a20 ftn $4a /--* t2701 long [004302] ----------- t4302 = * PUTARG_REG long REG x11 /--* t4302 long r2r cell in x11 N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void lowering call (before): N001 ( 14, 2) [004154] --CXG------ CALL help void CORINFO_HELP_RNGCHKFAIL args: ====== late: ====== results of lowering call: N001 ( 2, 8) [004303] H---------- t4303 = CNS_INT(h) long 0x4000000000421828 ftn /--* t4303 long N002 ( 5, 10) [004304] ----------- t4304 = * IND long lowering call (after): N001 ( 2, 8) [004303] H---------- t4303 = CNS_INT(h) long 0x4000000000421828 ftn /--* t4303 long N002 ( 5, 10) [004304] ----------- t4304 = * IND long /--* t4304 long control expr N001 ( 14, 2) [004154] --CXG------ * CALL help void CORINFO_HELP_RNGCHKFAIL Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..061)-> BB10 ( cond ) i bwd LIR BB255 [0364] 1 BB09 8 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31 (switch) i bwd LIR BB10 [0009] 1 BB09 8 1 [083..083)-> BB11 ( cond ) i bwd LIR BB256 [0365] 1 BB10 8 [083..0A1)-> BB23,BB47,BB21,BB47,BB18 (switch) i bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB255 8 1 [0CF..0D8)-> BB47 (always) i bwd LIR BB18 [0017] 1 BB256 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd LIR BB21 [0020] 1 BB256 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB256 8 1 [0FB..102)-> BB47 ( cond ) i bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd LIR BB30 [0029] 1 BB255 8 1 [12C..137)-> BB47 (always) i bwd LIR BB31 [0031] 3 BB32,BB255(2) 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd LIR BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd LIR BB47 [0047] 24 BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB255(2),BB256(2) 64 1 [204..20F)-> BB50 ( cond ) i bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd LIR BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i LIR BB245 [0190] 25 BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB258 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd LIR BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd LIR BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src LIR BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd LIR BB137 [0117] 1 BB136 2 3 [478..478)-> BB138 ( cond ) i bwd LIR BB257 [0366] 1 BB137 2 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194 (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..49A)-> BB139 ( cond ) i bwd LIR BB258 [0367] 1 BB138 2 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145 (switch) i bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB257,BB258 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd LIR BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd LIR BB171 [0143] 1 BB258 2 3 [564..571)-> BB245 ( cond ) i bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd LIR BB186 [0149] 1 BB257 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd LIR BB194 [0151] 4 BB192,BB193,BB257(2) 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src LIR BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB140,BB143,BB257(2),BB258(2) 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd LIR BB254 [0363] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} [003780] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 $101 /--* t0 byref [004185] ----------- t4185 = * PUTARG_REG byref REG x0 N002 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn $42 /--* t2543 long [004186] ----------- t4186 = * PUTARG_REG long REG x11 /--* t4185 byref this in x0 +--* t4186 long r2r cell in x11 N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void [003781] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 1, 2) [000002] -c--------- t2 = CNS_INT int 0 $c0 /--* t2 int N003 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 [003782] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] N001 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] -c--------- t2547 = CNS_INT long 16 $200 /--* t2546 byref +--* t2547 long N003 ( 3, 4) [002548] -----O----- t2548 = * ADD byref $240 /--* t2548 byref N005 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 [003783] ----------- IL_OFFSET void INLRT @ 0x009[E-] N001 ( 1, 2) [001497] -c--------- t1497 = CNS_INT int 0 $c0 N002 ( 1, 1) [001502] ----------- t1502 = LCL_VAR byref V76 tmp36 u:1 $240 /--* t1502 byref N004 ( 3, 4) [002556] -c--------- t2556 = * LEA(b+8) byref /--* t2556 byref N005 ( 4, 3) [001503] ---XG------ t1503 = * IND int /--* t1497 int +--* t1503 int N006 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 (last use) $240 /--* t1501 byref N008 ( 3, 2) [001505] n---GO----- t1505 = * IND byref /--* t1505 byref N011 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 N012 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 /--* t2552 long N015 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 N001 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] $246 /--* t2558 byref N003 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 N004 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3710 byref N007 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 N008 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] $342 /--* t2561 int N010 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 N011 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 $342 /--* t3690 int N014 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 [003784] ----------- IL_OFFSET void INLRT @ 0x011[E-] N001 ( 1, 1) [000011] ----------- t11 = LCL_VAR long V17 loc13 u:1 (last use) /--* t11 long N002 ( 4, 3) [000012] ---XG------ t12 = * IND ubyte N003 ( 1, 2) [000013] -c--------- t13 = CNS_INT int 0 $c0 /--* t12 ubyte +--* t13 int N004 ( 6, 6) [000014] CEQ---XG--N--- * JCMP void ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2565 byref N003 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 N004 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2568 int N006 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 N001 ( 1, 1) [001472] ----------- t1472 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1472 byref N003 ( 3, 4) [002572] -c--------- t2572 = * LEA(b+8) byref /--* t2572 byref N004 ( 5, 4) [001473] n---GO----- t1473 = * IND bool N005 ( 1, 2) [001474] -c--------- t1474 = CNS_INT int 0 $c0 /--* t1473 bool +--* t1474 int N006 ( 7, 7) [001475] CNE----GO-N--- * JCMP void ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} N001 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2574 byref N003 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 N004 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2577 int N006 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 N001 ( 1, 2) [001489] -c--------- t1489 = CNS_INT int 0 $c0 /--* t1489 int N003 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} N001 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2581 byref N003 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 N004 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2584 int N006 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 N001 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 $c1 /--* t1482 int N003 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 ------------ BB05 [025..026), preds={BB01} succs={BB06} N001 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2588 byref N003 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 N004 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2591 int N006 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 N001 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 $c2 /--* t21 int N003 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} N001 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 (last use) $246 /--* t2596 byref [004187] ----------- t4187 = * PUTARG_REG byref REG x0 N002 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 (last use) $342 /--* t2597 int [004188] ----------- t4188 = * PUTARG_REG int REG x1 /--* t4187 byref +--* t4188 int N003 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct $141 N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 (last use) $281 /--* t29 int [004189] ----------- t4189 = * PUTARG_REG int REG x2 N005 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2594 long [004190] ----------- t4190 = * PUTARG_REG long REG x11 /--* t2595 struct arg1 x0,x1 +--* t4189 int arg2 in x2 +--* t4190 long r2r cell in x11 N006 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int $2c1 /--* t30 int N008 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} [003785] ----------- IL_OFFSET void INLRT @ 0x02D[E-] N001 ( 1, 2) [000035] -c--------- t35 = CNS_INT int 0 $c0 /--* t35 int N003 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 [003786] ----------- IL_OFFSET void INLRT @ 0x02F[E-] N001 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 $c4 /--* t38 int N003 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 [003787] ----------- IL_OFFSET void INLRT @ 0x031[E-] N001 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF $c9 /--* t41 int N003 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 [003788] ----------- IL_OFFSET void INLRT @ 0x037[E-] N001 ( 1, 2) [000044] -c--------- t44 = CNS_INT int 0 $c0 /--* t44 int N003 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 [003789] ----------- IL_OFFSET void INLRT @ 0x039[E-] N001 ( 1, 2) [002598] -c--------- t2598 = CNS_INT int 0 $c0 /--* t2598 int N003 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 [003790] ----------- IL_OFFSET void INLRT @ 0x03C[E-] N001 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 $c4 /--* t50 int N003 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 [003791] ----------- IL_OFFSET void INLRT @ 0x03F[E-] N001 ( 1, 2) [002599] -c--------- t2599 = CNS_INT int 0 $c0 /--* t2599 int N003 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 [003792] ----------- IL_OFFSET void INLRT @ 0x042[E-] N001 ( 1, 2) [000056] -c--------- t56 = CNS_INT int 0 $c0 /--* t56 int N003 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 [003793] ----------- IL_OFFSET void INLRT @ 0x045[E-] N001 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 $283 /--* t59 int N003 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 [003794] ----------- IL_OFFSET void INLRT @ 0x049[E-] N001 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3712 byref N003 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 [003795] ----------- IL_OFFSET void INLRT @ 0x049[E-] N001 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 $246 /--* t1512 byref N003 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 [003796] ----------- IL_OFFSET void INLRT @ 0x051[E-] N001 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 (last use) $246 /--* t69 byref N003 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 N004 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 (last use) $3c4 /--* t2609 long N007 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} [003797] ----------- IL_OFFSET void INLRT @ 0x05B[E-] N001 ( 1, 1) [001226] ----------- t1226 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] -c--------- t1227 = CNS_INT int 69 $d2 /--* t1226 int +--* t1227 int N003 ( 3, 4) [001228] N------N-U- * GT void N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void ------------ BB09 [061..061) -> BB10 (cond), preds={BB08} succs={BB255,BB10} [003798] ----------- IL_OFFSET void INLRT @ 0x061[E-] N001 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] -c--------- t1362 = CNS_INT int -34 $d6 /--* t1361 int +--* t1362 int N003 ( 3, 4) [001363] ----------- t1363 = * ADD int /--* t1363 int [004192] DA--------- * STORE_LCL_VAR int V182 rat0 N001 ( 3, 2) [004194] ----------- t4194 = LCL_VAR int V182 rat0 N002 ( 1, 2) [004195] -c--------- t4195 = CNS_INT int 5 /--* t4194 int +--* t4195 int N003 ( 8, 5) [004196] ---------U- * GT void N004 ( 10, 7) [004197] ----------- * JTRUE void ------------ BB255 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31 (switch), preds={BB09} succs={BB17,BB30,BB31,BB47} [004198] ----------- t4198 = LCL_VAR int V182 rat0 /--* t4198 int [004199] ---------U- t4199 = * CAST long <- ulong <- uint [004200] ----------- t4200 = JMPTABLE long /--* t4199 long +--* t4200 long [004201] ----------- * SWITCH_TABLE void ------------ BB10 [083..083) -> BB11 (cond), preds={BB09} succs={BB256,BB11} [003799] ----------- IL_OFFSET void INLRT @ 0x083[E-] N001 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] -c--------- t1366 = CNS_INT int -44 $d7 /--* t1365 int +--* t1366 int N003 ( 3, 4) [001367] ----------- t1367 = * ADD int /--* t1367 int [004203] DA--------- * STORE_LCL_VAR int V183 rat1 N001 ( 3, 2) [004205] ----------- t4205 = LCL_VAR int V183 rat1 N002 ( 1, 2) [004206] -c--------- t4206 = CNS_INT int 4 /--* t4205 int +--* t4206 int N003 ( 8, 5) [004207] ---------U- * GT void N004 ( 10, 7) [004208] ----------- * JTRUE void ------------ BB256 [083..0A1) -> BB23,BB47,BB21,BB47,BB18 (switch), preds={BB10} succs={BB18,BB21,BB23,BB47} [004209] ----------- t4209 = LCL_VAR int V183 rat1 /--* t4209 int [004210] ---------U- t4210 = * CAST long <- ulong <- uint [004211] ----------- t4211 = JMPTABLE long /--* t4210 long +--* t4211 long [004212] ----------- * SWITCH_TABLE void ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} [003800] ----------- IL_OFFSET void INLRT @ 0x0A1[E-] N001 ( 1, 1) [001369] ----------- t1369 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] -c--------- t1370 = CNS_INT int 69 $d2 /--* t1369 int +--* t1370 int N003 ( 3, 4) [001371] J------N--- * EQ void N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} [003801] ----------- IL_OFFSET void INLRT @ 0x0AF[E-] N001 ( 1, 1) [001230] ----------- t1230 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] -c--------- t1231 = CNS_INT int 92 $d3 /--* t1230 int +--* t1231 int N003 ( 3, 4) [001232] J------N--- * EQ void N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} [003802] ----------- IL_OFFSET void INLRT @ 0x0B8[E-] N001 ( 1, 1) [001257] ----------- t1257 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] -c--------- t1258 = CNS_INT int 101 $d4 /--* t1257 int +--* t1258 int N003 ( 3, 4) [001259] J------N--- * EQ void N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} [003803] ----------- IL_OFFSET void INLRT @ 0x0C1[E-] N001 ( 1, 1) [001352] ----------- t1352 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- t1353 = CNS_INT int 0x2030 $d5 /--* t1352 int +--* t1353 int N003 ( 3, 6) [001354] J------N--- * NE void N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} [003804] ----------- IL_OFFSET void INLRT @ 0x137[E-] N001 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] -c--------- t1357 = CNS_INT int 3 $c3 /--* t1356 int +--* t1357 int N003 ( 3, 4) [001358] ----------- t1358 = * ADD int $376 /--* t1358 int N005 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB255} succs={BB47} [003805] ----------- IL_OFFSET void INLRT @ 0x0CF[E-] N001 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] -c--------- t1431 = CNS_INT int 1 $c1 /--* t1430 int +--* t1431 int N003 ( 3, 4) [001432] ----------- t1432 = * ADD int $68f /--* t1432 int N005 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB256} succs={BB19,BB20} [003806] ----------- IL_OFFSET void INLRT @ 0x0D8[E-] N001 ( 1, 1) [001373] ----------- t1373 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- t1374 = CNS_INT int 0x7FFFFFFF $c9 /--* t1373 int +--* t1374 int N003 ( 3, 6) [001375] N------N-U- * NE void $68e N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} [003807] ----------- IL_OFFSET void INLRT @ 0x0E0[E-] N001 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 $28a /--* t1385 int N003 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} [003808] ----------- IL_OFFSET void INLRT @ 0x0E2[E-] N001 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] -c--------- t1378 = CNS_INT int 1 $c1 /--* t1377 int +--* t1378 int N003 ( 3, 4) [001379] ----------- t1379 = * ADD int $68f /--* t1379 int N005 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 [003809] ----------- IL_OFFSET void INLRT @ 0x0E6[E-] N001 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 $68f /--* t1382 int N003 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB256} succs={BB22,BB47} [003810] ----------- IL_OFFSET void INLRT @ 0x0ED[E-] N001 ( 1, 1) [001388] ----------- t1388 = LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] -c--------- t1389 = CNS_INT int 0 $c0 /--* t1388 int +--* t1389 int N003 ( 3, 4) [001390] J------N--- * GE void $690 N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} [003811] ----------- IL_OFFSET void INLRT @ 0x0F4[E-] N001 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 $28a /--* t1392 int N003 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB256} succs={BB24,BB47} [003812] ----------- IL_OFFSET void INLRT @ 0x0FB[E-] N001 ( 1, 1) [001395] ----------- t1395 = LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] -c--------- t1396 = CNS_INT int 0 $c0 /--* t1395 int +--* t1396 int N003 ( 6, 4) [001397] -c-----N--- t1397 = * LE int $691 N004 ( 1, 1) [001399] ----------- t1399 = LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] -c--------- t1400 = CNS_INT int 0 $c0 /--* t1399 int +--* t1400 int N006 ( 6, 4) [001401] -c-----N--- t1401 = * GE int $690 /--* t1397 int +--* t1401 int N007 ( 13, 9) [003726] Jc-----N--- * AND void N008 ( 15, 11) [001398] ----------- * JTRUE void $VN.Void ------------ BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} [003813] ----------- IL_OFFSET void INLRT @ 0x102[E-] N001 ( 0, 0) [003727] ----------- NOP void [003814] ----------- IL_OFFSET void INLRT @ 0x109[E-] N001 ( 1, 1) [001403] ----------- t1403 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] -c--------- t1404 = CNS_INT int 0 $c0 /--* t1403 int +--* t1404 int N003 ( 3, 4) [001405] J------N--- * LT void $692 N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void ------------ BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} [003815] ----------- IL_OFFSET void INLRT @ 0x10E[E-] N001 ( 1, 1) [001413] ----------- t1413 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- t1414 = LCL_VAR int V04 loc0 u:2 $28a /--* t1413 int +--* t1414 int N003 ( 3, 3) [001415] N------N-U- * NE void $693 N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} [003816] ----------- IL_OFFSET void INLRT @ 0x113[E-] N001 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] -c--------- t1421 = CNS_INT int 1 $c1 /--* t1420 int +--* t1421 int N003 ( 3, 4) [001422] ----------- t1422 = * ADD int $694 /--* t1422 int N005 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 ------------ BB28 [11E..121), preds={BB26} succs={BB29} [003817] ----------- IL_OFFSET void INLRT @ 0x11E[E-] N001 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 $c1 /--* t2612 int N003 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 ------------ BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} [003818] ----------- IL_OFFSET void INLRT @ 0x121[E-] N001 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 $28a /--* t1407 int N003 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 [003819] ----------- IL_OFFSET void INLRT @ 0x124[E-] N001 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 $c1 /--* t1410 int N003 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 ------------ BB30 [12C..137) -> BB47 (always), preds={BB255} succs={BB47} [003820] ----------- IL_OFFSET void INLRT @ 0x12C[E-] N001 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] -c--------- t1426 = CNS_INT int 2 $c2 /--* t1425 int +--* t1426 int N003 ( 3, 4) [001427] ----------- t1427 = * ADD int $695 /--* t1427 int N005 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 ------------ BB31 [142..150) -> BB47 (cond), preds={BB32,BB255(2)} succs={BB32,BB47} [003821] ----------- IL_OFFSET void INLRT @ 0x142[E-] N001 ( 1, 1) [001435] ----------- t1435 = LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- t3693 = LCL_VAR int V179 cse8 u:1 $342 /--* t1435 int +--* t3693 int N003 ( 6, 3) [001440] -c-----N--- t1440 = * GE int $8b7 N004 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1443 int N006 ( 2, 3) [001444] -c--------- t1444 = * CAST long <- int $3de N007 ( 1, 2) [001446] -c--------- t1446 = CNS_INT long 1 $204 /--* t1444 long +--* t1446 long N008 ( 4, 6) [001447] -c--------- t1447 = * BFIZ long /--* t1442 long +--* t1447 long N009 ( 6, 8) [001448] -c--------- t1448 = * LEA(b+(i*1)+0) long /--* t1448 long N010 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort /--* t1449 ushort N012 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 N013 ( 1, 1) [003626] ----------- t3626 = LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] -c--------- t1450 = CNS_INT int 0 $c0 /--* t3626 int +--* t1450 int N016 ( 15, 14) [001451] -c-XG--N--- t1451 = * EQ int /--* t1440 int +--* t1451 int N017 ( 22, 18) [003728] Jc-XG--N--- * AND void N018 ( 24, 20) [001441] ---XG------ * JTRUE void $VN.Void ------------ BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} [003822] ----------- IL_OFFSET void INLRT @ 0x150[E-] N001 ( 0, 0) [003729] ----------- NOP void [003823] ----------- IL_OFFSET void INLRT @ 0x15E[E-] N001 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1454 int N003 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 [003824] ----------- IL_OFFSET void INLRT @ 0x15E[E-] N001 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] -c--------- t1456 = CNS_INT int 1 $c1 /--* t1455 int +--* t1456 int N003 ( 3, 4) [001457] ----------- t1457 = * ADD int $8bc /--* t1457 int N005 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 N001 ( 1, 1) [003628] ----------- t3628 = LCL_VAR int V171 cse0 u:1 N002 ( 1, 1) [001469] ----------- t1469 = LCL_VAR int V18 loc14 u:5 /--* t3628 int +--* t1469 int N003 ( 3, 3) [001470] N---G--N-U- * NE void N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 ------------ BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} [003825] ----------- IL_OFFSET void INLRT @ 0x175[E-] N001 ( 1, 1) [001234] ----------- t1234 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- t3694 = LCL_VAR int V179 cse8 u:1 $342 /--* t1234 int +--* t3694 int N003 ( 6, 3) [001239] -c-----N--- t1239 = * GE int $36c N004 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 $361 /--* t1242 int N006 ( 2, 3) [001243] -c--------- t1243 = * CAST long <- int $3c8 N007 ( 1, 2) [001245] -c--------- t1245 = CNS_INT long 1 $204 /--* t1243 long +--* t1245 long N008 ( 4, 6) [001246] -c--------- t1246 = * BFIZ long /--* t1241 long +--* t1246 long N009 ( 6, 8) [001247] -c--------- t1247 = * LEA(b+(i*1)+0) long /--* t1247 long N010 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort /--* t1248 ushort N012 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 N013 ( 1, 1) [003646] ----------- t3646 = LCL_VAR int V174 cse3 N015 ( 1, 2) [001249] -c--------- t1249 = CNS_INT int 0 $c0 /--* t3646 int +--* t1249 int N016 ( 15, 14) [001250] -c-XG--N--- t1250 = * EQ int /--* t1239 int +--* t1250 int N017 ( 22, 18) [003730] Jc-XG--N--- * AND void N018 ( 24, 20) [001240] ---XG------ * JTRUE void $VN.Void ------------ BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} [003826] ----------- IL_OFFSET void INLRT @ 0x183[E-] N001 ( 0, 0) [003731] ----------- NOP void [003827] ----------- IL_OFFSET void INLRT @ 0x18E[E-] N001 ( 1, 1) [001252] ----------- t1252 = LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] -c--------- t1253 = CNS_INT int 1 $c1 /--* t1252 int +--* t1253 int N003 ( 3, 4) [001254] ----------- t1254 = * ADD int $371 /--* t1254 int N005 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} [003828] ----------- IL_OFFSET void INLRT @ 0x196[E-] N001 ( 1, 1) [001261] ----------- t1261 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- t3695 = LCL_VAR int V179 cse8 u:1 $342 /--* t1261 int +--* t3695 int N003 ( 3, 3) [001266] J------N--- * GE void $36c N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} [003829] ----------- IL_OFFSET void INLRT @ 0x1A1[E-] N001 ( 1, 1) [001341] ----------- t1341 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001342] ----------- t1342 = LCL_VAR int V16 loc12 u:17 $361 /--* t1342 int N003 ( 2, 3) [001343] -c--------- t1343 = * CAST long <- int $3c8 N004 ( 1, 2) [001345] -c--------- t1345 = CNS_INT long 1 $204 /--* t1343 long +--* t1345 long N005 ( 4, 6) [001346] -c--------- t1346 = * BFIZ long /--* t1341 long +--* t1346 long N006 ( 6, 8) [001347] -c--------- t1347 = * LEA(b+(i*1)+0) long /--* t1347 long N007 ( 9, 10) [001348] ---XG------ t1348 = * IND ushort /--* t1348 ushort N009 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 N010 ( 1, 1) [003650] ----------- t3650 = LCL_VAR int V174 cse3 N012 ( 1, 2) [001349] -c--------- t1349 = CNS_INT int 48 $d8 /--* t3650 int +--* t1349 int N013 ( 12, 14) [001350] J--XG--N--- * EQ void N014 ( 14, 16) [001351] ---XG------ * JTRUE void $311 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} [003830] ----------- IL_OFFSET void INLRT @ 0x1AE[E-] N001 ( 1, 1) [001268] ----------- t1268 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] -c--------- t1269 = CNS_INT int 1 $c1 /--* t1268 int +--* t1269 int N003 ( 3, 4) [001270] ----------- t1270 = * ADD int $371 N004 ( 1, 1) [003696] ----------- t3696 = LCL_VAR int V179 cse8 u:1 $342 /--* t1270 int +--* t3696 int N005 ( 5, 6) [001275] J------N--- * GE void $681 N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} [003831] ----------- IL_OFFSET void INLRT @ 0x1BB[E-] N001 ( 1, 1) [001277] ----------- t1277 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001278] ----------- t1278 = LCL_VAR int V16 loc12 u:17 $361 /--* t1278 int N003 ( 2, 3) [001279] -c--------- t1279 = * CAST long <- int $3c8 N004 ( 1, 2) [001281] -c--------- t1281 = CNS_INT long 1 $204 /--* t1279 long +--* t1281 long N005 ( 4, 6) [001282] -c--------- t1282 = * BFIZ long /--* t1277 long +--* t1282 long N006 ( 6, 8) [001283] -c--------- t1283 = * LEA(b+(i*1)+0) long /--* t1283 long N007 ( 9, 10) [001284] ---XG------ t1284 = * IND ushort /--* t1284 ushort N009 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 N010 ( 1, 1) [003654] ----------- t3654 = LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] -c--------- t1285 = CNS_INT int 43 $d9 /--* t3654 int +--* t1285 int N013 ( 12, 14) [001286] J--XG--N--- * EQ void N014 ( 14, 16) [001287] ---XG------ * JTRUE void $311 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} [003832] ----------- IL_OFFSET void INLRT @ 0x1C8[E-] N001 ( 1, 1) [003656] ----------- t3656 = LCL_VAR int V174 cse3 N002 ( 1, 2) [001338] -c--------- t1338 = CNS_INT int 45 $da /--* t3656 int +--* t1338 int N003 ( 3, 4) [001339] N---G--N-U- * NE void N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} [003833] ----------- IL_OFFSET void INLRT @ 0x1D5[E-] N001 ( 1, 1) [001288] ----------- t1288 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001289] ----------- t1289 = LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] -c--------- t1290 = CNS_INT int 1 $c1 /--* t1289 int +--* t1290 int N004 ( 3, 4) [001291] ----------- t1291 = * ADD int $371 /--* t1291 int N005 ( 4, 6) [001292] -c--------- t1292 = * CAST long <- int $3cb N006 ( 1, 2) [001294] -c--------- t1294 = CNS_INT long 1 $204 /--* t1292 long +--* t1294 long N007 ( 6, 9) [001295] -c--------- t1295 = * BFIZ long /--* t1288 long +--* t1295 long N008 ( 8, 11) [001296] -c--------- t1296 = * LEA(b+(i*1)+0) long /--* t1296 long N009 ( 11, 13) [001297] ---XG------ t1297 = * IND ushort N010 ( 1, 2) [001298] -c--------- t1298 = CNS_INT int 48 $d8 /--* t1297 ushort +--* t1298 int N011 ( 13, 16) [001299] N--XG--N-U- * NE void N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} [003834] ----------- IL_OFFSET void INLRT @ 0x1E4[E-] N001 ( 1, 1) [001301] ----------- t1301 = LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] -c--------- t1302 = CNS_INT int 1 $c1 /--* t1301 int +--* t1302 int N003 ( 3, 4) [001303] ----------- t1303 = * ADD int $942 /--* t1303 int N005 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 N001 ( 1, 1) [001307] ----------- t1307 = LCL_VAR int V73 tmp33 u:1 $942 /--* t1307 int N003 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 N001 ( 1, 1) [001306] ----------- t1306 = LCL_VAR int V16 loc12 u:19 (last use) $942 N002 ( 1, 1) [003697] ----------- t3697 = LCL_VAR int V179 cse8 u:1 $342 /--* t1306 int +--* t3697 int N003 ( 3, 3) [001314] J------N--- * GE void $943 N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} [003835] ----------- IL_OFFSET void INLRT @ 0x1F4[E-] N001 ( 1, 1) [001319] ----------- t1319 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001320] ----------- t1320 = LCL_VAR int V16 loc12 u:19 $942 /--* t1320 int N003 ( 2, 3) [001321] -c--------- t1321 = * CAST long <- int $3e1 N004 ( 1, 2) [001323] -c--------- t1323 = CNS_INT long 1 $204 /--* t1321 long +--* t1323 long N005 ( 4, 6) [001324] -c--------- t1324 = * BFIZ long /--* t1319 long +--* t1324 long N006 ( 6, 8) [001325] -c--------- t1325 = * LEA(b+(i*1)+0) long /--* t1325 long N007 ( 9, 10) [001326] ---XG------ t1326 = * IND ushort N008 ( 1, 2) [001327] -c--------- t1327 = CNS_INT int 48 $d8 /--* t1326 ushort +--* t1327 int N009 ( 11, 13) [001328] J--XG--N--- * EQ void N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} [003836] ----------- IL_OFFSET void INLRT @ 0x201[E-] N001 ( 1, 2) [002613] ----------- t2613 = CNS_INT int 1 $c1 /--* t2613 int N003 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB255(2),BB256(2)} succs={BB48,BB50} [003837] ----------- IL_OFFSET void INLRT @ 0x204[E-] N001 ( 1, 1) [000073] ----------- t73 = LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- t3698 = LCL_VAR int V179 cse8 u:1 $342 /--* t73 int +--* t3698 int N003 ( 3, 3) [000078] J------N--- * GE void $360 N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} [003838] ----------- IL_OFFSET void INLRT @ 0x20F[E-] N001 ( 1, 1) [001198] ----------- t1198 = LCL_VAR int V16 loc12 u:2 $28b /--* t1198 int N003 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 [003839] ----------- IL_OFFSET void INLRT @ 0x20F[E-] N001 ( 1, 1) [001199] ----------- t1199 = LCL_VAR int V71 tmp31 u:1 (last use) $28b N002 ( 1, 2) [001200] -c--------- t1200 = CNS_INT int 1 $c1 /--* t1199 int +--* t1200 int N003 ( 3, 4) [001201] ----------- t1201 = * ADD int $361 /--* t1201 int N005 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 N001 ( 1, 1) [001197] ----------- t1197 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001206] ----------- t1206 = LCL_VAR int V71 tmp31 u:1 (last use) $28b /--* t1206 int N003 ( 2, 3) [001207] -c--------- t1207 = * CAST long <- int $3c5 N004 ( 1, 2) [001209] -c--------- t1209 = CNS_INT long 1 $204 /--* t1207 long +--* t1209 long N005 ( 4, 6) [001210] -c--------- t1210 = * BFIZ long /--* t1197 long +--* t1210 long N006 ( 6, 8) [001211] -c--------- t1211 = * LEA(b+(i*1)+0) long /--* t1211 long N007 ( 9, 10) [001212] ---XG------ t1212 = * IND ushort /--* t1212 ushort N009 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 N001 ( 1, 1) [001216] ----------- t1216 = LCL_VAR int V72 tmp32 u:1 /--* t1216 int N003 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 N001 ( 1, 1) [001215] ----------- t1215 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001219] -c--------- t1219 = CNS_INT int 0 $c0 /--* t1215 int +--* t1219 int N003 ( 3, 4) [001220] CEQ-------N--- * JCMP void ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} [003840] ----------- IL_OFFSET void INLRT @ 0x222[E-] N001 ( 1, 1) [001222] ----------- t1222 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] -c--------- t1223 = CNS_INT int 59 $d1 /--* t1222 int +--* t1223 int N003 ( 3, 4) [001224] N------N-U- * NE void N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} [003841] ----------- IL_OFFSET void INLRT @ 0x22B[E-] N001 ( 1, 2) [000081] -c--------- t81 = CNS_INT long 0 $205 /--* t81 long N003 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 [003842] ----------- IL_OFFSET void INLRT @ 0x22F[E-] N001 ( 1, 1) [000084] ----------- t84 = LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] -c--------- t85 = CNS_INT int 0 $c0 /--* t84 int +--* t85 int N003 ( 3, 4) [000086] J------N--- * GE void $690 N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void ------------ BB51 [233..235), preds={BB50} succs={BB52} [003843] ----------- IL_OFFSET void INLRT @ 0x233[E-] N001 ( 1, 1) [001194] ----------- t1194 = LCL_VAR int V04 loc0 u:2 $28a /--* t1194 int N003 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} [003844] ----------- IL_OFFSET void INLRT @ 0x235[E-] N001 ( 1, 1) [000088] ----------- t88 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] -c--------- t89 = CNS_INT int 0 $c0 /--* t88 int +--* t89 int N003 ( 3, 4) [000090] J------N--- * LT void $692 N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} [003845] ----------- IL_OFFSET void INLRT @ 0x23A[E-] N001 ( 1, 1) [001180] ----------- t1180 = LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- t1181 = LCL_VAR int V05 loc1 u:3 $28d /--* t1180 int +--* t1181 int N003 ( 3, 3) [001182] N------N-U- * NE void $696 N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} [003846] ----------- IL_OFFSET void INLRT @ 0x23F[E-] N001 ( 1, 1) [001187] ----------- t1187 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 1) [001188] ----------- t1188 = LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- t1189 = CNS_INT int 3 $c3 /--* t1188 int +--* t1189 int N004 ( 6, 6) [001190] -c--------- t1190 = * MUL int $697 /--* t1187 int +--* t1190 int N005 ( 8, 8) [001191] ----------- t1191 = * SUB int $698 /--* t1191 int N007 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} [003847] ----------- IL_OFFSET void INLRT @ 0x24A[E-] N001 ( 1, 2) [002615] ----------- t2615 = CNS_INT int 1 $c1 /--* t2615 int N003 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} [003848] ----------- IL_OFFSET void INLRT @ 0x24D[E-] N001 ( 1, 1) [000092] ----------- t92 = LCL_VAR long V17 loc13 u:1 /--* t92 long N002 ( 4, 3) [000093] ---XG------ t93 = * IND ubyte N003 ( 1, 2) [000094] -c--------- t94 = CNS_INT int 0 $c0 /--* t93 ubyte +--* t94 int N004 ( 6, 6) [000095] CEQ---XG--N--- * JCMP void ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} [003849] ----------- IL_OFFSET void INLRT @ 0x252[E-] N001 ( 1, 1) [002618] ----------- t2618 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] -c--------- t2619 = CNS_INT long 4 $207 /--* t2618 byref +--* t2619 long N003 ( 3, 4) [002620] -----O----- t2620 = * ADD byref $24a /--* t2620 byref N005 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 N001 ( 1, 1) [001131] ----------- t1131 = LCL_VAR byref V69 tmp29 u:1 $24a /--* t1131 byref N002 ( 3, 2) [001132] n---GO----- t1132 = * IND int N003 ( 1, 1) [001133] ----------- t1133 = LCL_VAR int V13 loc9 u:3 (last use) $28e /--* t1132 int +--* t1133 int N004 ( 5, 4) [001134] ----GO----- t1134 = * ADD int N005 ( 1, 1) [001130] ----------- t1130 = LCL_VAR byref V69 tmp29 u:1 (last use) $24a /--* t1130 byref +--* t1134 int [003850] -A--GO----- * STOREIND int [003851] ----------- IL_OFFSET void INLRT @ 0x25E[E-] N001 ( 1, 1) [001137] ----------- t1137 = LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] -c--------- t1138 = CNS_INT int 0 $c0 /--* t1137 int +--* t1138 int N003 ( 3, 4) [001139] CNE-------N--- * JCMP void ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} [003852] ----------- IL_OFFSET void INLRT @ 0x262[E-] N001 ( 1, 1) [001171] ----------- t1171 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1171 byref N003 ( 3, 4) [002623] -c--------- t2623 = * LEA(b+4) byref /--* t2623 byref N004 ( 4, 3) [001172] n---GO----- t1172 = * IND int N005 ( 1, 1) [001173] ----------- t1173 = LCL_VAR int V04 loc0 u:2 $28a /--* t1172 int +--* t1173 int N006 ( 6, 5) [001174] ----GO----- t1174 = * ADD int N007 ( 1, 1) [001175] ----------- t1175 = LCL_VAR int V05 loc1 u:3 $28d /--* t1174 int +--* t1175 int N008 ( 8, 7) [001176] ----GO----- t1176 = * SUB int /--* t1176 int N010 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} [003853] ----------- IL_OFFSET void INLRT @ 0x26E[E-] N001 ( 1, 1) [001141] ----------- t1141 = LCL_VAR int V04 loc0 u:2 $28a /--* t1141 int N003 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} [003854] ----------- IL_OFFSET void INLRT @ 0x271[E-] N001 ( 1, 1) [001145] ----------- t1145 = LCL_VAR int V70 tmp30 u:1 (last use) $291 /--* t1145 int [004213] ----------- t4213 = * PUTARG_REG int REG x1 N002 ( 1, 1) [001148] ----------- t1148 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1148 byref [004214] ----------- t4214 = * PUTARG_REG byref REG x0 N003 ( 2, 8) [002624] H---------- t2624 = CNS_INT(h) long 0x400000000046acb8 ftn $45 /--* t2624 long [004215] ----------- t4215 = * PUTARG_REG long REG x11 N004 ( 1, 2) [001150] ----------- t1150 = CNS_INT int 0 $c0 /--* t1150 int [004216] ----------- t4216 = * PUTARG_REG int REG x2 /--* t4213 int arg2 in x1 +--* t4214 byref arg1 in x0 +--* t4215 long r2r cell in x11 +--* t4216 int arg3 in x2 N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void [003855] ----------- IL_OFFSET void INLRT @ 0x27A[E-] N001 ( 1, 1) [001152] ----------- t1152 = LCL_VAR long V17 loc13 u:1 /--* t1152 long N002 ( 4, 3) [001153] ---XG------ t1153 = * IND ubyte N003 ( 1, 2) [001154] -c--------- t1154 = CNS_INT int 0 $c0 /--* t1153 ubyte +--* t1154 int N004 ( 6, 6) [001155] CNE---XG--N--- * JCMP void ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} [003856] ----------- IL_OFFSET void INLRT @ 0x27F[E-] N001 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3713 byref [004217] ----------- t4217 = * PUTARG_REG byref REG x0 N002 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] $3ce /--* t2628 long [004218] ----------- t4218 = * PUTARG_REG long REG x1 /--* t4217 byref +--* t4218 long N003 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct $142 N004 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2625 long [004219] ----------- t4219 = * PUTARG_REG long REG x11 N005 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 $c2 /--* t1158 int [004220] ----------- t4220 = * PUTARG_REG int REG x2 /--* t2626 struct arg1 x0,x1 +--* t4219 long r2r cell in x11 +--* t4220 int arg2 in x2 N006 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int $2c4 /--* t1159 int N008 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 [003857] ----------- IL_OFFSET void INLRT @ 0x288[E-] N001 ( 1, 1) [001164] ----------- t1164 = LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- t1165 = LCL_VAR int V15 loc11 u:2 $283 /--* t1164 int +--* t1165 int N003 ( 3, 3) [001166] J------N--- * EQ void $6b6 N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} [003858] ----------- IL_OFFSET void INLRT @ 0x28E[E-] N001 ( 1, 1) [001168] ----------- t1168 = LCL_VAR int V16 loc12 u:16 (last use) $2c4 /--* t1168 int N003 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} [003859] ----------- IL_OFFSET void INLRT @ 0x297[E-] N001 ( 1, 1) [000097] ----------- t97 = LCL_VAR byref V01 arg1 u:1 $101 /--* t97 byref N003 ( 3, 4) [002630] -c--------- t2630 = * LEA(b+10) byref /--* t2630 byref N004 ( 5, 4) [000098] n---GO----- t98 = * IND ubyte N005 ( 1, 2) [000099] -c--------- t99 = CNS_INT int 3 $c3 /--* t98 ubyte +--* t99 int N006 ( 7, 7) [000100] J---GO-N--- * EQ void N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} [003860] ----------- IL_OFFSET void INLRT @ 0x2A0[E-] N001 ( 1, 1) [001122] ----------- t1122 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1122 byref N003 ( 3, 4) [002632] -c--------- t2632 = * LEA(b+8) byref N005 ( 1, 2) [001123] -c--------- t1123 = CNS_INT int 0 $c0 /--* t2632 byref +--* t1123 int [003861] -A--GO----- * STOREIND bool ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} [003862] ----------- IL_OFFSET void INLRT @ 0x2A7[E-] N001 ( 1, 1) [000102] ----------- t102 = LCL_VAR byref V01 arg1 u:1 $101 /--* t102 byref N003 ( 3, 4) [002634] -c--------- t2634 = * LEA(b+4) byref N005 ( 1, 2) [000103] -c--------- t103 = CNS_INT int 0 $c0 /--* t2634 byref +--* t103 int [003863] -A--GO----- * STOREIND int ------------ BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} [003864] ----------- IL_OFFSET void INLRT @ 0x2AE[E-] N001 ( 0, 0) [003778] ----------- NOP void [003865] ----------- IL_OFFSET void INLRT @ 0x2B2[E-] N001 ( 1, 1) [000106] ----------- t106 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- t107 = LCL_VAR int V05 loc1 u:3 $28d /--* t106 int +--* t107 int N003 ( 3, 3) [000108] Jc-----N--- t108 = * LT int $6b7 N004 ( 1, 1) [000110] ----------- t110 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- t111 = LCL_VAR int V06 loc2 u:2 (last use) $284 /--* t110 int +--* t111 int N006 ( 3, 3) [000112] ----------- t112 = * SUB int $6b8 N007 ( 1, 2) [001118] -c--------- t1118 = CNS_INT int 0 $c0 /--* t108 int +--* t112 int +--* t1118 int N008 ( 8, 9) [003777] ----------- t3777 = * SELECT int /--* t3777 int N010 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 [003866] ----------- IL_OFFSET void INLRT @ 0x2B5[E-] N001 ( 0, 0) [003779] ----------- NOP void N001 ( 3, 2) [000116] ----------- t116 = LCL_VAR int V44 tmp4 u:1 (last use) $292 /--* t116 int N003 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 [003867] ----------- IL_OFFSET void INLRT @ 0x2B9[E-] N001 ( 0, 0) [003775] ----------- NOP void [003868] ----------- IL_OFFSET void INLRT @ 0x2BD[E-] N001 ( 1, 1) [000119] ----------- t119 = LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- t120 = LCL_VAR int V05 loc1 u:3 $28d /--* t119 int +--* t120 int N003 ( 3, 3) [000121] Jc-----N--- t121 = * GT int $6b9 N004 ( 1, 1) [000123] ----------- t123 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- t124 = LCL_VAR int V07 loc3 u:2 (last use) $285 /--* t123 int +--* t124 int N006 ( 3, 3) [000125] ----------- t125 = * SUB int $6ba N007 ( 1, 2) [001114] -c--------- t1114 = CNS_INT int 0 $c0 /--* t121 int +--* t125 int +--* t1114 int N008 ( 8, 9) [003774] ----------- t3774 = * SELECT int /--* t3774 int N010 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 [003869] ----------- IL_OFFSET void INLRT @ 0x2C0[E-] N001 ( 0, 0) [003776] ----------- NOP void N001 ( 3, 2) [000129] ----------- t129 = LCL_VAR int V45 tmp5 u:1 (last use) $293 /--* t129 int N003 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 [003870] ----------- IL_OFFSET void INLRT @ 0x2C4[E-] N001 ( 1, 1) [000132] ----------- t132 = LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] -c--------- t133 = CNS_INT int 0 $c0 /--* t132 int +--* t133 int N003 ( 3, 4) [000134] CEQ-------N--- * JCMP void ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} [003871] ----------- IL_OFFSET void INLRT @ 0x2C8[E-] N001 ( 1, 1) [001108] ----------- t1108 = LCL_VAR int V05 loc1 u:3 $28d /--* t1108 int N003 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 [003872] ----------- IL_OFFSET void INLRT @ 0x2CB[E-] N001 ( 1, 2) [001111] -c--------- t1111 = CNS_INT int 0 $c0 /--* t1111 int N003 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 ------------ BB74 [2D0..2EE), preds={BB66} succs={BB78} [003873] ----------- IL_OFFSET void INLRT @ 0x2D0[E-] N001 ( 0, 0) [003772] ----------- NOP void [003874] ----------- IL_OFFSET void INLRT @ 0x2D9[E-] N001 ( 1, 1) [000136] ----------- t136 = LCL_VAR byref V01 arg1 u:1 $101 /--* t136 byref N003 ( 3, 4) [002636] -c--------- t2636 = * LEA(b+4) byref /--* t2636 byref N004 ( 4, 3) [000137] n---GO----- t137 = * IND int /--* t137 int N006 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 N007 ( 3, 2) [003684] ----------- t3684 = LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- t138 = LCL_VAR int V05 loc1 u:3 $28d /--* t3684 int +--* t138 int N010 ( 13, 10) [000139] Jc--GO-N--- t139 = * GT int N011 ( 3, 2) [003686] ----------- t3686 = LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- t1104 = LCL_VAR int V05 loc1 u:3 $28d /--* t139 int +--* t3686 int +--* t1104 int N013 ( 18, 14) [003771] ----GO----- t3771 = * SELECT int /--* t3771 int N015 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 [003875] ----------- IL_OFFSET void INLRT @ 0x2DC[E-] N001 ( 0, 0) [003773] ----------- NOP void N001 ( 3, 2) [000146] ----------- t146 = LCL_VAR int V46 tmp6 u:1 (last use) $295 /--* t146 int N003 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 [003876] ----------- IL_OFFSET void INLRT @ 0x2E4[E-] N001 ( 3, 2) [003687] ----------- t3687 = LCL_VAR int V178 cse7 u:1 N002 ( 1, 1) [000151] ----------- t151 = LCL_VAR int V05 loc1 u:3 $28d /--* t3687 int +--* t151 int N003 ( 5, 4) [000152] ----G------ t152 = * SUB int /--* t152 int N005 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB74} succs={BB79,BB103} [003877] ----------- IL_OFFSET void INLRT @ 0x2EE[E-] N001 ( 1, 1) [000155] ----------- t155 = LCL_VAR int V15 loc11 u:2 $283 /--* t155 int N003 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 [003878] ----------- IL_OFFSET void INLRT @ 0x2F2[E-] [003879] ----------- IL_OFFSET void INL09 @ 0x01F[E-] <- INLRT @ ??? N001 ( 3, 3) [001550] ----------- t1550 = LCL_VAR_ADDR long V47 tmp7 $740 /--* t1550 long N003 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 [003880] ----------- IL_OFFSET void INL09 @ 0x026[E-] <- INLRT @ ??? N001 ( 1, 2) [001556] ----------- t1556 = CNS_INT int 4 $c8 /--* t1556 int N003 ( 1, 3) [001558] DA--------- * STORE_LCL_VAR int V152 tmp112 d:1 [003881] ----------- IL_OFFSET void INLRT @ 0x2FF[E-] N001 ( 1, 1) [002649] ----------- t2649 = LCL_VAR byref V151 tmp111 u:1 (last use) $24b /--* t2649 byref N003 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 N004 ( 1, 2) [003720] ----------- t3720 = CNS_INT int 4 $c8 /--* t3720 int N006 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 [003882] ----------- IL_OFFSET void INLRT @ 0x303[E-] N001 ( 1, 2) [000175] ----------- t175 = CNS_INT int -1 $c4 /--* t175 int N003 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 [003883] ----------- IL_OFFSET void INLRT @ 0x306[E-] N001 ( 1, 1) [000941] ----------- t941 = LCL_VAR ref V03 arg3 u:1 $180 /--* t941 ref N003 ( 3, 4) [002656] -c--------- t2656 = * LEA(b+56) byref /--* t2656 byref N004 ( 4, 3) [001570] ---XG------ t1570 = * IND ref /--* t1570 ref [004156] -c--------- t4156 = * LEA(b+8) byref /--* t4156 byref N005 ( 6, 5) [000944] ---XG------ t944 = * IND int N006 ( 1, 2) [000945] -c--------- t945 = CNS_INT int 0 $c0 /--* t944 int +--* t945 int N007 ( 11, 8) [000946] -c-XG--N--- t946 = * LE int N008 ( 1, 1) [000178] ----------- t178 = LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] -c--------- t179 = CNS_INT int 0 $c0 /--* t178 int +--* t179 int N010 ( 6, 4) [000180] -c-----N--- t180 = * EQ int $70a /--* t946 int +--* t180 int N011 ( 18, 13) [003732] Jc-XG--N--- * AND void N012 ( 20, 15) [000181] ---XG------ * JTRUE void $VN.Void ------------ BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} [003884] ----------- IL_OFFSET void INLRT @ 0x30D[E-] N001 ( 0, 0) [003733] ----------- NOP void [003885] ----------- IL_OFFSET void INLRT @ 0x31E[E-] N001 ( 1, 1) [000948] ----------- t948 = LCL_VAR ref V03 arg3 u:1 $180 /--* t948 ref N003 ( 3, 4) [002658] -c--------- t2658 = * LEA(b+8) byref /--* t2658 byref N004 ( 4, 3) [000949] n---GO----- t949 = * IND ref /--* t949 ref N006 ( 4, 3) [000951] DA--GO----- * STORE_LCL_VAR ref V26 loc22 d:1 [003886] ----------- IL_OFFSET void INLRT @ 0x326[E-] N001 ( 1, 2) [000952] -c--------- t952 = CNS_INT int 0 $c0 /--* t952 int N003 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 [003887] ----------- IL_OFFSET void INLRT @ 0x329[E-] N001 ( 1, 2) [000955] -c--------- t955 = CNS_INT int 0 $c0 /--* t955 int N003 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 [003888] ----------- IL_OFFSET void INLRT @ 0x32C[E-] N001 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 /--* t958 ref [004158] -c--------- t4158 = * LEA(b+8) byref /--* t4158 byref N002 ( 3, 3) [000959] ---X------- t959 = * IND int /--* t959 int N004 ( 3, 3) [000961] DA-X------- * STORE_LCL_VAR int V29 loc25 d:1 [003889] ----------- IL_OFFSET void INLRT @ 0x332[E-] N001 ( 1, 1) [000962] ----------- t962 = LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] -c--------- t963 = CNS_INT int 0 $c0 /--* t962 int +--* t963 int N003 ( 3, 4) [000964] CEQ-------N--- * JCMP void ------------ BB81 [336..33D), preds={BB79} succs={BB82} [003890] ----------- IL_OFFSET void INLRT @ 0x336[E-] N002 ( 1, 1) [002659] ----------- t2659 = LCL_VAR ref V26 loc22 u:1 /--* t2659 ref N004 ( 1, 1) [002667] -c--------- t2667 = * LEA(b+16) byref /--* t2667 byref N006 ( 4, 3) [002671] n---GO----- t2671 = * IND int /--* t2671 int N009 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} [003891] ----------- IL_OFFSET void INLRT @ 0x33D[E-] N001 ( 1, 1) [000966] ----------- t966 = LCL_VAR int V28 loc24 u:2 $298 /--* t966 int N003 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 N001 ( 1, 1) [000969] ----------- t969 = LCL_VAR int V08 loc4 u:1 $297 /--* t969 int N003 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 [003892] ----------- IL_OFFSET void INLRT @ 0x341[E-] N001 ( 1, 1) [000970] ----------- t970 = LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] -c--------- t971 = CNS_INT int 0 $c0 /--* t970 int +--* t971 int N003 ( 3, 4) [000972] J------N--- * LT void $719 N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} N001 ( 3, 2) [000977] ----------- t977 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t977 int N003 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 N001 ( 1, 2) [001091] -c--------- t1091 = CNS_INT int 0 $c0 /--* t1091 int N003 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} N001 ( 3, 2) [000978] ----------- t978 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t978 int N003 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 N001 ( 1, 1) [000979] ----------- t979 = LCL_VAR int V14 loc10 u:1 $296 /--* t979 int N003 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 ------------ BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} N001 ( 3, 2) [000986] ----------- t986 = LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- t987 = LCL_VAR int V66 tmp26 u:1 (last use) $299 /--* t986 int +--* t987 int N003 ( 7, 5) [000988] ----------- t988 = * ADD int $71a /--* t988 int N005 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 [003893] ----------- IL_OFFSET void INLRT @ 0x350[E-] N001 ( 0, 0) [003769] ----------- NOP void [003894] ----------- IL_OFFSET void INLRT @ 0x355[E-] N001 ( 1, 1) [000991] ----------- t991 = LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- t992 = LCL_VAR int V31 loc27 u:1 $71a /--* t991 int +--* t992 int N003 ( 5, 4) [000993] Jc-----N--- t993 = * GT int $71b N004 ( 1, 1) [000995] ----------- t995 = LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- t1087 = LCL_VAR int V31 loc27 u:1 (last use) $71a /--* t993 int +--* t995 int +--* t1087 int N006 ( 10, 8) [003768] ----------- t3768 = * SELECT int /--* t3768 int N008 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 [003895] ----------- IL_OFFSET void INLRT @ 0x359[E-] N001 ( 0, 0) [003770] ----------- NOP void N001 ( 3, 2) [000999] ----------- t999 = LCL_VAR int V67 tmp27 u:1 (last use) $29a /--* t999 int N003 ( 3, 3) [001001] DA--------- * STORE_LCL_VAR int V32 loc28 d:1 [003896] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] N001 ( 1, 1) [003158] ----------- t3158 = LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- t3159 = LCL_VAR int V30 loc26 u:1 $298 /--* t3158 int +--* t3159 int N003 ( 3, 3) [003157] J------N--- * LE void $71c N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void ------------ BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} [003897] ----------- IL_OFFSET void INLRT @ 0x35E[E-] N001 ( 1, 1) [001006] ----------- t1006 = LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] -c--------- t1007 = CNS_INT int 0 $c0 /--* t1006 int +--* t1007 int N003 ( 3, 4) [001008] CEQ-------N--- * JCMP void ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} [003898] ----------- IL_OFFSET void INLRT @ 0x362[E-] N001 ( 1, 1) [001010] ----------- t1010 = LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] -c--------- t1011 = CNS_INT int 1 $c1 /--* t1010 int +--* t1011 int N003 ( 3, 4) [001012] ----------- t1012 = * ADD int $71f /--* t1012 int N005 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 [003899] ----------- IL_OFFSET void INLRT @ 0x368[E-] N001 ( 1, 1) [001015] ----------- t1015 = LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- t1574 = LCL_VAR int V144 tmp104 u:3 $29c /--* t1015 int +--* t1574 int N003 ( 3, 3) [001020] J------N--- * LT void $720 N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} [003900] ----------- IL_OFFSET void INLRT @ 0x373[E-] N001 ( 1, 1) [001578] ----------- t1578 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] -c--------- t1065 = CNS_INT int 1 $c1 /--* t1578 int +--* t1065 int N003 ( 3, 4) [001066] ----------- t1066 = * LSH int $721 /--* t1066 int N004 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int $3cf /--* t1067 long [004221] ----------- t4221 = * PUTARG_REG long REG x0 N005 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn $49 /--* t2672 long [004222] ----------- t4222 = * PUTARG_REG long REG x11 /--* t4221 long arg1 in x0 +--* t4222 long r2r cell in x11 N006 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 /--* t1068 ref N008 ( 20, 18) [001070] DA-XG------ * STORE_LCL_VAR ref V33 loc29 d:1 [003901] ----------- IL_OFFSET void INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] [003902] ----------- IL_OFFSET void INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001 ( 1, 1) [002689] ----------- t2689 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] -c--------- t2690 = CNS_INT long 16 Fseq[] $200 /--* t2689 ref +--* t2690 long N003 ( 3, 4) [002691] -----O----- t2691 = * ADD byref $253 /--* t2691 byref N005 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 [003903] ----------- IL_OFFSET void INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001 ( 1, 1) [001607] ----------- t1607 = LCL_VAR ref V33 loc29 u:1 $800 /--* t1607 ref [004160] -c--------- t4160 = * LEA(b+8) byref /--* t4160 byref N002 ( 3, 3) [001608] ---X------- t1608 = * IND int $2cc /--* t1608 int N004 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 N001 ( 1, 1) [002694] ----------- t2694 = LCL_VAR byref V159 tmp119 u:1 (last use) $382 /--* t2694 byref N003 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 N001 ( 1, 1) [001620] ----------- t1620 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- t1647 = LCL_VAR int V160 tmp120 u:1 (last use) $2a0 /--* t1620 int +--* t1647 int N003 ( 3, 3) [001628] N------N-U- * GT void $722 N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void ------------ BB95 [000..392), preds={BB91} succs={BB100} [003904] ----------- IL_OFFSET void INL17 @ 0x00F[E-] <- INLRT @ ??? N001 ( 1, 1) [001639] ----------- t1639 = LCL_VAR int V144 tmp104 u:3 (last use) $29c /--* t1639 int N002 ( 2, 3) [001640] ---------U- t1640 = * CAST long <- ulong <- uint $3d0 /--* t1640 long N004 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 [003905] ----------- IL_OFFSET void INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? N001 ( 1, 1) [001663] ----------- t1663 = LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] -c--------- t1665 = CNS_INT long 2 $20a /--* t1663 long +--* t1665 long N003 ( 3, 4) [001666] ----------- t1666 = * LSH long $3d1 /--* t1666 long [004223] ----------- t4223 = * PUTARG_REG long REG x2 N004 ( 1, 1) [001661] ----------- t1661 = LCL_VAR byref V161 tmp121 u:1 (last use) $382 /--* t1661 byref [004224] ----------- t4224 = * PUTARG_REG byref REG x0 N005 ( 1, 1) [001662] ----------- t1662 = LCL_VAR byref V143 tmp103 u:3 (last use) $381 /--* t1662 byref [004225] ----------- t4225 = * PUTARG_REG byref REG x1 N006 ( 2, 8) [002700] H---------- t2700 = CNS_INT(h) long 0x4000000000420490 ftn $4b /--* t2700 long [004226] ----------- t4226 = * PUTARG_REG long REG x11 /--* t4223 long arg3 in x2 +--* t4224 byref arg1 in x0 +--* t4225 byref arg2 in x1 +--* t4226 long r2r cell in x11 N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void [003906] ----------- IL_OFFSET void INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] [003907] ----------- IL_OFFSET void INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001 ( 1, 1) [002718] ----------- t2718 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] -c--------- t2719 = CNS_INT long 16 Fseq[] $200 /--* t2718 ref +--* t2719 long N003 ( 3, 4) [002720] -----O----- t2720 = * ADD byref $253 /--* t2720 byref N005 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 [003908] ----------- IL_OFFSET void INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 (last use) $800 /--* t1719 ref [004162] -c--------- t4162 = * LEA(b+8) byref /--* t4162 byref N002 ( 3, 3) [001720] ---X------- t1720 = * IND int $2cc /--* t1720 int N004 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 [003909] ----------- IL_OFFSET void INLRT @ 0x391[E-] N001 ( 1, 1) [002723] ----------- t2723 = LCL_VAR byref V163 tmp123 u:1 (last use) $383 /--* t2723 byref N003 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 N004 ( 1, 1) [002726] ----------- t2726 = LCL_VAR int V164 tmp124 u:1 (last use) $2a1 /--* t2726 int N006 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} [003910] ----------- IL_OFFSET void INLRT @ 0x39A[E-] N001 ( 1, 1) [001024] ----------- t1024 = LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- t1028 = LCL_VAR int V144 tmp104 u:4 $2a2 /--* t1024 int +--* t1028 int N003 ( 6, 9) [001029] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $334 N004 ( 1, 1) [001033] ----------- t1033 = LCL_VAR byref V143 tmp103 u:4 $384 N005 ( 1, 1) [001025] ----------- t1025 = LCL_VAR int V20 loc16 u:11 $71f /--* t1025 int N006 ( 2, 3) [001030] -c-------U- t1030 = * CAST long <- uint $3d2 N007 ( 1, 2) [001031] -c--------- t1031 = CNS_INT long 2 $20a /--* t1030 long +--* t1031 long N008 ( 4, 6) [001032] -c--------- t1032 = * BFIZ long /--* t1033 byref +--* t1032 long N009 ( 6, 8) [001034] -c--------- t1034 = * LEA(b+(i*1)+0) byref N012 ( 1, 1) [001036] ----------- t1036 = LCL_VAR int V28 loc24 u:3 $29f /--* t1034 byref +--* t1036 int [003911] -A-XGO----- * STOREIND int [003912] ----------- IL_OFFSET void INLRT @ 0x3A6[E-] N001 ( 1, 1) [001039] ----------- t1039 = LCL_VAR int V27 loc23 u:2 $29e N002 ( 1, 1) [001040] ----------- t1040 = LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] -c--------- t1041 = CNS_INT int -1 $c4 /--* t1040 int +--* t1041 int N004 ( 3, 4) [001042] ----------- t1042 = * ADD int /--* t1039 int +--* t1042 int N005 ( 5, 6) [001043] J------N--- * GE void N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} [003913] ----------- IL_OFFSET void INLRT @ 0x3AE[E-] N001 ( 1, 1) [001050] ----------- t1050 = LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] -c--------- t1051 = CNS_INT int 1 $c1 /--* t1050 int +--* t1051 int N003 ( 3, 4) [001052] ----------- t1052 = * ADD int $727 /--* t1052 int N005 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 [003914] ----------- IL_OFFSET void INLRT @ 0x3B4[E-] N001 ( 1, 1) [001056] ----------- t1056 = LCL_VAR int V27 loc23 u:4 $727 N002 ( 1, 1) [001055] ----------- t1055 = LCL_VAR ref V26 loc22 u:1 /--* t1055 ref [004164] -c--------- t4164 = * LEA(b+8) byref /--* t4164 byref N003 ( 3, 3) [002732] ---X------- t2732 = * IND int /--* t1056 int +--* t2732 int N004 ( 8, 11) [002733] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N005 ( 1, 1) [002730] ----------- t2730 = LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] -c--------- t2737 = CNS_INT long 16 $200 /--* t2730 ref +--* t2737 long N007 ( 3, 4) [002738] ----------- t2738 = * ADD byref N008 ( 1, 1) [002731] ----------- t2731 = LCL_VAR int V27 loc23 u:4 $727 /--* t2731 int N009 ( 2, 3) [002734] -c-------U- t2734 = * CAST long <- uint $3d4 N010 ( 1, 2) [002735] -c-----N--- t2735 = CNS_INT long 2 $20a /--* t2734 long +--* t2735 long N011 ( 4, 6) [002736] -c--------- t2736 = * BFIZ long /--* t2738 byref +--* t2736 long N012 ( 7, 10) [002739] -c--------- t2739 = * LEA(b+(i*1)+0) byref /--* t2739 byref N014 ( 10, 12) [002742] n---GO----- t2742 = * IND int /--* t2742 int N017 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} [003915] ----------- IL_OFFSET void INLRT @ 0x3BB[E-] N001 ( 1, 1) [001045] ----------- t1045 = LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- t1046 = LCL_VAR int V30 loc26 u:3 $2a3 /--* t1045 int +--* t1046 int N003 ( 3, 3) [001047] ----------- t1047 = * ADD int $72b /--* t1047 int N005 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 [003916] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] N001 ( 1, 1) [001002] ----------- t1002 = LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- t1003 = LCL_VAR int V28 loc24 u:4 $72b /--* t1002 int +--* t1003 int N003 ( 3, 3) [001004] J------N--- * GT void $72c N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB85,BB89,BB102} succs={BB104,BB112} [003917] ----------- IL_OFFSET void INLRT @ 0x3C8[E-] N001 ( 1, 1) [000182] ----------- t182 = LCL_VAR byref V01 arg1 u:1 $101 /--* t182 byref N003 ( 3, 4) [002744] -c--------- t2744 = * LEA(b+8) byref /--* t2744 byref N004 ( 5, 4) [000183] n---GO----- t183 = * IND bool N005 ( 1, 2) [000184] -c--------- t184 = CNS_INT int 0 $c0 /--* t183 bool +--* t184 int N006 ( 10, 7) [000185] -c--GO-N--- t185 = * EQ int N007 ( 1, 1) [000927] ----------- t927 = LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] -c--------- t928 = CNS_INT int 0 $c0 /--* t927 int +--* t928 int N009 ( 6, 4) [000929] -c-----N--- t929 = * NE int $733 /--* t185 int +--* t929 int N010 ( 17, 12) [003734] Jc--GO-N--- * AND void N011 ( 19, 14) [000186] ----GO----- * JTRUE void $301 ------------ BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} [003918] ----------- IL_OFFSET void INLRT @ 0x3D0[E-] N001 ( 0, 0) [003735] ----------- NOP void [003919] ----------- IL_OFFSET void INLRT @ 0x3D4[E-] N001 ( 1, 1) [000931] ----------- t931 = LCL_VAR byref V01 arg1 u:1 $101 /--* t931 byref N003 ( 3, 4) [002746] -c--------- t2746 = * LEA(b+4) byref /--* t2746 byref N004 ( 4, 3) [000932] n---GO----- t932 = * IND int N005 ( 1, 2) [000933] -c--------- t933 = CNS_INT int 0 $c0 /--* t932 int +--* t933 int N006 ( 6, 6) [000934] CEQ----GO-N--- * JCMP void ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} [003920] ----------- IL_OFFSET void INLRT @ 0x3DC[E-] N001 ( 1, 1) [000937] ----------- t937 = LCL_VAR ref V03 arg3 u:1 $180 /--* t937 ref N003 ( 3, 4) [002748] -c--------- t2748 = * LEA(b+40) byref /--* t2748 byref N004 ( 4, 3) [001730] ---XG------ t1730 = * IND ref /--* t1730 ref N006 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 [003921] ----------- IL_OFFSET void INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001732] ----------- t1732 = LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] -c--------- t1733 = CNS_INT ref null $VN.Null /--* t1732 ref +--* t1733 ref N003 ( 3, 4) [001734] CEQ-------N--- * JCMP void ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} [003922] ----------- IL_OFFSET void INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [000936] ----------- t936 = LCL_VAR byref V00 arg0 u:1 $100 /--* t936 byref N003 ( 3, 4) [002750] -c--------- t2750 = * LEA(b+8) byref /--* t2750 byref N004 ( 4, 3) [001736] ---XG------ t1736 = * IND int /--* t1736 int N006 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 [003923] ----------- IL_OFFSET void INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001739] ----------- t1739 = LCL_VAR ref V86 tmp46 u:1 /--* t1739 ref [004166] -c--------- t4166 = * LEA(b+8) byref /--* t4166 byref N002 ( 3, 3) [001740] ---X------- t1740 = * IND int N003 ( 1, 2) [001741] -c--------- t1741 = CNS_INT int 1 $c1 /--* t1740 int +--* t1741 int N004 ( 8, 6) [001742] Nc-X---N-U- t1742 = * NE int N005 ( 3, 2) [001747] ----------- t1747 = LCL_VAR int V87 tmp47 u:1 N006 ( 1, 1) [001748] ----------- t1748 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1748 byref N008 ( 3, 4) [002754] -c--------- t2754 = * LEA(b+24) byref /--* t2754 byref N009 ( 4, 3) [001786] n---GO----- t1786 = * IND int /--* t1747 int +--* t1786 int N010 ( 11, 6) [001752] Nc--GO-N-U- t1752 = * GE int /--* t1742 int +--* t1752 int N011 ( 20, 13) [003736] Jc-XGO-N--- * AND void N012 ( 22, 15) [001743] ---XGO----- * JTRUE void ------------ BB108 [3DC..3DD), preds={BB107} succs={BB112} [003924] ----------- IL_OFFSET void INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] N001 ( 0, 0) [003737] ----------- NOP void [003925] ----------- IL_OFFSET void INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [002758] ----------- t2758 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] -c--------- t2759 = CNS_INT long 16 $200 /--* t2758 byref +--* t2759 long N003 ( 3, 4) [002760] -----O----- t2760 = * ADD byref $25c /--* t2760 byref N005 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 [003926] ----------- IL_OFFSET void INL26 @ ??? <- INLRT @ 0x3DC[E-] N001 ( 3, 2) [001756] ----------- t1756 = LCL_VAR int V87 tmp47 u:1 N002 ( 1, 1) [001761] ----------- t1761 = LCL_VAR byref V88 tmp48 u:1 $25c /--* t1761 byref N004 ( 3, 4) [002763] -c--------- t2763 = * LEA(b+8) byref /--* t2763 byref N005 ( 4, 3) [001762] n---GO----- t1762 = * IND int /--* t1756 int +--* t1762 int N006 ( 11, 12) [001763] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001760] ----------- t1760 = LCL_VAR byref V88 tmp48 u:1 (last use) $25c /--* t1760 byref N008 ( 3, 2) [001767] n---GO----- t1767 = * IND byref N009 ( 3, 2) [001757] ----------- t1757 = LCL_VAR int V87 tmp47 u:1 /--* t1757 int N010 ( 4, 4) [001764] -c-------U- t1764 = * CAST long <- uint N011 ( 1, 2) [001765] -c--------- t1765 = CNS_INT long 1 $204 /--* t1764 long +--* t1765 long N012 ( 6, 7) [001766] ----------- t1766 = * BFIZ long /--* t1767 byref +--* t1766 long N013 ( 10, 10) [001768] ----GO-N--- t1768 = * ADD byref N017 ( 1, 1) [002765] ----------- t2765 = LCL_VAR ref V86 tmp46 u:1 (last use) /--* t2765 ref N019 ( 1, 1) [002772] -c--------- t2772 = * LEA(b+12) byref /--* t2772 byref N021 ( 5, 4) [002777] n---GO----- t2777 = * IND ushort /--* t1768 byref +--* t2777 ushort [003927] -A-XGO----- * STOREIND short [003928] ----------- IL_OFFSET void INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] N001 ( 3, 2) [001777] ----------- t1777 = LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] -c--------- t1778 = CNS_INT int 1 $c1 /--* t1777 int +--* t1778 int N003 ( 5, 5) [001779] ----------- t1779 = * ADD int N004 ( 1, 1) [001776] ----------- t1776 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1776 byref N006 ( 3, 4) [002779] -c--------- t2779 = * LEA(b+8) byref /--* t2779 byref +--* t1779 int [003929] -A--GO----- * STOREIND int ------------ BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} [003930] ----------- IL_OFFSET void INLRT @ 0x3E8[E-] N001 ( 1, 2) [002781] -c--------- t2781 = CNS_INT int 0 $c0 /--* t2781 int N003 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 [003931] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] N001 ( 1, 1) [003714] ----------- t3714 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3714 byref N003 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 [003932] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] N001 ( 1, 1) [001792] ----------- t1792 = LCL_VAR byref V165 tmp125 u:1 $246 /--* t1792 byref N003 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 [003933] ----------- IL_OFFSET void INLRT @ 0x3F3[E-] N001 ( 1, 1) [000197] ----------- t197 = LCL_VAR byref V165 tmp125 u:1 (last use) $246 /--* t197 byref N003 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 N004 ( 1, 1) [002791] ----------- t2791 = LCL_VAR long V169 tmp129 u:1 (last use) $3c4 /--* t2791 long N007 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 [003934] ----------- IL_OFFSET void INLRT @ 0x3F8[E-] N001 ( 1, 1) [000201] ----------- t201 = LCL_VAR long V17 loc13 u:1 /--* t201 long N003 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB258} succs={BB246,BB248} [003935] ----------- IL_OFFSET void INLRT @ 0x7AA[E-] N001 ( 1, 1) [000204] ----------- t204 = LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- t3707 = LCL_VAR int V179 cse8 u:1 $342 /--* t204 int +--* t3707 int N003 ( 3, 3) [000209] J------N--- * GE void $897 N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} [003936] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] N001 ( 1, 1) [000243] ----------- t243 = LCL_VAR int V16 loc12 u:4 $2ae /--* t243 int N003 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 [003937] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] N001 ( 1, 1) [000244] ----------- t244 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae N002 ( 1, 2) [000245] -c--------- t245 = CNS_INT int 1 $c1 /--* t244 int +--* t245 int N003 ( 3, 4) [000246] ----------- t246 = * ADD int $898 /--* t246 int N005 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 N001 ( 1, 1) [000242] ----------- t242 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000251] ----------- t251 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae /--* t251 int N003 ( 2, 3) [000252] -c--------- t252 = * CAST long <- int $3db N004 ( 1, 2) [000254] -c--------- t254 = CNS_INT long 1 $204 /--* t252 long +--* t254 long N005 ( 4, 6) [000255] -c--------- t255 = * BFIZ long /--* t242 long +--* t255 long N006 ( 6, 8) [000256] -c--------- t256 = * LEA(b+(i*1)+0) long /--* t256 long N007 ( 9, 10) [000257] ---XG------ t257 = * IND ushort /--* t257 ushort N009 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 N001 ( 1, 1) [000261] ----------- t261 = LCL_VAR int V50 tmp10 u:1 /--* t261 int N003 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 N001 ( 1, 1) [000260] ----------- t260 = LCL_VAR int V18 loc14 u:1 (last use) N002 ( 1, 2) [000264] -c--------- t264 = CNS_INT int 0 $c0 /--* t260 int +--* t264 int N003 ( 3, 4) [000265] CEQ-------N--- * JCMP void ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} [003938] ----------- IL_OFFSET void INLRT @ 0x7C8[E-] N001 ( 1, 1) [000267] ----------- t267 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] -c--------- t268 = CNS_INT int 59 $d1 /--* t267 int +--* t268 int N003 ( 3, 4) [000269] N------N-U- * NE void N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} [003939] ----------- IL_OFFSET void INLRT @ 0x7D1[E-] N001 ( 1, 2) [000212] -c--------- t212 = CNS_INT long 0 $205 /--* t212 long N003 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 [003940] ----------- IL_OFFSET void INLRT @ 0x7D5[E-] N001 ( 1, 1) [000215] ----------- t215 = LCL_VAR byref V01 arg1 u:1 $101 /--* t215 byref N003 ( 3, 4) [003148] -c--------- t3148 = * LEA(b+8) byref /--* t3148 byref N004 ( 5, 4) [000216] n---GO----- t216 = * IND bool N005 ( 1, 2) [000217] -c--------- t217 = CNS_INT int 0 $c0 /--* t216 bool +--* t217 int N006 ( 10, 7) [000218] -c--GO-N--- t218 = * EQ int N007 ( 1, 1) [000221] ----------- t221 = LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] -c--------- t222 = CNS_INT int 0 $c0 /--* t221 int +--* t222 int N009 ( 6, 4) [000223] -c-----N--- t223 = * NE int $733 /--* t218 int +--* t223 int N010 ( 17, 12) [003764] Jc--GO-N--- * AND void N011 ( 19, 14) [000219] ----GO----- * JTRUE void $301 ------------ BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} [003941] ----------- IL_OFFSET void INLRT @ 0x7DD[E-] N001 ( 0, 0) [003765] ----------- NOP void [003942] ----------- IL_OFFSET void INLRT @ 0x7E1[E-] N001 ( 1, 1) [000225] ----------- t225 = LCL_VAR byref V01 arg1 u:1 (last use) $101 /--* t225 byref N003 ( 3, 4) [003150] -c--------- t3150 = * LEA(b+4) byref /--* t3150 byref N004 ( 4, 3) [000226] n---GO----- t226 = * IND int N005 ( 1, 2) [000227] -c--------- t227 = CNS_INT int 0 $c0 /--* t226 int +--* t227 int N006 ( 9, 6) [000228] ----GO-N--- t228 = * NE int N007 ( 1, 1) [000230] ----------- t230 = LCL_VAR byref V00 arg0 u:1 $100 /--* t230 byref N009 ( 3, 4) [003152] -c--------- t3152 = * LEA(b+8) byref /--* t3152 byref N010 ( 4, 3) [002539] ---XG------ t2539 = * IND int N011 ( 1, 2) [000233] -c--------- t233 = CNS_INT int 0 $c0 /--* t2539 int +--* t233 int N012 ( 9, 6) [000234] ---XG--N--- t234 = * LE int /--* t228 int +--* t234 int N013 ( 19, 13) [003766] J--XGO-N--- t3766 = * AND int /--* t3766 int N014 ( 21, 15) [000229] ---XGO----- * JTRUE void $301 ------------ BB251 [7E9..7FF), preds={BB249} succs={BB253} [003943] ----------- IL_OFFSET void INLRT @ 0x7E9[E-] N001 ( 0, 0) [003767] ----------- NOP void [003944] ----------- IL_OFFSET void INLRT @ 0x7F2[E-] N001 ( 1, 1) [000238] ----------- t238 = LCL_VAR ref V03 arg3 u:1 (last use) $180 /--* t238 ref N003 ( 3, 4) [003155] -c--------- t3155 = * LEA(b+40) byref /--* t3155 byref N004 ( 4, 3) [002541] ---XG------ t2541 = * IND ref /--* t2541 ref [004227] ---XG------ t4227 = * PUTARG_REG ref REG x2 N005 ( 1, 1) [000236] ----------- t236 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t236 byref [004228] ----------- t4228 = * PUTARG_REG byref REG x0 N006 ( 2, 8) [003153] H---------- t3153 = CNS_INT(h) long 0x4000000000540210 ftn $51 /--* t3153 long [004229] ----------- t4229 = * PUTARG_REG long REG x11 N007 ( 1, 2) [000237] ----------- t237 = CNS_INT int 0 $c0 /--* t237 int [004230] ----------- t4230 = * PUTARG_REG int REG x1 /--* t4227 ref arg3 in x2 +--* t4228 byref this in x0 +--* t4229 long r2r cell in x11 +--* t4230 int arg2 in x1 N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} [003945] ----------- IL_OFFSET void INLRT @ 0x7FF[E-] N001 ( 0, 0) [000220] ----------- RETURN void $VN.Void ------------ BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} [003946] ----------- IL_OFFSET void INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001744] ----------- t1744 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1744 byref [004231] ----------- t4231 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001745] ----------- t1745 = LCL_VAR ref V86 tmp46 u:1 (last use) /--* t1745 ref [004232] ----------- t4232 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002780] H---------- t2780 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2780 long [004233] ----------- t4233 = * PUTARG_REG long REG x11 /--* t4231 byref this in x0 +--* t4232 ref arg2 in x1 +--* t4233 long r2r cell in x11 N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} [003947] ----------- IL_OFFSET void INLRT @ 0x401[E-] N001 ( 1, 1) [000271] ----------- t271 = LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] -c--------- t272 = CNS_INT int 0 $c0 /--* t271 int +--* t272 int N003 ( 3, 4) [000273] J------N--- * LE void $89f N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} [003948] ----------- IL_OFFSET void INLRT @ 0x406[E-] N001 ( 1, 1) [000821] ----------- t821 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] -c--------- t822 = CNS_INT int 35 $ea /--* t821 int +--* t822 int N003 ( 6, 4) [000823] -c-----N--- t823 = * EQ int N004 ( 1, 1) [000919] ----------- t919 = LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- t920 = CNS_INT int 46 $eb /--* t919 int +--* t920 int N006 ( 6, 4) [000921] -c-----N--- t921 = * EQ int /--* t823 int +--* t921 int N007 ( 13, 9) [003738] Jc-----N--- * AND void N008 ( 15, 11) [000824] ----------- * JTRUE void $VN.Void ------------ BB115 [40C..418) -> BB135 (cond), preds={BB114} succs={BB117,BB135} [003949] ----------- IL_OFFSET void INLRT @ 0x40C[E-] N001 ( 0, 0) [003739] ----------- NOP void [003950] ----------- IL_OFFSET void INLRT @ 0x412[E-] N001 ( 1, 1) [000923] ----------- t923 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] -c--------- t924 = CNS_INT int 48 $d8 /--* t923 int +--* t924 int N003 ( 3, 4) [000925] J------N--- * EQ void N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void ------------ BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} N001 ( 1, 1) [000829] ----------- t829 = LCL_VAR byref V00 arg0 u:1 $100 /--* t829 byref N003 ( 1, 3) [000836] DA--------- * STORE_LCL_VAR byref V60 tmp20 d:1 [003951] ----------- IL_OFFSET void INLRT @ 0x41A[E-] N001 ( 1, 1) [000830] ----------- t830 = LCL_VAR long V36 loc32 u:7 $904 /--* t830 long N002 ( 4, 3) [000831] ---XG------ t831 = * IND ubyte /--* t831 ubyte N004 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 N005 ( 1, 1) [003679] ----------- t3679 = LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] -c--------- t832 = CNS_INT int 0 $c0 /--* t3679 int +--* t832 int N008 ( 7, 7) [000833] CNE---XG--N--- * JCMP void ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} N001 ( 1, 1) [000838] ----------- t838 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t838 byref N003 ( 1, 3) [000914] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:3 N001 ( 1, 2) [000912] ----------- t912 = CNS_INT int 48 $d8 /--* t912 int N003 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 ------------ BB120 [424..42C), preds={BB118} succs={BB121} N001 ( 1, 1) [000840] ----------- t840 = LCL_VAR long V36 loc32 u:7 $904 /--* t840 long N003 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 N001 ( 1, 1) [000841] ----------- t841 = LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] -c--------- t843 = CNS_INT long 1 $204 /--* t841 long +--* t843 long N003 ( 3, 4) [000844] ----------- t844 = * ADD long $adc /--* t844 long N005 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 N001 ( 1, 1) [000839] ----------- t839 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t839 byref N003 ( 1, 3) [000852] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:2 N001 ( 1, 1) [003681] ----------- t3681 = LCL_VAR int V177 cse6 u:1 /--* t3681 int N003 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} N001 ( 1, 1) [000858] ----------- t858 = LCL_VAR int V63 tmp23 u:1 (last use) $b16 /--* t858 int N002 ( 2, 3) [001796] ----------- t1796 = * CAST int <- ushort <- int $c75 /--* t1796 int N004 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 [003952] ----------- IL_OFFSET void INL29 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000857] ----------- t857 = LCL_VAR byref V00 arg0 u:1 $100 /--* t857 byref N003 ( 3, 4) [002795] -c--------- t2795 = * LEA(b+8) byref /--* t2795 byref N004 ( 4, 3) [001797] ---XG------ t1797 = * IND int /--* t1797 int N006 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 [003953] ----------- IL_OFFSET void INL29 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [001800] ----------- t1800 = LCL_VAR int V91 tmp51 u:1 N002 ( 1, 1) [001801] ----------- t1801 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1801 byref N004 ( 3, 4) [002799] -c--------- t2799 = * LEA(b+24) byref /--* t2799 byref N005 ( 4, 3) [001839] n---GO----- t1839 = * IND int /--* t1800 int +--* t1839 int N006 ( 6, 5) [001805] N---GO-N-U- * GE void N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} [003954] ----------- IL_OFFSET void INL29 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [002803] ----------- t2803 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] -c--------- t2804 = CNS_INT long 16 $200 /--* t2803 byref +--* t2804 long N003 ( 3, 4) [002805] -----O----- t2805 = * ADD byref $25c /--* t2805 byref N005 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 N001 ( 1, 1) [001812] ----------- t1812 = LCL_VAR int V91 tmp51 u:1 N002 ( 1, 1) [001817] ----------- t1817 = LCL_VAR byref V93 tmp53 u:1 $25c /--* t1817 byref N004 ( 3, 4) [002808] -c--------- t2808 = * LEA(b+8) byref /--* t2808 byref N005 ( 4, 3) [001818] n---GO----- t1818 = * IND int /--* t1812 int +--* t1818 int N006 ( 9, 11) [001819] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001816] ----------- t1816 = LCL_VAR byref V93 tmp53 u:1 (last use) $25c /--* t1816 byref N008 ( 3, 2) [001823] n---GO----- t1823 = * IND byref N009 ( 1, 1) [001813] ----------- t1813 = LCL_VAR int V91 tmp51 u:1 /--* t1813 int N010 ( 2, 3) [001820] -c-------U- t1820 = * CAST long <- uint N011 ( 1, 2) [001821] -c--------- t1821 = CNS_INT long 1 $204 /--* t1820 long +--* t1821 long N012 ( 4, 6) [001822] -c--------- t1822 = * BFIZ long /--* t1823 byref +--* t1822 long N013 ( 8, 9) [001824] -c--------- t1824 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [001826] ----------- t1826 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 /--* t1824 byref +--* t1826 int [003955] -A-XGO----- * STOREIND short [003956] ----------- IL_OFFSET void INL29 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [001830] ----------- t1830 = LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] -c--------- t1831 = CNS_INT int 1 $c1 /--* t1830 int +--* t1831 int N003 ( 3, 4) [001832] ----------- t1832 = * ADD int N004 ( 1, 1) [001829] ----------- t1829 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t1829 byref N006 ( 3, 4) [002811] -c--------- t2811 = * LEA(b+8) byref /--* t2811 byref +--* t1832 int [003957] -A--GO----- * STOREIND int ------------ BB123 [000..000), preds={BB121} succs={BB124} [003958] ----------- IL_OFFSET void INL29 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [001807] ----------- t1807 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t1807 byref [004234] ----------- t4234 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001808] ----------- t1808 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 /--* t1808 int [004235] ----------- t4235 = * PUTARG_REG int REG x1 N003 ( 2, 8) [002812] H---------- t2812 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2812 long [004236] ----------- t4236 = * PUTARG_REG long REG x11 /--* t4234 byref this in x0 +--* t4235 int arg2 in x1 +--* t4236 long r2r cell in x11 N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} [003959] ----------- IL_OFFSET void INLRT @ 0x431[E-] N001 ( 1, 1) [000860] ----------- t860 = LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] -c--------- t861 = CNS_INT int 0 $c0 /--* t860 int +--* t861 int N003 ( 6, 4) [000862] -c-----N--- t862 = * EQ int $70a N004 ( 1, 1) [000874] ----------- t874 = LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] -c--------- t875 = CNS_INT int 1 $c1 /--* t874 int +--* t875 int N006 ( 6, 4) [000876] -c-----N--- t876 = * LE int $d03 /--* t862 int +--* t876 int N007 ( 13, 9) [003740] Jc-----N--- * AND void N008 ( 15, 11) [000863] ----------- * JTRUE void $VN.Void ------------ BB125 [435..43F) -> BB134 (cond), preds={BB124} succs={BB127,BB134} [003960] ----------- IL_OFFSET void INLRT @ 0x435[E-] N001 ( 0, 0) [003741] ----------- NOP void [003961] ----------- IL_OFFSET void INLRT @ 0x43A[E-] N001 ( 1, 1) [000885] ----------- t885 = LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- t889 = LCL_VAR int V144 tmp104 u:2 $2a6 /--* t885 int +--* t889 int N003 ( 6, 9) [000890] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $c31 N004 ( 1, 1) [000894] ----------- t894 = LCL_VAR byref V143 tmp103 u:2 $385 N005 ( 1, 1) [000886] ----------- t886 = LCL_VAR int V20 loc16 u:7 $b13 /--* t886 int N006 ( 2, 3) [000891] -c-------U- t891 = * CAST long <- uint $ae2 N007 ( 1, 2) [000892] -c--------- t892 = CNS_INT long 2 $20a /--* t891 long +--* t892 long N008 ( 4, 6) [000893] -c--------- t893 = * BFIZ long /--* t894 byref +--* t893 long N009 ( 6, 8) [000895] -c--------- t895 = * LEA(b+(i*1)+0) byref /--* t895 byref N010 ( 8, 9) [002813] ---XGO----- t2813 = * IND int N012 ( 1, 2) [000898] -c--------- t898 = CNS_INT int 1 $c1 /--* t2813 int +--* t898 int N013 ( 16, 21) [000899] ---XGO----- t899 = * ADD int N014 ( 1, 1) [000882] ----------- t882 = LCL_VAR int V08 loc4 u:5 $b15 /--* t899 int +--* t882 int N015 ( 21, 23) [000900] Nc-XGO-N-U- t900 = * NE int N016 ( 1, 1) [000878] ----------- t878 = LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] -c--------- t879 = CNS_INT int 0 $c0 /--* t878 int +--* t879 int N018 ( 6, 4) [000880] -c-----N--- t880 = * LT int $d04 /--* t900 int +--* t880 int N019 ( 28, 28) [003742] Jc-XGO-N--- * AND void N020 ( 30, 30) [000881] ---XGO----- * JTRUE void $VN.Void ------------ BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} [003962] ----------- IL_OFFSET void INLRT @ 0x43F[E-] N001 ( 0, 0) [003743] ----------- NOP void [003963] ----------- IL_OFFSET void INLRT @ 0x44F[E-] N001 ( 1, 1) [000903] ----------- t903 = LCL_VAR ref V03 arg3 u:1 $180 /--* t903 ref N003 ( 3, 4) [002815] -c--------- t2815 = * LEA(b+56) byref /--* t2815 byref N004 ( 4, 3) [001843] ---XG------ t1843 = * IND ref /--* t1843 ref N006 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 [003964] ----------- IL_OFFSET void INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001845] ----------- t1845 = LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] -c--------- t1846 = CNS_INT ref null $VN.Null /--* t1845 ref +--* t1846 ref N003 ( 3, 4) [001847] CEQ-------N--- * JCMP void ------------ BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} [003965] ----------- IL_OFFSET void INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [000902] ----------- t902 = LCL_VAR byref V00 arg0 u:1 $100 /--* t902 byref N003 ( 3, 4) [002817] -c--------- t2817 = * LEA(b+8) byref /--* t2817 byref N004 ( 4, 3) [001849] n---GO----- t1849 = * IND int /--* t1849 int N006 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 [003966] ----------- IL_OFFSET void INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 /--* t1852 ref [004168] -c--------- t4168 = * LEA(b+8) byref /--* t4168 byref N002 ( 3, 3) [001853] ---X------- t1853 = * IND int /--* t1853 int N004 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 N005 ( 1, 1) [003717] ----------- t3717 = LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] -c--------- t1854 = CNS_INT int 1 $c1 /--* t3717 int +--* t1854 int N008 ( 9, 7) [001855] Nc-X---N-U- t1855 = * NE int N009 ( 1, 1) [001860] ----------- t1860 = LCL_VAR int V96 tmp56 u:1 N010 ( 1, 1) [001861] ----------- t1861 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1861 byref N012 ( 3, 4) [002821] -c--------- t2821 = * LEA(b+24) byref /--* t2821 byref N013 ( 4, 3) [001899] n---GO----- t1899 = * IND int /--* t1860 int +--* t1899 int N014 ( 9, 5) [001865] Nc--GO-N-U- t1865 = * GE int /--* t1855 int +--* t1865 int N015 ( 19, 13) [003744] Jc-XGO-N--- * AND void N016 ( 21, 15) [001856] ---XGO----- * JTRUE void ------------ BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} [003967] ----------- IL_OFFSET void INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] N001 ( 0, 0) [003745] ----------- NOP void [003968] ----------- IL_OFFSET void INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [002825] ----------- t2825 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] -c--------- t2826 = CNS_INT long 16 $200 /--* t2825 byref +--* t2826 long N003 ( 3, 4) [002827] -----O----- t2827 = * ADD byref $25c /--* t2827 byref N005 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 [003969] ----------- IL_OFFSET void INL32 @ ??? <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001869] ----------- t1869 = LCL_VAR int V96 tmp56 u:1 N002 ( 1, 1) [001874] ----------- t1874 = LCL_VAR byref V97 tmp57 u:1 $25c /--* t1874 byref N004 ( 3, 4) [002830] -c--------- t2830 = * LEA(b+8) byref /--* t2830 byref N005 ( 4, 3) [001875] n---GO----- t1875 = * IND int /--* t1869 int +--* t1875 int N006 ( 9, 11) [001876] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001873] ----------- t1873 = LCL_VAR byref V97 tmp57 u:1 (last use) $25c /--* t1873 byref N008 ( 3, 2) [001880] n---GO----- t1880 = * IND byref N009 ( 1, 1) [001870] ----------- t1870 = LCL_VAR int V96 tmp56 u:1 /--* t1870 int N010 ( 2, 3) [001877] -c-------U- t1877 = * CAST long <- uint N011 ( 1, 2) [001878] -c--------- t1878 = CNS_INT long 1 $204 /--* t1877 long +--* t1878 long N012 ( 4, 6) [001879] ----------- t1879 = * BFIZ long /--* t1880 byref +--* t1879 long N013 ( 8, 9) [001881] ----GO-N--- t1881 = * ADD byref N016 ( 1, 2) [001884] -c--------- t1884 = CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- t3719 = LCL_VAR int V181 cse10 u:1 /--* t1884 int +--* t3719 int N018 ( 6, 10) [002835] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N019 ( 1, 1) [002832] ----------- t2832 = LCL_VAR ref V95 tmp55 u:1 (last use) /--* t2832 ref N021 ( 1, 1) [002839] -c--------- t2839 = * LEA(b+12) byref /--* t2839 byref N023 ( 5, 4) [002844] n---GO----- t2844 = * IND ushort /--* t1881 byref +--* t2844 ushort [003970] -A-XGO----- * STOREIND short [003971] ----------- IL_OFFSET void INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001890] ----------- t1890 = LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] -c--------- t1891 = CNS_INT int 1 $c1 /--* t1890 int +--* t1891 int N003 ( 3, 4) [001892] ----------- t1892 = * ADD int N004 ( 1, 1) [001889] ----------- t1889 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1889 byref N006 ( 3, 4) [002846] -c--------- t2846 = * LEA(b+8) byref /--* t2846 byref +--* t1892 int [003972] -A--GO----- * STOREIND int ------------ BB132 [44F..450), preds={BB129} succs={BB133} [003973] ----------- IL_OFFSET void INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001857] ----------- t1857 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1857 byref [004237] ----------- t4237 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001858] ----------- t1858 = LCL_VAR ref V95 tmp55 u:1 (last use) /--* t1858 ref [004238] ----------- t4238 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002847] H---------- t2847 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2847 long [004239] ----------- t4239 = * PUTARG_REG long REG x11 /--* t4237 byref this in x0 +--* t4238 ref arg2 in x1 +--* t4239 long r2r cell in x11 N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} [003974] ----------- IL_OFFSET void INLRT @ 0x45B[E-] N001 ( 1, 1) [000907] ----------- t907 = LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] -c--------- t908 = CNS_INT int -1 $c4 /--* t907 int +--* t908 int N003 ( 3, 4) [000909] ----------- t909 = * ADD int $d27 /--* t909 int N005 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 ------------ BB134 [461..46D), preds={BB124,BB125,BB133} succs={BB135} [003975] ----------- IL_OFFSET void INLRT @ 0x461[E-] N001 ( 1, 1) [000864] ----------- t864 = LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] -c--------- t865 = CNS_INT int -1 $c4 /--* t864 int +--* t865 int N003 ( 3, 4) [000866] ----------- t866 = * ADD int $d29 /--* t866 int N005 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 [003976] ----------- IL_OFFSET void INLRT @ 0x467[E-] N001 ( 1, 1) [000869] ----------- t869 = LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] -c--------- t870 = CNS_INT int -1 $c4 /--* t869 int +--* t870 int N003 ( 3, 4) [000871] ----------- t871 = * ADD int $d2a /--* t871 int N005 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB134} succs={BB136,BB118} [003977] ----------- IL_OFFSET void INLRT @ 0x46D[E-] N001 ( 1, 1) [000825] ----------- t825 = LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] -c--------- t826 = CNS_INT int 0 $c0 /--* t825 int +--* t826 int N003 ( 3, 4) [000827] J------N--- * GT void $c6e N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} [003978] ----------- IL_OFFSET void INLRT @ 0x472[E-] N001 ( 1, 1) [000275] ----------- t275 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] -c--------- t276 = CNS_INT int 69 $d2 /--* t275 int +--* t276 int N003 ( 3, 4) [000277] N------N-U- * GT void N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void ------------ BB137 [478..478) -> BB138 (cond), preds={BB136} succs={BB257,BB138} [003979] ----------- IL_OFFSET void INLRT @ 0x478[E-] N001 ( 1, 1) [000593] ----------- t593 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] -c--------- t594 = CNS_INT int -34 $d6 /--* t593 int +--* t594 int N003 ( 3, 4) [000595] ----------- t595 = * ADD int /--* t595 int [004241] DA--------- * STORE_LCL_VAR int V184 rat2 N001 ( 3, 2) [004243] ----------- t4243 = LCL_VAR int V184 rat2 N002 ( 1, 2) [004244] -c--------- t4244 = CNS_INT int 5 /--* t4243 int +--* t4244 int N003 ( 8, 5) [004245] ---------U- * GT void N004 ( 10, 7) [004246] ----------- * JTRUE void ------------ BB257 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194 (switch), preds={BB137} succs={BB145,BB186,BB194,BB242} [004247] ----------- t4247 = LCL_VAR int V184 rat2 /--* t4247 int [004248] ---------U- t4248 = * CAST long <- ulong <- uint [004249] ----------- t4249 = JMPTABLE long /--* t4248 long +--* t4249 long [004250] ----------- * SWITCH_TABLE void ------------ BB138 [49A..49A) -> BB139 (cond), preds={BB137} succs={BB258,BB139} [003980] ----------- IL_OFFSET void INLRT @ 0x49A[E-] N001 ( 1, 1) [000597] ----------- t597 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] -c--------- t598 = CNS_INT int -44 $d7 /--* t597 int +--* t598 int N003 ( 3, 4) [000599] ----------- t599 = * ADD int /--* t599 int [004252] DA--------- * STORE_LCL_VAR int V185 rat3 N001 ( 3, 2) [004254] ----------- t4254 = LCL_VAR int V185 rat3 N002 ( 1, 2) [004255] -c--------- t4255 = CNS_INT int 4 /--* t4254 int +--* t4255 int N003 ( 8, 5) [004256] ---------U- * GT void N004 ( 10, 7) [004257] ----------- * JTRUE void ------------ BB258 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145 (switch), preds={BB138} succs={BB145,BB171,BB242,BB245} [004258] ----------- t4258 = LCL_VAR int V185 rat3 /--* t4258 int [004259] ---------U- t4259 = * CAST long <- ulong <- uint [004260] ----------- t4260 = JMPTABLE long /--* t4259 long +--* t4260 long [004261] ----------- * SWITCH_TABLE void ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} [003981] ----------- IL_OFFSET void INLRT @ 0x4B8[E-] N001 ( 1, 1) [000601] ----------- t601 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] -c--------- t602 = CNS_INT int 69 $d2 /--* t601 int +--* t602 int N003 ( 3, 4) [000603] J------N--- * EQ void N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} [003982] ----------- IL_OFFSET void INLRT @ 0x4C6[E-] N001 ( 1, 1) [000279] ----------- t279 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] -c--------- t280 = CNS_INT int 92 $d3 /--* t279 int +--* t280 int N003 ( 3, 4) [000281] J------N--- * EQ void N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} [003983] ----------- IL_OFFSET void INLRT @ 0x4CF[E-] N001 ( 1, 1) [000319] ----------- t319 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] -c--------- t320 = CNS_INT int 101 $d4 /--* t319 int +--* t320 int N003 ( 3, 4) [000321] J------N--- * EQ void N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} [003984] ----------- IL_OFFSET void INLRT @ 0x4D8[E-] N001 ( 1, 1) [000581] ----------- t581 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- t582 = CNS_INT int 0x2030 $d5 /--* t581 int +--* t582 int N003 ( 3, 6) [000583] J------N--- * NE void N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} [003985] ----------- IL_OFFSET void INLRT @ 0x598[E-] N001 ( 1, 1) [000586] ----------- t586 = LCL_VAR ref V03 arg3 u:1 $180 /--* t586 ref N003 ( 3, 4) [002849] -c--------- t2849 = * LEA(b+136) byref /--* t2849 byref N004 ( 4, 3) [002066] ---XG------ t2066 = * IND ref /--* t2066 ref N006 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB257,BB258} succs={BB146,BB150} [003986] ----------- IL_OFFSET void INLRT @ 0x4E9[E-] N001 ( 1, 1) [000639] ----------- t639 = LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] -c--------- t640 = CNS_INT int 0 $c0 /--* t639 int +--* t640 int N003 ( 3, 4) [000641] J------N--- * GE void $9ff N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} [003987] ----------- IL_OFFSET void INLRT @ 0x4EE[E-] N001 ( 1, 1) [000731] ----------- t731 = LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] -c--------- t732 = CNS_INT int 1 $c1 /--* t731 int +--* t732 int N003 ( 3, 4) [000733] ----------- t733 = * ADD int $a88 /--* t733 int N005 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 [003988] ----------- IL_OFFSET void INLRT @ 0x4F4[E-] N001 ( 1, 1) [000736] ----------- t736 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- t737 = LCL_VAR int V06 loc2 u:3 $292 /--* t736 int +--* t737 int N003 ( 3, 3) [000738] J------N--- * LE void $a89 N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} [003989] ----------- IL_OFFSET void INLRT @ 0x4F9[E-] N001 ( 1, 2) [000747] -c--------- t747 = CNS_INT int 0 $c0 /--* t747 int N003 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} [003990] ----------- IL_OFFSET void INLRT @ 0x4FC[E-] N001 ( 1, 2) [000740] ----------- t740 = CNS_INT int 48 $d8 /--* t740 int N003 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} N001 ( 1, 1) [000744] ----------- t744 = LCL_VAR int V58 tmp18 u:1 (last use) $2bd /--* t744 int N002 ( 2, 3) [002850] ----------- t2850 = * CAST int <- ushort <- int $a8a /--* t2850 int N004 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} [003991] ----------- IL_OFFSET void INLRT @ 0x502[E-] N001 ( 1, 1) [000643] ----------- t643 = LCL_VAR long V36 loc32 u:3 $901 /--* t643 long N002 ( 4, 3) [000644] ---XG------ t644 = * IND ubyte N003 ( 1, 2) [000645] -c--------- t645 = CNS_INT int 0 $c0 /--* t644 ubyte +--* t645 int N004 ( 6, 6) [000646] CNE---XG--N--- * JCMP void ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} [003992] ----------- IL_OFFSET void INLRT @ 0x507[E-] N001 ( 1, 1) [000719] ----------- t719 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- t720 = LCL_VAR int V07 loc3 u:3 $293 /--* t719 int +--* t720 int N003 ( 3, 3) [000721] J------N--- * GT void $a86 N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} [003993] ----------- IL_OFFSET void INLRT @ 0x50C[E-] N001 ( 1, 2) [000727] -c--------- t727 = CNS_INT int 0 $c0 /--* t727 int N003 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} [003994] ----------- IL_OFFSET void INLRT @ 0x50F[E-] N001 ( 1, 2) [000723] ----------- t723 = CNS_INT int 48 $d8 /--* t723 int N003 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 ------------ BB154 [513..51B), preds={BB150} succs={BB155} [003995] ----------- IL_OFFSET void INLRT @ 0x513[E-] N001 ( 1, 1) [000648] ----------- t648 = LCL_VAR long V36 loc32 u:3 $901 /--* t648 long N003 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 [003996] ----------- IL_OFFSET void INLRT @ 0x513[E-] N001 ( 1, 1) [000649] ----------- t649 = LCL_VAR long V56 tmp16 u:1 (last use) $901 N002 ( 1, 2) [000651] -c--------- t651 = CNS_INT long 1 $204 /--* t649 long +--* t651 long N003 ( 3, 4) [000652] ----------- t652 = * ADD long $3fb /--* t652 long N005 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 N001 ( 1, 1) [000657] ----------- t657 = LCL_VAR long V56 tmp16 u:1 (last use) $901 /--* t657 long N002 ( 4, 3) [000658] ---XG------ t658 = * IND ubyte /--* t658 ubyte N004 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} N001 ( 1, 1) [000662] ----------- t662 = LCL_VAR int V57 tmp17 u:1 (last use) $2bc /--* t662 int N002 ( 2, 3) [002851] ----------- t2851 = * CAST int <- ushort <- int $a87 /--* t2851 int N004 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} [003997] ----------- IL_OFFSET void INLRT @ 0x51D[E-] N001 ( 1, 1) [000665] ----------- t665 = LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] -c--------- t666 = CNS_INT int 0 $c0 /--* t665 int +--* t666 int N003 ( 3, 4) [000667] CEQ-------N--- * JCMP void ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} [003998] ----------- IL_OFFSET void INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [000674] ----------- t674 = LCL_VAR byref V00 arg0 u:1 $100 /--* t674 byref N003 ( 3, 4) [002853] -c--------- t2853 = * LEA(b+8) byref /--* t2853 byref N004 ( 4, 3) [001903] ---XG------ t1903 = * IND int /--* t1903 int N006 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 [003999] ----------- IL_OFFSET void INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001906] ----------- t1906 = LCL_VAR int V99 tmp59 u:1 N002 ( 1, 1) [001907] ----------- t1907 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1907 byref N004 ( 3, 4) [002857] -c--------- t2857 = * LEA(b+24) byref /--* t2857 byref N005 ( 4, 3) [001942] n---GO----- t1942 = * IND int /--* t1906 int +--* t1942 int N006 ( 6, 5) [001911] N---GO-N-U- * GE void N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} [004000] ----------- IL_OFFSET void INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [002861] ----------- t2861 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] -c--------- t2862 = CNS_INT long 16 $200 /--* t2861 byref +--* t2862 long N003 ( 3, 4) [002863] -----O----- t2863 = * ADD byref $25c /--* t2863 byref N005 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 [004001] ----------- IL_OFFSET void INL34 @ ??? <- INLRT @ 0x521[E-] N001 ( 1, 1) [001917] ----------- t1917 = LCL_VAR int V99 tmp59 u:1 N002 ( 1, 1) [001922] ----------- t1922 = LCL_VAR byref V100 tmp60 u:1 $25c /--* t1922 byref N004 ( 3, 4) [002866] -c--------- t2866 = * LEA(b+8) byref /--* t2866 byref N005 ( 4, 3) [001923] n---GO----- t1923 = * IND int /--* t1917 int +--* t1923 int N006 ( 9, 11) [001924] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001921] ----------- t1921 = LCL_VAR byref V100 tmp60 u:1 (last use) $25c /--* t1921 byref N008 ( 3, 2) [001928] n---GO----- t1928 = * IND byref N009 ( 1, 1) [001918] ----------- t1918 = LCL_VAR int V99 tmp59 u:1 /--* t1918 int N010 ( 2, 3) [001925] -c-------U- t1925 = * CAST long <- uint N011 ( 1, 2) [001926] -c--------- t1926 = CNS_INT long 1 $204 /--* t1925 long +--* t1926 long N012 ( 4, 6) [001927] -c--------- t1927 = * BFIZ long /--* t1928 byref +--* t1927 long N013 ( 8, 9) [001929] -c--------- t1929 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [001931] ----------- t1931 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 /--* t1929 byref +--* t1931 int [004002] -A-XGO----- * STOREIND short [004003] ----------- IL_OFFSET void INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001935] ----------- t1935 = LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] -c--------- t1936 = CNS_INT int 1 $c1 /--* t1935 int +--* t1936 int N003 ( 3, 4) [001937] ----------- t1937 = * ADD int N004 ( 1, 1) [001934] ----------- t1934 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1934 byref N006 ( 3, 4) [002869] -c--------- t2869 = * LEA(b+8) byref /--* t2869 byref +--* t1937 int [004004] -A--GO----- * STOREIND int ------------ BB159 [521..522), preds={BB157} succs={BB160} [004005] ----------- IL_OFFSET void INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001913] ----------- t1913 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1913 byref [004262] ----------- t4262 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000675] ----------- t675 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 /--* t675 int [004263] ----------- t4263 = * PUTARG_REG int REG x1 N003 ( 2, 8) [002870] H---------- t2870 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2870 long [004264] ----------- t4264 = * PUTARG_REG long REG x11 /--* t4262 byref this in x0 +--* t4263 int arg2 in x1 +--* t4264 long r2r cell in x11 N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} [004006] ----------- IL_OFFSET void INLRT @ 0x529[E-] N001 ( 1, 1) [000677] ----------- t677 = LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] -c--------- t678 = CNS_INT int 0 $c0 /--* t677 int +--* t678 int N003 ( 6, 4) [000679] -c-----N--- t679 = * EQ int $70a N004 ( 1, 1) [000681] ----------- t681 = LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] -c--------- t682 = CNS_INT int 1 $c1 /--* t681 int +--* t682 int N006 ( 6, 4) [000683] -c-----N--- t683 = * LE int $a93 /--* t679 int +--* t683 int N007 ( 13, 9) [003746] Jc-----N--- * AND void N008 ( 15, 11) [000680] ----------- * JTRUE void $VN.Void ------------ BB161 [52D..537) -> BB170 (cond), preds={BB160} succs={BB163,BB170} [004007] ----------- IL_OFFSET void INLRT @ 0x52D[E-] N001 ( 0, 0) [003747] ----------- NOP void [004008] ----------- IL_OFFSET void INLRT @ 0x532[E-] N001 ( 1, 1) [000692] ----------- t692 = LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- t696 = LCL_VAR int V144 tmp104 u:2 $2a6 /--* t692 int +--* t696 int N003 ( 6, 9) [000697] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $a34 N004 ( 1, 1) [000701] ----------- t701 = LCL_VAR byref V143 tmp103 u:2 $385 N005 ( 1, 1) [000693] ----------- t693 = LCL_VAR int V20 loc16 u:4 $2b3 /--* t693 int N006 ( 2, 3) [000698] -c-------U- t698 = * CAST long <- uint $ac0 N007 ( 1, 2) [000699] -c--------- t699 = CNS_INT long 2 $20a /--* t698 long +--* t699 long N008 ( 4, 6) [000700] -c--------- t700 = * BFIZ long /--* t701 byref +--* t700 long N009 ( 6, 8) [000702] -c--------- t702 = * LEA(b+(i*1)+0) byref /--* t702 byref N010 ( 8, 9) [002871] ---XGO----- t2871 = * IND int N012 ( 1, 2) [000705] -c--------- t705 = CNS_INT int 1 $c1 /--* t2871 int +--* t705 int N013 ( 16, 21) [000706] ---XGO----- t706 = * ADD int N014 ( 1, 1) [000689] ----------- t689 = LCL_VAR int V08 loc4 u:3 $2b5 /--* t706 int +--* t689 int N015 ( 21, 23) [000707] Nc-XGO-N-U- t707 = * NE int N016 ( 1, 1) [000685] ----------- t685 = LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] -c--------- t686 = CNS_INT int 0 $c0 /--* t685 int +--* t686 int N018 ( 6, 4) [000687] -c-----N--- t687 = * LT int $a94 /--* t707 int +--* t687 int N019 ( 28, 28) [003748] Jc-XGO-N--- * AND void N020 ( 30, 30) [000688] ---XGO----- * JTRUE void $VN.Void ------------ BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} [004009] ----------- IL_OFFSET void INLRT @ 0x537[E-] N001 ( 0, 0) [003749] ----------- NOP void [004010] ----------- IL_OFFSET void INLRT @ 0x547[E-] N001 ( 1, 1) [000710] ----------- t710 = LCL_VAR ref V03 arg3 u:1 $180 /--* t710 ref N003 ( 3, 4) [002873] -c--------- t2873 = * LEA(b+56) byref /--* t2873 byref N004 ( 4, 3) [001946] ---XG------ t1946 = * IND ref /--* t1946 ref N006 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 [004011] ----------- IL_OFFSET void INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001948] ----------- t1948 = LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] -c--------- t1949 = CNS_INT ref null $VN.Null /--* t1948 ref +--* t1949 ref N003 ( 3, 4) [001950] CEQ-------N--- * JCMP void ------------ BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} [004012] ----------- IL_OFFSET void INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [000709] ----------- t709 = LCL_VAR byref V00 arg0 u:1 $100 /--* t709 byref N003 ( 3, 4) [002875] -c--------- t2875 = * LEA(b+8) byref /--* t2875 byref N004 ( 4, 3) [001952] n---GO----- t1952 = * IND int /--* t1952 int N006 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 [004013] ----------- IL_OFFSET void INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001955] ----------- t1955 = LCL_VAR ref V102 tmp62 u:1 /--* t1955 ref [004170] -c--------- t4170 = * LEA(b+8) byref /--* t4170 byref N002 ( 3, 3) [001956] ---X------- t1956 = * IND int N003 ( 1, 2) [001957] -c--------- t1957 = CNS_INT int 1 $c1 /--* t1956 int +--* t1957 int N004 ( 8, 6) [001958] Nc-X---N-U- t1958 = * NE int N005 ( 1, 1) [001963] ----------- t1963 = LCL_VAR int V103 tmp63 u:1 N006 ( 1, 1) [001964] ----------- t1964 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1964 byref N008 ( 3, 4) [002879] -c--------- t2879 = * LEA(b+24) byref /--* t2879 byref N009 ( 4, 3) [002002] n---GO----- t2002 = * IND int /--* t1963 int +--* t2002 int N010 ( 9, 5) [001968] Nc--GO-N-U- t1968 = * GE int /--* t1958 int +--* t1968 int N011 ( 18, 12) [003750] Jc-XGO-N--- * AND void N012 ( 20, 14) [001959] ---XGO----- * JTRUE void ------------ BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} [004014] ----------- IL_OFFSET void INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] N001 ( 0, 0) [003751] ----------- NOP void [004015] ----------- IL_OFFSET void INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [002883] ----------- t2883 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] -c--------- t2884 = CNS_INT long 16 $200 /--* t2883 byref +--* t2884 long N003 ( 3, 4) [002885] -----O----- t2885 = * ADD byref $25c /--* t2885 byref N005 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 [004016] ----------- IL_OFFSET void INL37 @ ??? <- INLRT @ 0x547[E-] N001 ( 1, 1) [001972] ----------- t1972 = LCL_VAR int V103 tmp63 u:1 N002 ( 1, 1) [001977] ----------- t1977 = LCL_VAR byref V104 tmp64 u:1 $25c /--* t1977 byref N004 ( 3, 4) [002888] -c--------- t2888 = * LEA(b+8) byref /--* t2888 byref N005 ( 4, 3) [001978] n---GO----- t1978 = * IND int /--* t1972 int +--* t1978 int N006 ( 9, 11) [001979] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001976] ----------- t1976 = LCL_VAR byref V104 tmp64 u:1 (last use) $25c /--* t1976 byref N008 ( 3, 2) [001983] n---GO----- t1983 = * IND byref N009 ( 1, 1) [001973] ----------- t1973 = LCL_VAR int V103 tmp63 u:1 /--* t1973 int N010 ( 2, 3) [001980] -c-------U- t1980 = * CAST long <- uint N011 ( 1, 2) [001981] -c--------- t1981 = CNS_INT long 1 $204 /--* t1980 long +--* t1981 long N012 ( 4, 6) [001982] ----------- t1982 = * BFIZ long /--* t1983 byref +--* t1982 long N013 ( 8, 9) [001984] ----GO-N--- t1984 = * ADD byref N016 ( 1, 2) [001987] -c--------- t1987 = CNS_INT int 0 $c0 N017 ( 1, 1) [001986] ----------- t1986 = LCL_VAR ref V102 tmp62 u:1 /--* t1986 ref [004172] -c--------- t4172 = * LEA(b+8) byref /--* t4172 byref N018 ( 3, 3) [002892] ---X------- t2892 = * IND int /--* t1987 int +--* t2892 int N019 ( 8, 12) [002893] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002890] ----------- t2890 = LCL_VAR ref V102 tmp62 u:1 (last use) /--* t2890 ref N022 ( 1, 1) [002897] -c--------- t2897 = * LEA(b+12) byref /--* t2897 byref N024 ( 5, 4) [002902] n---GO----- t2902 = * IND ushort /--* t1984 byref +--* t2902 ushort [004017] -A-XGO----- * STOREIND short [004018] ----------- IL_OFFSET void INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001993] ----------- t1993 = LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] -c--------- t1994 = CNS_INT int 1 $c1 /--* t1993 int +--* t1994 int N003 ( 3, 4) [001995] ----------- t1995 = * ADD int N004 ( 1, 1) [001992] ----------- t1992 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1992 byref N006 ( 3, 4) [002904] -c--------- t2904 = * LEA(b+8) byref /--* t2904 byref +--* t1995 int [004019] -A--GO----- * STOREIND int ------------ BB168 [547..548), preds={BB165} succs={BB169} [004020] ----------- IL_OFFSET void INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001960] ----------- t1960 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1960 byref [004265] ----------- t4265 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001961] ----------- t1961 = LCL_VAR ref V102 tmp62 u:1 (last use) /--* t1961 ref [004266] ----------- t4266 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002905] H---------- t2905 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2905 long [004267] ----------- t4267 = * PUTARG_REG long REG x11 /--* t4265 byref this in x0 +--* t4266 ref arg2 in x1 +--* t4267 long r2r cell in x11 N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} [004021] ----------- IL_OFFSET void INLRT @ 0x553[E-] N001 ( 1, 1) [000714] ----------- t714 = LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] -c--------- t715 = CNS_INT int -1 $c4 /--* t714 int +--* t715 int N003 ( 3, 4) [000716] ----------- t716 = * ADD int $ab7 /--* t716 int N005 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB169} succs={BB245} [004022] ----------- IL_OFFSET void INLRT @ 0x559[E-] N001 ( 1, 1) [000669] ----------- t669 = LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] -c--------- t670 = CNS_INT int -1 $c4 /--* t669 int +--* t670 int N003 ( 3, 4) [000671] ----------- t671 = * ADD int $ab9 /--* t671 int N005 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB258} succs={BB172,BB245} [004023] ----------- IL_OFFSET void INLRT @ 0x564[E-] N001 ( 1, 1) [000605] ----------- t605 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] -c--------- t606 = CNS_INT int 0 $c0 /--* t605 int +--* t606 int N003 ( 6, 4) [000607] ----------- t607 = * NE int $aba N004 ( 1, 1) [000608] ----------- t608 = LCL_VAR int V21 loc17 u:2 $4c7 /--* t607 int +--* t608 int N005 ( 8, 6) [000609] ----------- t609 = * OR int $abb N006 ( 1, 2) [000610] -c--------- t610 = CNS_INT int 0 $c0 /--* t609 int +--* t610 int N007 ( 10, 9) [000611] CNE-------N--- * JCMP void ------------ BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} [004024] ----------- IL_OFFSET void INLRT @ 0x571[E-] N001 ( 1, 1) [000613] ----------- t613 = LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] -c--------- t614 = CNS_INT int 0 $c0 /--* t613 int +--* t614 int N003 ( 3, 4) [000615] J------N--- * LT void $abd N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} [004025] ----------- IL_OFFSET void INLRT @ 0x575[E-] N001 ( 1, 1) [000625] ----------- t625 = LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- t626 = LCL_VAR int V04 loc0 u:2 $28a /--* t625 int +--* t626 int N003 ( 6, 3) [000627] -c-----N--- t627 = * GE int $abe N004 ( 1, 1) [000629] ----------- t629 = LCL_VAR long V36 loc32 u:3 $901 /--* t629 long N005 ( 4, 3) [000630] ---XG------ t630 = * IND ubyte N006 ( 1, 2) [000631] -c--------- t631 = CNS_INT int 0 $c0 /--* t630 ubyte +--* t631 int N007 ( 9, 6) [000632] -c-XG--N--- t632 = * EQ int /--* t627 int +--* t632 int N008 ( 16, 10) [003752] Jc-XG--N--- * AND void N009 ( 18, 12) [000628] ---XG------ * JTRUE void $VN.Void ------------ BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} [004026] ----------- IL_OFFSET void INLRT @ 0x57C[E-] N001 ( 0, 0) [003753] ----------- NOP void [004027] ----------- IL_OFFSET void INLRT @ 0x584[E-] N001 ( 1, 1) [000618] ----------- t618 = LCL_VAR ref V03 arg3 u:1 $180 /--* t618 ref N003 ( 3, 4) [002907] -c--------- t2907 = * LEA(b+48) byref /--* t2907 byref N004 ( 4, 3) [002006] ---XG------ t2006 = * IND ref /--* t2006 ref N006 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 [004028] ----------- IL_OFFSET void INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002008] ----------- t2008 = LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] -c--------- t2009 = CNS_INT ref null $VN.Null /--* t2008 ref +--* t2009 ref N003 ( 3, 4) [002010] CEQ-------N--- * JCMP void ------------ BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} [004029] ----------- IL_OFFSET void INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [000617] ----------- t617 = LCL_VAR byref V00 arg0 u:1 $100 /--* t617 byref N003 ( 3, 4) [002909] -c--------- t2909 = * LEA(b+8) byref /--* t2909 byref N004 ( 4, 3) [002012] ---XG------ t2012 = * IND int /--* t2012 int N006 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 [004030] ----------- IL_OFFSET void INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002015] ----------- t2015 = LCL_VAR ref V106 tmp66 u:1 /--* t2015 ref [004174] -c--------- t4174 = * LEA(b+8) byref /--* t4174 byref N002 ( 3, 3) [002016] ---X------- t2016 = * IND int N003 ( 1, 2) [002017] -c--------- t2017 = CNS_INT int 1 $c1 /--* t2016 int +--* t2017 int N004 ( 8, 6) [002018] Nc-X---N-U- t2018 = * NE int N005 ( 1, 1) [002023] ----------- t2023 = LCL_VAR int V107 tmp67 u:1 N006 ( 1, 1) [002024] ----------- t2024 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2024 byref N008 ( 3, 4) [002913] -c--------- t2913 = * LEA(b+24) byref /--* t2913 byref N009 ( 4, 3) [002062] n---GO----- t2062 = * IND int /--* t2023 int +--* t2062 int N010 ( 9, 5) [002028] Nc--GO-N-U- t2028 = * GE int /--* t2018 int +--* t2028 int N011 ( 18, 12) [003754] Jc-XGO-N--- * AND void N012 ( 20, 14) [002019] ---XGO----- * JTRUE void ------------ BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} [004031] ----------- IL_OFFSET void INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] N001 ( 0, 0) [003755] ----------- NOP void [004032] ----------- IL_OFFSET void INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002917] ----------- t2917 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] -c--------- t2918 = CNS_INT long 16 $200 /--* t2917 byref +--* t2918 long N003 ( 3, 4) [002919] -----O----- t2919 = * ADD byref $25c /--* t2919 byref N005 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 [004033] ----------- IL_OFFSET void INL40 @ ??? <- INLRT @ 0x584[E-] N001 ( 1, 1) [002032] ----------- t2032 = LCL_VAR int V107 tmp67 u:1 N002 ( 1, 1) [002037] ----------- t2037 = LCL_VAR byref V108 tmp68 u:1 $25c /--* t2037 byref N004 ( 3, 4) [002922] -c--------- t2922 = * LEA(b+8) byref /--* t2922 byref N005 ( 4, 3) [002038] n---GO----- t2038 = * IND int /--* t2032 int +--* t2038 int N006 ( 9, 11) [002039] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002036] ----------- t2036 = LCL_VAR byref V108 tmp68 u:1 (last use) $25c /--* t2036 byref N008 ( 3, 2) [002043] n---GO----- t2043 = * IND byref N009 ( 1, 1) [002033] ----------- t2033 = LCL_VAR int V107 tmp67 u:1 /--* t2033 int N010 ( 2, 3) [002040] -c-------U- t2040 = * CAST long <- uint N011 ( 1, 2) [002041] -c--------- t2041 = CNS_INT long 1 $204 /--* t2040 long +--* t2041 long N012 ( 4, 6) [002042] ----------- t2042 = * BFIZ long /--* t2043 byref +--* t2042 long N013 ( 8, 9) [002044] ----GO-N--- t2044 = * ADD byref N016 ( 1, 2) [002047] -c--------- t2047 = CNS_INT int 0 $c0 N017 ( 1, 1) [002046] ----------- t2046 = LCL_VAR ref V106 tmp66 u:1 /--* t2046 ref [004176] -c--------- t4176 = * LEA(b+8) byref /--* t4176 byref N018 ( 3, 3) [002926] ---X------- t2926 = * IND int /--* t2047 int +--* t2926 int N019 ( 8, 12) [002927] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002924] ----------- t2924 = LCL_VAR ref V106 tmp66 u:1 (last use) /--* t2924 ref N022 ( 1, 1) [002931] -c--------- t2931 = * LEA(b+12) byref /--* t2931 byref N024 ( 5, 4) [002936] n---GO----- t2936 = * IND ushort /--* t2044 byref +--* t2936 ushort [004034] -A-XGO----- * STOREIND short [004035] ----------- IL_OFFSET void INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002053] ----------- t2053 = LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] -c--------- t2054 = CNS_INT int 1 $c1 /--* t2053 int +--* t2054 int N003 ( 3, 4) [002055] ----------- t2055 = * ADD int N004 ( 1, 1) [002052] ----------- t2052 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2052 byref N006 ( 3, 4) [002938] -c--------- t2938 = * LEA(b+8) byref /--* t2938 byref +--* t2055 int [004036] -A--GO----- * STOREIND int ------------ BB179 [584..585), preds={BB176} succs={BB180} [004037] ----------- IL_OFFSET void INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002020] ----------- t2020 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2020 byref [004268] ----------- t4268 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002021] ----------- t2021 = LCL_VAR ref V106 tmp66 u:1 (last use) /--* t2021 ref [004269] ----------- t4269 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002939] H---------- t2939 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2939 long [004270] ----------- t4270 = * PUTARG_REG long REG x11 /--* t4268 byref this in x0 +--* t4269 ref arg2 in x1 +--* t4270 long r2r cell in x11 N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} [004038] ----------- IL_OFFSET void INLRT @ 0x590[E-] N001 ( 1, 2) [002940] ----------- t2940 = CNS_INT int 1 $c1 /--* t2940 int N003 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} [004039] ----------- IL_OFFSET void INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002068] ----------- t2068 = LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] -c--------- t2069 = CNS_INT ref null $VN.Null /--* t2068 ref +--* t2069 ref N003 ( 3, 4) [002070] CEQ-------N--- * JCMP void ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} [004040] ----------- IL_OFFSET void INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [000585] ----------- t585 = LCL_VAR byref V00 arg0 u:1 $100 /--* t585 byref N003 ( 3, 4) [002942] -c--------- t2942 = * LEA(b+8) byref /--* t2942 byref N004 ( 4, 3) [002072] ---XG------ t2072 = * IND int /--* t2072 int N006 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 [004041] ----------- IL_OFFSET void INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002075] ----------- t2075 = LCL_VAR ref V110 tmp70 u:1 /--* t2075 ref [004178] -c--------- t4178 = * LEA(b+8) byref /--* t4178 byref N002 ( 3, 3) [002076] ---X------- t2076 = * IND int N003 ( 1, 2) [002077] -c--------- t2077 = CNS_INT int 1 $c1 /--* t2076 int +--* t2077 int N004 ( 8, 6) [002078] Nc-X---N-U- t2078 = * NE int N005 ( 1, 1) [002083] ----------- t2083 = LCL_VAR int V111 tmp71 u:1 N006 ( 1, 1) [002084] ----------- t2084 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2084 byref N008 ( 3, 4) [002946] -c--------- t2946 = * LEA(b+24) byref /--* t2946 byref N009 ( 4, 3) [002122] n---GO----- t2122 = * IND int /--* t2083 int +--* t2122 int N010 ( 9, 5) [002088] Nc--GO-N-U- t2088 = * GE int /--* t2078 int +--* t2088 int N011 ( 18, 12) [003756] Jc-XGO-N--- * AND void N012 ( 20, 14) [002079] ---XGO----- * JTRUE void ------------ BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} [004042] ----------- IL_OFFSET void INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] N001 ( 0, 0) [003757] ----------- NOP void [004043] ----------- IL_OFFSET void INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002950] ----------- t2950 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] -c--------- t2951 = CNS_INT long 16 $200 /--* t2950 byref +--* t2951 long N003 ( 3, 4) [002952] -----O----- t2952 = * ADD byref $25c /--* t2952 byref N005 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 [004044] ----------- IL_OFFSET void INL43 @ ??? <- INLRT @ 0x598[E-] N001 ( 1, 1) [002092] ----------- t2092 = LCL_VAR int V111 tmp71 u:1 N002 ( 1, 1) [002097] ----------- t2097 = LCL_VAR byref V112 tmp72 u:1 $25c /--* t2097 byref N004 ( 3, 4) [002955] -c--------- t2955 = * LEA(b+8) byref /--* t2955 byref N005 ( 4, 3) [002098] n---GO----- t2098 = * IND int /--* t2092 int +--* t2098 int N006 ( 9, 11) [002099] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002096] ----------- t2096 = LCL_VAR byref V112 tmp72 u:1 (last use) $25c /--* t2096 byref N008 ( 3, 2) [002103] n---GO----- t2103 = * IND byref N009 ( 1, 1) [002093] ----------- t2093 = LCL_VAR int V111 tmp71 u:1 /--* t2093 int N010 ( 2, 3) [002100] -c-------U- t2100 = * CAST long <- uint N011 ( 1, 2) [002101] -c--------- t2101 = CNS_INT long 1 $204 /--* t2100 long +--* t2101 long N012 ( 4, 6) [002102] ----------- t2102 = * BFIZ long /--* t2103 byref +--* t2102 long N013 ( 8, 9) [002104] ----GO-N--- t2104 = * ADD byref N016 ( 1, 2) [002107] -c--------- t2107 = CNS_INT int 0 $c0 N017 ( 1, 1) [002106] ----------- t2106 = LCL_VAR ref V110 tmp70 u:1 /--* t2106 ref [004180] -c--------- t4180 = * LEA(b+8) byref /--* t4180 byref N018 ( 3, 3) [002959] ---X------- t2959 = * IND int /--* t2107 int +--* t2959 int N019 ( 8, 12) [002960] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002957] ----------- t2957 = LCL_VAR ref V110 tmp70 u:1 (last use) /--* t2957 ref N022 ( 1, 1) [002964] -c--------- t2964 = * LEA(b+12) byref /--* t2964 byref N024 ( 5, 4) [002969] n---GO----- t2969 = * IND ushort /--* t2104 byref +--* t2969 ushort [004045] -A-XGO----- * STOREIND short [004046] ----------- IL_OFFSET void INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002113] ----------- t2113 = LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] -c--------- t2114 = CNS_INT int 1 $c1 /--* t2113 int +--* t2114 int N003 ( 3, 4) [002115] ----------- t2115 = * ADD int N004 ( 1, 1) [002112] ----------- t2112 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2112 byref N006 ( 3, 4) [002971] -c--------- t2971 = * LEA(b+8) byref /--* t2971 byref +--* t2115 int [004047] -A--GO----- * STOREIND int ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} [004048] ----------- IL_OFFSET void INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002080] ----------- t2080 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2080 byref [004271] ----------- t4271 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002081] ----------- t2081 = LCL_VAR ref V110 tmp70 u:1 (last use) /--* t2081 ref [004272] ----------- t4272 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002972] H---------- t2972 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2972 long [004273] ----------- t4273 = * PUTARG_REG long REG x11 /--* t4271 byref this in x0 +--* t4272 ref arg2 in x1 +--* t4273 long r2r cell in x11 N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB257} succs={BB187,BB245} [004049] ----------- IL_OFFSET void INLRT @ 0x5A9[E-] N001 ( 1, 1) [000635] ----------- t635 = LCL_VAR ref V03 arg3 u:1 $180 /--* t635 ref N003 ( 3, 4) [002974] -c--------- t2974 = * LEA(b+128) byref /--* t2974 byref N004 ( 4, 3) [002126] ---XG------ t2126 = * IND ref /--* t2126 ref N006 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 [004050] ----------- IL_OFFSET void INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002128] ----------- t2128 = LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] -c--------- t2129 = CNS_INT ref null $VN.Null /--* t2128 ref +--* t2129 ref N003 ( 3, 4) [002130] CEQ-------N--- * JCMP void ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} [004051] ----------- IL_OFFSET void INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [000634] ----------- t634 = LCL_VAR byref V00 arg0 u:1 $100 /--* t634 byref N003 ( 3, 4) [002976] -c--------- t2976 = * LEA(b+8) byref /--* t2976 byref N004 ( 4, 3) [002132] ---XG------ t2132 = * IND int /--* t2132 int N006 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 [004052] ----------- IL_OFFSET void INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002135] ----------- t2135 = LCL_VAR ref V114 tmp74 u:1 /--* t2135 ref [004182] -c--------- t4182 = * LEA(b+8) byref /--* t4182 byref N002 ( 3, 3) [002136] ---X------- t2136 = * IND int N003 ( 1, 2) [002137] -c--------- t2137 = CNS_INT int 1 $c1 /--* t2136 int +--* t2137 int N004 ( 8, 6) [002138] Nc-X---N-U- t2138 = * NE int N005 ( 1, 1) [002143] ----------- t2143 = LCL_VAR int V115 tmp75 u:1 N006 ( 1, 1) [002144] ----------- t2144 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2144 byref N008 ( 3, 4) [002980] -c--------- t2980 = * LEA(b+24) byref /--* t2980 byref N009 ( 4, 3) [002182] n---GO----- t2182 = * IND int /--* t2143 int +--* t2182 int N010 ( 9, 5) [002148] Nc--GO-N-U- t2148 = * GE int /--* t2138 int +--* t2148 int N011 ( 18, 12) [003758] Jc-XGO-N--- * AND void N012 ( 20, 14) [002139] ---XGO----- * JTRUE void ------------ BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} [004053] ----------- IL_OFFSET void INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] N001 ( 0, 0) [003759] ----------- NOP void [004054] ----------- IL_OFFSET void INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002984] ----------- t2984 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] -c--------- t2985 = CNS_INT long 16 $200 /--* t2984 byref +--* t2985 long N003 ( 3, 4) [002986] -----O----- t2986 = * ADD byref $25c /--* t2986 byref N005 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 [004055] ----------- IL_OFFSET void INL46 @ ??? <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002152] ----------- t2152 = LCL_VAR int V115 tmp75 u:1 N002 ( 1, 1) [002157] ----------- t2157 = LCL_VAR byref V116 tmp76 u:1 $25c /--* t2157 byref N004 ( 3, 4) [002989] -c--------- t2989 = * LEA(b+8) byref /--* t2989 byref N005 ( 4, 3) [002158] n---GO----- t2158 = * IND int /--* t2152 int +--* t2158 int N006 ( 9, 11) [002159] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002156] ----------- t2156 = LCL_VAR byref V116 tmp76 u:1 (last use) $25c /--* t2156 byref N008 ( 3, 2) [002163] n---GO----- t2163 = * IND byref N009 ( 1, 1) [002153] ----------- t2153 = LCL_VAR int V115 tmp75 u:1 /--* t2153 int N010 ( 2, 3) [002160] -c-------U- t2160 = * CAST long <- uint N011 ( 1, 2) [002161] -c--------- t2161 = CNS_INT long 1 $204 /--* t2160 long +--* t2161 long N012 ( 4, 6) [002162] ----------- t2162 = * BFIZ long /--* t2163 byref +--* t2162 long N013 ( 8, 9) [002164] ----GO-N--- t2164 = * ADD byref N016 ( 1, 2) [002167] -c--------- t2167 = CNS_INT int 0 $c0 N017 ( 1, 1) [002166] ----------- t2166 = LCL_VAR ref V114 tmp74 u:1 /--* t2166 ref [004184] -c--------- t4184 = * LEA(b+8) byref /--* t4184 byref N018 ( 3, 3) [002993] ---X------- t2993 = * IND int /--* t2167 int +--* t2993 int N019 ( 8, 12) [002994] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002991] ----------- t2991 = LCL_VAR ref V114 tmp74 u:1 (last use) /--* t2991 ref N022 ( 1, 1) [002998] -c--------- t2998 = * LEA(b+12) byref /--* t2998 byref N024 ( 5, 4) [003003] n---GO----- t3003 = * IND ushort /--* t2164 byref +--* t3003 ushort [004056] -A-XGO----- * STOREIND short [004057] ----------- IL_OFFSET void INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002173] ----------- t2173 = LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] -c--------- t2174 = CNS_INT int 1 $c1 /--* t2173 int +--* t2174 int N003 ( 3, 4) [002175] ----------- t2175 = * ADD int N004 ( 1, 1) [002172] ----------- t2172 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2172 byref N006 ( 3, 4) [003005] -c--------- t3005 = * LEA(b+8) byref /--* t3005 byref +--* t2175 int [004058] -A--GO----- * STOREIND int ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} [004059] ----------- IL_OFFSET void INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002140] ----------- t2140 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2140 byref [004274] ----------- t4274 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002141] ----------- t2141 = LCL_VAR ref V114 tmp74 u:1 (last use) /--* t2141 ref [004275] ----------- t4275 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [003006] H---------- t3006 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t3006 long [004276] ----------- t4276 = * PUTARG_REG long REG x11 /--* t4274 byref this in x0 +--* t4275 ref arg2 in x1 +--* t4276 long r2r cell in x11 N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} [004060] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] N001 ( 1, 1) [000805] ----------- t805 = LCL_VAR int V16 loc12 u:13 $b04 /--* t805 int N003 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 [004061] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] N001 ( 1, 1) [000806] ----------- t806 = LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] -c--------- t807 = CNS_INT int 1 $c1 /--* t806 int +--* t807 int N003 ( 3, 4) [000808] ----------- t808 = * ADD int $bad /--* t808 int N005 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 N001 ( 1, 1) [003629] ----------- t3629 = LCL_VAR int V172 cse1 /--* t3629 int N003 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 [004062] ----------- IL_OFFSET void INL48 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000803] ----------- t803 = LCL_VAR byref V00 arg0 u:1 $100 /--* t803 byref N003 ( 3, 4) [003008] -c--------- t3008 = * LEA(b+8) byref /--* t3008 byref N004 ( 4, 3) [002186] ---XG------ t2186 = * IND int /--* t2186 int N006 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 [004063] ----------- IL_OFFSET void INL48 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002189] ----------- t2189 = LCL_VAR int V118 tmp78 u:1 N002 ( 1, 1) [002190] ----------- t2190 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2190 byref N004 ( 3, 4) [003012] -c--------- t3012 = * LEA(b+24) byref /--* t3012 byref N005 ( 4, 3) [002228] n---GO----- t2228 = * IND int /--* t2189 int +--* t2228 int N006 ( 6, 5) [002194] N---GO-N-U- * GE void N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} [004064] ----------- IL_OFFSET void INL48 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003016] ----------- t3016 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] -c--------- t3017 = CNS_INT long 16 $200 /--* t3016 byref +--* t3017 long N003 ( 3, 4) [003018] -----O----- t3018 = * ADD byref $25c /--* t3018 byref N005 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 N001 ( 1, 1) [002201] ----------- t2201 = LCL_VAR int V118 tmp78 u:1 N002 ( 1, 1) [002206] ----------- t2206 = LCL_VAR byref V120 tmp80 u:1 $25c /--* t2206 byref N004 ( 3, 4) [003021] -c--------- t3021 = * LEA(b+8) byref /--* t3021 byref N005 ( 4, 3) [002207] n---GO----- t2207 = * IND int /--* t2201 int +--* t2207 int N006 ( 9, 11) [002208] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002205] ----------- t2205 = LCL_VAR byref V120 tmp80 u:1 (last use) $25c /--* t2205 byref N008 ( 3, 2) [002212] n---GO----- t2212 = * IND byref N009 ( 1, 1) [002202] ----------- t2202 = LCL_VAR int V118 tmp78 u:1 /--* t2202 int N010 ( 2, 3) [002209] -c-------U- t2209 = * CAST long <- uint N011 ( 1, 2) [002210] -c--------- t2210 = CNS_INT long 1 $204 /--* t2209 long +--* t2210 long N012 ( 4, 6) [002211] -c--------- t2211 = * BFIZ long /--* t2212 byref +--* t2211 long N013 ( 8, 9) [002213] -c--------- t2213 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002215] ----------- t2215 = LCL_VAR int V119 tmp79 u:1 (last use) /--* t2213 byref +--* t2215 int [004065] -A-XGO----- * STOREIND short [004066] ----------- IL_OFFSET void INL48 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002219] ----------- t2219 = LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] -c--------- t2220 = CNS_INT int 1 $c1 /--* t2219 int +--* t2220 int N003 ( 3, 4) [002221] ----------- t2221 = * ADD int N004 ( 1, 1) [002218] ----------- t2218 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2218 byref N006 ( 3, 4) [003024] -c--------- t3024 = * LEA(b+8) byref /--* t3024 byref +--* t2221 int [004067] -A--GO----- * STOREIND int ------------ BB193 [000..000), preds={BB191} succs={BB194} [004068] ----------- IL_OFFSET void INL48 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002196] ----------- t2196 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2196 byref [004277] ----------- t4277 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002197] ----------- t2197 = LCL_VAR int V119 tmp79 u:1 (last use) /--* t2197 int [004278] ----------- t4278 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003025] H---------- t3025 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3025 long [004279] ----------- t4279 = * PUTARG_REG long REG x11 /--* t4277 byref this in x0 +--* t4278 int arg2 in x1 +--* t4279 long r2r cell in x11 N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB192,BB193,BB257(2)} succs={BB195,BB197} [004069] ----------- IL_OFFSET void INLRT @ 0x5CE[E-] N001 ( 1, 1) [000751] ----------- t751 = LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- t3699 = LCL_VAR int V179 cse8 u:1 $342 /--* t751 int +--* t3699 int N003 ( 3, 3) [000756] J------N--- * GE void $ba4 N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} [004070] ----------- IL_OFFSET void INLRT @ 0x5D9[E-] N001 ( 1, 1) [000781] ----------- t781 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000782] ----------- t782 = LCL_VAR int V16 loc12 u:13 $b04 /--* t782 int N003 ( 2, 3) [000783] -c--------- t783 = * CAST long <- int $aca N004 ( 1, 2) [000785] -c--------- t785 = CNS_INT long 1 $204 /--* t783 long +--* t785 long N005 ( 4, 6) [000786] -c--------- t786 = * BFIZ long /--* t781 long +--* t786 long N006 ( 6, 8) [000787] -c--------- t787 = * LEA(b+(i*1)+0) long /--* t787 long N007 ( 9, 10) [000788] ---XG------ t788 = * IND ushort /--* t788 ushort N009 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 N010 ( 1, 1) [003632] ----------- t3632 = LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] -c--------- t789 = CNS_INT int 0 $c0 /--* t3632 int +--* t789 int N013 ( 12, 14) [000790] CEQ---XG--N--- * JCMP void ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} [004071] ----------- IL_OFFSET void INLRT @ 0x5E4[E-] N001 ( 1, 1) [003634] ----------- t3634 = LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- t800 = LCL_VAR int V18 loc14 u:1 /--* t3634 int +--* t800 int N003 ( 3, 3) [000801] N---G--N-U- * NE void N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} [004072] ----------- IL_OFFSET void INLRT @ 0x5F1[E-] N001 ( 1, 1) [000758] ----------- t758 = LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- t3700 = LCL_VAR int V179 cse8 u:1 $342 /--* t758 int +--* t3700 int N003 ( 3, 3) [000763] J------N--- * GE void $ba4 N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} [004073] ----------- IL_OFFSET void INLRT @ 0x5FF[E-] N001 ( 1, 1) [000765] ----------- t765 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000766] ----------- t766 = LCL_VAR int V16 loc12 u:13 $b04 /--* t766 int N003 ( 2, 3) [000767] -c--------- t767 = * CAST long <- int $aca N004 ( 1, 2) [000769] -c--------- t769 = CNS_INT long 1 $204 /--* t767 long +--* t769 long N005 ( 4, 6) [000770] -c--------- t770 = * BFIZ long /--* t765 long +--* t770 long N006 ( 6, 8) [000771] -c--------- t771 = * LEA(b+(i*1)+0) long /--* t771 long N007 ( 9, 10) [000772] ---XG------ t772 = * IND ushort /--* t772 ushort N009 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 N010 ( 1, 1) [003637] ----------- t3637 = LCL_VAR int V172 cse1 N012 ( 1, 2) [000773] -c--------- t773 = CNS_INT int 0 $c0 /--* t3637 int +--* t773 int N013 ( 12, 14) [000774] CEQ---XG--N--- * JCMP void ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} [004074] ----------- IL_OFFSET void INLRT @ 0x60D[E-] N001 ( 1, 1) [000776] ----------- t776 = LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] -c--------- t777 = CNS_INT int 1 $c1 /--* t776 int +--* t777 int N003 ( 3, 4) [000778] ----------- t778 = * ADD int $bad /--* t778 int N005 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} [004075] ----------- IL_OFFSET void INLRT @ 0x618[E-] N001 ( 1, 1) [000283] ----------- t283 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- t3701 = LCL_VAR int V179 cse8 u:1 $342 /--* t283 int +--* t3701 int N003 ( 6, 3) [000288] -c-----N--- t288 = * GE int $94d N004 ( 1, 1) [000290] ----------- t290 = LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 1, 1) [000291] ----------- t291 = LCL_VAR int V16 loc12 u:5 $898 /--* t291 int N006 ( 2, 3) [000292] -c--------- t292 = * CAST long <- int $3e5 N007 ( 1, 2) [000294] -c--------- t294 = CNS_INT long 1 $204 /--* t292 long +--* t294 long N008 ( 4, 6) [000295] -c--------- t295 = * BFIZ long /--* t290 long +--* t295 long N009 ( 6, 8) [000296] -c--------- t296 = * LEA(b+(i*1)+0) long /--* t296 long N010 ( 9, 10) [000297] ---XG------ t297 = * IND ushort /--* t297 ushort N012 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 N013 ( 1, 1) [003665] ----------- t3665 = LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] -c--------- t298 = CNS_INT int 0 $c0 /--* t3665 int +--* t298 int N016 ( 15, 14) [000299] -c-XG--N--- t299 = * EQ int /--* t288 int +--* t299 int N017 ( 22, 18) [003760] Jc-XG--N--- * AND void N018 ( 24, 20) [000289] ---XG------ * JTRUE void $VN.Void ------------ BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} [004076] ----------- IL_OFFSET void INLRT @ 0x626[E-] N001 ( 0, 0) [003761] ----------- NOP void [004077] ----------- IL_OFFSET void INLRT @ 0x634[E-] N001 ( 1, 1) [000303] ----------- t303 = LCL_VAR int V16 loc12 u:5 $898 /--* t303 int N003 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 [004078] ----------- IL_OFFSET void INLRT @ 0x634[E-] N001 ( 1, 1) [000304] ----------- t304 = LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] -c--------- t305 = CNS_INT int 1 $c1 /--* t304 int +--* t305 int N003 ( 3, 4) [000306] ----------- t306 = * ADD int $952 /--* t306 int N005 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 N001 ( 1, 1) [003667] ----------- t3667 = LCL_VAR int V176 cse5 /--* t3667 int N003 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 [004079] ----------- IL_OFFSET void INL53 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000301] ----------- t301 = LCL_VAR byref V00 arg0 u:1 $100 /--* t301 byref N003 ( 3, 4) [003027] -c--------- t3027 = * LEA(b+8) byref /--* t3027 byref N004 ( 4, 3) [002244] ---XG------ t2244 = * IND int /--* t2244 int N006 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 [004080] ----------- IL_OFFSET void INL53 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002247] ----------- t2247 = LCL_VAR int V122 tmp82 u:1 N002 ( 1, 1) [002248] ----------- t2248 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2248 byref N004 ( 3, 4) [003031] -c--------- t3031 = * LEA(b+24) byref /--* t3031 byref N005 ( 4, 3) [002286] n---GO----- t2286 = * IND int /--* t2247 int +--* t2286 int N006 ( 6, 5) [002252] N---GO-N-U- * GE void N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 ------------ BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} [004081] ----------- IL_OFFSET void INL53 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003035] ----------- t3035 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] -c--------- t3036 = CNS_INT long 16 $200 /--* t3035 byref +--* t3036 long N003 ( 3, 4) [003037] -----O----- t3037 = * ADD byref $25c /--* t3037 byref N005 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 N001 ( 1, 1) [002259] ----------- t2259 = LCL_VAR int V122 tmp82 u:1 N002 ( 1, 1) [002264] ----------- t2264 = LCL_VAR byref V124 tmp84 u:1 $25c /--* t2264 byref N004 ( 3, 4) [003040] -c--------- t3040 = * LEA(b+8) byref /--* t3040 byref N005 ( 4, 3) [002265] n---GO----- t2265 = * IND int /--* t2259 int +--* t2265 int N006 ( 9, 11) [002266] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002263] ----------- t2263 = LCL_VAR byref V124 tmp84 u:1 (last use) $25c /--* t2263 byref N008 ( 3, 2) [002270] n---GO----- t2270 = * IND byref N009 ( 1, 1) [002260] ----------- t2260 = LCL_VAR int V122 tmp82 u:1 /--* t2260 int N010 ( 2, 3) [002267] -c-------U- t2267 = * CAST long <- uint N011 ( 1, 2) [002268] -c--------- t2268 = CNS_INT long 1 $204 /--* t2267 long +--* t2268 long N012 ( 4, 6) [002269] -c--------- t2269 = * BFIZ long /--* t2270 byref +--* t2269 long N013 ( 8, 9) [002271] -c--------- t2271 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002273] ----------- t2273 = LCL_VAR int V123 tmp83 u:1 (last use) /--* t2271 byref +--* t2273 int [004082] -A-XGO----- * STOREIND short [004083] ----------- IL_OFFSET void INL53 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002277] ----------- t2277 = LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] -c--------- t2278 = CNS_INT int 1 $c1 /--* t2277 int +--* t2278 int N003 ( 3, 4) [002279] ----------- t2279 = * ADD int N004 ( 1, 1) [002276] ----------- t2276 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2276 byref N006 ( 3, 4) [003043] -c--------- t3043 = * LEA(b+8) byref /--* t3043 byref +--* t2279 int [004084] -A--GO----- * STOREIND int ------------ BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} [004085] ----------- IL_OFFSET void INL53 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002254] ----------- t2254 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2254 byref [004280] ----------- t4280 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002255] ----------- t2255 = LCL_VAR int V123 tmp83 u:1 (last use) /--* t2255 int [004281] ----------- t4281 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003044] H---------- t3044 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3044 long [004282] ----------- t4282 = * PUTARG_REG long REG x11 /--* t4280 byref this in x0 +--* t4281 int arg2 in x1 +--* t4282 long r2r cell in x11 N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} [004086] ----------- IL_OFFSET void INLRT @ 0x64D[E-] N001 ( 1, 2) [003045] -c--------- t3045 = CNS_INT int 0 $c0 /--* t3045 int N003 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 [004087] ----------- IL_OFFSET void INLRT @ 0x650[E-] N001 ( 1, 2) [000326] -c--------- t326 = CNS_INT int 0 $c0 /--* t326 int N003 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 [004088] ----------- IL_OFFSET void INLRT @ 0x653[E-] N001 ( 1, 1) [000329] ----------- t329 = LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] -c--------- t330 = CNS_INT int 0 $c0 /--* t329 int +--* t330 int N003 ( 3, 4) [000331] CEQ-------N--- * JCMP void ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} [004089] ----------- IL_OFFSET void INLRT @ 0x65A[E-] N001 ( 1, 1) [000419] ----------- t419 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- t3702 = LCL_VAR int V179 cse8 u:1 $342 /--* t419 int +--* t3702 int N003 ( 3, 3) [000424] J------N--- * GE void $94d N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} [004090] ----------- IL_OFFSET void INLRT @ 0x665[E-] N001 ( 1, 1) [000565] ----------- t565 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000566] ----------- t566 = LCL_VAR int V16 loc12 u:5 $898 /--* t566 int N003 ( 2, 3) [000567] -c--------- t567 = * CAST long <- int $3e5 N004 ( 1, 2) [000569] -c--------- t569 = CNS_INT long 1 $204 /--* t567 long +--* t569 long N005 ( 4, 6) [000570] -c--------- t570 = * BFIZ long /--* t565 long +--* t570 long N006 ( 6, 8) [000571] -c--------- t571 = * LEA(b+(i*1)+0) long /--* t571 long N007 ( 9, 10) [000572] ---XG------ t572 = * IND ushort /--* t572 ushort N009 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 N010 ( 1, 1) [003670] ----------- t3670 = LCL_VAR int V176 cse5 N012 ( 1, 2) [000573] -c--------- t573 = CNS_INT int 48 $d8 /--* t3670 int +--* t573 int N013 ( 12, 14) [000574] N--XG--N-U- * EQ void N014 ( 14, 16) [000575] ---XG------ * JTRUE void $87a ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} [004091] ----------- IL_OFFSET void INLRT @ 0x67A[E-] N001 ( 1, 1) [000426] ----------- t426 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] -c--------- t427 = CNS_INT int 1 $c1 /--* t426 int +--* t427 int N003 ( 3, 4) [000428] ----------- t428 = * ADD int $952 N004 ( 1, 1) [003703] ----------- t3703 = LCL_VAR int V179 cse8 u:1 $342 /--* t428 int +--* t3703 int N005 ( 5, 6) [000433] J------N--- * GE void $9e2 N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} [004092] ----------- IL_OFFSET void INLRT @ 0x687[E-] N001 ( 1, 1) [000538] ----------- t538 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000539] ----------- t539 = LCL_VAR int V16 loc12 u:5 $898 /--* t539 int N003 ( 2, 3) [000540] -c--------- t540 = * CAST long <- int $3e5 N004 ( 1, 2) [000542] -c--------- t542 = CNS_INT long 1 $204 /--* t540 long +--* t542 long N005 ( 4, 6) [000543] -c--------- t543 = * BFIZ long /--* t538 long +--* t543 long N006 ( 6, 8) [000544] -c--------- t544 = * LEA(b+(i*1)+0) long /--* t544 long N007 ( 9, 10) [000545] ---XG------ t545 = * IND ushort /--* t545 ushort N009 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 N010 ( 1, 1) [003674] ----------- t3674 = LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] -c--------- t546 = CNS_INT int 43 $d9 /--* t3674 int +--* t546 int N013 ( 15, 14) [000547] N--XG--N-U- t547 = * NE int N014 ( 1, 1) [000549] ----------- t549 = LCL_VAR long V34 loc30 u:1 $3c4 N015 ( 1, 1) [000550] ----------- t550 = LCL_VAR int V16 loc12 u:5 $898 N016 ( 1, 2) [000551] -c--------- t551 = CNS_INT int 1 $c1 /--* t550 int +--* t551 int N017 ( 3, 4) [000552] ----------- t552 = * ADD int $952 /--* t552 int N018 ( 4, 6) [000553] -c--------- t553 = * CAST long <- int $3f4 N019 ( 1, 2) [000555] -c--------- t555 = CNS_INT long 1 $204 /--* t553 long +--* t555 long N020 ( 6, 9) [000556] -c--------- t556 = * BFIZ long /--* t549 long +--* t556 long N021 ( 8, 11) [000557] -c--------- t557 = * LEA(b+(i*1)+0) long /--* t557 long N022 ( 11, 13) [000558] ---XG------ t558 = * IND ushort N023 ( 1, 2) [000559] -c--------- t559 = CNS_INT int 48 $d8 /--* t558 ushort +--* t559 int N024 ( 16, 16) [000560] N--XG--N-U- t560 = * NE int /--* t547 int +--* t560 int N025 ( 32, 31) [003762] J--XG--N--- t3762 = * AND int /--* t3762 int N026 ( 34, 33) [000548] ---XG------ * JTRUE void $87a ------------ BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} [004093] ----------- IL_OFFSET void INLRT @ 0x694[E-] N001 ( 0, 0) [003763] ----------- NOP void [004094] ----------- IL_OFFSET void INLRT @ 0x6A3[E-] N001 ( 1, 2) [003046] ----------- t3046 = CNS_INT int 1 $c1 /--* t3046 int N003 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} [004095] ----------- IL_OFFSET void INLRT @ 0x6B5[E-] N001 ( 1, 1) [003676] ----------- t3676 = LCL_VAR int V176 cse5 N002 ( 1, 2) [000455] -c--------- t455 = CNS_INT int 45 $da /--* t3676 int +--* t455 int N003 ( 3, 4) [000456] N---G--N-U- * NE void N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} [004096] ----------- IL_OFFSET void INLRT @ 0x6C2[E-] N001 ( 1, 1) [000458] ----------- t458 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000459] ----------- t459 = LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] -c--------- t460 = CNS_INT int 1 $c1 /--* t459 int +--* t460 int N004 ( 3, 4) [000461] ----------- t461 = * ADD int $952 /--* t461 int N005 ( 4, 6) [000462] -c--------- t462 = * CAST long <- int $3f4 N006 ( 1, 2) [000464] -c--------- t464 = CNS_INT long 1 $204 /--* t462 long +--* t464 long N007 ( 6, 9) [000465] -c--------- t465 = * BFIZ long /--* t458 long +--* t465 long N008 ( 8, 11) [000466] -c--------- t466 = * LEA(b+(i*1)+0) long /--* t466 long N009 ( 11, 13) [000467] ---XG------ t467 = * IND ushort N010 ( 1, 2) [000468] -c--------- t468 = CNS_INT int 48 $d8 /--* t467 ushort +--* t468 int N011 ( 13, 16) [000469] J--XG--N--- * EQ void N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 ------------ BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} [004097] ----------- IL_OFFSET void INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [000444] ----------- t444 = LCL_VAR byref V00 arg0 u:1 $100 /--* t444 byref N003 ( 3, 4) [003048] -c--------- t3048 = * LEA(b+8) byref /--* t3048 byref N004 ( 4, 3) [002302] ---XG------ t2302 = * IND int /--* t2302 int N006 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 [004098] ----------- IL_OFFSET void INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002305] ----------- t2305 = LCL_VAR int V126 tmp86 u:1 N002 ( 1, 1) [002306] ----------- t2306 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2306 byref N004 ( 3, 4) [003052] -c--------- t3052 = * LEA(b+24) byref /--* t3052 byref N005 ( 4, 3) [002341] n---GO----- t2341 = * IND int /--* t2305 int +--* t2341 int N006 ( 6, 5) [002310] N---GO-N-U- * GE void N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} [004099] ----------- IL_OFFSET void INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [003056] ----------- t3056 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] -c--------- t3057 = CNS_INT long 16 $200 /--* t3056 byref +--* t3057 long N003 ( 3, 4) [003058] -----O----- t3058 = * ADD byref $25c /--* t3058 byref N005 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 [004100] ----------- IL_OFFSET void INL58 @ ??? <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002316] ----------- t2316 = LCL_VAR int V126 tmp86 u:1 N002 ( 1, 1) [002321] ----------- t2321 = LCL_VAR byref V127 tmp87 u:1 $25c /--* t2321 byref N004 ( 3, 4) [003061] -c--------- t3061 = * LEA(b+8) byref /--* t3061 byref N005 ( 4, 3) [002322] n---GO----- t2322 = * IND int /--* t2316 int +--* t2322 int N006 ( 9, 11) [002323] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002320] ----------- t2320 = LCL_VAR byref V127 tmp87 u:1 (last use) $25c /--* t2320 byref N008 ( 3, 2) [002327] n---GO----- t2327 = * IND byref N009 ( 1, 1) [002317] ----------- t2317 = LCL_VAR int V126 tmp86 u:1 /--* t2317 int N010 ( 2, 3) [002324] -c-------U- t2324 = * CAST long <- uint N011 ( 1, 2) [002325] -c--------- t2325 = CNS_INT long 1 $204 /--* t2324 long +--* t2325 long N012 ( 4, 6) [002326] -c--------- t2326 = * BFIZ long /--* t2327 byref +--* t2326 long N013 ( 8, 9) [002328] -c--------- t2328 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002330] ----------- t2330 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2328 byref +--* t2330 int [004101] -A-XGO----- * STOREIND short [004102] ----------- IL_OFFSET void INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002334] ----------- t2334 = LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] -c--------- t2335 = CNS_INT int 1 $c1 /--* t2334 int +--* t2335 int N003 ( 3, 4) [002336] ----------- t2336 = * ADD int N004 ( 1, 1) [002333] ----------- t2333 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2333 byref N006 ( 3, 4) [003064] -c--------- t3064 = * LEA(b+8) byref /--* t3064 byref +--* t2336 int [004103] -A--GO----- * STOREIND int ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} [004104] ----------- IL_OFFSET void INLRT @ 0x6DE[E-] N001 ( 1, 1) [000533] ----------- t533 = LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] -c--------- t534 = CNS_INT int 1 $c1 /--* t533 int +--* t534 int N003 ( 3, 4) [000535] ----------- t535 = * ADD int $c59 /--* t535 int N005 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} [004105] ----------- IL_OFFSET void INLRT @ 0x6E4[E-] N001 ( 1, 1) [000471] ----------- t471 = LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] -c--------- t472 = CNS_INT int 1 $c1 /--* t471 int +--* t472 int N003 ( 3, 4) [000473] ----------- t473 = * ADD int $c5c /--* t473 int N005 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 N001 ( 1, 1) [000477] ----------- t477 = LCL_VAR int V54 tmp14 u:1 $c5c /--* t477 int N003 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 N001 ( 1, 1) [000476] ----------- t476 = LCL_VAR int V16 loc12 u:10 (last use) $c5c N002 ( 1, 1) [003704] ----------- t3704 = LCL_VAR int V179 cse8 u:1 $342 /--* t476 int +--* t3704 int N003 ( 3, 3) [000484] J------N--- * GE void $c5d N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} [004106] ----------- IL_OFFSET void INLRT @ 0x6F4[E-] N001 ( 1, 1) [000522] ----------- t522 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000523] ----------- t523 = LCL_VAR int V16 loc12 u:10 $c5c /--* t523 int N003 ( 2, 3) [000524] -c--------- t524 = * CAST long <- int $ad8 N004 ( 1, 2) [000526] -c--------- t526 = CNS_INT long 1 $204 /--* t524 long +--* t526 long N005 ( 4, 6) [000527] -c--------- t527 = * BFIZ long /--* t522 long +--* t527 long N006 ( 6, 8) [000528] -c--------- t528 = * LEA(b+(i*1)+0) long /--* t528 long N007 ( 9, 10) [000529] ---XG------ t529 = * IND ushort N008 ( 1, 2) [000530] -c--------- t530 = CNS_INT int 48 $d8 /--* t529 ushort +--* t530 int N009 ( 11, 13) [000531] J--XG--N--- * EQ void N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} [004107] ----------- IL_OFFSET void INLRT @ 0x701[E-] N001 ( 1, 1) [000486] ----------- t486 = LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] -c--------- t487 = CNS_INT int 10 $e4 /--* t486 int +--* t487 int N003 ( 3, 4) [000488] J------N--- * LE void $c62 N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void ------------ BB222 [707..70B), preds={BB221} succs={BB223} [004108] ----------- IL_OFFSET void INLRT @ 0x707[E-] N001 ( 1, 2) [000519] ----------- t519 = CNS_INT int 10 $e4 /--* t519 int N003 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} [004109] ----------- IL_OFFSET void INLRT @ 0x70B[E-] N001 ( 1, 1) [000490] ----------- t490 = LCL_VAR long V17 loc13 u:1 /--* t490 long N002 ( 4, 3) [000491] ---XG------ t491 = * IND ubyte N003 ( 1, 2) [000492] -c--------- t492 = CNS_INT int 0 $c0 /--* t491 ubyte +--* t492 int N004 ( 6, 6) [000493] CEQ---XG--N--- * JCMP void ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} [004110] ----------- IL_OFFSET void INLRT @ 0x710[E-] N001 ( 1, 1) [000512] ----------- t512 = LCL_VAR byref V01 arg1 u:1 $101 /--* t512 byref N003 ( 3, 4) [003067] -c--------- t3067 = * LEA(b+4) byref /--* t3067 byref N004 ( 4, 3) [000513] n---GO----- t513 = * IND int N005 ( 1, 1) [000514] ----------- t514 = LCL_VAR int V05 loc1 u:3 $28d /--* t513 int +--* t514 int N006 ( 6, 5) [000515] ----GO----- t515 = * SUB int /--* t515 int N008 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} [004111] ----------- IL_OFFSET void INLRT @ 0x71A[E-] N001 ( 1, 2) [000495] -c--------- t495 = CNS_INT int 0 $c0 /--* t495 int N003 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} [004112] ----------- IL_OFFSET void INLRT @ 0x71D[E-] N001 ( 1, 1) [000507] ----------- t507 = LCL_VAR int V37 loc33 u:2 (last use) $4ca /--* t507 int [004283] ----------- t4283 = * PUTARG_REG int REG x5 N002 ( 1, 1) [000502] ----------- t502 = LCL_VAR byref V00 arg0 u:1 $100 /--* t502 byref [004284] ----------- t4284 = * PUTARG_REG byref REG x0 N003 ( 1, 1) [000503] ----------- t503 = LCL_VAR ref V03 arg3 u:1 $180 /--* t503 ref [004285] ----------- t4285 = * PUTARG_REG ref REG x1 N004 ( 1, 1) [000499] ----------- t499 = LCL_VAR int V55 tmp15 u:1 (last use) $b12 /--* t499 int [004286] ----------- t4286 = * PUTARG_REG int REG x2 N005 ( 1, 1) [000505] ----------- t505 = LCL_VAR int V18 loc14 u:1 (last use) /--* t505 int [004287] ----------- t4287 = * PUTARG_REG int REG x3 N006 ( 1, 1) [000506] ----------- t506 = LCL_VAR int V38 loc34 u:3 (last use) $b10 /--* t506 int [004288] ----------- t4288 = * PUTARG_REG int REG x4 N007 ( 2, 8) [003068] H---------- t3068 = CNS_INT(h) long 0x4000000000540240 ftn $5e /--* t3068 long [004289] ----------- t4289 = * PUTARG_REG long REG x11 /--* t4283 int arg6 in x5 +--* t4284 byref arg1 in x0 +--* t4285 ref arg2 in x1 +--* t4286 int arg3 in x2 +--* t4287 int arg4 in x3 +--* t4288 int arg5 in x4 +--* t4289 long r2r cell in x11 N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void [004113] ----------- IL_OFFSET void INLRT @ 0x72C[E-] N001 ( 1, 2) [003069] -c--------- t3069 = CNS_INT int 0 $c0 /--* t3069 int N003 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} [004114] ----------- IL_OFFSET void INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [000333] ----------- t333 = LCL_VAR byref V00 arg0 u:1 $100 /--* t333 byref N003 ( 3, 4) [003071] -c--------- t3071 = * LEA(b+8) byref /--* t3071 byref N004 ( 4, 3) [002349] ---XG------ t2349 = * IND int /--* t2349 int N006 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 [004115] ----------- IL_OFFSET void INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002352] ----------- t2352 = LCL_VAR int V129 tmp89 u:1 N002 ( 1, 1) [002353] ----------- t2353 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2353 byref N004 ( 3, 4) [003075] -c--------- t3075 = * LEA(b+24) byref /--* t3075 byref N005 ( 4, 3) [002388] n---GO----- t2388 = * IND int /--* t2352 int +--* t2388 int N006 ( 6, 5) [002357] N---GO-N-U- * GE void N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} [004116] ----------- IL_OFFSET void INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [003079] ----------- t3079 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] -c--------- t3080 = CNS_INT long 16 $200 /--* t3079 byref +--* t3080 long N003 ( 3, 4) [003081] -----O----- t3081 = * ADD byref $25c /--* t3081 byref N005 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 [004117] ----------- IL_OFFSET void INL61 @ ??? <- INLRT @ 0x731[E-] N001 ( 1, 1) [002363] ----------- t2363 = LCL_VAR int V129 tmp89 u:1 N002 ( 1, 1) [002368] ----------- t2368 = LCL_VAR byref V130 tmp90 u:1 $25c /--* t2368 byref N004 ( 3, 4) [003084] -c--------- t3084 = * LEA(b+8) byref /--* t3084 byref N005 ( 4, 3) [002369] n---GO----- t2369 = * IND int /--* t2363 int +--* t2369 int N006 ( 9, 11) [002370] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002367] ----------- t2367 = LCL_VAR byref V130 tmp90 u:1 (last use) $25c /--* t2367 byref N008 ( 3, 2) [002374] n---GO----- t2374 = * IND byref N009 ( 1, 1) [002364] ----------- t2364 = LCL_VAR int V129 tmp89 u:1 /--* t2364 int N010 ( 2, 3) [002371] -c-------U- t2371 = * CAST long <- uint N011 ( 1, 2) [002372] -c--------- t2372 = CNS_INT long 1 $204 /--* t2371 long +--* t2372 long N012 ( 4, 6) [002373] -c--------- t2373 = * BFIZ long /--* t2374 byref +--* t2373 long N013 ( 8, 9) [002375] -c--------- t2375 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002377] ----------- t2377 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2375 byref +--* t2377 int [004118] -A-XGO----- * STOREIND short [004119] ----------- IL_OFFSET void INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002381] ----------- t2381 = LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] -c--------- t2382 = CNS_INT int 1 $c1 /--* t2381 int +--* t2382 int N003 ( 3, 4) [002383] ----------- t2383 = * ADD int N004 ( 1, 1) [002380] ----------- t2380 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2380 byref N006 ( 3, 4) [003087] -c--------- t3087 = * LEA(b+8) byref /--* t3087 byref +--* t2383 int [004120] -A--GO----- * STOREIND int ------------ BB229 [731..732), preds={BB227} succs={BB230} [004121] ----------- IL_OFFSET void INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002359] ----------- t2359 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2359 byref [004290] ----------- t4290 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000334] ----------- t334 = LCL_VAR int V18 loc14 u:1 (last use) /--* t334 int [004291] ----------- t4291 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003088] H---------- t3088 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3088 long [004292] ----------- t4292 = * PUTARG_REG long REG x11 /--* t4290 byref this in x0 +--* t4291 int arg2 in x1 +--* t4292 long r2r cell in x11 N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} [004122] ----------- IL_OFFSET void INLRT @ 0x739[E-] N001 ( 1, 1) [000336] ----------- t336 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- t3705 = LCL_VAR int V179 cse8 u:1 $342 /--* t336 int +--* t3705 int N003 ( 3, 3) [000341] J------N--- * GE void $94d N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} [004123] ----------- IL_OFFSET void INLRT @ 0x744[E-] N001 ( 1, 1) [000343] ----------- t343 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000344] ----------- t344 = LCL_VAR int V16 loc12 u:5 $898 /--* t344 int N003 ( 2, 3) [000345] -c--------- t345 = * CAST long <- int $3e5 N004 ( 1, 2) [000347] -c--------- t347 = CNS_INT long 1 $204 /--* t345 long +--* t347 long N005 ( 4, 6) [000348] -c--------- t348 = * BFIZ long /--* t343 long +--* t348 long N006 ( 6, 8) [000349] -c--------- t349 = * LEA(b+(i*1)+0) long /--* t349 long N007 ( 9, 10) [000350] ---XG------ t350 = * IND ushort /--* t350 ushort N009 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 N010 ( 1, 1) [003659] ----------- t3659 = LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] -c--------- t351 = CNS_INT int 43 $d9 /--* t3659 int +--* t351 int N013 ( 12, 14) [000352] J--XG--N--- * EQ void N014 ( 14, 16) [000353] ---XG------ * JTRUE void $87a ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} [004124] ----------- IL_OFFSET void INLRT @ 0x751[E-] N001 ( 1, 1) [003661] ----------- t3661 = LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] -c--------- t416 = CNS_INT int 45 $da /--* t3661 int +--* t416 int N003 ( 3, 4) [000417] N---G--N-U- * NE void N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} [004125] ----------- IL_OFFSET void INLRT @ 0x75E[E-] N001 ( 1, 1) [000356] ----------- t356 = LCL_VAR int V16 loc12 u:5 $898 /--* t356 int N003 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 [004126] ----------- IL_OFFSET void INLRT @ 0x75E[E-] N001 ( 1, 1) [000357] ----------- t357 = LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] -c--------- t358 = CNS_INT int 1 $c1 /--* t357 int +--* t358 int N003 ( 3, 4) [000359] ----------- t359 = * ADD int $952 /--* t359 int N005 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 N001 ( 1, 1) [003662] ----------- t3662 = LCL_VAR int V175 cse4 u:1 /--* t3662 int N003 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 [004127] ----------- IL_OFFSET void INL64 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000354] ----------- t354 = LCL_VAR byref V00 arg0 u:1 $100 /--* t354 byref N003 ( 3, 4) [003090] -c--------- t3090 = * LEA(b+8) byref /--* t3090 byref N004 ( 4, 3) [002396] n---GO----- t2396 = * IND int /--* t2396 int N006 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 [004128] ----------- IL_OFFSET void INL64 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002399] ----------- t2399 = LCL_VAR int V132 tmp92 u:1 N002 ( 1, 1) [002400] ----------- t2400 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2400 byref N004 ( 3, 4) [003094] -c--------- t3094 = * LEA(b+24) byref /--* t3094 byref N005 ( 4, 3) [002438] n---GO----- t2438 = * IND int /--* t2399 int +--* t2438 int N006 ( 6, 5) [002404] N---GO-N-U- * GE void N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} [004129] ----------- IL_OFFSET void INL64 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003098] ----------- t3098 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] -c--------- t3099 = CNS_INT long 16 $200 /--* t3098 byref +--* t3099 long N003 ( 3, 4) [003100] -----O----- t3100 = * ADD byref $25c /--* t3100 byref N005 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 N001 ( 1, 1) [002411] ----------- t2411 = LCL_VAR int V132 tmp92 u:1 N002 ( 1, 1) [002416] ----------- t2416 = LCL_VAR byref V134 tmp94 u:1 $25c /--* t2416 byref N004 ( 3, 4) [003103] -c--------- t3103 = * LEA(b+8) byref /--* t3103 byref N005 ( 4, 3) [002417] n---GO----- t2417 = * IND int /--* t2411 int +--* t2417 int N006 ( 9, 11) [002418] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002415] ----------- t2415 = LCL_VAR byref V134 tmp94 u:1 (last use) $25c /--* t2415 byref N008 ( 3, 2) [002422] n---GO----- t2422 = * IND byref N009 ( 1, 1) [002412] ----------- t2412 = LCL_VAR int V132 tmp92 u:1 /--* t2412 int N010 ( 2, 3) [002419] -c-------U- t2419 = * CAST long <- uint N011 ( 1, 2) [002420] -c--------- t2420 = CNS_INT long 1 $204 /--* t2419 long +--* t2420 long N012 ( 4, 6) [002421] -c--------- t2421 = * BFIZ long /--* t2422 byref +--* t2421 long N013 ( 8, 9) [002423] -c--------- t2423 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002425] ----------- t2425 = LCL_VAR int V133 tmp93 u:1 (last use) /--* t2423 byref +--* t2425 int [004130] -A-XGO----- * STOREIND short [004131] ----------- IL_OFFSET void INL64 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002429] ----------- t2429 = LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] -c--------- t2430 = CNS_INT int 1 $c1 /--* t2429 int +--* t2430 int N003 ( 3, 4) [002431] ----------- t2431 = * ADD int N004 ( 1, 1) [002428] ----------- t2428 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2428 byref N006 ( 3, 4) [003106] -c--------- t3106 = * LEA(b+8) byref /--* t3106 byref +--* t2431 int [004132] -A--GO----- * STOREIND int ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} [004133] ----------- IL_OFFSET void INL64 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002406] ----------- t2406 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2406 byref [004293] ----------- t4293 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002407] ----------- t2407 = LCL_VAR int V133 tmp93 u:1 (last use) /--* t2407 int [004294] ----------- t4294 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003107] H---------- t3107 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3107 long [004295] ----------- t4295 = * PUTARG_REG long REG x11 /--* t4293 byref this in x0 +--* t4294 int arg2 in x1 +--* t4295 long r2r cell in x11 N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} [004134] ----------- IL_OFFSET void INLRT @ 0x774[E-] N001 ( 1, 1) [000392] ----------- t392 = LCL_VAR int V16 loc12 u:6 $b08 /--* t392 int N003 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 [004135] ----------- IL_OFFSET void INLRT @ 0x774[E-] N001 ( 1, 1) [000393] ----------- t393 = LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] -c--------- t394 = CNS_INT int 1 $c1 /--* t393 int +--* t394 int N003 ( 3, 4) [000395] ----------- t395 = * ADD int $c47 /--* t395 int N005 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 N001 ( 1, 1) [003639] ----------- t3639 = LCL_VAR int V173 cse2 u:1 /--* t3639 int N003 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 [004136] ----------- IL_OFFSET void INL66 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000390] ----------- t390 = LCL_VAR byref V00 arg0 u:1 $100 /--* t390 byref N003 ( 3, 4) [003109] -c--------- t3109 = * LEA(b+8) byref /--* t3109 byref N004 ( 4, 3) [002442] n---GO----- t2442 = * IND int /--* t2442 int N006 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 [004137] ----------- IL_OFFSET void INL66 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002445] ----------- t2445 = LCL_VAR int V136 tmp96 u:1 N002 ( 1, 1) [002446] ----------- t2446 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2446 byref N004 ( 3, 4) [003113] -c--------- t3113 = * LEA(b+24) byref /--* t3113 byref N005 ( 4, 3) [002484] n---GO----- t2484 = * IND int /--* t2445 int +--* t2484 int N006 ( 6, 5) [002450] N---GO-N-U- * GE void N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} [004138] ----------- IL_OFFSET void INL66 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003117] ----------- t3117 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] -c--------- t3118 = CNS_INT long 16 $200 /--* t3117 byref +--* t3118 long N003 ( 3, 4) [003119] -----O----- t3119 = * ADD byref $25c /--* t3119 byref N005 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 N001 ( 1, 1) [002457] ----------- t2457 = LCL_VAR int V136 tmp96 u:1 N002 ( 1, 1) [002462] ----------- t2462 = LCL_VAR byref V138 tmp98 u:1 $25c /--* t2462 byref N004 ( 3, 4) [003122] -c--------- t3122 = * LEA(b+8) byref /--* t3122 byref N005 ( 4, 3) [002463] n---GO----- t2463 = * IND int /--* t2457 int +--* t2463 int N006 ( 9, 11) [002464] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002461] ----------- t2461 = LCL_VAR byref V138 tmp98 u:1 (last use) $25c /--* t2461 byref N008 ( 3, 2) [002468] n---GO----- t2468 = * IND byref N009 ( 1, 1) [002458] ----------- t2458 = LCL_VAR int V136 tmp96 u:1 /--* t2458 int N010 ( 2, 3) [002465] -c-------U- t2465 = * CAST long <- uint N011 ( 1, 2) [002466] -c--------- t2466 = CNS_INT long 1 $204 /--* t2465 long +--* t2466 long N012 ( 4, 6) [002467] -c--------- t2467 = * BFIZ long /--* t2468 byref +--* t2467 long N013 ( 8, 9) [002469] -c--------- t2469 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002471] ----------- t2471 = LCL_VAR int V137 tmp97 u:1 (last use) /--* t2469 byref +--* t2471 int [004139] -A-XGO----- * STOREIND short [004140] ----------- IL_OFFSET void INL66 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002475] ----------- t2475 = LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] -c--------- t2476 = CNS_INT int 1 $c1 /--* t2475 int +--* t2476 int N003 ( 3, 4) [002477] ----------- t2477 = * ADD int N004 ( 1, 1) [002474] ----------- t2474 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2474 byref N006 ( 3, 4) [003125] -c--------- t3125 = * LEA(b+8) byref /--* t3125 byref +--* t2477 int [004141] -A--GO----- * STOREIND int ------------ BB238 [000..000), preds={BB236} succs={BB239} [004142] ----------- IL_OFFSET void INL66 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002452] ----------- t2452 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2452 byref [004296] ----------- t4296 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002453] ----------- t2453 = LCL_VAR int V137 tmp97 u:1 (last use) /--* t2453 int [004297] ----------- t4297 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003126] H---------- t3126 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3126 long [004298] ----------- t4298 = * PUTARG_REG long REG x11 /--* t4296 byref this in x0 +--* t4297 int arg2 in x1 +--* t4298 long r2r cell in x11 N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} [004143] ----------- IL_OFFSET void INLRT @ 0x788[E-] N001 ( 1, 1) [000372] ----------- t372 = LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- t3706 = LCL_VAR int V179 cse8 u:1 $342 /--* t372 int +--* t3706 int N003 ( 3, 3) [000377] J------N--- * GE void $c42 N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} [004144] ----------- IL_OFFSET void INLRT @ 0x793[E-] N001 ( 1, 1) [000379] ----------- t379 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000380] ----------- t380 = LCL_VAR int V16 loc12 u:6 $b08 /--* t380 int N003 ( 2, 3) [000381] -c--------- t381 = * CAST long <- int $ad1 N004 ( 1, 2) [000383] -c--------- t383 = CNS_INT long 1 $204 /--* t381 long +--* t383 long N005 ( 4, 6) [000384] -c--------- t384 = * BFIZ long /--* t379 long +--* t384 long N006 ( 6, 8) [000385] -c--------- t385 = * LEA(b+(i*1)+0) long /--* t385 long N007 ( 9, 10) [000386] ---XG------ t386 = * IND ushort /--* t386 ushort N009 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 N010 ( 1, 1) [003642] ----------- t3642 = LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] -c--------- t387 = CNS_INT int 48 $d8 /--* t3642 int +--* t387 int N013 ( 12, 14) [000388] J--XG--N--- * EQ void N014 ( 14, 16) [000389] ---XG------ * JTRUE void $c02 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB140,BB143,BB257(2),BB258(2)} succs={BB243,BB244} [004145] ----------- IL_OFFSET void INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [000590] ----------- t590 = LCL_VAR byref V00 arg0 u:1 $100 /--* t590 byref N003 ( 3, 4) [003128] -c--------- t3128 = * LEA(b+8) byref /--* t3128 byref N004 ( 4, 3) [002492] ---XG------ t2492 = * IND int /--* t2492 int N006 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 [004146] ----------- IL_OFFSET void INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002495] ----------- t2495 = LCL_VAR int V140 tmp100 u:1 N002 ( 1, 1) [002496] ----------- t2496 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2496 byref N004 ( 3, 4) [003132] -c--------- t3132 = * LEA(b+24) byref /--* t3132 byref N005 ( 4, 3) [002531] n---GO----- t2531 = * IND int /--* t2495 int +--* t2531 int N006 ( 6, 5) [002500] N---GO-N-U- * GE void N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} [004147] ----------- IL_OFFSET void INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [003136] ----------- t3136 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] -c--------- t3137 = CNS_INT long 16 $200 /--* t3136 byref +--* t3137 long N003 ( 3, 4) [003138] -----O----- t3138 = * ADD byref $25c /--* t3138 byref N005 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 [004148] ----------- IL_OFFSET void INL69 @ ??? <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002506] ----------- t2506 = LCL_VAR int V140 tmp100 u:1 N002 ( 1, 1) [002511] ----------- t2511 = LCL_VAR byref V141 tmp101 u:1 $25c /--* t2511 byref N004 ( 3, 4) [003141] -c--------- t3141 = * LEA(b+8) byref /--* t3141 byref N005 ( 4, 3) [002512] n---GO----- t2512 = * IND int /--* t2506 int +--* t2512 int N006 ( 9, 11) [002513] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002510] ----------- t2510 = LCL_VAR byref V141 tmp101 u:1 (last use) $25c /--* t2510 byref N008 ( 3, 2) [002517] n---GO----- t2517 = * IND byref N009 ( 1, 1) [002507] ----------- t2507 = LCL_VAR int V140 tmp100 u:1 /--* t2507 int N010 ( 2, 3) [002514] -c-------U- t2514 = * CAST long <- uint N011 ( 1, 2) [002515] -c--------- t2515 = CNS_INT long 1 $204 /--* t2514 long +--* t2515 long N012 ( 4, 6) [002516] -c--------- t2516 = * BFIZ long /--* t2517 byref +--* t2516 long N013 ( 8, 9) [002518] -c--------- t2518 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002520] ----------- t2520 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2518 byref +--* t2520 int [004149] -A-XGO----- * STOREIND short [004150] ----------- IL_OFFSET void INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002524] ----------- t2524 = LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] -c--------- t2525 = CNS_INT int 1 $c1 /--* t2524 int +--* t2525 int N003 ( 3, 4) [002526] ----------- t2526 = * ADD int N004 ( 1, 1) [002523] ----------- t2523 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2523 byref N006 ( 3, 4) [003144] -c--------- t3144 = * LEA(b+8) byref /--* t3144 byref +--* t2526 int [004151] -A--GO----- * STOREIND int ------------ BB244 [7A2..7A3) -> BB245 (always), preds={BB215,BB242} succs={BB245} [004152] ----------- IL_OFFSET void INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002502] ----------- t2502 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2502 byref [004299] ----------- t4299 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000591] ----------- t591 = LCL_VAR int V18 loc14 u:1 (last use) /--* t591 int [004300] ----------- t4300 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003145] H---------- t3145 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3145 long [004301] ----------- t4301 = * PUTARG_REG long REG x11 /--* t4299 byref this in x0 +--* t4300 int arg2 in x1 +--* t4301 long r2r cell in x11 N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB110 [000..000) (throw), preds={BB91} succs={} [004153] ----------- IL_OFFSET void INL17 @ 0x029[E-] <- INLRT @ ??? N001 ( 2, 8) [002701] H---------- t2701 = CNS_INT(h) long 0x4000000000424a20 ftn $4a /--* t2701 long [004302] ----------- t4302 = * PUTARG_REG long REG x11 /--* t4302 long r2r cell in x11 N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void ------------ BB254 [???..???) (throw), preds={} succs={} N001 ( 2, 8) [004303] H---------- t4303 = CNS_INT(h) long 0x4000000000421828 ftn /--* t4303 long N002 ( 5, 10) [004304] ----------- t4304 = * IND long /--* t4304 long control expr N001 ( 14, 2) [004154] --CXG------ * CALL help void CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V01: refCnt = 1, refCntWtd = 1 New refCnts for V11: refCnt = 1, refCntWtd = 1 New refCnts for V01: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 1, refCntWtd = 2 New refCnts for V76: refCnt = 2, refCntWtd = 4 New refCnts for V76: refCnt = 3, refCntWtd = 6 New refCnts for V167: refCnt = 1, refCntWtd = 2 New refCnts for V167: refCnt = 2, refCntWtd = 4 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V180: refCnt = 1, refCntWtd = 1 New refCnts for V180: refCnt = 2, refCntWtd = 2 New refCnts for V147: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V179: refCnt = 1, refCntWtd = 1 New refCnts for V179: refCnt = 2, refCntWtd = 2 New refCnts for V148: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 2 New refCnts for V147: refCnt = 2, refCntWtd = 1.50 New refCnts for V155: refCnt = 1, refCntWtd = 0.50 New refCnts for V148: refCnt = 2, refCntWtd = 1.50 New refCnts for V156: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 3, refCntWtd = 2.50 New refCnts for V155: refCnt = 2, refCntWtd = 1 New refCnts for V149: refCnt = 1, refCntWtd = 0.50 New refCnts for V156: refCnt = 2, refCntWtd = 1 New refCnts for V150: refCnt = 1, refCntWtd = 0.50 New refCnts for V43: refCnt = 1, refCntWtd = 0.50 New refCnts for V155: refCnt = 3, refCntWtd = 1.50 New refCnts for V149: refCnt = 2, refCntWtd = 1 New refCnts for V156: refCnt = 3, refCntWtd = 1.50 New refCnts for V150: refCnt = 2, refCntWtd = 1 New refCnts for V43: refCnt = 2, refCntWtd = 1 New refCnts for V147: refCnt = 3, refCntWtd = 2 New refCnts for V149: refCnt = 3, refCntWtd = 1.50 New refCnts for V148: refCnt = 3, refCntWtd = 2 New refCnts for V150: refCnt = 3, refCntWtd = 1.50 New refCnts for V43: refCnt = 3, refCntWtd = 1.50 New refCnts for V149: refCnt = 4, refCntWtd = 2.50 New refCnts for V150: refCnt = 4, refCntWtd = 2.50 New refCnts for V43: refCnt = 4, refCntWtd = 2.50 New refCnts for V15: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 1, refCntWtd = 8 New refCnts for V05: refCnt = 1, refCntWtd = 8 New refCnts for V06: refCnt = 1, refCntWtd = 8 New refCnts for V07: refCnt = 1, refCntWtd = 8 New refCnts for V09: refCnt = 1, refCntWtd = 8 New refCnts for V10: refCnt = 1, refCntWtd = 8 New refCnts for V12: refCnt = 1, refCntWtd = 8 New refCnts for V13: refCnt = 1, refCntWtd = 8 New refCnts for V15: refCnt = 2, refCntWtd = 9 New refCnts for V16: refCnt = 1, refCntWtd = 8 New refCnts for V180: refCnt = 3, refCntWtd = 10 New refCnts for V157: refCnt = 1, refCntWtd = 8 New refCnts for V157: refCnt = 2, refCntWtd = 16 New refCnts for V23: refCnt = 1, refCntWtd = 8 New refCnts for V157: refCnt = 3, refCntWtd = 24 New refCnts for V168: refCnt = 1, refCntWtd = 16 New refCnts for V168: refCnt = 2, refCntWtd = 32 New refCnts for V22: refCnt = 1, refCntWtd = 8 New refCnts for V18: refCnt = 1, refCntWtd = 8 New refCnts for V18: refCnt = 2, refCntWtd = 16 New refCnts for V182: refCnt = 1, refCntWtd = 16 New refCnts for V182: refCnt = 2, refCntWtd = 32 New refCnts for V182: refCnt = 3, refCntWtd = 48 New refCnts for V18: refCnt = 3, refCntWtd = 24 New refCnts for V183: refCnt = 1, refCntWtd = 16 New refCnts for V183: refCnt = 2, refCntWtd = 32 New refCnts for V183: refCnt = 3, refCntWtd = 48 New refCnts for V18: refCnt = 4, refCntWtd = 32 New refCnts for V18: refCnt = 5, refCntWtd = 40 New refCnts for V18: refCnt = 6, refCntWtd = 48 New refCnts for V18: refCnt = 7, refCntWtd = 56 New refCnts for V13: refCnt = 2, refCntWtd = 16 New refCnts for V13: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 3, refCntWtd = 24 New refCnts for V06: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 4, refCntWtd = 32 New refCnts for V06: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 5, refCntWtd = 40 New refCnts for V04: refCnt = 6, refCntWtd = 48 New refCnts for V04: refCnt = 7, refCntWtd = 56 New refCnts for V07: refCnt = 2, refCntWtd = 16 New refCnts for V05: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 8, refCntWtd = 64 New refCnts for V05: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 9, refCntWtd = 72 New refCnts for V05: refCnt = 4, refCntWtd = 32 New refCnts for V10: refCnt = 2, refCntWtd = 16 New refCnts for V10: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 10, refCntWtd = 80 New refCnts for V11: refCnt = 2, refCntWtd = 9 New refCnts for V11: refCnt = 3, refCntWtd = 17 New refCnts for V12: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 11, refCntWtd = 88 New refCnts for V10: refCnt = 4, refCntWtd = 32 New refCnts for V11: refCnt = 4, refCntWtd = 25 New refCnts for V13: refCnt = 4, refCntWtd = 32 New refCnts for V13: refCnt = 5, refCntWtd = 40 New refCnts for V16: refCnt = 2, refCntWtd = 72 New refCnts for V179: refCnt = 3, refCntWtd = 66 New refCnts for V22: refCnt = 2, refCntWtd = 72 New refCnts for V16: refCnt = 3, refCntWtd = 136 New refCnts for V171: refCnt = 1, refCntWtd = 64 New refCnts for V171: refCnt = 2, refCntWtd = 128 New refCnts for V16: refCnt = 4, refCntWtd = 200 New refCnts for V74: refCnt = 1, refCntWtd = 128 New refCnts for V74: refCnt = 2, refCntWtd = 256 New refCnts for V16: refCnt = 5, refCntWtd = 264 New refCnts for V171: refCnt = 3, refCntWtd = 192 New refCnts for V18: refCnt = 8, refCntWtd = 120 New refCnts for V16: refCnt = 6, refCntWtd = 272 New refCnts for V179: refCnt = 4, refCntWtd = 74 New refCnts for V22: refCnt = 3, refCntWtd = 80 New refCnts for V16: refCnt = 7, refCntWtd = 280 New refCnts for V174: refCnt = 1, refCntWtd = 8 New refCnts for V174: refCnt = 2, refCntWtd = 16 New refCnts for V16: refCnt = 8, refCntWtd = 288 New refCnts for V16: refCnt = 9, refCntWtd = 296 New refCnts for V16: refCnt = 10, refCntWtd = 304 New refCnts for V179: refCnt = 5, refCntWtd = 82 New refCnts for V22: refCnt = 4, refCntWtd = 88 New refCnts for V16: refCnt = 11, refCntWtd = 312 New refCnts for V174: refCnt = 3, refCntWtd = 24 New refCnts for V174: refCnt = 4, refCntWtd = 32 New refCnts for V16: refCnt = 12, refCntWtd = 320 New refCnts for V179: refCnt = 6, refCntWtd = 90 New refCnts for V22: refCnt = 5, refCntWtd = 96 New refCnts for V16: refCnt = 13, refCntWtd = 328 New refCnts for V174: refCnt = 5, refCntWtd = 40 New refCnts for V174: refCnt = 6, refCntWtd = 48 New refCnts for V174: refCnt = 7, refCntWtd = 56 New refCnts for V22: refCnt = 6, refCntWtd = 104 New refCnts for V16: refCnt = 14, refCntWtd = 336 New refCnts for V16: refCnt = 15, refCntWtd = 400 New refCnts for V73: refCnt = 1, refCntWtd = 128 New refCnts for V73: refCnt = 2, refCntWtd = 256 New refCnts for V16: refCnt = 16, refCntWtd = 464 New refCnts for V16: refCnt = 17, refCntWtd = 528 New refCnts for V179: refCnt = 7, refCntWtd = 154 New refCnts for V22: refCnt = 7, refCntWtd = 168 New refCnts for V16: refCnt = 18, refCntWtd = 592 New refCnts for V09: refCnt = 2, refCntWtd = 16 New refCnts for V16: refCnt = 19, refCntWtd = 656 New refCnts for V179: refCnt = 8, refCntWtd = 218 New refCnts for V16: refCnt = 20, refCntWtd = 672 New refCnts for V71: refCnt = 1, refCntWtd = 32 New refCnts for V71: refCnt = 2, refCntWtd = 64 New refCnts for V16: refCnt = 21, refCntWtd = 688 New refCnts for V22: refCnt = 8, refCntWtd = 184 New refCnts for V71: refCnt = 3, refCntWtd = 96 New refCnts for V72: refCnt = 1, refCntWtd = 32 New refCnts for V72: refCnt = 2, refCntWtd = 64 New refCnts for V18: refCnt = 9, refCntWtd = 136 New refCnts for V18: refCnt = 10, refCntWtd = 152 New refCnts for V18: refCnt = 11, refCntWtd = 168 New refCnts for V23: refCnt = 2, refCntWtd = 16 New refCnts for V05: refCnt = 5, refCntWtd = 40 New refCnts for V04: refCnt = 12, refCntWtd = 90 New refCnts for V05: refCnt = 6, refCntWtd = 42 New refCnts for V10: refCnt = 5, refCntWtd = 40 New refCnts for V10: refCnt = 6, refCntWtd = 42 New refCnts for V05: refCnt = 7, refCntWtd = 44 New refCnts for V13: refCnt = 6, refCntWtd = 42 New refCnts for V11: refCnt = 5, refCntWtd = 27 New refCnts for V13: refCnt = 7, refCntWtd = 44 New refCnts for V12: refCnt = 3, refCntWtd = 18 New refCnts for V17: refCnt = 3, refCntWtd = 10 New refCnts for V01: refCnt = 4, refCntWtd = 6.50 New refCnts for V69: refCnt = 1, refCntWtd = 8 New refCnts for V69: refCnt = 2, refCntWtd = 16 New refCnts for V13: refCnt = 8, refCntWtd = 48 New refCnts for V69: refCnt = 3, refCntWtd = 24 New refCnts for V09: refCnt = 3, refCntWtd = 20 New refCnts for V01: refCnt = 5, refCntWtd = 8.50 New refCnts for V04: refCnt = 13, refCntWtd = 92 New refCnts for V05: refCnt = 8, refCntWtd = 46 New refCnts for V70: refCnt = 1, refCntWtd = 2 New refCnts for V04: refCnt = 14, refCntWtd = 94 New refCnts for V70: refCnt = 2, refCntWtd = 4 New refCnts for V70: refCnt = 3, refCntWtd = 8 New refCnts for V01: refCnt = 6, refCntWtd = 12.50 New refCnts for V17: refCnt = 4, refCntWtd = 14 New refCnts for V180: refCnt = 4, refCntWtd = 14 New refCnts for V02: refCnt = 3, refCntWtd = 6 New refCnts for V16: refCnt = 22, refCntWtd = 692 New refCnts for V16: refCnt = 23, refCntWtd = 696 New refCnts for V15: refCnt = 3, refCntWtd = 13 New refCnts for V16: refCnt = 24, refCntWtd = 700 New refCnts for V15: refCnt = 4, refCntWtd = 17 New refCnts for V01: refCnt = 7, refCntWtd = 13 New refCnts for V01: refCnt = 8, refCntWtd = 13.50 New refCnts for V01: refCnt = 9, refCntWtd = 14 New refCnts for V06: refCnt = 4, refCntWtd = 25 New refCnts for V05: refCnt = 9, refCntWtd = 47 New refCnts for V05: refCnt = 10, refCntWtd = 48 New refCnts for V06: refCnt = 5, refCntWtd = 26 New refCnts for V44: refCnt = 1, refCntWtd = 1 New refCnts for V44: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 6, refCntWtd = 27 New refCnts for V07: refCnt = 3, refCntWtd = 17 New refCnts for V05: refCnt = 11, refCntWtd = 49 New refCnts for V05: refCnt = 12, refCntWtd = 50 New refCnts for V07: refCnt = 4, refCntWtd = 18 New refCnts for V45: refCnt = 1, refCntWtd = 1 New refCnts for V45: refCnt = 2, refCntWtd = 2 New refCnts for V07: refCnt = 5, refCntWtd = 19 New refCnts for V09: refCnt = 4, refCntWtd = 21 New refCnts for V05: refCnt = 13, refCntWtd = 50.50 New refCnts for V08: refCnt = 1, refCntWtd = 0.50 New refCnts for V14: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 10, refCntWtd = 14.50 New refCnts for V178: refCnt = 1, refCntWtd = 0.50 New refCnts for V178: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 14, refCntWtd = 51 New refCnts for V178: refCnt = 3, refCntWtd = 1.50 New refCnts for V05: refCnt = 15, refCntWtd = 51.50 New refCnts for V46: refCnt = 1, refCntWtd = 0.50 New refCnts for V46: refCnt = 2, refCntWtd = 1 New refCnts for V08: refCnt = 2, refCntWtd = 1 New refCnts for V178: refCnt = 4, refCntWtd = 2 New refCnts for V05: refCnt = 16, refCntWtd = 52 New refCnts for V14: refCnt = 2, refCntWtd = 1 New refCnts for V15: refCnt = 5, refCntWtd = 18 New refCnts for V16: refCnt = 25, refCntWtd = 701 New refCnts for V47: refCnt = 1, refCntWtd = 1 New refCnts for V151: refCnt = 1, refCntWtd = 1 New refCnts for V152: refCnt = 1, refCntWtd = 1 New refCnts for V151: refCnt = 2, refCntWtd = 2 New refCnts for V143: refCnt = 1, refCntWtd = 1 New refCnts for V144: refCnt = 1, refCntWtd = 1 New refCnts for V20: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V12: refCnt = 4, refCntWtd = 19 New refCnts for V03: refCnt = 2, refCntWtd = 1.50 New refCnts for V26: refCnt = 1, refCntWtd = 0.50 New refCnts for V27: refCnt = 1, refCntWtd = 0.50 New refCnts for V28: refCnt = 1, refCntWtd = 0.50 New refCnts for V26: refCnt = 2, refCntWtd = 1 New refCnts for V29: refCnt = 1, refCntWtd = 0.50 New refCnts for V29: refCnt = 2, refCntWtd = 1 New refCnts for V26: refCnt = 3, refCntWtd = 1.50 New refCnts for V28: refCnt = 2, refCntWtd = 1 New refCnts for V28: refCnt = 3, refCntWtd = 1.50 New refCnts for V30: refCnt = 1, refCntWtd = 0.50 New refCnts for V08: refCnt = 3, refCntWtd = 1.50 New refCnts for V64: refCnt = 1, refCntWtd = 0.50 New refCnts for V14: refCnt = 3, refCntWtd = 1.50 New refCnts for V64: refCnt = 2, refCntWtd = 1 New refCnts for V65: refCnt = 1, refCntWtd = 0.50 New refCnts for V66: refCnt = 1, refCntWtd = 0.50 New refCnts for V64: refCnt = 3, refCntWtd = 1.50 New refCnts for V65: refCnt = 2, refCntWtd = 1 New refCnts for V14: refCnt = 4, refCntWtd = 2 New refCnts for V66: refCnt = 2, refCntWtd = 1 New refCnts for V65: refCnt = 3, refCntWtd = 1.50 New refCnts for V66: refCnt = 3, refCntWtd = 1.50 New refCnts for V31: refCnt = 1, refCntWtd = 0.50 New refCnts for V06: refCnt = 7, refCntWtd = 27.50 New refCnts for V31: refCnt = 2, refCntWtd = 1 New refCnts for V06: refCnt = 8, refCntWtd = 28 New refCnts for V31: refCnt = 3, refCntWtd = 1.50 New refCnts for V67: refCnt = 1, refCntWtd = 0.50 New refCnts for V67: refCnt = 2, refCntWtd = 1 New refCnts for V32: refCnt = 1, refCntWtd = 0.50 New refCnts for V32: refCnt = 2, refCntWtd = 1 New refCnts for V30: refCnt = 2, refCntWtd = 1 New refCnts for V30: refCnt = 3, refCntWtd = 5 New refCnts for V20: refCnt = 2, refCntWtd = 5 New refCnts for V20: refCnt = 3, refCntWtd = 9 New refCnts for V20: refCnt = 4, refCntWtd = 13 New refCnts for V144: refCnt = 2, refCntWtd = 5 New refCnts for V144: refCnt = 3, refCntWtd = 7 New refCnts for V33: refCnt = 1, refCntWtd = 2 New refCnts for V33: refCnt = 2, refCntWtd = 4 New refCnts for V159: refCnt = 1, refCntWtd = 2 New refCnts for V33: refCnt = 3, refCntWtd = 6 New refCnts for V160: refCnt = 1, refCntWtd = 2 New refCnts for V159: refCnt = 2, refCntWtd = 4 New refCnts for V161: refCnt = 1, refCntWtd = 2 New refCnts for V144: refCnt = 4, refCntWtd = 9 New refCnts for V160: refCnt = 2, refCntWtd = 4 New refCnts for V144: refCnt = 5, refCntWtd = 11 New refCnts for V83: refCnt = 1, refCntWtd = 4 New refCnts for V83: refCnt = 2, refCntWtd = 8 New refCnts for V161: refCnt = 2, refCntWtd = 4 New refCnts for V143: refCnt = 2, refCntWtd = 3 New refCnts for V33: refCnt = 4, refCntWtd = 8 New refCnts for V163: refCnt = 1, refCntWtd = 2 New refCnts for V33: refCnt = 5, refCntWtd = 10 New refCnts for V164: refCnt = 1, refCntWtd = 2 New refCnts for V163: refCnt = 2, refCntWtd = 4 New refCnts for V143: refCnt = 3, refCntWtd = 5 New refCnts for V164: refCnt = 2, refCntWtd = 4 New refCnts for V144: refCnt = 6, refCntWtd = 13 New refCnts for V20: refCnt = 5, refCntWtd = 17 New refCnts for V144: refCnt = 7, refCntWtd = 17 New refCnts for V143: refCnt = 4, refCntWtd = 9 New refCnts for V20: refCnt = 6, refCntWtd = 21 New refCnts for V28: refCnt = 4, refCntWtd = 5.50 New refCnts for V27: refCnt = 2, refCntWtd = 4.50 New refCnts for V29: refCnt = 3, refCntWtd = 5 New refCnts for V27: refCnt = 3, refCntWtd = 6.50 New refCnts for V27: refCnt = 4, refCntWtd = 8.50 New refCnts for V27: refCnt = 5, refCntWtd = 10.50 New refCnts for V26: refCnt = 4, refCntWtd = 3.50 New refCnts for V26: refCnt = 5, refCntWtd = 5.50 New refCnts for V27: refCnt = 6, refCntWtd = 12.50 New refCnts for V30: refCnt = 4, refCntWtd = 7 New refCnts for V28: refCnt = 5, refCntWtd = 9.50 New refCnts for V30: refCnt = 5, refCntWtd = 11 New refCnts for V28: refCnt = 6, refCntWtd = 13.50 New refCnts for V32: refCnt = 3, refCntWtd = 5 New refCnts for V28: refCnt = 7, refCntWtd = 17.50 New refCnts for V01: refCnt = 11, refCntWtd = 15.50 New refCnts for V16: refCnt = 26, refCntWtd = 702 New refCnts for V01: refCnt = 12, refCntWtd = 16 New refCnts for V03: refCnt = 3, refCntWtd = 2 New refCnts for V86: refCnt = 1, refCntWtd = 1 New refCnts for V86: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 1, refCntWtd = 0.50 New refCnts for V87: refCnt = 1, refCntWtd = 0.50 New refCnts for V86: refCnt = 3, refCntWtd = 3 New refCnts for V87: refCnt = 2, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 1 New refCnts for V00: refCnt = 3, refCntWtd = 1.50 New refCnts for V88: refCnt = 1, refCntWtd = 1 New refCnts for V87: refCnt = 3, refCntWtd = 1.50 New refCnts for V88: refCnt = 2, refCntWtd = 2 New refCnts for V88: refCnt = 3, refCntWtd = 3 New refCnts for V87: refCnt = 4, refCntWtd = 2 New refCnts for V86: refCnt = 4, refCntWtd = 4 New refCnts for V87: refCnt = 5, refCntWtd = 2.50 New refCnts for V00: refCnt = 4, refCntWtd = 2 New refCnts for V21: refCnt = 1, refCntWtd = 1 New refCnts for V180: refCnt = 5, refCntWtd = 15 New refCnts for V165: refCnt = 1, refCntWtd = 1 New refCnts for V165: refCnt = 2, refCntWtd = 2 New refCnts for V35: refCnt = 1, refCntWtd = 1 New refCnts for V165: refCnt = 3, refCntWtd = 3 New refCnts for V169: refCnt = 1, refCntWtd = 2 New refCnts for V169: refCnt = 2, refCntWtd = 4 New refCnts for V34: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 5, refCntWtd = 15 New refCnts for V36: refCnt = 1, refCntWtd = 1 New refCnts for V16: refCnt = 27, refCntWtd = 710 New refCnts for V179: refCnt = 9, refCntWtd = 226 New refCnts for V16: refCnt = 28, refCntWtd = 714 New refCnts for V49: refCnt = 1, refCntWtd = 8 New refCnts for V49: refCnt = 2, refCntWtd = 16 New refCnts for V16: refCnt = 29, refCntWtd = 718 New refCnts for V34: refCnt = 2, refCntWtd = 5 New refCnts for V49: refCnt = 3, refCntWtd = 24 New refCnts for V50: refCnt = 1, refCntWtd = 8 New refCnts for V50: refCnt = 2, refCntWtd = 16 New refCnts for V18: refCnt = 12, refCntWtd = 172 New refCnts for V18: refCnt = 13, refCntWtd = 176 New refCnts for V18: refCnt = 14, refCntWtd = 180 New refCnts for V35: refCnt = 2, refCntWtd = 2 New refCnts for V01: refCnt = 13, refCntWtd = 17 New refCnts for V15: refCnt = 6, refCntWtd = 19 New refCnts for V01: refCnt = 14, refCntWtd = 17.50 New refCnts for V00: refCnt = 5, refCntWtd = 2.50 New refCnts for V03: refCnt = 4, refCntWtd = 2.50 New refCnts for V00: refCnt = 6, refCntWtd = 3 New refCnts for V00: refCnt = 7, refCntWtd = 3.50 New refCnts for V86: refCnt = 5, refCntWtd = 5 New refCnts for V14: refCnt = 5, refCntWtd = 4 New refCnts for V18: refCnt = 15, refCntWtd = 182 New refCnts for V18: refCnt = 16, refCntWtd = 184 New refCnts for V18: refCnt = 17, refCntWtd = 186 New refCnts for V00: refCnt = 8, refCntWtd = 11.50 New refCnts for V60: refCnt = 1, refCntWtd = 8 New refCnts for V36: refCnt = 2, refCntWtd = 9 New refCnts for V177: refCnt = 1, refCntWtd = 8 New refCnts for V177: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 9, refCntWtd = 19.50 New refCnts for V62: refCnt = 1, refCntWtd = 8 New refCnts for V63: refCnt = 1, refCntWtd = 8 New refCnts for V36: refCnt = 3, refCntWtd = 17 New refCnts for V61: refCnt = 1, refCntWtd = 16 New refCnts for V61: refCnt = 2, refCntWtd = 32 New refCnts for V36: refCnt = 4, refCntWtd = 25 New refCnts for V00: refCnt = 10, refCntWtd = 27.50 New refCnts for V62: refCnt = 2, refCntWtd = 16 New refCnts for V177: refCnt = 3, refCntWtd = 24 New refCnts for V63: refCnt = 2, refCntWtd = 16 New refCnts for V63: refCnt = 3, refCntWtd = 24 New refCnts for V92: refCnt = 1, refCntWtd = 16 New refCnts for V00: refCnt = 11, refCntWtd = 35.50 New refCnts for V91: refCnt = 1, refCntWtd = 8 New refCnts for V91: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 12, refCntWtd = 43.50 New refCnts for V00: refCnt = 13, refCntWtd = 51.50 New refCnts for V93: refCnt = 1, refCntWtd = 16 New refCnts for V91: refCnt = 3, refCntWtd = 24 New refCnts for V93: refCnt = 2, refCntWtd = 32 New refCnts for V93: refCnt = 3, refCntWtd = 48 New refCnts for V91: refCnt = 4, refCntWtd = 32 New refCnts for V92: refCnt = 2, refCntWtd = 32 New refCnts for V91: refCnt = 5, refCntWtd = 40 New refCnts for V00: refCnt = 14, refCntWtd = 59.50 New refCnts for V00: refCnt = 15, refCntWtd = 67.50 New refCnts for V92: refCnt = 3, refCntWtd = 48 New refCnts for V12: refCnt = 5, refCntWtd = 27 New refCnts for V08: refCnt = 4, refCntWtd = 9.50 New refCnts for V20: refCnt = 7, refCntWtd = 29 New refCnts for V144: refCnt = 8, refCntWtd = 25 New refCnts for V143: refCnt = 5, refCntWtd = 17 New refCnts for V20: refCnt = 8, refCntWtd = 37 New refCnts for V08: refCnt = 5, refCntWtd = 17.50 New refCnts for V20: refCnt = 9, refCntWtd = 45 New refCnts for V03: refCnt = 5, refCntWtd = 10.50 New refCnts for V95: refCnt = 1, refCntWtd = 16 New refCnts for V95: refCnt = 2, refCntWtd = 32 New refCnts for V00: refCnt = 16, refCntWtd = 75.50 New refCnts for V96: refCnt = 1, refCntWtd = 8 New refCnts for V95: refCnt = 3, refCntWtd = 48 New refCnts for V181: refCnt = 1, refCntWtd = 8 New refCnts for V181: refCnt = 2, refCntWtd = 16 New refCnts for V96: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 17, refCntWtd = 83.50 New refCnts for V00: refCnt = 18, refCntWtd = 91.50 New refCnts for V97: refCnt = 1, refCntWtd = 16 New refCnts for V96: refCnt = 3, refCntWtd = 24 New refCnts for V97: refCnt = 2, refCntWtd = 32 New refCnts for V97: refCnt = 3, refCntWtd = 48 New refCnts for V96: refCnt = 4, refCntWtd = 32 New refCnts for V181: refCnt = 3, refCntWtd = 24 New refCnts for V95: refCnt = 4, refCntWtd = 64 New refCnts for V96: refCnt = 5, refCntWtd = 40 New refCnts for V00: refCnt = 19, refCntWtd = 99.50 New refCnts for V00: refCnt = 20, refCntWtd = 107.50 New refCnts for V95: refCnt = 5, refCntWtd = 80 New refCnts for V20: refCnt = 10, refCntWtd = 53 New refCnts for V20: refCnt = 11, refCntWtd = 61 New refCnts for V08: refCnt = 6, refCntWtd = 25.50 New refCnts for V08: refCnt = 7, refCntWtd = 33.50 New refCnts for V14: refCnt = 6, refCntWtd = 12 New refCnts for V14: refCnt = 7, refCntWtd = 20 New refCnts for V14: refCnt = 8, refCntWtd = 36 New refCnts for V18: refCnt = 18, refCntWtd = 188 New refCnts for V18: refCnt = 19, refCntWtd = 190 New refCnts for V184: refCnt = 1, refCntWtd = 4 New refCnts for V184: refCnt = 2, refCntWtd = 8 New refCnts for V184: refCnt = 3, refCntWtd = 12 New refCnts for V18: refCnt = 20, refCntWtd = 192 New refCnts for V185: refCnt = 1, refCntWtd = 4 New refCnts for V185: refCnt = 2, refCntWtd = 8 New refCnts for V185: refCnt = 3, refCntWtd = 12 New refCnts for V18: refCnt = 21, refCntWtd = 194 New refCnts for V18: refCnt = 22, refCntWtd = 196 New refCnts for V18: refCnt = 23, refCntWtd = 198 New refCnts for V18: refCnt = 24, refCntWtd = 200 New refCnts for V03: refCnt = 6, refCntWtd = 12.50 New refCnts for V110: refCnt = 1, refCntWtd = 4 New refCnts for V14: refCnt = 9, refCntWtd = 38 New refCnts for V14: refCnt = 10, refCntWtd = 40 New refCnts for V14: refCnt = 11, refCntWtd = 42 New refCnts for V08: refCnt = 8, refCntWtd = 35.50 New refCnts for V06: refCnt = 9, refCntWtd = 30 New refCnts for V58: refCnt = 1, refCntWtd = 2 New refCnts for V58: refCnt = 2, refCntWtd = 4 New refCnts for V58: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 25, refCntWtd = 202 New refCnts for V36: refCnt = 5, refCntWtd = 27 New refCnts for V08: refCnt = 9, refCntWtd = 37.50 New refCnts for V07: refCnt = 6, refCntWtd = 21 New refCnts for V57: refCnt = 1, refCntWtd = 2 New refCnts for V57: refCnt = 2, refCntWtd = 4 New refCnts for V36: refCnt = 6, refCntWtd = 29 New refCnts for V56: refCnt = 1, refCntWtd = 4 New refCnts for V56: refCnt = 2, refCntWtd = 8 New refCnts for V36: refCnt = 7, refCntWtd = 31 New refCnts for V56: refCnt = 3, refCntWtd = 12 New refCnts for V57: refCnt = 3, refCntWtd = 6 New refCnts for V57: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 26, refCntWtd = 204 New refCnts for V18: refCnt = 27, refCntWtd = 206 New refCnts for V00: refCnt = 21, refCntWtd = 109.50 New refCnts for V99: refCnt = 1, refCntWtd = 2 New refCnts for V99: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 22, refCntWtd = 111.50 New refCnts for V00: refCnt = 23, refCntWtd = 113.50 New refCnts for V100: refCnt = 1, refCntWtd = 4 New refCnts for V99: refCnt = 3, refCntWtd = 6 New refCnts for V100: refCnt = 2, refCntWtd = 8 New refCnts for V100: refCnt = 3, refCntWtd = 12 New refCnts for V99: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 28, refCntWtd = 208 New refCnts for V99: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 24, refCntWtd = 115.50 New refCnts for V00: refCnt = 25, refCntWtd = 117.50 New refCnts for V18: refCnt = 29, refCntWtd = 210 New refCnts for V12: refCnt = 6, refCntWtd = 29 New refCnts for V08: refCnt = 10, refCntWtd = 39.50 New refCnts for V20: refCnt = 12, refCntWtd = 63 New refCnts for V144: refCnt = 9, refCntWtd = 27 New refCnts for V143: refCnt = 6, refCntWtd = 19 New refCnts for V20: refCnt = 13, refCntWtd = 65 New refCnts for V08: refCnt = 11, refCntWtd = 41.50 New refCnts for V20: refCnt = 14, refCntWtd = 67 New refCnts for V03: refCnt = 7, refCntWtd = 14.50 New refCnts for V102: refCnt = 1, refCntWtd = 4 New refCnts for V102: refCnt = 2, refCntWtd = 8 New refCnts for V00: refCnt = 26, refCntWtd = 119.50 New refCnts for V103: refCnt = 1, refCntWtd = 2 New refCnts for V102: refCnt = 3, refCntWtd = 12 New refCnts for V103: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 27, refCntWtd = 121.50 New refCnts for V00: refCnt = 28, refCntWtd = 123.50 New refCnts for V104: refCnt = 1, refCntWtd = 4 New refCnts for V103: refCnt = 3, refCntWtd = 6 New refCnts for V104: refCnt = 2, refCntWtd = 8 New refCnts for V104: refCnt = 3, refCntWtd = 12 New refCnts for V103: refCnt = 4, refCntWtd = 8 New refCnts for V102: refCnt = 4, refCntWtd = 16 New refCnts for V102: refCnt = 5, refCntWtd = 20 New refCnts for V103: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 29, refCntWtd = 125.50 New refCnts for V00: refCnt = 30, refCntWtd = 127.50 New refCnts for V102: refCnt = 6, refCntWtd = 24 New refCnts for V20: refCnt = 15, refCntWtd = 69 New refCnts for V20: refCnt = 16, refCntWtd = 71 New refCnts for V08: refCnt = 12, refCntWtd = 43.50 New refCnts for V08: refCnt = 13, refCntWtd = 45.50 New refCnts for V08: refCnt = 14, refCntWtd = 47.50 New refCnts for V21: refCnt = 2, refCntWtd = 3 New refCnts for V07: refCnt = 7, refCntWtd = 23 New refCnts for V05: refCnt = 17, refCntWtd = 54 New refCnts for V04: refCnt = 15, refCntWtd = 96 New refCnts for V36: refCnt = 8, refCntWtd = 33 New refCnts for V03: refCnt = 8, refCntWtd = 16.50 New refCnts for V106: refCnt = 1, refCntWtd = 4 New refCnts for V106: refCnt = 2, refCntWtd = 8 New refCnts for V00: refCnt = 31, refCntWtd = 129.50 New refCnts for V107: refCnt = 1, refCntWtd = 2 New refCnts for V106: refCnt = 3, refCntWtd = 12 New refCnts for V107: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 32, refCntWtd = 131.50 New refCnts for V00: refCnt = 33, refCntWtd = 133.50 New refCnts for V108: refCnt = 1, refCntWtd = 4 New refCnts for V107: refCnt = 3, refCntWtd = 6 New refCnts for V108: refCnt = 2, refCntWtd = 8 New refCnts for V108: refCnt = 3, refCntWtd = 12 New refCnts for V107: refCnt = 4, refCntWtd = 8 New refCnts for V106: refCnt = 4, refCntWtd = 16 New refCnts for V106: refCnt = 5, refCntWtd = 20 New refCnts for V107: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 34, refCntWtd = 135.50 New refCnts for V00: refCnt = 35, refCntWtd = 137.50 New refCnts for V106: refCnt = 6, refCntWtd = 24 New refCnts for V21: refCnt = 3, refCntWtd = 5 New refCnts for V110: refCnt = 2, refCntWtd = 8 New refCnts for V00: refCnt = 36, refCntWtd = 139.50 New refCnts for V111: refCnt = 1, refCntWtd = 2 New refCnts for V110: refCnt = 3, refCntWtd = 12 New refCnts for V111: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 37, refCntWtd = 141.50 New refCnts for V00: refCnt = 38, refCntWtd = 143.50 New refCnts for V112: refCnt = 1, refCntWtd = 4 New refCnts for V111: refCnt = 3, refCntWtd = 6 New refCnts for V112: refCnt = 2, refCntWtd = 8 New refCnts for V112: refCnt = 3, refCntWtd = 12 New refCnts for V111: refCnt = 4, refCntWtd = 8 New refCnts for V110: refCnt = 4, refCntWtd = 16 New refCnts for V110: refCnt = 5, refCntWtd = 20 New refCnts for V111: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 39, refCntWtd = 145.50 New refCnts for V00: refCnt = 40, refCntWtd = 147.50 New refCnts for V110: refCnt = 6, refCntWtd = 24 New refCnts for V03: refCnt = 9, refCntWtd = 18.50 New refCnts for V114: refCnt = 1, refCntWtd = 4 New refCnts for V114: refCnt = 2, refCntWtd = 8 New refCnts for V00: refCnt = 41, refCntWtd = 149.50 New refCnts for V115: refCnt = 1, refCntWtd = 2 New refCnts for V114: refCnt = 3, refCntWtd = 12 New refCnts for V115: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 42, refCntWtd = 151.50 New refCnts for V00: refCnt = 43, refCntWtd = 153.50 New refCnts for V116: refCnt = 1, refCntWtd = 4 New refCnts for V115: refCnt = 3, refCntWtd = 6 New refCnts for V116: refCnt = 2, refCntWtd = 8 New refCnts for V116: refCnt = 3, refCntWtd = 12 New refCnts for V115: refCnt = 4, refCntWtd = 8 New refCnts for V114: refCnt = 4, refCntWtd = 16 New refCnts for V114: refCnt = 5, refCntWtd = 20 New refCnts for V115: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 44, refCntWtd = 155.50 New refCnts for V00: refCnt = 45, refCntWtd = 157.50 New refCnts for V114: refCnt = 6, refCntWtd = 24 New refCnts for V16: refCnt = 30, refCntWtd = 726 New refCnts for V59: refCnt = 1, refCntWtd = 16 New refCnts for V59: refCnt = 2, refCntWtd = 32 New refCnts for V16: refCnt = 31, refCntWtd = 734 New refCnts for V172: refCnt = 1, refCntWtd = 8 New refCnts for V119: refCnt = 1, refCntWtd = 16 New refCnts for V00: refCnt = 46, refCntWtd = 165.50 New refCnts for V118: refCnt = 1, refCntWtd = 8 New refCnts for V118: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 47, refCntWtd = 173.50 New refCnts for V00: refCnt = 48, refCntWtd = 181.50 New refCnts for V120: refCnt = 1, refCntWtd = 16 New refCnts for V118: refCnt = 3, refCntWtd = 24 New refCnts for V120: refCnt = 2, refCntWtd = 32 New refCnts for V120: refCnt = 3, refCntWtd = 48 New refCnts for V118: refCnt = 4, refCntWtd = 32 New refCnts for V119: refCnt = 2, refCntWtd = 32 New refCnts for V118: refCnt = 5, refCntWtd = 40 New refCnts for V00: refCnt = 49, refCntWtd = 189.50 New refCnts for V00: refCnt = 50, refCntWtd = 197.50 New refCnts for V119: refCnt = 3, refCntWtd = 48 New refCnts for V16: refCnt = 32, refCntWtd = 750 New refCnts for V179: refCnt = 10, refCntWtd = 242 New refCnts for V34: refCnt = 3, refCntWtd = 21 New refCnts for V16: refCnt = 33, refCntWtd = 766 New refCnts for V172: refCnt = 2, refCntWtd = 24 New refCnts for V172: refCnt = 3, refCntWtd = 40 New refCnts for V172: refCnt = 4, refCntWtd = 56 New refCnts for V18: refCnt = 30, refCntWtd = 226 New refCnts for V16: refCnt = 34, refCntWtd = 768 New refCnts for V179: refCnt = 11, refCntWtd = 244 New refCnts for V34: refCnt = 4, refCntWtd = 23 New refCnts for V16: refCnt = 35, refCntWtd = 770 New refCnts for V172: refCnt = 5, refCntWtd = 58 New refCnts for V172: refCnt = 6, refCntWtd = 60 New refCnts for V16: refCnt = 36, refCntWtd = 772 New refCnts for V16: refCnt = 37, refCntWtd = 774 New refCnts for V16: refCnt = 38, refCntWtd = 776 New refCnts for V179: refCnt = 12, refCntWtd = 246 New refCnts for V34: refCnt = 5, refCntWtd = 25 New refCnts for V16: refCnt = 39, refCntWtd = 778 New refCnts for V176: refCnt = 1, refCntWtd = 2 New refCnts for V176: refCnt = 2, refCntWtd = 4 New refCnts for V16: refCnt = 40, refCntWtd = 780 New refCnts for V51: refCnt = 1, refCntWtd = 4 New refCnts for V51: refCnt = 2, refCntWtd = 8 New refCnts for V16: refCnt = 41, refCntWtd = 782 New refCnts for V176: refCnt = 3, refCntWtd = 6 New refCnts for V123: refCnt = 1, refCntWtd = 4 New refCnts for V00: refCnt = 51, refCntWtd = 199.50 New refCnts for V122: refCnt = 1, refCntWtd = 2 New refCnts for V122: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 52, refCntWtd = 201.50 New refCnts for V00: refCnt = 53, refCntWtd = 203.50 New refCnts for V124: refCnt = 1, refCntWtd = 4 New refCnts for V122: refCnt = 3, refCntWtd = 6 New refCnts for V124: refCnt = 2, refCntWtd = 8 New refCnts for V124: refCnt = 3, refCntWtd = 12 New refCnts for V122: refCnt = 4, refCntWtd = 8 New refCnts for V123: refCnt = 2, refCntWtd = 8 New refCnts for V122: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 54, refCntWtd = 205.50 New refCnts for V00: refCnt = 55, refCntWtd = 207.50 New refCnts for V123: refCnt = 3, refCntWtd = 12 New refCnts for V37: refCnt = 1, refCntWtd = 2 New refCnts for V38: refCnt = 1, refCntWtd = 2 New refCnts for V09: refCnt = 5, refCntWtd = 23 New refCnts for V16: refCnt = 42, refCntWtd = 784 New refCnts for V179: refCnt = 13, refCntWtd = 248 New refCnts for V34: refCnt = 6, refCntWtd = 27 New refCnts for V16: refCnt = 43, refCntWtd = 786 New refCnts for V176: refCnt = 4, refCntWtd = 8 New refCnts for V176: refCnt = 5, refCntWtd = 10 New refCnts for V16: refCnt = 44, refCntWtd = 788 New refCnts for V179: refCnt = 14, refCntWtd = 250 New refCnts for V34: refCnt = 7, refCntWtd = 29 New refCnts for V16: refCnt = 45, refCntWtd = 790 New refCnts for V176: refCnt = 6, refCntWtd = 12 New refCnts for V176: refCnt = 7, refCntWtd = 14 New refCnts for V34: refCnt = 8, refCntWtd = 31 New refCnts for V16: refCnt = 46, refCntWtd = 792 New refCnts for V37: refCnt = 2, refCntWtd = 4 New refCnts for V176: refCnt = 8, refCntWtd = 16 New refCnts for V34: refCnt = 9, refCntWtd = 33 New refCnts for V16: refCnt = 47, refCntWtd = 794 New refCnts for V00: refCnt = 56, refCntWtd = 209.50 New refCnts for V126: refCnt = 1, refCntWtd = 2 New refCnts for V126: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 57, refCntWtd = 211.50 New refCnts for V00: refCnt = 58, refCntWtd = 213.50 New refCnts for V127: refCnt = 1, refCntWtd = 4 New refCnts for V126: refCnt = 3, refCntWtd = 6 New refCnts for V127: refCnt = 2, refCntWtd = 8 New refCnts for V127: refCnt = 3, refCntWtd = 12 New refCnts for V126: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 31, refCntWtd = 228 New refCnts for V126: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 59, refCntWtd = 215.50 New refCnts for V38: refCnt = 2, refCntWtd = 10 New refCnts for V38: refCnt = 3, refCntWtd = 18 New refCnts for V16: refCnt = 48, refCntWtd = 810 New refCnts for V54: refCnt = 1, refCntWtd = 32 New refCnts for V54: refCnt = 2, refCntWtd = 64 New refCnts for V16: refCnt = 49, refCntWtd = 826 New refCnts for V16: refCnt = 50, refCntWtd = 842 New refCnts for V179: refCnt = 15, refCntWtd = 266 New refCnts for V34: refCnt = 10, refCntWtd = 49 New refCnts for V16: refCnt = 51, refCntWtd = 858 New refCnts for V38: refCnt = 4, refCntWtd = 20 New refCnts for V38: refCnt = 5, refCntWtd = 22 New refCnts for V17: refCnt = 6, refCntWtd = 17 New refCnts for V01: refCnt = 15, refCntWtd = 19.50 New refCnts for V05: refCnt = 18, refCntWtd = 56 New refCnts for V55: refCnt = 1, refCntWtd = 2 New refCnts for V55: refCnt = 2, refCntWtd = 4 New refCnts for V37: refCnt = 3, refCntWtd = 6 New refCnts for V00: refCnt = 60, refCntWtd = 217.50 New refCnts for V03: refCnt = 10, refCntWtd = 20.50 New refCnts for V55: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 32, refCntWtd = 230 New refCnts for V38: refCnt = 6, refCntWtd = 24 New refCnts for V09: refCnt = 6, refCntWtd = 25 New refCnts for V00: refCnt = 61, refCntWtd = 219.50 New refCnts for V129: refCnt = 1, refCntWtd = 2 New refCnts for V129: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 62, refCntWtd = 221.50 New refCnts for V00: refCnt = 63, refCntWtd = 223.50 New refCnts for V130: refCnt = 1, refCntWtd = 4 New refCnts for V129: refCnt = 3, refCntWtd = 6 New refCnts for V130: refCnt = 2, refCntWtd = 8 New refCnts for V130: refCnt = 3, refCntWtd = 12 New refCnts for V129: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 33, refCntWtd = 232 New refCnts for V129: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 64, refCntWtd = 225.50 New refCnts for V00: refCnt = 65, refCntWtd = 227.50 New refCnts for V18: refCnt = 34, refCntWtd = 234 New refCnts for V16: refCnt = 52, refCntWtd = 860 New refCnts for V179: refCnt = 16, refCntWtd = 268 New refCnts for V34: refCnt = 11, refCntWtd = 51 New refCnts for V16: refCnt = 53, refCntWtd = 862 New refCnts for V175: refCnt = 1, refCntWtd = 2 New refCnts for V175: refCnt = 2, refCntWtd = 4 New refCnts for V175: refCnt = 3, refCntWtd = 6 New refCnts for V16: refCnt = 54, refCntWtd = 864 New refCnts for V52: refCnt = 1, refCntWtd = 4 New refCnts for V52: refCnt = 2, refCntWtd = 8 New refCnts for V16: refCnt = 55, refCntWtd = 866 New refCnts for V175: refCnt = 4, refCntWtd = 8 New refCnts for V133: refCnt = 1, refCntWtd = 4 New refCnts for V00: refCnt = 66, refCntWtd = 229.50 New refCnts for V132: refCnt = 1, refCntWtd = 2 New refCnts for V132: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 67, refCntWtd = 231.50 New refCnts for V00: refCnt = 68, refCntWtd = 233.50 New refCnts for V134: refCnt = 1, refCntWtd = 4 New refCnts for V132: refCnt = 3, refCntWtd = 6 New refCnts for V134: refCnt = 2, refCntWtd = 8 New refCnts for V134: refCnt = 3, refCntWtd = 12 New refCnts for V132: refCnt = 4, refCntWtd = 8 New refCnts for V133: refCnt = 2, refCntWtd = 8 New refCnts for V132: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 69, refCntWtd = 235.50 New refCnts for V00: refCnt = 70, refCntWtd = 237.50 New refCnts for V133: refCnt = 3, refCntWtd = 12 New refCnts for V16: refCnt = 56, refCntWtd = 874 New refCnts for V53: refCnt = 1, refCntWtd = 16 New refCnts for V53: refCnt = 2, refCntWtd = 32 New refCnts for V16: refCnt = 57, refCntWtd = 882 New refCnts for V173: refCnt = 1, refCntWtd = 8 New refCnts for V137: refCnt = 1, refCntWtd = 16 New refCnts for V00: refCnt = 71, refCntWtd = 245.50 New refCnts for V136: refCnt = 1, refCntWtd = 8 New refCnts for V136: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 72, refCntWtd = 253.50 New refCnts for V00: refCnt = 73, refCntWtd = 261.50 New refCnts for V138: refCnt = 1, refCntWtd = 16 New refCnts for V136: refCnt = 3, refCntWtd = 24 New refCnts for V138: refCnt = 2, refCntWtd = 32 New refCnts for V138: refCnt = 3, refCntWtd = 48 New refCnts for V136: refCnt = 4, refCntWtd = 32 New refCnts for V137: refCnt = 2, refCntWtd = 32 New refCnts for V136: refCnt = 5, refCntWtd = 40 New refCnts for V00: refCnt = 74, refCntWtd = 269.50 New refCnts for V00: refCnt = 75, refCntWtd = 277.50 New refCnts for V137: refCnt = 3, refCntWtd = 48 New refCnts for V16: refCnt = 58, refCntWtd = 898 New refCnts for V179: refCnt = 17, refCntWtd = 284 New refCnts for V34: refCnt = 12, refCntWtd = 67 New refCnts for V16: refCnt = 59, refCntWtd = 914 New refCnts for V173: refCnt = 2, refCntWtd = 24 New refCnts for V173: refCnt = 3, refCntWtd = 40 New refCnts for V00: refCnt = 76, refCntWtd = 279.50 New refCnts for V140: refCnt = 1, refCntWtd = 2 New refCnts for V140: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 77, refCntWtd = 281.50 New refCnts for V00: refCnt = 78, refCntWtd = 283.50 New refCnts for V141: refCnt = 1, refCntWtd = 4 New refCnts for V140: refCnt = 3, refCntWtd = 6 New refCnts for V141: refCnt = 2, refCntWtd = 8 New refCnts for V141: refCnt = 3, refCntWtd = 12 New refCnts for V140: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 35, refCntWtd = 236 New refCnts for V140: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 79, refCntWtd = 285.50 New refCnts for V00: refCnt = 80, refCntWtd = 287.50 New refCnts for V18: refCnt = 36, refCntWtd = 238 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 81, refCntWtd = 288.50 New refCnts for V00: refCnt = 82, refCntWtd = 289.50 New refCnts for V01: refCnt = 16, refCntWtd = 20.50 New refCnts for V01: refCnt = 17, refCntWtd = 21.50 New refCnts for V02: refCnt = 4, refCntWtd = 7 New refCnts for V02: refCnt = 5, refCntWtd = 8 New refCnts for V03: refCnt = 11, refCntWtd = 21.50 New refCnts for V03: refCnt = 12, refCntWtd = 22.50 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 byref single-def ptr ; V01 arg1 byref single-def ptr ; V02 arg2 struct do-not-enreg[SFA] multireg-arg ld-addr-op single-def ptr ; V03 arg3 ref class-hnd single-def ptr ; V04 loc0 int ptr ; V05 loc1 int ptr ; V06 loc2 int ptr ; V07 loc3 int ptr ; V08 loc4 int ptr ; V09 loc5 bool ; V10 loc6 int ptr ; V11 loc7 int ; V12 loc8 bool ; V13 loc9 int ; V14 loc10 int ptr ; V15 loc11 int ptr ; V16 loc12 int ptr ; V17 loc13 long ptr ; V18 loc14 ushort ptr ; V19 loc15 struct ld-addr-op ; V20 loc16 int ptr ; V21 loc17 bool ; V22 loc18 long ptr ; V23 loc19 byref pinned ptr ; V24 loc20 int ; V25 loc21 struct ; V26 loc22 ref class-hnd single-def ptr ; V27 loc23 int ptr ; V28 loc24 int ptr ; V29 loc25 int ptr ; V30 loc26 int ptr ; V31 loc27 int ptr ; V32 loc28 int ptr ; V33 loc29 ref class-hnd exact ptr ; V34 loc30 long ptr ; V35 loc31 byref pinned ptr ; V36 loc32 long ptr ; V37 loc33 bool ; V38 loc34 int ; V39 loc35 int ; V40 OutArgs lclBlk <0> "OutgoingArgSpace" ; V41 tmp1 struct ; V42 tmp2 struct multireg-arg ; V43 tmp3 int ; V44 tmp4 int ptr ; V45 tmp5 int ptr ; V46 tmp6 int ptr ; V47 tmp7 blk do-not-enreg[X] addr-exposed ld-addr-op unsafe-buffer "stackallocLocal" ; V48 tmp8 struct ld-addr-op "NewObj constructor temp" ; V49 tmp9 int ptr "impSpillLclRefs" ; V50 tmp10 int ptr "dup spill" ; V51 tmp11 int ptr "impSpillLclRefs" ; V52 tmp12 int ptr "impSpillLclRefs" ; V53 tmp13 int ptr "impSpillLclRefs" ; V54 tmp14 int ptr "dup spill" ; V55 tmp15 int ptr ; V56 tmp16 long ptr "impSpillLclRefs" ; V57 tmp17 int ptr ; V58 tmp18 int ptr ; V59 tmp19 int ptr "impSpillLclRefs" ; V60 tmp20 byref ptr ; V61 tmp21 long ptr "impSpillLclRefs" ; V62 tmp22 byref ptr ; V63 tmp23 int ptr ; V64 tmp24 int ptr ; V65 tmp25 int ptr ; V66 tmp26 int ptr ; V67 tmp27 int ptr ; V68 tmp28 struct "struct address for call/obj" ; V69 tmp29 byref ptr "dup spill" ; V70 tmp30 int ptr ; V71 tmp31 int ptr "impSpillLclRefs" ; V72 tmp32 int ptr "dup spill" ; V73 tmp33 int ptr "dup spill" ; V74 tmp34 int ptr "impSpillLclRefs" ; V75 tmp35 struct ; V76 tmp36 byref single-def ptr "Span.get_Item ptrToSpan" ; V77 tmp37 struct ld-addr-op "Inlining Arg" ; V78 tmp38 struct ld-addr-op "NewObj constructor temp" ; V79 tmp39 struct ld-addr-op "Inlining Arg" ; V80 tmp40 int "impAppendStmt" ; V81 tmp41 byref ptr "Inlining Arg" ; V82 tmp42 byref ptr "Inlining Arg" ; V83 tmp43 long ptr "Inlining Arg" ; V84 tmp44 long "Inlining Arg" ; V85 tmp45 struct ld-addr-op "NewObj constructor temp" ; V86 tmp46 ref class-hnd single-def ptr "Inlining Arg" ; V87 tmp47 int ptr "Inline stloc first use temp" ; V88 tmp48 byref single-def ptr "Span.get_Item ptrToSpan" ; V89 tmp49 byref "Inlining Arg" ; V90 tmp50 struct ld-addr-op "Inlining Arg" ; V91 tmp51 int ptr "Inline stloc first use temp" ; V92 tmp52 ushort ptr "Inlining Arg" ; V93 tmp53 byref ptr "Span.get_Item ptrToSpan" ; V94 tmp54 byref "Inlining Arg" ; V95 tmp55 ref class-hnd ptr "Inlining Arg" ; V96 tmp56 int ptr "Inline stloc first use temp" ; V97 tmp57 byref ptr "Span.get_Item ptrToSpan" ; V98 tmp58 byref "Inlining Arg" ; V99 tmp59 int ptr "Inline stloc first use temp" ; V100 tmp60 byref ptr "Span.get_Item ptrToSpan" ; V101 tmp61 byref "Inlining Arg" ; V102 tmp62 ref class-hnd ptr "Inlining Arg" ; V103 tmp63 int ptr "Inline stloc first use temp" ; V104 tmp64 byref ptr "Span.get_Item ptrToSpan" ; V105 tmp65 byref "Inlining Arg" ; V106 tmp66 ref class-hnd ptr "Inlining Arg" ; V107 tmp67 int ptr "Inline stloc first use temp" ; V108 tmp68 byref ptr "Span.get_Item ptrToSpan" ; V109 tmp69 byref "Inlining Arg" ; V110 tmp70 ref class-hnd ptr "Inlining Arg" ; V111 tmp71 int ptr "Inline stloc first use temp" ; V112 tmp72 byref ptr "Span.get_Item ptrToSpan" ; V113 tmp73 byref "Inlining Arg" ; V114 tmp74 ref class-hnd ptr "Inlining Arg" ; V115 tmp75 int ptr "Inline stloc first use temp" ; V116 tmp76 byref ptr "Span.get_Item ptrToSpan" ; V117 tmp77 byref "Inlining Arg" ; V118 tmp78 int ptr "Inline stloc first use temp" ; V119 tmp79 ushort ptr "Inlining Arg" ; V120 tmp80 byref ptr "Span.get_Item ptrToSpan" ; V121 tmp81 byref "Inlining Arg" ; V122 tmp82 int ptr "Inline stloc first use temp" ; V123 tmp83 ushort ptr "Inlining Arg" ; V124 tmp84 byref ptr "Span.get_Item ptrToSpan" ; V125 tmp85 byref "Inlining Arg" ; V126 tmp86 int ptr "Inline stloc first use temp" ; V127 tmp87 byref ptr "Span.get_Item ptrToSpan" ; V128 tmp88 byref "Inlining Arg" ; V129 tmp89 int ptr "Inline stloc first use temp" ; V130 tmp90 byref ptr "Span.get_Item ptrToSpan" ; V131 tmp91 byref "Inlining Arg" ; V132 tmp92 int ptr "Inline stloc first use temp" ; V133 tmp93 ushort ptr "Inlining Arg" ; V134 tmp94 byref ptr "Span.get_Item ptrToSpan" ; V135 tmp95 byref "Inlining Arg" ; V136 tmp96 int ptr "Inline stloc first use temp" ; V137 tmp97 ushort ptr "Inlining Arg" ; V138 tmp98 byref ptr "Span.get_Item ptrToSpan" ; V139 tmp99 byref "Inlining Arg" ; V140 tmp100 int ptr "Inline stloc first use temp" ; V141 tmp101 byref ptr "Span.get_Item ptrToSpan" ; V142 tmp102 byref "Inlining Arg" ; V143 tmp103 byref ptr V19._reference(offs=0x00) P-INDEP "field V19._reference (fldOffset=0x0)" ; V144 tmp104 int ptr V19._length(offs=0x08) P-INDEP "field V19._length (fldOffset=0x8)" ; V145 tmp105 byref V25._reference(offs=0x00) P-INDEP "field V25._reference (fldOffset=0x0)" ; V146 tmp106 int V25._length(offs=0x08) P-INDEP "field V25._length (fldOffset=0x8)" ; V147 tmp107 byref single-def ptr V41._reference(offs=0x00) P-INDEP "field V41._reference (fldOffset=0x0)" ; V148 tmp108 int ptr V41._length(offs=0x08) P-INDEP "field V41._length (fldOffset=0x8)" ; V149 tmp109 byref ptr V42._reference(offs=0x00) P-INDEP "field V42._reference (fldOffset=0x0)" ; V150 tmp110 int ptr V42._length(offs=0x08) P-INDEP "field V42._length (fldOffset=0x8)" ; V151 tmp111 byref ptr V48._reference(offs=0x00) P-INDEP "field V48._reference (fldOffset=0x0)" ; V152 tmp112 int ptr V48._length(offs=0x08) P-INDEP "field V48._length (fldOffset=0x8)" ; V153 tmp113 byref V68._reference(offs=0x00) P-INDEP "field V68._reference (fldOffset=0x0)" ; V154 tmp114 int V68._length(offs=0x08) P-INDEP "field V68._length (fldOffset=0x8)" ; V155 tmp115 byref single-def ptr V75._reference(offs=0x00) P-INDEP "field V75._reference (fldOffset=0x0)" ; V156 tmp116 int ptr V75._length(offs=0x08) P-INDEP "field V75._length (fldOffset=0x8)" ; V157 tmp117 byref ptr V77._reference(offs=0x00) P-INDEP "field V77._reference (fldOffset=0x0)" ; V158 tmp118 int ptr V77._length(offs=0x08) P-INDEP "field V77._length (fldOffset=0x8)" ; V159 tmp119 byref ptr V78._reference(offs=0x00) P-INDEP "field V78._reference (fldOffset=0x0)" ; V160 tmp120 int ptr V78._length(offs=0x08) P-INDEP "field V78._length (fldOffset=0x8)" ; V161 tmp121 byref ptr V79._reference(offs=0x00) P-INDEP "field V79._reference (fldOffset=0x0)" ; V162 tmp122 int ptr V79._length(offs=0x08) P-INDEP "field V79._length (fldOffset=0x8)" ; V163 tmp123 byref ptr V85._reference(offs=0x00) P-INDEP "field V85._reference (fldOffset=0x0)" ; V164 tmp124 int ptr V85._length(offs=0x08) P-INDEP "field V85._length (fldOffset=0x8)" ; V165 tmp125 byref single-def ptr V90._reference(offs=0x00) P-INDEP "field V90._reference (fldOffset=0x0)" ; V166 tmp126 int ptr V90._length(offs=0x08) P-INDEP "field V90._length (fldOffset=0x8)" ; V167 tmp127 long ptr "Cast away GC" ; V168 tmp128 long ptr "Cast away GC" ; V169 tmp129 long ptr "Cast away GC" ; V170 GsCookie long do-not-enreg[X] addr-exposed "GSSecurityCookie" ; V171 cse0 int "CSE - aggressive" ; V172 cse1 int "CSE - aggressive" ; V173 cse2 int "CSE - moderate" ; V174 cse3 int "CSE - aggressive" ; V175 cse4 int "CSE - conservative" ; V176 cse5 int "CSE - moderate" ; V177 cse6 int "CSE - moderate" ; V178 cse7 int "CSE - conservative" ; V179 cse8 int "CSE - aggressive" ; V180 cse9 byref "CSE - moderate" ; V181 cse10 int "CSE - moderate" ; V182 rat0 int "ReplaceWithLclVar is creating a new local variable" ; V183 rat1 int "ReplaceWithLclVar is creating a new local variable" ; V184 rat2 int "ReplaceWithLclVar is creating a new local variable" ; V185 rat3 int "ReplaceWithLclVar is creating a new local variable" In fgLocalVarLivenessInit Local V02 should not be enregistered because: struct size does not match reg size Tracked variable (141 out of 186) table: V16 loc12 [ int]: refCnt = 59, refCntWtd = 914 V00 arg0 [ byref]: refCnt = 82, refCntWtd = 289.50 V179 cse8 [ int]: refCnt = 17, refCntWtd = 284 V73 tmp33 [ int]: refCnt = 2, refCntWtd = 256 V74 tmp34 [ int]: refCnt = 2, refCntWtd = 256 V18 loc14 [ushort]: refCnt = 36, refCntWtd = 238 V171 cse0 [ int]: refCnt = 3, refCntWtd = 192 V22 loc18 [ long]: refCnt = 8, refCntWtd = 184 V04 loc0 [ int]: refCnt = 15, refCntWtd = 96 V71 tmp31 [ int]: refCnt = 3, refCntWtd = 96 V95 tmp55 [ ref]: refCnt = 5, refCntWtd = 80 V20 loc16 [ int]: refCnt = 16, refCntWtd = 71 V34 loc30 [ long]: refCnt = 12, refCntWtd = 67 V54 tmp14 [ int]: refCnt = 2, refCntWtd = 64 V72 tmp32 [ int]: refCnt = 2, refCntWtd = 64 V172 cse1 [ int]: refCnt = 6, refCntWtd = 60 V05 loc1 [ int]: refCnt = 18, refCntWtd = 56 V174 cse3 [ int]: refCnt = 7, refCntWtd = 56 V13 loc9 [ int]: refCnt = 8, refCntWtd = 48 V93 tmp53 [ byref]: refCnt = 3, refCntWtd = 48 V97 tmp57 [ byref]: refCnt = 3, refCntWtd = 48 V120 tmp80 [ byref]: refCnt = 3, refCntWtd = 48 V138 tmp98 [ byref]: refCnt = 3, refCntWtd = 48 V92 tmp52 [ushort]: refCnt = 3, refCntWtd = 48 V119 tmp79 [ushort]: refCnt = 3, refCntWtd = 48 V137 tmp97 [ushort]: refCnt = 3, refCntWtd = 48 V182 rat0 [ int]: refCnt = 3, refCntWtd = 48 V183 rat1 [ int]: refCnt = 3, refCntWtd = 48 V08 loc4 [ int]: refCnt = 14, refCntWtd = 47.50 V14 loc10 [ int]: refCnt = 11, refCntWtd = 42 V10 loc6 [ int]: refCnt = 6, refCntWtd = 42 V91 tmp51 [ int]: refCnt = 5, refCntWtd = 40 V96 tmp56 [ int]: refCnt = 5, refCntWtd = 40 V118 tmp78 [ int]: refCnt = 5, refCntWtd = 40 V136 tmp96 [ int]: refCnt = 5, refCntWtd = 40 V173 cse2 [ int]: refCnt = 3, refCntWtd = 40 V36 loc32 [ long]: refCnt = 8, refCntWtd = 33 V53 tmp13 [ int]: refCnt = 2, refCntWtd = 32 V59 tmp19 [ int]: refCnt = 2, refCntWtd = 32 V61 tmp21 [ long]: refCnt = 2, refCntWtd = 32 V168 tmp128 [ long]: refCnt = 2, refCntWtd = 32 V06 loc2 [ int]: refCnt = 9, refCntWtd = 30 V12 loc8 [ bool]: refCnt = 6, refCntWtd = 29 V144 tmp104 [ int]: refCnt = 9, refCntWtd = 27 V11 loc7 [ int]: refCnt = 5, refCntWtd = 27 V09 loc5 [ bool]: refCnt = 6, refCntWtd = 25 V03 arg3 [ ref]: refCnt = 12, refCntWtd = 22.50 V102 tmp62 [ ref]: refCnt = 6, refCntWtd = 24 V106 tmp66 [ ref]: refCnt = 6, refCntWtd = 24 V110 tmp70 [ ref]: refCnt = 6, refCntWtd = 24 V114 tmp74 [ ref]: refCnt = 6, refCntWtd = 24 V38 loc34 [ int]: refCnt = 6, refCntWtd = 24 V69 tmp29 [ byref]: refCnt = 3, refCntWtd = 24 V157 tmp117 [ byref]: refCnt = 3, refCntWtd = 24 V49 tmp9 [ int]: refCnt = 3, refCntWtd = 24 V63 tmp23 [ int]: refCnt = 3, refCntWtd = 24 V177 cse6 [ int]: refCnt = 3, refCntWtd = 24 V181 cse10 [ int]: refCnt = 3, refCntWtd = 24 V01 arg1 [ byref]: refCnt = 17, refCntWtd = 21.50 V07 loc3 [ int]: refCnt = 7, refCntWtd = 23 V143 tmp103 [ byref]: refCnt = 6, refCntWtd = 19 V15 loc11 [ int]: refCnt = 6, refCntWtd = 19 V28 loc24 [ int]: refCnt = 7, refCntWtd = 17.50 V17 loc13 [ long]: refCnt = 6, refCntWtd = 17 V176 cse5 [ int]: refCnt = 8, refCntWtd = 16 V62 tmp22 [ byref]: refCnt = 2, refCntWtd = 16 V50 tmp10 [ int]: refCnt = 2, refCntWtd = 16 V180 cse9 [ byref]: refCnt = 5, refCntWtd = 15 V27 loc23 [ int]: refCnt = 6, refCntWtd = 12.50 V100 tmp60 [ byref]: refCnt = 3, refCntWtd = 12 V104 tmp64 [ byref]: refCnt = 3, refCntWtd = 12 V108 tmp68 [ byref]: refCnt = 3, refCntWtd = 12 V112 tmp72 [ byref]: refCnt = 3, refCntWtd = 12 V116 tmp76 [ byref]: refCnt = 3, refCntWtd = 12 V124 tmp84 [ byref]: refCnt = 3, refCntWtd = 12 V127 tmp87 [ byref]: refCnt = 3, refCntWtd = 12 V130 tmp90 [ byref]: refCnt = 3, refCntWtd = 12 V134 tmp94 [ byref]: refCnt = 3, refCntWtd = 12 V141 tmp101 [ byref]: refCnt = 3, refCntWtd = 12 V56 tmp16 [ long]: refCnt = 3, refCntWtd = 12 V123 tmp83 [ushort]: refCnt = 3, refCntWtd = 12 V133 tmp93 [ushort]: refCnt = 3, refCntWtd = 12 V184 rat2 [ int]: refCnt = 3, refCntWtd = 12 V185 rat3 [ int]: refCnt = 3, refCntWtd = 12 V30 loc26 [ int]: refCnt = 5, refCntWtd = 11 V33 loc29 [ ref]: refCnt = 5, refCntWtd = 10 V02 arg2 [struct]: refCnt = 5, refCntWtd = 8 V99 tmp59 [ int]: refCnt = 5, refCntWtd = 10 V103 tmp63 [ int]: refCnt = 5, refCntWtd = 10 V107 tmp67 [ int]: refCnt = 5, refCntWtd = 10 V111 tmp71 [ int]: refCnt = 5, refCntWtd = 10 V115 tmp75 [ int]: refCnt = 5, refCntWtd = 10 V122 tmp82 [ int]: refCnt = 5, refCntWtd = 10 V126 tmp86 [ int]: refCnt = 5, refCntWtd = 10 V129 tmp89 [ int]: refCnt = 5, refCntWtd = 10 V132 tmp92 [ int]: refCnt = 5, refCntWtd = 10 V140 tmp100 [ int]: refCnt = 5, refCntWtd = 10 V57 tmp17 [ int]: refCnt = 4, refCntWtd = 8 V175 cse4 [ int]: refCnt = 4, refCntWtd = 8 V70 tmp30 [ int]: refCnt = 3, refCntWtd = 8 V51 tmp11 [ int]: refCnt = 2, refCntWtd = 8 V52 tmp12 [ int]: refCnt = 2, refCntWtd = 8 V83 tmp43 [ long]: refCnt = 2, refCntWtd = 8 V60 tmp20 [ byref]: refCnt = 1, refCntWtd = 8 V76 tmp36 [ byref]: refCnt = 3, refCntWtd = 6 V37 loc33 [ bool]: refCnt = 3, refCntWtd = 6 V55 tmp15 [ int]: refCnt = 3, refCntWtd = 6 V58 tmp18 [ int]: refCnt = 3, refCntWtd = 6 V26 loc22 [ ref]: refCnt = 5, refCntWtd = 5.50 V86 tmp46 [ ref]: refCnt = 5, refCntWtd = 5 V21 loc17 [ bool]: refCnt = 3, refCntWtd = 5 V29 loc25 [ int]: refCnt = 3, refCntWtd = 5 V32 loc28 [ int]: refCnt = 3, refCntWtd = 5 V159 tmp119 [ byref]: refCnt = 2, refCntWtd = 4 V161 tmp121 [ byref]: refCnt = 2, refCntWtd = 4 V163 tmp123 [ byref]: refCnt = 2, refCntWtd = 4 V160 tmp120 [ int]: refCnt = 2, refCntWtd = 4 V164 tmp124 [ int]: refCnt = 2, refCntWtd = 4 V167 tmp127 [ long]: refCnt = 2, refCntWtd = 4 V169 tmp129 [ long]: refCnt = 2, refCntWtd = 4 V88 tmp48 [ byref]: refCnt = 3, refCntWtd = 3 V165 tmp125 [ byref]: refCnt = 3, refCntWtd = 3 V87 tmp47 [ int]: refCnt = 5, refCntWtd = 2.50 V149 tmp109 [ byref]: refCnt = 4, refCntWtd = 2.50 V43 tmp3 [ int]: refCnt = 4, refCntWtd = 2.50 V150 tmp110 [ int]: refCnt = 4, refCntWtd = 2.50 V178 cse7 [ int]: refCnt = 4, refCntWtd = 2 V147 tmp107 [ byref]: refCnt = 3, refCntWtd = 2 V148 tmp108 [ int]: refCnt = 3, refCntWtd = 2 V151 tmp111 [ byref]: refCnt = 2, refCntWtd = 2 V44 tmp4 [ int]: refCnt = 2, refCntWtd = 2 V45 tmp5 [ int]: refCnt = 2, refCntWtd = 2 V155 tmp115 [ byref]: refCnt = 3, refCntWtd = 1.50 V31 loc27 [ int]: refCnt = 3, refCntWtd = 1.50 V64 tmp24 [ int]: refCnt = 3, refCntWtd = 1.50 V65 tmp25 [ int]: refCnt = 3, refCntWtd = 1.50 V66 tmp26 [ int]: refCnt = 3, refCntWtd = 1.50 V156 tmp116 [ int]: refCnt = 3, refCntWtd = 1.50 V46 tmp6 [ int]: refCnt = 2, refCntWtd = 1 V67 tmp27 [ int]: refCnt = 2, refCntWtd = 1 V152 tmp112 [ int]: refCnt = 1, refCntWtd = 1 *************** In fgPerBlockLocalVarLiveness() BB01 USE(2)={ V01 V02 } + ByrefExposed + GcHeap DEF(8)={V179 V11 V17 V180 V76 V167 V147 V148} + ByrefExposed* + GcHeap* BB02 USE(3)={V01 V147 V148 } + ByrefExposed + GcHeap DEF(2)={ V155 V156} BB03 USE(2)={ V155 V156} DEF(3)={V149 V43 V150 } BB04 USE(2)={ V155 V156} DEF(3)={V149 V43 V150 } BB05 USE(2)={ V147 V148} DEF(3)={V149 V43 V150 } BB06 USE(3)={ V149 V43 V150} + ByrefExposed + GcHeap DEF(1)={V15 } + ByrefExposed* + GcHeap* BB07 USE(2)={ V15 V180} DEF(12)={V16 V22 V04 V05 V13 V10 V168 V06 V12 V09 V157 V07 } BB08 USE(1)={V18} DEF(0)={ } BB09 USE(1)={V18 } DEF(1)={ V182} BB255 USE(1)={V182} DEF(0)={ } BB10 USE(1)={V18 } DEF(1)={ V183} BB256 USE(1)={V183} DEF(0)={ } BB11 USE(1)={V18} DEF(0)={ } BB12 USE(0)={} DEF(0)={} BB13 USE(1)={V18} DEF(0)={ } BB14 USE(1)={V18} DEF(0)={ } BB15 USE(1)={V18} DEF(0)={ } BB16 USE(1)={V13} DEF(1)={V13} BB17 USE(1)={V04} DEF(1)={V04} BB18 USE(1)={V06} DEF(0)={ } BB19 USE(1)={V04 } DEF(1)={ V06} BB20 USE(1)={V04 } DEF(2)={V04 V07} BB21 USE(1)={V05} DEF(0)={ } BB22 USE(1)={V04 } DEF(1)={ V05} BB23 USE(2)={V04 V05} DEF(0)={ } BB24 USE(1)={V10} DEF(0)={ } BB26 USE(2)={V04 V10} DEF(0)={ } BB27 USE(1)={V11} DEF(1)={V11} BB28 USE(0)={ } DEF(1)={V12} BB29 USE(1)={V04 } DEF(2)={ V10 V11} BB30 USE(1)={V13} DEF(1)={V13} BB31 USE(3)={V16 V179 V22} + ByrefExposed + GcHeap DEF(1)={ V171 } BB32 USE(3)={V16 V18 V171} DEF(2)={V16 V74 } BB34 USE(0)={} DEF(0)={} BB35 USE(3)={V16 V179 V22 } + ByrefExposed + GcHeap DEF(1)={ V174} BB36 USE(1)={V16} DEF(1)={V16} BB38 USE(2)={V16 V179} DEF(0)={ } BB39 USE(2)={V16 V22 } + ByrefExposed + GcHeap DEF(1)={ V174} BB40 USE(2)={V16 V179} DEF(0)={ } BB41 USE(2)={V16 V22 } + ByrefExposed + GcHeap DEF(1)={ V174} BB42 USE(1)={V174} DEF(0)={ } BB43 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB44 USE(2)={V16 V179 } DEF(2)={V16 V73} BB45 USE(2)={V16 V22} + ByrefExposed + GcHeap DEF(0)={ } BB46 USE(0)={ } DEF(1)={V09} BB47 USE(2)={V16 V179} DEF(0)={ } BB48 USE(2)={V16 V22 } + ByrefExposed + GcHeap DEF(4)={V16 V18 V71 V72} BB49 USE(1)={V18} DEF(0)={ } BB50 USE(1)={V05} DEF(0)={ } BB51 USE(1)={V04 } DEF(1)={ V05} BB52 USE(1)={V10} DEF(0)={ } BB53 USE(2)={V05 V10} DEF(0)={ } BB54 USE(2)={V13 V11} DEF(1)={V13 } BB55 USE(0)={ } DEF(1)={V12} BB56 USE(1)={V17} + ByrefExposed + GcHeap DEF(0)={ } BB57 USE(3)={V13 V09 V01} + ByrefExposed + GcHeap DEF(1)={ V69 } BB58 USE(3)={V04 V05 V01 } + ByrefExposed + GcHeap DEF(1)={ V70} BB59 USE(1)={V04 } DEF(1)={ V70} BB60 USE(3)={V01 V17 V70} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB61 USE(3)={ V15 V180 V02} + ByrefExposed + GcHeap DEF(1)={V16 } + ByrefExposed* + GcHeap* BB62 USE(1)={V16 } DEF(1)={ V15} BB63 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } BB64 USE(1)={V01} DEF(0)={ } BB65 USE(1)={V01} DEF(0)={ } BB66 USE(4)={V05 V06 V09 V07 } DEF(4)={ V06 V07 V44 V45} BB73 USE(1)={V05 } DEF(2)={ V08 V14} BB74 USE(2)={V05 V01 } + ByrefExposed + GcHeap DEF(4)={ V08 V14 V178 V46} BB78 USE(3)={ V12 V03 V15 } + ByrefExposed + GcHeap DEF(6)={V16 V20 V144 V143 V151 V152} BB79 USE(1)={V03 } + ByrefExposed + GcHeap DEF(4)={ V28 V27 V26 V29} BB81 USE(1)={ V26} + ByrefExposed + GcHeap DEF(1)={V28 } BB82 USE(3)={V08 V14 V28 } DEF(2)={ V30 V64} BB83 USE(1)={V64 } DEF(2)={ V65 V66} BB84 USE(2)={V14 V64 } DEF(2)={ V65 V66} BB85 USE(4)={V06 V30 V65 V66 } DEF(3)={ V32 V31 V67} BB89 USE(1)={V30} DEF(0)={ } BB90 USE(2)={V20 V144} DEF(1)={V20 } BB91 USE(1)={V144 } + ByrefExposed + GcHeap DEF(4)={ V33 V159 V161 V160} BB95 USE(4)={V144 V143 V33 V161 } + ByrefExposed + GcHeap DEF(5)={V144 V143 V83 V163 V164} + ByrefExposed* + GcHeap* BB100 USE(6)={V20 V144 V143 V28 V27 V29} DEF(0)={ } BB101 USE(2)={V27 V26} + ByrefExposed + GcHeap DEF(2)={V27 V30 } BB102 USE(3)={V28 V30 V32} DEF(1)={V28 } BB103 USE(2)={V16 V01} + ByrefExposed + GcHeap DEF(0)={ } BB104 USE(1)={V01} + ByrefExposed + GcHeap DEF(0)={ } BB106 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V86} BB107 USE(2)={V00 V86 } + ByrefExposed + GcHeap DEF(1)={ V87} BB108 USE(3)={V00 V86 V87} + ByrefExposed + GcHeap DEF(1)={ V88 } BB112 USE(2)={ V17 V180 } DEF(5)={V34 V36 V21 V169 V165} BB245 USE(2)={V16 V179} DEF(0)={ } BB246 USE(2)={V16 V34 } + ByrefExposed + GcHeap DEF(4)={V16 V18 V49 V50} BB247 USE(1)={V18} DEF(0)={ } BB248 USE(2)={V01 V15} + ByrefExposed + GcHeap DEF(0)={ } BB249 USE(2)={V00 V01} + ByrefExposed + GcHeap DEF(0)={ } BB251 USE(2)={V00 V03} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB253 USE(0)={} DEF(0)={} BB111 USE(2)={V00 V86} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB113 USE(1)={V14} DEF(0)={ } BB114 USE(1)={V18} DEF(0)={ } BB115 USE(1)={V18} DEF(0)={ } BB117 USE(0)={} DEF(0)={} BB118 USE(2)={V00 V36 } + ByrefExposed + GcHeap DEF(2)={ V177 V60} BB119 USE(1)={V00 } DEF(2)={ V63 V62} BB120 USE(3)={V00 V36 V177 } DEF(4)={ V36 V61 V63 V62} BB121 USE(2)={V00 V63} + ByrefExposed + GcHeap DEF(2)={ V92 V91 } BB122 USE(3)={V00 V92 V91} + ByrefExposed + GcHeap DEF(1)={ V93 } BB123 USE(2)={V00 V92} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB124 USE(2)={V08 V12} DEF(0)={ } BB125 USE(4)={V20 V08 V144 V143} + ByrefExposed + GcHeap DEF(0)={ } BB127 USE(1)={ V03} + ByrefExposed + GcHeap DEF(1)={V95 } BB129 USE(2)={V00 V95 } + ByrefExposed + GcHeap DEF(2)={ V96 V181} BB130 USE(4)={V00 V95 V96 V181} + ByrefExposed + GcHeap DEF(1)={ V97 } BB132 USE(2)={V00 V95} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB133 USE(1)={V20} DEF(1)={V20} BB134 USE(2)={V08 V14} DEF(2)={V08 V14} BB135 USE(1)={V14} DEF(0)={ } BB136 USE(1)={V18} DEF(0)={ } BB137 USE(1)={V18 } DEF(1)={ V184} BB257 USE(1)={V184} DEF(0)={ } BB138 USE(1)={V18 } DEF(1)={ V185} BB258 USE(1)={V185} DEF(0)={ } BB139 USE(1)={V18} DEF(0)={ } BB140 USE(0)={} DEF(0)={} BB141 USE(1)={V18} DEF(0)={ } BB142 USE(1)={V18} DEF(0)={ } BB143 USE(1)={V18} DEF(0)={ } BB144 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V110} BB145 USE(1)={V14} DEF(0)={ } BB146 USE(3)={V08 V14 V06} DEF(1)={ V14 } BB147 USE(0)={ } DEF(1)={V58} BB148 USE(0)={ } DEF(1)={V58} BB149 USE(1)={ V58} DEF(1)={V18 } BB150 USE(1)={V36} + ByrefExposed + GcHeap DEF(0)={ } BB151 USE(2)={V08 V07} DEF(0)={ } BB152 USE(0)={ } DEF(1)={V57} BB153 USE(0)={ } DEF(1)={V57} BB154 USE(1)={V36 } + ByrefExposed + GcHeap DEF(3)={V36 V56 V57} BB155 USE(1)={ V57} DEF(1)={V18 } BB156 USE(1)={V18} DEF(0)={ } BB157 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V99} BB158 USE(3)={V00 V18 V99} + ByrefExposed + GcHeap DEF(1)={ V100 } BB159 USE(2)={V00 V18} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB160 USE(2)={V08 V12} DEF(0)={ } BB161 USE(4)={V20 V08 V144 V143} + ByrefExposed + GcHeap DEF(0)={ } BB163 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V102} BB165 USE(2)={V00 V102 } + ByrefExposed + GcHeap DEF(1)={ V103} BB166 USE(3)={V00 V102 V103} + ByrefExposed + GcHeap DEF(1)={ V104 } BB168 USE(2)={V00 V102} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB169 USE(1)={V20} DEF(1)={V20} BB170 USE(1)={V08} DEF(1)={V08} BB171 USE(2)={V08 V21} DEF(0)={ } BB172 USE(1)={V07} DEF(0)={ } BB173 USE(3)={V04 V05 V36} + ByrefExposed + GcHeap DEF(0)={ } BB174 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V106} BB176 USE(2)={V00 V106 } + ByrefExposed + GcHeap DEF(1)={ V107} BB177 USE(3)={V00 V106 V107} + ByrefExposed + GcHeap DEF(1)={ V108 } BB179 USE(2)={V00 V106} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB180 USE(0)={ } DEF(1)={V21} BB181 USE(1)={V110} DEF(0)={ } BB182 USE(2)={V00 V110 } + ByrefExposed + GcHeap DEF(1)={ V111} BB183 USE(3)={V00 V110 V111} + ByrefExposed + GcHeap DEF(1)={ V112 } BB185 USE(2)={V00 V110} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB186 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V114} BB187 USE(2)={V00 V114 } + ByrefExposed + GcHeap DEF(1)={ V115} BB188 USE(3)={V00 V114 V115} + ByrefExposed + GcHeap DEF(1)={ V116 } BB190 USE(2)={V00 V114} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB191 USE(3)={V16 V00 V172 } + ByrefExposed + GcHeap DEF(4)={V16 V119 V118 V59} BB192 USE(3)={V00 V119 V118} + ByrefExposed + GcHeap DEF(1)={ V120 } BB193 USE(2)={V00 V119} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB194 USE(2)={V16 V179} DEF(0)={ } BB195 USE(2)={V16 V34 } + ByrefExposed + GcHeap DEF(1)={ V172} BB196 USE(2)={V18 V172} DEF(0)={ } BB197 USE(2)={V16 V179} DEF(0)={ } BB198 USE(2)={V16 V34 } + ByrefExposed + GcHeap DEF(1)={ V172} BB199 USE(1)={V16} DEF(1)={V16} BB200 USE(3)={V16 V179 V34 } + ByrefExposed + GcHeap DEF(1)={ V176} BB201 USE(3)={V16 V00 V176 } + ByrefExposed + GcHeap DEF(4)={V16 V123 V122 V51} BB203 USE(3)={V00 V123 V122} + ByrefExposed + GcHeap DEF(1)={ V124 } BB204 USE(2)={V00 V123} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB205 USE(1)={V09 } DEF(2)={ V38 V37} BB206 USE(2)={V16 V179} DEF(0)={ } BB207 USE(2)={V16 V34 } + ByrefExposed + GcHeap DEF(1)={ V176} BB208 USE(2)={V16 V179} DEF(0)={ } BB209 USE(2)={V16 V34 } + ByrefExposed + GcHeap DEF(1)={ V176} BB210 USE(0)={ } DEF(1)={V37} BB213 USE(1)={V176} DEF(0)={ } BB214 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB215 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V126} BB216 USE(3)={V00 V18 V126} + ByrefExposed + GcHeap DEF(1)={ V127 } BB218 USE(1)={V38} DEF(1)={V38} BB219 USE(2)={V16 V179 } DEF(2)={V16 V54} BB220 USE(2)={V16 V34} + ByrefExposed + GcHeap DEF(0)={ } BB221 USE(1)={V38} DEF(0)={ } BB222 USE(0)={ } DEF(1)={V38} BB223 USE(1)={V17} + ByrefExposed + GcHeap DEF(0)={ } BB224 USE(2)={V05 V01 } + ByrefExposed + GcHeap DEF(1)={ V55} BB225 USE(0)={ } DEF(1)={V55} BB226 USE(6)={V00 V18 V03 V38 V37 V55} + ByrefExposed + GcHeap DEF(1)={ V09 } + ByrefExposed* + GcHeap* BB227 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V129} BB228 USE(3)={V00 V18 V129} + ByrefExposed + GcHeap DEF(1)={ V130 } BB229 USE(2)={V00 V18} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB230 USE(2)={V16 V179} DEF(0)={ } BB231 USE(2)={V16 V34 } + ByrefExposed + GcHeap DEF(1)={ V175} BB232 USE(1)={V175} DEF(0)={ } BB233 USE(3)={V16 V00 V175 } + ByrefExposed + GcHeap DEF(4)={V16 V133 V132 V52} BB234 USE(3)={V00 V133 V132} + ByrefExposed + GcHeap DEF(1)={ V134 } BB235 USE(2)={V00 V133} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB236 USE(3)={V16 V00 V173 } + ByrefExposed + GcHeap DEF(4)={V16 V137 V136 V53} BB237 USE(3)={V00 V137 V136} + ByrefExposed + GcHeap DEF(1)={ V138 } BB238 USE(2)={V00 V137} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB239 USE(2)={V16 V179} DEF(0)={ } BB240 USE(2)={V16 V34 } + ByrefExposed + GcHeap DEF(1)={ V173} BB241 USE(0)={} DEF(0)={} BB242 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V140} BB243 USE(3)={V00 V18 V140} + ByrefExposed + GcHeap DEF(1)={ V141 } BB244 USE(2)={V00 V18} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB110 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB254 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (4)={V00 V03 V01 V02 } + ByrefExposed + GcHeap OUT(10)={V00 V179 V11 V03 V01 V17 V180 V02 V147 V148} + ByrefExposed + GcHeap BB02 IN (10)={V00 V179 V11 V03 V01 V17 V180 V02 V147 V148 } + ByrefExposed + GcHeap OUT(10)={V00 V179 V11 V03 V01 V17 V180 V02 V155 V156} + ByrefExposed + GcHeap BB03 IN (10)={V00 V179 V11 V03 V01 V17 V180 V02 V155 V156} + ByrefExposed + GcHeap OUT(11)={V00 V179 V11 V03 V01 V17 V180 V02 V149 V43 V150 } + ByrefExposed + GcHeap BB04 IN (10)={V00 V179 V11 V03 V01 V17 V180 V02 V155 V156} + ByrefExposed + GcHeap OUT(11)={V00 V179 V11 V03 V01 V17 V180 V02 V149 V43 V150 } + ByrefExposed + GcHeap BB05 IN (10)={V00 V179 V11 V03 V01 V17 V180 V02 V147 V148} + ByrefExposed + GcHeap OUT(11)={V00 V179 V11 V03 V01 V17 V180 V02 V149 V43 V150 } + ByrefExposed + GcHeap BB06 IN (11)={V00 V179 V11 V03 V01 V17 V180 V02 V149 V43 V150} + ByrefExposed + GcHeap OUT(9)={V00 V179 V11 V03 V01 V15 V17 V180 V02 } + ByrefExposed + GcHeap BB07 IN (9)={ V00 V179 V11 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB08 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB09 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V18 V22 V04 V05 V13 V182 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB255 IN (21)={V16 V00 V179 V18 V22 V04 V05 V13 V182 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB10 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V18 V22 V04 V05 V13 V183 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB256 IN (20)={V16 V00 V179 V22 V04 V05 V13 V183 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB11 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB12 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB13 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB14 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB15 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB16 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB17 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB18 IN (18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap BB19 IN (17)={V16 V00 V179 V22 V04 V05 V13 V10 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap BB20 IN (18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB21 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB22 IN (18)={V16 V00 V179 V22 V04 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB23 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB24 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB26 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB27 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB28 IN (16)={V16 V00 V179 V22 V04 V05 V13 V06 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(17)={V16 V00 V179 V22 V04 V05 V13 V06 V12 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB29 IN (17)={V16 V00 V179 V22 V04 V05 V13 V06 V12 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB30 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB31 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V18 V171 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB32 IN (21)={V16 V00 V179 V18 V171 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB34 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB35 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB36 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB38 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB39 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB40 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB41 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V22 V04 V05 V174 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB42 IN (20)={V16 V00 V179 V22 V04 V05 V174 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB43 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB44 IN (18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB45 IN (18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB46 IN (18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB47 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB48 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB49 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB50 IN (17)={V00 V179 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(17)={V00 V179 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB51 IN (16)={V00 V179 V04 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(17)={V00 V179 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB52 IN (17)={V00 V179 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(17)={V00 V179 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB53 IN (17)={V00 V179 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(16)={V00 V179 V04 V05 V13 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB54 IN (16)={V00 V179 V04 V05 V13 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(16)={V00 V179 V04 V05 V13 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB55 IN (15)={V00 V179 V04 V05 V13 V06 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(16)={V00 V179 V04 V05 V13 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB56 IN (16)={V00 V179 V04 V05 V13 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(16)={V00 V179 V04 V05 V13 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB57 IN (16)={V00 V179 V04 V05 V13 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(15)={V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB58 IN (15)={V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02 } + ByrefExposed + GcHeap OUT(16)={V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02 V70} + ByrefExposed + GcHeap BB59 IN (15)={V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02 } + ByrefExposed + GcHeap OUT(16)={V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02 V70} + ByrefExposed + GcHeap BB60 IN (16)={V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02 V70} + ByrefExposed + GcHeap OUT(15)={V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02 } + ByrefExposed + GcHeap BB61 IN (15)={ V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(16)={V16 V00 V179 V04 V05 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap BB62 IN (9)={V16 V00 V179 V11 V03 V01 V17 V180 V02} + ByrefExposed + GcHeap OUT(9)={ V00 V179 V11 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap BB63 IN (13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap OUT(13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap BB64 IN (13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap OUT(13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap BB65 IN (13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap OUT(13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap BB66 IN (13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap OUT(13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap BB73 IN (13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap OUT(15)={V00 V179 V04 V05 V08 V14 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap BB74 IN (13)={V00 V179 V04 V05 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap OUT(15)={V00 V179 V04 V05 V08 V14 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap BB78 IN (15)={ V00 V179 V04 V05 V08 V14 V06 V12 V09 V03 V01 V07 V15 V17 V180} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180} + ByrefExposed + GcHeap BB79 IN (19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 } + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V26 V29} + ByrefExposed + GcHeap BB81 IN (22)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 V27 V26 V29} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V26 V29} + ByrefExposed + GcHeap BB82 IN (23)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V26 V29 } + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V64} + ByrefExposed + GcHeap BB83 IN (25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V64 } + ByrefExposed + GcHeap OUT(26)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V65 V66} + ByrefExposed + GcHeap BB84 IN (25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V64 } + ByrefExposed + GcHeap OUT(26)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V65 V66} + ByrefExposed + GcHeap BB85 IN (26)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V65 V66} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32 } + ByrefExposed + GcHeap BB89 IN (25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB90 IN (25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB91 IN (25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32 } + ByrefExposed + GcHeap OUT(27)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V33 V26 V29 V32 V161} + ByrefExposed + GcHeap BB95 IN (27)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V33 V26 V29 V32 V161} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32 } + ByrefExposed + GcHeap BB100 IN (25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB101 IN (24)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V26 V29 V32} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB102 IN (25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V28 V17 V180 V27 V30 V26 V29 V32} + ByrefExposed + GcHeap BB103 IN (19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180} + ByrefExposed + GcHeap BB104 IN (19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180} + ByrefExposed + GcHeap BB106 IN (19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 } + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 V86} + ByrefExposed + GcHeap BB107 IN (20)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 V86 } + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 V86 V87} + ByrefExposed + GcHeap BB108 IN (21)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 V86 V87} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 } + ByrefExposed + GcHeap BB112 IN (19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 } + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB245 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB246 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB247 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB248 IN (4)={V00 V03 V01 V15} + ByrefExposed + GcHeap OUT(3)={V00 V03 V01 } + ByrefExposed + GcHeap BB249 IN (3)={V00 V03 V01} + ByrefExposed + GcHeap OUT(2)={V00 V03 } + ByrefExposed + GcHeap BB251 IN (2)={V00 V03} + ByrefExposed + GcHeap OUT(0)={ } BB253 IN (0)={} OUT(0)={} BB111 IN (20)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 V86} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V04 V20 V05 V08 V14 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V180 } + ByrefExposed + GcHeap BB113 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB114 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB115 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB117 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB118 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V177 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB119 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V63 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB120 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V177 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V63 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB121 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V63 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V92 V08 V14 V91 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB122 IN (24)={V16 V00 V179 V18 V04 V20 V34 V05 V92 V08 V14 V91 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB123 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V92 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB124 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB125 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB127 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V95 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB129 IN (23)={V16 V00 V179 V18 V04 V95 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V18 V04 V95 V20 V34 V05 V08 V14 V96 V36 V06 V12 V144 V09 V03 V181 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB130 IN (25)={V16 V00 V179 V18 V04 V95 V20 V34 V05 V08 V14 V96 V36 V06 V12 V144 V09 V03 V181 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB132 IN (23)={V16 V00 V179 V18 V04 V95 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB133 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB134 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB135 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB136 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB137 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V184 V21} + ByrefExposed + GcHeap BB257 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V184 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB138 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V185 V21} + ByrefExposed + GcHeap BB258 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V185 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB139 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB140 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB141 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB142 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB143 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB144 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V110 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB145 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB146 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB147 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V58 V21} + ByrefExposed + GcHeap BB148 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V58 V21} + ByrefExposed + GcHeap BB149 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V58 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB150 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB151 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB152 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V57 V21} + ByrefExposed + GcHeap BB153 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V57 V21} + ByrefExposed + GcHeap BB154 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V57 V21} + ByrefExposed + GcHeap BB155 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V57 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB156 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB157 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V99 V21} + ByrefExposed + GcHeap BB158 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V99 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB159 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB160 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB161 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB163 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V102 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB165 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V102 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V102 V01 V07 V143 V15 V17 V103 V21} + ByrefExposed + GcHeap BB166 IN (23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V102 V01 V07 V143 V15 V17 V103 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB168 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V102 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB169 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB170 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB171 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB172 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB173 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB174 IN (20)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V106 V01 V07 V143 V15 V17} + ByrefExposed + GcHeap BB176 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V106 V01 V07 V143 V15 V17 } + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V106 V01 V07 V143 V15 V17 V107} + ByrefExposed + GcHeap BB177 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V106 V01 V07 V143 V15 V17 V107} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 } + ByrefExposed + GcHeap BB179 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V106 V01 V07 V143 V15 V17} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17} + ByrefExposed + GcHeap BB180 IN (20)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 } + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB181 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V110 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V110 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB182 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V110 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V110 V01 V07 V143 V15 V17 V111 V21} + ByrefExposed + GcHeap BB183 IN (23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V110 V01 V07 V143 V15 V17 V111 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB185 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V110 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB186 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V114 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB187 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V114 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V114 V01 V07 V143 V15 V17 V115 V21} + ByrefExposed + GcHeap BB188 IN (23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V114 V01 V07 V143 V15 V17 V115 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB190 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V114 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB191 IN (23)={V16 V00 V179 V18 V04 V20 V34 V172 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V119 V08 V14 V118 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB192 IN (24)={V16 V00 V179 V18 V04 V20 V34 V05 V119 V08 V14 V118 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB193 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V119 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB194 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB195 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V172 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB196 IN (23)={V16 V00 V179 V18 V04 V20 V34 V172 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V172 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB197 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB198 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB199 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB200 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V176 V21} + ByrefExposed + GcHeap BB201 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V176 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V123 V122 V21} + ByrefExposed + GcHeap BB203 IN (23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V123 V122 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB204 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V123 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB205 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB206 IN (24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB207 IN (24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB208 IN (24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB209 IN (24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(25)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V176 V37 V21} + ByrefExposed + GcHeap BB210 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB213 IN (25)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V176 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB214 IN (24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB215 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V126 V21} + ByrefExposed + GcHeap BB216 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V126 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB218 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB219 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB220 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB221 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB222 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB223 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap BB224 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V55 V21} + ByrefExposed + GcHeap BB225 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V21} + ByrefExposed + GcHeap OUT(24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V55 V21} + ByrefExposed + GcHeap BB226 IN (24)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V03 V38 V01 V07 V143 V15 V17 V37 V55 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB227 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V129 V21} + ByrefExposed + GcHeap BB228 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V129 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB229 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB230 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB231 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V175 V21} + ByrefExposed + GcHeap BB232 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V175 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V175 V21} + ByrefExposed + GcHeap BB233 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V175 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V133 V132 V21} + ByrefExposed + GcHeap BB234 IN (23)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V133 V132 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB235 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V133 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB236 IN (22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V173 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V04 V20 V34 V05 V137 V08 V14 V136 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB237 IN (23)={V16 V00 V179 V04 V20 V34 V05 V137 V08 V14 V136 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB238 IN (22)={V16 V00 V179 V04 V20 V34 V05 V137 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB239 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB240 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(22)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V173 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB241 IN (21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB242 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V140 V21} + ByrefExposed + GcHeap BB243 IN (23)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V140 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB244 IN (22)={V16 V00 V179 V18 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V04 V20 V34 V05 V08 V14 V36 V06 V12 V144 V09 V03 V01 V07 V143 V15 V17 V21} + ByrefExposed + GcHeap BB110 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB254 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} Removing dead node: N001 ( 0, 0) [003727] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003729] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003731] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003776] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003775] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003779] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003778] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003773] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003772] ----------- * NOP void Removing dead local store: N003 ( 1, 3) [001558] DA--------- * STORE_LCL_VAR int V152 tmp112 d:1 (last use) Removing dead node: N001 ( 1, 2) [001556] ----------- * CNS_INT int 4 $c8 Removing dead node: N001 ( 0, 0) [003733] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003770] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003769] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003735] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003737] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003765] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003767] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003739] ----------- * NOP void Removing dead local store: N003 ( 1, 3) [000836] DA--------- * STORE_LCL_VAR byref V60 tmp20 d:1 (last use) Removing dead LclVar use: N001 ( 1, 1) [000829] ----------- * LCL_VAR byref V00 arg0 u:1 $100 Removing dead local store: N003 ( 1, 3) [000914] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:3 (last use) Removing dead LclVar use: N001 ( 1, 1) [000838] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 Removing dead local store: N003 ( 1, 3) [000852] DA--------- * STORE_LCL_VAR byref V62 tmp22 d:2 (last use) Removing dead LclVar use: N001 ( 1, 1) [000839] ----------- * LCL_VAR byref V00 arg0 u:1 (last use) $100 Removing dead node: N001 ( 0, 0) [003741] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003743] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003745] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003747] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003749] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003751] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003753] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003755] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003757] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003759] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003761] ----------- * NOP void Removing dead node: N001 ( 0, 0) [003763] ----------- * NOP void *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..061)-> BB10 ( cond ) i bwd LIR BB255 [0364] 1 BB09 8 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31 (switch) i bwd LIR BB10 [0009] 1 BB09 8 1 [083..083)-> BB11 ( cond ) i bwd LIR BB256 [0365] 1 BB10 8 [083..0A1)-> BB23,BB47,BB21,BB47,BB18 (switch) i bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB255 8 1 [0CF..0D8)-> BB47 (always) i bwd LIR BB18 [0017] 1 BB256 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd LIR BB21 [0020] 1 BB256 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB256 8 1 [0FB..102)-> BB47 ( cond ) i bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd LIR BB30 [0029] 1 BB255 8 1 [12C..137)-> BB47 (always) i bwd LIR BB31 [0031] 3 BB32,BB255(2) 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd LIR BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd LIR BB47 [0047] 24 BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB255(2),BB256(2) 64 1 [204..20F)-> BB50 ( cond ) i bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd LIR BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i LIR BB245 [0190] 25 BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB258 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd LIR BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd LIR BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src LIR BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd LIR BB137 [0117] 1 BB136 2 3 [478..478)-> BB138 ( cond ) i bwd LIR BB257 [0366] 1 BB137 2 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194 (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..49A)-> BB139 ( cond ) i bwd LIR BB258 [0367] 1 BB138 2 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145 (switch) i bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB257,BB258 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd LIR BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd LIR BB171 [0143] 1 BB258 2 3 [564..571)-> BB245 ( cond ) i bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd LIR BB186 [0149] 1 BB257 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd LIR BB194 [0151] 4 BB192,BB193,BB257(2) 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src LIR BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB140,BB143,BB257(2),BB258(2) 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd LIR BB254 [0363] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgRemoveDeadBlocks() New BlockSet epoch 5, # of blocks (including unused BB00): 259, bitset array size: 5 (long) Removing unreachable blocks for fgRemoveDeadBlocks iteration #1 *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V01: refCnt = 1, refCntWtd = 1 New refCnts for V11: refCnt = 1, refCntWtd = 1 New refCnts for V01: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 1, refCntWtd = 2 New refCnts for V76: refCnt = 2, refCntWtd = 4 New refCnts for V76: refCnt = 3, refCntWtd = 6 New refCnts for V167: refCnt = 1, refCntWtd = 2 New refCnts for V167: refCnt = 2, refCntWtd = 4 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V180: refCnt = 1, refCntWtd = 1 New refCnts for V180: refCnt = 2, refCntWtd = 2 New refCnts for V147: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V179: refCnt = 1, refCntWtd = 1 New refCnts for V179: refCnt = 2, refCntWtd = 2 New refCnts for V148: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 2 New refCnts for V147: refCnt = 2, refCntWtd = 1.50 New refCnts for V155: refCnt = 1, refCntWtd = 0.50 New refCnts for V148: refCnt = 2, refCntWtd = 1.50 New refCnts for V156: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 3, refCntWtd = 2.50 New refCnts for V155: refCnt = 2, refCntWtd = 1 New refCnts for V149: refCnt = 1, refCntWtd = 0.50 New refCnts for V156: refCnt = 2, refCntWtd = 1 New refCnts for V150: refCnt = 1, refCntWtd = 0.50 New refCnts for V43: refCnt = 1, refCntWtd = 0.50 New refCnts for V155: refCnt = 3, refCntWtd = 1.50 New refCnts for V149: refCnt = 2, refCntWtd = 1 New refCnts for V156: refCnt = 3, refCntWtd = 1.50 New refCnts for V150: refCnt = 2, refCntWtd = 1 New refCnts for V43: refCnt = 2, refCntWtd = 1 New refCnts for V147: refCnt = 3, refCntWtd = 2 New refCnts for V149: refCnt = 3, refCntWtd = 1.50 New refCnts for V148: refCnt = 3, refCntWtd = 2 New refCnts for V150: refCnt = 3, refCntWtd = 1.50 New refCnts for V43: refCnt = 3, refCntWtd = 1.50 New refCnts for V149: refCnt = 4, refCntWtd = 2.50 New refCnts for V150: refCnt = 4, refCntWtd = 2.50 New refCnts for V43: refCnt = 4, refCntWtd = 2.50 New refCnts for V15: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 1, refCntWtd = 8 New refCnts for V05: refCnt = 1, refCntWtd = 8 New refCnts for V06: refCnt = 1, refCntWtd = 8 New refCnts for V07: refCnt = 1, refCntWtd = 8 New refCnts for V09: refCnt = 1, refCntWtd = 8 New refCnts for V10: refCnt = 1, refCntWtd = 8 New refCnts for V12: refCnt = 1, refCntWtd = 8 New refCnts for V13: refCnt = 1, refCntWtd = 8 New refCnts for V15: refCnt = 2, refCntWtd = 9 New refCnts for V16: refCnt = 1, refCntWtd = 8 New refCnts for V180: refCnt = 3, refCntWtd = 10 New refCnts for V157: refCnt = 1, refCntWtd = 8 New refCnts for V157: refCnt = 2, refCntWtd = 16 New refCnts for V23: refCnt = 1, refCntWtd = 8 New refCnts for V157: refCnt = 3, refCntWtd = 24 New refCnts for V168: refCnt = 1, refCntWtd = 16 New refCnts for V168: refCnt = 2, refCntWtd = 32 New refCnts for V22: refCnt = 1, refCntWtd = 8 New refCnts for V18: refCnt = 1, refCntWtd = 8 New refCnts for V18: refCnt = 2, refCntWtd = 16 New refCnts for V182: refCnt = 1, refCntWtd = 16 New refCnts for V182: refCnt = 2, refCntWtd = 32 New refCnts for V182: refCnt = 3, refCntWtd = 48 New refCnts for V18: refCnt = 3, refCntWtd = 24 New refCnts for V183: refCnt = 1, refCntWtd = 16 New refCnts for V183: refCnt = 2, refCntWtd = 32 New refCnts for V183: refCnt = 3, refCntWtd = 48 New refCnts for V18: refCnt = 4, refCntWtd = 32 New refCnts for V18: refCnt = 5, refCntWtd = 40 New refCnts for V18: refCnt = 6, refCntWtd = 48 New refCnts for V18: refCnt = 7, refCntWtd = 56 New refCnts for V13: refCnt = 2, refCntWtd = 16 New refCnts for V13: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 3, refCntWtd = 24 New refCnts for V06: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 4, refCntWtd = 32 New refCnts for V06: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 5, refCntWtd = 40 New refCnts for V04: refCnt = 6, refCntWtd = 48 New refCnts for V04: refCnt = 7, refCntWtd = 56 New refCnts for V07: refCnt = 2, refCntWtd = 16 New refCnts for V05: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 8, refCntWtd = 64 New refCnts for V05: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 9, refCntWtd = 72 New refCnts for V05: refCnt = 4, refCntWtd = 32 New refCnts for V10: refCnt = 2, refCntWtd = 16 New refCnts for V10: refCnt = 3, refCntWtd = 24 New refCnts for V04: refCnt = 10, refCntWtd = 80 New refCnts for V11: refCnt = 2, refCntWtd = 9 New refCnts for V11: refCnt = 3, refCntWtd = 17 New refCnts for V12: refCnt = 2, refCntWtd = 16 New refCnts for V04: refCnt = 11, refCntWtd = 88 New refCnts for V10: refCnt = 4, refCntWtd = 32 New refCnts for V11: refCnt = 4, refCntWtd = 25 New refCnts for V13: refCnt = 4, refCntWtd = 32 New refCnts for V13: refCnt = 5, refCntWtd = 40 New refCnts for V16: refCnt = 2, refCntWtd = 72 New refCnts for V179: refCnt = 3, refCntWtd = 66 New refCnts for V22: refCnt = 2, refCntWtd = 72 New refCnts for V16: refCnt = 3, refCntWtd = 136 New refCnts for V171: refCnt = 1, refCntWtd = 64 New refCnts for V171: refCnt = 2, refCntWtd = 128 New refCnts for V16: refCnt = 4, refCntWtd = 200 New refCnts for V74: refCnt = 1, refCntWtd = 128 New refCnts for V74: refCnt = 2, refCntWtd = 256 New refCnts for V16: refCnt = 5, refCntWtd = 264 New refCnts for V171: refCnt = 3, refCntWtd = 192 New refCnts for V18: refCnt = 8, refCntWtd = 120 New refCnts for V16: refCnt = 6, refCntWtd = 272 New refCnts for V179: refCnt = 4, refCntWtd = 74 New refCnts for V22: refCnt = 3, refCntWtd = 80 New refCnts for V16: refCnt = 7, refCntWtd = 280 New refCnts for V174: refCnt = 1, refCntWtd = 8 New refCnts for V174: refCnt = 2, refCntWtd = 16 New refCnts for V16: refCnt = 8, refCntWtd = 288 New refCnts for V16: refCnt = 9, refCntWtd = 296 New refCnts for V16: refCnt = 10, refCntWtd = 304 New refCnts for V179: refCnt = 5, refCntWtd = 82 New refCnts for V22: refCnt = 4, refCntWtd = 88 New refCnts for V16: refCnt = 11, refCntWtd = 312 New refCnts for V174: refCnt = 3, refCntWtd = 24 New refCnts for V174: refCnt = 4, refCntWtd = 32 New refCnts for V16: refCnt = 12, refCntWtd = 320 New refCnts for V179: refCnt = 6, refCntWtd = 90 New refCnts for V22: refCnt = 5, refCntWtd = 96 New refCnts for V16: refCnt = 13, refCntWtd = 328 New refCnts for V174: refCnt = 5, refCntWtd = 40 New refCnts for V174: refCnt = 6, refCntWtd = 48 New refCnts for V174: refCnt = 7, refCntWtd = 56 New refCnts for V22: refCnt = 6, refCntWtd = 104 New refCnts for V16: refCnt = 14, refCntWtd = 336 New refCnts for V16: refCnt = 15, refCntWtd = 400 New refCnts for V73: refCnt = 1, refCntWtd = 128 New refCnts for V73: refCnt = 2, refCntWtd = 256 New refCnts for V16: refCnt = 16, refCntWtd = 464 New refCnts for V16: refCnt = 17, refCntWtd = 528 New refCnts for V179: refCnt = 7, refCntWtd = 154 New refCnts for V22: refCnt = 7, refCntWtd = 168 New refCnts for V16: refCnt = 18, refCntWtd = 592 New refCnts for V09: refCnt = 2, refCntWtd = 16 New refCnts for V16: refCnt = 19, refCntWtd = 656 New refCnts for V179: refCnt = 8, refCntWtd = 218 New refCnts for V16: refCnt = 20, refCntWtd = 672 New refCnts for V71: refCnt = 1, refCntWtd = 32 New refCnts for V71: refCnt = 2, refCntWtd = 64 New refCnts for V16: refCnt = 21, refCntWtd = 688 New refCnts for V22: refCnt = 8, refCntWtd = 184 New refCnts for V71: refCnt = 3, refCntWtd = 96 New refCnts for V72: refCnt = 1, refCntWtd = 32 New refCnts for V72: refCnt = 2, refCntWtd = 64 New refCnts for V18: refCnt = 9, refCntWtd = 136 New refCnts for V18: refCnt = 10, refCntWtd = 152 New refCnts for V18: refCnt = 11, refCntWtd = 168 New refCnts for V23: refCnt = 2, refCntWtd = 16 New refCnts for V05: refCnt = 5, refCntWtd = 40 New refCnts for V04: refCnt = 12, refCntWtd = 90 New refCnts for V05: refCnt = 6, refCntWtd = 42 New refCnts for V10: refCnt = 5, refCntWtd = 40 New refCnts for V10: refCnt = 6, refCntWtd = 42 New refCnts for V05: refCnt = 7, refCntWtd = 44 New refCnts for V13: refCnt = 6, refCntWtd = 42 New refCnts for V11: refCnt = 5, refCntWtd = 27 New refCnts for V13: refCnt = 7, refCntWtd = 44 New refCnts for V12: refCnt = 3, refCntWtd = 18 New refCnts for V17: refCnt = 3, refCntWtd = 10 New refCnts for V01: refCnt = 4, refCntWtd = 6.50 New refCnts for V69: refCnt = 1, refCntWtd = 8 New refCnts for V69: refCnt = 2, refCntWtd = 16 New refCnts for V13: refCnt = 8, refCntWtd = 48 New refCnts for V69: refCnt = 3, refCntWtd = 24 New refCnts for V09: refCnt = 3, refCntWtd = 20 New refCnts for V01: refCnt = 5, refCntWtd = 8.50 New refCnts for V04: refCnt = 13, refCntWtd = 92 New refCnts for V05: refCnt = 8, refCntWtd = 46 New refCnts for V70: refCnt = 1, refCntWtd = 2 New refCnts for V04: refCnt = 14, refCntWtd = 94 New refCnts for V70: refCnt = 2, refCntWtd = 4 New refCnts for V70: refCnt = 3, refCntWtd = 8 New refCnts for V01: refCnt = 6, refCntWtd = 12.50 New refCnts for V17: refCnt = 4, refCntWtd = 14 New refCnts for V180: refCnt = 4, refCntWtd = 14 New refCnts for V02: refCnt = 3, refCntWtd = 6 New refCnts for V16: refCnt = 22, refCntWtd = 692 New refCnts for V16: refCnt = 23, refCntWtd = 696 New refCnts for V15: refCnt = 3, refCntWtd = 13 New refCnts for V16: refCnt = 24, refCntWtd = 700 New refCnts for V15: refCnt = 4, refCntWtd = 17 New refCnts for V01: refCnt = 7, refCntWtd = 13 New refCnts for V01: refCnt = 8, refCntWtd = 13.50 New refCnts for V01: refCnt = 9, refCntWtd = 14 New refCnts for V06: refCnt = 4, refCntWtd = 25 New refCnts for V05: refCnt = 9, refCntWtd = 47 New refCnts for V05: refCnt = 10, refCntWtd = 48 New refCnts for V06: refCnt = 5, refCntWtd = 26 New refCnts for V44: refCnt = 1, refCntWtd = 1 New refCnts for V44: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 6, refCntWtd = 27 New refCnts for V07: refCnt = 3, refCntWtd = 17 New refCnts for V05: refCnt = 11, refCntWtd = 49 New refCnts for V05: refCnt = 12, refCntWtd = 50 New refCnts for V07: refCnt = 4, refCntWtd = 18 New refCnts for V45: refCnt = 1, refCntWtd = 1 New refCnts for V45: refCnt = 2, refCntWtd = 2 New refCnts for V07: refCnt = 5, refCntWtd = 19 New refCnts for V09: refCnt = 4, refCntWtd = 21 New refCnts for V05: refCnt = 13, refCntWtd = 50.50 New refCnts for V08: refCnt = 1, refCntWtd = 0.50 New refCnts for V14: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 10, refCntWtd = 14.50 New refCnts for V178: refCnt = 1, refCntWtd = 0.50 New refCnts for V178: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 14, refCntWtd = 51 New refCnts for V178: refCnt = 3, refCntWtd = 1.50 New refCnts for V05: refCnt = 15, refCntWtd = 51.50 New refCnts for V46: refCnt = 1, refCntWtd = 0.50 New refCnts for V46: refCnt = 2, refCntWtd = 1 New refCnts for V08: refCnt = 2, refCntWtd = 1 New refCnts for V178: refCnt = 4, refCntWtd = 2 New refCnts for V05: refCnt = 16, refCntWtd = 52 New refCnts for V14: refCnt = 2, refCntWtd = 1 New refCnts for V15: refCnt = 5, refCntWtd = 18 New refCnts for V16: refCnt = 25, refCntWtd = 701 New refCnts for V47: refCnt = 1, refCntWtd = 1 New refCnts for V151: refCnt = 1, refCntWtd = 1 New refCnts for V151: refCnt = 2, refCntWtd = 2 New refCnts for V143: refCnt = 1, refCntWtd = 1 New refCnts for V144: refCnt = 1, refCntWtd = 1 New refCnts for V20: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V12: refCnt = 4, refCntWtd = 19 New refCnts for V03: refCnt = 2, refCntWtd = 1.50 New refCnts for V26: refCnt = 1, refCntWtd = 0.50 New refCnts for V27: refCnt = 1, refCntWtd = 0.50 New refCnts for V28: refCnt = 1, refCntWtd = 0.50 New refCnts for V26: refCnt = 2, refCntWtd = 1 New refCnts for V29: refCnt = 1, refCntWtd = 0.50 New refCnts for V29: refCnt = 2, refCntWtd = 1 New refCnts for V26: refCnt = 3, refCntWtd = 1.50 New refCnts for V28: refCnt = 2, refCntWtd = 1 New refCnts for V28: refCnt = 3, refCntWtd = 1.50 New refCnts for V30: refCnt = 1, refCntWtd = 0.50 New refCnts for V08: refCnt = 3, refCntWtd = 1.50 New refCnts for V64: refCnt = 1, refCntWtd = 0.50 New refCnts for V14: refCnt = 3, refCntWtd = 1.50 New refCnts for V64: refCnt = 2, refCntWtd = 1 New refCnts for V65: refCnt = 1, refCntWtd = 0.50 New refCnts for V66: refCnt = 1, refCntWtd = 0.50 New refCnts for V64: refCnt = 3, refCntWtd = 1.50 New refCnts for V65: refCnt = 2, refCntWtd = 1 New refCnts for V14: refCnt = 4, refCntWtd = 2 New refCnts for V66: refCnt = 2, refCntWtd = 1 New refCnts for V65: refCnt = 3, refCntWtd = 1.50 New refCnts for V66: refCnt = 3, refCntWtd = 1.50 New refCnts for V31: refCnt = 1, refCntWtd = 0.50 New refCnts for V06: refCnt = 7, refCntWtd = 27.50 New refCnts for V31: refCnt = 2, refCntWtd = 1 New refCnts for V06: refCnt = 8, refCntWtd = 28 New refCnts for V31: refCnt = 3, refCntWtd = 1.50 New refCnts for V67: refCnt = 1, refCntWtd = 0.50 New refCnts for V67: refCnt = 2, refCntWtd = 1 New refCnts for V32: refCnt = 1, refCntWtd = 0.50 New refCnts for V32: refCnt = 2, refCntWtd = 1 New refCnts for V30: refCnt = 2, refCntWtd = 1 New refCnts for V30: refCnt = 3, refCntWtd = 5 New refCnts for V20: refCnt = 2, refCntWtd = 5 New refCnts for V20: refCnt = 3, refCntWtd = 9 New refCnts for V20: refCnt = 4, refCntWtd = 13 New refCnts for V144: refCnt = 2, refCntWtd = 5 New refCnts for V144: refCnt = 3, refCntWtd = 7 New refCnts for V33: refCnt = 1, refCntWtd = 2 New refCnts for V33: refCnt = 2, refCntWtd = 4 New refCnts for V159: refCnt = 1, refCntWtd = 2 New refCnts for V33: refCnt = 3, refCntWtd = 6 New refCnts for V160: refCnt = 1, refCntWtd = 2 New refCnts for V159: refCnt = 2, refCntWtd = 4 New refCnts for V161: refCnt = 1, refCntWtd = 2 New refCnts for V144: refCnt = 4, refCntWtd = 9 New refCnts for V160: refCnt = 2, refCntWtd = 4 New refCnts for V144: refCnt = 5, refCntWtd = 11 New refCnts for V83: refCnt = 1, refCntWtd = 4 New refCnts for V83: refCnt = 2, refCntWtd = 8 New refCnts for V161: refCnt = 2, refCntWtd = 4 New refCnts for V143: refCnt = 2, refCntWtd = 3 New refCnts for V33: refCnt = 4, refCntWtd = 8 New refCnts for V163: refCnt = 1, refCntWtd = 2 New refCnts for V33: refCnt = 5, refCntWtd = 10 New refCnts for V164: refCnt = 1, refCntWtd = 2 New refCnts for V163: refCnt = 2, refCntWtd = 4 New refCnts for V143: refCnt = 3, refCntWtd = 5 New refCnts for V164: refCnt = 2, refCntWtd = 4 New refCnts for V144: refCnt = 6, refCntWtd = 13 New refCnts for V20: refCnt = 5, refCntWtd = 17 New refCnts for V144: refCnt = 7, refCntWtd = 17 New refCnts for V143: refCnt = 4, refCntWtd = 9 New refCnts for V20: refCnt = 6, refCntWtd = 21 New refCnts for V28: refCnt = 4, refCntWtd = 5.50 New refCnts for V27: refCnt = 2, refCntWtd = 4.50 New refCnts for V29: refCnt = 3, refCntWtd = 5 New refCnts for V27: refCnt = 3, refCntWtd = 6.50 New refCnts for V27: refCnt = 4, refCntWtd = 8.50 New refCnts for V27: refCnt = 5, refCntWtd = 10.50 New refCnts for V26: refCnt = 4, refCntWtd = 3.50 New refCnts for V26: refCnt = 5, refCntWtd = 5.50 New refCnts for V27: refCnt = 6, refCntWtd = 12.50 New refCnts for V30: refCnt = 4, refCntWtd = 7 New refCnts for V28: refCnt = 5, refCntWtd = 9.50 New refCnts for V30: refCnt = 5, refCntWtd = 11 New refCnts for V28: refCnt = 6, refCntWtd = 13.50 New refCnts for V32: refCnt = 3, refCntWtd = 5 New refCnts for V28: refCnt = 7, refCntWtd = 17.50 New refCnts for V01: refCnt = 11, refCntWtd = 15.50 New refCnts for V16: refCnt = 26, refCntWtd = 702 New refCnts for V01: refCnt = 12, refCntWtd = 16 New refCnts for V03: refCnt = 3, refCntWtd = 2 New refCnts for V86: refCnt = 1, refCntWtd = 1 New refCnts for V86: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 1, refCntWtd = 0.50 New refCnts for V87: refCnt = 1, refCntWtd = 0.50 New refCnts for V86: refCnt = 3, refCntWtd = 3 New refCnts for V87: refCnt = 2, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 1 New refCnts for V00: refCnt = 3, refCntWtd = 1.50 New refCnts for V88: refCnt = 1, refCntWtd = 1 New refCnts for V87: refCnt = 3, refCntWtd = 1.50 New refCnts for V88: refCnt = 2, refCntWtd = 2 New refCnts for V88: refCnt = 3, refCntWtd = 3 New refCnts for V87: refCnt = 4, refCntWtd = 2 New refCnts for V86: refCnt = 4, refCntWtd = 4 New refCnts for V87: refCnt = 5, refCntWtd = 2.50 New refCnts for V00: refCnt = 4, refCntWtd = 2 New refCnts for V21: refCnt = 1, refCntWtd = 1 New refCnts for V180: refCnt = 5, refCntWtd = 15 New refCnts for V165: refCnt = 1, refCntWtd = 1 New refCnts for V165: refCnt = 2, refCntWtd = 2 New refCnts for V35: refCnt = 1, refCntWtd = 1 New refCnts for V165: refCnt = 3, refCntWtd = 3 New refCnts for V169: refCnt = 1, refCntWtd = 2 New refCnts for V169: refCnt = 2, refCntWtd = 4 New refCnts for V34: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 5, refCntWtd = 15 New refCnts for V36: refCnt = 1, refCntWtd = 1 New refCnts for V16: refCnt = 27, refCntWtd = 710 New refCnts for V179: refCnt = 9, refCntWtd = 226 New refCnts for V16: refCnt = 28, refCntWtd = 714 New refCnts for V49: refCnt = 1, refCntWtd = 8 New refCnts for V49: refCnt = 2, refCntWtd = 16 New refCnts for V16: refCnt = 29, refCntWtd = 718 New refCnts for V34: refCnt = 2, refCntWtd = 5 New refCnts for V49: refCnt = 3, refCntWtd = 24 New refCnts for V50: refCnt = 1, refCntWtd = 8 New refCnts for V50: refCnt = 2, refCntWtd = 16 New refCnts for V18: refCnt = 12, refCntWtd = 172 New refCnts for V18: refCnt = 13, refCntWtd = 176 New refCnts for V18: refCnt = 14, refCntWtd = 180 New refCnts for V35: refCnt = 2, refCntWtd = 2 New refCnts for V01: refCnt = 13, refCntWtd = 17 New refCnts for V15: refCnt = 6, refCntWtd = 19 New refCnts for V01: refCnt = 14, refCntWtd = 17.50 New refCnts for V00: refCnt = 5, refCntWtd = 2.50 New refCnts for V03: refCnt = 4, refCntWtd = 2.50 New refCnts for V00: refCnt = 6, refCntWtd = 3 New refCnts for V00: refCnt = 7, refCntWtd = 3.50 New refCnts for V86: refCnt = 5, refCntWtd = 5 New refCnts for V14: refCnt = 5, refCntWtd = 4 New refCnts for V18: refCnt = 15, refCntWtd = 182 New refCnts for V18: refCnt = 16, refCntWtd = 184 New refCnts for V18: refCnt = 17, refCntWtd = 186 New refCnts for V36: refCnt = 2, refCntWtd = 9 New refCnts for V177: refCnt = 1, refCntWtd = 8 New refCnts for V177: refCnt = 2, refCntWtd = 16 New refCnts for V63: refCnt = 1, refCntWtd = 8 New refCnts for V36: refCnt = 3, refCntWtd = 17 New refCnts for V61: refCnt = 1, refCntWtd = 16 New refCnts for V61: refCnt = 2, refCntWtd = 32 New refCnts for V36: refCnt = 4, refCntWtd = 25 New refCnts for V177: refCnt = 3, refCntWtd = 24 New refCnts for V63: refCnt = 2, refCntWtd = 16 New refCnts for V63: refCnt = 3, refCntWtd = 24 New refCnts for V92: refCnt = 1, refCntWtd = 16 New refCnts for V00: refCnt = 8, refCntWtd = 11.50 New refCnts for V91: refCnt = 1, refCntWtd = 8 New refCnts for V91: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 9, refCntWtd = 19.50 New refCnts for V00: refCnt = 10, refCntWtd = 27.50 New refCnts for V93: refCnt = 1, refCntWtd = 16 New refCnts for V91: refCnt = 3, refCntWtd = 24 New refCnts for V93: refCnt = 2, refCntWtd = 32 New refCnts for V93: refCnt = 3, refCntWtd = 48 New refCnts for V91: refCnt = 4, refCntWtd = 32 New refCnts for V92: refCnt = 2, refCntWtd = 32 New refCnts for V91: refCnt = 5, refCntWtd = 40 New refCnts for V00: refCnt = 11, refCntWtd = 35.50 New refCnts for V00: refCnt = 12, refCntWtd = 43.50 New refCnts for V92: refCnt = 3, refCntWtd = 48 New refCnts for V12: refCnt = 5, refCntWtd = 27 New refCnts for V08: refCnt = 4, refCntWtd = 9.50 New refCnts for V20: refCnt = 7, refCntWtd = 29 New refCnts for V144: refCnt = 8, refCntWtd = 25 New refCnts for V143: refCnt = 5, refCntWtd = 17 New refCnts for V20: refCnt = 8, refCntWtd = 37 New refCnts for V08: refCnt = 5, refCntWtd = 17.50 New refCnts for V20: refCnt = 9, refCntWtd = 45 New refCnts for V03: refCnt = 5, refCntWtd = 10.50 New refCnts for V95: refCnt = 1, refCntWtd = 16 New refCnts for V95: refCnt = 2, refCntWtd = 32 New refCnts for V00: refCnt = 13, refCntWtd = 51.50 New refCnts for V96: refCnt = 1, refCntWtd = 8 New refCnts for V95: refCnt = 3, refCntWtd = 48 New refCnts for V181: refCnt = 1, refCntWtd = 8 New refCnts for V181: refCnt = 2, refCntWtd = 16 New refCnts for V96: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 14, refCntWtd = 59.50 New refCnts for V00: refCnt = 15, refCntWtd = 67.50 New refCnts for V97: refCnt = 1, refCntWtd = 16 New refCnts for V96: refCnt = 3, refCntWtd = 24 New refCnts for V97: refCnt = 2, refCntWtd = 32 New refCnts for V97: refCnt = 3, refCntWtd = 48 New refCnts for V96: refCnt = 4, refCntWtd = 32 New refCnts for V181: refCnt = 3, refCntWtd = 24 New refCnts for V95: refCnt = 4, refCntWtd = 64 New refCnts for V96: refCnt = 5, refCntWtd = 40 New refCnts for V00: refCnt = 16, refCntWtd = 75.50 New refCnts for V00: refCnt = 17, refCntWtd = 83.50 New refCnts for V95: refCnt = 5, refCntWtd = 80 New refCnts for V20: refCnt = 10, refCntWtd = 53 New refCnts for V20: refCnt = 11, refCntWtd = 61 New refCnts for V08: refCnt = 6, refCntWtd = 25.50 New refCnts for V08: refCnt = 7, refCntWtd = 33.50 New refCnts for V14: refCnt = 6, refCntWtd = 12 New refCnts for V14: refCnt = 7, refCntWtd = 20 New refCnts for V14: refCnt = 8, refCntWtd = 36 New refCnts for V18: refCnt = 18, refCntWtd = 188 New refCnts for V18: refCnt = 19, refCntWtd = 190 New refCnts for V184: refCnt = 1, refCntWtd = 4 New refCnts for V184: refCnt = 2, refCntWtd = 8 New refCnts for V184: refCnt = 3, refCntWtd = 12 New refCnts for V18: refCnt = 20, refCntWtd = 192 New refCnts for V185: refCnt = 1, refCntWtd = 4 New refCnts for V185: refCnt = 2, refCntWtd = 8 New refCnts for V185: refCnt = 3, refCntWtd = 12 New refCnts for V18: refCnt = 21, refCntWtd = 194 New refCnts for V18: refCnt = 22, refCntWtd = 196 New refCnts for V18: refCnt = 23, refCntWtd = 198 New refCnts for V18: refCnt = 24, refCntWtd = 200 New refCnts for V03: refCnt = 6, refCntWtd = 12.50 New refCnts for V110: refCnt = 1, refCntWtd = 4 New refCnts for V14: refCnt = 9, refCntWtd = 38 New refCnts for V14: refCnt = 10, refCntWtd = 40 New refCnts for V14: refCnt = 11, refCntWtd = 42 New refCnts for V08: refCnt = 8, refCntWtd = 35.50 New refCnts for V06: refCnt = 9, refCntWtd = 30 New refCnts for V58: refCnt = 1, refCntWtd = 2 New refCnts for V58: refCnt = 2, refCntWtd = 4 New refCnts for V58: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 25, refCntWtd = 202 New refCnts for V36: refCnt = 5, refCntWtd = 27 New refCnts for V08: refCnt = 9, refCntWtd = 37.50 New refCnts for V07: refCnt = 6, refCntWtd = 21 New refCnts for V57: refCnt = 1, refCntWtd = 2 New refCnts for V57: refCnt = 2, refCntWtd = 4 New refCnts for V36: refCnt = 6, refCntWtd = 29 New refCnts for V56: refCnt = 1, refCntWtd = 4 New refCnts for V56: refCnt = 2, refCntWtd = 8 New refCnts for V36: refCnt = 7, refCntWtd = 31 New refCnts for V56: refCnt = 3, refCntWtd = 12 New refCnts for V57: refCnt = 3, refCntWtd = 6 New refCnts for V57: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 26, refCntWtd = 204 New refCnts for V18: refCnt = 27, refCntWtd = 206 New refCnts for V00: refCnt = 18, refCntWtd = 85.50 New refCnts for V99: refCnt = 1, refCntWtd = 2 New refCnts for V99: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 19, refCntWtd = 87.50 New refCnts for V00: refCnt = 20, refCntWtd = 89.50 New refCnts for V100: refCnt = 1, refCntWtd = 4 New refCnts for V99: refCnt = 3, refCntWtd = 6 New refCnts for V100: refCnt = 2, refCntWtd = 8 New refCnts for V100: refCnt = 3, refCntWtd = 12 New refCnts for V99: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 28, refCntWtd = 208 New refCnts for V99: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 21, refCntWtd = 91.50 New refCnts for V00: refCnt = 22, refCntWtd = 93.50 New refCnts for V18: refCnt = 29, refCntWtd = 210 New refCnts for V12: refCnt = 6, refCntWtd = 29 New refCnts for V08: refCnt = 10, refCntWtd = 39.50 New refCnts for V20: refCnt = 12, refCntWtd = 63 New refCnts for V144: refCnt = 9, refCntWtd = 27 New refCnts for V143: refCnt = 6, refCntWtd = 19 New refCnts for V20: refCnt = 13, refCntWtd = 65 New refCnts for V08: refCnt = 11, refCntWtd = 41.50 New refCnts for V20: refCnt = 14, refCntWtd = 67 New refCnts for V03: refCnt = 7, refCntWtd = 14.50 New refCnts for V102: refCnt = 1, refCntWtd = 4 New refCnts for V102: refCnt = 2, refCntWtd = 8 New refCnts for V00: refCnt = 23, refCntWtd = 95.50 New refCnts for V103: refCnt = 1, refCntWtd = 2 New refCnts for V102: refCnt = 3, refCntWtd = 12 New refCnts for V103: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 24, refCntWtd = 97.50 New refCnts for V00: refCnt = 25, refCntWtd = 99.50 New refCnts for V104: refCnt = 1, refCntWtd = 4 New refCnts for V103: refCnt = 3, refCntWtd = 6 New refCnts for V104: refCnt = 2, refCntWtd = 8 New refCnts for V104: refCnt = 3, refCntWtd = 12 New refCnts for V103: refCnt = 4, refCntWtd = 8 New refCnts for V102: refCnt = 4, refCntWtd = 16 New refCnts for V102: refCnt = 5, refCntWtd = 20 New refCnts for V103: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 26, refCntWtd = 101.50 New refCnts for V00: refCnt = 27, refCntWtd = 103.50 New refCnts for V102: refCnt = 6, refCntWtd = 24 New refCnts for V20: refCnt = 15, refCntWtd = 69 New refCnts for V20: refCnt = 16, refCntWtd = 71 New refCnts for V08: refCnt = 12, refCntWtd = 43.50 New refCnts for V08: refCnt = 13, refCntWtd = 45.50 New refCnts for V08: refCnt = 14, refCntWtd = 47.50 New refCnts for V21: refCnt = 2, refCntWtd = 3 New refCnts for V07: refCnt = 7, refCntWtd = 23 New refCnts for V05: refCnt = 17, refCntWtd = 54 New refCnts for V04: refCnt = 15, refCntWtd = 96 New refCnts for V36: refCnt = 8, refCntWtd = 33 New refCnts for V03: refCnt = 8, refCntWtd = 16.50 New refCnts for V106: refCnt = 1, refCntWtd = 4 New refCnts for V106: refCnt = 2, refCntWtd = 8 New refCnts for V00: refCnt = 28, refCntWtd = 105.50 New refCnts for V107: refCnt = 1, refCntWtd = 2 New refCnts for V106: refCnt = 3, refCntWtd = 12 New refCnts for V107: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 29, refCntWtd = 107.50 New refCnts for V00: refCnt = 30, refCntWtd = 109.50 New refCnts for V108: refCnt = 1, refCntWtd = 4 New refCnts for V107: refCnt = 3, refCntWtd = 6 New refCnts for V108: refCnt = 2, refCntWtd = 8 New refCnts for V108: refCnt = 3, refCntWtd = 12 New refCnts for V107: refCnt = 4, refCntWtd = 8 New refCnts for V106: refCnt = 4, refCntWtd = 16 New refCnts for V106: refCnt = 5, refCntWtd = 20 New refCnts for V107: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 31, refCntWtd = 111.50 New refCnts for V00: refCnt = 32, refCntWtd = 113.50 New refCnts for V106: refCnt = 6, refCntWtd = 24 New refCnts for V21: refCnt = 3, refCntWtd = 5 New refCnts for V110: refCnt = 2, refCntWtd = 8 New refCnts for V00: refCnt = 33, refCntWtd = 115.50 New refCnts for V111: refCnt = 1, refCntWtd = 2 New refCnts for V110: refCnt = 3, refCntWtd = 12 New refCnts for V111: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 34, refCntWtd = 117.50 New refCnts for V00: refCnt = 35, refCntWtd = 119.50 New refCnts for V112: refCnt = 1, refCntWtd = 4 New refCnts for V111: refCnt = 3, refCntWtd = 6 New refCnts for V112: refCnt = 2, refCntWtd = 8 New refCnts for V112: refCnt = 3, refCntWtd = 12 New refCnts for V111: refCnt = 4, refCntWtd = 8 New refCnts for V110: refCnt = 4, refCntWtd = 16 New refCnts for V110: refCnt = 5, refCntWtd = 20 New refCnts for V111: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 36, refCntWtd = 121.50 New refCnts for V00: refCnt = 37, refCntWtd = 123.50 New refCnts for V110: refCnt = 6, refCntWtd = 24 New refCnts for V03: refCnt = 9, refCntWtd = 18.50 New refCnts for V114: refCnt = 1, refCntWtd = 4 New refCnts for V114: refCnt = 2, refCntWtd = 8 New refCnts for V00: refCnt = 38, refCntWtd = 125.50 New refCnts for V115: refCnt = 1, refCntWtd = 2 New refCnts for V114: refCnt = 3, refCntWtd = 12 New refCnts for V115: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 39, refCntWtd = 127.50 New refCnts for V00: refCnt = 40, refCntWtd = 129.50 New refCnts for V116: refCnt = 1, refCntWtd = 4 New refCnts for V115: refCnt = 3, refCntWtd = 6 New refCnts for V116: refCnt = 2, refCntWtd = 8 New refCnts for V116: refCnt = 3, refCntWtd = 12 New refCnts for V115: refCnt = 4, refCntWtd = 8 New refCnts for V114: refCnt = 4, refCntWtd = 16 New refCnts for V114: refCnt = 5, refCntWtd = 20 New refCnts for V115: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 41, refCntWtd = 131.50 New refCnts for V00: refCnt = 42, refCntWtd = 133.50 New refCnts for V114: refCnt = 6, refCntWtd = 24 New refCnts for V16: refCnt = 30, refCntWtd = 726 New refCnts for V59: refCnt = 1, refCntWtd = 16 New refCnts for V59: refCnt = 2, refCntWtd = 32 New refCnts for V16: refCnt = 31, refCntWtd = 734 New refCnts for V172: refCnt = 1, refCntWtd = 8 New refCnts for V119: refCnt = 1, refCntWtd = 16 New refCnts for V00: refCnt = 43, refCntWtd = 141.50 New refCnts for V118: refCnt = 1, refCntWtd = 8 New refCnts for V118: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 44, refCntWtd = 149.50 New refCnts for V00: refCnt = 45, refCntWtd = 157.50 New refCnts for V120: refCnt = 1, refCntWtd = 16 New refCnts for V118: refCnt = 3, refCntWtd = 24 New refCnts for V120: refCnt = 2, refCntWtd = 32 New refCnts for V120: refCnt = 3, refCntWtd = 48 New refCnts for V118: refCnt = 4, refCntWtd = 32 New refCnts for V119: refCnt = 2, refCntWtd = 32 New refCnts for V118: refCnt = 5, refCntWtd = 40 New refCnts for V00: refCnt = 46, refCntWtd = 165.50 New refCnts for V00: refCnt = 47, refCntWtd = 173.50 New refCnts for V119: refCnt = 3, refCntWtd = 48 New refCnts for V16: refCnt = 32, refCntWtd = 750 New refCnts for V179: refCnt = 10, refCntWtd = 242 New refCnts for V34: refCnt = 3, refCntWtd = 21 New refCnts for V16: refCnt = 33, refCntWtd = 766 New refCnts for V172: refCnt = 2, refCntWtd = 24 New refCnts for V172: refCnt = 3, refCntWtd = 40 New refCnts for V172: refCnt = 4, refCntWtd = 56 New refCnts for V18: refCnt = 30, refCntWtd = 226 New refCnts for V16: refCnt = 34, refCntWtd = 768 New refCnts for V179: refCnt = 11, refCntWtd = 244 New refCnts for V34: refCnt = 4, refCntWtd = 23 New refCnts for V16: refCnt = 35, refCntWtd = 770 New refCnts for V172: refCnt = 5, refCntWtd = 58 New refCnts for V172: refCnt = 6, refCntWtd = 60 New refCnts for V16: refCnt = 36, refCntWtd = 772 New refCnts for V16: refCnt = 37, refCntWtd = 774 New refCnts for V16: refCnt = 38, refCntWtd = 776 New refCnts for V179: refCnt = 12, refCntWtd = 246 New refCnts for V34: refCnt = 5, refCntWtd = 25 New refCnts for V16: refCnt = 39, refCntWtd = 778 New refCnts for V176: refCnt = 1, refCntWtd = 2 New refCnts for V176: refCnt = 2, refCntWtd = 4 New refCnts for V16: refCnt = 40, refCntWtd = 780 New refCnts for V51: refCnt = 1, refCntWtd = 4 New refCnts for V51: refCnt = 2, refCntWtd = 8 New refCnts for V16: refCnt = 41, refCntWtd = 782 New refCnts for V176: refCnt = 3, refCntWtd = 6 New refCnts for V123: refCnt = 1, refCntWtd = 4 New refCnts for V00: refCnt = 48, refCntWtd = 175.50 New refCnts for V122: refCnt = 1, refCntWtd = 2 New refCnts for V122: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 49, refCntWtd = 177.50 New refCnts for V00: refCnt = 50, refCntWtd = 179.50 New refCnts for V124: refCnt = 1, refCntWtd = 4 New refCnts for V122: refCnt = 3, refCntWtd = 6 New refCnts for V124: refCnt = 2, refCntWtd = 8 New refCnts for V124: refCnt = 3, refCntWtd = 12 New refCnts for V122: refCnt = 4, refCntWtd = 8 New refCnts for V123: refCnt = 2, refCntWtd = 8 New refCnts for V122: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 51, refCntWtd = 181.50 New refCnts for V00: refCnt = 52, refCntWtd = 183.50 New refCnts for V123: refCnt = 3, refCntWtd = 12 New refCnts for V37: refCnt = 1, refCntWtd = 2 New refCnts for V38: refCnt = 1, refCntWtd = 2 New refCnts for V09: refCnt = 5, refCntWtd = 23 New refCnts for V16: refCnt = 42, refCntWtd = 784 New refCnts for V179: refCnt = 13, refCntWtd = 248 New refCnts for V34: refCnt = 6, refCntWtd = 27 New refCnts for V16: refCnt = 43, refCntWtd = 786 New refCnts for V176: refCnt = 4, refCntWtd = 8 New refCnts for V176: refCnt = 5, refCntWtd = 10 New refCnts for V16: refCnt = 44, refCntWtd = 788 New refCnts for V179: refCnt = 14, refCntWtd = 250 New refCnts for V34: refCnt = 7, refCntWtd = 29 New refCnts for V16: refCnt = 45, refCntWtd = 790 New refCnts for V176: refCnt = 6, refCntWtd = 12 New refCnts for V176: refCnt = 7, refCntWtd = 14 New refCnts for V34: refCnt = 8, refCntWtd = 31 New refCnts for V16: refCnt = 46, refCntWtd = 792 New refCnts for V37: refCnt = 2, refCntWtd = 4 New refCnts for V176: refCnt = 8, refCntWtd = 16 New refCnts for V34: refCnt = 9, refCntWtd = 33 New refCnts for V16: refCnt = 47, refCntWtd = 794 New refCnts for V00: refCnt = 53, refCntWtd = 185.50 New refCnts for V126: refCnt = 1, refCntWtd = 2 New refCnts for V126: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 54, refCntWtd = 187.50 New refCnts for V00: refCnt = 55, refCntWtd = 189.50 New refCnts for V127: refCnt = 1, refCntWtd = 4 New refCnts for V126: refCnt = 3, refCntWtd = 6 New refCnts for V127: refCnt = 2, refCntWtd = 8 New refCnts for V127: refCnt = 3, refCntWtd = 12 New refCnts for V126: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 31, refCntWtd = 228 New refCnts for V126: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 56, refCntWtd = 191.50 New refCnts for V38: refCnt = 2, refCntWtd = 10 New refCnts for V38: refCnt = 3, refCntWtd = 18 New refCnts for V16: refCnt = 48, refCntWtd = 810 New refCnts for V54: refCnt = 1, refCntWtd = 32 New refCnts for V54: refCnt = 2, refCntWtd = 64 New refCnts for V16: refCnt = 49, refCntWtd = 826 New refCnts for V16: refCnt = 50, refCntWtd = 842 New refCnts for V179: refCnt = 15, refCntWtd = 266 New refCnts for V34: refCnt = 10, refCntWtd = 49 New refCnts for V16: refCnt = 51, refCntWtd = 858 New refCnts for V38: refCnt = 4, refCntWtd = 20 New refCnts for V38: refCnt = 5, refCntWtd = 22 New refCnts for V17: refCnt = 6, refCntWtd = 17 New refCnts for V01: refCnt = 15, refCntWtd = 19.50 New refCnts for V05: refCnt = 18, refCntWtd = 56 New refCnts for V55: refCnt = 1, refCntWtd = 2 New refCnts for V55: refCnt = 2, refCntWtd = 4 New refCnts for V37: refCnt = 3, refCntWtd = 6 New refCnts for V00: refCnt = 57, refCntWtd = 193.50 New refCnts for V03: refCnt = 10, refCntWtd = 20.50 New refCnts for V55: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 32, refCntWtd = 230 New refCnts for V38: refCnt = 6, refCntWtd = 24 New refCnts for V09: refCnt = 6, refCntWtd = 25 New refCnts for V00: refCnt = 58, refCntWtd = 195.50 New refCnts for V129: refCnt = 1, refCntWtd = 2 New refCnts for V129: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 59, refCntWtd = 197.50 New refCnts for V00: refCnt = 60, refCntWtd = 199.50 New refCnts for V130: refCnt = 1, refCntWtd = 4 New refCnts for V129: refCnt = 3, refCntWtd = 6 New refCnts for V130: refCnt = 2, refCntWtd = 8 New refCnts for V130: refCnt = 3, refCntWtd = 12 New refCnts for V129: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 33, refCntWtd = 232 New refCnts for V129: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 61, refCntWtd = 201.50 New refCnts for V00: refCnt = 62, refCntWtd = 203.50 New refCnts for V18: refCnt = 34, refCntWtd = 234 New refCnts for V16: refCnt = 52, refCntWtd = 860 New refCnts for V179: refCnt = 16, refCntWtd = 268 New refCnts for V34: refCnt = 11, refCntWtd = 51 New refCnts for V16: refCnt = 53, refCntWtd = 862 New refCnts for V175: refCnt = 1, refCntWtd = 2 New refCnts for V175: refCnt = 2, refCntWtd = 4 New refCnts for V175: refCnt = 3, refCntWtd = 6 New refCnts for V16: refCnt = 54, refCntWtd = 864 New refCnts for V52: refCnt = 1, refCntWtd = 4 New refCnts for V52: refCnt = 2, refCntWtd = 8 New refCnts for V16: refCnt = 55, refCntWtd = 866 New refCnts for V175: refCnt = 4, refCntWtd = 8 New refCnts for V133: refCnt = 1, refCntWtd = 4 New refCnts for V00: refCnt = 63, refCntWtd = 205.50 New refCnts for V132: refCnt = 1, refCntWtd = 2 New refCnts for V132: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 64, refCntWtd = 207.50 New refCnts for V00: refCnt = 65, refCntWtd = 209.50 New refCnts for V134: refCnt = 1, refCntWtd = 4 New refCnts for V132: refCnt = 3, refCntWtd = 6 New refCnts for V134: refCnt = 2, refCntWtd = 8 New refCnts for V134: refCnt = 3, refCntWtd = 12 New refCnts for V132: refCnt = 4, refCntWtd = 8 New refCnts for V133: refCnt = 2, refCntWtd = 8 New refCnts for V132: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 66, refCntWtd = 211.50 New refCnts for V00: refCnt = 67, refCntWtd = 213.50 New refCnts for V133: refCnt = 3, refCntWtd = 12 New refCnts for V16: refCnt = 56, refCntWtd = 874 New refCnts for V53: refCnt = 1, refCntWtd = 16 New refCnts for V53: refCnt = 2, refCntWtd = 32 New refCnts for V16: refCnt = 57, refCntWtd = 882 New refCnts for V173: refCnt = 1, refCntWtd = 8 New refCnts for V137: refCnt = 1, refCntWtd = 16 New refCnts for V00: refCnt = 68, refCntWtd = 221.50 New refCnts for V136: refCnt = 1, refCntWtd = 8 New refCnts for V136: refCnt = 2, refCntWtd = 16 New refCnts for V00: refCnt = 69, refCntWtd = 229.50 New refCnts for V00: refCnt = 70, refCntWtd = 237.50 New refCnts for V138: refCnt = 1, refCntWtd = 16 New refCnts for V136: refCnt = 3, refCntWtd = 24 New refCnts for V138: refCnt = 2, refCntWtd = 32 New refCnts for V138: refCnt = 3, refCntWtd = 48 New refCnts for V136: refCnt = 4, refCntWtd = 32 New refCnts for V137: refCnt = 2, refCntWtd = 32 New refCnts for V136: refCnt = 5, refCntWtd = 40 New refCnts for V00: refCnt = 71, refCntWtd = 245.50 New refCnts for V00: refCnt = 72, refCntWtd = 253.50 New refCnts for V137: refCnt = 3, refCntWtd = 48 New refCnts for V16: refCnt = 58, refCntWtd = 898 New refCnts for V179: refCnt = 17, refCntWtd = 284 New refCnts for V34: refCnt = 12, refCntWtd = 67 New refCnts for V16: refCnt = 59, refCntWtd = 914 New refCnts for V173: refCnt = 2, refCntWtd = 24 New refCnts for V173: refCnt = 3, refCntWtd = 40 New refCnts for V00: refCnt = 73, refCntWtd = 255.50 New refCnts for V140: refCnt = 1, refCntWtd = 2 New refCnts for V140: refCnt = 2, refCntWtd = 4 New refCnts for V00: refCnt = 74, refCntWtd = 257.50 New refCnts for V00: refCnt = 75, refCntWtd = 259.50 New refCnts for V141: refCnt = 1, refCntWtd = 4 New refCnts for V140: refCnt = 3, refCntWtd = 6 New refCnts for V141: refCnt = 2, refCntWtd = 8 New refCnts for V141: refCnt = 3, refCntWtd = 12 New refCnts for V140: refCnt = 4, refCntWtd = 8 New refCnts for V18: refCnt = 35, refCntWtd = 236 New refCnts for V140: refCnt = 5, refCntWtd = 10 New refCnts for V00: refCnt = 76, refCntWtd = 261.50 New refCnts for V00: refCnt = 77, refCntWtd = 263.50 New refCnts for V18: refCnt = 36, refCntWtd = 238 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 78, refCntWtd = 264.50 New refCnts for V00: refCnt = 79, refCntWtd = 265.50 New refCnts for V01: refCnt = 16, refCntWtd = 20.50 New refCnts for V01: refCnt = 17, refCntWtd = 21.50 New refCnts for V02: refCnt = 4, refCntWtd = 7 New refCnts for V02: refCnt = 5, refCntWtd = 8 New refCnts for V03: refCnt = 11, refCntWtd = 21.50 New refCnts for V03: refCnt = 12, refCntWtd = 22.50 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..061)-> BB10 ( cond ) i bwd LIR BB255 [0364] 1 BB09 8 [061..083)-> BB31,BB17,BB47,BB30,BB47,BB31 (switch) i bwd LIR BB10 [0009] 1 BB09 8 1 [083..083)-> BB11 ( cond ) i bwd LIR BB256 [0365] 1 BB10 8 [083..0A1)-> BB23,BB47,BB21,BB47,BB18 (switch) i bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB255 8 1 [0CF..0D8)-> BB47 (always) i bwd LIR BB18 [0017] 1 BB256 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd LIR BB21 [0020] 1 BB256 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB256 8 1 [0FB..102)-> BB47 ( cond ) i bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd LIR BB30 [0029] 1 BB255 8 1 [12C..137)-> BB47 (always) i bwd LIR BB31 [0031] 3 BB32,BB255(2) 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd LIR BB44 [0044] 3 BB39,BB43,BB45 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd LIR BB47 [0047] 24 BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB255(2),BB256(2) 64 1 [204..20F)-> BB50 ( cond ) i bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB103 ( cond ) i idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd LIR BB103 [0096] 4 BB78,BB85,BB89,BB102 1 [3C8..3D0)-> BB112 ( cond ) i LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i LIR BB245 [0190] 25 BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB258 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB136 ( cond ) i Loop Loop0 bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB135 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB134 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd LIR BB134 [0114] 3 BB124,BB125,BB133 8 3 [461..46D) i bwd LIR BB135 [0115] 3 BB114,BB115,BB134 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src LIR BB136 [0116] 3 BB113,BB117,BB135 2 3 [472..478)-> BB141 ( cond ) i bwd LIR BB137 [0117] 1 BB136 2 3 [478..478)-> BB138 ( cond ) i bwd LIR BB257 [0366] 1 BB137 2 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194 (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..49A)-> BB139 ( cond ) i bwd LIR BB258 [0367] 1 BB138 2 [49A..4B8)-> BB245,BB242,BB171,BB242,BB145 (switch) i bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB257,BB258 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB170 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd LIR BB170 [0142] 4 BB156,BB160,BB161,BB169 2 3 [559..564)-> BB245 (always) i bwd LIR BB171 [0143] 1 BB258 2 3 [564..571)-> BB245 ( cond ) i bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd LIR BB186 [0149] 1 BB257 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd LIR BB194 [0151] 4 BB192,BB193,BB257(2) 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB245 ( cond ) i bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB244 ( cond ) i bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB218 [0172] 2 BB207,BB220 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB218 ( cond ) i bwd bwd-src LIR BB221 [0175] 2 BB219,BB220 2 3 [701..707)-> BB223 ( cond ) i bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB140,BB143,BB257(2),BB258(2) 2 3 [7A2..7AA)-> BB244 ( cond ) i bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB244 [0355] 2 BB215,BB242 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd LIR BB254 [0363] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} [003780] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 $101 /--* t0 byref [004185] ----------- t4185 = * PUTARG_REG byref REG x0 N002 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn $42 /--* t2543 long [004186] ----------- t4186 = * PUTARG_REG long REG x11 /--* t4185 byref this in x0 +--* t4186 long r2r cell in x11 N003 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void $VN.Void [003781] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 1, 2) [000002] -c--------- t2 = CNS_INT int 0 $c0 /--* t2 int N003 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 [003782] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] N001 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002547] -c--------- t2547 = CNS_INT long 16 $200 /--* t2546 byref +--* t2547 long N003 ( 3, 4) [002548] -----O----- t2548 = * ADD byref $240 /--* t2548 byref N005 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 [003783] ----------- IL_OFFSET void INLRT @ 0x009[E-] N001 ( 1, 2) [001497] -c--------- t1497 = CNS_INT int 0 $c0 N002 ( 1, 1) [001502] ----------- t1502 = LCL_VAR byref V76 tmp36 u:1 $240 /--* t1502 byref N004 ( 3, 4) [002556] -c--------- t2556 = * LEA(b+8) byref /--* t2556 byref N005 ( 4, 3) [001503] ---XG------ t1503 = * IND int /--* t1497 int +--* t1503 int N006 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 (last use) $240 /--* t1501 byref N008 ( 3, 2) [001505] n---GO----- t1505 = * IND byref /--* t1505 byref N011 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 N012 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 (last use) /--* t2552 long N015 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 N001 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] $246 /--* t2558 byref N003 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 N004 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3710 byref N007 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 N008 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] $342 /--* t2561 int N010 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 N011 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 $342 /--* t3690 int N014 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 [003784] ----------- IL_OFFSET void INLRT @ 0x011[E-] N001 ( 1, 1) [000011] ----------- t11 = LCL_VAR long V17 loc13 u:1 /--* t11 long N002 ( 4, 3) [000012] ---XG------ t12 = * IND ubyte N003 ( 1, 2) [000013] -c--------- t13 = CNS_INT int 0 $c0 /--* t12 ubyte +--* t13 int N004 ( 6, 6) [000014] CEQ---XG--N--- * JCMP void ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N001 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2565 byref N003 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 N004 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2568 int N006 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 N001 ( 1, 1) [001472] ----------- t1472 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1472 byref N003 ( 3, 4) [002572] -c--------- t2572 = * LEA(b+8) byref /--* t2572 byref N004 ( 5, 4) [001473] n---GO----- t1473 = * IND bool N005 ( 1, 2) [001474] -c--------- t1474 = CNS_INT int 0 $c0 /--* t1473 bool +--* t1474 int N006 ( 7, 7) [001475] CNE----GO-N--- * JCMP void ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} N001 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2574 byref N003 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 N004 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2577 int N006 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 N001 ( 1, 2) [001489] -c--------- t1489 = CNS_INT int 0 $c0 /--* t1489 int N003 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} N001 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 (last use) $246 /--* t2581 byref N003 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 N004 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 (last use) $342 /--* t2584 int N006 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 N001 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 $c1 /--* t1482 int N003 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 ------------ BB05 [025..026), preds={BB01} succs={BB06} N001 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 (last use) $246 /--* t2588 byref N003 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 N004 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 (last use) $342 /--* t2591 int N006 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 N001 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 $c2 /--* t21 int N003 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} N001 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 (last use) $246 /--* t2596 byref [004187] ----------- t4187 = * PUTARG_REG byref REG x0 N002 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 (last use) $342 /--* t2597 int [004188] ----------- t4188 = * PUTARG_REG int REG x1 /--* t4187 byref +--* t4188 int N003 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct $141 N004 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 (last use) $281 /--* t29 int [004189] ----------- t4189 = * PUTARG_REG int REG x2 N005 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2594 long [004190] ----------- t4190 = * PUTARG_REG long REG x11 /--* t2595 struct arg1 x0,x1 +--* t4189 int arg2 in x2 +--* t4190 long r2r cell in x11 N006 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int $2c1 /--* t30 int N008 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} [003785] ----------- IL_OFFSET void INLRT @ 0x02D[E-] N001 ( 1, 2) [000035] -c--------- t35 = CNS_INT int 0 $c0 /--* t35 int N003 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 [003786] ----------- IL_OFFSET void INLRT @ 0x02F[E-] N001 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 $c4 /--* t38 int N003 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 [003787] ----------- IL_OFFSET void INLRT @ 0x031[E-] N001 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF $c9 /--* t41 int N003 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 [003788] ----------- IL_OFFSET void INLRT @ 0x037[E-] N001 ( 1, 2) [000044] -c--------- t44 = CNS_INT int 0 $c0 /--* t44 int N003 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 [003789] ----------- IL_OFFSET void INLRT @ 0x039[E-] N001 ( 1, 2) [002598] -c--------- t2598 = CNS_INT int 0 $c0 /--* t2598 int N003 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 [003790] ----------- IL_OFFSET void INLRT @ 0x03C[E-] N001 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 $c4 /--* t50 int N003 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 [003791] ----------- IL_OFFSET void INLRT @ 0x03F[E-] N001 ( 1, 2) [002599] -c--------- t2599 = CNS_INT int 0 $c0 /--* t2599 int N003 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 [003792] ----------- IL_OFFSET void INLRT @ 0x042[E-] N001 ( 1, 2) [000056] -c--------- t56 = CNS_INT int 0 $c0 /--* t56 int N003 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 [003793] ----------- IL_OFFSET void INLRT @ 0x045[E-] N001 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 $283 /--* t59 int N003 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 [003794] ----------- IL_OFFSET void INLRT @ 0x049[E-] N001 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3712 byref N003 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 [003795] ----------- IL_OFFSET void INLRT @ 0x049[E-] N001 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 $246 /--* t1512 byref N003 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 [003796] ----------- IL_OFFSET void INLRT @ 0x051[E-] N001 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 (last use) $246 /--* t69 byref N003 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 N004 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 (last use) $3c4 /--* t2609 long N007 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} [003797] ----------- IL_OFFSET void INLRT @ 0x05B[E-] N001 ( 1, 1) [001226] ----------- t1226 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001227] -c--------- t1227 = CNS_INT int 69 $d2 /--* t1226 int +--* t1227 int N003 ( 3, 4) [001228] N------N-U- * GT void N004 ( 5, 6) [001229] ----------- * JTRUE void $VN.Void ------------ BB09 [061..061) -> BB10 (cond), preds={BB08} succs={BB255,BB10} [003798] ----------- IL_OFFSET void INLRT @ 0x061[E-] N001 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001362] -c--------- t1362 = CNS_INT int -34 $d6 /--* t1361 int +--* t1362 int N003 ( 3, 4) [001363] ----------- t1363 = * ADD int /--* t1363 int [004192] DA--------- * STORE_LCL_VAR int V182 rat0 N001 ( 3, 2) [004194] ----------- t4194 = LCL_VAR int V182 rat0 N002 ( 1, 2) [004195] -c--------- t4195 = CNS_INT int 5 /--* t4194 int +--* t4195 int N003 ( 8, 5) [004196] ---------U- * GT void N004 ( 10, 7) [004197] ----------- * JTRUE void ------------ BB255 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31 (switch), preds={BB09} succs={BB17,BB30,BB31,BB47} [004198] ----------- t4198 = LCL_VAR int V182 rat0 (last use) /--* t4198 int [004199] ---------U- t4199 = * CAST long <- ulong <- uint [004200] ----------- t4200 = JMPTABLE long /--* t4199 long +--* t4200 long [004201] ----------- * SWITCH_TABLE void ------------ BB10 [083..083) -> BB11 (cond), preds={BB09} succs={BB256,BB11} [003799] ----------- IL_OFFSET void INLRT @ 0x083[E-] N001 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001366] -c--------- t1366 = CNS_INT int -44 $d7 /--* t1365 int +--* t1366 int N003 ( 3, 4) [001367] ----------- t1367 = * ADD int /--* t1367 int [004203] DA--------- * STORE_LCL_VAR int V183 rat1 N001 ( 3, 2) [004205] ----------- t4205 = LCL_VAR int V183 rat1 N002 ( 1, 2) [004206] -c--------- t4206 = CNS_INT int 4 /--* t4205 int +--* t4206 int N003 ( 8, 5) [004207] ---------U- * GT void N004 ( 10, 7) [004208] ----------- * JTRUE void ------------ BB256 [083..0A1) -> BB23,BB47,BB21,BB47,BB18 (switch), preds={BB10} succs={BB18,BB21,BB23,BB47} [004209] ----------- t4209 = LCL_VAR int V183 rat1 (last use) /--* t4209 int [004210] ---------U- t4210 = * CAST long <- ulong <- uint [004211] ----------- t4211 = JMPTABLE long /--* t4210 long +--* t4211 long [004212] ----------- * SWITCH_TABLE void ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} [003800] ----------- IL_OFFSET void INLRT @ 0x0A1[E-] N001 ( 1, 1) [001369] ----------- t1369 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 2) [001370] -c--------- t1370 = CNS_INT int 69 $d2 /--* t1369 int +--* t1370 int N003 ( 3, 4) [001371] J------N--- * EQ void N004 ( 5, 6) [001372] ----------- * JTRUE void $VN.Void ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} [003801] ----------- IL_OFFSET void INLRT @ 0x0AF[E-] N001 ( 1, 1) [001230] ----------- t1230 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001231] -c--------- t1231 = CNS_INT int 92 $d3 /--* t1230 int +--* t1231 int N003 ( 3, 4) [001232] J------N--- * EQ void N004 ( 5, 6) [001233] ----------- * JTRUE void $VN.Void ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} [003802] ----------- IL_OFFSET void INLRT @ 0x0B8[E-] N001 ( 1, 1) [001257] ----------- t1257 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001258] -c--------- t1258 = CNS_INT int 101 $d4 /--* t1257 int +--* t1258 int N003 ( 3, 4) [001259] J------N--- * EQ void N004 ( 5, 6) [001260] ----------- * JTRUE void $VN.Void ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} [003803] ----------- IL_OFFSET void INLRT @ 0x0C1[E-] N001 ( 1, 1) [001352] ----------- t1352 = LCL_VAR int V18 loc14 u:5 (last use) N002 ( 1, 4) [001353] ----------- t1353 = CNS_INT int 0x2030 $d5 /--* t1352 int +--* t1353 int N003 ( 3, 6) [001354] J------N--- * NE void N004 ( 5, 8) [001355] ----------- * JTRUE void $VN.Void ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} [003804] ----------- IL_OFFSET void INLRT @ 0x137[E-] N001 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001357] -c--------- t1357 = CNS_INT int 3 $c3 /--* t1356 int +--* t1357 int N003 ( 3, 4) [001358] ----------- t1358 = * ADD int $376 /--* t1358 int N005 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB255} succs={BB47} [003805] ----------- IL_OFFSET void INLRT @ 0x0CF[E-] N001 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001431] -c--------- t1431 = CNS_INT int 1 $c1 /--* t1430 int +--* t1431 int N003 ( 3, 4) [001432] ----------- t1432 = * ADD int $68f /--* t1432 int N005 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB256} succs={BB19,BB20} [003806] ----------- IL_OFFSET void INLRT @ 0x0D8[E-] N001 ( 1, 1) [001373] ----------- t1373 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 4) [001374] ----------- t1374 = CNS_INT int 0x7FFFFFFF $c9 /--* t1373 int +--* t1374 int N003 ( 3, 6) [001375] N------N-U- * NE void $68e N004 ( 5, 8) [001376] ----------- * JTRUE void $VN.Void ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} [003807] ----------- IL_OFFSET void INLRT @ 0x0E0[E-] N001 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 $28a /--* t1385 int N003 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} [003808] ----------- IL_OFFSET void INLRT @ 0x0E2[E-] N001 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 (last use) $28a N002 ( 1, 2) [001378] -c--------- t1378 = CNS_INT int 1 $c1 /--* t1377 int +--* t1378 int N003 ( 3, 4) [001379] ----------- t1379 = * ADD int $68f /--* t1379 int N005 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 [003809] ----------- IL_OFFSET void INLRT @ 0x0E6[E-] N001 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 $68f /--* t1382 int N003 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB256} succs={BB22,BB47} [003810] ----------- IL_OFFSET void INLRT @ 0x0ED[E-] N001 ( 1, 1) [001388] ----------- t1388 = LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [001389] -c--------- t1389 = CNS_INT int 0 $c0 /--* t1388 int +--* t1389 int N003 ( 3, 4) [001390] J------N--- * GE void $690 N004 ( 5, 6) [001391] ----------- * JTRUE void $VN.Void ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} [003811] ----------- IL_OFFSET void INLRT @ 0x0F4[E-] N001 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 $28a /--* t1392 int N003 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB256} succs={BB24,BB47} [003812] ----------- IL_OFFSET void INLRT @ 0x0FB[E-] N001 ( 1, 1) [001395] ----------- t1395 = LCL_VAR int V04 loc0 u:2 $28a N002 ( 1, 2) [001396] -c--------- t1396 = CNS_INT int 0 $c0 /--* t1395 int +--* t1396 int N003 ( 6, 4) [001397] -c-----N--- t1397 = * LE int $691 N004 ( 1, 1) [001399] ----------- t1399 = LCL_VAR int V05 loc1 u:2 $286 N005 ( 1, 2) [001400] -c--------- t1400 = CNS_INT int 0 $c0 /--* t1399 int +--* t1400 int N006 ( 6, 4) [001401] -c-----N--- t1401 = * GE int $690 /--* t1397 int +--* t1401 int N007 ( 13, 9) [003726] Jc-----N--- * AND void N008 ( 15, 11) [001398] ----------- * JTRUE void $VN.Void ------------ BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} [003813] ----------- IL_OFFSET void INLRT @ 0x102[E-] [003814] ----------- IL_OFFSET void INLRT @ 0x109[E-] N001 ( 1, 1) [001403] ----------- t1403 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [001404] -c--------- t1404 = CNS_INT int 0 $c0 /--* t1403 int +--* t1404 int N003 ( 3, 4) [001405] J------N--- * LT void $692 N004 ( 5, 6) [001406] ----------- * JTRUE void $VN.Void ------------ BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} [003815] ----------- IL_OFFSET void INLRT @ 0x10E[E-] N001 ( 1, 1) [001413] ----------- t1413 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 1) [001414] ----------- t1414 = LCL_VAR int V04 loc0 u:2 $28a /--* t1413 int +--* t1414 int N003 ( 3, 3) [001415] N------N-U- * NE void $693 N004 ( 5, 5) [001416] ----------- * JTRUE void $VN.Void ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} [003816] ----------- IL_OFFSET void INLRT @ 0x113[E-] N001 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 (last use) $288 N002 ( 1, 2) [001421] -c--------- t1421 = CNS_INT int 1 $c1 /--* t1420 int +--* t1421 int N003 ( 3, 4) [001422] ----------- t1422 = * ADD int $694 /--* t1422 int N005 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 ------------ BB28 [11E..121), preds={BB26} succs={BB29} [003817] ----------- IL_OFFSET void INLRT @ 0x11E[E-] N001 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 $c1 /--* t2612 int N003 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 ------------ BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} [003818] ----------- IL_OFFSET void INLRT @ 0x121[E-] N001 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 $28a /--* t1407 int N003 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 [003819] ----------- IL_OFFSET void INLRT @ 0x124[E-] N001 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 $c1 /--* t1410 int N003 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 ------------ BB30 [12C..137) -> BB47 (always), preds={BB255} succs={BB47} [003820] ----------- IL_OFFSET void INLRT @ 0x12C[E-] N001 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 2) [001426] -c--------- t1426 = CNS_INT int 2 $c2 /--* t1425 int +--* t1426 int N003 ( 3, 4) [001427] ----------- t1427 = * ADD int $695 /--* t1427 int N005 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 ------------ BB31 [142..150) -> BB47 (cond), preds={BB32,BB255(2)} succs={BB32,BB47} [003821] ----------- IL_OFFSET void INLRT @ 0x142[E-] N001 ( 1, 1) [001435] ----------- t1435 = LCL_VAR int V16 loc12 u:21 $2b1 N002 ( 1, 1) [003693] ----------- t3693 = LCL_VAR int V179 cse8 u:1 $342 /--* t1435 int +--* t3693 int N003 ( 6, 3) [001440] -c-----N--- t1440 = * GE int $8b7 N004 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 $2b1 /--* t1443 int N006 ( 2, 3) [001444] -c--------- t1444 = * CAST long <- int $3de N007 ( 1, 2) [001446] -c--------- t1446 = CNS_INT long 1 $204 /--* t1444 long +--* t1446 long N008 ( 4, 6) [001447] -c--------- t1447 = * BFIZ long /--* t1442 long +--* t1447 long N009 ( 6, 8) [001448] -c--------- t1448 = * LEA(b+(i*1)+0) long /--* t1448 long N010 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort /--* t1449 ushort N012 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 N013 ( 1, 1) [003626] ----------- t3626 = LCL_VAR int V171 cse0 u:1 N015 ( 1, 2) [001450] -c--------- t1450 = CNS_INT int 0 $c0 /--* t3626 int +--* t1450 int N016 ( 15, 14) [001451] -c-XG--N--- t1451 = * EQ int /--* t1440 int +--* t1451 int N017 ( 22, 18) [003728] Jc-XG--N--- * AND void N018 ( 24, 20) [001441] ---XG------ * JTRUE void $VN.Void ------------ BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} [003822] ----------- IL_OFFSET void INLRT @ 0x150[E-] [003823] ----------- IL_OFFSET void INLRT @ 0x15E[E-] N001 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 (last use) $2b1 /--* t1454 int N003 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 [003824] ----------- IL_OFFSET void INLRT @ 0x15E[E-] N001 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 (last use) $2b1 N002 ( 1, 2) [001456] -c--------- t1456 = CNS_INT int 1 $c1 /--* t1455 int +--* t1456 int N003 ( 3, 4) [001457] ----------- t1457 = * ADD int $8bc /--* t1457 int N005 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 N001 ( 1, 1) [003628] ----------- t3628 = LCL_VAR int V171 cse0 u:1 (last use) N002 ( 1, 1) [001469] ----------- t1469 = LCL_VAR int V18 loc14 u:5 /--* t3628 int +--* t1469 int N003 ( 3, 3) [001470] N---G--N-U- * NE void N004 ( 5, 5) [001471] ----G------ * JTRUE void $876 ------------ BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} [003825] ----------- IL_OFFSET void INLRT @ 0x175[E-] N001 ( 1, 1) [001234] ----------- t1234 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003694] ----------- t3694 = LCL_VAR int V179 cse8 u:1 $342 /--* t1234 int +--* t3694 int N003 ( 6, 3) [001239] -c-----N--- t1239 = * GE int $36c N004 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 $3c4 N005 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 $361 /--* t1242 int N006 ( 2, 3) [001243] -c--------- t1243 = * CAST long <- int $3c8 N007 ( 1, 2) [001245] -c--------- t1245 = CNS_INT long 1 $204 /--* t1243 long +--* t1245 long N008 ( 4, 6) [001246] -c--------- t1246 = * BFIZ long /--* t1241 long +--* t1246 long N009 ( 6, 8) [001247] -c--------- t1247 = * LEA(b+(i*1)+0) long /--* t1247 long N010 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort /--* t1248 ushort N012 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 N013 ( 1, 1) [003646] ----------- t3646 = LCL_VAR int V174 cse3 (last use) N015 ( 1, 2) [001249] -c--------- t1249 = CNS_INT int 0 $c0 /--* t3646 int +--* t1249 int N016 ( 15, 14) [001250] -c-XG--N--- t1250 = * EQ int /--* t1239 int +--* t1250 int N017 ( 22, 18) [003730] Jc-XG--N--- * AND void N018 ( 24, 20) [001240] ---XG------ * JTRUE void $VN.Void ------------ BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} [003826] ----------- IL_OFFSET void INLRT @ 0x183[E-] [003827] ----------- IL_OFFSET void INLRT @ 0x18E[E-] N001 ( 1, 1) [001252] ----------- t1252 = LCL_VAR int V16 loc12 u:17 (last use) $361 N002 ( 1, 2) [001253] -c--------- t1253 = CNS_INT int 1 $c1 /--* t1252 int +--* t1253 int N003 ( 3, 4) [001254] ----------- t1254 = * ADD int $371 /--* t1254 int N005 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} [003828] ----------- IL_OFFSET void INLRT @ 0x196[E-] N001 ( 1, 1) [001261] ----------- t1261 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 1) [003695] ----------- t3695 = LCL_VAR int V179 cse8 u:1 $342 /--* t1261 int +--* t3695 int N003 ( 3, 3) [001266] J------N--- * GE void $36c N004 ( 5, 5) [001267] ----------- * JTRUE void $VN.Void ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} [003829] ----------- IL_OFFSET void INLRT @ 0x1A1[E-] N001 ( 1, 1) [001341] ----------- t1341 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001342] ----------- t1342 = LCL_VAR int V16 loc12 u:17 $361 /--* t1342 int N003 ( 2, 3) [001343] -c--------- t1343 = * CAST long <- int $3c8 N004 ( 1, 2) [001345] -c--------- t1345 = CNS_INT long 1 $204 /--* t1343 long +--* t1345 long N005 ( 4, 6) [001346] -c--------- t1346 = * BFIZ long /--* t1341 long +--* t1346 long N006 ( 6, 8) [001347] -c--------- t1347 = * LEA(b+(i*1)+0) long /--* t1347 long N007 ( 9, 10) [001348] ---XG------ t1348 = * IND ushort /--* t1348 ushort N009 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 N010 ( 1, 1) [003650] ----------- t3650 = LCL_VAR int V174 cse3 (last use) N012 ( 1, 2) [001349] -c--------- t1349 = CNS_INT int 48 $d8 /--* t3650 int +--* t1349 int N013 ( 12, 14) [001350] J--XG--N--- * EQ void N014 ( 14, 16) [001351] ---XG------ * JTRUE void $311 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} [003830] ----------- IL_OFFSET void INLRT @ 0x1AE[E-] N001 ( 1, 1) [001268] ----------- t1268 = LCL_VAR int V16 loc12 u:17 $361 N002 ( 1, 2) [001269] -c--------- t1269 = CNS_INT int 1 $c1 /--* t1268 int +--* t1269 int N003 ( 3, 4) [001270] ----------- t1270 = * ADD int $371 N004 ( 1, 1) [003696] ----------- t3696 = LCL_VAR int V179 cse8 u:1 $342 /--* t1270 int +--* t3696 int N005 ( 5, 6) [001275] J------N--- * GE void $681 N006 ( 7, 8) [001276] ----------- * JTRUE void $VN.Void ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} [003831] ----------- IL_OFFSET void INLRT @ 0x1BB[E-] N001 ( 1, 1) [001277] ----------- t1277 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001278] ----------- t1278 = LCL_VAR int V16 loc12 u:17 $361 /--* t1278 int N003 ( 2, 3) [001279] -c--------- t1279 = * CAST long <- int $3c8 N004 ( 1, 2) [001281] -c--------- t1281 = CNS_INT long 1 $204 /--* t1279 long +--* t1281 long N005 ( 4, 6) [001282] -c--------- t1282 = * BFIZ long /--* t1277 long +--* t1282 long N006 ( 6, 8) [001283] -c--------- t1283 = * LEA(b+(i*1)+0) long /--* t1283 long N007 ( 9, 10) [001284] ---XG------ t1284 = * IND ushort /--* t1284 ushort N009 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 N010 ( 1, 1) [003654] ----------- t3654 = LCL_VAR int V174 cse3 N012 ( 1, 2) [001285] -c--------- t1285 = CNS_INT int 43 $d9 /--* t3654 int +--* t1285 int N013 ( 12, 14) [001286] J--XG--N--- * EQ void N014 ( 14, 16) [001287] ---XG------ * JTRUE void $311 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} [003832] ----------- IL_OFFSET void INLRT @ 0x1C8[E-] N001 ( 1, 1) [003656] ----------- t3656 = LCL_VAR int V174 cse3 (last use) N002 ( 1, 2) [001338] -c--------- t1338 = CNS_INT int 45 $da /--* t3656 int +--* t1338 int N003 ( 3, 4) [001339] N---G--N-U- * NE void N004 ( 5, 6) [001340] ----G------ * JTRUE void $311 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} [003833] ----------- IL_OFFSET void INLRT @ 0x1D5[E-] N001 ( 1, 1) [001288] ----------- t1288 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001289] ----------- t1289 = LCL_VAR int V16 loc12 u:17 $361 N003 ( 1, 2) [001290] -c--------- t1290 = CNS_INT int 1 $c1 /--* t1289 int +--* t1290 int N004 ( 3, 4) [001291] ----------- t1291 = * ADD int $371 /--* t1291 int N005 ( 4, 6) [001292] -c--------- t1292 = * CAST long <- int $3cb N006 ( 1, 2) [001294] -c--------- t1294 = CNS_INT long 1 $204 /--* t1292 long +--* t1294 long N007 ( 6, 9) [001295] -c--------- t1295 = * BFIZ long /--* t1288 long +--* t1295 long N008 ( 8, 11) [001296] -c--------- t1296 = * LEA(b+(i*1)+0) long /--* t1296 long N009 ( 11, 13) [001297] ---XG------ t1297 = * IND ushort N010 ( 1, 2) [001298] -c--------- t1298 = CNS_INT int 48 $d8 /--* t1297 ushort +--* t1298 int N011 ( 13, 16) [001299] N--XG--N-U- * NE void N012 ( 15, 18) [001300] ---XG------ * JTRUE void $313 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} [003834] ----------- IL_OFFSET void INLRT @ 0x1E4[E-] N001 ( 1, 1) [001301] ----------- t1301 = LCL_VAR int V16 loc12 u:18 (last use) $2b2 N002 ( 1, 2) [001302] -c--------- t1302 = CNS_INT int 1 $c1 /--* t1301 int +--* t1302 int N003 ( 3, 4) [001303] ----------- t1303 = * ADD int $942 /--* t1303 int N005 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 N001 ( 1, 1) [001307] ----------- t1307 = LCL_VAR int V73 tmp33 u:1 (last use) $942 /--* t1307 int N003 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 N001 ( 1, 1) [001306] ----------- t1306 = LCL_VAR int V16 loc12 u:19 $942 N002 ( 1, 1) [003697] ----------- t3697 = LCL_VAR int V179 cse8 u:1 $342 /--* t1306 int +--* t3697 int N003 ( 3, 3) [001314] J------N--- * GE void $943 N004 ( 5, 5) [001315] ----------- * JTRUE void $VN.Void ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} [003835] ----------- IL_OFFSET void INLRT @ 0x1F4[E-] N001 ( 1, 1) [001319] ----------- t1319 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001320] ----------- t1320 = LCL_VAR int V16 loc12 u:19 $942 /--* t1320 int N003 ( 2, 3) [001321] -c--------- t1321 = * CAST long <- int $3e1 N004 ( 1, 2) [001323] -c--------- t1323 = CNS_INT long 1 $204 /--* t1321 long +--* t1323 long N005 ( 4, 6) [001324] -c--------- t1324 = * BFIZ long /--* t1319 long +--* t1324 long N006 ( 6, 8) [001325] -c--------- t1325 = * LEA(b+(i*1)+0) long /--* t1325 long N007 ( 9, 10) [001326] ---XG------ t1326 = * IND ushort N008 ( 1, 2) [001327] -c--------- t1327 = CNS_INT int 48 $d8 /--* t1326 ushort +--* t1327 int N009 ( 11, 13) [001328] J--XG--N--- * EQ void N010 ( 13, 15) [001329] ---XG------ * JTRUE void $878 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} [003836] ----------- IL_OFFSET void INLRT @ 0x201[E-] N001 ( 1, 2) [002613] ----------- t2613 = CNS_INT int 1 $c1 /--* t2613 int N003 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB255(2),BB256(2)} succs={BB48,BB50} [003837] ----------- IL_OFFSET void INLRT @ 0x204[E-] N001 ( 1, 1) [000073] ----------- t73 = LCL_VAR int V16 loc12 u:2 $28b N002 ( 1, 1) [003698] ----------- t3698 = LCL_VAR int V179 cse8 u:1 $342 /--* t73 int +--* t3698 int N003 ( 3, 3) [000078] J------N--- * GE void $360 N004 ( 5, 5) [000079] ----------- * JTRUE void $VN.Void ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} [003838] ----------- IL_OFFSET void INLRT @ 0x20F[E-] N001 ( 1, 1) [001198] ----------- t1198 = LCL_VAR int V16 loc12 u:2 (last use) $28b /--* t1198 int N003 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 [003839] ----------- IL_OFFSET void INLRT @ 0x20F[E-] N001 ( 1, 1) [001199] ----------- t1199 = LCL_VAR int V71 tmp31 u:1 $28b N002 ( 1, 2) [001200] -c--------- t1200 = CNS_INT int 1 $c1 /--* t1199 int +--* t1200 int N003 ( 3, 4) [001201] ----------- t1201 = * ADD int $361 /--* t1201 int N005 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 N001 ( 1, 1) [001197] ----------- t1197 = LCL_VAR long V22 loc18 u:1 $3c4 N002 ( 1, 1) [001206] ----------- t1206 = LCL_VAR int V71 tmp31 u:1 (last use) $28b /--* t1206 int N003 ( 2, 3) [001207] -c--------- t1207 = * CAST long <- int $3c5 N004 ( 1, 2) [001209] -c--------- t1209 = CNS_INT long 1 $204 /--* t1207 long +--* t1209 long N005 ( 4, 6) [001210] -c--------- t1210 = * BFIZ long /--* t1197 long +--* t1210 long N006 ( 6, 8) [001211] -c--------- t1211 = * LEA(b+(i*1)+0) long /--* t1211 long N007 ( 9, 10) [001212] ---XG------ t1212 = * IND ushort /--* t1212 ushort N009 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 N001 ( 1, 1) [001216] ----------- t1216 = LCL_VAR int V72 tmp32 u:1 (last use) /--* t1216 int N003 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 N001 ( 1, 1) [001215] ----------- t1215 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001219] -c--------- t1219 = CNS_INT int 0 $c0 /--* t1215 int +--* t1219 int N003 ( 3, 4) [001220] CEQ-------N--- * JCMP void ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} [003840] ----------- IL_OFFSET void INLRT @ 0x222[E-] N001 ( 1, 1) [001222] ----------- t1222 = LCL_VAR int V18 loc14 u:5 N002 ( 1, 2) [001223] -c--------- t1223 = CNS_INT int 59 $d1 /--* t1222 int +--* t1223 int N003 ( 3, 4) [001224] N------N-U- * NE void N004 ( 5, 6) [001225] ----------- * JTRUE void $VN.Void ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} [003841] ----------- IL_OFFSET void INLRT @ 0x22B[E-] N001 ( 1, 2) [000081] -c--------- t81 = CNS_INT long 0 $205 /--* t81 long N003 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 [003842] ----------- IL_OFFSET void INLRT @ 0x22F[E-] N001 ( 1, 1) [000084] ----------- t84 = LCL_VAR int V05 loc1 u:2 $286 N002 ( 1, 2) [000085] -c--------- t85 = CNS_INT int 0 $c0 /--* t84 int +--* t85 int N003 ( 3, 4) [000086] J------N--- * GE void $690 N004 ( 5, 6) [000087] ----------- * JTRUE void $VN.Void ------------ BB51 [233..235), preds={BB50} succs={BB52} [003843] ----------- IL_OFFSET void INLRT @ 0x233[E-] N001 ( 1, 1) [001194] ----------- t1194 = LCL_VAR int V04 loc0 u:2 $28a /--* t1194 int N003 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} [003844] ----------- IL_OFFSET void INLRT @ 0x235[E-] N001 ( 1, 1) [000088] ----------- t88 = LCL_VAR int V10 loc6 u:2 $287 N002 ( 1, 2) [000089] -c--------- t89 = CNS_INT int 0 $c0 /--* t88 int +--* t89 int N003 ( 3, 4) [000090] J------N--- * LT void $692 N004 ( 5, 6) [000091] ----------- * JTRUE void $VN.Void ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} [003845] ----------- IL_OFFSET void INLRT @ 0x23A[E-] N001 ( 1, 1) [001180] ----------- t1180 = LCL_VAR int V10 loc6 u:2 (last use) $287 N002 ( 1, 1) [001181] ----------- t1181 = LCL_VAR int V05 loc1 u:3 $28d /--* t1180 int +--* t1181 int N003 ( 3, 3) [001182] N------N-U- * NE void $696 N004 ( 5, 5) [001183] ----------- * JTRUE void $VN.Void ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} [003846] ----------- IL_OFFSET void INLRT @ 0x23F[E-] N001 ( 1, 1) [001187] ----------- t1187 = LCL_VAR int V13 loc9 u:2 (last use) $289 N002 ( 1, 1) [001188] ----------- t1188 = LCL_VAR int V11 loc7 u:3 $288 N003 ( 1, 2) [001189] ----------- t1189 = CNS_INT int 3 $c3 /--* t1188 int +--* t1189 int N004 ( 6, 6) [001190] -c--------- t1190 = * MUL int $697 /--* t1187 int +--* t1190 int N005 ( 8, 8) [001191] ----------- t1191 = * SUB int $698 /--* t1191 int N007 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} [003847] ----------- IL_OFFSET void INLRT @ 0x24A[E-] N001 ( 1, 2) [002615] ----------- t2615 = CNS_INT int 1 $c1 /--* t2615 int N003 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} [003848] ----------- IL_OFFSET void INLRT @ 0x24D[E-] N001 ( 1, 1) [000092] ----------- t92 = LCL_VAR long V17 loc13 u:1 /--* t92 long N002 ( 4, 3) [000093] ---XG------ t93 = * IND ubyte N003 ( 1, 2) [000094] -c--------- t94 = CNS_INT int 0 $c0 /--* t93 ubyte +--* t94 int N004 ( 6, 6) [000095] CEQ---XG--N--- * JCMP void ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} [003849] ----------- IL_OFFSET void INLRT @ 0x252[E-] N001 ( 1, 1) [002618] ----------- t2618 = LCL_VAR byref V01 arg1 u:1 $101 N002 ( 1, 2) [002619] -c--------- t2619 = CNS_INT long 4 $207 /--* t2618 byref +--* t2619 long N003 ( 3, 4) [002620] -----O----- t2620 = * ADD byref $24a /--* t2620 byref N005 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 N001 ( 1, 1) [001131] ----------- t1131 = LCL_VAR byref V69 tmp29 u:1 $24a /--* t1131 byref N002 ( 3, 2) [001132] n---GO----- t1132 = * IND int N003 ( 1, 1) [001133] ----------- t1133 = LCL_VAR int V13 loc9 u:3 (last use) $28e /--* t1132 int +--* t1133 int N004 ( 5, 4) [001134] ----GO----- t1134 = * ADD int N005 ( 1, 1) [001130] ----------- t1130 = LCL_VAR byref V69 tmp29 u:1 (last use) $24a /--* t1130 byref +--* t1134 int [003850] -A--GO----- * STOREIND int [003851] ----------- IL_OFFSET void INLRT @ 0x25E[E-] N001 ( 1, 1) [001137] ----------- t1137 = LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [001138] -c--------- t1138 = CNS_INT int 0 $c0 /--* t1137 int +--* t1138 int N003 ( 3, 4) [001139] CNE-------N--- * JCMP void ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} [003852] ----------- IL_OFFSET void INLRT @ 0x262[E-] N001 ( 1, 1) [001171] ----------- t1171 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1171 byref N003 ( 3, 4) [002623] -c--------- t2623 = * LEA(b+4) byref /--* t2623 byref N004 ( 4, 3) [001172] n---GO----- t1172 = * IND int N005 ( 1, 1) [001173] ----------- t1173 = LCL_VAR int V04 loc0 u:2 $28a /--* t1172 int +--* t1173 int N006 ( 6, 5) [001174] ----GO----- t1174 = * ADD int N007 ( 1, 1) [001175] ----------- t1175 = LCL_VAR int V05 loc1 u:3 $28d /--* t1174 int +--* t1175 int N008 ( 8, 7) [001176] ----GO----- t1176 = * SUB int /--* t1176 int N010 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} [003853] ----------- IL_OFFSET void INLRT @ 0x26E[E-] N001 ( 1, 1) [001141] ----------- t1141 = LCL_VAR int V04 loc0 u:2 $28a /--* t1141 int N003 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} [003854] ----------- IL_OFFSET void INLRT @ 0x271[E-] N001 ( 1, 1) [001145] ----------- t1145 = LCL_VAR int V70 tmp30 u:1 (last use) $291 /--* t1145 int [004213] ----------- t4213 = * PUTARG_REG int REG x1 N002 ( 1, 1) [001148] ----------- t1148 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1148 byref [004214] ----------- t4214 = * PUTARG_REG byref REG x0 N003 ( 2, 8) [002624] H---------- t2624 = CNS_INT(h) long 0x400000000046acb8 ftn $45 /--* t2624 long [004215] ----------- t4215 = * PUTARG_REG long REG x11 N004 ( 1, 2) [001150] ----------- t1150 = CNS_INT int 0 $c0 /--* t1150 int [004216] ----------- t4216 = * PUTARG_REG int REG x2 /--* t4213 int arg2 in x1 +--* t4214 byref arg1 in x0 +--* t4215 long r2r cell in x11 +--* t4216 int arg3 in x2 N005 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void $VN.Void [003855] ----------- IL_OFFSET void INLRT @ 0x27A[E-] N001 ( 1, 1) [001152] ----------- t1152 = LCL_VAR long V17 loc13 u:1 /--* t1152 long N002 ( 4, 3) [001153] ---XG------ t1153 = * IND ubyte N003 ( 1, 2) [001154] -c--------- t1154 = CNS_INT int 0 $c0 /--* t1153 ubyte +--* t1154 int N004 ( 6, 6) [001155] CNE---XG--N--- * JCMP void ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} [003856] ----------- IL_OFFSET void INLRT @ 0x27F[E-] N001 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 $246 /--* t3713 byref [004217] ----------- t4217 = * PUTARG_REG byref REG x0 N002 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] $3ce /--* t2628 long [004218] ----------- t4218 = * PUTARG_REG long REG x1 /--* t4217 byref +--* t4218 long N003 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct $142 N004 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn $43 /--* t2625 long [004219] ----------- t4219 = * PUTARG_REG long REG x11 N005 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 $c2 /--* t1158 int [004220] ----------- t4220 = * PUTARG_REG int REG x2 /--* t2626 struct arg1 x0,x1 +--* t4219 long r2r cell in x11 +--* t4220 int arg2 in x2 N006 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int $2c4 /--* t1159 int N008 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 [003857] ----------- IL_OFFSET void INLRT @ 0x288[E-] N001 ( 1, 1) [001164] ----------- t1164 = LCL_VAR int V16 loc12 u:16 $2c4 N002 ( 1, 1) [001165] ----------- t1165 = LCL_VAR int V15 loc11 u:2 $283 /--* t1164 int +--* t1165 int N003 ( 3, 3) [001166] J------N--- * EQ void $6b6 N004 ( 5, 5) [001167] ----------- * JTRUE void $VN.Void ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} [003858] ----------- IL_OFFSET void INLRT @ 0x28E[E-] N001 ( 1, 1) [001168] ----------- t1168 = LCL_VAR int V16 loc12 u:16 (last use) $2c4 /--* t1168 int N003 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} [003859] ----------- IL_OFFSET void INLRT @ 0x297[E-] N001 ( 1, 1) [000097] ----------- t97 = LCL_VAR byref V01 arg1 u:1 $101 /--* t97 byref N003 ( 3, 4) [002630] -c--------- t2630 = * LEA(b+10) byref /--* t2630 byref N004 ( 5, 4) [000098] n---GO----- t98 = * IND ubyte N005 ( 1, 2) [000099] -c--------- t99 = CNS_INT int 3 $c3 /--* t98 ubyte +--* t99 int N006 ( 7, 7) [000100] J---GO-N--- * EQ void N007 ( 9, 9) [000101] ----GO----- * JTRUE void $301 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} [003860] ----------- IL_OFFSET void INLRT @ 0x2A0[E-] N001 ( 1, 1) [001122] ----------- t1122 = LCL_VAR byref V01 arg1 u:1 $101 /--* t1122 byref N003 ( 3, 4) [002632] -c--------- t2632 = * LEA(b+8) byref N005 ( 1, 2) [001123] -c--------- t1123 = CNS_INT int 0 $c0 /--* t2632 byref +--* t1123 int [003861] -A--GO----- * STOREIND bool ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} [003862] ----------- IL_OFFSET void INLRT @ 0x2A7[E-] N001 ( 1, 1) [000102] ----------- t102 = LCL_VAR byref V01 arg1 u:1 $101 /--* t102 byref N003 ( 3, 4) [002634] -c--------- t2634 = * LEA(b+4) byref N005 ( 1, 2) [000103] -c--------- t103 = CNS_INT int 0 $c0 /--* t2634 byref +--* t103 int [003863] -A--GO----- * STOREIND int ------------ BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} [003864] ----------- IL_OFFSET void INLRT @ 0x2AE[E-] [003865] ----------- IL_OFFSET void INLRT @ 0x2B2[E-] N001 ( 1, 1) [000106] ----------- t106 = LCL_VAR int V06 loc2 u:2 $284 N002 ( 1, 1) [000107] ----------- t107 = LCL_VAR int V05 loc1 u:3 $28d /--* t106 int +--* t107 int N003 ( 3, 3) [000108] Jc-----N--- t108 = * LT int $6b7 N004 ( 1, 1) [000110] ----------- t110 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000111] ----------- t111 = LCL_VAR int V06 loc2 u:2 (last use) $284 /--* t110 int +--* t111 int N006 ( 3, 3) [000112] ----------- t112 = * SUB int $6b8 N007 ( 1, 2) [001118] -c--------- t1118 = CNS_INT int 0 $c0 /--* t108 int +--* t112 int +--* t1118 int N008 ( 8, 9) [003777] ----------- t3777 = * SELECT int /--* t3777 int N010 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 [003866] ----------- IL_OFFSET void INLRT @ 0x2B5[E-] N001 ( 3, 2) [000116] ----------- t116 = LCL_VAR int V44 tmp4 u:1 (last use) $292 /--* t116 int N003 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 [003867] ----------- IL_OFFSET void INLRT @ 0x2B9[E-] [003868] ----------- IL_OFFSET void INLRT @ 0x2BD[E-] N001 ( 1, 1) [000119] ----------- t119 = LCL_VAR int V07 loc3 u:2 $285 N002 ( 1, 1) [000120] ----------- t120 = LCL_VAR int V05 loc1 u:3 $28d /--* t119 int +--* t120 int N003 ( 3, 3) [000121] Jc-----N--- t121 = * GT int $6b9 N004 ( 1, 1) [000123] ----------- t123 = LCL_VAR int V05 loc1 u:3 $28d N005 ( 1, 1) [000124] ----------- t124 = LCL_VAR int V07 loc3 u:2 (last use) $285 /--* t123 int +--* t124 int N006 ( 3, 3) [000125] ----------- t125 = * SUB int $6ba N007 ( 1, 2) [001114] -c--------- t1114 = CNS_INT int 0 $c0 /--* t121 int +--* t125 int +--* t1114 int N008 ( 8, 9) [003774] ----------- t3774 = * SELECT int /--* t3774 int N010 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 [003869] ----------- IL_OFFSET void INLRT @ 0x2C0[E-] N001 ( 3, 2) [000129] ----------- t129 = LCL_VAR int V45 tmp5 u:1 (last use) $293 /--* t129 int N003 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 [003870] ----------- IL_OFFSET void INLRT @ 0x2C4[E-] N001 ( 1, 1) [000132] ----------- t132 = LCL_VAR int V09 loc5 u:2 $4c1 N002 ( 1, 2) [000133] -c--------- t133 = CNS_INT int 0 $c0 /--* t132 int +--* t133 int N003 ( 3, 4) [000134] CEQ-------N--- * JCMP void ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} [003871] ----------- IL_OFFSET void INLRT @ 0x2C8[E-] N001 ( 1, 1) [001108] ----------- t1108 = LCL_VAR int V05 loc1 u:3 $28d /--* t1108 int N003 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 [003872] ----------- IL_OFFSET void INLRT @ 0x2CB[E-] N001 ( 1, 2) [001111] -c--------- t1111 = CNS_INT int 0 $c0 /--* t1111 int N003 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 ------------ BB74 [2D0..2EE), preds={BB66} succs={BB78} [003873] ----------- IL_OFFSET void INLRT @ 0x2D0[E-] [003874] ----------- IL_OFFSET void INLRT @ 0x2D9[E-] N001 ( 1, 1) [000136] ----------- t136 = LCL_VAR byref V01 arg1 u:1 $101 /--* t136 byref N003 ( 3, 4) [002636] -c--------- t2636 = * LEA(b+4) byref /--* t2636 byref N004 ( 4, 3) [000137] n---GO----- t137 = * IND int /--* t137 int N006 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 N007 ( 3, 2) [003684] ----------- t3684 = LCL_VAR int V178 cse7 u:1 N009 ( 1, 1) [000138] ----------- t138 = LCL_VAR int V05 loc1 u:3 $28d /--* t3684 int +--* t138 int N010 ( 13, 10) [000139] Jc--GO-N--- t139 = * GT int N011 ( 3, 2) [003686] ----------- t3686 = LCL_VAR int V178 cse7 u:1 N012 ( 1, 1) [001104] ----------- t1104 = LCL_VAR int V05 loc1 u:3 $28d /--* t139 int +--* t3686 int +--* t1104 int N013 ( 18, 14) [003771] ----GO----- t3771 = * SELECT int /--* t3771 int N015 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 [003875] ----------- IL_OFFSET void INLRT @ 0x2DC[E-] N001 ( 3, 2) [000146] ----------- t146 = LCL_VAR int V46 tmp6 u:1 (last use) $295 /--* t146 int N003 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 [003876] ----------- IL_OFFSET void INLRT @ 0x2E4[E-] N001 ( 3, 2) [003687] ----------- t3687 = LCL_VAR int V178 cse7 u:1 (last use) N002 ( 1, 1) [000151] ----------- t151 = LCL_VAR int V05 loc1 u:3 $28d /--* t3687 int +--* t151 int N003 ( 5, 4) [000152] ----G------ t152 = * SUB int /--* t152 int N005 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 ------------ BB78 [000..30D) -> BB103 (cond), preds={BB73,BB74} succs={BB79,BB103} [003877] ----------- IL_OFFSET void INLRT @ 0x2EE[E-] N001 ( 1, 1) [000155] ----------- t155 = LCL_VAR int V15 loc11 u:2 $283 /--* t155 int N003 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 [003878] ----------- IL_OFFSET void INLRT @ 0x2F2[E-] [003879] ----------- IL_OFFSET void INL09 @ 0x01F[E-] <- INLRT @ ??? N001 ( 3, 3) [001550] ----------- t1550 = LCL_VAR_ADDR long V47 tmp7 $740 /--* t1550 long N003 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 [003880] ----------- IL_OFFSET void INL09 @ 0x026[E-] <- INLRT @ ??? [003881] ----------- IL_OFFSET void INLRT @ 0x2FF[E-] N001 ( 1, 1) [002649] ----------- t2649 = LCL_VAR byref V151 tmp111 u:1 (last use) $24b /--* t2649 byref N003 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 N004 ( 1, 2) [003720] ----------- t3720 = CNS_INT int 4 $c8 /--* t3720 int N006 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 [003882] ----------- IL_OFFSET void INLRT @ 0x303[E-] N001 ( 1, 2) [000175] ----------- t175 = CNS_INT int -1 $c4 /--* t175 int N003 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 [003883] ----------- IL_OFFSET void INLRT @ 0x306[E-] N001 ( 1, 1) [000941] ----------- t941 = LCL_VAR ref V03 arg3 u:1 $180 /--* t941 ref N003 ( 3, 4) [002656] -c--------- t2656 = * LEA(b+56) byref /--* t2656 byref N004 ( 4, 3) [001570] ---XG------ t1570 = * IND ref /--* t1570 ref [004156] -c--------- t4156 = * LEA(b+8) byref /--* t4156 byref N005 ( 6, 5) [000944] ---XG------ t944 = * IND int N006 ( 1, 2) [000945] -c--------- t945 = CNS_INT int 0 $c0 /--* t944 int +--* t945 int N007 ( 11, 8) [000946] -c-XG--N--- t946 = * LE int N008 ( 1, 1) [000178] ----------- t178 = LCL_VAR int V12 loc8 u:3 $4c4 N009 ( 1, 2) [000179] -c--------- t179 = CNS_INT int 0 $c0 /--* t178 int +--* t179 int N010 ( 6, 4) [000180] -c-----N--- t180 = * EQ int $70a /--* t946 int +--* t180 int N011 ( 18, 13) [003732] Jc-XG--N--- * AND void N012 ( 20, 15) [000181] ---XG------ * JTRUE void $VN.Void ------------ BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} [003884] ----------- IL_OFFSET void INLRT @ 0x30D[E-] [003885] ----------- IL_OFFSET void INLRT @ 0x31E[E-] N001 ( 1, 1) [000948] ----------- t948 = LCL_VAR ref V03 arg3 u:1 $180 /--* t948 ref N003 ( 3, 4) [002658] -c--------- t2658 = * LEA(b+8) byref /--* t2658 byref N004 ( 4, 3) [000949] n---GO----- t949 = * IND ref /--* t949 ref N006 ( 4, 3) [000951] DA--GO----- * STORE_LCL_VAR ref V26 loc22 d:1 [003886] ----------- IL_OFFSET void INLRT @ 0x326[E-] N001 ( 1, 2) [000952] -c--------- t952 = CNS_INT int 0 $c0 /--* t952 int N003 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 [003887] ----------- IL_OFFSET void INLRT @ 0x329[E-] N001 ( 1, 2) [000955] -c--------- t955 = CNS_INT int 0 $c0 /--* t955 int N003 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 [003888] ----------- IL_OFFSET void INLRT @ 0x32C[E-] N001 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 /--* t958 ref [004158] -c--------- t4158 = * LEA(b+8) byref /--* t4158 byref N002 ( 3, 3) [000959] ---X------- t959 = * IND int /--* t959 int N004 ( 3, 3) [000961] DA-X------- * STORE_LCL_VAR int V29 loc25 d:1 [003889] ----------- IL_OFFSET void INLRT @ 0x332[E-] N001 ( 1, 1) [000962] ----------- t962 = LCL_VAR int V29 loc25 u:1 N002 ( 1, 2) [000963] -c--------- t963 = CNS_INT int 0 $c0 /--* t962 int +--* t963 int N003 ( 3, 4) [000964] CEQ-------N--- * JCMP void ------------ BB81 [336..33D), preds={BB79} succs={BB82} [003890] ----------- IL_OFFSET void INLRT @ 0x336[E-] N002 ( 1, 1) [002659] ----------- t2659 = LCL_VAR ref V26 loc22 u:1 /--* t2659 ref N004 ( 1, 1) [002667] -c--------- t2667 = * LEA(b+16) byref /--* t2667 byref N006 ( 4, 3) [002671] n---GO----- t2671 = * IND int /--* t2671 int N009 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} [003891] ----------- IL_OFFSET void INLRT @ 0x33D[E-] N001 ( 1, 1) [000966] ----------- t966 = LCL_VAR int V28 loc24 u:2 $298 /--* t966 int N003 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 N001 ( 1, 1) [000969] ----------- t969 = LCL_VAR int V08 loc4 u:1 $297 /--* t969 int N003 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 [003892] ----------- IL_OFFSET void INLRT @ 0x341[E-] N001 ( 1, 1) [000970] ----------- t970 = LCL_VAR int V14 loc10 u:1 $296 N002 ( 1, 2) [000971] -c--------- t971 = CNS_INT int 0 $c0 /--* t970 int +--* t971 int N003 ( 3, 4) [000972] J------N--- * LT void $719 N004 ( 5, 6) [000973] ----------- * JTRUE void $VN.Void ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} N001 ( 3, 2) [000977] ----------- t977 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t977 int N003 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 N001 ( 1, 2) [001091] -c--------- t1091 = CNS_INT int 0 $c0 /--* t1091 int N003 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} N001 ( 3, 2) [000978] ----------- t978 = LCL_VAR int V64 tmp24 u:1 (last use) $297 /--* t978 int N003 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 N001 ( 1, 1) [000979] ----------- t979 = LCL_VAR int V14 loc10 u:1 $296 /--* t979 int N003 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 ------------ BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} N001 ( 3, 2) [000986] ----------- t986 = LCL_VAR int V65 tmp25 u:1 (last use) $297 N002 ( 3, 2) [000987] ----------- t987 = LCL_VAR int V66 tmp26 u:1 (last use) $299 /--* t986 int +--* t987 int N003 ( 7, 5) [000988] ----------- t988 = * ADD int $71a /--* t988 int N005 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 [003893] ----------- IL_OFFSET void INLRT @ 0x350[E-] [003894] ----------- IL_OFFSET void INLRT @ 0x355[E-] N001 ( 1, 1) [000991] ----------- t991 = LCL_VAR int V06 loc2 u:3 $292 N002 ( 3, 2) [000992] ----------- t992 = LCL_VAR int V31 loc27 u:1 $71a /--* t991 int +--* t992 int N003 ( 5, 4) [000993] Jc-----N--- t993 = * GT int $71b N004 ( 1, 1) [000995] ----------- t995 = LCL_VAR int V06 loc2 u:3 $292 N005 ( 3, 2) [001087] ----------- t1087 = LCL_VAR int V31 loc27 u:1 (last use) $71a /--* t993 int +--* t995 int +--* t1087 int N006 ( 10, 8) [003768] ----------- t3768 = * SELECT int /--* t3768 int N008 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 [003895] ----------- IL_OFFSET void INLRT @ 0x359[E-] N001 ( 3, 2) [000999] ----------- t999 = LCL_VAR int V67 tmp27 u:1 (last use) $29a /--* t999 int N003 ( 3, 3) [001001] DA--------- * STORE_LCL_VAR int V32 loc28 d:1 [003896] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] N001 ( 1, 1) [003158] ----------- t3158 = LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [003159] ----------- t3159 = LCL_VAR int V30 loc26 u:1 $298 /--* t3158 int +--* t3159 int N003 ( 3, 3) [003157] J------N--- * LE void $71c N004 ( 5, 5) [003156] ----------- * JTRUE void $VN.Void ------------ BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} [003897] ----------- IL_OFFSET void INLRT @ 0x35E[E-] N001 ( 1, 1) [001006] ----------- t1006 = LCL_VAR int V30 loc26 u:2 $29d N002 ( 1, 2) [001007] -c--------- t1007 = CNS_INT int 0 $c0 /--* t1006 int +--* t1007 int N003 ( 3, 4) [001008] CEQ-------N--- * JCMP void ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} [003898] ----------- IL_OFFSET void INLRT @ 0x362[E-] N001 ( 1, 1) [001010] ----------- t1010 = LCL_VAR int V20 loc16 u:10 (last use) $29b N002 ( 1, 2) [001011] -c--------- t1011 = CNS_INT int 1 $c1 /--* t1010 int +--* t1011 int N003 ( 3, 4) [001012] ----------- t1012 = * ADD int $71f /--* t1012 int N005 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 [003899] ----------- IL_OFFSET void INLRT @ 0x368[E-] N001 ( 1, 1) [001015] ----------- t1015 = LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001574] ----------- t1574 = LCL_VAR int V144 tmp104 u:3 $29c /--* t1015 int +--* t1574 int N003 ( 3, 3) [001020] J------N--- * LT void $720 N004 ( 5, 5) [001021] ----------- * JTRUE void $VN.Void ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} [003900] ----------- IL_OFFSET void INLRT @ 0x373[E-] N001 ( 1, 1) [001578] ----------- t1578 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 2) [001065] -c--------- t1065 = CNS_INT int 1 $c1 /--* t1578 int +--* t1065 int N003 ( 3, 4) [001066] ----------- t1066 = * LSH int $721 /--* t1066 int N004 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int $3cf /--* t1067 long [004221] ----------- t4221 = * PUTARG_REG long REG x0 N005 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn $49 /--* t2672 long [004222] ----------- t4222 = * PUTARG_REG long REG x11 /--* t4221 long arg1 in x0 +--* t4222 long r2r cell in x11 N006 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 $330 /--* t1068 ref N008 ( 20, 18) [001070] DA-XG------ * STORE_LCL_VAR ref V33 loc29 d:1 [003901] ----------- IL_OFFSET void INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] [003902] ----------- IL_OFFSET void INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001 ( 1, 1) [002689] ----------- t2689 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002690] -c--------- t2690 = CNS_INT long 16 Fseq[] $200 /--* t2689 ref +--* t2690 long N003 ( 3, 4) [002691] -----O----- t2691 = * ADD byref $253 /--* t2691 byref N005 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 [003903] ----------- IL_OFFSET void INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001 ( 1, 1) [001607] ----------- t1607 = LCL_VAR ref V33 loc29 u:1 $800 /--* t1607 ref [004160] -c--------- t4160 = * LEA(b+8) byref /--* t4160 byref N002 ( 3, 3) [001608] ---X------- t1608 = * IND int $2cc /--* t1608 int N004 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 N001 ( 1, 1) [002694] ----------- t2694 = LCL_VAR byref V159 tmp119 u:1 (last use) $382 /--* t2694 byref N003 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 N001 ( 1, 1) [001620] ----------- t1620 = LCL_VAR int V144 tmp104 u:3 $29c N002 ( 1, 1) [001647] ----------- t1647 = LCL_VAR int V160 tmp120 u:1 (last use) $2a0 /--* t1620 int +--* t1647 int N003 ( 3, 3) [001628] N------N-U- * GT void $722 N004 ( 5, 5) [001629] ----------- * JTRUE void $VN.Void ------------ BB95 [000..392), preds={BB91} succs={BB100} [003904] ----------- IL_OFFSET void INL17 @ 0x00F[E-] <- INLRT @ ??? N001 ( 1, 1) [001639] ----------- t1639 = LCL_VAR int V144 tmp104 u:3 (last use) $29c /--* t1639 int N002 ( 2, 3) [001640] ---------U- t1640 = * CAST long <- ulong <- uint $3d0 /--* t1640 long N004 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 [003905] ----------- IL_OFFSET void INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? N001 ( 1, 1) [001663] ----------- t1663 = LCL_VAR long V83 tmp43 u:1 (last use) $3d0 N002 ( 1, 2) [001665] -c--------- t1665 = CNS_INT long 2 $20a /--* t1663 long +--* t1665 long N003 ( 3, 4) [001666] ----------- t1666 = * LSH long $3d1 /--* t1666 long [004223] ----------- t4223 = * PUTARG_REG long REG x2 N004 ( 1, 1) [001661] ----------- t1661 = LCL_VAR byref V161 tmp121 u:1 (last use) $382 /--* t1661 byref [004224] ----------- t4224 = * PUTARG_REG byref REG x0 N005 ( 1, 1) [001662] ----------- t1662 = LCL_VAR byref V143 tmp103 u:3 (last use) $381 /--* t1662 byref [004225] ----------- t4225 = * PUTARG_REG byref REG x1 N006 ( 2, 8) [002700] H---------- t2700 = CNS_INT(h) long 0x4000000000420490 ftn $4b /--* t2700 long [004226] ----------- t4226 = * PUTARG_REG long REG x11 /--* t4223 long arg3 in x2 +--* t4224 byref arg1 in x0 +--* t4225 byref arg2 in x1 +--* t4226 long r2r cell in x11 N007 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void $VN.Void [003906] ----------- IL_OFFSET void INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] [003907] ----------- IL_OFFSET void INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001 ( 1, 1) [002718] ----------- t2718 = LCL_VAR ref V33 loc29 u:1 $800 N002 ( 1, 2) [002719] -c--------- t2719 = CNS_INT long 16 Fseq[] $200 /--* t2718 ref +--* t2719 long N003 ( 3, 4) [002720] -----O----- t2720 = * ADD byref $253 /--* t2720 byref N005 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 [003908] ----------- IL_OFFSET void INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 (last use) $800 /--* t1719 ref [004162] -c--------- t4162 = * LEA(b+8) byref /--* t4162 byref N002 ( 3, 3) [001720] ---X------- t1720 = * IND int $2cc /--* t1720 int N004 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 [003909] ----------- IL_OFFSET void INLRT @ 0x391[E-] N001 ( 1, 1) [002723] ----------- t2723 = LCL_VAR byref V163 tmp123 u:1 (last use) $383 /--* t2723 byref N003 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 N004 ( 1, 1) [002726] ----------- t2726 = LCL_VAR int V164 tmp124 u:1 (last use) $2a1 /--* t2726 int N006 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} [003910] ----------- IL_OFFSET void INLRT @ 0x39A[E-] N001 ( 1, 1) [001024] ----------- t1024 = LCL_VAR int V20 loc16 u:11 $71f N002 ( 1, 1) [001028] ----------- t1028 = LCL_VAR int V144 tmp104 u:4 $2a2 /--* t1024 int +--* t1028 int N003 ( 6, 9) [001029] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $334 N004 ( 1, 1) [001033] ----------- t1033 = LCL_VAR byref V143 tmp103 u:4 $384 N005 ( 1, 1) [001025] ----------- t1025 = LCL_VAR int V20 loc16 u:11 $71f /--* t1025 int N006 ( 2, 3) [001030] -c-------U- t1030 = * CAST long <- uint $3d2 N007 ( 1, 2) [001031] -c--------- t1031 = CNS_INT long 2 $20a /--* t1030 long +--* t1031 long N008 ( 4, 6) [001032] -c--------- t1032 = * BFIZ long /--* t1033 byref +--* t1032 long N009 ( 6, 8) [001034] -c--------- t1034 = * LEA(b+(i*1)+0) byref N012 ( 1, 1) [001036] ----------- t1036 = LCL_VAR int V28 loc24 u:3 $29f /--* t1034 byref +--* t1036 int [003911] -A-XGO----- * STOREIND int [003912] ----------- IL_OFFSET void INLRT @ 0x3A6[E-] N001 ( 1, 1) [001039] ----------- t1039 = LCL_VAR int V27 loc23 u:2 $29e N002 ( 1, 1) [001040] ----------- t1040 = LCL_VAR int V29 loc25 u:1 N003 ( 1, 2) [001041] -c--------- t1041 = CNS_INT int -1 $c4 /--* t1040 int +--* t1041 int N004 ( 3, 4) [001042] ----------- t1042 = * ADD int /--* t1039 int +--* t1042 int N005 ( 5, 6) [001043] J------N--- * GE void N006 ( 7, 8) [001044] ----------- * JTRUE void $VN.Void ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} [003913] ----------- IL_OFFSET void INLRT @ 0x3AE[E-] N001 ( 1, 1) [001050] ----------- t1050 = LCL_VAR int V27 loc23 u:2 (last use) $29e N002 ( 1, 2) [001051] -c--------- t1051 = CNS_INT int 1 $c1 /--* t1050 int +--* t1051 int N003 ( 3, 4) [001052] ----------- t1052 = * ADD int $727 /--* t1052 int N005 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 [003914] ----------- IL_OFFSET void INLRT @ 0x3B4[E-] N001 ( 1, 1) [001056] ----------- t1056 = LCL_VAR int V27 loc23 u:4 $727 N002 ( 1, 1) [001055] ----------- t1055 = LCL_VAR ref V26 loc22 u:1 /--* t1055 ref [004164] -c--------- t4164 = * LEA(b+8) byref /--* t4164 byref N003 ( 3, 3) [002732] ---X------- t2732 = * IND int /--* t1056 int +--* t2732 int N004 ( 8, 11) [002733] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N005 ( 1, 1) [002730] ----------- t2730 = LCL_VAR ref V26 loc22 u:1 N006 ( 1, 2) [002737] -c--------- t2737 = CNS_INT long 16 $200 /--* t2730 ref +--* t2737 long N007 ( 3, 4) [002738] ----------- t2738 = * ADD byref N008 ( 1, 1) [002731] ----------- t2731 = LCL_VAR int V27 loc23 u:4 $727 /--* t2731 int N009 ( 2, 3) [002734] -c-------U- t2734 = * CAST long <- uint $3d4 N010 ( 1, 2) [002735] -c-----N--- t2735 = CNS_INT long 2 $20a /--* t2734 long +--* t2735 long N011 ( 4, 6) [002736] -c--------- t2736 = * BFIZ long /--* t2738 byref +--* t2736 long N012 ( 7, 10) [002739] -c--------- t2739 = * LEA(b+(i*1)+0) byref /--* t2739 byref N014 ( 10, 12) [002742] n---GO----- t2742 = * IND int /--* t2742 int N017 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} [003915] ----------- IL_OFFSET void INLRT @ 0x3BB[E-] N001 ( 1, 1) [001045] ----------- t1045 = LCL_VAR int V28 loc24 u:3 (last use) $29f N002 ( 1, 1) [001046] ----------- t1046 = LCL_VAR int V30 loc26 u:3 $2a3 /--* t1045 int +--* t1046 int N003 ( 3, 3) [001047] ----------- t1047 = * ADD int $72b /--* t1047 int N005 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 [003916] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] N001 ( 1, 1) [001002] ----------- t1002 = LCL_VAR int V32 loc28 u:1 $29a N002 ( 1, 1) [001003] ----------- t1003 = LCL_VAR int V28 loc24 u:4 $72b /--* t1002 int +--* t1003 int N003 ( 3, 3) [001004] J------N--- * GT void $72c N004 ( 5, 5) [001005] ----------- * JTRUE void $VN.Void ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB85,BB89,BB102} succs={BB104,BB112} [003917] ----------- IL_OFFSET void INLRT @ 0x3C8[E-] N001 ( 1, 1) [000182] ----------- t182 = LCL_VAR byref V01 arg1 u:1 $101 /--* t182 byref N003 ( 3, 4) [002744] -c--------- t2744 = * LEA(b+8) byref /--* t2744 byref N004 ( 5, 4) [000183] n---GO----- t183 = * IND bool N005 ( 1, 2) [000184] -c--------- t184 = CNS_INT int 0 $c0 /--* t183 bool +--* t184 int N006 ( 10, 7) [000185] -c--GO-N--- t185 = * EQ int N007 ( 1, 1) [000927] ----------- t927 = LCL_VAR int V16 loc12 u:3 $283 N008 ( 1, 2) [000928] -c--------- t928 = CNS_INT int 0 $c0 /--* t927 int +--* t928 int N009 ( 6, 4) [000929] -c-----N--- t929 = * NE int $733 /--* t185 int +--* t929 int N010 ( 17, 12) [003734] Jc--GO-N--- * AND void N011 ( 19, 14) [000186] ----GO----- * JTRUE void $301 ------------ BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} [003918] ----------- IL_OFFSET void INLRT @ 0x3D0[E-] [003919] ----------- IL_OFFSET void INLRT @ 0x3D4[E-] N001 ( 1, 1) [000931] ----------- t931 = LCL_VAR byref V01 arg1 u:1 $101 /--* t931 byref N003 ( 3, 4) [002746] -c--------- t2746 = * LEA(b+4) byref /--* t2746 byref N004 ( 4, 3) [000932] n---GO----- t932 = * IND int N005 ( 1, 2) [000933] -c--------- t933 = CNS_INT int 0 $c0 /--* t932 int +--* t933 int N006 ( 6, 6) [000934] CEQ----GO-N--- * JCMP void ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} [003920] ----------- IL_OFFSET void INLRT @ 0x3DC[E-] N001 ( 1, 1) [000937] ----------- t937 = LCL_VAR ref V03 arg3 u:1 $180 /--* t937 ref N003 ( 3, 4) [002748] -c--------- t2748 = * LEA(b+40) byref /--* t2748 byref N004 ( 4, 3) [001730] ---XG------ t1730 = * IND ref /--* t1730 ref N006 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 [003921] ----------- IL_OFFSET void INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001732] ----------- t1732 = LCL_VAR ref V86 tmp46 u:1 N002 ( 1, 2) [001733] -c--------- t1733 = CNS_INT ref null $VN.Null /--* t1732 ref +--* t1733 ref N003 ( 3, 4) [001734] CEQ-------N--- * JCMP void ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} [003922] ----------- IL_OFFSET void INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [000936] ----------- t936 = LCL_VAR byref V00 arg0 u:1 $100 /--* t936 byref N003 ( 3, 4) [002750] -c--------- t2750 = * LEA(b+8) byref /--* t2750 byref N004 ( 4, 3) [001736] ---XG------ t1736 = * IND int /--* t1736 int N006 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 [003923] ----------- IL_OFFSET void INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001739] ----------- t1739 = LCL_VAR ref V86 tmp46 u:1 /--* t1739 ref [004166] -c--------- t4166 = * LEA(b+8) byref /--* t4166 byref N002 ( 3, 3) [001740] ---X------- t1740 = * IND int N003 ( 1, 2) [001741] -c--------- t1741 = CNS_INT int 1 $c1 /--* t1740 int +--* t1741 int N004 ( 8, 6) [001742] Nc-X---N-U- t1742 = * NE int N005 ( 3, 2) [001747] ----------- t1747 = LCL_VAR int V87 tmp47 u:1 N006 ( 1, 1) [001748] ----------- t1748 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1748 byref N008 ( 3, 4) [002754] -c--------- t2754 = * LEA(b+24) byref /--* t2754 byref N009 ( 4, 3) [001786] n---GO----- t1786 = * IND int /--* t1747 int +--* t1786 int N010 ( 11, 6) [001752] Nc--GO-N-U- t1752 = * GE int /--* t1742 int +--* t1752 int N011 ( 20, 13) [003736] Jc-XGO-N--- * AND void N012 ( 22, 15) [001743] ---XGO----- * JTRUE void ------------ BB108 [3DC..3DD), preds={BB107} succs={BB112} [003924] ----------- IL_OFFSET void INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] [003925] ----------- IL_OFFSET void INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [002758] ----------- t2758 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002759] -c--------- t2759 = CNS_INT long 16 $200 /--* t2758 byref +--* t2759 long N003 ( 3, 4) [002760] -----O----- t2760 = * ADD byref $25c /--* t2760 byref N005 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 [003926] ----------- IL_OFFSET void INL26 @ ??? <- INLRT @ 0x3DC[E-] N001 ( 3, 2) [001756] ----------- t1756 = LCL_VAR int V87 tmp47 u:1 N002 ( 1, 1) [001761] ----------- t1761 = LCL_VAR byref V88 tmp48 u:1 $25c /--* t1761 byref N004 ( 3, 4) [002763] -c--------- t2763 = * LEA(b+8) byref /--* t2763 byref N005 ( 4, 3) [001762] n---GO----- t1762 = * IND int /--* t1756 int +--* t1762 int N006 ( 11, 12) [001763] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001760] ----------- t1760 = LCL_VAR byref V88 tmp48 u:1 (last use) $25c /--* t1760 byref N008 ( 3, 2) [001767] n---GO----- t1767 = * IND byref N009 ( 3, 2) [001757] ----------- t1757 = LCL_VAR int V87 tmp47 u:1 /--* t1757 int N010 ( 4, 4) [001764] -c-------U- t1764 = * CAST long <- uint N011 ( 1, 2) [001765] -c--------- t1765 = CNS_INT long 1 $204 /--* t1764 long +--* t1765 long N012 ( 6, 7) [001766] ----------- t1766 = * BFIZ long /--* t1767 byref +--* t1766 long N013 ( 10, 10) [001768] ----GO-N--- t1768 = * ADD byref N017 ( 1, 1) [002765] ----------- t2765 = LCL_VAR ref V86 tmp46 u:1 (last use) /--* t2765 ref N019 ( 1, 1) [002772] -c--------- t2772 = * LEA(b+12) byref /--* t2772 byref N021 ( 5, 4) [002777] n---GO----- t2777 = * IND ushort /--* t1768 byref +--* t2777 ushort [003927] -A-XGO----- * STOREIND short [003928] ----------- IL_OFFSET void INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] N001 ( 3, 2) [001777] ----------- t1777 = LCL_VAR int V87 tmp47 u:1 (last use) N002 ( 1, 2) [001778] -c--------- t1778 = CNS_INT int 1 $c1 /--* t1777 int +--* t1778 int N003 ( 5, 5) [001779] ----------- t1779 = * ADD int N004 ( 1, 1) [001776] ----------- t1776 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1776 byref N006 ( 3, 4) [002779] -c--------- t2779 = * LEA(b+8) byref /--* t2779 byref +--* t1779 int [003929] -A--GO----- * STOREIND int ------------ BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} [003930] ----------- IL_OFFSET void INLRT @ 0x3E8[E-] N001 ( 1, 2) [002781] -c--------- t2781 = CNS_INT int 0 $c0 /--* t2781 int N003 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 [003931] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] N001 ( 1, 1) [003714] ----------- t3714 = LCL_VAR byref V180 cse9 u:1 (last use) $246 /--* t3714 byref N003 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 [003932] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] N001 ( 1, 1) [001792] ----------- t1792 = LCL_VAR byref V165 tmp125 u:1 $246 /--* t1792 byref N003 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 [003933] ----------- IL_OFFSET void INLRT @ 0x3F3[E-] N001 ( 1, 1) [000197] ----------- t197 = LCL_VAR byref V165 tmp125 u:1 (last use) $246 /--* t197 byref N003 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 N004 ( 1, 1) [002791] ----------- t2791 = LCL_VAR long V169 tmp129 u:1 (last use) $3c4 /--* t2791 long N007 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 [003934] ----------- IL_OFFSET void INLRT @ 0x3F8[E-] N001 ( 1, 1) [000201] ----------- t201 = LCL_VAR long V17 loc13 u:1 /--* t201 long N003 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB258} succs={BB246,BB248} [003935] ----------- IL_OFFSET void INLRT @ 0x7AA[E-] N001 ( 1, 1) [000204] ----------- t204 = LCL_VAR int V16 loc12 u:4 $2ae N002 ( 1, 1) [003707] ----------- t3707 = LCL_VAR int V179 cse8 u:1 $342 /--* t204 int +--* t3707 int N003 ( 3, 3) [000209] J------N--- * GE void $897 N004 ( 5, 5) [000210] ----------- * JTRUE void $VN.Void ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} [003936] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] N001 ( 1, 1) [000243] ----------- t243 = LCL_VAR int V16 loc12 u:4 (last use) $2ae /--* t243 int N003 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 [003937] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] N001 ( 1, 1) [000244] ----------- t244 = LCL_VAR int V49 tmp9 u:1 $2ae N002 ( 1, 2) [000245] -c--------- t245 = CNS_INT int 1 $c1 /--* t244 int +--* t245 int N003 ( 3, 4) [000246] ----------- t246 = * ADD int $898 /--* t246 int N005 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 N001 ( 1, 1) [000242] ----------- t242 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000251] ----------- t251 = LCL_VAR int V49 tmp9 u:1 (last use) $2ae /--* t251 int N003 ( 2, 3) [000252] -c--------- t252 = * CAST long <- int $3db N004 ( 1, 2) [000254] -c--------- t254 = CNS_INT long 1 $204 /--* t252 long +--* t254 long N005 ( 4, 6) [000255] -c--------- t255 = * BFIZ long /--* t242 long +--* t255 long N006 ( 6, 8) [000256] -c--------- t256 = * LEA(b+(i*1)+0) long /--* t256 long N007 ( 9, 10) [000257] ---XG------ t257 = * IND ushort /--* t257 ushort N009 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 N001 ( 1, 1) [000261] ----------- t261 = LCL_VAR int V50 tmp10 u:1 (last use) /--* t261 int N003 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 N001 ( 1, 1) [000260] ----------- t260 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000264] -c--------- t264 = CNS_INT int 0 $c0 /--* t260 int +--* t264 int N003 ( 3, 4) [000265] CEQ-------N--- * JCMP void ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} [003938] ----------- IL_OFFSET void INLRT @ 0x7C8[E-] N001 ( 1, 1) [000267] ----------- t267 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000268] -c--------- t268 = CNS_INT int 59 $d1 /--* t267 int +--* t268 int N003 ( 3, 4) [000269] N------N-U- * NE void N004 ( 5, 6) [000270] ----------- * JTRUE void $VN.Void ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} [003939] ----------- IL_OFFSET void INLRT @ 0x7D1[E-] N001 ( 1, 2) [000212] -c--------- t212 = CNS_INT long 0 $205 /--* t212 long N003 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 [003940] ----------- IL_OFFSET void INLRT @ 0x7D5[E-] N001 ( 1, 1) [000215] ----------- t215 = LCL_VAR byref V01 arg1 u:1 $101 /--* t215 byref N003 ( 3, 4) [003148] -c--------- t3148 = * LEA(b+8) byref /--* t3148 byref N004 ( 5, 4) [000216] n---GO----- t216 = * IND bool N005 ( 1, 2) [000217] -c--------- t217 = CNS_INT int 0 $c0 /--* t216 bool +--* t217 int N006 ( 10, 7) [000218] -c--GO-N--- t218 = * EQ int N007 ( 1, 1) [000221] ----------- t221 = LCL_VAR int V15 loc11 u:2 (last use) $283 N008 ( 1, 2) [000222] -c--------- t222 = CNS_INT int 0 $c0 /--* t221 int +--* t222 int N009 ( 6, 4) [000223] -c-----N--- t223 = * NE int $733 /--* t218 int +--* t223 int N010 ( 17, 12) [003764] Jc--GO-N--- * AND void N011 ( 19, 14) [000219] ----GO----- * JTRUE void $301 ------------ BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} [003941] ----------- IL_OFFSET void INLRT @ 0x7DD[E-] [003942] ----------- IL_OFFSET void INLRT @ 0x7E1[E-] N001 ( 1, 1) [000225] ----------- t225 = LCL_VAR byref V01 arg1 u:1 (last use) $101 /--* t225 byref N003 ( 3, 4) [003150] -c--------- t3150 = * LEA(b+4) byref /--* t3150 byref N004 ( 4, 3) [000226] n---GO----- t226 = * IND int N005 ( 1, 2) [000227] -c--------- t227 = CNS_INT int 0 $c0 /--* t226 int +--* t227 int N006 ( 9, 6) [000228] ----GO-N--- t228 = * NE int N007 ( 1, 1) [000230] ----------- t230 = LCL_VAR byref V00 arg0 u:1 $100 /--* t230 byref N009 ( 3, 4) [003152] -c--------- t3152 = * LEA(b+8) byref /--* t3152 byref N010 ( 4, 3) [002539] ---XG------ t2539 = * IND int N011 ( 1, 2) [000233] -c--------- t233 = CNS_INT int 0 $c0 /--* t2539 int +--* t233 int N012 ( 9, 6) [000234] ---XG--N--- t234 = * LE int /--* t228 int +--* t234 int N013 ( 19, 13) [003766] J--XGO-N--- t3766 = * AND int /--* t3766 int N014 ( 21, 15) [000229] ---XGO----- * JTRUE void $301 ------------ BB251 [7E9..7FF), preds={BB249} succs={BB253} [003943] ----------- IL_OFFSET void INLRT @ 0x7E9[E-] [003944] ----------- IL_OFFSET void INLRT @ 0x7F2[E-] N001 ( 1, 1) [000238] ----------- t238 = LCL_VAR ref V03 arg3 u:1 (last use) $180 /--* t238 ref N003 ( 3, 4) [003155] -c--------- t3155 = * LEA(b+40) byref /--* t3155 byref N004 ( 4, 3) [002541] ---XG------ t2541 = * IND ref /--* t2541 ref [004227] ---XG------ t4227 = * PUTARG_REG ref REG x2 N005 ( 1, 1) [000236] ----------- t236 = LCL_VAR byref V00 arg0 u:1 (last use) $100 /--* t236 byref [004228] ----------- t4228 = * PUTARG_REG byref REG x0 N006 ( 2, 8) [003153] H---------- t3153 = CNS_INT(h) long 0x4000000000540210 ftn $51 /--* t3153 long [004229] ----------- t4229 = * PUTARG_REG long REG x11 N007 ( 1, 2) [000237] ----------- t237 = CNS_INT int 0 $c0 /--* t237 int [004230] ----------- t4230 = * PUTARG_REG int REG x1 /--* t4227 ref arg3 in x2 +--* t4228 byref this in x0 +--* t4229 long r2r cell in x11 +--* t4230 int arg2 in x1 N008 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} [003945] ----------- IL_OFFSET void INLRT @ 0x7FF[E-] N001 ( 0, 0) [000220] ----------- RETURN void $VN.Void ------------ BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} [003946] ----------- IL_OFFSET void INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] N001 ( 1, 1) [001744] ----------- t1744 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1744 byref [004231] ----------- t4231 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001745] ----------- t1745 = LCL_VAR ref V86 tmp46 u:1 (last use) /--* t1745 ref [004232] ----------- t4232 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002780] H---------- t2780 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2780 long [004233] ----------- t4233 = * PUTARG_REG long REG x11 /--* t4231 byref this in x0 +--* t4232 ref arg2 in x1 +--* t4233 long r2r cell in x11 N004 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} [003947] ----------- IL_OFFSET void INLRT @ 0x401[E-] N001 ( 1, 1) [000271] ----------- t271 = LCL_VAR int V14 loc10 u:2 $2ab N002 ( 1, 2) [000272] -c--------- t272 = CNS_INT int 0 $c0 /--* t271 int +--* t272 int N003 ( 3, 4) [000273] J------N--- * LE void $89f N004 ( 5, 6) [000274] ----------- * JTRUE void $VN.Void ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} [003948] ----------- IL_OFFSET void INLRT @ 0x406[E-] N001 ( 1, 1) [000821] ----------- t821 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000822] -c--------- t822 = CNS_INT int 35 $ea /--* t821 int +--* t822 int N003 ( 6, 4) [000823] -c-----N--- t823 = * EQ int N004 ( 1, 1) [000919] ----------- t919 = LCL_VAR int V18 loc14 u:1 N005 ( 1, 2) [000920] ----------- t920 = CNS_INT int 46 $eb /--* t919 int +--* t920 int N006 ( 6, 4) [000921] -c-----N--- t921 = * EQ int /--* t823 int +--* t921 int N007 ( 13, 9) [003738] Jc-----N--- * AND void N008 ( 15, 11) [000824] ----------- * JTRUE void $VN.Void ------------ BB115 [40C..418) -> BB135 (cond), preds={BB114} succs={BB117,BB135} [003949] ----------- IL_OFFSET void INLRT @ 0x40C[E-] [003950] ----------- IL_OFFSET void INLRT @ 0x412[E-] N001 ( 1, 1) [000923] ----------- t923 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000924] -c--------- t924 = CNS_INT int 48 $d8 /--* t923 int +--* t924 int N003 ( 3, 4) [000925] J------N--- * EQ void N004 ( 5, 6) [000926] ----------- * JTRUE void $VN.Void ------------ BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} [003951] ----------- IL_OFFSET void INLRT @ 0x41A[E-] N001 ( 1, 1) [000830] ----------- t830 = LCL_VAR long V36 loc32 u:7 $904 /--* t830 long N002 ( 4, 3) [000831] ---XG------ t831 = * IND ubyte /--* t831 ubyte N004 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 N005 ( 1, 1) [003679] ----------- t3679 = LCL_VAR int V177 cse6 u:1 N007 ( 1, 2) [000832] -c--------- t832 = CNS_INT int 0 $c0 /--* t3679 int +--* t832 int N008 ( 7, 7) [000833] CNE---XG--N--- * JCMP void ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} N001 ( 1, 2) [000912] ----------- t912 = CNS_INT int 48 $d8 /--* t912 int N003 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 ------------ BB120 [424..42C), preds={BB118} succs={BB121} N001 ( 1, 1) [000840] ----------- t840 = LCL_VAR long V36 loc32 u:7 (last use) $904 /--* t840 long N003 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 N001 ( 1, 1) [000841] ----------- t841 = LCL_VAR long V61 tmp21 u:1 (last use) $904 N002 ( 1, 2) [000843] -c--------- t843 = CNS_INT long 1 $204 /--* t841 long +--* t843 long N003 ( 3, 4) [000844] ----------- t844 = * ADD long $adc /--* t844 long N005 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 N001 ( 1, 1) [003681] ----------- t3681 = LCL_VAR int V177 cse6 u:1 (last use) /--* t3681 int N003 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} N001 ( 1, 1) [000858] ----------- t858 = LCL_VAR int V63 tmp23 u:1 (last use) $b16 /--* t858 int N002 ( 2, 3) [001796] ----------- t1796 = * CAST int <- ushort <- int $c75 /--* t1796 int N004 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 [003952] ----------- IL_OFFSET void INL29 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000857] ----------- t857 = LCL_VAR byref V00 arg0 u:1 $100 /--* t857 byref N003 ( 3, 4) [002795] -c--------- t2795 = * LEA(b+8) byref /--* t2795 byref N004 ( 4, 3) [001797] ---XG------ t1797 = * IND int /--* t1797 int N006 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 [003953] ----------- IL_OFFSET void INL29 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [001800] ----------- t1800 = LCL_VAR int V91 tmp51 u:1 N002 ( 1, 1) [001801] ----------- t1801 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1801 byref N004 ( 3, 4) [002799] -c--------- t2799 = * LEA(b+24) byref /--* t2799 byref N005 ( 4, 3) [001839] n---GO----- t1839 = * IND int /--* t1800 int +--* t1839 int N006 ( 6, 5) [001805] N---GO-N-U- * GE void N007 ( 8, 7) [001806] ----GO----- * JTRUE void $845 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} [003954] ----------- IL_OFFSET void INL29 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [002803] ----------- t2803 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002804] -c--------- t2804 = CNS_INT long 16 $200 /--* t2803 byref +--* t2804 long N003 ( 3, 4) [002805] -----O----- t2805 = * ADD byref $25c /--* t2805 byref N005 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 N001 ( 1, 1) [001812] ----------- t1812 = LCL_VAR int V91 tmp51 u:1 N002 ( 1, 1) [001817] ----------- t1817 = LCL_VAR byref V93 tmp53 u:1 $25c /--* t1817 byref N004 ( 3, 4) [002808] -c--------- t2808 = * LEA(b+8) byref /--* t2808 byref N005 ( 4, 3) [001818] n---GO----- t1818 = * IND int /--* t1812 int +--* t1818 int N006 ( 9, 11) [001819] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001816] ----------- t1816 = LCL_VAR byref V93 tmp53 u:1 (last use) $25c /--* t1816 byref N008 ( 3, 2) [001823] n---GO----- t1823 = * IND byref N009 ( 1, 1) [001813] ----------- t1813 = LCL_VAR int V91 tmp51 u:1 /--* t1813 int N010 ( 2, 3) [001820] -c-------U- t1820 = * CAST long <- uint N011 ( 1, 2) [001821] -c--------- t1821 = CNS_INT long 1 $204 /--* t1820 long +--* t1821 long N012 ( 4, 6) [001822] -c--------- t1822 = * BFIZ long /--* t1823 byref +--* t1822 long N013 ( 8, 9) [001824] -c--------- t1824 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [001826] ----------- t1826 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 /--* t1824 byref +--* t1826 int [003955] -A-XGO----- * STOREIND short [003956] ----------- IL_OFFSET void INL29 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [001830] ----------- t1830 = LCL_VAR int V91 tmp51 u:1 (last use) N002 ( 1, 2) [001831] -c--------- t1831 = CNS_INT int 1 $c1 /--* t1830 int +--* t1831 int N003 ( 3, 4) [001832] ----------- t1832 = * ADD int N004 ( 1, 1) [001829] ----------- t1829 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1829 byref N006 ( 3, 4) [002811] -c--------- t2811 = * LEA(b+8) byref /--* t2811 byref +--* t1832 int [003957] -A--GO----- * STOREIND int ------------ BB123 [000..000), preds={BB121} succs={BB124} [003958] ----------- IL_OFFSET void INL29 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [001807] ----------- t1807 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1807 byref [004234] ----------- t4234 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001808] ----------- t1808 = LCL_VAR int V92 tmp52 u:1 (last use) $c75 /--* t1808 int [004235] ----------- t4235 = * PUTARG_REG int REG x1 N003 ( 2, 8) [002812] H---------- t2812 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2812 long [004236] ----------- t4236 = * PUTARG_REG long REG x11 /--* t4234 byref this in x0 +--* t4235 int arg2 in x1 +--* t4236 long r2r cell in x11 N004 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} [003959] ----------- IL_OFFSET void INLRT @ 0x431[E-] N001 ( 1, 1) [000860] ----------- t860 = LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000861] -c--------- t861 = CNS_INT int 0 $c0 /--* t860 int +--* t861 int N003 ( 6, 4) [000862] -c-----N--- t862 = * EQ int $70a N004 ( 1, 1) [000874] ----------- t874 = LCL_VAR int V08 loc4 u:5 $b15 N005 ( 1, 2) [000875] -c--------- t875 = CNS_INT int 1 $c1 /--* t874 int +--* t875 int N006 ( 6, 4) [000876] -c-----N--- t876 = * LE int $d03 /--* t862 int +--* t876 int N007 ( 13, 9) [003740] Jc-----N--- * AND void N008 ( 15, 11) [000863] ----------- * JTRUE void $VN.Void ------------ BB125 [435..43F) -> BB134 (cond), preds={BB124} succs={BB127,BB134} [003960] ----------- IL_OFFSET void INLRT @ 0x435[E-] [003961] ----------- IL_OFFSET void INLRT @ 0x43A[E-] N001 ( 1, 1) [000885] ----------- t885 = LCL_VAR int V20 loc16 u:7 $b13 N002 ( 1, 1) [000889] ----------- t889 = LCL_VAR int V144 tmp104 u:2 $2a6 /--* t885 int +--* t889 int N003 ( 6, 9) [000890] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $c31 N004 ( 1, 1) [000894] ----------- t894 = LCL_VAR byref V143 tmp103 u:2 $385 N005 ( 1, 1) [000886] ----------- t886 = LCL_VAR int V20 loc16 u:7 $b13 /--* t886 int N006 ( 2, 3) [000891] -c-------U- t891 = * CAST long <- uint $ae2 N007 ( 1, 2) [000892] -c--------- t892 = CNS_INT long 2 $20a /--* t891 long +--* t892 long N008 ( 4, 6) [000893] -c--------- t893 = * BFIZ long /--* t894 byref +--* t893 long N009 ( 6, 8) [000895] -c--------- t895 = * LEA(b+(i*1)+0) byref /--* t895 byref N010 ( 8, 9) [002813] ---XGO----- t2813 = * IND int N012 ( 1, 2) [000898] -c--------- t898 = CNS_INT int 1 $c1 /--* t2813 int +--* t898 int N013 ( 16, 21) [000899] ---XGO----- t899 = * ADD int N014 ( 1, 1) [000882] ----------- t882 = LCL_VAR int V08 loc4 u:5 $b15 /--* t899 int +--* t882 int N015 ( 21, 23) [000900] Nc-XGO-N-U- t900 = * NE int N016 ( 1, 1) [000878] ----------- t878 = LCL_VAR int V20 loc16 u:7 $b13 N017 ( 1, 2) [000879] -c--------- t879 = CNS_INT int 0 $c0 /--* t878 int +--* t879 int N018 ( 6, 4) [000880] -c-----N--- t880 = * LT int $d04 /--* t900 int +--* t880 int N019 ( 28, 28) [003742] Jc-XGO-N--- * AND void N020 ( 30, 30) [000881] ---XGO----- * JTRUE void $VN.Void ------------ BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} [003962] ----------- IL_OFFSET void INLRT @ 0x43F[E-] [003963] ----------- IL_OFFSET void INLRT @ 0x44F[E-] N001 ( 1, 1) [000903] ----------- t903 = LCL_VAR ref V03 arg3 u:1 $180 /--* t903 ref N003 ( 3, 4) [002815] -c--------- t2815 = * LEA(b+56) byref /--* t2815 byref N004 ( 4, 3) [001843] ---XG------ t1843 = * IND ref /--* t1843 ref N006 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 [003964] ----------- IL_OFFSET void INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001845] ----------- t1845 = LCL_VAR ref V95 tmp55 u:1 N002 ( 1, 2) [001846] -c--------- t1846 = CNS_INT ref null $VN.Null /--* t1845 ref +--* t1846 ref N003 ( 3, 4) [001847] CEQ-------N--- * JCMP void ------------ BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} [003965] ----------- IL_OFFSET void INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [000902] ----------- t902 = LCL_VAR byref V00 arg0 u:1 $100 /--* t902 byref N003 ( 3, 4) [002817] -c--------- t2817 = * LEA(b+8) byref /--* t2817 byref N004 ( 4, 3) [001849] n---GO----- t1849 = * IND int /--* t1849 int N006 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 [003966] ----------- IL_OFFSET void INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 /--* t1852 ref [004168] -c--------- t4168 = * LEA(b+8) byref /--* t4168 byref N002 ( 3, 3) [001853] ---X------- t1853 = * IND int /--* t1853 int N004 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 N005 ( 1, 1) [003717] ----------- t3717 = LCL_VAR int V181 cse10 u:1 N007 ( 1, 2) [001854] -c--------- t1854 = CNS_INT int 1 $c1 /--* t3717 int +--* t1854 int N008 ( 9, 7) [001855] Nc-X---N-U- t1855 = * NE int N009 ( 1, 1) [001860] ----------- t1860 = LCL_VAR int V96 tmp56 u:1 N010 ( 1, 1) [001861] ----------- t1861 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1861 byref N012 ( 3, 4) [002821] -c--------- t2821 = * LEA(b+24) byref /--* t2821 byref N013 ( 4, 3) [001899] n---GO----- t1899 = * IND int /--* t1860 int +--* t1899 int N014 ( 9, 5) [001865] Nc--GO-N-U- t1865 = * GE int /--* t1855 int +--* t1865 int N015 ( 19, 13) [003744] Jc-XGO-N--- * AND void N016 ( 21, 15) [001856] ---XGO----- * JTRUE void ------------ BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} [003967] ----------- IL_OFFSET void INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] [003968] ----------- IL_OFFSET void INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [002825] ----------- t2825 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002826] -c--------- t2826 = CNS_INT long 16 $200 /--* t2825 byref +--* t2826 long N003 ( 3, 4) [002827] -----O----- t2827 = * ADD byref $25c /--* t2827 byref N005 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 [003969] ----------- IL_OFFSET void INL32 @ ??? <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001869] ----------- t1869 = LCL_VAR int V96 tmp56 u:1 N002 ( 1, 1) [001874] ----------- t1874 = LCL_VAR byref V97 tmp57 u:1 $25c /--* t1874 byref N004 ( 3, 4) [002830] -c--------- t2830 = * LEA(b+8) byref /--* t2830 byref N005 ( 4, 3) [001875] n---GO----- t1875 = * IND int /--* t1869 int +--* t1875 int N006 ( 9, 11) [001876] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001873] ----------- t1873 = LCL_VAR byref V97 tmp57 u:1 (last use) $25c /--* t1873 byref N008 ( 3, 2) [001880] n---GO----- t1880 = * IND byref N009 ( 1, 1) [001870] ----------- t1870 = LCL_VAR int V96 tmp56 u:1 /--* t1870 int N010 ( 2, 3) [001877] -c-------U- t1877 = * CAST long <- uint N011 ( 1, 2) [001878] -c--------- t1878 = CNS_INT long 1 $204 /--* t1877 long +--* t1878 long N012 ( 4, 6) [001879] ----------- t1879 = * BFIZ long /--* t1880 byref +--* t1879 long N013 ( 8, 9) [001881] ----GO-N--- t1881 = * ADD byref N016 ( 1, 2) [001884] -c--------- t1884 = CNS_INT int 0 $c0 N017 ( 1, 1) [003719] ----------- t3719 = LCL_VAR int V181 cse10 u:1 (last use) /--* t1884 int +--* t3719 int N018 ( 6, 10) [002835] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N019 ( 1, 1) [002832] ----------- t2832 = LCL_VAR ref V95 tmp55 u:1 (last use) /--* t2832 ref N021 ( 1, 1) [002839] -c--------- t2839 = * LEA(b+12) byref /--* t2839 byref N023 ( 5, 4) [002844] n---GO----- t2844 = * IND ushort /--* t1881 byref +--* t2844 ushort [003970] -A-XGO----- * STOREIND short [003971] ----------- IL_OFFSET void INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001890] ----------- t1890 = LCL_VAR int V96 tmp56 u:1 (last use) N002 ( 1, 2) [001891] -c--------- t1891 = CNS_INT int 1 $c1 /--* t1890 int +--* t1891 int N003 ( 3, 4) [001892] ----------- t1892 = * ADD int N004 ( 1, 1) [001889] ----------- t1889 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1889 byref N006 ( 3, 4) [002846] -c--------- t2846 = * LEA(b+8) byref /--* t2846 byref +--* t1892 int [003972] -A--GO----- * STOREIND int ------------ BB132 [44F..450), preds={BB129} succs={BB133} [003973] ----------- IL_OFFSET void INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] N001 ( 1, 1) [001857] ----------- t1857 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1857 byref [004237] ----------- t4237 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001858] ----------- t1858 = LCL_VAR ref V95 tmp55 u:1 (last use) /--* t1858 ref [004238] ----------- t4238 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002847] H---------- t2847 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2847 long [004239] ----------- t4239 = * PUTARG_REG long REG x11 /--* t4237 byref this in x0 +--* t4238 ref arg2 in x1 +--* t4239 long r2r cell in x11 N004 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} [003974] ----------- IL_OFFSET void INLRT @ 0x45B[E-] N001 ( 1, 1) [000907] ----------- t907 = LCL_VAR int V20 loc16 u:7 (last use) $b13 N002 ( 1, 2) [000908] -c--------- t908 = CNS_INT int -1 $c4 /--* t907 int +--* t908 int N003 ( 3, 4) [000909] ----------- t909 = * ADD int $d27 /--* t909 int N005 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 ------------ BB134 [461..46D), preds={BB124,BB125,BB133} succs={BB135} [003975] ----------- IL_OFFSET void INLRT @ 0x461[E-] N001 ( 1, 1) [000864] ----------- t864 = LCL_VAR int V08 loc4 u:5 (last use) $b15 N002 ( 1, 2) [000865] -c--------- t865 = CNS_INT int -1 $c4 /--* t864 int +--* t865 int N003 ( 3, 4) [000866] ----------- t866 = * ADD int $d29 /--* t866 int N005 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 [003976] ----------- IL_OFFSET void INLRT @ 0x467[E-] N001 ( 1, 1) [000869] ----------- t869 = LCL_VAR int V14 loc10 u:6 (last use) $b14 N002 ( 1, 2) [000870] -c--------- t870 = CNS_INT int -1 $c4 /--* t869 int +--* t870 int N003 ( 3, 4) [000871] ----------- t871 = * ADD int $d2a /--* t871 int N005 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB134} succs={BB136,BB118} [003977] ----------- IL_OFFSET void INLRT @ 0x46D[E-] N001 ( 1, 1) [000825] ----------- t825 = LCL_VAR int V14 loc10 u:6 $b14 N002 ( 1, 2) [000826] -c--------- t826 = CNS_INT int 0 $c0 /--* t825 int +--* t826 int N003 ( 3, 4) [000827] J------N--- * GT void $c6e N004 ( 5, 6) [000828] ----------- * JTRUE void $VN.Void ------------ BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} [003978] ----------- IL_OFFSET void INLRT @ 0x472[E-] N001 ( 1, 1) [000275] ----------- t275 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000276] -c--------- t276 = CNS_INT int 69 $d2 /--* t275 int +--* t276 int N003 ( 3, 4) [000277] N------N-U- * GT void N004 ( 5, 6) [000278] ----------- * JTRUE void $VN.Void ------------ BB137 [478..478) -> BB138 (cond), preds={BB136} succs={BB257,BB138} [003979] ----------- IL_OFFSET void INLRT @ 0x478[E-] N001 ( 1, 1) [000593] ----------- t593 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000594] -c--------- t594 = CNS_INT int -34 $d6 /--* t593 int +--* t594 int N003 ( 3, 4) [000595] ----------- t595 = * ADD int /--* t595 int [004241] DA--------- * STORE_LCL_VAR int V184 rat2 N001 ( 3, 2) [004243] ----------- t4243 = LCL_VAR int V184 rat2 N002 ( 1, 2) [004244] -c--------- t4244 = CNS_INT int 5 /--* t4243 int +--* t4244 int N003 ( 8, 5) [004245] ---------U- * GT void N004 ( 10, 7) [004246] ----------- * JTRUE void ------------ BB257 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194 (switch), preds={BB137} succs={BB145,BB186,BB194,BB242} [004247] ----------- t4247 = LCL_VAR int V184 rat2 (last use) /--* t4247 int [004248] ---------U- t4248 = * CAST long <- ulong <- uint [004249] ----------- t4249 = JMPTABLE long /--* t4248 long +--* t4249 long [004250] ----------- * SWITCH_TABLE void ------------ BB138 [49A..49A) -> BB139 (cond), preds={BB137} succs={BB258,BB139} [003980] ----------- IL_OFFSET void INLRT @ 0x49A[E-] N001 ( 1, 1) [000597] ----------- t597 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000598] -c--------- t598 = CNS_INT int -44 $d7 /--* t597 int +--* t598 int N003 ( 3, 4) [000599] ----------- t599 = * ADD int /--* t599 int [004252] DA--------- * STORE_LCL_VAR int V185 rat3 N001 ( 3, 2) [004254] ----------- t4254 = LCL_VAR int V185 rat3 N002 ( 1, 2) [004255] -c--------- t4255 = CNS_INT int 4 /--* t4254 int +--* t4255 int N003 ( 8, 5) [004256] ---------U- * GT void N004 ( 10, 7) [004257] ----------- * JTRUE void ------------ BB258 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145 (switch), preds={BB138} succs={BB145,BB171,BB242,BB245} [004258] ----------- t4258 = LCL_VAR int V185 rat3 (last use) /--* t4258 int [004259] ---------U- t4259 = * CAST long <- ulong <- uint [004260] ----------- t4260 = JMPTABLE long /--* t4259 long +--* t4260 long [004261] ----------- * SWITCH_TABLE void ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} [003981] ----------- IL_OFFSET void INLRT @ 0x4B8[E-] N001 ( 1, 1) [000601] ----------- t601 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000602] -c--------- t602 = CNS_INT int 69 $d2 /--* t601 int +--* t602 int N003 ( 3, 4) [000603] J------N--- * EQ void N004 ( 5, 6) [000604] ----------- * JTRUE void $VN.Void ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} [003982] ----------- IL_OFFSET void INLRT @ 0x4C6[E-] N001 ( 1, 1) [000279] ----------- t279 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000280] -c--------- t280 = CNS_INT int 92 $d3 /--* t279 int +--* t280 int N003 ( 3, 4) [000281] J------N--- * EQ void N004 ( 5, 6) [000282] ----------- * JTRUE void $VN.Void ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} [003983] ----------- IL_OFFSET void INLRT @ 0x4CF[E-] N001 ( 1, 1) [000319] ----------- t319 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 2) [000320] -c--------- t320 = CNS_INT int 101 $d4 /--* t319 int +--* t320 int N003 ( 3, 4) [000321] J------N--- * EQ void N004 ( 5, 6) [000322] ----------- * JTRUE void $VN.Void ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} [003984] ----------- IL_OFFSET void INLRT @ 0x4D8[E-] N001 ( 1, 1) [000581] ----------- t581 = LCL_VAR int V18 loc14 u:1 N002 ( 1, 4) [000582] ----------- t582 = CNS_INT int 0x2030 $d5 /--* t581 int +--* t582 int N003 ( 3, 6) [000583] J------N--- * NE void N004 ( 5, 8) [000584] ----------- * JTRUE void $VN.Void ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} [003985] ----------- IL_OFFSET void INLRT @ 0x598[E-] N001 ( 1, 1) [000586] ----------- t586 = LCL_VAR ref V03 arg3 u:1 $180 /--* t586 ref N003 ( 3, 4) [002849] -c--------- t2849 = * LEA(b+136) byref /--* t2849 byref N004 ( 4, 3) [002066] ---XG------ t2066 = * IND ref /--* t2066 ref N006 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB257,BB258} succs={BB146,BB150} [003986] ----------- IL_OFFSET void INLRT @ 0x4E9[E-] N001 ( 1, 1) [000639] ----------- t639 = LCL_VAR int V14 loc10 u:3 $2b4 N002 ( 1, 2) [000640] -c--------- t640 = CNS_INT int 0 $c0 /--* t639 int +--* t640 int N003 ( 3, 4) [000641] J------N--- * GE void $9ff N004 ( 5, 6) [000642] ----------- * JTRUE void $VN.Void ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} [003987] ----------- IL_OFFSET void INLRT @ 0x4EE[E-] N001 ( 1, 1) [000731] ----------- t731 = LCL_VAR int V14 loc10 u:3 (last use) $2b4 N002 ( 1, 2) [000732] -c--------- t732 = CNS_INT int 1 $c1 /--* t731 int +--* t732 int N003 ( 3, 4) [000733] ----------- t733 = * ADD int $a88 /--* t733 int N005 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 [003988] ----------- IL_OFFSET void INLRT @ 0x4F4[E-] N001 ( 1, 1) [000736] ----------- t736 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000737] ----------- t737 = LCL_VAR int V06 loc2 u:3 $292 /--* t736 int +--* t737 int N003 ( 3, 3) [000738] J------N--- * LE void $a89 N004 ( 5, 5) [000739] ----------- * JTRUE void $VN.Void ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} [003989] ----------- IL_OFFSET void INLRT @ 0x4F9[E-] N001 ( 1, 2) [000747] -c--------- t747 = CNS_INT int 0 $c0 /--* t747 int N003 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} [003990] ----------- IL_OFFSET void INLRT @ 0x4FC[E-] N001 ( 1, 2) [000740] ----------- t740 = CNS_INT int 48 $d8 /--* t740 int N003 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} N001 ( 1, 1) [000744] ----------- t744 = LCL_VAR int V58 tmp18 u:1 (last use) $2bd /--* t744 int N002 ( 2, 3) [002850] ----------- t2850 = * CAST int <- ushort <- int $a8a /--* t2850 int N004 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} [003991] ----------- IL_OFFSET void INLRT @ 0x502[E-] N001 ( 1, 1) [000643] ----------- t643 = LCL_VAR long V36 loc32 u:3 $901 /--* t643 long N002 ( 4, 3) [000644] ---XG------ t644 = * IND ubyte N003 ( 1, 2) [000645] -c--------- t645 = CNS_INT int 0 $c0 /--* t644 ubyte +--* t645 int N004 ( 6, 6) [000646] CNE---XG--N--- * JCMP void ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} [003992] ----------- IL_OFFSET void INLRT @ 0x507[E-] N001 ( 1, 1) [000719] ----------- t719 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 1) [000720] ----------- t720 = LCL_VAR int V07 loc3 u:3 $293 /--* t719 int +--* t720 int N003 ( 3, 3) [000721] J------N--- * GT void $a86 N004 ( 5, 5) [000722] ----------- * JTRUE void $VN.Void ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} [003993] ----------- IL_OFFSET void INLRT @ 0x50C[E-] N001 ( 1, 2) [000727] -c--------- t727 = CNS_INT int 0 $c0 /--* t727 int N003 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} [003994] ----------- IL_OFFSET void INLRT @ 0x50F[E-] N001 ( 1, 2) [000723] ----------- t723 = CNS_INT int 48 $d8 /--* t723 int N003 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 ------------ BB154 [513..51B), preds={BB150} succs={BB155} [003995] ----------- IL_OFFSET void INLRT @ 0x513[E-] N001 ( 1, 1) [000648] ----------- t648 = LCL_VAR long V36 loc32 u:3 (last use) $901 /--* t648 long N003 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 [003996] ----------- IL_OFFSET void INLRT @ 0x513[E-] N001 ( 1, 1) [000649] ----------- t649 = LCL_VAR long V56 tmp16 u:1 $901 N002 ( 1, 2) [000651] -c--------- t651 = CNS_INT long 1 $204 /--* t649 long +--* t651 long N003 ( 3, 4) [000652] ----------- t652 = * ADD long $3fb /--* t652 long N005 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 N001 ( 1, 1) [000657] ----------- t657 = LCL_VAR long V56 tmp16 u:1 (last use) $901 /--* t657 long N002 ( 4, 3) [000658] ---XG------ t658 = * IND ubyte /--* t658 ubyte N004 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} N001 ( 1, 1) [000662] ----------- t662 = LCL_VAR int V57 tmp17 u:1 (last use) $2bc /--* t662 int N002 ( 2, 3) [002851] ----------- t2851 = * CAST int <- ushort <- int $a87 /--* t2851 int N004 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} [003997] ----------- IL_OFFSET void INLRT @ 0x51D[E-] N001 ( 1, 1) [000665] ----------- t665 = LCL_VAR int V18 loc14 u:2 $5c9 N002 ( 1, 2) [000666] -c--------- t666 = CNS_INT int 0 $c0 /--* t665 int +--* t666 int N003 ( 3, 4) [000667] CEQ-------N--- * JCMP void ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} [003998] ----------- IL_OFFSET void INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [000674] ----------- t674 = LCL_VAR byref V00 arg0 u:1 $100 /--* t674 byref N003 ( 3, 4) [002853] -c--------- t2853 = * LEA(b+8) byref /--* t2853 byref N004 ( 4, 3) [001903] ---XG------ t1903 = * IND int /--* t1903 int N006 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 [003999] ----------- IL_OFFSET void INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001906] ----------- t1906 = LCL_VAR int V99 tmp59 u:1 N002 ( 1, 1) [001907] ----------- t1907 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1907 byref N004 ( 3, 4) [002857] -c--------- t2857 = * LEA(b+24) byref /--* t2857 byref N005 ( 4, 3) [001942] n---GO----- t1942 = * IND int /--* t1906 int +--* t1942 int N006 ( 6, 5) [001911] N---GO-N-U- * GE void N007 ( 8, 7) [001912] ----GO----- * JTRUE void $845 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} [004000] ----------- IL_OFFSET void INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [002861] ----------- t2861 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002862] -c--------- t2862 = CNS_INT long 16 $200 /--* t2861 byref +--* t2862 long N003 ( 3, 4) [002863] -----O----- t2863 = * ADD byref $25c /--* t2863 byref N005 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 [004001] ----------- IL_OFFSET void INL34 @ ??? <- INLRT @ 0x521[E-] N001 ( 1, 1) [001917] ----------- t1917 = LCL_VAR int V99 tmp59 u:1 N002 ( 1, 1) [001922] ----------- t1922 = LCL_VAR byref V100 tmp60 u:1 $25c /--* t1922 byref N004 ( 3, 4) [002866] -c--------- t2866 = * LEA(b+8) byref /--* t2866 byref N005 ( 4, 3) [001923] n---GO----- t1923 = * IND int /--* t1917 int +--* t1923 int N006 ( 9, 11) [001924] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001921] ----------- t1921 = LCL_VAR byref V100 tmp60 u:1 (last use) $25c /--* t1921 byref N008 ( 3, 2) [001928] n---GO----- t1928 = * IND byref N009 ( 1, 1) [001918] ----------- t1918 = LCL_VAR int V99 tmp59 u:1 /--* t1918 int N010 ( 2, 3) [001925] -c-------U- t1925 = * CAST long <- uint N011 ( 1, 2) [001926] -c--------- t1926 = CNS_INT long 1 $204 /--* t1925 long +--* t1926 long N012 ( 4, 6) [001927] -c--------- t1927 = * BFIZ long /--* t1928 byref +--* t1927 long N013 ( 8, 9) [001929] -c--------- t1929 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [001931] ----------- t1931 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 /--* t1929 byref +--* t1931 int [004002] -A-XGO----- * STOREIND short [004003] ----------- IL_OFFSET void INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001935] ----------- t1935 = LCL_VAR int V99 tmp59 u:1 (last use) N002 ( 1, 2) [001936] -c--------- t1936 = CNS_INT int 1 $c1 /--* t1935 int +--* t1936 int N003 ( 3, 4) [001937] ----------- t1937 = * ADD int N004 ( 1, 1) [001934] ----------- t1934 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1934 byref N006 ( 3, 4) [002869] -c--------- t2869 = * LEA(b+8) byref /--* t2869 byref +--* t1937 int [004004] -A--GO----- * STOREIND int ------------ BB159 [521..522), preds={BB157} succs={BB160} [004005] ----------- IL_OFFSET void INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] N001 ( 1, 1) [001913] ----------- t1913 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1913 byref [004262] ----------- t4262 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000675] ----------- t675 = LCL_VAR int V18 loc14 u:2 (last use) $5c9 /--* t675 int [004263] ----------- t4263 = * PUTARG_REG int REG x1 N003 ( 2, 8) [002870] H---------- t2870 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t2870 long [004264] ----------- t4264 = * PUTARG_REG long REG x11 /--* t4262 byref this in x0 +--* t4263 int arg2 in x1 +--* t4264 long r2r cell in x11 N004 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} [004006] ----------- IL_OFFSET void INLRT @ 0x529[E-] N001 ( 1, 1) [000677] ----------- t677 = LCL_VAR int V12 loc8 u:3 $4c4 N002 ( 1, 2) [000678] -c--------- t678 = CNS_INT int 0 $c0 /--* t677 int +--* t678 int N003 ( 6, 4) [000679] -c-----N--- t679 = * EQ int $70a N004 ( 1, 1) [000681] ----------- t681 = LCL_VAR int V08 loc4 u:3 $2b5 N005 ( 1, 2) [000682] -c--------- t682 = CNS_INT int 1 $c1 /--* t681 int +--* t682 int N006 ( 6, 4) [000683] -c-----N--- t683 = * LE int $a93 /--* t679 int +--* t683 int N007 ( 13, 9) [003746] Jc-----N--- * AND void N008 ( 15, 11) [000680] ----------- * JTRUE void $VN.Void ------------ BB161 [52D..537) -> BB170 (cond), preds={BB160} succs={BB163,BB170} [004007] ----------- IL_OFFSET void INLRT @ 0x52D[E-] [004008] ----------- IL_OFFSET void INLRT @ 0x532[E-] N001 ( 1, 1) [000692] ----------- t692 = LCL_VAR int V20 loc16 u:4 $2b3 N002 ( 1, 1) [000696] ----------- t696 = LCL_VAR int V144 tmp104 u:2 $2a6 /--* t692 int +--* t696 int N003 ( 6, 9) [000697] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void $a34 N004 ( 1, 1) [000701] ----------- t701 = LCL_VAR byref V143 tmp103 u:2 $385 N005 ( 1, 1) [000693] ----------- t693 = LCL_VAR int V20 loc16 u:4 $2b3 /--* t693 int N006 ( 2, 3) [000698] -c-------U- t698 = * CAST long <- uint $ac0 N007 ( 1, 2) [000699] -c--------- t699 = CNS_INT long 2 $20a /--* t698 long +--* t699 long N008 ( 4, 6) [000700] -c--------- t700 = * BFIZ long /--* t701 byref +--* t700 long N009 ( 6, 8) [000702] -c--------- t702 = * LEA(b+(i*1)+0) byref /--* t702 byref N010 ( 8, 9) [002871] ---XGO----- t2871 = * IND int N012 ( 1, 2) [000705] -c--------- t705 = CNS_INT int 1 $c1 /--* t2871 int +--* t705 int N013 ( 16, 21) [000706] ---XGO----- t706 = * ADD int N014 ( 1, 1) [000689] ----------- t689 = LCL_VAR int V08 loc4 u:3 $2b5 /--* t706 int +--* t689 int N015 ( 21, 23) [000707] Nc-XGO-N-U- t707 = * NE int N016 ( 1, 1) [000685] ----------- t685 = LCL_VAR int V20 loc16 u:4 $2b3 N017 ( 1, 2) [000686] -c--------- t686 = CNS_INT int 0 $c0 /--* t685 int +--* t686 int N018 ( 6, 4) [000687] -c-----N--- t687 = * LT int $a94 /--* t707 int +--* t687 int N019 ( 28, 28) [003748] Jc-XGO-N--- * AND void N020 ( 30, 30) [000688] ---XGO----- * JTRUE void $VN.Void ------------ BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} [004009] ----------- IL_OFFSET void INLRT @ 0x537[E-] [004010] ----------- IL_OFFSET void INLRT @ 0x547[E-] N001 ( 1, 1) [000710] ----------- t710 = LCL_VAR ref V03 arg3 u:1 $180 /--* t710 ref N003 ( 3, 4) [002873] -c--------- t2873 = * LEA(b+56) byref /--* t2873 byref N004 ( 4, 3) [001946] ---XG------ t1946 = * IND ref /--* t1946 ref N006 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 [004011] ----------- IL_OFFSET void INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001948] ----------- t1948 = LCL_VAR ref V102 tmp62 u:1 N002 ( 1, 2) [001949] -c--------- t1949 = CNS_INT ref null $VN.Null /--* t1948 ref +--* t1949 ref N003 ( 3, 4) [001950] CEQ-------N--- * JCMP void ------------ BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} [004012] ----------- IL_OFFSET void INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [000709] ----------- t709 = LCL_VAR byref V00 arg0 u:1 $100 /--* t709 byref N003 ( 3, 4) [002875] -c--------- t2875 = * LEA(b+8) byref /--* t2875 byref N004 ( 4, 3) [001952] n---GO----- t1952 = * IND int /--* t1952 int N006 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 [004013] ----------- IL_OFFSET void INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001955] ----------- t1955 = LCL_VAR ref V102 tmp62 u:1 /--* t1955 ref [004170] -c--------- t4170 = * LEA(b+8) byref /--* t4170 byref N002 ( 3, 3) [001956] ---X------- t1956 = * IND int N003 ( 1, 2) [001957] -c--------- t1957 = CNS_INT int 1 $c1 /--* t1956 int +--* t1957 int N004 ( 8, 6) [001958] Nc-X---N-U- t1958 = * NE int N005 ( 1, 1) [001963] ----------- t1963 = LCL_VAR int V103 tmp63 u:1 N006 ( 1, 1) [001964] ----------- t1964 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1964 byref N008 ( 3, 4) [002879] -c--------- t2879 = * LEA(b+24) byref /--* t2879 byref N009 ( 4, 3) [002002] n---GO----- t2002 = * IND int /--* t1963 int +--* t2002 int N010 ( 9, 5) [001968] Nc--GO-N-U- t1968 = * GE int /--* t1958 int +--* t1968 int N011 ( 18, 12) [003750] Jc-XGO-N--- * AND void N012 ( 20, 14) [001959] ---XGO----- * JTRUE void ------------ BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} [004014] ----------- IL_OFFSET void INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] [004015] ----------- IL_OFFSET void INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [002883] ----------- t2883 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002884] -c--------- t2884 = CNS_INT long 16 $200 /--* t2883 byref +--* t2884 long N003 ( 3, 4) [002885] -----O----- t2885 = * ADD byref $25c /--* t2885 byref N005 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 [004016] ----------- IL_OFFSET void INL37 @ ??? <- INLRT @ 0x547[E-] N001 ( 1, 1) [001972] ----------- t1972 = LCL_VAR int V103 tmp63 u:1 N002 ( 1, 1) [001977] ----------- t1977 = LCL_VAR byref V104 tmp64 u:1 $25c /--* t1977 byref N004 ( 3, 4) [002888] -c--------- t2888 = * LEA(b+8) byref /--* t2888 byref N005 ( 4, 3) [001978] n---GO----- t1978 = * IND int /--* t1972 int +--* t1978 int N006 ( 9, 11) [001979] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [001976] ----------- t1976 = LCL_VAR byref V104 tmp64 u:1 (last use) $25c /--* t1976 byref N008 ( 3, 2) [001983] n---GO----- t1983 = * IND byref N009 ( 1, 1) [001973] ----------- t1973 = LCL_VAR int V103 tmp63 u:1 /--* t1973 int N010 ( 2, 3) [001980] -c-------U- t1980 = * CAST long <- uint N011 ( 1, 2) [001981] -c--------- t1981 = CNS_INT long 1 $204 /--* t1980 long +--* t1981 long N012 ( 4, 6) [001982] ----------- t1982 = * BFIZ long /--* t1983 byref +--* t1982 long N013 ( 8, 9) [001984] ----GO-N--- t1984 = * ADD byref N016 ( 1, 2) [001987] -c--------- t1987 = CNS_INT int 0 $c0 N017 ( 1, 1) [001986] ----------- t1986 = LCL_VAR ref V102 tmp62 u:1 /--* t1986 ref [004172] -c--------- t4172 = * LEA(b+8) byref /--* t4172 byref N018 ( 3, 3) [002892] ---X------- t2892 = * IND int /--* t1987 int +--* t2892 int N019 ( 8, 12) [002893] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002890] ----------- t2890 = LCL_VAR ref V102 tmp62 u:1 (last use) /--* t2890 ref N022 ( 1, 1) [002897] -c--------- t2897 = * LEA(b+12) byref /--* t2897 byref N024 ( 5, 4) [002902] n---GO----- t2902 = * IND ushort /--* t1984 byref +--* t2902 ushort [004017] -A-XGO----- * STOREIND short [004018] ----------- IL_OFFSET void INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001993] ----------- t1993 = LCL_VAR int V103 tmp63 u:1 (last use) N002 ( 1, 2) [001994] -c--------- t1994 = CNS_INT int 1 $c1 /--* t1993 int +--* t1994 int N003 ( 3, 4) [001995] ----------- t1995 = * ADD int N004 ( 1, 1) [001992] ----------- t1992 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1992 byref N006 ( 3, 4) [002904] -c--------- t2904 = * LEA(b+8) byref /--* t2904 byref +--* t1995 int [004019] -A--GO----- * STOREIND int ------------ BB168 [547..548), preds={BB165} succs={BB169} [004020] ----------- IL_OFFSET void INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] N001 ( 1, 1) [001960] ----------- t1960 = LCL_VAR byref V00 arg0 u:1 $100 /--* t1960 byref [004265] ----------- t4265 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [001961] ----------- t1961 = LCL_VAR ref V102 tmp62 u:1 (last use) /--* t1961 ref [004266] ----------- t4266 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002905] H---------- t2905 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2905 long [004267] ----------- t4267 = * PUTARG_REG long REG x11 /--* t4265 byref this in x0 +--* t4266 ref arg2 in x1 +--* t4267 long r2r cell in x11 N004 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} [004021] ----------- IL_OFFSET void INLRT @ 0x553[E-] N001 ( 1, 1) [000714] ----------- t714 = LCL_VAR int V20 loc16 u:4 (last use) $2b3 N002 ( 1, 2) [000715] -c--------- t715 = CNS_INT int -1 $c4 /--* t714 int +--* t715 int N003 ( 3, 4) [000716] ----------- t716 = * ADD int $ab7 /--* t716 int N005 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB169} succs={BB245} [004022] ----------- IL_OFFSET void INLRT @ 0x559[E-] N001 ( 1, 1) [000669] ----------- t669 = LCL_VAR int V08 loc4 u:3 (last use) $2b5 N002 ( 1, 2) [000670] -c--------- t670 = CNS_INT int -1 $c4 /--* t669 int +--* t670 int N003 ( 3, 4) [000671] ----------- t671 = * ADD int $ab9 /--* t671 int N005 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 ------------ BB171 [564..571) -> BB245 (cond), preds={BB258} succs={BB172,BB245} [004023] ----------- IL_OFFSET void INLRT @ 0x564[E-] N001 ( 1, 1) [000605] ----------- t605 = LCL_VAR int V08 loc4 u:3 $2b5 N002 ( 1, 2) [000606] -c--------- t606 = CNS_INT int 0 $c0 /--* t605 int +--* t606 int N003 ( 6, 4) [000607] ----------- t607 = * NE int $aba N004 ( 1, 1) [000608] ----------- t608 = LCL_VAR int V21 loc17 u:2 $4c7 /--* t607 int +--* t608 int N005 ( 8, 6) [000609] ----------- t609 = * OR int $abb N006 ( 1, 2) [000610] -c--------- t610 = CNS_INT int 0 $c0 /--* t609 int +--* t610 int N007 ( 10, 9) [000611] CNE-------N--- * JCMP void ------------ BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} [004024] ----------- IL_OFFSET void INLRT @ 0x571[E-] N001 ( 1, 1) [000613] ----------- t613 = LCL_VAR int V07 loc3 u:3 $293 N002 ( 1, 2) [000614] -c--------- t614 = CNS_INT int 0 $c0 /--* t613 int +--* t614 int N003 ( 3, 4) [000615] J------N--- * LT void $abd N004 ( 5, 6) [000616] ----------- * JTRUE void $VN.Void ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} [004025] ----------- IL_OFFSET void INLRT @ 0x575[E-] N001 ( 1, 1) [000625] ----------- t625 = LCL_VAR int V05 loc1 u:3 $28d N002 ( 1, 1) [000626] ----------- t626 = LCL_VAR int V04 loc0 u:2 $28a /--* t625 int +--* t626 int N003 ( 6, 3) [000627] -c-----N--- t627 = * GE int $abe N004 ( 1, 1) [000629] ----------- t629 = LCL_VAR long V36 loc32 u:3 $901 /--* t629 long N005 ( 4, 3) [000630] ---XG------ t630 = * IND ubyte N006 ( 1, 2) [000631] -c--------- t631 = CNS_INT int 0 $c0 /--* t630 ubyte +--* t631 int N007 ( 9, 6) [000632] -c-XG--N--- t632 = * EQ int /--* t627 int +--* t632 int N008 ( 16, 10) [003752] Jc-XG--N--- * AND void N009 ( 18, 12) [000628] ---XG------ * JTRUE void $VN.Void ------------ BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} [004026] ----------- IL_OFFSET void INLRT @ 0x57C[E-] [004027] ----------- IL_OFFSET void INLRT @ 0x584[E-] N001 ( 1, 1) [000618] ----------- t618 = LCL_VAR ref V03 arg3 u:1 $180 /--* t618 ref N003 ( 3, 4) [002907] -c--------- t2907 = * LEA(b+48) byref /--* t2907 byref N004 ( 4, 3) [002006] ---XG------ t2006 = * IND ref /--* t2006 ref N006 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 [004028] ----------- IL_OFFSET void INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002008] ----------- t2008 = LCL_VAR ref V106 tmp66 u:1 N002 ( 1, 2) [002009] -c--------- t2009 = CNS_INT ref null $VN.Null /--* t2008 ref +--* t2009 ref N003 ( 3, 4) [002010] CEQ-------N--- * JCMP void ------------ BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} [004029] ----------- IL_OFFSET void INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [000617] ----------- t617 = LCL_VAR byref V00 arg0 u:1 $100 /--* t617 byref N003 ( 3, 4) [002909] -c--------- t2909 = * LEA(b+8) byref /--* t2909 byref N004 ( 4, 3) [002012] ---XG------ t2012 = * IND int /--* t2012 int N006 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 [004030] ----------- IL_OFFSET void INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002015] ----------- t2015 = LCL_VAR ref V106 tmp66 u:1 /--* t2015 ref [004174] -c--------- t4174 = * LEA(b+8) byref /--* t4174 byref N002 ( 3, 3) [002016] ---X------- t2016 = * IND int N003 ( 1, 2) [002017] -c--------- t2017 = CNS_INT int 1 $c1 /--* t2016 int +--* t2017 int N004 ( 8, 6) [002018] Nc-X---N-U- t2018 = * NE int N005 ( 1, 1) [002023] ----------- t2023 = LCL_VAR int V107 tmp67 u:1 N006 ( 1, 1) [002024] ----------- t2024 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2024 byref N008 ( 3, 4) [002913] -c--------- t2913 = * LEA(b+24) byref /--* t2913 byref N009 ( 4, 3) [002062] n---GO----- t2062 = * IND int /--* t2023 int +--* t2062 int N010 ( 9, 5) [002028] Nc--GO-N-U- t2028 = * GE int /--* t2018 int +--* t2028 int N011 ( 18, 12) [003754] Jc-XGO-N--- * AND void N012 ( 20, 14) [002019] ---XGO----- * JTRUE void ------------ BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} [004031] ----------- IL_OFFSET void INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] [004032] ----------- IL_OFFSET void INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002917] ----------- t2917 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002918] -c--------- t2918 = CNS_INT long 16 $200 /--* t2917 byref +--* t2918 long N003 ( 3, 4) [002919] -----O----- t2919 = * ADD byref $25c /--* t2919 byref N005 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 [004033] ----------- IL_OFFSET void INL40 @ ??? <- INLRT @ 0x584[E-] N001 ( 1, 1) [002032] ----------- t2032 = LCL_VAR int V107 tmp67 u:1 N002 ( 1, 1) [002037] ----------- t2037 = LCL_VAR byref V108 tmp68 u:1 $25c /--* t2037 byref N004 ( 3, 4) [002922] -c--------- t2922 = * LEA(b+8) byref /--* t2922 byref N005 ( 4, 3) [002038] n---GO----- t2038 = * IND int /--* t2032 int +--* t2038 int N006 ( 9, 11) [002039] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002036] ----------- t2036 = LCL_VAR byref V108 tmp68 u:1 (last use) $25c /--* t2036 byref N008 ( 3, 2) [002043] n---GO----- t2043 = * IND byref N009 ( 1, 1) [002033] ----------- t2033 = LCL_VAR int V107 tmp67 u:1 /--* t2033 int N010 ( 2, 3) [002040] -c-------U- t2040 = * CAST long <- uint N011 ( 1, 2) [002041] -c--------- t2041 = CNS_INT long 1 $204 /--* t2040 long +--* t2041 long N012 ( 4, 6) [002042] ----------- t2042 = * BFIZ long /--* t2043 byref +--* t2042 long N013 ( 8, 9) [002044] ----GO-N--- t2044 = * ADD byref N016 ( 1, 2) [002047] -c--------- t2047 = CNS_INT int 0 $c0 N017 ( 1, 1) [002046] ----------- t2046 = LCL_VAR ref V106 tmp66 u:1 /--* t2046 ref [004176] -c--------- t4176 = * LEA(b+8) byref /--* t4176 byref N018 ( 3, 3) [002926] ---X------- t2926 = * IND int /--* t2047 int +--* t2926 int N019 ( 8, 12) [002927] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002924] ----------- t2924 = LCL_VAR ref V106 tmp66 u:1 (last use) /--* t2924 ref N022 ( 1, 1) [002931] -c--------- t2931 = * LEA(b+12) byref /--* t2931 byref N024 ( 5, 4) [002936] n---GO----- t2936 = * IND ushort /--* t2044 byref +--* t2936 ushort [004034] -A-XGO----- * STOREIND short [004035] ----------- IL_OFFSET void INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002053] ----------- t2053 = LCL_VAR int V107 tmp67 u:1 (last use) N002 ( 1, 2) [002054] -c--------- t2054 = CNS_INT int 1 $c1 /--* t2053 int +--* t2054 int N003 ( 3, 4) [002055] ----------- t2055 = * ADD int N004 ( 1, 1) [002052] ----------- t2052 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2052 byref N006 ( 3, 4) [002938] -c--------- t2938 = * LEA(b+8) byref /--* t2938 byref +--* t2055 int [004036] -A--GO----- * STOREIND int ------------ BB179 [584..585), preds={BB176} succs={BB180} [004037] ----------- IL_OFFSET void INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] N001 ( 1, 1) [002020] ----------- t2020 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2020 byref [004268] ----------- t4268 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002021] ----------- t2021 = LCL_VAR ref V106 tmp66 u:1 (last use) /--* t2021 ref [004269] ----------- t4269 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002939] H---------- t2939 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2939 long [004270] ----------- t4270 = * PUTARG_REG long REG x11 /--* t4268 byref this in x0 +--* t4269 ref arg2 in x1 +--* t4270 long r2r cell in x11 N004 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} [004038] ----------- IL_OFFSET void INLRT @ 0x590[E-] N001 ( 1, 2) [002940] ----------- t2940 = CNS_INT int 1 $c1 /--* t2940 int N003 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} [004039] ----------- IL_OFFSET void INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002068] ----------- t2068 = LCL_VAR ref V110 tmp70 u:1 N002 ( 1, 2) [002069] -c--------- t2069 = CNS_INT ref null $VN.Null /--* t2068 ref +--* t2069 ref N003 ( 3, 4) [002070] CEQ-------N--- * JCMP void ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} [004040] ----------- IL_OFFSET void INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [000585] ----------- t585 = LCL_VAR byref V00 arg0 u:1 $100 /--* t585 byref N003 ( 3, 4) [002942] -c--------- t2942 = * LEA(b+8) byref /--* t2942 byref N004 ( 4, 3) [002072] ---XG------ t2072 = * IND int /--* t2072 int N006 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 [004041] ----------- IL_OFFSET void INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002075] ----------- t2075 = LCL_VAR ref V110 tmp70 u:1 /--* t2075 ref [004178] -c--------- t4178 = * LEA(b+8) byref /--* t4178 byref N002 ( 3, 3) [002076] ---X------- t2076 = * IND int N003 ( 1, 2) [002077] -c--------- t2077 = CNS_INT int 1 $c1 /--* t2076 int +--* t2077 int N004 ( 8, 6) [002078] Nc-X---N-U- t2078 = * NE int N005 ( 1, 1) [002083] ----------- t2083 = LCL_VAR int V111 tmp71 u:1 N006 ( 1, 1) [002084] ----------- t2084 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2084 byref N008 ( 3, 4) [002946] -c--------- t2946 = * LEA(b+24) byref /--* t2946 byref N009 ( 4, 3) [002122] n---GO----- t2122 = * IND int /--* t2083 int +--* t2122 int N010 ( 9, 5) [002088] Nc--GO-N-U- t2088 = * GE int /--* t2078 int +--* t2088 int N011 ( 18, 12) [003756] Jc-XGO-N--- * AND void N012 ( 20, 14) [002079] ---XGO----- * JTRUE void ------------ BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} [004042] ----------- IL_OFFSET void INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] [004043] ----------- IL_OFFSET void INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002950] ----------- t2950 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002951] -c--------- t2951 = CNS_INT long 16 $200 /--* t2950 byref +--* t2951 long N003 ( 3, 4) [002952] -----O----- t2952 = * ADD byref $25c /--* t2952 byref N005 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 [004044] ----------- IL_OFFSET void INL43 @ ??? <- INLRT @ 0x598[E-] N001 ( 1, 1) [002092] ----------- t2092 = LCL_VAR int V111 tmp71 u:1 N002 ( 1, 1) [002097] ----------- t2097 = LCL_VAR byref V112 tmp72 u:1 $25c /--* t2097 byref N004 ( 3, 4) [002955] -c--------- t2955 = * LEA(b+8) byref /--* t2955 byref N005 ( 4, 3) [002098] n---GO----- t2098 = * IND int /--* t2092 int +--* t2098 int N006 ( 9, 11) [002099] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002096] ----------- t2096 = LCL_VAR byref V112 tmp72 u:1 (last use) $25c /--* t2096 byref N008 ( 3, 2) [002103] n---GO----- t2103 = * IND byref N009 ( 1, 1) [002093] ----------- t2093 = LCL_VAR int V111 tmp71 u:1 /--* t2093 int N010 ( 2, 3) [002100] -c-------U- t2100 = * CAST long <- uint N011 ( 1, 2) [002101] -c--------- t2101 = CNS_INT long 1 $204 /--* t2100 long +--* t2101 long N012 ( 4, 6) [002102] ----------- t2102 = * BFIZ long /--* t2103 byref +--* t2102 long N013 ( 8, 9) [002104] ----GO-N--- t2104 = * ADD byref N016 ( 1, 2) [002107] -c--------- t2107 = CNS_INT int 0 $c0 N017 ( 1, 1) [002106] ----------- t2106 = LCL_VAR ref V110 tmp70 u:1 /--* t2106 ref [004180] -c--------- t4180 = * LEA(b+8) byref /--* t4180 byref N018 ( 3, 3) [002959] ---X------- t2959 = * IND int /--* t2107 int +--* t2959 int N019 ( 8, 12) [002960] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002957] ----------- t2957 = LCL_VAR ref V110 tmp70 u:1 (last use) /--* t2957 ref N022 ( 1, 1) [002964] -c--------- t2964 = * LEA(b+12) byref /--* t2964 byref N024 ( 5, 4) [002969] n---GO----- t2969 = * IND ushort /--* t2104 byref +--* t2969 ushort [004045] -A-XGO----- * STOREIND short [004046] ----------- IL_OFFSET void INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002113] ----------- t2113 = LCL_VAR int V111 tmp71 u:1 (last use) N002 ( 1, 2) [002114] -c--------- t2114 = CNS_INT int 1 $c1 /--* t2113 int +--* t2114 int N003 ( 3, 4) [002115] ----------- t2115 = * ADD int N004 ( 1, 1) [002112] ----------- t2112 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2112 byref N006 ( 3, 4) [002971] -c--------- t2971 = * LEA(b+8) byref /--* t2971 byref +--* t2115 int [004047] -A--GO----- * STOREIND int ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} [004048] ----------- IL_OFFSET void INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] N001 ( 1, 1) [002080] ----------- t2080 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2080 byref [004271] ----------- t4271 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002081] ----------- t2081 = LCL_VAR ref V110 tmp70 u:1 (last use) /--* t2081 ref [004272] ----------- t4272 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [002972] H---------- t2972 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t2972 long [004273] ----------- t4273 = * PUTARG_REG long REG x11 /--* t4271 byref this in x0 +--* t4272 ref arg2 in x1 +--* t4273 long r2r cell in x11 N004 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB257} succs={BB187,BB245} [004049] ----------- IL_OFFSET void INLRT @ 0x5A9[E-] N001 ( 1, 1) [000635] ----------- t635 = LCL_VAR ref V03 arg3 u:1 $180 /--* t635 ref N003 ( 3, 4) [002974] -c--------- t2974 = * LEA(b+128) byref /--* t2974 byref N004 ( 4, 3) [002126] ---XG------ t2126 = * IND ref /--* t2126 ref N006 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 [004050] ----------- IL_OFFSET void INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002128] ----------- t2128 = LCL_VAR ref V114 tmp74 u:1 N002 ( 1, 2) [002129] -c--------- t2129 = CNS_INT ref null $VN.Null /--* t2128 ref +--* t2129 ref N003 ( 3, 4) [002130] CEQ-------N--- * JCMP void ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} [004051] ----------- IL_OFFSET void INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [000634] ----------- t634 = LCL_VAR byref V00 arg0 u:1 $100 /--* t634 byref N003 ( 3, 4) [002976] -c--------- t2976 = * LEA(b+8) byref /--* t2976 byref N004 ( 4, 3) [002132] ---XG------ t2132 = * IND int /--* t2132 int N006 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 [004052] ----------- IL_OFFSET void INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002135] ----------- t2135 = LCL_VAR ref V114 tmp74 u:1 /--* t2135 ref [004182] -c--------- t4182 = * LEA(b+8) byref /--* t4182 byref N002 ( 3, 3) [002136] ---X------- t2136 = * IND int N003 ( 1, 2) [002137] -c--------- t2137 = CNS_INT int 1 $c1 /--* t2136 int +--* t2137 int N004 ( 8, 6) [002138] Nc-X---N-U- t2138 = * NE int N005 ( 1, 1) [002143] ----------- t2143 = LCL_VAR int V115 tmp75 u:1 N006 ( 1, 1) [002144] ----------- t2144 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2144 byref N008 ( 3, 4) [002980] -c--------- t2980 = * LEA(b+24) byref /--* t2980 byref N009 ( 4, 3) [002182] n---GO----- t2182 = * IND int /--* t2143 int +--* t2182 int N010 ( 9, 5) [002148] Nc--GO-N-U- t2148 = * GE int /--* t2138 int +--* t2148 int N011 ( 18, 12) [003758] Jc-XGO-N--- * AND void N012 ( 20, 14) [002139] ---XGO----- * JTRUE void ------------ BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} [004053] ----------- IL_OFFSET void INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] [004054] ----------- IL_OFFSET void INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002984] ----------- t2984 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [002985] -c--------- t2985 = CNS_INT long 16 $200 /--* t2984 byref +--* t2985 long N003 ( 3, 4) [002986] -----O----- t2986 = * ADD byref $25c /--* t2986 byref N005 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 [004055] ----------- IL_OFFSET void INL46 @ ??? <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002152] ----------- t2152 = LCL_VAR int V115 tmp75 u:1 N002 ( 1, 1) [002157] ----------- t2157 = LCL_VAR byref V116 tmp76 u:1 $25c /--* t2157 byref N004 ( 3, 4) [002989] -c--------- t2989 = * LEA(b+8) byref /--* t2989 byref N005 ( 4, 3) [002158] n---GO----- t2158 = * IND int /--* t2152 int +--* t2158 int N006 ( 9, 11) [002159] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002156] ----------- t2156 = LCL_VAR byref V116 tmp76 u:1 (last use) $25c /--* t2156 byref N008 ( 3, 2) [002163] n---GO----- t2163 = * IND byref N009 ( 1, 1) [002153] ----------- t2153 = LCL_VAR int V115 tmp75 u:1 /--* t2153 int N010 ( 2, 3) [002160] -c-------U- t2160 = * CAST long <- uint N011 ( 1, 2) [002161] -c--------- t2161 = CNS_INT long 1 $204 /--* t2160 long +--* t2161 long N012 ( 4, 6) [002162] ----------- t2162 = * BFIZ long /--* t2163 byref +--* t2162 long N013 ( 8, 9) [002164] ----GO-N--- t2164 = * ADD byref N016 ( 1, 2) [002167] -c--------- t2167 = CNS_INT int 0 $c0 N017 ( 1, 1) [002166] ----------- t2166 = LCL_VAR ref V114 tmp74 u:1 /--* t2166 ref [004184] -c--------- t4184 = * LEA(b+8) byref /--* t4184 byref N018 ( 3, 3) [002993] ---X------- t2993 = * IND int /--* t2167 int +--* t2993 int N019 ( 8, 12) [002994] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void N020 ( 1, 1) [002991] ----------- t2991 = LCL_VAR ref V114 tmp74 u:1 (last use) /--* t2991 ref N022 ( 1, 1) [002998] -c--------- t2998 = * LEA(b+12) byref /--* t2998 byref N024 ( 5, 4) [003003] n---GO----- t3003 = * IND ushort /--* t2164 byref +--* t3003 ushort [004056] -A-XGO----- * STOREIND short [004057] ----------- IL_OFFSET void INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002173] ----------- t2173 = LCL_VAR int V115 tmp75 u:1 (last use) N002 ( 1, 2) [002174] -c--------- t2174 = CNS_INT int 1 $c1 /--* t2173 int +--* t2174 int N003 ( 3, 4) [002175] ----------- t2175 = * ADD int N004 ( 1, 1) [002172] ----------- t2172 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2172 byref N006 ( 3, 4) [003005] -c--------- t3005 = * LEA(b+8) byref /--* t3005 byref +--* t2175 int [004058] -A--GO----- * STOREIND int ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} [004059] ----------- IL_OFFSET void INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] N001 ( 1, 1) [002140] ----------- t2140 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2140 byref [004274] ----------- t4274 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002141] ----------- t2141 = LCL_VAR ref V114 tmp74 u:1 (last use) /--* t2141 ref [004275] ----------- t4275 = * PUTARG_REG ref REG x1 N003 ( 2, 8) [003006] H---------- t3006 = CNS_INT(h) long 0x4000000000431d58 ftn $4f /--* t3006 long [004276] ----------- t4276 = * PUTARG_REG long REG x11 /--* t4274 byref this in x0 +--* t4275 ref arg2 in x1 +--* t4276 long r2r cell in x11 N004 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this $VN.Void ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} [004060] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] N001 ( 1, 1) [000805] ----------- t805 = LCL_VAR int V16 loc12 u:13 (last use) $b04 /--* t805 int N003 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 [004061] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] N001 ( 1, 1) [000806] ----------- t806 = LCL_VAR int V59 tmp19 u:1 (last use) $b04 N002 ( 1, 2) [000807] -c--------- t807 = CNS_INT int 1 $c1 /--* t806 int +--* t807 int N003 ( 3, 4) [000808] ----------- t808 = * ADD int $bad /--* t808 int N005 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 N001 ( 1, 1) [003629] ----------- t3629 = LCL_VAR int V172 cse1 (last use) /--* t3629 int N003 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 [004062] ----------- IL_OFFSET void INL48 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000803] ----------- t803 = LCL_VAR byref V00 arg0 u:1 $100 /--* t803 byref N003 ( 3, 4) [003008] -c--------- t3008 = * LEA(b+8) byref /--* t3008 byref N004 ( 4, 3) [002186] ---XG------ t2186 = * IND int /--* t2186 int N006 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 [004063] ----------- IL_OFFSET void INL48 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002189] ----------- t2189 = LCL_VAR int V118 tmp78 u:1 N002 ( 1, 1) [002190] ----------- t2190 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2190 byref N004 ( 3, 4) [003012] -c--------- t3012 = * LEA(b+24) byref /--* t3012 byref N005 ( 4, 3) [002228] n---GO----- t2228 = * IND int /--* t2189 int +--* t2228 int N006 ( 6, 5) [002194] N---GO-N-U- * GE void N007 ( 8, 7) [002195] ----GO----- * JTRUE void $845 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} [004064] ----------- IL_OFFSET void INL48 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003016] ----------- t3016 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003017] -c--------- t3017 = CNS_INT long 16 $200 /--* t3016 byref +--* t3017 long N003 ( 3, 4) [003018] -----O----- t3018 = * ADD byref $25c /--* t3018 byref N005 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 N001 ( 1, 1) [002201] ----------- t2201 = LCL_VAR int V118 tmp78 u:1 N002 ( 1, 1) [002206] ----------- t2206 = LCL_VAR byref V120 tmp80 u:1 $25c /--* t2206 byref N004 ( 3, 4) [003021] -c--------- t3021 = * LEA(b+8) byref /--* t3021 byref N005 ( 4, 3) [002207] n---GO----- t2207 = * IND int /--* t2201 int +--* t2207 int N006 ( 9, 11) [002208] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002205] ----------- t2205 = LCL_VAR byref V120 tmp80 u:1 (last use) $25c /--* t2205 byref N008 ( 3, 2) [002212] n---GO----- t2212 = * IND byref N009 ( 1, 1) [002202] ----------- t2202 = LCL_VAR int V118 tmp78 u:1 /--* t2202 int N010 ( 2, 3) [002209] -c-------U- t2209 = * CAST long <- uint N011 ( 1, 2) [002210] -c--------- t2210 = CNS_INT long 1 $204 /--* t2209 long +--* t2210 long N012 ( 4, 6) [002211] -c--------- t2211 = * BFIZ long /--* t2212 byref +--* t2211 long N013 ( 8, 9) [002213] -c--------- t2213 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002215] ----------- t2215 = LCL_VAR int V119 tmp79 u:1 (last use) /--* t2213 byref +--* t2215 int [004065] -A-XGO----- * STOREIND short [004066] ----------- IL_OFFSET void INL48 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002219] ----------- t2219 = LCL_VAR int V118 tmp78 u:1 (last use) N002 ( 1, 2) [002220] -c--------- t2220 = CNS_INT int 1 $c1 /--* t2219 int +--* t2220 int N003 ( 3, 4) [002221] ----------- t2221 = * ADD int N004 ( 1, 1) [002218] ----------- t2218 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2218 byref N006 ( 3, 4) [003024] -c--------- t3024 = * LEA(b+8) byref /--* t3024 byref +--* t2221 int [004067] -A--GO----- * STOREIND int ------------ BB193 [000..000), preds={BB191} succs={BB194} [004068] ----------- IL_OFFSET void INL48 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002196] ----------- t2196 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2196 byref [004277] ----------- t4277 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002197] ----------- t2197 = LCL_VAR int V119 tmp79 u:1 (last use) /--* t2197 int [004278] ----------- t4278 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003025] H---------- t3025 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3025 long [004279] ----------- t4279 = * PUTARG_REG long REG x11 /--* t4277 byref this in x0 +--* t4278 int arg2 in x1 +--* t4279 long r2r cell in x11 N004 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB192,BB193,BB257(2)} succs={BB195,BB197} [004069] ----------- IL_OFFSET void INLRT @ 0x5CE[E-] N001 ( 1, 1) [000751] ----------- t751 = LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003699] ----------- t3699 = LCL_VAR int V179 cse8 u:1 $342 /--* t751 int +--* t3699 int N003 ( 3, 3) [000756] J------N--- * GE void $ba4 N004 ( 5, 5) [000757] ----------- * JTRUE void $VN.Void ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} [004070] ----------- IL_OFFSET void INLRT @ 0x5D9[E-] N001 ( 1, 1) [000781] ----------- t781 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000782] ----------- t782 = LCL_VAR int V16 loc12 u:13 $b04 /--* t782 int N003 ( 2, 3) [000783] -c--------- t783 = * CAST long <- int $aca N004 ( 1, 2) [000785] -c--------- t785 = CNS_INT long 1 $204 /--* t783 long +--* t785 long N005 ( 4, 6) [000786] -c--------- t786 = * BFIZ long /--* t781 long +--* t786 long N006 ( 6, 8) [000787] -c--------- t787 = * LEA(b+(i*1)+0) long /--* t787 long N007 ( 9, 10) [000788] ---XG------ t788 = * IND ushort /--* t788 ushort N009 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 N010 ( 1, 1) [003632] ----------- t3632 = LCL_VAR int V172 cse1 N012 ( 1, 2) [000789] -c--------- t789 = CNS_INT int 0 $c0 /--* t3632 int +--* t789 int N013 ( 12, 14) [000790] CEQ---XG--N--- * JCMP void ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} [004071] ----------- IL_OFFSET void INLRT @ 0x5E4[E-] N001 ( 1, 1) [003634] ----------- t3634 = LCL_VAR int V172 cse1 N002 ( 1, 1) [000800] ----------- t800 = LCL_VAR int V18 loc14 u:1 /--* t3634 int +--* t800 int N003 ( 3, 3) [000801] N---G--N-U- * NE void N004 ( 5, 5) [000802] ----G------ * JTRUE void $bec ------------ BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} [004072] ----------- IL_OFFSET void INLRT @ 0x5F1[E-] N001 ( 1, 1) [000758] ----------- t758 = LCL_VAR int V16 loc12 u:13 $b04 N002 ( 1, 1) [003700] ----------- t3700 = LCL_VAR int V179 cse8 u:1 $342 /--* t758 int +--* t3700 int N003 ( 3, 3) [000763] J------N--- * GE void $ba4 N004 ( 5, 5) [000764] ----------- * JTRUE void $VN.Void ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} [004073] ----------- IL_OFFSET void INLRT @ 0x5FF[E-] N001 ( 1, 1) [000765] ----------- t765 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000766] ----------- t766 = LCL_VAR int V16 loc12 u:13 $b04 /--* t766 int N003 ( 2, 3) [000767] -c--------- t767 = * CAST long <- int $aca N004 ( 1, 2) [000769] -c--------- t769 = CNS_INT long 1 $204 /--* t767 long +--* t769 long N005 ( 4, 6) [000770] -c--------- t770 = * BFIZ long /--* t765 long +--* t770 long N006 ( 6, 8) [000771] -c--------- t771 = * LEA(b+(i*1)+0) long /--* t771 long N007 ( 9, 10) [000772] ---XG------ t772 = * IND ushort /--* t772 ushort N009 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 N010 ( 1, 1) [003637] ----------- t3637 = LCL_VAR int V172 cse1 (last use) N012 ( 1, 2) [000773] -c--------- t773 = CNS_INT int 0 $c0 /--* t3637 int +--* t773 int N013 ( 12, 14) [000774] CEQ---XG--N--- * JCMP void ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} [004074] ----------- IL_OFFSET void INLRT @ 0x60D[E-] N001 ( 1, 1) [000776] ----------- t776 = LCL_VAR int V16 loc12 u:13 (last use) $b04 N002 ( 1, 2) [000777] -c--------- t777 = CNS_INT int 1 $c1 /--* t776 int +--* t777 int N003 ( 3, 4) [000778] ----------- t778 = * ADD int $bad /--* t778 int N005 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} [004075] ----------- IL_OFFSET void INLRT @ 0x618[E-] N001 ( 1, 1) [000283] ----------- t283 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003701] ----------- t3701 = LCL_VAR int V179 cse8 u:1 $342 /--* t283 int +--* t3701 int N003 ( 6, 3) [000288] -c-----N--- t288 = * GE int $94d N004 ( 1, 1) [000290] ----------- t290 = LCL_VAR long V34 loc30 u:1 $3c4 N005 ( 1, 1) [000291] ----------- t291 = LCL_VAR int V16 loc12 u:5 $898 /--* t291 int N006 ( 2, 3) [000292] -c--------- t292 = * CAST long <- int $3e5 N007 ( 1, 2) [000294] -c--------- t294 = CNS_INT long 1 $204 /--* t292 long +--* t294 long N008 ( 4, 6) [000295] -c--------- t295 = * BFIZ long /--* t290 long +--* t295 long N009 ( 6, 8) [000296] -c--------- t296 = * LEA(b+(i*1)+0) long /--* t296 long N010 ( 9, 10) [000297] ---XG------ t297 = * IND ushort /--* t297 ushort N012 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 N013 ( 1, 1) [003665] ----------- t3665 = LCL_VAR int V176 cse5 N015 ( 1, 2) [000298] -c--------- t298 = CNS_INT int 0 $c0 /--* t3665 int +--* t298 int N016 ( 15, 14) [000299] -c-XG--N--- t299 = * EQ int /--* t288 int +--* t299 int N017 ( 22, 18) [003760] Jc-XG--N--- * AND void N018 ( 24, 20) [000289] ---XG------ * JTRUE void $VN.Void ------------ BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} [004076] ----------- IL_OFFSET void INLRT @ 0x626[E-] [004077] ----------- IL_OFFSET void INLRT @ 0x634[E-] N001 ( 1, 1) [000303] ----------- t303 = LCL_VAR int V16 loc12 u:5 (last use) $898 /--* t303 int N003 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 [004078] ----------- IL_OFFSET void INLRT @ 0x634[E-] N001 ( 1, 1) [000304] ----------- t304 = LCL_VAR int V51 tmp11 u:1 (last use) $898 N002 ( 1, 2) [000305] -c--------- t305 = CNS_INT int 1 $c1 /--* t304 int +--* t305 int N003 ( 3, 4) [000306] ----------- t306 = * ADD int $952 /--* t306 int N005 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 N001 ( 1, 1) [003667] ----------- t3667 = LCL_VAR int V176 cse5 (last use) /--* t3667 int N003 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 [004079] ----------- IL_OFFSET void INL53 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000301] ----------- t301 = LCL_VAR byref V00 arg0 u:1 $100 /--* t301 byref N003 ( 3, 4) [003027] -c--------- t3027 = * LEA(b+8) byref /--* t3027 byref N004 ( 4, 3) [002244] ---XG------ t2244 = * IND int /--* t2244 int N006 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 [004080] ----------- IL_OFFSET void INL53 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002247] ----------- t2247 = LCL_VAR int V122 tmp82 u:1 N002 ( 1, 1) [002248] ----------- t2248 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2248 byref N004 ( 3, 4) [003031] -c--------- t3031 = * LEA(b+24) byref /--* t3031 byref N005 ( 4, 3) [002286] n---GO----- t2286 = * IND int /--* t2247 int +--* t2286 int N006 ( 6, 5) [002252] N---GO-N-U- * GE void N007 ( 8, 7) [002253] ----GO----- * JTRUE void $845 ------------ BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} [004081] ----------- IL_OFFSET void INL53 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003035] ----------- t3035 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003036] -c--------- t3036 = CNS_INT long 16 $200 /--* t3035 byref +--* t3036 long N003 ( 3, 4) [003037] -----O----- t3037 = * ADD byref $25c /--* t3037 byref N005 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 N001 ( 1, 1) [002259] ----------- t2259 = LCL_VAR int V122 tmp82 u:1 N002 ( 1, 1) [002264] ----------- t2264 = LCL_VAR byref V124 tmp84 u:1 $25c /--* t2264 byref N004 ( 3, 4) [003040] -c--------- t3040 = * LEA(b+8) byref /--* t3040 byref N005 ( 4, 3) [002265] n---GO----- t2265 = * IND int /--* t2259 int +--* t2265 int N006 ( 9, 11) [002266] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002263] ----------- t2263 = LCL_VAR byref V124 tmp84 u:1 (last use) $25c /--* t2263 byref N008 ( 3, 2) [002270] n---GO----- t2270 = * IND byref N009 ( 1, 1) [002260] ----------- t2260 = LCL_VAR int V122 tmp82 u:1 /--* t2260 int N010 ( 2, 3) [002267] -c-------U- t2267 = * CAST long <- uint N011 ( 1, 2) [002268] -c--------- t2268 = CNS_INT long 1 $204 /--* t2267 long +--* t2268 long N012 ( 4, 6) [002269] -c--------- t2269 = * BFIZ long /--* t2270 byref +--* t2269 long N013 ( 8, 9) [002271] -c--------- t2271 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002273] ----------- t2273 = LCL_VAR int V123 tmp83 u:1 (last use) /--* t2271 byref +--* t2273 int [004082] -A-XGO----- * STOREIND short [004083] ----------- IL_OFFSET void INL53 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002277] ----------- t2277 = LCL_VAR int V122 tmp82 u:1 (last use) N002 ( 1, 2) [002278] -c--------- t2278 = CNS_INT int 1 $c1 /--* t2277 int +--* t2278 int N003 ( 3, 4) [002279] ----------- t2279 = * ADD int N004 ( 1, 1) [002276] ----------- t2276 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2276 byref N006 ( 3, 4) [003043] -c--------- t3043 = * LEA(b+8) byref /--* t3043 byref +--* t2279 int [004084] -A--GO----- * STOREIND int ------------ BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} [004085] ----------- IL_OFFSET void INL53 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002254] ----------- t2254 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2254 byref [004280] ----------- t4280 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002255] ----------- t2255 = LCL_VAR int V123 tmp83 u:1 (last use) /--* t2255 int [004281] ----------- t4281 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003044] H---------- t3044 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3044 long [004282] ----------- t4282 = * PUTARG_REG long REG x11 /--* t4280 byref this in x0 +--* t4281 int arg2 in x1 +--* t4282 long r2r cell in x11 N004 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} [004086] ----------- IL_OFFSET void INLRT @ 0x64D[E-] N001 ( 1, 2) [003045] -c--------- t3045 = CNS_INT int 0 $c0 /--* t3045 int N003 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 [004087] ----------- IL_OFFSET void INLRT @ 0x650[E-] N001 ( 1, 2) [000326] -c--------- t326 = CNS_INT int 0 $c0 /--* t326 int N003 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 [004088] ----------- IL_OFFSET void INLRT @ 0x653[E-] N001 ( 1, 1) [000329] ----------- t329 = LCL_VAR int V09 loc5 u:3 $4c6 N002 ( 1, 2) [000330] -c--------- t330 = CNS_INT int 0 $c0 /--* t329 int +--* t330 int N003 ( 3, 4) [000331] CEQ-------N--- * JCMP void ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} [004089] ----------- IL_OFFSET void INLRT @ 0x65A[E-] N001 ( 1, 1) [000419] ----------- t419 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003702] ----------- t3702 = LCL_VAR int V179 cse8 u:1 $342 /--* t419 int +--* t3702 int N003 ( 3, 3) [000424] J------N--- * GE void $94d N004 ( 5, 5) [000425] ----------- * JTRUE void $VN.Void ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} [004090] ----------- IL_OFFSET void INLRT @ 0x665[E-] N001 ( 1, 1) [000565] ----------- t565 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000566] ----------- t566 = LCL_VAR int V16 loc12 u:5 $898 /--* t566 int N003 ( 2, 3) [000567] -c--------- t567 = * CAST long <- int $3e5 N004 ( 1, 2) [000569] -c--------- t569 = CNS_INT long 1 $204 /--* t567 long +--* t569 long N005 ( 4, 6) [000570] -c--------- t570 = * BFIZ long /--* t565 long +--* t570 long N006 ( 6, 8) [000571] -c--------- t571 = * LEA(b+(i*1)+0) long /--* t571 long N007 ( 9, 10) [000572] ---XG------ t572 = * IND ushort /--* t572 ushort N009 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 N010 ( 1, 1) [003670] ----------- t3670 = LCL_VAR int V176 cse5 (last use) N012 ( 1, 2) [000573] -c--------- t573 = CNS_INT int 48 $d8 /--* t3670 int +--* t573 int N013 ( 12, 14) [000574] N--XG--N-U- * EQ void N014 ( 14, 16) [000575] ---XG------ * JTRUE void $87a ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} [004091] ----------- IL_OFFSET void INLRT @ 0x67A[E-] N001 ( 1, 1) [000426] ----------- t426 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 2) [000427] -c--------- t427 = CNS_INT int 1 $c1 /--* t426 int +--* t427 int N003 ( 3, 4) [000428] ----------- t428 = * ADD int $952 N004 ( 1, 1) [003703] ----------- t3703 = LCL_VAR int V179 cse8 u:1 $342 /--* t428 int +--* t3703 int N005 ( 5, 6) [000433] J------N--- * GE void $9e2 N006 ( 7, 8) [000434] ----------- * JTRUE void $VN.Void ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} [004092] ----------- IL_OFFSET void INLRT @ 0x687[E-] N001 ( 1, 1) [000538] ----------- t538 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000539] ----------- t539 = LCL_VAR int V16 loc12 u:5 $898 /--* t539 int N003 ( 2, 3) [000540] -c--------- t540 = * CAST long <- int $3e5 N004 ( 1, 2) [000542] -c--------- t542 = CNS_INT long 1 $204 /--* t540 long +--* t542 long N005 ( 4, 6) [000543] -c--------- t543 = * BFIZ long /--* t538 long +--* t543 long N006 ( 6, 8) [000544] -c--------- t544 = * LEA(b+(i*1)+0) long /--* t544 long N007 ( 9, 10) [000545] ---XG------ t545 = * IND ushort /--* t545 ushort N009 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 N010 ( 1, 1) [003674] ----------- t3674 = LCL_VAR int V176 cse5 N012 ( 1, 2) [000546] -c--------- t546 = CNS_INT int 43 $d9 /--* t3674 int +--* t546 int N013 ( 15, 14) [000547] N--XG--N-U- t547 = * NE int N014 ( 1, 1) [000549] ----------- t549 = LCL_VAR long V34 loc30 u:1 $3c4 N015 ( 1, 1) [000550] ----------- t550 = LCL_VAR int V16 loc12 u:5 $898 N016 ( 1, 2) [000551] -c--------- t551 = CNS_INT int 1 $c1 /--* t550 int +--* t551 int N017 ( 3, 4) [000552] ----------- t552 = * ADD int $952 /--* t552 int N018 ( 4, 6) [000553] -c--------- t553 = * CAST long <- int $3f4 N019 ( 1, 2) [000555] -c--------- t555 = CNS_INT long 1 $204 /--* t553 long +--* t555 long N020 ( 6, 9) [000556] -c--------- t556 = * BFIZ long /--* t549 long +--* t556 long N021 ( 8, 11) [000557] -c--------- t557 = * LEA(b+(i*1)+0) long /--* t557 long N022 ( 11, 13) [000558] ---XG------ t558 = * IND ushort N023 ( 1, 2) [000559] -c--------- t559 = CNS_INT int 48 $d8 /--* t558 ushort +--* t559 int N024 ( 16, 16) [000560] N--XG--N-U- t560 = * NE int /--* t547 int +--* t560 int N025 ( 32, 31) [003762] J--XG--N--- t3762 = * AND int /--* t3762 int N026 ( 34, 33) [000548] ---XG------ * JTRUE void $87a ------------ BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} [004093] ----------- IL_OFFSET void INLRT @ 0x694[E-] [004094] ----------- IL_OFFSET void INLRT @ 0x6A3[E-] N001 ( 1, 2) [003046] ----------- t3046 = CNS_INT int 1 $c1 /--* t3046 int N003 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} [004095] ----------- IL_OFFSET void INLRT @ 0x6B5[E-] N001 ( 1, 1) [003676] ----------- t3676 = LCL_VAR int V176 cse5 (last use) N002 ( 1, 2) [000455] -c--------- t455 = CNS_INT int 45 $da /--* t3676 int +--* t455 int N003 ( 3, 4) [000456] N---G--N-U- * NE void N004 ( 5, 6) [000457] ----G------ * JTRUE void $87a ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} [004096] ----------- IL_OFFSET void INLRT @ 0x6C2[E-] N001 ( 1, 1) [000458] ----------- t458 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000459] ----------- t459 = LCL_VAR int V16 loc12 u:5 $898 N003 ( 1, 2) [000460] -c--------- t460 = CNS_INT int 1 $c1 /--* t459 int +--* t460 int N004 ( 3, 4) [000461] ----------- t461 = * ADD int $952 /--* t461 int N005 ( 4, 6) [000462] -c--------- t462 = * CAST long <- int $3f4 N006 ( 1, 2) [000464] -c--------- t464 = CNS_INT long 1 $204 /--* t462 long +--* t464 long N007 ( 6, 9) [000465] -c--------- t465 = * BFIZ long /--* t458 long +--* t465 long N008 ( 8, 11) [000466] -c--------- t466 = * LEA(b+(i*1)+0) long /--* t466 long N009 ( 11, 13) [000467] ---XG------ t467 = * IND ushort N010 ( 1, 2) [000468] -c--------- t468 = CNS_INT int 48 $d8 /--* t467 ushort +--* t468 int N011 ( 13, 16) [000469] J--XG--N--- * EQ void N012 ( 15, 18) [000470] ---XG------ * JTRUE void $a11 ------------ BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} [004097] ----------- IL_OFFSET void INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [000444] ----------- t444 = LCL_VAR byref V00 arg0 u:1 $100 /--* t444 byref N003 ( 3, 4) [003048] -c--------- t3048 = * LEA(b+8) byref /--* t3048 byref N004 ( 4, 3) [002302] ---XG------ t2302 = * IND int /--* t2302 int N006 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 [004098] ----------- IL_OFFSET void INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002305] ----------- t2305 = LCL_VAR int V126 tmp86 u:1 N002 ( 1, 1) [002306] ----------- t2306 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2306 byref N004 ( 3, 4) [003052] -c--------- t3052 = * LEA(b+24) byref /--* t3052 byref N005 ( 4, 3) [002341] n---GO----- t2341 = * IND int /--* t2305 int +--* t2341 int N006 ( 6, 5) [002310] N---GO-N-U- * GE void N007 ( 8, 7) [002311] ----GO----- * JTRUE void $845 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} [004099] ----------- IL_OFFSET void INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [003056] ----------- t3056 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003057] -c--------- t3057 = CNS_INT long 16 $200 /--* t3056 byref +--* t3057 long N003 ( 3, 4) [003058] -----O----- t3058 = * ADD byref $25c /--* t3058 byref N005 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 [004100] ----------- IL_OFFSET void INL58 @ ??? <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002316] ----------- t2316 = LCL_VAR int V126 tmp86 u:1 N002 ( 1, 1) [002321] ----------- t2321 = LCL_VAR byref V127 tmp87 u:1 $25c /--* t2321 byref N004 ( 3, 4) [003061] -c--------- t3061 = * LEA(b+8) byref /--* t3061 byref N005 ( 4, 3) [002322] n---GO----- t2322 = * IND int /--* t2316 int +--* t2322 int N006 ( 9, 11) [002323] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002320] ----------- t2320 = LCL_VAR byref V127 tmp87 u:1 (last use) $25c /--* t2320 byref N008 ( 3, 2) [002327] n---GO----- t2327 = * IND byref N009 ( 1, 1) [002317] ----------- t2317 = LCL_VAR int V126 tmp86 u:1 /--* t2317 int N010 ( 2, 3) [002324] -c-------U- t2324 = * CAST long <- uint N011 ( 1, 2) [002325] -c--------- t2325 = CNS_INT long 1 $204 /--* t2324 long +--* t2325 long N012 ( 4, 6) [002326] -c--------- t2326 = * BFIZ long /--* t2327 byref +--* t2326 long N013 ( 8, 9) [002328] -c--------- t2328 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002330] ----------- t2330 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2328 byref +--* t2330 int [004101] -A-XGO----- * STOREIND short [004102] ----------- IL_OFFSET void INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] N001 ( 1, 1) [002334] ----------- t2334 = LCL_VAR int V126 tmp86 u:1 (last use) N002 ( 1, 2) [002335] -c--------- t2335 = CNS_INT int 1 $c1 /--* t2334 int +--* t2335 int N003 ( 3, 4) [002336] ----------- t2336 = * ADD int N004 ( 1, 1) [002333] ----------- t2333 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2333 byref N006 ( 3, 4) [003064] -c--------- t3064 = * LEA(b+8) byref /--* t3064 byref +--* t2336 int [004103] -A--GO----- * STOREIND int ------------ BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} [004104] ----------- IL_OFFSET void INLRT @ 0x6DE[E-] N001 ( 1, 1) [000533] ----------- t533 = LCL_VAR int V38 loc34 u:5 (last use) $b0d N002 ( 1, 2) [000534] -c--------- t534 = CNS_INT int 1 $c1 /--* t533 int +--* t534 int N003 ( 3, 4) [000535] ----------- t535 = * ADD int $c59 /--* t535 int N005 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} [004105] ----------- IL_OFFSET void INLRT @ 0x6E4[E-] N001 ( 1, 1) [000471] ----------- t471 = LCL_VAR int V16 loc12 u:9 (last use) $b0e N002 ( 1, 2) [000472] -c--------- t472 = CNS_INT int 1 $c1 /--* t471 int +--* t472 int N003 ( 3, 4) [000473] ----------- t473 = * ADD int $c5c /--* t473 int N005 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 N001 ( 1, 1) [000477] ----------- t477 = LCL_VAR int V54 tmp14 u:1 (last use) $c5c /--* t477 int N003 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 N001 ( 1, 1) [000476] ----------- t476 = LCL_VAR int V16 loc12 u:10 $c5c N002 ( 1, 1) [003704] ----------- t3704 = LCL_VAR int V179 cse8 u:1 $342 /--* t476 int +--* t3704 int N003 ( 3, 3) [000484] J------N--- * GE void $c5d N004 ( 5, 5) [000485] ----------- * JTRUE void $VN.Void ------------ BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} [004106] ----------- IL_OFFSET void INLRT @ 0x6F4[E-] N001 ( 1, 1) [000522] ----------- t522 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000523] ----------- t523 = LCL_VAR int V16 loc12 u:10 $c5c /--* t523 int N003 ( 2, 3) [000524] -c--------- t524 = * CAST long <- int $ad8 N004 ( 1, 2) [000526] -c--------- t526 = CNS_INT long 1 $204 /--* t524 long +--* t526 long N005 ( 4, 6) [000527] -c--------- t527 = * BFIZ long /--* t522 long +--* t527 long N006 ( 6, 8) [000528] -c--------- t528 = * LEA(b+(i*1)+0) long /--* t528 long N007 ( 9, 10) [000529] ---XG------ t529 = * IND ushort N008 ( 1, 2) [000530] -c--------- t530 = CNS_INT int 48 $d8 /--* t529 ushort +--* t530 int N009 ( 11, 13) [000531] J--XG--N--- * EQ void N010 ( 13, 15) [000532] ---XG------ * JTRUE void $c18 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} [004107] ----------- IL_OFFSET void INLRT @ 0x701[E-] N001 ( 1, 1) [000486] ----------- t486 = LCL_VAR int V38 loc34 u:2 $b0f N002 ( 1, 2) [000487] -c--------- t487 = CNS_INT int 10 $e4 /--* t486 int +--* t487 int N003 ( 3, 4) [000488] J------N--- * LE void $c62 N004 ( 5, 6) [000489] ----------- * JTRUE void $VN.Void ------------ BB222 [707..70B), preds={BB221} succs={BB223} [004108] ----------- IL_OFFSET void INLRT @ 0x707[E-] N001 ( 1, 2) [000519] ----------- t519 = CNS_INT int 10 $e4 /--* t519 int N003 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} [004109] ----------- IL_OFFSET void INLRT @ 0x70B[E-] N001 ( 1, 1) [000490] ----------- t490 = LCL_VAR long V17 loc13 u:1 /--* t490 long N002 ( 4, 3) [000491] ---XG------ t491 = * IND ubyte N003 ( 1, 2) [000492] -c--------- t492 = CNS_INT int 0 $c0 /--* t491 ubyte +--* t492 int N004 ( 6, 6) [000493] CEQ---XG--N--- * JCMP void ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} [004110] ----------- IL_OFFSET void INLRT @ 0x710[E-] N001 ( 1, 1) [000512] ----------- t512 = LCL_VAR byref V01 arg1 u:1 $101 /--* t512 byref N003 ( 3, 4) [003067] -c--------- t3067 = * LEA(b+4) byref /--* t3067 byref N004 ( 4, 3) [000513] n---GO----- t513 = * IND int N005 ( 1, 1) [000514] ----------- t514 = LCL_VAR int V05 loc1 u:3 $28d /--* t513 int +--* t514 int N006 ( 6, 5) [000515] ----GO----- t515 = * SUB int /--* t515 int N008 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} [004111] ----------- IL_OFFSET void INLRT @ 0x71A[E-] N001 ( 1, 2) [000495] -c--------- t495 = CNS_INT int 0 $c0 /--* t495 int N003 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} [004112] ----------- IL_OFFSET void INLRT @ 0x71D[E-] N001 ( 1, 1) [000507] ----------- t507 = LCL_VAR int V37 loc33 u:2 (last use) $4ca /--* t507 int [004283] ----------- t4283 = * PUTARG_REG int REG x5 N002 ( 1, 1) [000502] ----------- t502 = LCL_VAR byref V00 arg0 u:1 $100 /--* t502 byref [004284] ----------- t4284 = * PUTARG_REG byref REG x0 N003 ( 1, 1) [000503] ----------- t503 = LCL_VAR ref V03 arg3 u:1 $180 /--* t503 ref [004285] ----------- t4285 = * PUTARG_REG ref REG x1 N004 ( 1, 1) [000499] ----------- t499 = LCL_VAR int V55 tmp15 u:1 (last use) $b12 /--* t499 int [004286] ----------- t4286 = * PUTARG_REG int REG x2 N005 ( 1, 1) [000505] ----------- t505 = LCL_VAR int V18 loc14 u:1 (last use) /--* t505 int [004287] ----------- t4287 = * PUTARG_REG int REG x3 N006 ( 1, 1) [000506] ----------- t506 = LCL_VAR int V38 loc34 u:3 (last use) $b10 /--* t506 int [004288] ----------- t4288 = * PUTARG_REG int REG x4 N007 ( 2, 8) [003068] H---------- t3068 = CNS_INT(h) long 0x4000000000540240 ftn $5e /--* t3068 long [004289] ----------- t4289 = * PUTARG_REG long REG x11 /--* t4283 int arg6 in x5 +--* t4284 byref arg1 in x0 +--* t4285 ref arg2 in x1 +--* t4286 int arg3 in x2 +--* t4287 int arg4 in x3 +--* t4288 int arg5 in x4 +--* t4289 long r2r cell in x11 N008 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) $VN.Void [004113] ----------- IL_OFFSET void INLRT @ 0x72C[E-] N001 ( 1, 2) [003069] -c--------- t3069 = CNS_INT int 0 $c0 /--* t3069 int N003 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} [004114] ----------- IL_OFFSET void INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [000333] ----------- t333 = LCL_VAR byref V00 arg0 u:1 $100 /--* t333 byref N003 ( 3, 4) [003071] -c--------- t3071 = * LEA(b+8) byref /--* t3071 byref N004 ( 4, 3) [002349] ---XG------ t2349 = * IND int /--* t2349 int N006 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 [004115] ----------- IL_OFFSET void INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002352] ----------- t2352 = LCL_VAR int V129 tmp89 u:1 N002 ( 1, 1) [002353] ----------- t2353 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2353 byref N004 ( 3, 4) [003075] -c--------- t3075 = * LEA(b+24) byref /--* t3075 byref N005 ( 4, 3) [002388] n---GO----- t2388 = * IND int /--* t2352 int +--* t2388 int N006 ( 6, 5) [002357] N---GO-N-U- * GE void N007 ( 8, 7) [002358] ----GO----- * JTRUE void $845 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} [004116] ----------- IL_OFFSET void INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [003079] ----------- t3079 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003080] -c--------- t3080 = CNS_INT long 16 $200 /--* t3079 byref +--* t3080 long N003 ( 3, 4) [003081] -----O----- t3081 = * ADD byref $25c /--* t3081 byref N005 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 [004117] ----------- IL_OFFSET void INL61 @ ??? <- INLRT @ 0x731[E-] N001 ( 1, 1) [002363] ----------- t2363 = LCL_VAR int V129 tmp89 u:1 N002 ( 1, 1) [002368] ----------- t2368 = LCL_VAR byref V130 tmp90 u:1 $25c /--* t2368 byref N004 ( 3, 4) [003084] -c--------- t3084 = * LEA(b+8) byref /--* t3084 byref N005 ( 4, 3) [002369] n---GO----- t2369 = * IND int /--* t2363 int +--* t2369 int N006 ( 9, 11) [002370] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002367] ----------- t2367 = LCL_VAR byref V130 tmp90 u:1 (last use) $25c /--* t2367 byref N008 ( 3, 2) [002374] n---GO----- t2374 = * IND byref N009 ( 1, 1) [002364] ----------- t2364 = LCL_VAR int V129 tmp89 u:1 /--* t2364 int N010 ( 2, 3) [002371] -c-------U- t2371 = * CAST long <- uint N011 ( 1, 2) [002372] -c--------- t2372 = CNS_INT long 1 $204 /--* t2371 long +--* t2372 long N012 ( 4, 6) [002373] -c--------- t2373 = * BFIZ long /--* t2374 byref +--* t2373 long N013 ( 8, 9) [002375] -c--------- t2375 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002377] ----------- t2377 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2375 byref +--* t2377 int [004118] -A-XGO----- * STOREIND short [004119] ----------- IL_OFFSET void INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002381] ----------- t2381 = LCL_VAR int V129 tmp89 u:1 (last use) N002 ( 1, 2) [002382] -c--------- t2382 = CNS_INT int 1 $c1 /--* t2381 int +--* t2382 int N003 ( 3, 4) [002383] ----------- t2383 = * ADD int N004 ( 1, 1) [002380] ----------- t2380 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2380 byref N006 ( 3, 4) [003087] -c--------- t3087 = * LEA(b+8) byref /--* t3087 byref +--* t2383 int [004120] -A--GO----- * STOREIND int ------------ BB229 [731..732), preds={BB227} succs={BB230} [004121] ----------- IL_OFFSET void INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] N001 ( 1, 1) [002359] ----------- t2359 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2359 byref [004290] ----------- t4290 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000334] ----------- t334 = LCL_VAR int V18 loc14 u:1 (last use) /--* t334 int [004291] ----------- t4291 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003088] H---------- t3088 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3088 long [004292] ----------- t4292 = * PUTARG_REG long REG x11 /--* t4290 byref this in x0 +--* t4291 int arg2 in x1 +--* t4292 long r2r cell in x11 N004 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} [004122] ----------- IL_OFFSET void INLRT @ 0x739[E-] N001 ( 1, 1) [000336] ----------- t336 = LCL_VAR int V16 loc12 u:5 $898 N002 ( 1, 1) [003705] ----------- t3705 = LCL_VAR int V179 cse8 u:1 $342 /--* t336 int +--* t3705 int N003 ( 3, 3) [000341] J------N--- * GE void $94d N004 ( 5, 5) [000342] ----------- * JTRUE void $VN.Void ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} [004123] ----------- IL_OFFSET void INLRT @ 0x744[E-] N001 ( 1, 1) [000343] ----------- t343 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000344] ----------- t344 = LCL_VAR int V16 loc12 u:5 $898 /--* t344 int N003 ( 2, 3) [000345] -c--------- t345 = * CAST long <- int $3e5 N004 ( 1, 2) [000347] -c--------- t347 = CNS_INT long 1 $204 /--* t345 long +--* t347 long N005 ( 4, 6) [000348] -c--------- t348 = * BFIZ long /--* t343 long +--* t348 long N006 ( 6, 8) [000349] -c--------- t349 = * LEA(b+(i*1)+0) long /--* t349 long N007 ( 9, 10) [000350] ---XG------ t350 = * IND ushort /--* t350 ushort N009 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 N010 ( 1, 1) [003659] ----------- t3659 = LCL_VAR int V175 cse4 u:1 N012 ( 1, 2) [000351] -c--------- t351 = CNS_INT int 43 $d9 /--* t3659 int +--* t351 int N013 ( 12, 14) [000352] J--XG--N--- * EQ void N014 ( 14, 16) [000353] ---XG------ * JTRUE void $87a ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} [004124] ----------- IL_OFFSET void INLRT @ 0x751[E-] N001 ( 1, 1) [003661] ----------- t3661 = LCL_VAR int V175 cse4 u:1 N002 ( 1, 2) [000416] -c--------- t416 = CNS_INT int 45 $da /--* t3661 int +--* t416 int N003 ( 3, 4) [000417] N---G--N-U- * NE void N004 ( 5, 6) [000418] ----G------ * JTRUE void $87a ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} [004125] ----------- IL_OFFSET void INLRT @ 0x75E[E-] N001 ( 1, 1) [000356] ----------- t356 = LCL_VAR int V16 loc12 u:5 (last use) $898 /--* t356 int N003 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 [004126] ----------- IL_OFFSET void INLRT @ 0x75E[E-] N001 ( 1, 1) [000357] ----------- t357 = LCL_VAR int V52 tmp12 u:1 (last use) $898 N002 ( 1, 2) [000358] -c--------- t358 = CNS_INT int 1 $c1 /--* t357 int +--* t358 int N003 ( 3, 4) [000359] ----------- t359 = * ADD int $952 /--* t359 int N005 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 N001 ( 1, 1) [003662] ----------- t3662 = LCL_VAR int V175 cse4 u:1 (last use) /--* t3662 int N003 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 [004127] ----------- IL_OFFSET void INL64 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000354] ----------- t354 = LCL_VAR byref V00 arg0 u:1 $100 /--* t354 byref N003 ( 3, 4) [003090] -c--------- t3090 = * LEA(b+8) byref /--* t3090 byref N004 ( 4, 3) [002396] n---GO----- t2396 = * IND int /--* t2396 int N006 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 [004128] ----------- IL_OFFSET void INL64 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002399] ----------- t2399 = LCL_VAR int V132 tmp92 u:1 N002 ( 1, 1) [002400] ----------- t2400 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2400 byref N004 ( 3, 4) [003094] -c--------- t3094 = * LEA(b+24) byref /--* t3094 byref N005 ( 4, 3) [002438] n---GO----- t2438 = * IND int /--* t2399 int +--* t2438 int N006 ( 6, 5) [002404] N---GO-N-U- * GE void N007 ( 8, 7) [002405] ----GO----- * JTRUE void $845 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} [004129] ----------- IL_OFFSET void INL64 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003098] ----------- t3098 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003099] -c--------- t3099 = CNS_INT long 16 $200 /--* t3098 byref +--* t3099 long N003 ( 3, 4) [003100] -----O----- t3100 = * ADD byref $25c /--* t3100 byref N005 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 N001 ( 1, 1) [002411] ----------- t2411 = LCL_VAR int V132 tmp92 u:1 N002 ( 1, 1) [002416] ----------- t2416 = LCL_VAR byref V134 tmp94 u:1 $25c /--* t2416 byref N004 ( 3, 4) [003103] -c--------- t3103 = * LEA(b+8) byref /--* t3103 byref N005 ( 4, 3) [002417] n---GO----- t2417 = * IND int /--* t2411 int +--* t2417 int N006 ( 9, 11) [002418] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002415] ----------- t2415 = LCL_VAR byref V134 tmp94 u:1 (last use) $25c /--* t2415 byref N008 ( 3, 2) [002422] n---GO----- t2422 = * IND byref N009 ( 1, 1) [002412] ----------- t2412 = LCL_VAR int V132 tmp92 u:1 /--* t2412 int N010 ( 2, 3) [002419] -c-------U- t2419 = * CAST long <- uint N011 ( 1, 2) [002420] -c--------- t2420 = CNS_INT long 1 $204 /--* t2419 long +--* t2420 long N012 ( 4, 6) [002421] -c--------- t2421 = * BFIZ long /--* t2422 byref +--* t2421 long N013 ( 8, 9) [002423] -c--------- t2423 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002425] ----------- t2425 = LCL_VAR int V133 tmp93 u:1 (last use) /--* t2423 byref +--* t2425 int [004130] -A-XGO----- * STOREIND short [004131] ----------- IL_OFFSET void INL64 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002429] ----------- t2429 = LCL_VAR int V132 tmp92 u:1 (last use) N002 ( 1, 2) [002430] -c--------- t2430 = CNS_INT int 1 $c1 /--* t2429 int +--* t2430 int N003 ( 3, 4) [002431] ----------- t2431 = * ADD int N004 ( 1, 1) [002428] ----------- t2428 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2428 byref N006 ( 3, 4) [003106] -c--------- t3106 = * LEA(b+8) byref /--* t3106 byref +--* t2431 int [004132] -A--GO----- * STOREIND int ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} [004133] ----------- IL_OFFSET void INL64 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002406] ----------- t2406 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2406 byref [004293] ----------- t4293 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002407] ----------- t2407 = LCL_VAR int V133 tmp93 u:1 (last use) /--* t2407 int [004294] ----------- t4294 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003107] H---------- t3107 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3107 long [004295] ----------- t4295 = * PUTARG_REG long REG x11 /--* t4293 byref this in x0 +--* t4294 int arg2 in x1 +--* t4295 long r2r cell in x11 N004 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} [004134] ----------- IL_OFFSET void INLRT @ 0x774[E-] N001 ( 1, 1) [000392] ----------- t392 = LCL_VAR int V16 loc12 u:6 (last use) $b08 /--* t392 int N003 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 [004135] ----------- IL_OFFSET void INLRT @ 0x774[E-] N001 ( 1, 1) [000393] ----------- t393 = LCL_VAR int V53 tmp13 u:1 (last use) $b08 N002 ( 1, 2) [000394] -c--------- t394 = CNS_INT int 1 $c1 /--* t393 int +--* t394 int N003 ( 3, 4) [000395] ----------- t395 = * ADD int $c47 /--* t395 int N005 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 N001 ( 1, 1) [003639] ----------- t3639 = LCL_VAR int V173 cse2 u:1 (last use) /--* t3639 int N003 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 [004136] ----------- IL_OFFSET void INL66 @ 0x000[E-] <- INLRT @ ??? N001 ( 1, 1) [000390] ----------- t390 = LCL_VAR byref V00 arg0 u:1 $100 /--* t390 byref N003 ( 3, 4) [003109] -c--------- t3109 = * LEA(b+8) byref /--* t3109 byref N004 ( 4, 3) [002442] n---GO----- t2442 = * IND int /--* t2442 int N006 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 [004137] ----------- IL_OFFSET void INL66 @ 0x007[E-] <- INLRT @ ??? N001 ( 1, 1) [002445] ----------- t2445 = LCL_VAR int V136 tmp96 u:1 N002 ( 1, 1) [002446] ----------- t2446 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2446 byref N004 ( 3, 4) [003113] -c--------- t3113 = * LEA(b+24) byref /--* t3113 byref N005 ( 4, 3) [002484] n---GO----- t2484 = * IND int /--* t2445 int +--* t2484 int N006 ( 6, 5) [002450] N---GO-N-U- * GE void N007 ( 8, 7) [002451] ----GO----- * JTRUE void $845 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} [004138] ----------- IL_OFFSET void INL66 @ 0x015[E-] <- INLRT @ ??? N001 ( 1, 1) [003117] ----------- t3117 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003118] -c--------- t3118 = CNS_INT long 16 $200 /--* t3117 byref +--* t3118 long N003 ( 3, 4) [003119] -----O----- t3119 = * ADD byref $25c /--* t3119 byref N005 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 N001 ( 1, 1) [002457] ----------- t2457 = LCL_VAR int V136 tmp96 u:1 N002 ( 1, 1) [002462] ----------- t2462 = LCL_VAR byref V138 tmp98 u:1 $25c /--* t2462 byref N004 ( 3, 4) [003122] -c--------- t3122 = * LEA(b+8) byref /--* t3122 byref N005 ( 4, 3) [002463] n---GO----- t2463 = * IND int /--* t2457 int +--* t2463 int N006 ( 9, 11) [002464] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002461] ----------- t2461 = LCL_VAR byref V138 tmp98 u:1 (last use) $25c /--* t2461 byref N008 ( 3, 2) [002468] n---GO----- t2468 = * IND byref N009 ( 1, 1) [002458] ----------- t2458 = LCL_VAR int V136 tmp96 u:1 /--* t2458 int N010 ( 2, 3) [002465] -c-------U- t2465 = * CAST long <- uint N011 ( 1, 2) [002466] -c--------- t2466 = CNS_INT long 1 $204 /--* t2465 long +--* t2466 long N012 ( 4, 6) [002467] -c--------- t2467 = * BFIZ long /--* t2468 byref +--* t2467 long N013 ( 8, 9) [002469] -c--------- t2469 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002471] ----------- t2471 = LCL_VAR int V137 tmp97 u:1 (last use) /--* t2469 byref +--* t2471 int [004139] -A-XGO----- * STOREIND short [004140] ----------- IL_OFFSET void INL66 @ 0x023[E-] <- INLRT @ ??? N001 ( 1, 1) [002475] ----------- t2475 = LCL_VAR int V136 tmp96 u:1 (last use) N002 ( 1, 2) [002476] -c--------- t2476 = CNS_INT int 1 $c1 /--* t2475 int +--* t2476 int N003 ( 3, 4) [002477] ----------- t2477 = * ADD int N004 ( 1, 1) [002474] ----------- t2474 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2474 byref N006 ( 3, 4) [003125] -c--------- t3125 = * LEA(b+8) byref /--* t3125 byref +--* t2477 int [004141] -A--GO----- * STOREIND int ------------ BB238 [000..000), preds={BB236} succs={BB239} [004142] ----------- IL_OFFSET void INL66 @ 0x02D[E-] <- INLRT @ ??? N001 ( 1, 1) [002452] ----------- t2452 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2452 byref [004296] ----------- t4296 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [002453] ----------- t2453 = LCL_VAR int V137 tmp97 u:1 (last use) /--* t2453 int [004297] ----------- t4297 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003126] H---------- t3126 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3126 long [004298] ----------- t4298 = * PUTARG_REG long REG x11 /--* t4296 byref this in x0 +--* t4297 int arg2 in x1 +--* t4298 long r2r cell in x11 N004 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} [004143] ----------- IL_OFFSET void INLRT @ 0x788[E-] N001 ( 1, 1) [000372] ----------- t372 = LCL_VAR int V16 loc12 u:6 $b08 N002 ( 1, 1) [003706] ----------- t3706 = LCL_VAR int V179 cse8 u:1 $342 /--* t372 int +--* t3706 int N003 ( 3, 3) [000377] J------N--- * GE void $c42 N004 ( 5, 5) [000378] ----------- * JTRUE void $VN.Void ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} [004144] ----------- IL_OFFSET void INLRT @ 0x793[E-] N001 ( 1, 1) [000379] ----------- t379 = LCL_VAR long V34 loc30 u:1 $3c4 N002 ( 1, 1) [000380] ----------- t380 = LCL_VAR int V16 loc12 u:6 $b08 /--* t380 int N003 ( 2, 3) [000381] -c--------- t381 = * CAST long <- int $ad1 N004 ( 1, 2) [000383] -c--------- t383 = CNS_INT long 1 $204 /--* t381 long +--* t383 long N005 ( 4, 6) [000384] -c--------- t384 = * BFIZ long /--* t379 long +--* t384 long N006 ( 6, 8) [000385] -c--------- t385 = * LEA(b+(i*1)+0) long /--* t385 long N007 ( 9, 10) [000386] ---XG------ t386 = * IND ushort /--* t386 ushort N009 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 N010 ( 1, 1) [003642] ----------- t3642 = LCL_VAR int V173 cse2 u:1 N012 ( 1, 2) [000387] -c--------- t387 = CNS_INT int 48 $d8 /--* t3642 int +--* t387 int N013 ( 12, 14) [000388] J--XG--N--- * EQ void N014 ( 14, 16) [000389] ---XG------ * JTRUE void $c02 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ------------ BB242 [7A2..7AA) -> BB244 (cond), preds={BB140,BB143,BB257(2),BB258(2)} succs={BB243,BB244} [004145] ----------- IL_OFFSET void INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [000590] ----------- t590 = LCL_VAR byref V00 arg0 u:1 $100 /--* t590 byref N003 ( 3, 4) [003128] -c--------- t3128 = * LEA(b+8) byref /--* t3128 byref N004 ( 4, 3) [002492] ---XG------ t2492 = * IND int /--* t2492 int N006 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 [004146] ----------- IL_OFFSET void INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002495] ----------- t2495 = LCL_VAR int V140 tmp100 u:1 N002 ( 1, 1) [002496] ----------- t2496 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2496 byref N004 ( 3, 4) [003132] -c--------- t3132 = * LEA(b+24) byref /--* t3132 byref N005 ( 4, 3) [002531] n---GO----- t2531 = * IND int /--* t2495 int +--* t2531 int N006 ( 6, 5) [002500] N---GO-N-U- * GE void N007 ( 8, 7) [002501] ----GO----- * JTRUE void $845 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} [004147] ----------- IL_OFFSET void INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [003136] ----------- t3136 = LCL_VAR byref V00 arg0 u:1 $100 N002 ( 1, 2) [003137] -c--------- t3137 = CNS_INT long 16 $200 /--* t3136 byref +--* t3137 long N003 ( 3, 4) [003138] -----O----- t3138 = * ADD byref $25c /--* t3138 byref N005 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 [004148] ----------- IL_OFFSET void INL69 @ ??? <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002506] ----------- t2506 = LCL_VAR int V140 tmp100 u:1 N002 ( 1, 1) [002511] ----------- t2511 = LCL_VAR byref V141 tmp101 u:1 $25c /--* t2511 byref N004 ( 3, 4) [003141] -c--------- t3141 = * LEA(b+8) byref /--* t3141 byref N005 ( 4, 3) [002512] n---GO----- t2512 = * IND int /--* t2506 int +--* t2512 int N006 ( 9, 11) [002513] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void N007 ( 1, 1) [002510] ----------- t2510 = LCL_VAR byref V141 tmp101 u:1 (last use) $25c /--* t2510 byref N008 ( 3, 2) [002517] n---GO----- t2517 = * IND byref N009 ( 1, 1) [002507] ----------- t2507 = LCL_VAR int V140 tmp100 u:1 /--* t2507 int N010 ( 2, 3) [002514] -c-------U- t2514 = * CAST long <- uint N011 ( 1, 2) [002515] -c--------- t2515 = CNS_INT long 1 $204 /--* t2514 long +--* t2515 long N012 ( 4, 6) [002516] -c--------- t2516 = * BFIZ long /--* t2517 byref +--* t2516 long N013 ( 8, 9) [002518] -c--------- t2518 = * LEA(b+(i*1)+0) byref N016 ( 1, 1) [002520] ----------- t2520 = LCL_VAR int V18 loc14 u:1 (last use) /--* t2518 byref +--* t2520 int [004149] -A-XGO----- * STOREIND short [004150] ----------- IL_OFFSET void INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002524] ----------- t2524 = LCL_VAR int V140 tmp100 u:1 (last use) N002 ( 1, 2) [002525] -c--------- t2525 = CNS_INT int 1 $c1 /--* t2524 int +--* t2525 int N003 ( 3, 4) [002526] ----------- t2526 = * ADD int N004 ( 1, 1) [002523] ----------- t2523 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2523 byref N006 ( 3, 4) [003144] -c--------- t3144 = * LEA(b+8) byref /--* t3144 byref +--* t2526 int [004151] -A--GO----- * STOREIND int ------------ BB244 [7A2..7A3) -> BB245 (always), preds={BB215,BB242} succs={BB245} [004152] ----------- IL_OFFSET void INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] N001 ( 1, 1) [002502] ----------- t2502 = LCL_VAR byref V00 arg0 u:1 $100 /--* t2502 byref [004299] ----------- t4299 = * PUTARG_REG byref REG x0 N002 ( 1, 1) [000591] ----------- t591 = LCL_VAR int V18 loc14 u:1 (last use) /--* t591 int [004300] ----------- t4300 = * PUTARG_REG int REG x1 N003 ( 2, 8) [003145] H---------- t3145 = CNS_INT(h) long 0x4000000000435c58 ftn $53 /--* t3145 long [004301] ----------- t4301 = * PUTARG_REG long REG x11 /--* t4299 byref this in x0 +--* t4300 int arg2 in x1 +--* t4301 long r2r cell in x11 N004 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void $VN.Void ------------ BB110 [000..000) (throw), preds={BB91} succs={} [004153] ----------- IL_OFFSET void INL17 @ 0x029[E-] <- INLRT @ ??? N001 ( 2, 8) [002701] H---------- t2701 = CNS_INT(h) long 0x4000000000424a20 ftn $4a /--* t2701 long [004302] ----------- t4302 = * PUTARG_REG long REG x11 /--* t4302 long r2r cell in x11 N002 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() $VN.Void ------------ BB254 [???..???) (throw), preds={} succs={} N001 ( 2, 8) [004303] H---------- t4303 = CNS_INT(h) long 0x4000000000421828 ftn /--* t4303 long N002 ( 5, 10) [004304] ----------- t4304 = * IND long /--* t4304 long control expr N001 ( 14, 2) [004154] --CXG------ * CALL help void CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Calculate stack level slots *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use: {V01 V02} def: {V11 V17 V76 V147 V148 V167 V179 V180} in: {V00 V01 V02 V03} out: {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} BB02 use: {V01 V147 V148} def: {V155 V156} in: {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} out: {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} BB03 use: {V155 V156} def: {V43 V149 V150} in: {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} out: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} BB04 use: {V155 V156} def: {V43 V149 V150} in: {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} out: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} BB05 use: {V147 V148} def: {V43 V149 V150} in: {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} out: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} BB06 use: {V43 V149 V150} def: {V15} in: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} out: {V00 V01 V02 V03 V11 V15 V17 V179 V180} BB07 use: {V15 V180} def: {V04 V05 V06 V07 V09 V10 V12 V13 V16 V22 V157 V168} in: {V00 V01 V02 V03 V11 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB08 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} BB09 use: {V18} def: {V182} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V182} BB255 use: {V182} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V182} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} BB10 use: {V18} def: {V183} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V183} BB256 use: {V183} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180 V183} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB11 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB12 use: {} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB13 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} BB14 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} BB15 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB16 use: {V13} def: {V13} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB17 use: {V04} def: {V04} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB18 use: {V06} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB19 use: {V04} def: {V06} in: {V00 V01 V02 V03 V04 V05 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB20 use: {V04} def: {V04 V07} in: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB21 use: {V05} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB22 use: {V04} def: {V05} in: {V00 V01 V02 V03 V04 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB23 use: {V04 V05} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB24 use: {V10} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB26 use: {V04 V10} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB27 use: {V11} def: {V11} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB28 use: {} def: {V12} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22 V179 V180} BB29 use: {V04} def: {V10 V11} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB30 use: {V13} def: {V13} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB31 use: {V16 V22 V179} def: {V171} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} BB32 use: {V16 V18 V171} def: {V16 V74} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} BB34 use: {} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB35 use: {V16 V22 V179} def: {V174} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB36 use: {V16} def: {V16} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB38 use: {V16 V179} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB39 use: {V16 V22} def: {V174} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB40 use: {V16 V179} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB41 use: {V16 V22} def: {V174} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V174 V179 V180} BB42 use: {V174} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V174 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB43 use: {V16 V22} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB44 use: {V16 V179} def: {V16 V73} in: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB45 use: {V16 V22} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB46 use: {} def: {V09} in: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB47 use: {V16 V179} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} BB48 use: {V16 V22} def: {V16 V18 V71 V72} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} BB49 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} BB50 use: {V05} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} BB51 use: {V04} def: {V05} in: {V00 V01 V02 V03 V04 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} BB52 use: {V10} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} BB53 use: {V05 V10} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} BB54 use: {V11 V13} def: {V13} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} BB55 use: {} def: {V12} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} BB56 use: {V17} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} BB57 use: {V01 V09 V13} def: {V69} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} BB58 use: {V01 V04 V05} def: {V70} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70 V179 V180} BB59 use: {V04} def: {V70} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70 V179 V180} BB60 use: {V01 V17 V70} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} BB61 use: {V02 V15 V180} def: {V16} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V16 V17 V179 V180} BB62 use: {V16} def: {V15} in: {V00 V01 V02 V03 V11 V16 V17 V179 V180} out: {V00 V01 V02 V03 V11 V15 V17 V179 V180} BB63 use: {V01} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} BB64 use: {V01} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} BB65 use: {V01} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} BB66 use: {V05 V06 V07 V09} def: {V06 V07 V44 V45} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} BB73 use: {V05} def: {V08 V14} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V179 V180} BB74 use: {V01 V05} def: {V08 V14 V46 V178} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V179 V180} BB78 use: {V03 V12 V15} def: {V16 V20 V143 V144 V151 V152} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} BB79 use: {V03} def: {V26 V27 V28 V29} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144 V179 V180} BB81 use: {V26} def: {V28} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V29 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144 V179 V180} BB82 use: {V08 V14 V28} def: {V30 V64} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144 V179 V180} BB83 use: {V64} def: {V65 V66} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144 V179 V180} BB84 use: {V14 V64} def: {V65 V66} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144 V179 V180} BB85 use: {V06 V30 V65 V66} def: {V31 V32 V67} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} BB89 use: {V30} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} BB90 use: {V20 V144} def: {V20} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} BB91 use: {V144} def: {V33 V159 V160 V161} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V161 V179 V180} BB95 use: {V33 V143 V144 V161} def: {V83 V143 V144 V163 V164} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V161 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} BB100 use: {V20 V27 V28 V29 V143 V144} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} BB101 use: {V26 V27} def: {V27 V30} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} BB102 use: {V28 V30 V32} def: {V28} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} BB103 use: {V01 V16} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} BB104 use: {V01} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} BB106 use: {V03} def: {V86} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144 V179 V180} BB107 use: {V00 V86} def: {V87} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144 V179 V180} BB108 use: {V00 V86 V87} def: {V88} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} BB112 use: {V17 V180} def: {V21 V34 V36 V165 V169} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB245 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB246 use: {V16 V34} def: {V16 V18 V49 V50} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB247 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB248 use: {V01 V15} def: {} in: {V00 V01 V03 V15} out: {V00 V01 V03} BB249 use: {V00 V01} def: {} in: {V00 V01 V03} out: {V00 V03} BB251 use: {V00 V03} def: {} in: {V00 V03} out: {} BB253 use: {} def: {} in: {} out: {} BB111 use: {V00 V86} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} BB113 use: {V14} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB114 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB115 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB117 use: {} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB118 use: {V00 V36} def: {V60 V177} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V177 V179} BB119 use: {V00} def: {V62 V63} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V63 V143 V144 V179} BB120 use: {V00 V36 V177} def: {V36 V61 V62 V63} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V177 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V63 V143 V144 V179} BB121 use: {V00 V63} def: {V91 V92} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V63 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V91 V92 V143 V144 V179} BB122 use: {V00 V91 V92} def: {V93} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V91 V92 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB123 use: {V00 V92} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V92 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB124 use: {V08 V12} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB125 use: {V08 V20 V143 V144} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB127 use: {V03} def: {V95} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144 V179} BB129 use: {V00 V95} def: {V96 V181} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144 V179 V181} BB130 use: {V00 V95 V96 V181} def: {V97} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144 V179 V181} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB132 use: {V00 V95} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB133 use: {V20} def: {V20} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB134 use: {V08 V14} def: {V08 V14} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB135 use: {V14} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB136 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB137 use: {V18} def: {V184} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V184} BB257 use: {V184} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V184} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB138 use: {V18} def: {V185} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V185} BB258 use: {V185} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V185} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB139 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB140 use: {} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB141 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB142 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB143 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB144 use: {V03} def: {V110} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} BB145 use: {V14} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB146 use: {V06 V08 V14} def: {V14} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB147 use: {} def: {V58} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144 V179} BB148 use: {} def: {V58} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144 V179} BB149 use: {V58} def: {V18} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB150 use: {V36} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB151 use: {V07 V08} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB152 use: {} def: {V57} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} BB153 use: {} def: {V57} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} BB154 use: {V36} def: {V36 V56 V57} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} BB155 use: {V57} def: {V18} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB156 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB157 use: {V00} def: {V99} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144 V179} BB158 use: {V00 V18 V99} def: {V100} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB159 use: {V00 V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB160 use: {V08 V12} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB161 use: {V08 V20 V143 V144} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB163 use: {V03} def: {V102} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144 V179} BB165 use: {V00 V102} def: {V103} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144 V179} BB166 use: {V00 V102 V103} def: {V104} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB168 use: {V00 V102} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB169 use: {V20} def: {V20} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB170 use: {V08} def: {V08} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB171 use: {V08 V21} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB172 use: {V07} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB173 use: {V04 V05 V36} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB174 use: {V03} def: {V106} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144 V179} BB176 use: {V00 V106} def: {V107} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144 V179} BB177 use: {V00 V106 V107} def: {V108} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} BB179 use: {V00 V106} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} BB180 use: {} def: {V21} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB181 use: {V110} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} BB182 use: {V00 V110} def: {V111} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144 V179} BB183 use: {V00 V110 V111} def: {V112} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB185 use: {V00 V110} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB186 use: {V03} def: {V114} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144 V179} BB187 use: {V00 V114} def: {V115} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144 V179} BB188 use: {V00 V114 V115} def: {V116} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB190 use: {V00 V114} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB191 use: {V00 V16 V172} def: {V16 V59 V118 V119} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144 V179} BB192 use: {V00 V118 V119} def: {V120} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB193 use: {V00 V119} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V119 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB194 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} BB195 use: {V16 V34} def: {V172} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} BB196 use: {V18 V172} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} BB197 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB198 use: {V16 V34} def: {V172} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB199 use: {V16} def: {V16} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB200 use: {V16 V34 V179} def: {V176} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V176 V179} BB201 use: {V00 V16 V176} def: {V16 V51 V122 V123} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V176 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144 V179} BB203 use: {V00 V122 V123} def: {V124} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB204 use: {V00 V123} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V123 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB205 use: {V09} def: {V37 V38} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB206 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB207 use: {V16 V34} def: {V176} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB208 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB209 use: {V16 V34} def: {V176} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V176 V179} BB210 use: {} def: {V37} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB213 use: {V176} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V176 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB214 use: {V16 V34} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB215 use: {V00} def: {V126} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144 V179} BB216 use: {V00 V18 V126} def: {V127} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB218 use: {V38} def: {V38} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB219 use: {V16 V179} def: {V16 V54} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB220 use: {V16 V34} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB221 use: {V38} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB222 use: {} def: {V38} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB223 use: {V17} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} BB224 use: {V01 V05} def: {V55} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144 V179} BB225 use: {} def: {V55} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144 V179} BB226 use: {V00 V03 V18 V37 V38 V55} def: {V09} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB227 use: {V00} def: {V129} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144 V179} BB228 use: {V00 V18 V129} def: {V130} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB229 use: {V00 V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB230 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB231 use: {V16 V34} def: {V175} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} BB232 use: {V175} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} BB233 use: {V00 V16 V175} def: {V16 V52 V132 V133} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144 V179} BB234 use: {V00 V132 V133} def: {V134} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB235 use: {V00 V133} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V133 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB236 use: {V00 V16 V173} def: {V16 V53 V136 V137} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V173 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144 V179} BB237 use: {V00 V136 V137} def: {V138} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB238 use: {V00 V137} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V137 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB239 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB240 use: {V16 V34} def: {V173} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V173 V179} BB241 use: {} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB242 use: {V00} def: {V140} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144 V179} BB243 use: {V00 V18 V140} def: {V141} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB244 use: {V00 V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} BB110 use: {} def: {} in: {} out: {} BB254 use: {} def: {} in: {} out: {} Interval 0: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 0: (V00) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 1: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 1: (V01) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Local V02 should not be enregistered because: struct size does not match reg size Interval 2: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 2: (V03) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 3: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 3: (V04) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 4: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 4: (V05) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 5: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 5: (V06) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 6: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 6: (V07) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 7: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 7: (V08) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 8: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 8: (V09) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 9: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 9: (V10) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 10: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 10: (V11) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 11: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 11: (V12) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 12: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 12: (V13) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 13: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 13: (V14) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 14: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 14: (V15) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 15: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 15: (V16) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 16: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 16: (V17) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 17: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 17: (V18) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 18: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 18: (V20) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 19: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 19: (V21) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 20: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 20: (V22) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 21: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 21: (V26) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 22: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 22: (V27) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 23: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 23: (V28) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 24: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 24: (V29) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 25: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 25: (V30) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 26: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 26: (V31) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 27: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 27: (V32) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 28: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 28: (V33) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 29: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 29: (V34) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 30: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 30: (V36) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 31: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 31: (V37) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 32: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 32: (V38) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 33: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 33: (V43) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 34: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 34: (V44) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 35: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 35: (V45) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 36: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 36: (V46) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 37: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 37: (V49) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 38: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 38: (V50) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 39: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 39: (V51) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 40: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 40: (V52) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 41: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 41: (V53) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 42: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 42: (V54) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 43: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 43: (V55) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 44: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 44: (V56) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 45: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 45: (V57) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 46: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 46: (V58) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 47: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 47: (V59) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 48: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 48: (V61) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 49: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 49: (V63) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 50: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 50: (V64) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 51: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 51: (V65) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 52: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 52: (V66) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 53: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 53: (V67) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 54: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 54: (V69) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 55: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 55: (V70) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 56: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 56: (V71) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 57: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 57: (V72) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 58: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 58: (V73) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 59: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 59: (V74) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 60: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 60: (V76) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 61: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 61: (V83) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 62: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 62: (V86) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 63: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 63: (V87) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 64: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 64: (V88) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 65: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 65: (V91) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 66: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 66: (V92) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 67: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 67: (V93) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 68: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 68: (V95) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 69: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 69: (V96) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 70: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 70: (V97) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 71: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 71: (V99) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 72: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 72: (V100) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 73: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 73: (V102) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 74: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 74: (V103) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 75: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 75: (V104) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 76: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 76: (V106) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 77: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 77: (V107) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 78: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 78: (V108) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 79: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 79: (V110) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 80: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 80: (V111) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 81: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 81: (V112) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 82: ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 82: (V114) ref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 83: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 83: (V115) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 84: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 84: (V116) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 85: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 85: (V118) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 86: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 86: (V119) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 87: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 87: (V120) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 88: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 88: (V122) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 89: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 89: (V123) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 90: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 90: (V124) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 91: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 91: (V126) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 92: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 92: (V127) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 93: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 93: (V129) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 94: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 94: (V130) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 95: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 95: (V132) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 96: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 96: (V133) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 97: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 97: (V134) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 98: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 98: (V136) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 99: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 99: (V137) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 100: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 100: (V138) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 101: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 101: (V140) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 102: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 102: (V141) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 103: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 103: (V143) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 104: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 104: (V144) int (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 105: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 105: (V147) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 106: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 106: (V148) int (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 107: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 107: (V149) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 108: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 108: (V150) int (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 109: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 109: (V151) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 110: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 110: (V155) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 111: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 111: (V156) int (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 112: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 112: (V157) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 113: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 113: (V159) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 114: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 114: (V160) int (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 115: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 115: (V161) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 116: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 116: (V163) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 117: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 117: (V164) int (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 118: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 118: (V165) byref (field) RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 119: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 119: (V167) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 120: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 120: (V168) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 121: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 121: (V169) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 122: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 122: (V171) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 123: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 123: (V172) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 124: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 124: (V173) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 125: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 125: (V174) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 126: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 126: (V175) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 127: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 127: (V176) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 128: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 128: (V177) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 129: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 129: (V178) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 130: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 130: (V179) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 131: byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 131: (V180) byref RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 132: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 132: (V181) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 133: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 133: (V182) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 134: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 134: (V183) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 135: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 135: (V184) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 136: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 136: (V185) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] FP callee save candidate vars: None floatVarCount = 0; hasLoops = true, singleExit = true ; Decided to create an EBP based frame for ETW stackwalking (IL Code Size) *************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT) Setting genSaveFpLrWithAllCalleeSavedRegisters to false Pad V170 GsCookie, size=8, stkOffs=-0x57, pad=7 Assign V170 GsCookie, size=8, stkOffs=-0x5f Pad V47 tmp7, size=16, stkOffs=-0x66, pad=7 Assign V47 tmp7, size=16, stkOffs=-0x76 Pad V02 arg2, size=16, stkOffs=-0x7d, pad=7 Assign V02 arg2, size=16, stkOffs=-0x8d Assign V04 loc0, size=4, stkOffs=-0x91 Assign V05 loc1, size=4, stkOffs=-0x95 Assign V06 loc2, size=4, stkOffs=-0x99 Assign V07 loc3, size=4, stkOffs=-0x9d Assign V08 loc4, size=4, stkOffs=-0xa1 Assign V09 loc5, size=4, stkOffs=-0xa5 Assign V10 loc6, size=4, stkOffs=-0xa9 Assign V11 loc7, size=4, stkOffs=-0xad Assign V12 loc8, size=4, stkOffs=-0xb1 Assign V13 loc9, size=4, stkOffs=-0xb5 Assign V14 loc10, size=4, stkOffs=-0xb9 Assign V15 loc11, size=4, stkOffs=-0xbd Assign V16 loc12, size=4, stkOffs=-0xc1 Pad V17 loc13, size=8, stkOffs=-0xc8, pad=7 Assign V17 loc13, size=8, stkOffs=-0xd0 Assign V18 loc14, size=4, stkOffs=-0xd4 Pad V19 loc15, size=16, stkOffs=-0xdb, pad=7 Assign V19 loc15, size=16, stkOffs=-0xeb Assign V20 loc16, size=4, stkOffs=-0xef Assign V21 loc17, size=4, stkOffs=-0xf3 Pad V22 loc18, size=8, stkOffs=-0xfa, pad=7 Assign V22 loc18, size=8, stkOffs=-0x102 Pad V23 loc19, size=8, stkOffs=-0x109, pad=7 Assign V23 loc19, size=8, stkOffs=-0x111 Assign V24 loc20, size=4, stkOffs=-0x115 Pad V25 loc21, size=16, stkOffs=-0x11c, pad=7 Assign V25 loc21, size=16, stkOffs=-0x12c Assign V27 loc23, size=4, stkOffs=-0x130 Assign V28 loc24, size=4, stkOffs=-0x134 Assign V29 loc25, size=4, stkOffs=-0x138 Assign V30 loc26, size=4, stkOffs=-0x13c Assign V31 loc27, size=4, stkOffs=-0x140 Assign V32 loc28, size=4, stkOffs=-0x144 Pad V34 loc30, size=8, stkOffs=-0x14b, pad=7 Assign V34 loc30, size=8, stkOffs=-0x153 Pad V35 loc31, size=8, stkOffs=-0x15a, pad=7 Assign V35 loc31, size=8, stkOffs=-0x162 Pad V36 loc32, size=8, stkOffs=-0x169, pad=7 Assign V36 loc32, size=8, stkOffs=-0x171 Assign V37 loc33, size=4, stkOffs=-0x175 Assign V38 loc34, size=4, stkOffs=-0x179 Assign V39 loc35, size=4, stkOffs=-0x17d Pad V41 tmp1, size=16, stkOffs=-0x184, pad=7 Assign V41 tmp1, size=16, stkOffs=-0x194 Pad V42 tmp2, size=16, stkOffs=-0x19b, pad=7 Assign V42 tmp2, size=16, stkOffs=-0x1ab Assign V43 tmp3, size=4, stkOffs=-0x1af Assign V44 tmp4, size=4, stkOffs=-0x1b3 Assign V45 tmp5, size=4, stkOffs=-0x1b7 Assign V46 tmp6, size=4, stkOffs=-0x1bb Pad V48 tmp8, size=16, stkOffs=-0x1c2, pad=7 Assign V48 tmp8, size=16, stkOffs=-0x1d2 Assign V49 tmp9, size=4, stkOffs=-0x1d6 Assign V50 tmp10, size=4, stkOffs=-0x1da Assign V51 tmp11, size=4, stkOffs=-0x1de Assign V52 tmp12, size=4, stkOffs=-0x1e2 Assign V53 tmp13, size=4, stkOffs=-0x1e6 Assign V54 tmp14, size=4, stkOffs=-0x1ea Assign V55 tmp15, size=4, stkOffs=-0x1ee Pad V56 tmp16, size=8, stkOffs=-0x1f5, pad=7 Assign V56 tmp16, size=8, stkOffs=-0x1fd Assign V57 tmp17, size=4, stkOffs=-0x201 Assign V58 tmp18, size=4, stkOffs=-0x205 Assign V59 tmp19, size=4, stkOffs=-0x209 Pad V61 tmp21, size=8, stkOffs=-0x210, pad=7 Assign V61 tmp21, size=8, stkOffs=-0x218 Assign V63 tmp23, size=4, stkOffs=-0x21c Assign V64 tmp24, size=4, stkOffs=-0x220 Assign V65 tmp25, size=4, stkOffs=-0x224 Assign V66 tmp26, size=4, stkOffs=-0x228 Assign V67 tmp27, size=4, stkOffs=-0x22c Pad V68 tmp28, size=16, stkOffs=-0x233, pad=7 Assign V68 tmp28, size=16, stkOffs=-0x243 Assign V70 tmp30, size=4, stkOffs=-0x247 Assign V71 tmp31, size=4, stkOffs=-0x24b Assign V72 tmp32, size=4, stkOffs=-0x24f Assign V73 tmp33, size=4, stkOffs=-0x253 Assign V74 tmp34, size=4, stkOffs=-0x257 Pad V75 tmp35, size=16, stkOffs=-0x25e, pad=7 Assign V75 tmp35, size=16, stkOffs=-0x26e Pad V77 tmp37, size=16, stkOffs=-0x275, pad=7 Assign V77 tmp37, size=16, stkOffs=-0x285 Pad V78 tmp38, size=16, stkOffs=-0x28c, pad=7 Assign V78 tmp38, size=16, stkOffs=-0x29c Pad V79 tmp39, size=16, stkOffs=-0x2a3, pad=7 Assign V79 tmp39, size=16, stkOffs=-0x2b3 Assign V80 tmp40, size=4, stkOffs=-0x2b7 Pad V81 tmp41, size=8, stkOffs=-0x2be, pad=7 Assign V81 tmp41, size=8, stkOffs=-0x2c6 Pad V82 tmp42, size=8, stkOffs=-0x2cd, pad=7 Assign V82 tmp42, size=8, stkOffs=-0x2d5 Pad V83 tmp43, size=8, stkOffs=-0x2dc, pad=7 Assign V83 tmp43, size=8, stkOffs=-0x2e4 Pad V84 tmp44, size=8, stkOffs=-0x2eb, pad=7 Assign V84 tmp44, size=8, stkOffs=-0x2f3 Pad V85 tmp45, size=16, stkOffs=-0x2fa, pad=7 Assign V85 tmp45, size=16, stkOffs=-0x30a Assign V87 tmp47, size=4, stkOffs=-0x30e Pad V89 tmp49, size=8, stkOffs=-0x315, pad=7 Assign V89 tmp49, size=8, stkOffs=-0x31d Pad V90 tmp50, size=16, stkOffs=-0x324, pad=7 Assign V90 tmp50, size=16, stkOffs=-0x334 Assign V91 tmp51, size=4, stkOffs=-0x338 Assign V92 tmp52, size=4, stkOffs=-0x33c Pad V94 tmp54, size=8, stkOffs=-0x343, pad=7 Assign V94 tmp54, size=8, stkOffs=-0x34b Assign V96 tmp56, size=4, stkOffs=-0x34f Pad V98 tmp58, size=8, stkOffs=-0x356, pad=7 Assign V98 tmp58, size=8, stkOffs=-0x35e Assign V99 tmp59, size=4, stkOffs=-0x362 Pad V101 tmp61, size=8, stkOffs=-0x369, pad=7 Assign V101 tmp61, size=8, stkOffs=-0x371 Assign V103 tmp63, size=4, stkOffs=-0x375 Pad V105 tmp65, size=8, stkOffs=-0x37c, pad=7 Assign V105 tmp65, size=8, stkOffs=-0x384 Assign V107 tmp67, size=4, stkOffs=-0x388 Pad V109 tmp69, size=8, stkOffs=-0x38f, pad=7 Assign V109 tmp69, size=8, stkOffs=-0x397 Assign V111 tmp71, size=4, stkOffs=-0x39b Pad V113 tmp73, size=8, stkOffs=-0x3a2, pad=7 Assign V113 tmp73, size=8, stkOffs=-0x3aa Assign V115 tmp75, size=4, stkOffs=-0x3ae Pad V117 tmp77, size=8, stkOffs=-0x3b5, pad=7 Assign V117 tmp77, size=8, stkOffs=-0x3bd Assign V118 tmp78, size=4, stkOffs=-0x3c1 Assign V119 tmp79, size=4, stkOffs=-0x3c5 Pad V121 tmp81, size=8, stkOffs=-0x3cc, pad=7 Assign V121 tmp81, size=8, stkOffs=-0x3d4 Assign V122 tmp82, size=4, stkOffs=-0x3d8 Assign V123 tmp83, size=4, stkOffs=-0x3dc Pad V125 tmp85, size=8, stkOffs=-0x3e3, pad=7 Assign V125 tmp85, size=8, stkOffs=-0x3eb Assign V126 tmp86, size=4, stkOffs=-0x3ef Pad V128 tmp88, size=8, stkOffs=-0x3f6, pad=7 Assign V128 tmp88, size=8, stkOffs=-0x3fe Assign V129 tmp89, size=4, stkOffs=-0x402 Pad V131 tmp91, size=8, stkOffs=-0x409, pad=7 Assign V131 tmp91, size=8, stkOffs=-0x411 Assign V132 tmp92, size=4, stkOffs=-0x415 Assign V133 tmp93, size=4, stkOffs=-0x419 Pad V135 tmp95, size=8, stkOffs=-0x420, pad=7 Assign V135 tmp95, size=8, stkOffs=-0x428 Assign V136 tmp96, size=4, stkOffs=-0x42c Assign V137 tmp97, size=4, stkOffs=-0x430 Pad V139 tmp99, size=8, stkOffs=-0x437, pad=7 Assign V139 tmp99, size=8, stkOffs=-0x43f Assign V140 tmp100, size=4, stkOffs=-0x443 Pad V142 tmp102, size=8, stkOffs=-0x44a, pad=7 Assign V142 tmp102, size=8, stkOffs=-0x452 Assign V144 tmp104, size=4, stkOffs=-0x456 Pad V145 tmp105, size=8, stkOffs=-0x45d, pad=7 Assign V145 tmp105, size=8, stkOffs=-0x465 Assign V146 tmp106, size=4, stkOffs=-0x469 Assign V148 tmp108, size=4, stkOffs=-0x46d Assign V150 tmp110, size=4, stkOffs=-0x471 Assign V152 tmp112, size=4, stkOffs=-0x475 Pad V153 tmp113, size=8, stkOffs=-0x47c, pad=7 Assign V153 tmp113, size=8, stkOffs=-0x484 Assign V154 tmp114, size=4, stkOffs=-0x488 Assign V156 tmp116, size=4, stkOffs=-0x48c Assign V158 tmp118, size=4, stkOffs=-0x490 Assign V160 tmp120, size=4, stkOffs=-0x494 Assign V162 tmp122, size=4, stkOffs=-0x498 Assign V164 tmp124, size=4, stkOffs=-0x49c Assign V166 tmp126, size=4, stkOffs=-0x4a0 Pad V167 tmp127, size=8, stkOffs=-0x4a7, pad=7 Assign V167 tmp127, size=8, stkOffs=-0x4af Pad V168 tmp128, size=8, stkOffs=-0x4b6, pad=7 Assign V168 tmp128, size=8, stkOffs=-0x4be Pad V169 tmp129, size=8, stkOffs=-0x4c5, pad=7 Assign V169 tmp129, size=8, stkOffs=-0x4cd Assign V171 cse0, size=4, stkOffs=-0x4d1 Assign V172 cse1, size=4, stkOffs=-0x4d5 Assign V173 cse2, size=4, stkOffs=-0x4d9 Assign V174 cse3, size=4, stkOffs=-0x4dd Assign V175 cse4, size=4, stkOffs=-0x4e1 Assign V176 cse5, size=4, stkOffs=-0x4e5 Assign V177 cse6, size=4, stkOffs=-0x4e9 Assign V178 cse7, size=4, stkOffs=-0x4ed Assign V179 cse8, size=4, stkOffs=-0x4f1 Assign V181 cse10, size=4, stkOffs=-0x4f5 Assign V182 rat0, size=4, stkOffs=-0x4f9 Assign V183 rat1, size=4, stkOffs=-0x4fd Assign V184 rat2, size=4, stkOffs=-0x501 Assign V185 rat3, size=4, stkOffs=-0x505 Pad V00 arg0, size=8, stkOffs=-0x50c, pad=7 Assign V00 arg0, size=8, stkOffs=-0x514 Pad V01 arg1, size=8, stkOffs=-0x51b, pad=7 Assign V01 arg1, size=8, stkOffs=-0x523 Pad V03 arg3, size=8, stkOffs=-0x52a, pad=7 Assign V03 arg3, size=8, stkOffs=-0x532 Pad V26 loc22, size=8, stkOffs=-0x539, pad=7 Assign V26 loc22, size=8, stkOffs=-0x541 Pad V33 loc29, size=8, stkOffs=-0x548, pad=7 Assign V33 loc29, size=8, stkOffs=-0x550 Pad V60 tmp20, size=8, stkOffs=-0x557, pad=7 Assign V60 tmp20, size=8, stkOffs=-0x55f Pad V62 tmp22, size=8, stkOffs=-0x566, pad=7 Assign V62 tmp22, size=8, stkOffs=-0x56e Pad V69 tmp29, size=8, stkOffs=-0x575, pad=7 Assign V69 tmp29, size=8, stkOffs=-0x57d Pad V76 tmp36, size=8, stkOffs=-0x584, pad=7 Assign V76 tmp36, size=8, stkOffs=-0x58c Pad V86 tmp46, size=8, stkOffs=-0x593, pad=7 Assign V86 tmp46, size=8, stkOffs=-0x59b Pad V88 tmp48, size=8, stkOffs=-0x5a2, pad=7 Assign V88 tmp48, size=8, stkOffs=-0x5aa Pad V93 tmp53, size=8, stkOffs=-0x5b1, pad=7 Assign V93 tmp53, size=8, stkOffs=-0x5b9 Pad V95 tmp55, size=8, stkOffs=-0x5c0, pad=7 Assign V95 tmp55, size=8, stkOffs=-0x5c8 Pad V97 tmp57, size=8, stkOffs=-0x5cf, pad=7 Assign V97 tmp57, size=8, stkOffs=-0x5d7 Pad V100 tmp60, size=8, stkOffs=-0x5de, pad=7 Assign V100 tmp60, size=8, stkOffs=-0x5e6 Pad V102 tmp62, size=8, stkOffs=-0x5ed, pad=7 Assign V102 tmp62, size=8, stkOffs=-0x5f5 Pad V104 tmp64, size=8, stkOffs=-0x5fc, pad=7 Assign V104 tmp64, size=8, stkOffs=-0x604 Pad V106 tmp66, size=8, stkOffs=-0x60b, pad=7 Assign V106 tmp66, size=8, stkOffs=-0x613 Pad V108 tmp68, size=8, stkOffs=-0x61a, pad=7 Assign V108 tmp68, size=8, stkOffs=-0x622 Pad V110 tmp70, size=8, stkOffs=-0x629, pad=7 Assign V110 tmp70, size=8, stkOffs=-0x631 Pad V112 tmp72, size=8, stkOffs=-0x638, pad=7 Assign V112 tmp72, size=8, stkOffs=-0x640 Pad V114 tmp74, size=8, stkOffs=-0x647, pad=7 Assign V114 tmp74, size=8, stkOffs=-0x64f Pad V116 tmp76, size=8, stkOffs=-0x656, pad=7 Assign V116 tmp76, size=8, stkOffs=-0x65e Pad V120 tmp80, size=8, stkOffs=-0x665, pad=7 Assign V120 tmp80, size=8, stkOffs=-0x66d Pad V124 tmp84, size=8, stkOffs=-0x674, pad=7 Assign V124 tmp84, size=8, stkOffs=-0x67c Pad V127 tmp87, size=8, stkOffs=-0x683, pad=7 Assign V127 tmp87, size=8, stkOffs=-0x68b Pad V130 tmp90, size=8, stkOffs=-0x692, pad=7 Assign V130 tmp90, size=8, stkOffs=-0x69a Pad V134 tmp94, size=8, stkOffs=-0x6a1, pad=7 Assign V134 tmp94, size=8, stkOffs=-0x6a9 Pad V138 tmp98, size=8, stkOffs=-0x6b0, pad=7 Assign V138 tmp98, size=8, stkOffs=-0x6b8 Pad V141 tmp101, size=8, stkOffs=-0x6bf, pad=7 Assign V141 tmp101, size=8, stkOffs=-0x6c7 Pad V143 tmp103, size=8, stkOffs=-0x6ce, pad=7 Assign V143 tmp103, size=8, stkOffs=-0x6d6 Pad V147 tmp107, size=8, stkOffs=-0x6dd, pad=7 Assign V147 tmp107, size=8, stkOffs=-0x6e5 Pad V149 tmp109, size=8, stkOffs=-0x6ec, pad=7 Assign V149 tmp109, size=8, stkOffs=-0x6f4 Pad V151 tmp111, size=8, stkOffs=-0x6fb, pad=7 Assign V151 tmp111, size=8, stkOffs=-0x703 Pad V155 tmp115, size=8, stkOffs=-0x70a, pad=7 Assign V155 tmp115, size=8, stkOffs=-0x712 Pad V157 tmp117, size=8, stkOffs=-0x719, pad=7 Assign V157 tmp117, size=8, stkOffs=-0x721 Pad V159 tmp119, size=8, stkOffs=-0x728, pad=7 Assign V159 tmp119, size=8, stkOffs=-0x730 Pad V161 tmp121, size=8, stkOffs=-0x737, pad=7 Assign V161 tmp121, size=8, stkOffs=-0x73f Pad V163 tmp123, size=8, stkOffs=-0x746, pad=7 Assign V163 tmp123, size=8, stkOffs=-0x74e Pad V165 tmp125, size=8, stkOffs=-0x755, pad=7 Assign V165 tmp125, size=8, stkOffs=-0x75d Pad V180 cse9, size=8, stkOffs=-0x764, pad=7 Assign V180 cse9, size=8, stkOffs=-0x76c --- delta bump 1952 for FP frame --- virtual stack offset to actual stack offset delta is 1952 -- V00 was -1300, now 652 -- V01 was -1315, now 637 -- V02 was -141, now 1811 -- V03 was -1330, now 622 -- V04 was -145, now 1807 -- V05 was -149, now 1803 -- V06 was -153, now 1799 -- V07 was -157, now 1795 -- V08 was -161, now 1791 -- V09 was -165, now 1787 -- V10 was -169, now 1783 -- V11 was -173, now 1779 -- V12 was -177, now 1775 -- V13 was -181, now 1771 -- V14 was -185, now 1767 -- V15 was -189, now 1763 -- V16 was -193, now 1759 -- V17 was -208, now 1744 -- V18 was -212, now 1740 -- V19 was -235, now 1717 -- V20 was -239, now 1713 -- V21 was -243, now 1709 -- V22 was -258, now 1694 -- V23 was -273, now 1679 -- V24 was -277, now 1675 -- V25 was -300, now 1652 -- V26 was -1345, now 607 -- V27 was -304, now 1648 -- V28 was -308, now 1644 -- V29 was -312, now 1640 -- V30 was -316, now 1636 -- V31 was -320, now 1632 -- V32 was -324, now 1628 -- V33 was -1360, now 592 -- V34 was -339, now 1613 -- V35 was -354, now 1598 -- V36 was -369, now 1583 -- V37 was -373, now 1579 -- V38 was -377, now 1575 -- V39 was -381, now 1571 -- V40 was 0, now 1952 -- V41 was -404, now 1548 -- V42 was -427, now 1525 -- V43 was -431, now 1521 -- V44 was -435, now 1517 -- V45 was -439, now 1513 -- V46 was -443, now 1509 -- V47 was -118, now 1834 -- V48 was -466, now 1486 -- V49 was -470, now 1482 -- V50 was -474, now 1478 -- V51 was -478, now 1474 -- V52 was -482, now 1470 -- V53 was -486, now 1466 -- V54 was -490, now 1462 -- V55 was -494, now 1458 -- V56 was -509, now 1443 -- V57 was -513, now 1439 -- V58 was -517, now 1435 -- V59 was -521, now 1431 -- V60 was -1375, now 577 -- V61 was -536, now 1416 -- V62 was -1390, now 562 -- V63 was -540, now 1412 -- V64 was -544, now 1408 -- V65 was -548, now 1404 -- V66 was -552, now 1400 -- V67 was -556, now 1396 -- V68 was -579, now 1373 -- V69 was -1405, now 547 -- V70 was -583, now 1369 -- V71 was -587, now 1365 -- V72 was -591, now 1361 -- V73 was -595, now 1357 -- V74 was -599, now 1353 -- V75 was -622, now 1330 -- V76 was -1420, now 532 -- V77 was -645, now 1307 -- V78 was -668, now 1284 -- V79 was -691, now 1261 -- V80 was -695, now 1257 -- V81 was -710, now 1242 -- V82 was -725, now 1227 -- V83 was -740, now 1212 -- V84 was -755, now 1197 -- V85 was -778, now 1174 -- V86 was -1435, now 517 -- V87 was -782, now 1170 -- V88 was -1450, now 502 -- V89 was -797, now 1155 -- V90 was -820, now 1132 -- V91 was -824, now 1128 -- V92 was -828, now 1124 -- V93 was -1465, now 487 -- V94 was -843, now 1109 -- V95 was -1480, now 472 -- V96 was -847, now 1105 -- V97 was -1495, now 457 -- V98 was -862, now 1090 -- V99 was -866, now 1086 -- V100 was -1510, now 442 -- V101 was -881, now 1071 -- V102 was -1525, now 427 -- V103 was -885, now 1067 -- V104 was -1540, now 412 -- V105 was -900, now 1052 -- V106 was -1555, now 397 -- V107 was -904, now 1048 -- V108 was -1570, now 382 -- V109 was -919, now 1033 -- V110 was -1585, now 367 -- V111 was -923, now 1029 -- V112 was -1600, now 352 -- V113 was -938, now 1014 -- V114 was -1615, now 337 -- V115 was -942, now 1010 -- V116 was -1630, now 322 -- V117 was -957, now 995 -- V118 was -961, now 991 -- V119 was -965, now 987 -- V120 was -1645, now 307 -- V121 was -980, now 972 -- V122 was -984, now 968 -- V123 was -988, now 964 -- V124 was -1660, now 292 -- V125 was -1003, now 949 -- V126 was -1007, now 945 -- V127 was -1675, now 277 -- V128 was -1022, now 930 -- V129 was -1026, now 926 -- V130 was -1690, now 262 -- V131 was -1041, now 911 -- V132 was -1045, now 907 -- V133 was -1049, now 903 -- V134 was -1705, now 247 -- V135 was -1064, now 888 -- V136 was -1068, now 884 -- V137 was -1072, now 880 -- V138 was -1720, now 232 -- V139 was -1087, now 865 -- V140 was -1091, now 861 -- V141 was -1735, now 217 -- V142 was -1106, now 846 -- V143 was -1750, now 202 -- V144 was -1110, now 842 -- V145 was -1125, now 827 -- V146 was -1129, now 823 -- V147 was -1765, now 187 -- V148 was -1133, now 819 -- V149 was -1780, now 172 -- V150 was -1137, now 815 -- V151 was -1795, now 157 -- V152 was -1141, now 811 -- V153 was -1156, now 796 -- V154 was -1160, now 792 -- V155 was -1810, now 142 -- V156 was -1164, now 788 -- V157 was -1825, now 127 -- V158 was -1168, now 784 -- V159 was -1840, now 112 -- V160 was -1172, now 780 -- V161 was -1855, now 97 -- V162 was -1176, now 776 -- V163 was -1870, now 82 -- V164 was -1180, now 772 -- V165 was -1885, now 67 -- V166 was -1184, now 768 -- V167 was -1199, now 753 -- V168 was -1214, now 738 -- V169 was -1229, now 723 -- V170 was -95, now 1857 -- V171 was -1233, now 719 -- V172 was -1237, now 715 -- V173 was -1241, now 711 -- V174 was -1245, now 707 -- V175 was -1249, now 703 -- V176 was -1253, now 699 -- V177 was -1257, now 695 -- V178 was -1261, now 691 -- V179 was -1265, now 687 -- V180 was -1900, now 52 -- V181 was -1269, now 683 -- V182 was -1273, now 679 -- V183 was -1277, now 675 -- V184 was -1281, now 671 -- V185 was -1285, now 667 compRsvdRegCheck frame size = 1952 compArgSize = 40 Returning true (ARM64) Reserved REG_OPT_RSVD (xip1) due to large frame TUPLE STYLE DUMP BEFORE LSRA Start LSRA Block Sequence: Current block: BB01 Succ block: BB02, Criteria: weight, Worklist: [BB02 ] Succ block: BB05, Criteria: bbNum, Worklist: [BB02 BB05 ] Current block: BB02 Succ block: BB03, Criteria: bbNum, Worklist: [BB03 BB05 ] Succ block: BB04, Criteria: bbNum, Worklist: [BB03 BB04 BB05 ] Current block: BB03 Succ block: BB06, Criteria: bbNum, Worklist: [BB04 BB05 BB06 ] Current block: BB04 Current block: BB05 Current block: BB06 Succ block: BB07, Criteria: bbNum, Worklist: [BB07 ] Current block: BB07 Succ block: BB47, Criteria: bbNum, Worklist: [BB47 ] Current block: BB47 Succ block: BB48, Criteria: bbNum, Worklist: [BB48 ] Succ block: BB50, Criteria: bbNum, Worklist: [BB48 BB50 ] Current block: BB48 Succ block: BB49, Criteria: bbNum, Worklist: [BB49 BB50 ] Current block: BB49 Succ block: BB08, Criteria: bbNum, Worklist: [BB08 BB50 ] Current block: BB08 Succ block: BB09, Criteria: bbNum, Worklist: [BB09 BB50 ] Succ block: BB13, Criteria: bbNum, Worklist: [BB09 BB13 BB50 ] Current block: BB09 Succ block: BB255, Criteria: bbNum, Worklist: [BB13 BB50 BB255 ] Succ block: BB10, Criteria: bbNum, Worklist: [BB10 BB13 BB50 BB255 ] Current block: BB10 Succ block: BB256, Criteria: bbNum, Worklist: [BB13 BB50 BB255 BB256 ] Succ block: BB11, Criteria: bbNum, Worklist: [BB11 BB13 BB50 BB255 BB256 ] Current block: BB11 Succ block: BB12, Criteria: bbNum, Worklist: [BB12 BB13 BB50 BB255 BB256 ] Succ block: BB38, Criteria: bbNum, Worklist: [BB12 BB13 BB38 BB50 BB255 BB256 ] Current block: BB12 Current block: BB13 Succ block: BB14, Criteria: bbNum, Worklist: [BB14 BB38 BB50 BB255 BB256 ] Succ block: BB35, Criteria: bbNum, Worklist: [BB14 BB35 BB38 BB50 BB255 BB256 ] Current block: BB14 Succ block: BB15, Criteria: bbNum, Worklist: [BB15 BB35 BB38 BB50 BB255 BB256 ] Current block: BB15 Succ block: BB16, Criteria: bbNum, Worklist: [BB16 BB35 BB38 BB50 BB255 BB256 ] Current block: BB16 Current block: BB35 Succ block: BB36, Criteria: bbNum, Worklist: [BB36 BB38 BB50 BB255 BB256 ] Current block: BB36 Current block: BB38 Succ block: BB39, Criteria: bbNum, Worklist: [BB39 BB50 BB255 BB256 ] Succ block: BB40, Criteria: bbNum, Worklist: [BB39 BB40 BB50 BB255 BB256 ] Current block: BB39 Succ block: BB44, Criteria: bbNum, Worklist: [BB40 BB44 BB50 BB255 BB256 ] Current block: BB40 Succ block: BB41, Criteria: bbNum, Worklist: [BB41 BB44 BB50 BB255 BB256 ] Current block: BB41 Succ block: BB42, Criteria: bbNum, Worklist: [BB42 BB44 BB50 BB255 BB256 ] Succ block: BB43, Criteria: bbNum, Worklist: [BB42 BB43 BB44 BB50 BB255 BB256 ] Current block: BB42 Current block: BB43 Current block: BB44 Succ block: BB45, Criteria: bbNum, Worklist: [BB45 BB50 BB255 BB256 ] Succ block: BB46, Criteria: bbNum, Worklist: [BB45 BB46 BB50 BB255 BB256 ] Current block: BB45 Current block: BB46 Current block: BB50 Succ block: BB51, Criteria: bbNum, Worklist: [BB51 BB255 BB256 ] Succ block: BB52, Criteria: bbNum, Worklist: [BB51 BB52 BB255 BB256 ] Current block: BB51 Current block: BB52 Succ block: BB53, Criteria: bbNum, Worklist: [BB53 BB255 BB256 ] Succ block: BB56, Criteria: bbNum, Worklist: [BB53 BB56 BB255 BB256 ] Current block: BB53 Succ block: BB54, Criteria: bbNum, Worklist: [BB54 BB56 BB255 BB256 ] Succ block: BB55, Criteria: bbNum, Worklist: [BB54 BB55 BB56 BB255 BB256 ] Current block: BB54 Current block: BB55 Current block: BB56 Succ block: BB57, Criteria: bbNum, Worklist: [BB57 BB255 BB256 ] Succ block: BB63, Criteria: bbNum, Worklist: [BB57 BB63 BB255 BB256 ] Current block: BB57 Succ block: BB58, Criteria: bbNum, Worklist: [BB58 BB63 BB255 BB256 ] Succ block: BB59, Criteria: bbNum, Worklist: [BB58 BB59 BB63 BB255 BB256 ] Current block: BB58 Succ block: BB60, Criteria: bbNum, Worklist: [BB59 BB60 BB63 BB255 BB256 ] Current block: BB59 Current block: BB60 Succ block: BB61, Criteria: bbNum, Worklist: [BB61 BB63 BB255 BB256 ] Succ block: BB66, Criteria: bbNum, Worklist: [BB61 BB63 BB66 BB255 BB256 ] Current block: BB61 Succ block: BB62, Criteria: bbNum, Worklist: [BB62 BB63 BB66 BB255 BB256 ] Current block: BB62 Current block: BB63 Succ block: BB64, Criteria: bbNum, Worklist: [BB64 BB66 BB255 BB256 ] Succ block: BB65, Criteria: bbNum, Worklist: [BB64 BB65 BB66 BB255 BB256 ] Current block: BB64 Current block: BB65 Current block: BB66 Succ block: BB73, Criteria: bbNum, Worklist: [BB73 BB255 BB256 ] Succ block: BB74, Criteria: bbNum, Worklist: [BB73 BB74 BB255 BB256 ] Current block: BB73 Succ block: BB78, Criteria: bbNum, Worklist: [BB74 BB78 BB255 BB256 ] Current block: BB74 Current block: BB78 Succ block: BB79, Criteria: bbNum, Worklist: [BB79 BB255 BB256 ] Succ block: BB103, Criteria: bbNum, Worklist: [BB79 BB103 BB255 BB256 ] Current block: BB79 Succ block: BB81, Criteria: bbNum, Worklist: [BB81 BB103 BB255 BB256 ] Succ block: BB82, Criteria: bbNum, Worklist: [BB81 BB82 BB103 BB255 BB256 ] Current block: BB81 Current block: BB82 Succ block: BB83, Criteria: bbNum, Worklist: [BB83 BB103 BB255 BB256 ] Succ block: BB84, Criteria: bbNum, Worklist: [BB83 BB84 BB103 BB255 BB256 ] Current block: BB83 Succ block: BB85, Criteria: bbNum, Worklist: [BB84 BB85 BB103 BB255 BB256 ] Current block: BB84 Current block: BB85 Succ block: BB89, Criteria: bbNum, Worklist: [BB89 BB103 BB255 BB256 ] Current block: BB89 Succ block: BB90, Criteria: bbNum, Worklist: [BB90 BB103 BB255 BB256 ] Current block: BB90 Succ block: BB91, Criteria: bbNum, Worklist: [BB91 BB103 BB255 BB256 ] Succ block: BB100, Criteria: bbNum, Worklist: [BB91 BB100 BB103 BB255 BB256 ] Current block: BB91 Succ block: BB95, Criteria: bbNum, Worklist: [BB95 BB100 BB103 BB255 BB256 ] Succ block: BB110, Criteria: weight, Worklist: [BB95 BB100 BB103 BB255 BB256 BB110 ] Current block: BB95 Current block: BB100 Succ block: BB101, Criteria: bbNum, Worklist: [BB101 BB103 BB255 BB256 BB110 ] Succ block: BB102, Criteria: bbNum, Worklist: [BB101 BB102 BB103 BB255 BB256 BB110 ] Current block: BB101 Current block: BB102 Current block: BB103 Succ block: BB104, Criteria: bbNum, Worklist: [BB104 BB255 BB256 BB110 ] Succ block: BB112, Criteria: bbNum, Worklist: [BB104 BB112 BB255 BB256 BB110 ] Current block: BB104 Succ block: BB106, Criteria: bbNum, Worklist: [BB106 BB112 BB255 BB256 BB110 ] Current block: BB106 Succ block: BB107, Criteria: bbNum, Worklist: [BB107 BB112 BB255 BB256 BB110 ] Current block: BB107 Succ block: BB108, Criteria: bbNum, Worklist: [BB108 BB112 BB255 BB256 BB110 ] Succ block: BB111, Criteria: bbNum, Worklist: [BB108 BB111 BB112 BB255 BB256 BB110 ] Current block: BB108 Current block: BB111 Current block: BB112 Succ block: BB245, Criteria: bbNum, Worklist: [BB245 BB255 BB256 BB110 ] Current block: BB245 Succ block: BB246, Criteria: bbNum, Worklist: [BB246 BB255 BB256 BB110 ] Succ block: BB248, Criteria: bbNum, Worklist: [BB246 BB248 BB255 BB256 BB110 ] Current block: BB246 Succ block: BB247, Criteria: bbNum, Worklist: [BB247 BB248 BB255 BB256 BB110 ] Current block: BB247 Succ block: BB113, Criteria: bbNum, Worklist: [BB113 BB248 BB255 BB256 BB110 ] Current block: BB113 Succ block: BB114, Criteria: bbNum, Worklist: [BB114 BB248 BB255 BB256 BB110 ] Succ block: BB136, Criteria: bbNum, Worklist: [BB114 BB136 BB248 BB255 BB256 BB110 ] Current block: BB114 Succ block: BB115, Criteria: bbNum, Worklist: [BB115 BB136 BB248 BB255 BB256 BB110 ] Succ block: BB135, Criteria: bbNum, Worklist: [BB115 BB135 BB136 BB248 BB255 BB256 BB110 ] Current block: BB115 Succ block: BB117, Criteria: bbNum, Worklist: [BB117 BB135 BB136 BB248 BB255 BB256 BB110 ] Current block: BB117 Current block: BB135 Succ block: BB118, Criteria: bbNum, Worklist: [BB118 BB136 BB248 BB255 BB256 BB110 ] Current block: BB118 Succ block: BB119, Criteria: bbNum, Worklist: [BB119 BB136 BB248 BB255 BB256 BB110 ] Succ block: BB120, Criteria: bbNum, Worklist: [BB119 BB120 BB136 BB248 BB255 BB256 BB110 ] Current block: BB119 Succ block: BB121, Criteria: bbNum, Worklist: [BB120 BB121 BB136 BB248 BB255 BB256 BB110 ] Current block: BB120 Current block: BB121 Succ block: BB122, Criteria: bbNum, Worklist: [BB122 BB136 BB248 BB255 BB256 BB110 ] Succ block: BB123, Criteria: bbNum, Worklist: [BB122 BB123 BB136 BB248 BB255 BB256 BB110 ] Current block: BB122 Succ block: BB124, Criteria: bbNum, Worklist: [BB123 BB124 BB136 BB248 BB255 BB256 BB110 ] Current block: BB123 Current block: BB124 Succ block: BB125, Criteria: bbNum, Worklist: [BB125 BB136 BB248 BB255 BB256 BB110 ] Succ block: BB134, Criteria: bbNum, Worklist: [BB125 BB134 BB136 BB248 BB255 BB256 BB110 ] Current block: BB125 Succ block: BB127, Criteria: bbNum, Worklist: [BB127 BB134 BB136 BB248 BB255 BB256 BB110 ] Current block: BB127 Succ block: BB129, Criteria: bbNum, Worklist: [BB129 BB134 BB136 BB248 BB255 BB256 BB110 ] Succ block: BB133, Criteria: bbNum, Worklist: [BB129 BB133 BB134 BB136 BB248 BB255 BB256 BB110 ] Current block: BB129 Succ block: BB130, Criteria: bbNum, Worklist: [BB130 BB133 BB134 BB136 BB248 BB255 BB256 BB110 ] Succ block: BB132, Criteria: bbNum, Worklist: [BB130 BB132 BB133 BB134 BB136 BB248 BB255 BB256 BB110 ] Current block: BB130 Current block: BB132 Current block: BB133 Current block: BB134 Current block: BB136 Succ block: BB137, Criteria: bbNum, Worklist: [BB137 BB248 BB255 BB256 BB110 ] Succ block: BB141, Criteria: bbNum, Worklist: [BB137 BB141 BB248 BB255 BB256 BB110 ] Current block: BB137 Succ block: BB257, Criteria: bbNum, Worklist: [BB141 BB248 BB255 BB256 BB257 BB110 ] Succ block: BB138, Criteria: bbNum, Worklist: [BB138 BB141 BB248 BB255 BB256 BB257 BB110 ] Current block: BB138 Succ block: BB258, Criteria: bbNum, Worklist: [BB141 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB139, Criteria: bbNum, Worklist: [BB139 BB141 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB139 Succ block: BB140, Criteria: bbNum, Worklist: [BB140 BB141 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB205, Criteria: bbNum, Worklist: [BB140 BB141 BB205 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB140 Succ block: BB242, Criteria: bbNum, Worklist: [BB141 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB141 Succ block: BB142, Criteria: bbNum, Worklist: [BB142 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB200, Criteria: bbNum, Worklist: [BB142 BB200 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB142 Succ block: BB143, Criteria: bbNum, Worklist: [BB143 BB200 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB143 Succ block: BB144, Criteria: bbNum, Worklist: [BB144 BB200 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB144 Succ block: BB181, Criteria: bbNum, Worklist: [BB181 BB200 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB181 Succ block: BB182, Criteria: bbNum, Worklist: [BB182 BB200 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB182 Succ block: BB183, Criteria: bbNum, Worklist: [BB183 BB200 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB185, Criteria: bbNum, Worklist: [BB183 BB185 BB200 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB183 Current block: BB185 Current block: BB200 Succ block: BB201, Criteria: bbNum, Worklist: [BB201 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB201 Succ block: BB203, Criteria: bbNum, Worklist: [BB203 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB204, Criteria: bbNum, Worklist: [BB203 BB204 BB205 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB203 Current block: BB204 Current block: BB205 Succ block: BB206, Criteria: bbNum, Worklist: [BB206 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB227, Criteria: bbNum, Worklist: [BB206 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB206 Succ block: BB207, Criteria: bbNum, Worklist: [BB207 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB208, Criteria: bbNum, Worklist: [BB207 BB208 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB207 Succ block: BB218, Criteria: bbNum, Worklist: [BB208 BB218 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB208 Succ block: BB209, Criteria: bbNum, Worklist: [BB209 BB218 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB215, Criteria: bbNum, Worklist: [BB209 BB215 BB218 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB209 Succ block: BB210, Criteria: bbNum, Worklist: [BB210 BB215 BB218 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB213, Criteria: bbNum, Worklist: [BB210 BB213 BB215 BB218 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB210 Succ block: BB219, Criteria: bbNum, Worklist: [BB213 BB215 BB218 BB219 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB213 Succ block: BB214, Criteria: bbNum, Worklist: [BB214 BB215 BB218 BB219 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB214 Current block: BB215 Succ block: BB216, Criteria: bbNum, Worklist: [BB216 BB218 BB219 BB227 BB242 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB244, Criteria: bbNum, Worklist: [BB216 BB218 BB219 BB227 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB216 Current block: BB218 Current block: BB219 Succ block: BB220, Criteria: bbNum, Worklist: [BB220 BB227 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB221, Criteria: bbNum, Worklist: [BB220 BB221 BB227 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB220 Current block: BB221 Succ block: BB222, Criteria: bbNum, Worklist: [BB222 BB227 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB223, Criteria: bbNum, Worklist: [BB222 BB223 BB227 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB222 Current block: BB223 Succ block: BB224, Criteria: bbNum, Worklist: [BB224 BB227 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB225, Criteria: bbNum, Worklist: [BB224 BB225 BB227 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB224 Succ block: BB226, Criteria: bbNum, Worklist: [BB225 BB226 BB227 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB225 Current block: BB226 Current block: BB227 Succ block: BB228, Criteria: bbNum, Worklist: [BB228 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB229, Criteria: bbNum, Worklist: [BB228 BB229 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB228 Succ block: BB230, Criteria: bbNum, Worklist: [BB229 BB230 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB229 Current block: BB230 Succ block: BB231, Criteria: bbNum, Worklist: [BB231 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB231 Succ block: BB232, Criteria: bbNum, Worklist: [BB232 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB233, Criteria: bbNum, Worklist: [BB232 BB233 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB232 Succ block: BB239, Criteria: bbNum, Worklist: [BB233 BB239 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB233 Succ block: BB234, Criteria: bbNum, Worklist: [BB234 BB239 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB235, Criteria: bbNum, Worklist: [BB234 BB235 BB239 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB234 Current block: BB235 Current block: BB239 Succ block: BB240, Criteria: bbNum, Worklist: [BB240 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB240 Succ block: BB241, Criteria: bbNum, Worklist: [BB241 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB236, Criteria: bbNum, Worklist: [BB236 BB241 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB236 Succ block: BB237, Criteria: bbNum, Worklist: [BB237 BB241 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB238, Criteria: bbNum, Worklist: [BB237 BB238 BB241 BB242 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB237 Current block: BB238 Current block: BB241 Current block: BB242 Succ block: BB243, Criteria: bbNum, Worklist: [BB243 BB244 BB248 BB255 BB256 BB257 BB258 BB110 ] Current block: BB243 Current block: BB244 Current block: BB248 Succ block: BB249, Criteria: bbNum, Worklist: [BB249 BB255 BB256 BB257 BB258 BB110 ] Succ block: BB253, Criteria: bbNum, Worklist: [BB249 BB253 BB255 BB256 BB257 BB258 BB110 ] Current block: BB249 Succ block: BB251, Criteria: bbNum, Worklist: [BB251 BB253 BB255 BB256 BB257 BB258 BB110 ] Current block: BB251 Current block: BB253 Current block: BB255 Succ block: BB31, Criteria: bbNum, Worklist: [BB31 BB256 BB257 BB258 BB110 ] Succ block: BB17, Criteria: bbNum, Worklist: [BB17 BB31 BB256 BB257 BB258 BB110 ] Succ block: BB30, Criteria: bbNum, Worklist: [BB17 BB30 BB31 BB256 BB257 BB258 BB110 ] Current block: BB17 Current block: BB30 Current block: BB31 Succ block: BB32, Criteria: bbNum, Worklist: [BB32 BB256 BB257 BB258 BB110 ] Current block: BB32 Succ block: BB34, Criteria: bbNum, Worklist: [BB34 BB256 BB257 BB258 BB110 ] Current block: BB34 Current block: BB256 Succ block: BB23, Criteria: bbNum, Worklist: [BB23 BB257 BB258 BB110 ] Succ block: BB21, Criteria: bbNum, Worklist: [BB21 BB23 BB257 BB258 BB110 ] Succ block: BB18, Criteria: bbNum, Worklist: [BB18 BB21 BB23 BB257 BB258 BB110 ] Current block: BB18 Succ block: BB19, Criteria: bbNum, Worklist: [BB19 BB21 BB23 BB257 BB258 BB110 ] Succ block: BB20, Criteria: bbNum, Worklist: [BB19 BB20 BB21 BB23 BB257 BB258 BB110 ] Current block: BB19 Current block: BB20 Current block: BB21 Succ block: BB22, Criteria: bbNum, Worklist: [BB22 BB23 BB257 BB258 BB110 ] Current block: BB22 Current block: BB23 Succ block: BB24, Criteria: bbNum, Worklist: [BB24 BB257 BB258 BB110 ] Current block: BB24 Succ block: BB26, Criteria: bbNum, Worklist: [BB26 BB257 BB258 BB110 ] Succ block: BB29, Criteria: bbNum, Worklist: [BB26 BB29 BB257 BB258 BB110 ] Current block: BB26 Succ block: BB27, Criteria: bbNum, Worklist: [BB27 BB29 BB257 BB258 BB110 ] Succ block: BB28, Criteria: bbNum, Worklist: [BB27 BB28 BB29 BB257 BB258 BB110 ] Current block: BB27 Current block: BB28 Current block: BB29 Current block: BB257 Succ block: BB194, Criteria: bbNum, Worklist: [BB194 BB258 BB110 ] Succ block: BB145, Criteria: bbNum, Worklist: [BB145 BB194 BB258 BB110 ] Succ block: BB186, Criteria: bbNum, Worklist: [BB145 BB186 BB194 BB258 BB110 ] Current block: BB145 Succ block: BB146, Criteria: bbNum, Worklist: [BB146 BB186 BB194 BB258 BB110 ] Succ block: BB150, Criteria: bbNum, Worklist: [BB146 BB150 BB186 BB194 BB258 BB110 ] Current block: BB146 Succ block: BB147, Criteria: bbNum, Worklist: [BB147 BB150 BB186 BB194 BB258 BB110 ] Succ block: BB148, Criteria: bbNum, Worklist: [BB147 BB148 BB150 BB186 BB194 BB258 BB110 ] Current block: BB147 Succ block: BB149, Criteria: bbNum, Worklist: [BB148 BB149 BB150 BB186 BB194 BB258 BB110 ] Current block: BB148 Current block: BB149 Succ block: BB156, Criteria: bbNum, Worklist: [BB150 BB156 BB186 BB194 BB258 BB110 ] Current block: BB150 Succ block: BB151, Criteria: bbNum, Worklist: [BB151 BB156 BB186 BB194 BB258 BB110 ] Succ block: BB154, Criteria: bbNum, Worklist: [BB151 BB154 BB156 BB186 BB194 BB258 BB110 ] Current block: BB151 Succ block: BB152, Criteria: bbNum, Worklist: [BB152 BB154 BB156 BB186 BB194 BB258 BB110 ] Succ block: BB153, Criteria: bbNum, Worklist: [BB152 BB153 BB154 BB156 BB186 BB194 BB258 BB110 ] Current block: BB152 Succ block: BB155, Criteria: bbNum, Worklist: [BB153 BB154 BB155 BB156 BB186 BB194 BB258 BB110 ] Current block: BB153 Current block: BB154 Current block: BB155 Current block: BB156 Succ block: BB157, Criteria: bbNum, Worklist: [BB157 BB186 BB194 BB258 BB110 ] Succ block: BB170, Criteria: bbNum, Worklist: [BB157 BB170 BB186 BB194 BB258 BB110 ] Current block: BB157 Succ block: BB158, Criteria: bbNum, Worklist: [BB158 BB170 BB186 BB194 BB258 BB110 ] Succ block: BB159, Criteria: bbNum, Worklist: [BB158 BB159 BB170 BB186 BB194 BB258 BB110 ] Current block: BB158 Succ block: BB160, Criteria: bbNum, Worklist: [BB159 BB160 BB170 BB186 BB194 BB258 BB110 ] Current block: BB159 Current block: BB160 Succ block: BB161, Criteria: bbNum, Worklist: [BB161 BB170 BB186 BB194 BB258 BB110 ] Current block: BB161 Succ block: BB163, Criteria: bbNum, Worklist: [BB163 BB170 BB186 BB194 BB258 BB110 ] Current block: BB163 Succ block: BB165, Criteria: bbNum, Worklist: [BB165 BB170 BB186 BB194 BB258 BB110 ] Succ block: BB169, Criteria: bbNum, Worklist: [BB165 BB169 BB170 BB186 BB194 BB258 BB110 ] Current block: BB165 Succ block: BB166, Criteria: bbNum, Worklist: [BB166 BB169 BB170 BB186 BB194 BB258 BB110 ] Succ block: BB168, Criteria: bbNum, Worklist: [BB166 BB168 BB169 BB170 BB186 BB194 BB258 BB110 ] Current block: BB166 Current block: BB168 Current block: BB169 Current block: BB170 Current block: BB186 Succ block: BB187, Criteria: bbNum, Worklist: [BB187 BB194 BB258 BB110 ] Current block: BB187 Succ block: BB188, Criteria: bbNum, Worklist: [BB188 BB194 BB258 BB110 ] Succ block: BB190, Criteria: bbNum, Worklist: [BB188 BB190 BB194 BB258 BB110 ] Current block: BB188 Current block: BB190 Current block: BB194 Succ block: BB195, Criteria: bbNum, Worklist: [BB195 BB258 BB110 ] Succ block: BB197, Criteria: bbNum, Worklist: [BB195 BB197 BB258 BB110 ] Current block: BB195 Succ block: BB196, Criteria: bbNum, Worklist: [BB196 BB197 BB258 BB110 ] Succ block: BB198, Criteria: bbNum, Worklist: [BB196 BB197 BB198 BB258 BB110 ] Current block: BB196 Succ block: BB191, Criteria: bbNum, Worklist: [BB191 BB197 BB198 BB258 BB110 ] Current block: BB191 Succ block: BB192, Criteria: bbNum, Worklist: [BB192 BB197 BB198 BB258 BB110 ] Succ block: BB193, Criteria: bbNum, Worklist: [BB192 BB193 BB197 BB198 BB258 BB110 ] Current block: BB192 Current block: BB193 Current block: BB197 Current block: BB198 Succ block: BB199, Criteria: bbNum, Worklist: [BB199 BB258 BB110 ] Current block: BB199 Current block: BB258 Succ block: BB171, Criteria: bbNum, Worklist: [BB171 BB110 ] Current block: BB171 Succ block: BB172, Criteria: bbNum, Worklist: [BB172 BB110 ] Current block: BB172 Succ block: BB173, Criteria: bbNum, Worklist: [BB173 BB110 ] Succ block: BB174, Criteria: bbNum, Worklist: [BB173 BB174 BB110 ] Current block: BB173 Current block: BB174 Succ block: BB176, Criteria: bbNum, Worklist: [BB176 BB110 ] Succ block: BB180, Criteria: bbNum, Worklist: [BB176 BB180 BB110 ] Current block: BB176 Succ block: BB177, Criteria: bbNum, Worklist: [BB177 BB180 BB110 ] Succ block: BB179, Criteria: bbNum, Worklist: [BB177 BB179 BB180 BB110 ] Current block: BB177 Current block: BB179 Current block: BB180 Current block: BB110 Unvisited block: BB254, Criteria: weight, Worklist: [BB254 ] Current block: BB254 Final LSRA Block Sequence: BB01 ( 1 ) BB02 ( 0.50) BB03 ( 0.50) BB04 ( 0.50) BB05 ( 0.50) BB06 ( 1 ) BB07 ( 8 ) BB47 ( 64 ) critical-in critical-out BB48 ( 16 ) critical-out BB49 ( 16 ) critical-out BB08 ( 8 ) BB09 ( 8 ) BB10 ( 8 ) BB11 ( 8 ) critical-out BB12 ( 8 ) BB13 ( 8 ) BB14 ( 8 ) critical-out BB15 ( 8 ) critical-out BB16 ( 8 ) BB35 ( 8 ) critical-out BB36 ( 8 ) BB38 ( 8 ) critical-in critical-out BB39 ( 8 ) critical-out BB40 ( 8 ) critical-in critical-out BB41 ( 8 ) critical-out BB42 ( 8 ) critical-out BB43 ( 8 ) critical-in critical-out BB44 ( 64 ) critical-in critical-out BB45 ( 64 ) critical-out BB46 ( 8 ) critical-in BB50 ( 8 ) critical-in critical-out BB51 ( 2 ) BB52 ( 8 ) critical-in critical-out BB53 ( 2 ) BB54 ( 2 ) BB55 ( 2 ) BB56 ( 8 ) critical-in BB57 ( 4 ) BB58 ( 2 ) BB59 ( 2 ) BB60 ( 4 ) critical-out BB61 ( 4 ) critical-out BB62 ( 4 ) BB63 ( 0.50) critical-out BB64 ( 0.50) BB65 ( 0.50) critical-in BB66 ( 1 ) critical-in BB73 ( 0.50) BB74 ( 0.50) BB78 ( 1 ) critical-out BB79 ( 0.50) critical-out BB81 ( 0.50) BB82 ( 0.50) critical-in BB83 ( 0.50) BB84 ( 0.50) BB85 ( 0.50) critical-out BB89 ( 4 ) critical-in critical-out BB90 ( 4 ) critical-out BB91 ( 2 ) BB95 ( 2 ) BB100 ( 4 ) critical-in critical-out BB101 ( 2 ) BB102 ( 4 ) critical-in critical-out BB103 ( 1 ) critical-in critical-out BB104 ( 0.50) critical-out BB106 ( 0.50) critical-out BB107 ( 0.50) BB108 ( 0.50) BB111 ( 0.50) BB112 ( 1 ) critical-in BB245 ( 8 ) critical-in critical-out BB246 ( 4 ) critical-out BB247 ( 4 ) critical-out BB113 ( 2 ) critical-out BB114 ( 2 ) critical-out BB115 ( 2 ) critical-out BB117 ( 2 ) BB135 ( 16 ) critical-in critical-out BB118 ( 8 ) BB119 ( 8 ) BB120 ( 8 ) BB121 ( 8 ) BB122 ( 8 ) BB123 ( 8 ) BB124 ( 8 ) critical-out BB125 ( 8 ) critical-out BB127 ( 8 ) critical-out BB129 ( 8 ) BB130 ( 8 ) BB132 ( 8 ) BB133 ( 8 ) critical-in BB134 ( 8 ) critical-in BB136 ( 2 ) critical-in BB137 ( 2 ) BB138 ( 2 ) BB139 ( 2 ) critical-out BB140 ( 2 ) BB141 ( 2 ) BB142 ( 2 ) critical-out BB143 ( 2 ) critical-out BB144 ( 2 ) BB181 ( 2 ) critical-out BB182 ( 2 ) BB183 ( 2 ) BB185 ( 2 ) BB200 ( 2 ) critical-out BB201 ( 2 ) BB203 ( 2 ) BB204 ( 2 ) BB205 ( 2 ) critical-in BB206 ( 2 ) critical-out BB207 ( 2 ) critical-out BB208 ( 2 ) critical-in critical-out BB209 ( 2 ) BB210 ( 2 ) BB213 ( 2 ) critical-out BB214 ( 2 ) critical-out BB215 ( 2 ) critical-in critical-out BB216 ( 2 ) BB218 ( 8 ) critical-in BB219 ( 16 ) critical-in critical-out BB220 ( 16 ) critical-out BB221 ( 2 ) critical-in critical-out BB222 ( 2 ) BB223 ( 2 ) critical-in BB224 ( 2 ) BB225 ( 2 ) BB226 ( 2 ) BB227 ( 2 ) BB228 ( 2 ) BB229 ( 2 ) BB230 ( 2 ) critical-out BB231 ( 2 ) critical-out BB232 ( 2 ) critical-out BB233 ( 2 ) critical-in BB234 ( 2 ) BB235 ( 2 ) BB239 ( 16 ) critical-in critical-out BB240 ( 16 ) BB236 ( 8 ) BB237 ( 8 ) BB238 ( 8 ) BB241 ( 2 ) BB242 ( 2 ) critical-in critical-out BB243 ( 2 ) BB244 ( 2 ) critical-in BB248 ( 1 ) critical-in critical-out BB249 ( 0.50) critical-out BB251 ( 0.50) BB253 ( 1 ) critical-in BB255 ( 8 ) critical-out BB17 ( 8 ) BB30 ( 8 ) BB31 ( 64 ) critical-in critical-out BB32 ( 64 ) critical-out BB34 ( 8 ) BB256 ( 8 ) critical-out BB18 ( 8 ) critical-out BB19 ( 8 ) BB20 ( 8 ) critical-in BB21 ( 8 ) critical-out BB22 ( 8 ) BB23 ( 8 ) critical-out BB24 ( 8 ) critical-out BB26 ( 8 ) BB27 ( 8 ) BB28 ( 8 ) BB29 ( 8 ) critical-in BB257 ( 2 ) critical-out BB145 ( 2 ) critical-in BB146 ( 2 ) BB147 ( 2 ) BB148 ( 2 ) BB149 ( 2 ) BB150 ( 2 ) BB151 ( 2 ) BB152 ( 2 ) BB153 ( 2 ) BB154 ( 2 ) BB155 ( 2 ) BB156 ( 2 ) critical-out BB157 ( 2 ) BB158 ( 2 ) BB159 ( 2 ) BB160 ( 2 ) critical-out BB161 ( 2 ) critical-out BB163 ( 2 ) critical-out BB165 ( 2 ) BB166 ( 2 ) BB168 ( 2 ) BB169 ( 2 ) critical-in BB170 ( 2 ) critical-in BB186 ( 2 ) critical-out BB187 ( 2 ) BB188 ( 2 ) BB190 ( 2 ) BB194 ( 16 ) critical-in critical-out BB195 ( 16 ) critical-out BB196 ( 16 ) critical-out BB191 ( 8 ) BB192 ( 8 ) BB193 ( 8 ) BB197 ( 2 ) critical-in critical-out BB198 ( 2 ) critical-in critical-out BB199 ( 2 ) BB258 ( 2 ) critical-out BB171 ( 2 ) critical-out BB172 ( 2 ) critical-out BB173 ( 2 ) critical-out BB174 ( 2 ) critical-in critical-out BB176 ( 2 ) BB177 ( 2 ) BB179 ( 2 ) BB180 ( 2 ) critical-in BB110 ( 0 ) BB254 ( 0 ) BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ===== N000. IL_OFFSET INLRT @ 0x000[E-] N001. V01(t0) N000. t4185 = PUTARG_REG; t0 N002. t2543 = CNS_INT(h) 0x400000000046ac80 ftn N000. t4186 = PUTARG_REG; t2543 N003. CALL r2r_ind; t4185,t4186 N000. IL_OFFSET INLRT @ 0x006[E-] N001. CNS_INT 0 N003. V11(t4) N000. IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] N001. V01(t2546) N002. CNS_INT 16 N003. t2548 = ADD ; t2546 N005. V76(t1500); t2548 N000. IL_OFFSET INLRT @ 0x009[E-] N001. CNS_INT 0 N002. V76(t1502) N004. t2556 = LEA(b+8) ; t1502 N005. t1503 = IND ; t2556 N006. BOUNDS_CHECK_Rng -> BB254; t1503 N007. V76(t1501*) N008. t1505 = IND ; t1501* N011. V167(t2551); t1505 N012. V167(t2552*) N015. V17(t9); t2552* N001. t2558 = V02 MEM N003. V180(t3709); t2558 N004. V180(t3710) N007. V147(t2559); t3710 N008. t2561 = V02 MEM N010. V179(t3689); t2561 N011. V179(t3690) N014. V148(t2562); t3690 N000. IL_OFFSET INLRT @ 0x011[E-] N001. V17(t11) N002. t12 = IND ; t11 N003. CNS_INT 0 N004. JCMP ; t12 BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N001. V147(t2565*) N003. V155(t2566); t2565* N004. V148(t2568*) N006. V156(t2569); t2568* N001. V01(t1472) N003. t2572 = LEA(b+8) ; t1472 N004. t1473 = IND ; t2572 N005. CNS_INT 0 N006. JCMP ; t1473 BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ===== N001. V155(t2574*) N003. V149(t2575); t2574* N004. V156(t2577*) N006. V150(t2578); t2577* N001. CNS_INT 0 N003. V43(t1494) BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ===== N001. V155(t2581*) N003. V149(t2582); t2581* N004. V156(t2584*) N006. V150(t2585); t2584* N001. t1482 = CNS_INT 1 N003. V43(t1487); t1482 BB05 [025..026), preds={BB01} succs={BB06} ===== N001. V147(t2588*) N003. V149(t2589); t2588* N004. V148(t2591*) N006. V150(t2592); t2591* N001. t21 = CNS_INT 2 N003. V43(t26); t21 BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ===== N001. V149(t2596*) N000. t4187 = PUTARG_REG; t2596* N002. V150(t2597*) N000. t4188 = PUTARG_REG; t2597* N003. t2595 = FIELD_LIST; t4187,t4188 N004. V43(t29*) N000. t4189 = PUTARG_REG; t29* N005. t2594 = CNS_INT(h) 0x40000000005401e8 ftn N000. t4190 = PUTARG_REG; t2594 N006. t30 = CALL r2r_ind; t2595,t4189,t4190 N008. V15(t34); t30 BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x02D[E-] N001. CNS_INT 0 N003. V04(t37) N000. IL_OFFSET INLRT @ 0x02F[E-] N001. t38 = CNS_INT -1 N003. V05(t40); t38 N000. IL_OFFSET INLRT @ 0x031[E-] N001. t41 = CNS_INT 0x7FFFFFFF N003. V06(t43); t41 N000. IL_OFFSET INLRT @ 0x037[E-] N001. CNS_INT 0 N003. V07(t46) N000. IL_OFFSET INLRT @ 0x039[E-] N001. CNS_INT 0 N003. V09(t49) N000. IL_OFFSET INLRT @ 0x03C[E-] N001. t50 = CNS_INT -1 N003. V10(t52); t50 N000. IL_OFFSET INLRT @ 0x03F[E-] N001. CNS_INT 0 N003. V12(t55) N000. IL_OFFSET INLRT @ 0x042[E-] N001. CNS_INT 0 N003. V13(t58) N000. IL_OFFSET INLRT @ 0x045[E-] N001. V15(t59) N003. V16(t61); t59 N000. IL_OFFSET INLRT @ 0x049[E-] N001. V180(t3712) N003. V157(t2602); t3712 N000. IL_OFFSET INLRT @ 0x049[E-] N001. V157(t1512) N003. V23 MEM; t1512 N000. IL_OFFSET INLRT @ 0x051[E-] N001. V157(t69*) N003. V168(t2608); t69* N004. V168(t2609*) N007. V22(t72); t2609* BB47 [204..20F) -> BB50 (cond), preds={BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB255(2),BB256(2)} succs={BB48,BB50} ===== N000. IL_OFFSET INLRT @ 0x204[E-] N001. V16(t73) N002. V179(t3698) N003. GE ; t73,t3698 N004. JTRUE BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ===== N000. IL_OFFSET INLRT @ 0x20F[E-] N001. V16(t1198*) N003. V71(t1205); t1198* N000. IL_OFFSET INLRT @ 0x20F[E-] N001. V71(t1199) N002. CNS_INT 1 N003. t1201 = ADD ; t1199 N005. V16(t1203); t1201 N001. V22(t1197) N002. V71(t1206*) N003. t1207 = CAST ; t1206* N004. CNS_INT 1 N005. t1210 = BFIZ ; t1207 N006. t1211 = LEA(b+(i*1)+0); t1197,t1210 N007. t1212 = IND ; t1211 N009. V72(t1214); t1212 N001. V72(t1216*) N003. V18(t1218); t1216* N001. V18(t1215) N002. CNS_INT 0 N003. JCMP ; t1215 BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ===== N000. IL_OFFSET INLRT @ 0x222[E-] N001. V18(t1222) N002. CNS_INT 59 N003. NE ; t1222 N004. JTRUE BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ===== N000. IL_OFFSET INLRT @ 0x05B[E-] N001. V18(t1226) N002. CNS_INT 69 N003. GT ; t1226 N004. JTRUE BB09 [061..061) -> BB10 (cond), preds={BB08} succs={BB255,BB10} ===== N000. IL_OFFSET INLRT @ 0x061[E-] N001. V18(t1361) N002. CNS_INT -34 N003. t1363 = ADD ; t1361 N000. V182(t4192); t1363 N001. V182(t4194) N002. CNS_INT 5 N003. GT ; t4194 N004. JTRUE BB10 [083..083) -> BB11 (cond), preds={BB09} succs={BB256,BB11} ===== N000. IL_OFFSET INLRT @ 0x083[E-] N001. V18(t1365) N002. CNS_INT -44 N003. t1367 = ADD ; t1365 N000. V183(t4203); t1367 N001. V183(t4205) N002. CNS_INT 4 N003. GT ; t4205 N004. JTRUE BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ===== N000. IL_OFFSET INLRT @ 0x0A1[E-] N001. V18(t1369*) N002. CNS_INT 69 N003. EQ ; t1369* N004. JTRUE BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ===== BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ===== N000. IL_OFFSET INLRT @ 0x0AF[E-] N001. V18(t1230) N002. CNS_INT 92 N003. EQ ; t1230 N004. JTRUE BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ===== N000. IL_OFFSET INLRT @ 0x0B8[E-] N001. V18(t1257) N002. CNS_INT 101 N003. EQ ; t1257 N004. JTRUE BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ===== N000. IL_OFFSET INLRT @ 0x0C1[E-] N001. V18(t1352*) N002. t1353 = CNS_INT 0x2030 N003. NE ; t1352*,t1353 N004. JTRUE BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x137[E-] N001. V13(t1356*) N002. CNS_INT 3 N003. t1358 = ADD ; t1356* N005. V13(t1360); t1358 BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ===== N000. IL_OFFSET INLRT @ 0x175[E-] N001. V16(t1234) N002. V179(t3694) N003. t1239 = GE ; t1234,t3694 N004. V22(t1241) N005. V16(t1242) N006. t1243 = CAST ; t1242 N007. CNS_INT 1 N008. t1246 = BFIZ ; t1243 N009. t1247 = LEA(b+(i*1)+0); t1241,t1246 N010. t1248 = IND ; t1247 N012. V174(t3645); t1248 N013. V174(t3646*) N015. CNS_INT 0 N016. t1250 = EQ ; t3646* N017. AND ; t1239,t1250 N018. JTRUE ; t3730 BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x183[E-] N000. IL_OFFSET INLRT @ 0x18E[E-] N001. V16(t1252*) N002. CNS_INT 1 N003. t1254 = ADD ; t1252* N005. V16(t1256); t1254 BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ===== N000. IL_OFFSET INLRT @ 0x196[E-] N001. V16(t1261) N002. V179(t3695) N003. GE ; t1261,t3695 N004. JTRUE BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ===== N000. IL_OFFSET INLRT @ 0x1A1[E-] N001. V22(t1341) N002. V16(t1342) N003. t1343 = CAST ; t1342 N004. CNS_INT 1 N005. t1346 = BFIZ ; t1343 N006. t1347 = LEA(b+(i*1)+0); t1341,t1346 N007. t1348 = IND ; t1347 N009. V174(t3649); t1348 N010. V174(t3650*) N012. CNS_INT 48 N013. EQ ; t3650* N014. JTRUE BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ===== N000. IL_OFFSET INLRT @ 0x1AE[E-] N001. V16(t1268) N002. CNS_INT 1 N003. t1270 = ADD ; t1268 N004. V179(t3696) N005. GE ; t1270,t3696 N006. JTRUE BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ===== N000. IL_OFFSET INLRT @ 0x1BB[E-] N001. V22(t1277) N002. V16(t1278) N003. t1279 = CAST ; t1278 N004. CNS_INT 1 N005. t1282 = BFIZ ; t1279 N006. t1283 = LEA(b+(i*1)+0); t1277,t1282 N007. t1284 = IND ; t1283 N009. V174(t3653); t1284 N010. V174(t3654) N012. CNS_INT 43 N013. EQ ; t3654 N014. JTRUE BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ===== N000. IL_OFFSET INLRT @ 0x1C8[E-] N001. V174(t3656*) N002. CNS_INT 45 N003. NE ; t3656* N004. JTRUE BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ===== N000. IL_OFFSET INLRT @ 0x1D5[E-] N001. V22(t1288) N002. V16(t1289) N003. CNS_INT 1 N004. t1291 = ADD ; t1289 N005. t1292 = CAST ; t1291 N006. CNS_INT 1 N007. t1295 = BFIZ ; t1292 N008. t1296 = LEA(b+(i*1)+0); t1288,t1295 N009. t1297 = IND ; t1296 N010. CNS_INT 48 N011. NE ; t1297 N012. JTRUE BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ===== N000. IL_OFFSET INLRT @ 0x1E4[E-] N001. V16(t1301*) N002. CNS_INT 1 N003. t1303 = ADD ; t1301* N005. V73(t1305); t1303 N001. V73(t1307*) N003. V16(t1309); t1307* N001. V16(t1306) N002. V179(t3697) N003. GE ; t1306,t3697 N004. JTRUE BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ===== N000. IL_OFFSET INLRT @ 0x1F4[E-] N001. V22(t1319) N002. V16(t1320) N003. t1321 = CAST ; t1320 N004. CNS_INT 1 N005. t1324 = BFIZ ; t1321 N006. t1325 = LEA(b+(i*1)+0); t1319,t1324 N007. t1326 = IND ; t1325 N008. CNS_INT 48 N009. EQ ; t1326 N010. JTRUE BB46 [201..204), preds={BB44,BB45} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x201[E-] N001. t2613 = CNS_INT 1 N003. V09(t1318); t2613 BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ===== N000. IL_OFFSET INLRT @ 0x22B[E-] N001. CNS_INT 0 N003. V23 MEM N000. IL_OFFSET INLRT @ 0x22F[E-] N001. V05(t84) N002. CNS_INT 0 N003. GE ; t84 N004. JTRUE BB51 [233..235), preds={BB50} succs={BB52} ===== N000. IL_OFFSET INLRT @ 0x233[E-] N001. V04(t1194) N003. V05(t1196); t1194 BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ===== N000. IL_OFFSET INLRT @ 0x235[E-] N001. V10(t88) N002. CNS_INT 0 N003. LT ; t88 N004. JTRUE BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ===== N000. IL_OFFSET INLRT @ 0x23A[E-] N001. V10(t1180*) N002. V05(t1181) N003. NE ; t1180*,t1181 N004. JTRUE BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ===== N000. IL_OFFSET INLRT @ 0x23F[E-] N001. V13(t1187*) N002. V11(t1188) N003. t1189 = CNS_INT 3 N004. t1190 = MUL ; t1188,t1189 N005. t1191 = SUB ; t1187*,t1190 N007. V13(t1193); t1191 BB55 [24A..24D), preds={BB53} succs={BB56} ===== N000. IL_OFFSET INLRT @ 0x24A[E-] N001. t2615 = CNS_INT 1 N003. V12(t1186); t2615 BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ===== N000. IL_OFFSET INLRT @ 0x24D[E-] N001. V17(t92) N002. t93 = IND ; t92 N003. CNS_INT 0 N004. JCMP ; t93 BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ===== N000. IL_OFFSET INLRT @ 0x252[E-] N001. V01(t2618) N002. CNS_INT 4 N003. t2620 = ADD ; t2618 N005. V69(t1129); t2620 N001. V69(t1131) N002. t1132 = IND ; t1131 N003. V13(t1133*) N004. t1134 = ADD ; t1132,t1133* N005. V69(t1130*) N000. STOREIND ; t1130*,t1134 N000. IL_OFFSET INLRT @ 0x25E[E-] N001. V09(t1137) N002. CNS_INT 0 N003. JCMP ; t1137 BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ===== N000. IL_OFFSET INLRT @ 0x262[E-] N001. V01(t1171) N003. t2623 = LEA(b+4) ; t1171 N004. t1172 = IND ; t2623 N005. V04(t1173) N006. t1174 = ADD ; t1172,t1173 N007. V05(t1175) N008. t1176 = SUB ; t1174,t1175 N010. V70(t1178); t1176 BB59 [26E..26F), preds={BB57} succs={BB60} ===== N000. IL_OFFSET INLRT @ 0x26E[E-] N001. V04(t1141) N003. V70(t1143); t1141 BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ===== N000. IL_OFFSET INLRT @ 0x271[E-] N001. V70(t1145*) N000. t4213 = PUTARG_REG; t1145* N002. V01(t1148) N000. t4214 = PUTARG_REG; t1148 N003. t2624 = CNS_INT(h) 0x400000000046acb8 ftn N000. t4215 = PUTARG_REG; t2624 N004. t1150 = CNS_INT 0 N000. t4216 = PUTARG_REG; t1150 N005. CALL r2r_ind; t4213,t4214,t4215,t4216 N000. IL_OFFSET INLRT @ 0x27A[E-] N001. V17(t1152) N002. t1153 = IND ; t1152 N003. CNS_INT 0 N004. JCMP ; t1153 BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ===== N000. IL_OFFSET INLRT @ 0x27F[E-] N001. V180(t3713) N000. t4217 = PUTARG_REG; t3713 N002. t2628 = V02 MEM N000. t4218 = PUTARG_REG; t2628 N003. t2626 = FIELD_LIST; t4217,t4218 N004. t2625 = CNS_INT(h) 0x40000000005401e8 ftn N000. t4219 = PUTARG_REG; t2625 N005. t1158 = CNS_INT 2 N000. t4220 = PUTARG_REG; t1158 N006. t1159 = CALL r2r_ind; t2626,t4219,t4220 N008. V16(t1163); t1159 N000. IL_OFFSET INLRT @ 0x288[E-] N001. V16(t1164) N002. V15(t1165) N003. EQ ; t1164,t1165 N004. JTRUE BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ===== N000. IL_OFFSET INLRT @ 0x28E[E-] N001. V16(t1168*) N003. V15(t1170); t1168* BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ===== N000. IL_OFFSET INLRT @ 0x297[E-] N001. V01(t97) N003. t2630 = LEA(b+10); t97 N004. t98 = IND ; t2630 N005. CNS_INT 3 N006. EQ ; t98 N007. JTRUE BB64 [2A0..2A7), preds={BB63} succs={BB65} ===== N000. IL_OFFSET INLRT @ 0x2A0[E-] N001. V01(t1122) N003. t2632 = LEA(b+8) ; t1122 N005. CNS_INT 0 N000. STOREIND ; t2632 BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ===== N000. IL_OFFSET INLRT @ 0x2A7[E-] N001. V01(t102) N003. t2634 = LEA(b+4) ; t102 N005. CNS_INT 0 N000. STOREIND ; t2634 BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} ===== N000. IL_OFFSET INLRT @ 0x2AE[E-] N000. IL_OFFSET INLRT @ 0x2B2[E-] N001. V06(t106) N002. V05(t107) N003. t108 = LT ; t106,t107 N004. V05(t110) N005. V06(t111*) N006. t112 = SUB ; t110,t111* N007. CNS_INT 0 N008. t3777 = SELECT ; t108,t112 N010. V44(t1120); t3777 N000. IL_OFFSET INLRT @ 0x2B5[E-] N001. V44(t116*) N003. V06(t118); t116* N000. IL_OFFSET INLRT @ 0x2B9[E-] N000. IL_OFFSET INLRT @ 0x2BD[E-] N001. V07(t119) N002. V05(t120) N003. t121 = GT ; t119,t120 N004. V05(t123) N005. V07(t124*) N006. t125 = SUB ; t123,t124* N007. CNS_INT 0 N008. t3774 = SELECT ; t121,t125 N010. V45(t1116); t3774 N000. IL_OFFSET INLRT @ 0x2C0[E-] N001. V45(t129*) N003. V07(t131); t129* N000. IL_OFFSET INLRT @ 0x2C4[E-] N001. V09(t132) N002. CNS_INT 0 N003. JCMP ; t132 BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} ===== N000. IL_OFFSET INLRT @ 0x2C8[E-] N001. V05(t1108) N003. V08(t1110); t1108 N000. IL_OFFSET INLRT @ 0x2CB[E-] N001. CNS_INT 0 N003. V14(t1113) BB74 [2D0..2EE), preds={BB66} succs={BB78} ===== N000. IL_OFFSET INLRT @ 0x2D0[E-] N000. IL_OFFSET INLRT @ 0x2D9[E-] N001. V01(t136) N003. t2636 = LEA(b+4) ; t136 N004. t137 = IND ; t2636 N006. V178(t3683); t137 N007. V178(t3684) N009. V05(t138) N010. t139 = GT ; t3684,t138 N011. V178(t3686) N012. V05(t1104) N013. t3771 = SELECT ; t139,t3686,t1104 N015. V46(t1106); t3771 N000. IL_OFFSET INLRT @ 0x2DC[E-] N001. V46(t146*) N003. V08(t148); t146* N000. IL_OFFSET INLRT @ 0x2E4[E-] N001. V178(t3687*) N002. V05(t151) N003. t152 = SUB ; t3687*,t151 N005. V14(t154); t152 BB78 [000..30D) -> BB103 (cond), preds={BB73,BB74} succs={BB79,BB103} ===== N000. IL_OFFSET INLRT @ 0x2EE[E-] N001. V15(t155) N003. V16(t157); t155 N000. IL_OFFSET INLRT @ 0x2F2[E-] N000. IL_OFFSET INL09 @ 0x01F[E-] <- INLRT @ ??? N001. t1550 = LCL_VAR_ADDR V47 tmp7 N003. V151(t1553); t1550 N000. IL_OFFSET INL09 @ 0x026[E-] <- INLRT @ ??? N000. IL_OFFSET INLRT @ 0x2FF[E-] N001. V151(t2649*) N003. V143(t2650); t2649* N004. t3720 = CNS_INT 4 N006. V144(t2653); t3720 N000. IL_OFFSET INLRT @ 0x303[E-] N001. t175 = CNS_INT -1 N003. V20(t177); t175 N000. IL_OFFSET INLRT @ 0x306[E-] N001. V03(t941) N003. t2656 = LEA(b+56); t941 N004. t1570 = IND ; t2656 N000. t4156 = LEA(b+8) ; t1570 N005. t944 = IND ; t4156 N006. CNS_INT 0 N007. t946 = LE ; t944 N008. V12(t178) N009. CNS_INT 0 N010. t180 = EQ ; t178 N011. AND ; t946,t180 N012. JTRUE ; t3732 BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} ===== N000. IL_OFFSET INLRT @ 0x30D[E-] N000. IL_OFFSET INLRT @ 0x31E[E-] N001. V03(t948) N003. t2658 = LEA(b+8) ; t948 N004. t949 = IND ; t2658 N006. V26(t951); t949 N000. IL_OFFSET INLRT @ 0x326[E-] N001. CNS_INT 0 N003. V27(t954) N000. IL_OFFSET INLRT @ 0x329[E-] N001. CNS_INT 0 N003. V28(t957) N000. IL_OFFSET INLRT @ 0x32C[E-] N001. V26(t958) N000. t4158 = LEA(b+8) ; t958 N002. t959 = IND ; t4158 N004. V29(t961); t959 N000. IL_OFFSET INLRT @ 0x332[E-] N001. V29(t962) N002. CNS_INT 0 N003. JCMP ; t962 BB81 [336..33D), preds={BB79} succs={BB82} ===== N000. IL_OFFSET INLRT @ 0x336[E-] N002. V26(t2659) N004. t2667 = LEA(b+16); t2659 N006. t2671 = IND ; t2667 N009. V28(t1103); t2671 BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} ===== N000. IL_OFFSET INLRT @ 0x33D[E-] N001. V28(t966) N003. V30(t968); t966 N001. V08(t969) N003. V64(t975); t969 N000. IL_OFFSET INLRT @ 0x341[E-] N001. V14(t970) N002. CNS_INT 0 N003. LT ; t970 N004. JTRUE BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ===== N001. V64(t977*) N003. V65(t1093); t977* N001. CNS_INT 0 N003. V66(t1096) BB84 [34B..34D), preds={BB82} succs={BB85} ===== N001. V64(t978*) N003. V65(t981); t978* N001. V14(t979) N003. V66(t984); t979 BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} ===== N001. V65(t986*) N002. V66(t987*) N003. t988 = ADD ; t986*,t987* N005. V31(t990); t988 N000. IL_OFFSET INLRT @ 0x350[E-] N000. IL_OFFSET INLRT @ 0x355[E-] N001. V06(t991) N002. V31(t992) N003. t993 = GT ; t991,t992 N004. V06(t995) N005. V31(t1087*) N006. t3768 = SELECT ; t993,t995,t1087* N008. V67(t1089); t3768 N000. IL_OFFSET INLRT @ 0x359[E-] N001. V67(t999*) N003. V32(t1001); t999* N000. IL_OFFSET INLRT @ 0x3C2[E-] N001. V32(t3158) N002. V30(t3159) N003. LE ; t3158,t3159 N004. JTRUE BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} ===== N000. IL_OFFSET INLRT @ 0x35E[E-] N001. V30(t1006) N002. CNS_INT 0 N003. JCMP ; t1006 BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ===== N000. IL_OFFSET INLRT @ 0x362[E-] N001. V20(t1010*) N002. CNS_INT 1 N003. t1012 = ADD ; t1010* N005. V20(t1014); t1012 N000. IL_OFFSET INLRT @ 0x368[E-] N001. V20(t1015) N002. V144(t1574) N003. LT ; t1015,t1574 N004. JTRUE BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} ===== N000. IL_OFFSET INLRT @ 0x373[E-] N001. V144(t1578) N002. CNS_INT 1 N003. t1066 = LSH ; t1578 N004. t1067 = CAST ; t1066 N000. t4221 = PUTARG_REG; t1067 N005. t2672 = CNS_INT(h) 0x4000000000421858 ftn N000. t4222 = PUTARG_REG; t2672 N006. t1068 = CALL help r2r_ind; t4221,t4222 N008. V33(t1070); t1068 N000. IL_OFFSET INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] N000. IL_OFFSET INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001. V33(t2689) N002. CNS_INT 16 Fseq[] N003. t2691 = ADD ; t2689 N005. V159(t1604); t2691 N000. IL_OFFSET INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N001. V33(t1607) N000. t4160 = LEA(b+8) ; t1607 N002. t1608 = IND ; t4160 N004. V160(t1610); t1608 N001. V159(t2694*) N003. V161(t2695); t2694* N001. V144(t1620) N002. V160(t1647*) N003. GT ; t1620,t1647* N004. JTRUE BB95 [000..392), preds={BB91} succs={BB100} ===== N000. IL_OFFSET INL17 @ 0x00F[E-] <- INLRT @ ??? N001. V144(t1639*) N002. t1640 = CAST ; t1639* N004. V83(t1673); t1640 N000. IL_OFFSET INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? N001. V83(t1663*) N002. CNS_INT 2 N003. t1666 = LSH ; t1663* N000. t4223 = PUTARG_REG; t1666 N004. V161(t1661*) N000. t4224 = PUTARG_REG; t1661* N005. V143(t1662*) N000. t4225 = PUTARG_REG; t1662* N006. t2700 = CNS_INT(h) 0x4000000000420490 ftn N000. t4226 = PUTARG_REG; t2700 N007. CALL r2r_ind; t4223,t4224,t4225,t4226 N000. IL_OFFSET INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] N000. IL_OFFSET INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001. V33(t2718) N002. CNS_INT 16 Fseq[] N003. t2720 = ADD ; t2718 N005. V163(t1716); t2720 N000. IL_OFFSET INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N001. V33(t1719*) N000. t4162 = LEA(b+8) ; t1719* N002. t1720 = IND ; t4162 N004. V164(t1722); t1720 N000. IL_OFFSET INLRT @ 0x391[E-] N001. V163(t2723*) N003. V143(t2724); t2723* N004. V164(t2726*) N006. V144(t2727); t2726* BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} ===== N000. IL_OFFSET INLRT @ 0x39A[E-] N001. V20(t1024) N002. V144(t1028) N003. BOUNDS_CHECK_Rng -> BB254; t1024,t1028 N004. V143(t1033) N005. V20(t1025) N006. t1030 = CAST ; t1025 N007. CNS_INT 2 N008. t1032 = BFIZ ; t1030 N009. t1034 = LEA(b+(i*1)+0); t1033,t1032 N012. V28(t1036) N000. STOREIND ; t1034,t1036 N000. IL_OFFSET INLRT @ 0x3A6[E-] N001. V27(t1039) N002. V29(t1040) N003. CNS_INT -1 N004. t1042 = ADD ; t1040 N005. GE ; t1039,t1042 N006. JTRUE BB101 [3AE..3BB), preds={BB100} succs={BB102} ===== N000. IL_OFFSET INLRT @ 0x3AE[E-] N001. V27(t1050*) N002. CNS_INT 1 N003. t1052 = ADD ; t1050* N005. V27(t1054); t1052 N000. IL_OFFSET INLRT @ 0x3B4[E-] N001. V27(t1056) N002. V26(t1055) N000. t4164 = LEA(b+8) ; t1055 N003. t2732 = IND ; t4164 N004. BOUNDS_CHECK_Rng -> BB254; t1056,t2732 N005. V26(t2730) N006. CNS_INT 16 N007. t2738 = ADD ; t2730 N008. V27(t2731) N009. t2734 = CAST ; t2731 N010. CNS_INT 2 N011. t2736 = BFIZ ; t2734 N012. t2739 = LEA(b+(i*1)+0); t2738,t2736 N014. t2742 = IND ; t2739 N017. V30(t1060); t2742 BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ===== N000. IL_OFFSET INLRT @ 0x3BB[E-] N001. V28(t1045*) N002. V30(t1046) N003. t1047 = ADD ; t1045*,t1046 N005. V28(t1049); t1047 N000. IL_OFFSET INLRT @ 0x3C2[E-] N001. V32(t1002) N002. V28(t1003) N003. GT ; t1002,t1003 N004. JTRUE BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB85,BB89,BB102} succs={BB104,BB112} ===== N000. IL_OFFSET INLRT @ 0x3C8[E-] N001. V01(t182) N003. t2744 = LEA(b+8) ; t182 N004. t183 = IND ; t2744 N005. CNS_INT 0 N006. t185 = EQ ; t183 N007. V16(t927) N008. CNS_INT 0 N009. t929 = NE ; t927 N010. AND ; t185,t929 N011. JTRUE ; t3734 BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} ===== N000. IL_OFFSET INLRT @ 0x3D0[E-] N000. IL_OFFSET INLRT @ 0x3D4[E-] N001. V01(t931) N003. t2746 = LEA(b+4) ; t931 N004. t932 = IND ; t2746 N005. CNS_INT 0 N006. JCMP ; t932 BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} ===== N000. IL_OFFSET INLRT @ 0x3DC[E-] N001. V03(t937) N003. t2748 = LEA(b+40); t937 N004. t1730 = IND ; t2748 N006. V86(t1783); t1730 N000. IL_OFFSET INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] N001. V86(t1732) N002. CNS_INT null N003. JCMP ; t1732 BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ===== N000. IL_OFFSET INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] N001. V00(t936) N003. t2750 = LEA(b+8) ; t936 N004. t1736 = IND ; t2750 N006. V87(t1738); t1736 N000. IL_OFFSET INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] N001. V86(t1739) N000. t4166 = LEA(b+8) ; t1739 N002. t1740 = IND ; t4166 N003. CNS_INT 1 N004. t1742 = NE ; t1740 N005. V87(t1747) N006. V00(t1748) N008. t2754 = LEA(b+24); t1748 N009. t1786 = IND ; t2754 N010. t1752 = GE ; t1747,t1786 N011. AND ; t1742,t1752 N012. JTRUE ; t3736 BB108 [3DC..3DD), preds={BB107} succs={BB112} ===== N000. IL_OFFSET INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] N000. IL_OFFSET INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] N001. V00(t2758) N002. CNS_INT 16 N003. t2760 = ADD ; t2758 N005. V88(t1759); t2760 N000. IL_OFFSET INL26 @ ??? <- INLRT @ 0x3DC[E-] N001. V87(t1756) N002. V88(t1761) N004. t2763 = LEA(b+8) ; t1761 N005. t1762 = IND ; t2763 N006. BOUNDS_CHECK_Rng -> BB254; t1756,t1762 N007. V88(t1760*) N008. t1767 = IND ; t1760* N009. V87(t1757) N010. t1764 = CAST ; t1757 N011. CNS_INT 1 N012. t1766 = BFIZ ; t1764 N013. t1768 = ADD ; t1767,t1766 N017. V86(t2765*) N019. t2772 = LEA(b+12); t2765* N021. t2777 = IND ; t2772 N000. STOREIND ; t1768,t2777 N000. IL_OFFSET INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] N001. V87(t1777*) N002. CNS_INT 1 N003. t1779 = ADD ; t1777* N004. V00(t1776) N006. t2779 = LEA(b+8) ; t1776 N000. STOREIND ; t2779,t1779 BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} ===== N000. IL_OFFSET INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] N001. V00(t1744) N000. t4231 = PUTARG_REG; t1744 N002. V86(t1745*) N000. t4232 = PUTARG_REG; t1745* N003. t2780 = CNS_INT(h) 0x4000000000431d58 ftn N000. t4233 = PUTARG_REG; t2780 N004. CALL r2r_ind; t4231,t4232,t4233 BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} ===== N000. IL_OFFSET INLRT @ 0x3E8[E-] N001. CNS_INT 0 N003. V21(t189) N000. IL_OFFSET INLRT @ 0x3EB[E-] N001. V180(t3714*) N003. V165(t2784); t3714* N000. IL_OFFSET INLRT @ 0x3EB[E-] N001. V165(t1792) N003. V35 MEM; t1792 N000. IL_OFFSET INLRT @ 0x3F3[E-] N001. V165(t197*) N003. V169(t2790); t197* N004. V169(t2791*) N007. V34(t200); t2791* N000. IL_OFFSET INLRT @ 0x3F8[E-] N001. V17(t201) N003. V36(t203); t201 BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB258} succs={BB246,BB248} ===== N000. IL_OFFSET INLRT @ 0x7AA[E-] N001. V16(t204) N002. V179(t3707) N003. GE ; t204,t3707 N004. JTRUE BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ===== N000. IL_OFFSET INLRT @ 0x7B5[E-] N001. V16(t243*) N003. V49(t250); t243* N000. IL_OFFSET INLRT @ 0x7B5[E-] N001. V49(t244) N002. CNS_INT 1 N003. t246 = ADD ; t244 N005. V16(t248); t246 N001. V34(t242) N002. V49(t251*) N003. t252 = CAST ; t251* N004. CNS_INT 1 N005. t255 = BFIZ ; t252 N006. t256 = LEA(b+(i*1)+0); t242,t255 N007. t257 = IND ; t256 N009. V50(t259); t257 N001. V50(t261*) N003. V18(t263); t261* N001. V18(t260) N002. CNS_INT 0 N003. JCMP ; t260 BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ===== N000. IL_OFFSET INLRT @ 0x7C8[E-] N001. V18(t267) N002. CNS_INT 59 N003. NE ; t267 N004. JTRUE BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ===== N000. IL_OFFSET INLRT @ 0x401[E-] N001. V14(t271) N002. CNS_INT 0 N003. LE ; t271 N004. JTRUE BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ===== N000. IL_OFFSET INLRT @ 0x406[E-] N001. V18(t821) N002. CNS_INT 35 N003. t823 = EQ ; t821 N004. V18(t919) N005. t920 = CNS_INT 46 N006. t921 = EQ ; t919,t920 N007. AND ; t823,t921 N008. JTRUE ; t3738 BB115 [40C..418) -> BB135 (cond), preds={BB114} succs={BB117,BB135} ===== N000. IL_OFFSET INLRT @ 0x40C[E-] N000. IL_OFFSET INLRT @ 0x412[E-] N001. V18(t923) N002. CNS_INT 48 N003. EQ ; t923 N004. JTRUE BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} ===== BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB134} succs={BB136,BB118} ===== N000. IL_OFFSET INLRT @ 0x46D[E-] N001. V14(t825) N002. CNS_INT 0 N003. GT ; t825 N004. JTRUE BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ===== N000. IL_OFFSET INLRT @ 0x41A[E-] N001. V36(t830) N002. t831 = IND ; t830 N004. V177(t3678); t831 N005. V177(t3679) N007. CNS_INT 0 N008. JCMP ; t3679 BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ===== N001. t912 = CNS_INT 48 N003. V63(t917); t912 BB120 [424..42C), preds={BB118} succs={BB121} ===== N001. V36(t840*) N003. V61(t848); t840* N001. V61(t841*) N002. CNS_INT 1 N003. t844 = ADD ; t841* N005. V36(t846); t844 N001. V177(t3681*) N003. V63(t855); t3681* BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ===== N001. V63(t858*) N002. t1796 = CAST ; t858* N004. V92(t1836); t1796 N000. IL_OFFSET INL29 @ 0x000[E-] <- INLRT @ ??? N001. V00(t857) N003. t2795 = LEA(b+8) ; t857 N004. t1797 = IND ; t2795 N006. V91(t1799); t1797 N000. IL_OFFSET INL29 @ 0x007[E-] <- INLRT @ ??? N001. V91(t1800) N002. V00(t1801) N004. t2799 = LEA(b+24); t1801 N005. t1839 = IND ; t2799 N006. GE ; t1800,t1839 N007. JTRUE BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ===== N000. IL_OFFSET INL29 @ 0x015[E-] <- INLRT @ ??? N001. V00(t2803) N002. CNS_INT 16 N003. t2805 = ADD ; t2803 N005. V93(t1815); t2805 N001. V91(t1812) N002. V93(t1817) N004. t2808 = LEA(b+8) ; t1817 N005. t1818 = IND ; t2808 N006. BOUNDS_CHECK_Rng -> BB254; t1812,t1818 N007. V93(t1816*) N008. t1823 = IND ; t1816* N009. V91(t1813) N010. t1820 = CAST ; t1813 N011. CNS_INT 1 N012. t1822 = BFIZ ; t1820 N013. t1824 = LEA(b+(i*1)+0); t1823,t1822 N016. V92(t1826*) N000. STOREIND ; t1824,t1826* N000. IL_OFFSET INL29 @ 0x023[E-] <- INLRT @ ??? N001. V91(t1830*) N002. CNS_INT 1 N003. t1832 = ADD ; t1830* N004. V00(t1829) N006. t2811 = LEA(b+8) ; t1829 N000. STOREIND ; t2811,t1832 BB123 [000..000), preds={BB121} succs={BB124} ===== N000. IL_OFFSET INL29 @ 0x02D[E-] <- INLRT @ ??? N001. V00(t1807) N000. t4234 = PUTARG_REG; t1807 N002. V92(t1808*) N000. t4235 = PUTARG_REG; t1808* N003. t2812 = CNS_INT(h) 0x4000000000435c58 ftn N000. t4236 = PUTARG_REG; t2812 N004. CALL r2r_ind; t4234,t4235,t4236 BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ===== N000. IL_OFFSET INLRT @ 0x431[E-] N001. V12(t860) N002. CNS_INT 0 N003. t862 = EQ ; t860 N004. V08(t874) N005. CNS_INT 1 N006. t876 = LE ; t874 N007. AND ; t862,t876 N008. JTRUE ; t3740 BB125 [435..43F) -> BB134 (cond), preds={BB124} succs={BB127,BB134} ===== N000. IL_OFFSET INLRT @ 0x435[E-] N000. IL_OFFSET INLRT @ 0x43A[E-] N001. V20(t885) N002. V144(t889) N003. BOUNDS_CHECK_Rng -> BB254; t885,t889 N004. V143(t894) N005. V20(t886) N006. t891 = CAST ; t886 N007. CNS_INT 2 N008. t893 = BFIZ ; t891 N009. t895 = LEA(b+(i*1)+0); t894,t893 N010. t2813 = IND ; t895 N012. CNS_INT 1 N013. t899 = ADD ; t2813 N014. V08(t882) N015. t900 = NE ; t899,t882 N016. V20(t878) N017. CNS_INT 0 N018. t880 = LT ; t878 N019. AND ; t900,t880 N020. JTRUE ; t3742 BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} ===== N000. IL_OFFSET INLRT @ 0x43F[E-] N000. IL_OFFSET INLRT @ 0x44F[E-] N001. V03(t903) N003. t2815 = LEA(b+56); t903 N004. t1843 = IND ; t2815 N006. V95(t1896); t1843 N000. IL_OFFSET INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] N001. V95(t1845) N002. CNS_INT null N003. JCMP ; t1845 BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} ===== N000. IL_OFFSET INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] N001. V00(t902) N003. t2817 = LEA(b+8) ; t902 N004. t1849 = IND ; t2817 N006. V96(t1851); t1849 N000. IL_OFFSET INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] N001. V95(t1852) N000. t4168 = LEA(b+8) ; t1852 N002. t1853 = IND ; t4168 N004. V181(t3716); t1853 N005. V181(t3717) N007. CNS_INT 1 N008. t1855 = NE ; t3717 N009. V96(t1860) N010. V00(t1861) N012. t2821 = LEA(b+24); t1861 N013. t1899 = IND ; t2821 N014. t1865 = GE ; t1860,t1899 N015. AND ; t1855,t1865 N016. JTRUE ; t3744 BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} ===== N000. IL_OFFSET INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] N000. IL_OFFSET INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] N001. V00(t2825) N002. CNS_INT 16 N003. t2827 = ADD ; t2825 N005. V97(t1872); t2827 N000. IL_OFFSET INL32 @ ??? <- INLRT @ 0x44F[E-] N001. V96(t1869) N002. V97(t1874) N004. t2830 = LEA(b+8) ; t1874 N005. t1875 = IND ; t2830 N006. BOUNDS_CHECK_Rng -> BB254; t1869,t1875 N007. V97(t1873*) N008. t1880 = IND ; t1873* N009. V96(t1870) N010. t1877 = CAST ; t1870 N011. CNS_INT 1 N012. t1879 = BFIZ ; t1877 N013. t1881 = ADD ; t1880,t1879 N016. CNS_INT 0 N017. V181(t3719*) N018. BOUNDS_CHECK_Rng -> BB254; t3719* N019. V95(t2832*) N021. t2839 = LEA(b+12); t2832* N023. t2844 = IND ; t2839 N000. STOREIND ; t1881,t2844 N000. IL_OFFSET INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] N001. V96(t1890*) N002. CNS_INT 1 N003. t1892 = ADD ; t1890* N004. V00(t1889) N006. t2846 = LEA(b+8) ; t1889 N000. STOREIND ; t2846,t1892 BB132 [44F..450), preds={BB129} succs={BB133} ===== N000. IL_OFFSET INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] N001. V00(t1857) N000. t4237 = PUTARG_REG; t1857 N002. V95(t1858*) N000. t4238 = PUTARG_REG; t1858* N003. t2847 = CNS_INT(h) 0x4000000000431d58 ftn N000. t4239 = PUTARG_REG; t2847 N004. CALL r2r_ind; t4237,t4238,t4239 BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} ===== N000. IL_OFFSET INLRT @ 0x45B[E-] N001. V20(t907*) N002. CNS_INT -1 N003. t909 = ADD ; t907* N005. V20(t911); t909 BB134 [461..46D), preds={BB124,BB125,BB133} succs={BB135} ===== N000. IL_OFFSET INLRT @ 0x461[E-] N001. V08(t864*) N002. CNS_INT -1 N003. t866 = ADD ; t864* N005. V08(t868); t866 N000. IL_OFFSET INLRT @ 0x467[E-] N001. V14(t869*) N002. CNS_INT -1 N003. t871 = ADD ; t869* N005. V14(t873); t871 BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ===== N000. IL_OFFSET INLRT @ 0x472[E-] N001. V18(t275) N002. CNS_INT 69 N003. GT ; t275 N004. JTRUE BB137 [478..478) -> BB138 (cond), preds={BB136} succs={BB257,BB138} ===== N000. IL_OFFSET INLRT @ 0x478[E-] N001. V18(t593) N002. CNS_INT -34 N003. t595 = ADD ; t593 N000. V184(t4241); t595 N001. V184(t4243) N002. CNS_INT 5 N003. GT ; t4243 N004. JTRUE BB138 [49A..49A) -> BB139 (cond), preds={BB137} succs={BB258,BB139} ===== N000. IL_OFFSET INLRT @ 0x49A[E-] N001. V18(t597) N002. CNS_INT -44 N003. t599 = ADD ; t597 N000. V185(t4252); t599 N001. V185(t4254) N002. CNS_INT 4 N003. GT ; t4254 N004. JTRUE BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ===== N000. IL_OFFSET INLRT @ 0x4B8[E-] N001. V18(t601) N002. CNS_INT 69 N003. EQ ; t601 N004. JTRUE BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ===== BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ===== N000. IL_OFFSET INLRT @ 0x4C6[E-] N001. V18(t279) N002. CNS_INT 92 N003. EQ ; t279 N004. JTRUE BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ===== N000. IL_OFFSET INLRT @ 0x4CF[E-] N001. V18(t319) N002. CNS_INT 101 N003. EQ ; t319 N004. JTRUE BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ===== N000. IL_OFFSET INLRT @ 0x4D8[E-] N001. V18(t581) N002. t582 = CNS_INT 0x2030 N003. NE ; t581,t582 N004. JTRUE BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ===== N000. IL_OFFSET INLRT @ 0x598[E-] N001. V03(t586) N003. t2849 = LEA(b+136); t586 N004. t2066 = IND ; t2849 N006. V110(t2119); t2066 BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ===== N000. IL_OFFSET INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] N001. V110(t2068) N002. CNS_INT null N003. JCMP ; t2068 BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ===== N000. IL_OFFSET INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] N001. V00(t585) N003. t2942 = LEA(b+8) ; t585 N004. t2072 = IND ; t2942 N006. V111(t2074); t2072 N000. IL_OFFSET INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] N001. V110(t2075) N000. t4178 = LEA(b+8) ; t2075 N002. t2076 = IND ; t4178 N003. CNS_INT 1 N004. t2078 = NE ; t2076 N005. V111(t2083) N006. V00(t2084) N008. t2946 = LEA(b+24); t2084 N009. t2122 = IND ; t2946 N010. t2088 = GE ; t2083,t2122 N011. AND ; t2078,t2088 N012. JTRUE ; t3756 BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ===== N000. IL_OFFSET INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] N000. IL_OFFSET INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] N001. V00(t2950) N002. CNS_INT 16 N003. t2952 = ADD ; t2950 N005. V112(t2095); t2952 N000. IL_OFFSET INL43 @ ??? <- INLRT @ 0x598[E-] N001. V111(t2092) N002. V112(t2097) N004. t2955 = LEA(b+8) ; t2097 N005. t2098 = IND ; t2955 N006. BOUNDS_CHECK_Rng -> BB254; t2092,t2098 N007. V112(t2096*) N008. t2103 = IND ; t2096* N009. V111(t2093) N010. t2100 = CAST ; t2093 N011. CNS_INT 1 N012. t2102 = BFIZ ; t2100 N013. t2104 = ADD ; t2103,t2102 N016. CNS_INT 0 N017. V110(t2106) N000. t4180 = LEA(b+8) ; t2106 N018. t2959 = IND ; t4180 N019. BOUNDS_CHECK_Rng -> BB254; t2959 N020. V110(t2957*) N022. t2964 = LEA(b+12); t2957* N024. t2969 = IND ; t2964 N000. STOREIND ; t2104,t2969 N000. IL_OFFSET INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] N001. V111(t2113*) N002. CNS_INT 1 N003. t2115 = ADD ; t2113* N004. V00(t2112) N006. t2971 = LEA(b+8) ; t2112 N000. STOREIND ; t2971,t2115 BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ===== N000. IL_OFFSET INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] N001. V00(t2080) N000. t4271 = PUTARG_REG; t2080 N002. V110(t2081*) N000. t4272 = PUTARG_REG; t2081* N003. t2972 = CNS_INT(h) 0x4000000000431d58 ftn N000. t4273 = PUTARG_REG; t2972 N004. CALL r2r_ind; t4271,t4272,t4273 BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ===== N000. IL_OFFSET INLRT @ 0x618[E-] N001. V16(t283) N002. V179(t3701) N003. t288 = GE ; t283,t3701 N004. V34(t290) N005. V16(t291) N006. t292 = CAST ; t291 N007. CNS_INT 1 N008. t295 = BFIZ ; t292 N009. t296 = LEA(b+(i*1)+0); t290,t295 N010. t297 = IND ; t296 N012. V176(t3664); t297 N013. V176(t3665) N015. CNS_INT 0 N016. t299 = EQ ; t3665 N017. AND ; t288,t299 N018. JTRUE ; t3760 BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} ===== N000. IL_OFFSET INLRT @ 0x626[E-] N000. IL_OFFSET INLRT @ 0x634[E-] N001. V16(t303*) N003. V51(t310); t303* N000. IL_OFFSET INLRT @ 0x634[E-] N001. V51(t304*) N002. CNS_INT 1 N003. t306 = ADD ; t304* N005. V16(t308); t306 N001. V176(t3667*) N003. V123(t2283); t3667* N000. IL_OFFSET INL53 @ 0x000[E-] <- INLRT @ ??? N001. V00(t301) N003. t3027 = LEA(b+8) ; t301 N004. t2244 = IND ; t3027 N006. V122(t2246); t2244 N000. IL_OFFSET INL53 @ 0x007[E-] <- INLRT @ ??? N001. V122(t2247) N002. V00(t2248) N004. t3031 = LEA(b+24); t2248 N005. t2286 = IND ; t3031 N006. GE ; t2247,t2286 N007. JTRUE BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} ===== N000. IL_OFFSET INL53 @ 0x015[E-] <- INLRT @ ??? N001. V00(t3035) N002. CNS_INT 16 N003. t3037 = ADD ; t3035 N005. V124(t2262); t3037 N001. V122(t2259) N002. V124(t2264) N004. t3040 = LEA(b+8) ; t2264 N005. t2265 = IND ; t3040 N006. BOUNDS_CHECK_Rng -> BB254; t2259,t2265 N007. V124(t2263*) N008. t2270 = IND ; t2263* N009. V122(t2260) N010. t2267 = CAST ; t2260 N011. CNS_INT 1 N012. t2269 = BFIZ ; t2267 N013. t2271 = LEA(b+(i*1)+0); t2270,t2269 N016. V123(t2273*) N000. STOREIND ; t2271,t2273* N000. IL_OFFSET INL53 @ 0x023[E-] <- INLRT @ ??? N001. V122(t2277*) N002. CNS_INT 1 N003. t2279 = ADD ; t2277* N004. V00(t2276) N006. t3043 = LEA(b+8) ; t2276 N000. STOREIND ; t3043,t2279 BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} ===== N000. IL_OFFSET INL53 @ 0x02D[E-] <- INLRT @ ??? N001. V00(t2254) N000. t4280 = PUTARG_REG; t2254 N002. V123(t2255*) N000. t4281 = PUTARG_REG; t2255* N003. t3044 = CNS_INT(h) 0x4000000000435c58 ftn N000. t4282 = PUTARG_REG; t3044 N004. CALL r2r_ind; t4280,t4281,t4282 BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ===== N000. IL_OFFSET INLRT @ 0x64D[E-] N001. CNS_INT 0 N003. V37(t325) N000. IL_OFFSET INLRT @ 0x650[E-] N001. CNS_INT 0 N003. V38(t328) N000. IL_OFFSET INLRT @ 0x653[E-] N001. V09(t329) N002. CNS_INT 0 N003. JCMP ; t329 BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ===== N000. IL_OFFSET INLRT @ 0x65A[E-] N001. V16(t419) N002. V179(t3702) N003. GE ; t419,t3702 N004. JTRUE BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ===== N000. IL_OFFSET INLRT @ 0x665[E-] N001. V34(t565) N002. V16(t566) N003. t567 = CAST ; t566 N004. CNS_INT 1 N005. t570 = BFIZ ; t567 N006. t571 = LEA(b+(i*1)+0); t565,t570 N007. t572 = IND ; t571 N009. V176(t3669); t572 N010. V176(t3670*) N012. CNS_INT 48 N013. EQ ; t3670* N014. JTRUE BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} ===== N000. IL_OFFSET INLRT @ 0x67A[E-] N001. V16(t426) N002. CNS_INT 1 N003. t428 = ADD ; t426 N004. V179(t3703) N005. GE ; t428,t3703 N006. JTRUE BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ===== N000. IL_OFFSET INLRT @ 0x687[E-] N001. V34(t538) N002. V16(t539) N003. t540 = CAST ; t539 N004. CNS_INT 1 N005. t543 = BFIZ ; t540 N006. t544 = LEA(b+(i*1)+0); t538,t543 N007. t545 = IND ; t544 N009. V176(t3673); t545 N010. V176(t3674) N012. CNS_INT 43 N013. t547 = NE ; t3674 N014. V34(t549) N015. V16(t550) N016. CNS_INT 1 N017. t552 = ADD ; t550 N018. t553 = CAST ; t552 N019. CNS_INT 1 N020. t556 = BFIZ ; t553 N021. t557 = LEA(b+(i*1)+0); t549,t556 N022. t558 = IND ; t557 N023. CNS_INT 48 N024. t560 = NE ; t558 N025. t3762 = AND ; t547,t560 N026. JTRUE ; t3762 BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} ===== N000. IL_OFFSET INLRT @ 0x694[E-] N000. IL_OFFSET INLRT @ 0x6A3[E-] N001. t3046 = CNS_INT 1 N003. V37(t564); t3046 BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} ===== N000. IL_OFFSET INLRT @ 0x6B5[E-] N001. V176(t3676*) N002. CNS_INT 45 N003. NE ; t3676* N004. JTRUE BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ===== N000. IL_OFFSET INLRT @ 0x6C2[E-] N001. V34(t458) N002. V16(t459) N003. CNS_INT 1 N004. t461 = ADD ; t459 N005. t462 = CAST ; t461 N006. CNS_INT 1 N007. t465 = BFIZ ; t462 N008. t466 = LEA(b+(i*1)+0); t458,t465 N009. t467 = IND ; t466 N010. CNS_INT 48 N011. EQ ; t467 N012. JTRUE BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} ===== N000. IL_OFFSET INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] N001. V00(t444) N003. t3048 = LEA(b+8) ; t444 N004. t2302 = IND ; t3048 N006. V126(t2304); t2302 N000. IL_OFFSET INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] N001. V126(t2305) N002. V00(t2306) N004. t3052 = LEA(b+24); t2306 N005. t2341 = IND ; t3052 N006. GE ; t2305,t2341 N007. JTRUE BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ===== N000. IL_OFFSET INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] N001. V00(t3056) N002. CNS_INT 16 N003. t3058 = ADD ; t3056 N005. V127(t2319); t3058 N000. IL_OFFSET INL58 @ ??? <- INLRT @ 0x6D1[E-] N001. V126(t2316) N002. V127(t2321) N004. t3061 = LEA(b+8) ; t2321 N005. t2322 = IND ; t3061 N006. BOUNDS_CHECK_Rng -> BB254; t2316,t2322 N007. V127(t2320*) N008. t2327 = IND ; t2320* N009. V126(t2317) N010. t2324 = CAST ; t2317 N011. CNS_INT 1 N012. t2326 = BFIZ ; t2324 N013. t2328 = LEA(b+(i*1)+0); t2327,t2326 N016. V18(t2330*) N000. STOREIND ; t2328,t2330* N000. IL_OFFSET INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] N001. V126(t2334*) N002. CNS_INT 1 N003. t2336 = ADD ; t2334* N004. V00(t2333) N006. t3064 = LEA(b+8) ; t2333 N000. STOREIND ; t3064,t2336 BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ===== N000. IL_OFFSET INLRT @ 0x6DE[E-] N001. V38(t533*) N002. CNS_INT 1 N003. t535 = ADD ; t533* N005. V38(t537); t535 BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} ===== N000. IL_OFFSET INLRT @ 0x6E4[E-] N001. V16(t471*) N002. CNS_INT 1 N003. t473 = ADD ; t471* N005. V54(t475); t473 N001. V54(t477*) N003. V16(t479); t477* N001. V16(t476) N002. V179(t3704) N003. GE ; t476,t3704 N004. JTRUE BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ===== N000. IL_OFFSET INLRT @ 0x6F4[E-] N001. V34(t522) N002. V16(t523) N003. t524 = CAST ; t523 N004. CNS_INT 1 N005. t527 = BFIZ ; t524 N006. t528 = LEA(b+(i*1)+0); t522,t527 N007. t529 = IND ; t528 N008. CNS_INT 48 N009. EQ ; t529 N010. JTRUE BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ===== N000. IL_OFFSET INLRT @ 0x701[E-] N001. V38(t486) N002. CNS_INT 10 N003. LE ; t486 N004. JTRUE BB222 [707..70B), preds={BB221} succs={BB223} ===== N000. IL_OFFSET INLRT @ 0x707[E-] N001. t519 = CNS_INT 10 N003. V38(t521); t519 BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ===== N000. IL_OFFSET INLRT @ 0x70B[E-] N001. V17(t490) N002. t491 = IND ; t490 N003. CNS_INT 0 N004. JCMP ; t491 BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ===== N000. IL_OFFSET INLRT @ 0x710[E-] N001. V01(t512) N003. t3067 = LEA(b+4) ; t512 N004. t513 = IND ; t3067 N005. V05(t514) N006. t515 = SUB ; t513,t514 N008. V55(t517); t515 BB225 [71A..71B), preds={BB223} succs={BB226} ===== N000. IL_OFFSET INLRT @ 0x71A[E-] N001. CNS_INT 0 N003. V55(t497) BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ===== N000. IL_OFFSET INLRT @ 0x71D[E-] N001. V37(t507*) N000. t4283 = PUTARG_REG; t507* N002. V00(t502) N000. t4284 = PUTARG_REG; t502 N003. V03(t503) N000. t4285 = PUTARG_REG; t503 N004. V55(t499*) N000. t4286 = PUTARG_REG; t499* N005. V18(t505*) N000. t4287 = PUTARG_REG; t505* N006. V38(t506*) N000. t4288 = PUTARG_REG; t506* N007. t3068 = CNS_INT(h) 0x4000000000540240 ftn N000. t4289 = PUTARG_REG; t3068 N008. CALL r2r_ind; t4283,t4284,t4285,t4286,t4287,t4288,t4289 N000. IL_OFFSET INLRT @ 0x72C[E-] N001. CNS_INT 0 N003. V09(t511) BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ===== N000. IL_OFFSET INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] N001. V00(t333) N003. t3071 = LEA(b+8) ; t333 N004. t2349 = IND ; t3071 N006. V129(t2351); t2349 N000. IL_OFFSET INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] N001. V129(t2352) N002. V00(t2353) N004. t3075 = LEA(b+24); t2353 N005. t2388 = IND ; t3075 N006. GE ; t2352,t2388 N007. JTRUE BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ===== N000. IL_OFFSET INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] N001. V00(t3079) N002. CNS_INT 16 N003. t3081 = ADD ; t3079 N005. V130(t2366); t3081 N000. IL_OFFSET INL61 @ ??? <- INLRT @ 0x731[E-] N001. V129(t2363) N002. V130(t2368) N004. t3084 = LEA(b+8) ; t2368 N005. t2369 = IND ; t3084 N006. BOUNDS_CHECK_Rng -> BB254; t2363,t2369 N007. V130(t2367*) N008. t2374 = IND ; t2367* N009. V129(t2364) N010. t2371 = CAST ; t2364 N011. CNS_INT 1 N012. t2373 = BFIZ ; t2371 N013. t2375 = LEA(b+(i*1)+0); t2374,t2373 N016. V18(t2377*) N000. STOREIND ; t2375,t2377* N000. IL_OFFSET INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] N001. V129(t2381*) N002. CNS_INT 1 N003. t2383 = ADD ; t2381* N004. V00(t2380) N006. t3087 = LEA(b+8) ; t2380 N000. STOREIND ; t3087,t2383 BB229 [731..732), preds={BB227} succs={BB230} ===== N000. IL_OFFSET INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] N001. V00(t2359) N000. t4290 = PUTARG_REG; t2359 N002. V18(t334*) N000. t4291 = PUTARG_REG; t334* N003. t3088 = CNS_INT(h) 0x4000000000435c58 ftn N000. t4292 = PUTARG_REG; t3088 N004. CALL r2r_ind; t4290,t4291,t4292 BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ===== N000. IL_OFFSET INLRT @ 0x739[E-] N001. V16(t336) N002. V179(t3705) N003. GE ; t336,t3705 N004. JTRUE BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ===== N000. IL_OFFSET INLRT @ 0x744[E-] N001. V34(t343) N002. V16(t344) N003. t345 = CAST ; t344 N004. CNS_INT 1 N005. t348 = BFIZ ; t345 N006. t349 = LEA(b+(i*1)+0); t343,t348 N007. t350 = IND ; t349 N009. V175(t3658); t350 N010. V175(t3659) N012. CNS_INT 43 N013. EQ ; t3659 N014. JTRUE BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ===== N000. IL_OFFSET INLRT @ 0x751[E-] N001. V175(t3661) N002. CNS_INT 45 N003. NE ; t3661 N004. JTRUE BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ===== N000. IL_OFFSET INLRT @ 0x75E[E-] N001. V16(t356*) N003. V52(t363); t356* N000. IL_OFFSET INLRT @ 0x75E[E-] N001. V52(t357*) N002. CNS_INT 1 N003. t359 = ADD ; t357* N005. V16(t361); t359 N001. V175(t3662*) N003. V133(t2435); t3662* N000. IL_OFFSET INL64 @ 0x000[E-] <- INLRT @ ??? N001. V00(t354) N003. t3090 = LEA(b+8) ; t354 N004. t2396 = IND ; t3090 N006. V132(t2398); t2396 N000. IL_OFFSET INL64 @ 0x007[E-] <- INLRT @ ??? N001. V132(t2399) N002. V00(t2400) N004. t3094 = LEA(b+24); t2400 N005. t2438 = IND ; t3094 N006. GE ; t2399,t2438 N007. JTRUE BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ===== N000. IL_OFFSET INL64 @ 0x015[E-] <- INLRT @ ??? N001. V00(t3098) N002. CNS_INT 16 N003. t3100 = ADD ; t3098 N005. V134(t2414); t3100 N001. V132(t2411) N002. V134(t2416) N004. t3103 = LEA(b+8) ; t2416 N005. t2417 = IND ; t3103 N006. BOUNDS_CHECK_Rng -> BB254; t2411,t2417 N007. V134(t2415*) N008. t2422 = IND ; t2415* N009. V132(t2412) N010. t2419 = CAST ; t2412 N011. CNS_INT 1 N012. t2421 = BFIZ ; t2419 N013. t2423 = LEA(b+(i*1)+0); t2422,t2421 N016. V133(t2425*) N000. STOREIND ; t2423,t2425* N000. IL_OFFSET INL64 @ 0x023[E-] <- INLRT @ ??? N001. V132(t2429*) N002. CNS_INT 1 N003. t2431 = ADD ; t2429* N004. V00(t2428) N006. t3106 = LEA(b+8) ; t2428 N000. STOREIND ; t3106,t2431 BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ===== N000. IL_OFFSET INL64 @ 0x02D[E-] <- INLRT @ ??? N001. V00(t2406) N000. t4293 = PUTARG_REG; t2406 N002. V133(t2407*) N000. t4294 = PUTARG_REG; t2407* N003. t3107 = CNS_INT(h) 0x4000000000435c58 ftn N000. t4295 = PUTARG_REG; t3107 N004. CALL r2r_ind; t4293,t4294,t4295 BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ===== N000. IL_OFFSET INLRT @ 0x788[E-] N001. V16(t372) N002. V179(t3706) N003. GE ; t372,t3706 N004. JTRUE BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ===== N000. IL_OFFSET INLRT @ 0x793[E-] N001. V34(t379) N002. V16(t380) N003. t381 = CAST ; t380 N004. CNS_INT 1 N005. t384 = BFIZ ; t381 N006. t385 = LEA(b+(i*1)+0); t379,t384 N007. t386 = IND ; t385 N009. V173(t3641); t386 N010. V173(t3642) N012. CNS_INT 48 N013. EQ ; t3642 N014. JTRUE BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ===== N000. IL_OFFSET INLRT @ 0x774[E-] N001. V16(t392*) N003. V53(t399); t392* N000. IL_OFFSET INLRT @ 0x774[E-] N001. V53(t393*) N002. CNS_INT 1 N003. t395 = ADD ; t393* N005. V16(t397); t395 N001. V173(t3639*) N003. V137(t2481); t3639* N000. IL_OFFSET INL66 @ 0x000[E-] <- INLRT @ ??? N001. V00(t390) N003. t3109 = LEA(b+8) ; t390 N004. t2442 = IND ; t3109 N006. V136(t2444); t2442 N000. IL_OFFSET INL66 @ 0x007[E-] <- INLRT @ ??? N001. V136(t2445) N002. V00(t2446) N004. t3113 = LEA(b+24); t2446 N005. t2484 = IND ; t3113 N006. GE ; t2445,t2484 N007. JTRUE BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ===== N000. IL_OFFSET INL66 @ 0x015[E-] <- INLRT @ ??? N001. V00(t3117) N002. CNS_INT 16 N003. t3119 = ADD ; t3117 N005. V138(t2460); t3119 N001. V136(t2457) N002. V138(t2462) N004. t3122 = LEA(b+8) ; t2462 N005. t2463 = IND ; t3122 N006. BOUNDS_CHECK_Rng -> BB254; t2457,t2463 N007. V138(t2461*) N008. t2468 = IND ; t2461* N009. V136(t2458) N010. t2465 = CAST ; t2458 N011. CNS_INT 1 N012. t2467 = BFIZ ; t2465 N013. t2469 = LEA(b+(i*1)+0); t2468,t2467 N016. V137(t2471*) N000. STOREIND ; t2469,t2471* N000. IL_OFFSET INL66 @ 0x023[E-] <- INLRT @ ??? N001. V136(t2475*) N002. CNS_INT 1 N003. t2477 = ADD ; t2475* N004. V00(t2474) N006. t3125 = LEA(b+8) ; t2474 N000. STOREIND ; t3125,t2477 BB238 [000..000), preds={BB236} succs={BB239} ===== N000. IL_OFFSET INL66 @ 0x02D[E-] <- INLRT @ ??? N001. V00(t2452) N000. t4296 = PUTARG_REG; t2452 N002. V137(t2453*) N000. t4297 = PUTARG_REG; t2453* N003. t3126 = CNS_INT(h) 0x4000000000435c58 ftn N000. t4298 = PUTARG_REG; t3126 N004. CALL r2r_ind; t4296,t4297,t4298 BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ===== BB242 [7A2..7AA) -> BB244 (cond), preds={BB140,BB143,BB257(2),BB258(2)} succs={BB243,BB244} ===== N000. IL_OFFSET INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] N001. V00(t590) N003. t3128 = LEA(b+8) ; t590 N004. t2492 = IND ; t3128 N006. V140(t2494); t2492 N000. IL_OFFSET INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] N001. V140(t2495) N002. V00(t2496) N004. t3132 = LEA(b+24); t2496 N005. t2531 = IND ; t3132 N006. GE ; t2495,t2531 N007. JTRUE BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ===== N000. IL_OFFSET INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] N001. V00(t3136) N002. CNS_INT 16 N003. t3138 = ADD ; t3136 N005. V141(t2509); t3138 N000. IL_OFFSET INL69 @ ??? <- INLRT @ 0x7A2[E-] N001. V140(t2506) N002. V141(t2511) N004. t3141 = LEA(b+8) ; t2511 N005. t2512 = IND ; t3141 N006. BOUNDS_CHECK_Rng -> BB254; t2506,t2512 N007. V141(t2510*) N008. t2517 = IND ; t2510* N009. V140(t2507) N010. t2514 = CAST ; t2507 N011. CNS_INT 1 N012. t2516 = BFIZ ; t2514 N013. t2518 = LEA(b+(i*1)+0); t2517,t2516 N016. V18(t2520*) N000. STOREIND ; t2518,t2520* N000. IL_OFFSET INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] N001. V140(t2524*) N002. CNS_INT 1 N003. t2526 = ADD ; t2524* N004. V00(t2523) N006. t3144 = LEA(b+8) ; t2523 N000. STOREIND ; t3144,t2526 BB244 [7A2..7A3) -> BB245 (always), preds={BB215,BB242} succs={BB245} ===== N000. IL_OFFSET INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] N001. V00(t2502) N000. t4299 = PUTARG_REG; t2502 N002. V18(t591*) N000. t4300 = PUTARG_REG; t591* N003. t3145 = CNS_INT(h) 0x4000000000435c58 ftn N000. t4301 = PUTARG_REG; t3145 N004. CALL r2r_ind; t4299,t4300,t4301 BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ===== N000. IL_OFFSET INLRT @ 0x7D1[E-] N001. CNS_INT 0 N003. V35 MEM N000. IL_OFFSET INLRT @ 0x7D5[E-] N001. V01(t215) N003. t3148 = LEA(b+8) ; t215 N004. t216 = IND ; t3148 N005. CNS_INT 0 N006. t218 = EQ ; t216 N007. V15(t221*) N008. CNS_INT 0 N009. t223 = NE ; t221* N010. AND ; t218,t223 N011. JTRUE ; t3764 BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} ===== N000. IL_OFFSET INLRT @ 0x7DD[E-] N000. IL_OFFSET INLRT @ 0x7E1[E-] N001. V01(t225*) N003. t3150 = LEA(b+4) ; t225* N004. t226 = IND ; t3150 N005. CNS_INT 0 N006. t228 = NE ; t226 N007. V00(t230) N009. t3152 = LEA(b+8) ; t230 N010. t2539 = IND ; t3152 N011. CNS_INT 0 N012. t234 = LE ; t2539 N013. t3766 = AND ; t228,t234 N014. JTRUE ; t3766 BB251 [7E9..7FF), preds={BB249} succs={BB253} ===== N000. IL_OFFSET INLRT @ 0x7E9[E-] N000. IL_OFFSET INLRT @ 0x7F2[E-] N001. V03(t238*) N003. t3155 = LEA(b+40); t238* N004. t2541 = IND ; t3155 N000. t4227 = PUTARG_REG; t2541 N005. V00(t236*) N000. t4228 = PUTARG_REG; t236* N006. t3153 = CNS_INT(h) 0x4000000000540210 ftn N000. t4229 = PUTARG_REG; t3153 N007. t237 = CNS_INT 0 N000. t4230 = PUTARG_REG; t237 N008. CALL r2r_ind; t4227,t4228,t4229,t4230 BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} ===== N000. IL_OFFSET INLRT @ 0x7FF[E-] N001. RETURN BB255 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31 (switch), preds={BB09} succs={BB17,BB30,BB31,BB47} ===== N000. V182(t4198*) N000. t4199 = CAST ; t4198* N000. t4200 = JMPTABLE N000. SWITCH_TABLE; t4199,t4200 BB17 [0CF..0D8) -> BB47 (always), preds={BB255} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x0CF[E-] N001. V04(t1430*) N002. CNS_INT 1 N003. t1432 = ADD ; t1430* N005. V04(t1434); t1432 BB30 [12C..137) -> BB47 (always), preds={BB255} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x12C[E-] N001. V13(t1425*) N002. CNS_INT 2 N003. t1427 = ADD ; t1425* N005. V13(t1429); t1427 BB31 [142..150) -> BB47 (cond), preds={BB32,BB255(2)} succs={BB32,BB47} ===== N000. IL_OFFSET INLRT @ 0x142[E-] N001. V16(t1435) N002. V179(t3693) N003. t1440 = GE ; t1435,t3693 N004. V22(t1442) N005. V16(t1443) N006. t1444 = CAST ; t1443 N007. CNS_INT 1 N008. t1447 = BFIZ ; t1444 N009. t1448 = LEA(b+(i*1)+0); t1442,t1447 N010. t1449 = IND ; t1448 N012. V171(t3625); t1449 N013. V171(t3626) N015. CNS_INT 0 N016. t1451 = EQ ; t3626 N017. AND ; t1440,t1451 N018. JTRUE ; t3728 BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} ===== N000. IL_OFFSET INLRT @ 0x150[E-] N000. IL_OFFSET INLRT @ 0x15E[E-] N001. V16(t1454*) N003. V74(t1461); t1454* N000. IL_OFFSET INLRT @ 0x15E[E-] N001. V74(t1455*) N002. CNS_INT 1 N003. t1457 = ADD ; t1455* N005. V16(t1459); t1457 N001. V171(t3628*) N002. V18(t1469) N003. NE ; t3628*,t1469 N004. JTRUE BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} ===== BB256 [083..0A1) -> BB23,BB47,BB21,BB47,BB18 (switch), preds={BB10} succs={BB18,BB21,BB23,BB47} ===== N000. V183(t4209*) N000. t4210 = CAST ; t4209* N000. t4211 = JMPTABLE N000. SWITCH_TABLE; t4210,t4211 BB18 [0D8..0E0) -> BB20 (cond), preds={BB256} succs={BB19,BB20} ===== N000. IL_OFFSET INLRT @ 0x0D8[E-] N001. V06(t1373) N002. t1374 = CNS_INT 0x7FFFFFFF N003. NE ; t1373,t1374 N004. JTRUE BB19 [0E0..0E2), preds={BB18} succs={BB20} ===== N000. IL_OFFSET INLRT @ 0x0E0[E-] N001. V04(t1385) N003. V06(t1387); t1385 BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x0E2[E-] N001. V04(t1377*) N002. CNS_INT 1 N003. t1379 = ADD ; t1377* N005. V04(t1381); t1379 N000. IL_OFFSET INLRT @ 0x0E6[E-] N001. V04(t1382) N003. V07(t1384); t1382 BB21 [0ED..0F4) -> BB47 (cond), preds={BB256} succs={BB22,BB47} ===== N000. IL_OFFSET INLRT @ 0x0ED[E-] N001. V05(t1388) N002. CNS_INT 0 N003. GE ; t1388 N004. JTRUE BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x0F4[E-] N001. V04(t1392) N003. V05(t1394); t1392 BB23 [0FB..102) -> BB47 (cond), preds={BB256} succs={BB24,BB47} ===== N000. IL_OFFSET INLRT @ 0x0FB[E-] N001. V04(t1395) N002. CNS_INT 0 N003. t1397 = LE ; t1395 N004. V05(t1399) N005. CNS_INT 0 N006. t1401 = GE ; t1399 N007. AND ; t1397,t1401 N008. JTRUE ; t3726 BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} ===== N000. IL_OFFSET INLRT @ 0x102[E-] N000. IL_OFFSET INLRT @ 0x109[E-] N001. V10(t1403) N002. CNS_INT 0 N003. LT ; t1403 N004. JTRUE BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} ===== N000. IL_OFFSET INLRT @ 0x10E[E-] N001. V10(t1413) N002. V04(t1414) N003. NE ; t1413,t1414 N004. JTRUE BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x113[E-] N001. V11(t1420*) N002. CNS_INT 1 N003. t1422 = ADD ; t1420* N005. V11(t1424); t1422 BB28 [11E..121), preds={BB26} succs={BB29} ===== N000. IL_OFFSET INLRT @ 0x11E[E-] N001. t2612 = CNS_INT 1 N003. V12(t1419); t2612 BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} ===== N000. IL_OFFSET INLRT @ 0x121[E-] N001. V04(t1407) N003. V10(t1409); t1407 N000. IL_OFFSET INLRT @ 0x124[E-] N001. t1410 = CNS_INT 1 N003. V11(t1412); t1410 BB257 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194 (switch), preds={BB137} succs={BB145,BB186,BB194,BB242} ===== N000. V184(t4247*) N000. t4248 = CAST ; t4247* N000. t4249 = JMPTABLE N000. SWITCH_TABLE; t4248,t4249 BB145 [4E9..4EE) -> BB150 (cond), preds={BB257,BB258} succs={BB146,BB150} ===== N000. IL_OFFSET INLRT @ 0x4E9[E-] N001. V14(t639) N002. CNS_INT 0 N003. GE ; t639 N004. JTRUE BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ===== N000. IL_OFFSET INLRT @ 0x4EE[E-] N001. V14(t731*) N002. CNS_INT 1 N003. t733 = ADD ; t731* N005. V14(t735); t733 N000. IL_OFFSET INLRT @ 0x4F4[E-] N001. V08(t736) N002. V06(t737) N003. LE ; t736,t737 N004. JTRUE BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ===== N000. IL_OFFSET INLRT @ 0x4F9[E-] N001. CNS_INT 0 N003. V58(t749) BB148 [4FC..4FE), preds={BB146} succs={BB149} ===== N000. IL_OFFSET INLRT @ 0x4FC[E-] N001. t740 = CNS_INT 48 N003. V58(t742); t740 BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ===== N001. V58(t744*) N002. t2850 = CAST ; t744* N004. V18(t746); t2850 BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ===== N000. IL_OFFSET INLRT @ 0x502[E-] N001. V36(t643) N002. t644 = IND ; t643 N003. CNS_INT 0 N004. JCMP ; t644 BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ===== N000. IL_OFFSET INLRT @ 0x507[E-] N001. V08(t719) N002. V07(t720) N003. GT ; t719,t720 N004. JTRUE BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ===== N000. IL_OFFSET INLRT @ 0x50C[E-] N001. CNS_INT 0 N003. V57(t729) BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ===== N000. IL_OFFSET INLRT @ 0x50F[E-] N001. t723 = CNS_INT 48 N003. V57(t725); t723 BB154 [513..51B), preds={BB150} succs={BB155} ===== N000. IL_OFFSET INLRT @ 0x513[E-] N001. V36(t648*) N003. V56(t656); t648* N000. IL_OFFSET INLRT @ 0x513[E-] N001. V56(t649) N002. CNS_INT 1 N003. t652 = ADD ; t649 N005. V36(t654); t652 N001. V56(t657*) N002. t658 = IND ; t657* N004. V57(t660); t658 BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ===== N001. V57(t662*) N002. t2851 = CAST ; t662* N004. V18(t664); t2851 BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ===== N000. IL_OFFSET INLRT @ 0x51D[E-] N001. V18(t665) N002. CNS_INT 0 N003. JCMP ; t665 BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ===== N000. IL_OFFSET INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] N001. V00(t674) N003. t2853 = LEA(b+8) ; t674 N004. t1903 = IND ; t2853 N006. V99(t1905); t1903 N000. IL_OFFSET INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] N001. V99(t1906) N002. V00(t1907) N004. t2857 = LEA(b+24); t1907 N005. t1942 = IND ; t2857 N006. GE ; t1906,t1942 N007. JTRUE BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ===== N000. IL_OFFSET INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] N001. V00(t2861) N002. CNS_INT 16 N003. t2863 = ADD ; t2861 N005. V100(t1920); t2863 N000. IL_OFFSET INL34 @ ??? <- INLRT @ 0x521[E-] N001. V99(t1917) N002. V100(t1922) N004. t2866 = LEA(b+8) ; t1922 N005. t1923 = IND ; t2866 N006. BOUNDS_CHECK_Rng -> BB254; t1917,t1923 N007. V100(t1921*) N008. t1928 = IND ; t1921* N009. V99(t1918) N010. t1925 = CAST ; t1918 N011. CNS_INT 1 N012. t1927 = BFIZ ; t1925 N013. t1929 = LEA(b+(i*1)+0); t1928,t1927 N016. V18(t1931*) N000. STOREIND ; t1929,t1931* N000. IL_OFFSET INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] N001. V99(t1935*) N002. CNS_INT 1 N003. t1937 = ADD ; t1935* N004. V00(t1934) N006. t2869 = LEA(b+8) ; t1934 N000. STOREIND ; t2869,t1937 BB159 [521..522), preds={BB157} succs={BB160} ===== N000. IL_OFFSET INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] N001. V00(t1913) N000. t4262 = PUTARG_REG; t1913 N002. V18(t675*) N000. t4263 = PUTARG_REG; t675* N003. t2870 = CNS_INT(h) 0x4000000000435c58 ftn N000. t4264 = PUTARG_REG; t2870 N004. CALL r2r_ind; t4262,t4263,t4264 BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ===== N000. IL_OFFSET INLRT @ 0x529[E-] N001. V12(t677) N002. CNS_INT 0 N003. t679 = EQ ; t677 N004. V08(t681) N005. CNS_INT 1 N006. t683 = LE ; t681 N007. AND ; t679,t683 N008. JTRUE ; t3746 BB161 [52D..537) -> BB170 (cond), preds={BB160} succs={BB163,BB170} ===== N000. IL_OFFSET INLRT @ 0x52D[E-] N000. IL_OFFSET INLRT @ 0x532[E-] N001. V20(t692) N002. V144(t696) N003. BOUNDS_CHECK_Rng -> BB254; t692,t696 N004. V143(t701) N005. V20(t693) N006. t698 = CAST ; t693 N007. CNS_INT 2 N008. t700 = BFIZ ; t698 N009. t702 = LEA(b+(i*1)+0); t701,t700 N010. t2871 = IND ; t702 N012. CNS_INT 1 N013. t706 = ADD ; t2871 N014. V08(t689) N015. t707 = NE ; t706,t689 N016. V20(t685) N017. CNS_INT 0 N018. t687 = LT ; t685 N019. AND ; t707,t687 N020. JTRUE ; t3748 BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} ===== N000. IL_OFFSET INLRT @ 0x537[E-] N000. IL_OFFSET INLRT @ 0x547[E-] N001. V03(t710) N003. t2873 = LEA(b+56); t710 N004. t1946 = IND ; t2873 N006. V102(t1999); t1946 N000. IL_OFFSET INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] N001. V102(t1948) N002. CNS_INT null N003. JCMP ; t1948 BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} ===== N000. IL_OFFSET INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] N001. V00(t709) N003. t2875 = LEA(b+8) ; t709 N004. t1952 = IND ; t2875 N006. V103(t1954); t1952 N000. IL_OFFSET INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] N001. V102(t1955) N000. t4170 = LEA(b+8) ; t1955 N002. t1956 = IND ; t4170 N003. CNS_INT 1 N004. t1958 = NE ; t1956 N005. V103(t1963) N006. V00(t1964) N008. t2879 = LEA(b+24); t1964 N009. t2002 = IND ; t2879 N010. t1968 = GE ; t1963,t2002 N011. AND ; t1958,t1968 N012. JTRUE ; t3750 BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} ===== N000. IL_OFFSET INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] N000. IL_OFFSET INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] N001. V00(t2883) N002. CNS_INT 16 N003. t2885 = ADD ; t2883 N005. V104(t1975); t2885 N000. IL_OFFSET INL37 @ ??? <- INLRT @ 0x547[E-] N001. V103(t1972) N002. V104(t1977) N004. t2888 = LEA(b+8) ; t1977 N005. t1978 = IND ; t2888 N006. BOUNDS_CHECK_Rng -> BB254; t1972,t1978 N007. V104(t1976*) N008. t1983 = IND ; t1976* N009. V103(t1973) N010. t1980 = CAST ; t1973 N011. CNS_INT 1 N012. t1982 = BFIZ ; t1980 N013. t1984 = ADD ; t1983,t1982 N016. CNS_INT 0 N017. V102(t1986) N000. t4172 = LEA(b+8) ; t1986 N018. t2892 = IND ; t4172 N019. BOUNDS_CHECK_Rng -> BB254; t2892 N020. V102(t2890*) N022. t2897 = LEA(b+12); t2890* N024. t2902 = IND ; t2897 N000. STOREIND ; t1984,t2902 N000. IL_OFFSET INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] N001. V103(t1993*) N002. CNS_INT 1 N003. t1995 = ADD ; t1993* N004. V00(t1992) N006. t2904 = LEA(b+8) ; t1992 N000. STOREIND ; t2904,t1995 BB168 [547..548), preds={BB165} succs={BB169} ===== N000. IL_OFFSET INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] N001. V00(t1960) N000. t4265 = PUTARG_REG; t1960 N002. V102(t1961*) N000. t4266 = PUTARG_REG; t1961* N003. t2905 = CNS_INT(h) 0x4000000000431d58 ftn N000. t4267 = PUTARG_REG; t2905 N004. CALL r2r_ind; t4265,t4266,t4267 BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} ===== N000. IL_OFFSET INLRT @ 0x553[E-] N001. V20(t714*) N002. CNS_INT -1 N003. t716 = ADD ; t714* N005. V20(t718); t716 BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB169} succs={BB245} ===== N000. IL_OFFSET INLRT @ 0x559[E-] N001. V08(t669*) N002. CNS_INT -1 N003. t671 = ADD ; t669* N005. V08(t673); t671 BB186 [5A9..5BA) -> BB245 (cond), preds={BB257} succs={BB187,BB245} ===== N000. IL_OFFSET INLRT @ 0x5A9[E-] N001. V03(t635) N003. t2974 = LEA(b+128); t635 N004. t2126 = IND ; t2974 N006. V114(t2179); t2126 N000. IL_OFFSET INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] N001. V114(t2128) N002. CNS_INT null N003. JCMP ; t2128 BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ===== N000. IL_OFFSET INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] N001. V00(t634) N003. t2976 = LEA(b+8) ; t634 N004. t2132 = IND ; t2976 N006. V115(t2134); t2132 N000. IL_OFFSET INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] N001. V114(t2135) N000. t4182 = LEA(b+8) ; t2135 N002. t2136 = IND ; t4182 N003. CNS_INT 1 N004. t2138 = NE ; t2136 N005. V115(t2143) N006. V00(t2144) N008. t2980 = LEA(b+24); t2144 N009. t2182 = IND ; t2980 N010. t2148 = GE ; t2143,t2182 N011. AND ; t2138,t2148 N012. JTRUE ; t3758 BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ===== N000. IL_OFFSET INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] N000. IL_OFFSET INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] N001. V00(t2984) N002. CNS_INT 16 N003. t2986 = ADD ; t2984 N005. V116(t2155); t2986 N000. IL_OFFSET INL46 @ ??? <- INLRT @ 0x5A9[E-] N001. V115(t2152) N002. V116(t2157) N004. t2989 = LEA(b+8) ; t2157 N005. t2158 = IND ; t2989 N006. BOUNDS_CHECK_Rng -> BB254; t2152,t2158 N007. V116(t2156*) N008. t2163 = IND ; t2156* N009. V115(t2153) N010. t2160 = CAST ; t2153 N011. CNS_INT 1 N012. t2162 = BFIZ ; t2160 N013. t2164 = ADD ; t2163,t2162 N016. CNS_INT 0 N017. V114(t2166) N000. t4184 = LEA(b+8) ; t2166 N018. t2993 = IND ; t4184 N019. BOUNDS_CHECK_Rng -> BB254; t2993 N020. V114(t2991*) N022. t2998 = LEA(b+12); t2991* N024. t3003 = IND ; t2998 N000. STOREIND ; t2164,t3003 N000. IL_OFFSET INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] N001. V115(t2173*) N002. CNS_INT 1 N003. t2175 = ADD ; t2173* N004. V00(t2172) N006. t3005 = LEA(b+8) ; t2172 N000. STOREIND ; t3005,t2175 BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ===== N000. IL_OFFSET INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] N001. V00(t2140) N000. t4274 = PUTARG_REG; t2140 N002. V114(t2141*) N000. t4275 = PUTARG_REG; t2141* N003. t3006 = CNS_INT(h) 0x4000000000431d58 ftn N000. t4276 = PUTARG_REG; t3006 N004. CALL r2r_ind; t4274,t4275,t4276 BB194 [5CE..5D9) -> BB197 (cond), preds={BB192,BB193,BB257(2)} succs={BB195,BB197} ===== N000. IL_OFFSET INLRT @ 0x5CE[E-] N001. V16(t751) N002. V179(t3699) N003. GE ; t751,t3699 N004. JTRUE BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ===== N000. IL_OFFSET INLRT @ 0x5D9[E-] N001. V34(t781) N002. V16(t782) N003. t783 = CAST ; t782 N004. CNS_INT 1 N005. t786 = BFIZ ; t783 N006. t787 = LEA(b+(i*1)+0); t781,t786 N007. t788 = IND ; t787 N009. V172(t3631); t788 N010. V172(t3632) N012. CNS_INT 0 N013. JCMP ; t3632 BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ===== N000. IL_OFFSET INLRT @ 0x5E4[E-] N001. V172(t3634) N002. V18(t800) N003. NE ; t3634,t800 N004. JTRUE BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ===== N000. IL_OFFSET INLRT @ 0x5BA[E-] N001. V16(t805*) N003. V59(t812); t805* N000. IL_OFFSET INLRT @ 0x5BA[E-] N001. V59(t806*) N002. CNS_INT 1 N003. t808 = ADD ; t806* N005. V16(t810); t808 N001. V172(t3629*) N003. V119(t2225); t3629* N000. IL_OFFSET INL48 @ 0x000[E-] <- INLRT @ ??? N001. V00(t803) N003. t3008 = LEA(b+8) ; t803 N004. t2186 = IND ; t3008 N006. V118(t2188); t2186 N000. IL_OFFSET INL48 @ 0x007[E-] <- INLRT @ ??? N001. V118(t2189) N002. V00(t2190) N004. t3012 = LEA(b+24); t2190 N005. t2228 = IND ; t3012 N006. GE ; t2189,t2228 N007. JTRUE BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ===== N000. IL_OFFSET INL48 @ 0x015[E-] <- INLRT @ ??? N001. V00(t3016) N002. CNS_INT 16 N003. t3018 = ADD ; t3016 N005. V120(t2204); t3018 N001. V118(t2201) N002. V120(t2206) N004. t3021 = LEA(b+8) ; t2206 N005. t2207 = IND ; t3021 N006. BOUNDS_CHECK_Rng -> BB254; t2201,t2207 N007. V120(t2205*) N008. t2212 = IND ; t2205* N009. V118(t2202) N010. t2209 = CAST ; t2202 N011. CNS_INT 1 N012. t2211 = BFIZ ; t2209 N013. t2213 = LEA(b+(i*1)+0); t2212,t2211 N016. V119(t2215*) N000. STOREIND ; t2213,t2215* N000. IL_OFFSET INL48 @ 0x023[E-] <- INLRT @ ??? N001. V118(t2219*) N002. CNS_INT 1 N003. t2221 = ADD ; t2219* N004. V00(t2218) N006. t3024 = LEA(b+8) ; t2218 N000. STOREIND ; t3024,t2221 BB193 [000..000), preds={BB191} succs={BB194} ===== N000. IL_OFFSET INL48 @ 0x02D[E-] <- INLRT @ ??? N001. V00(t2196) N000. t4277 = PUTARG_REG; t2196 N002. V119(t2197*) N000. t4278 = PUTARG_REG; t2197* N003. t3025 = CNS_INT(h) 0x4000000000435c58 ftn N000. t4279 = PUTARG_REG; t3025 N004. CALL r2r_ind; t4277,t4278,t4279 BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ===== N000. IL_OFFSET INLRT @ 0x5F1[E-] N001. V16(t758) N002. V179(t3700) N003. GE ; t758,t3700 N004. JTRUE BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ===== N000. IL_OFFSET INLRT @ 0x5FF[E-] N001. V34(t765) N002. V16(t766) N003. t767 = CAST ; t766 N004. CNS_INT 1 N005. t770 = BFIZ ; t767 N006. t771 = LEA(b+(i*1)+0); t765,t770 N007. t772 = IND ; t771 N009. V172(t3636); t772 N010. V172(t3637*) N012. CNS_INT 0 N013. JCMP ; t3637* BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ===== N000. IL_OFFSET INLRT @ 0x60D[E-] N001. V16(t776*) N002. CNS_INT 1 N003. t778 = ADD ; t776* N005. V16(t780); t778 BB258 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145 (switch), preds={BB138} succs={BB145,BB171,BB242,BB245} ===== N000. V185(t4258*) N000. t4259 = CAST ; t4258* N000. t4260 = JMPTABLE N000. SWITCH_TABLE; t4259,t4260 BB171 [564..571) -> BB245 (cond), preds={BB258} succs={BB172,BB245} ===== N000. IL_OFFSET INLRT @ 0x564[E-] N001. V08(t605) N002. CNS_INT 0 N003. t607 = NE ; t605 N004. V21(t608) N005. t609 = OR ; t607,t608 N006. CNS_INT 0 N007. JCMP ; t609 BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ===== N000. IL_OFFSET INLRT @ 0x571[E-] N001. V07(t613) N002. CNS_INT 0 N003. LT ; t613 N004. JTRUE BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ===== N000. IL_OFFSET INLRT @ 0x575[E-] N001. V05(t625) N002. V04(t626) N003. t627 = GE ; t625,t626 N004. V36(t629) N005. t630 = IND ; t629 N006. CNS_INT 0 N007. t632 = EQ ; t630 N008. AND ; t627,t632 N009. JTRUE ; t3752 BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} ===== N000. IL_OFFSET INLRT @ 0x57C[E-] N000. IL_OFFSET INLRT @ 0x584[E-] N001. V03(t618) N003. t2907 = LEA(b+48); t618 N004. t2006 = IND ; t2907 N006. V106(t2059); t2006 N000. IL_OFFSET INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] N001. V106(t2008) N002. CNS_INT null N003. JCMP ; t2008 BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} ===== N000. IL_OFFSET INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] N001. V00(t617) N003. t2909 = LEA(b+8) ; t617 N004. t2012 = IND ; t2909 N006. V107(t2014); t2012 N000. IL_OFFSET INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] N001. V106(t2015) N000. t4174 = LEA(b+8) ; t2015 N002. t2016 = IND ; t4174 N003. CNS_INT 1 N004. t2018 = NE ; t2016 N005. V107(t2023) N006. V00(t2024) N008. t2913 = LEA(b+24); t2024 N009. t2062 = IND ; t2913 N010. t2028 = GE ; t2023,t2062 N011. AND ; t2018,t2028 N012. JTRUE ; t3754 BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} ===== N000. IL_OFFSET INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] N000. IL_OFFSET INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] N001. V00(t2917) N002. CNS_INT 16 N003. t2919 = ADD ; t2917 N005. V108(t2035); t2919 N000. IL_OFFSET INL40 @ ??? <- INLRT @ 0x584[E-] N001. V107(t2032) N002. V108(t2037) N004. t2922 = LEA(b+8) ; t2037 N005. t2038 = IND ; t2922 N006. BOUNDS_CHECK_Rng -> BB254; t2032,t2038 N007. V108(t2036*) N008. t2043 = IND ; t2036* N009. V107(t2033) N010. t2040 = CAST ; t2033 N011. CNS_INT 1 N012. t2042 = BFIZ ; t2040 N013. t2044 = ADD ; t2043,t2042 N016. CNS_INT 0 N017. V106(t2046) N000. t4176 = LEA(b+8) ; t2046 N018. t2926 = IND ; t4176 N019. BOUNDS_CHECK_Rng -> BB254; t2926 N020. V106(t2924*) N022. t2931 = LEA(b+12); t2924* N024. t2936 = IND ; t2931 N000. STOREIND ; t2044,t2936 N000. IL_OFFSET INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] N001. V107(t2053*) N002. CNS_INT 1 N003. t2055 = ADD ; t2053* N004. V00(t2052) N006. t2938 = LEA(b+8) ; t2052 N000. STOREIND ; t2938,t2055 BB179 [584..585), preds={BB176} succs={BB180} ===== N000. IL_OFFSET INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] N001. V00(t2020) N000. t4268 = PUTARG_REG; t2020 N002. V106(t2021*) N000. t4269 = PUTARG_REG; t2021* N003. t2939 = CNS_INT(h) 0x4000000000431d58 ftn N000. t4270 = PUTARG_REG; t2939 N004. CALL r2r_ind; t4268,t4269,t4270 BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} ===== N000. IL_OFFSET INLRT @ 0x590[E-] N001. t2940 = CNS_INT 1 N003. V21(t624); t2940 BB110 [000..000) (throw), preds={BB91} succs={} ===== N000. IL_OFFSET INL17 @ 0x029[E-] <- INLRT @ ??? N001. t2701 = CNS_INT(h) 0x4000000000424a20 ftn N000. t4302 = PUTARG_REG; t2701 N002. CALL r2r_ind; t4302 BB254 [???..???) (throw), preds={} succs={} ===== N001. t4303 = CNS_INT(h) 0x4000000000421828 ftn N002. t4304 = IND ; t4303 N001. CALL help; t4304 buildIntervals second part ======== Int arg V00 in reg x0 BB00 regmask=[x0] minReg=1 fixed wt=100.00> Int arg V03 in reg x4 BB00 regmask=[x4] minReg=1 fixed wt=100.00> Int arg V01 in reg x1 BB00 regmask=[x1] minReg=1 fixed wt=100.00> Int arg V02 in reg x2 (second half) in reg x3 NEW BLOCK BB01 DefList: { } N003 (???,???) [003780] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA DefList: { } N005 ( 1, 1) [000000] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N007 (???,???) [004185] ----------- * PUTARG_REG byref REG x0 BB01 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 last fixed wt=2150.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 137: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB01 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00> Assigning related to DefList: { N007.t4185. PUTARG_REG } N009 ( 2, 8) [002543] H---------- * CNS_INT(h) long 0x400000000046ac80 ftn REG NA $42 Interval 138: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N007.t4185. PUTARG_REG; N009.t2543. CNS_INT } N011 (???,???) [004186] ----------- * PUTARG_REG long REG x11 BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 last fixed wt=100.00> Interval 139: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB01 regmask=[x11] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x11] minReg=1 fixed wt=400.00> DefList: { N007.t4185. PUTARG_REG; N011.t4186. PUTARG_REG } N013 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 140: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 last fixed wt=100.00> CALL BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x1] minReg=1 wt=100.00> BB01 regmask=[x2] minReg=1 wt=100.00> BB01 regmask=[x3] minReg=1 wt=100.00> BB01 regmask=[x4] minReg=1 wt=100.00> BB01 regmask=[x5] minReg=1 wt=100.00> BB01 regmask=[x6] minReg=1 wt=100.00> BB01 regmask=[x7] minReg=1 wt=100.00> BB01 regmask=[x8] minReg=1 wt=100.00> BB01 regmask=[x9] minReg=1 wt=100.00> BB01 regmask=[x10] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x12] minReg=1 wt=100.00> BB01 regmask=[x13] minReg=1 wt=100.00> BB01 regmask=[x14] minReg=1 wt=100.00> BB01 regmask=[x15] minReg=1 wt=100.00> BB01 regmask=[xip0] minReg=1 wt=100.00> BB01 regmask=[xip1] minReg=1 wt=100.00> BB01 regmask=[lr] minReg=1 wt=100.00> DefList: { } N015 (???,???) [003781] ----------- * IL_OFFSET void INLRT @ 0x006[E-] REG NA DefList: { } N017 ( 1, 2) [000002] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N019 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 NA REG NA STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> DefList: { } N021 (???,???) [003782] ----------- * IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] REG NA DefList: { } N023 ( 1, 1) [002546] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N025 ( 1, 2) [002547] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N027 ( 3, 4) [002548] -----O----- * ADD byref REG NA $240 LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 141: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N027.t2548. ADD } N029 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> DefList: { } N031 (???,???) [003783] ----------- * IL_OFFSET void INLRT @ 0x009[E-] REG NA DefList: { } N033 ( 1, 2) [001497] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N035 ( 1, 1) [001502] ----------- * LCL_VAR byref V76 tmp36 u:1 NA REG NA $240 DefList: { } N037 ( 3, 4) [002556] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N039 ( 4, 3) [001503] ---XG------ * IND int REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> Interval 142: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N039.t1503. IND } N041 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> DefList: { } N043 ( 1, 1) [001501] ----------- * LCL_VAR byref V76 tmp36 u:1 NA (last use) REG NA $240 DefList: { } N045 ( 3, 2) [001505] n---GO----- * IND byref REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> Interval 143: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N045.t1505. IND } N047 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N049 ( 1, 1) [002552] ----------- * LCL_VAR long V167 tmp127 u:1 NA (last use) REG NA DefList: { } N051 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 NA REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1700.00> DefList: { } N053 ( 3, 4) [002558] ----------- * LCL_FLD byref V02 arg2 u:1[+0] NA REG NA $246 Interval 144: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_FLD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N053.t2558. LCL_FLD } N055 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1500.00> DefList: { } N057 ( 1, 1) [003710] ----------- * LCL_VAR byref V180 cse9 u:1 NA REG NA $246 DefList: { } N059 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 NA REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1500.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N061 ( 3, 4) [002561] ----------- * LCL_FLD int V02 arg2 u:1[+8] NA REG NA $342 Interval 145: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_FLD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N061.t2561. LCL_FLD } N063 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N065 ( 1, 1) [003690] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N067 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 NA REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N069 (???,???) [003784] ----------- * IL_OFFSET void INLRT @ 0x011[E-] REG NA DefList: { } N071 ( 1, 1) [000011] ----------- * LCL_VAR long V17 loc13 u:1 NA REG NA DefList: { } N073 ( 4, 3) [000012] ---XG------ * IND ubyte REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1700.00> Interval 146: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N073.t12. IND } N075 ( 1, 2) [000013] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N073.t12. IND } N077 ( 6, 6) [000014] CEQ---XG--N--- * JCMP void REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> CHECKING LAST USES for BB01, liveout={V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} ============================== use: {V01 V02} def: {V11 V17 V76 V147 V148 V167 V179 V180} NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N081 ( 3, 2) [002565] ----------- * LCL_VAR byref V147 tmp107 u:1 NA (last use) REG NA $246 DefList: { } N083 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 NA REG NA LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N085 ( 3, 2) [002568] ----------- * LCL_VAR int V148 tmp108 u:1 NA (last use) REG NA $342 DefList: { } N087 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 NA REG NA LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N089 ( 1, 1) [001472] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N091 ( 3, 4) [002572] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N093 ( 5, 4) [001473] n---GO----- * IND bool REG NA LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 147: bool RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N093.t1473. IND } N095 ( 1, 2) [001474] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N093.t1473. IND } N097 ( 7, 7) [001475] CNE----GO-N--- * JCMP void REG NA BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> CHECKING LAST USES for BB02, liveout={V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} ============================== use: {V01 V147 V148} def: {V155 V156} NEW BLOCK BB03 Setting BB02 as the predecessor for determining incoming variable registers of BB03 DefList: { } N101 ( 3, 2) [002574] ----------- * LCL_VAR byref V155 tmp115 u:1 NA (last use) REG NA $246 DefList: { } N103 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 NA REG NA LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> Assigning related to STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> DefList: { } N105 ( 3, 2) [002577] ----------- * LCL_VAR int V156 tmp116 u:1 NA (last use) REG NA $342 DefList: { } N107 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 NA REG NA LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> Assigning related to STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> DefList: { } N109 ( 1, 2) [001489] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N111 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 NA REG NA STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> CHECKING LAST USES for BB03, liveout={V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} ============================== use: {V155 V156} def: {V43 V149 V150} NEW BLOCK BB04 Setting BB02 as the predecessor for determining incoming variable registers of BB04 DefList: { } N115 ( 3, 2) [002581] ----------- * LCL_VAR byref V155 tmp115 u:1 NA (last use) REG NA $246 DefList: { } N117 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 NA REG NA LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> DefList: { } N119 ( 3, 2) [002584] ----------- * LCL_VAR int V156 tmp116 u:1 NA (last use) REG NA $342 DefList: { } N121 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 NA REG NA LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> DefList: { } N123 ( 1, 2) [001482] ----------- * CNS_INT int 1 REG NA $c1 Interval 148: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N123.t1482. CNS_INT } N125 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 NA REG NA BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> CHECKING LAST USES for BB04, liveout={V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} ============================== use: {V155 V156} def: {V43 V149 V150} NEW BLOCK BB05 Setting BB01 as the predecessor for determining incoming variable registers of BB05 DefList: { } N129 ( 3, 2) [002588] ----------- * LCL_VAR byref V147 tmp107 u:1 NA (last use) REG NA $246 DefList: { } N131 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 NA REG NA LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> DefList: { } N133 ( 3, 2) [002591] ----------- * LCL_VAR int V148 tmp108 u:1 NA (last use) REG NA $342 DefList: { } N135 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 NA REG NA LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> DefList: { } N137 ( 1, 2) [000021] ----------- * CNS_INT int 2 REG NA $c2 Interval 149: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N137.t21. CNS_INT } N139 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 NA REG NA BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> CHECKING LAST USES for BB05, liveout={V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} ============================== use: {V147 V148} def: {V43 V149 V150} NEW BLOCK BB06 Setting BB03 as the predecessor for determining incoming variable registers of BB06 DefList: { } N143 ( 3, 2) [002596] ----------- * LCL_VAR byref V149 tmp109 u:1 NA (last use) REG NA $246 DefList: { } N145 (???,???) [004187] ----------- * PUTARG_REG byref REG x0 BB06 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x0] minReg=1 last fixed wt=250.00> Interval 150: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB06 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x0] minReg=1 fixed wt=400.00> DefList: { N145.t4187. PUTARG_REG } N147 ( 3, 2) [002597] ----------- * LCL_VAR int V150 tmp110 u:1 NA (last use) REG NA $342 DefList: { N145.t4187. PUTARG_REG } N149 (???,???) [004188] ----------- * PUTARG_REG int REG x1 Last use of V150 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB06 regmask=[x1] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x1] minReg=1 last fixed wt=250.00> Interval 151: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB06 regmask=[x1] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x1] minReg=1 fixed wt=400.00> DefList: { N145.t4187. PUTARG_REG; N149.t4188. PUTARG_REG } N151 ( 6, 4) [002595] -c--------- * FIELD_LIST struct REG NA $141 Contained DefList: { N145.t4187. PUTARG_REG; N149.t4188. PUTARG_REG } N153 ( 3, 2) [000029] ----------- * LCL_VAR int V43 tmp3 u:1 NA (last use) REG NA $281 DefList: { N145.t4187. PUTARG_REG; N149.t4188. PUTARG_REG } N155 (???,???) [004189] ----------- * PUTARG_REG int REG x2 Last use of V43 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0-x1] BB06 regmask=[x2] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x2] minReg=1 last fixed wt=250.00> Interval 152: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB06 regmask=[x2] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x2] minReg=1 fixed wt=400.00> DefList: { N145.t4187. PUTARG_REG; N149.t4188. PUTARG_REG; N155.t4189. PUTARG_REG } N157 ( 2, 8) [002594] H---------- * CNS_INT(h) long 0x40000000005401e8 ftn REG NA $43 Interval 153: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N145.t4187. PUTARG_REG; N149.t4188. PUTARG_REG; N155.t4189. PUTARG_REG; N157.t2594. CNS_INT } N159 (???,???) [004190] ----------- * PUTARG_REG long REG x11 BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 last fixed wt=100.00> Interval 154: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB06 regmask=[x11] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x11] minReg=1 fixed wt=400.00> DefList: { N145.t4187. PUTARG_REG; N149.t4188. PUTARG_REG; N155.t4189. PUTARG_REG; N159.t4190. PUTARG_REG } N161 ( 25, 19) [000030] --CXG------ * CALL r2r_ind int REG NA $2c1 Interval 155: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB06 regmask=[x0] minReg=1 wt=100.00> BB06 regmask=[x0] minReg=1 last fixed wt=100.00> BB06 regmask=[x1] minReg=1 wt=100.00> BB06 regmask=[x1] minReg=1 last fixed wt=100.00> BB06 regmask=[x2] minReg=1 wt=100.00> BB06 regmask=[x2] minReg=1 last fixed wt=100.00> BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 last fixed wt=100.00> CALL BB06 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> BB06 regmask=[x0] minReg=1 wt=100.00> BB06 regmask=[x1] minReg=1 wt=100.00> BB06 regmask=[x2] minReg=1 wt=100.00> BB06 regmask=[x3] minReg=1 wt=100.00> BB06 regmask=[x4] minReg=1 wt=100.00> BB06 regmask=[x5] minReg=1 wt=100.00> BB06 regmask=[x6] minReg=1 wt=100.00> BB06 regmask=[x7] minReg=1 wt=100.00> BB06 regmask=[x8] minReg=1 wt=100.00> BB06 regmask=[x9] minReg=1 wt=100.00> BB06 regmask=[x10] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x12] minReg=1 wt=100.00> BB06 regmask=[x13] minReg=1 wt=100.00> BB06 regmask=[x14] minReg=1 wt=100.00> BB06 regmask=[x15] minReg=1 wt=100.00> BB06 regmask=[xip0] minReg=1 wt=100.00> BB06 regmask=[xip1] minReg=1 wt=100.00> BB06 regmask=[lr] minReg=1 wt=100.00> Interval 156: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB06 regmask=[x0] minReg=1 wt=100.00> CALL BB06 regmask=[x0] minReg=1 fixed wt=400.00> DefList: { N161.t30. CALL } N163 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 NA REG NA BB06 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> CHECKING LAST USES for BB06, liveout={V00 V01 V02 V03 V11 V15 V17 V179 V180} ============================== use: {V43 V149 V150} def: {V15} NEW BLOCK BB07 Setting BB06 as the predecessor for determining incoming variable registers of BB07 DefList: { } N167 (???,???) [003785] ----------- * IL_OFFSET void INLRT @ 0x02D[E-] REG NA DefList: { } N169 ( 1, 2) [000035] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N171 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 NA REG NA STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> DefList: { } N173 (???,???) [003786] ----------- * IL_OFFSET void INLRT @ 0x02F[E-] REG NA DefList: { } N175 ( 1, 2) [000038] ----------- * CNS_INT int -1 REG NA $c4 Interval 157: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N175.t38. CNS_INT } N177 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 NA REG NA BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N179 (???,???) [003787] ----------- * IL_OFFSET void INLRT @ 0x031[E-] REG NA DefList: { } N181 ( 1, 4) [000041] ----------- * CNS_INT int 0x7FFFFFFF REG NA $c9 Interval 158: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N181.t41. CNS_INT } N183 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 NA REG NA BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> DefList: { } N185 (???,???) [003788] ----------- * IL_OFFSET void INLRT @ 0x037[E-] REG NA DefList: { } N187 ( 1, 2) [000044] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N189 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 NA REG NA STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> DefList: { } N191 (???,???) [003789] ----------- * IL_OFFSET void INLRT @ 0x039[E-] REG NA DefList: { } N193 ( 1, 2) [002598] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N195 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 NA REG NA STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2500.00> DefList: { } N197 (???,???) [003790] ----------- * IL_OFFSET void INLRT @ 0x03C[E-] REG NA DefList: { } N199 ( 1, 2) [000050] ----------- * CNS_INT int -1 REG NA $c4 Interval 159: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N199.t50. CNS_INT } N201 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 NA REG NA BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N203 (???,???) [003791] ----------- * IL_OFFSET void INLRT @ 0x03F[E-] REG NA DefList: { } N205 ( 1, 2) [002599] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N207 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 NA REG NA STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2900.00> DefList: { } N209 (???,???) [003792] ----------- * IL_OFFSET void INLRT @ 0x042[E-] REG NA DefList: { } N211 ( 1, 2) [000056] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N213 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 NA REG NA STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N215 (???,???) [003793] ----------- * IL_OFFSET void INLRT @ 0x045[E-] REG NA DefList: { } N217 ( 1, 1) [000059] ----------- * LCL_VAR int V15 loc11 u:2 NA REG NA $283 DefList: { } N219 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 NA REG NA LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N221 (???,???) [003794] ----------- * IL_OFFSET void INLRT @ 0x049[E-] REG NA DefList: { } N223 ( 1, 1) [003712] ----------- * LCL_VAR byref V180 cse9 u:1 NA REG NA $246 DefList: { } N225 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 NA REG NA LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1500.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N227 (???,???) [003795] ----------- * IL_OFFSET void INLRT @ 0x049[E-] REG NA DefList: { } N229 ( 1, 1) [001512] ----------- * LCL_VAR byref V157 tmp117 u:1 NA REG NA $246 DefList: { } N231 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 NA REG NA LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N233 (???,???) [003796] ----------- * IL_OFFSET void INLRT @ 0x051[E-] REG NA DefList: { } N235 ( 1, 1) [000069] ----------- * LCL_VAR byref V157 tmp117 u:1 NA (last use) REG NA $246 DefList: { } N237 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 NA REG NA LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Assigning related to STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> DefList: { } N239 ( 1, 1) [002609] ----------- * LCL_VAR long V168 tmp128 u:1 NA (last use) REG NA $3c4 DefList: { } N241 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 NA REG NA LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> Assigning related to STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=18400.00> CHECKING LAST USES for BB07, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V15 V180} def: {V04 V05 V06 V07 V09 V10 V12 V13 V16 V22 V157 V168} NEW BLOCK BB47 Setting BB07 as the predecessor for determining incoming variable registers of BB47 DefList: { } N245 (???,???) [003837] ----------- * IL_OFFSET void INLRT @ 0x204[E-] REG NA DefList: { } N247 ( 1, 1) [000073] ----------- * LCL_VAR int V16 loc12 u:2 NA REG NA $28b DefList: { } N249 ( 1, 1) [003698] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N251 ( 3, 3) [000078] J------N--- * GE void REG NA $360 LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N253 ( 5, 5) [000079] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB47, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16 V179} def: {} NEW BLOCK BB48 Setting BB47 as the predecessor for determining incoming variable registers of BB48 DefList: { } N257 (???,???) [003838] ----------- * IL_OFFSET void INLRT @ 0x20F[E-] REG NA DefList: { } N259 ( 1, 1) [001198] ----------- * LCL_VAR int V16 loc12 u:2 NA (last use) REG NA $28b DefList: { } N261 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 NA REG NA LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Assigning related to STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> DefList: { } N263 (???,???) [003839] ----------- * IL_OFFSET void INLRT @ 0x20F[E-] REG NA DefList: { } N265 ( 1, 1) [001199] ----------- * LCL_VAR int V71 tmp31 u:1 NA REG NA $28b DefList: { } N267 ( 1, 2) [001200] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N269 ( 3, 4) [001201] ----------- * ADD int REG NA $361 LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> Interval 160: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> DefList: { N269.t1201. ADD } N271 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 NA REG NA BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Assigning related to STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N273 ( 1, 1) [001197] ----------- * LCL_VAR long V22 loc18 u:1 NA REG NA $3c4 DefList: { } N275 ( 1, 1) [001206] ----------- * LCL_VAR int V71 tmp31 u:1 NA (last use) REG NA $28b DefList: { } N277 ( 2, 3) [001207] -c--------- * CAST long <- int REG NA $3c5 Contained DefList: { } N279 ( 1, 2) [001209] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N281 ( 4, 6) [001210] -c--------- * BFIZ long REG NA Contained DefList: { } N283 ( 6, 8) [001211] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N285 ( 9, 10) [001212] ---XG------ * IND ushort REG NA LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=18400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> Interval 161: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> DefList: { N285.t1212. IND } N287 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 NA REG NA BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Assigning related to STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> DefList: { } N289 ( 1, 1) [001216] ----------- * LCL_VAR int V72 tmp32 u:1 NA (last use) REG NA DefList: { } N291 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 NA REG NA LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> Assigning related to STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N293 ( 1, 1) [001215] ----------- * LCL_VAR int V18 loc14 u:5 NA REG NA DefList: { } N295 ( 1, 2) [001219] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N297 ( 3, 4) [001220] CEQ-------N--- * JCMP void REG NA LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> CHECKING LAST USES for BB48, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} ============================== use: {V16 V22} def: {V16 V18 V71 V72} NEW BLOCK BB49 Setting BB48 as the predecessor for determining incoming variable registers of BB49 DefList: { } N301 (???,???) [003840] ----------- * IL_OFFSET void INLRT @ 0x222[E-] REG NA DefList: { } N303 ( 1, 1) [001222] ----------- * LCL_VAR int V18 loc14 u:5 NA REG NA DefList: { } N305 ( 1, 2) [001223] -c--------- * CNS_INT int 59 REG NA $d1 Contained DefList: { } N307 ( 3, 4) [001224] N------N-U- * NE void REG NA LCL_VAR BB49 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N309 ( 5, 6) [001225] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB49, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} ============================== use: {V18} def: {} NEW BLOCK BB08 Setting BB49 as the predecessor for determining incoming variable registers of BB08 DefList: { } N313 (???,???) [003797] ----------- * IL_OFFSET void INLRT @ 0x05B[E-] REG NA DefList: { } N315 ( 1, 1) [001226] ----------- * LCL_VAR int V18 loc14 u:5 NA REG NA DefList: { } N317 ( 1, 2) [001227] -c--------- * CNS_INT int 69 REG NA $d2 Contained DefList: { } N319 ( 3, 4) [001228] N------N-U- * GT void REG NA LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N321 ( 5, 6) [001229] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB08, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} ============================== use: {V18} def: {} NEW BLOCK BB09 Setting BB08 as the predecessor for determining incoming variable registers of BB09 DefList: { } N325 (???,???) [003798] ----------- * IL_OFFSET void INLRT @ 0x061[E-] REG NA DefList: { } N327 ( 1, 1) [001361] ----------- * LCL_VAR int V18 loc14 u:5 NA REG NA DefList: { } N329 ( 1, 2) [001362] -c--------- * CNS_INT int -34 REG NA $d6 Contained DefList: { } N331 ( 3, 4) [001363] ----------- * ADD int REG NA LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> Interval 162: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N331.t1363. ADD } N333 (???,???) [004192] DA--------- * STORE_LCL_VAR int V182 rat0 NA REG NA BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N335 ( 3, 2) [004194] ----------- * LCL_VAR int V182 rat0 NA REG NA DefList: { } N337 ( 1, 2) [004195] -c--------- * CNS_INT int 5 REG NA Contained DefList: { } N339 ( 8, 5) [004196] ---------U- * GT void REG NA LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N341 ( 10, 7) [004197] ----------- * JTRUE void REG NA CHECKING LAST USES for BB09, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V182} ============================== use: {V18} def: {V182} NEW BLOCK BB10 Setting BB09 as the predecessor for determining incoming variable registers of BB10 DefList: { } N345 (???,???) [003799] ----------- * IL_OFFSET void INLRT @ 0x083[E-] REG NA DefList: { } N347 ( 1, 1) [001365] ----------- * LCL_VAR int V18 loc14 u:5 NA REG NA DefList: { } N349 ( 1, 2) [001366] -c--------- * CNS_INT int -44 REG NA $d7 Contained DefList: { } N351 ( 3, 4) [001367] ----------- * ADD int REG NA LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> Interval 163: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N351.t1367. ADD } N353 (???,???) [004203] DA--------- * STORE_LCL_VAR int V183 rat1 NA REG NA BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N355 ( 3, 2) [004205] ----------- * LCL_VAR int V183 rat1 NA REG NA DefList: { } N357 ( 1, 2) [004206] -c--------- * CNS_INT int 4 REG NA Contained DefList: { } N359 ( 8, 5) [004207] ---------U- * GT void REG NA LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N361 ( 10, 7) [004208] ----------- * JTRUE void REG NA CHECKING LAST USES for BB10, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V183} ============================== use: {V18} def: {V183} NEW BLOCK BB11 Setting BB10 as the predecessor for determining incoming variable registers of BB11 DefList: { } N365 (???,???) [003800] ----------- * IL_OFFSET void INLRT @ 0x0A1[E-] REG NA DefList: { } N367 ( 1, 1) [001369] ----------- * LCL_VAR int V18 loc14 u:5 NA (last use) REG NA DefList: { } N369 ( 1, 2) [001370] -c--------- * CNS_INT int 69 REG NA $d2 Contained DefList: { } N371 ( 3, 4) [001371] J------N--- * EQ void REG NA LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N373 ( 5, 6) [001372] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB11, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V18} def: {} NEW BLOCK BB12 Setting BB11 as the predecessor for determining incoming variable registers of BB12 CHECKING LAST USES for BB12, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {} def: {} NEW BLOCK BB13 Setting BB08 as the predecessor for determining incoming variable registers of BB13 DefList: { } N379 (???,???) [003801] ----------- * IL_OFFSET void INLRT @ 0x0AF[E-] REG NA DefList: { } N381 ( 1, 1) [001230] ----------- * LCL_VAR int V18 loc14 u:5 NA REG NA DefList: { } N383 ( 1, 2) [001231] -c--------- * CNS_INT int 92 REG NA $d3 Contained DefList: { } N385 ( 3, 4) [001232] J------N--- * EQ void REG NA LCL_VAR BB13 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N387 ( 5, 6) [001233] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB13, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} ============================== use: {V18} def: {} NEW BLOCK BB14 Setting BB13 as the predecessor for determining incoming variable registers of BB14 DefList: { } N391 (???,???) [003802] ----------- * IL_OFFSET void INLRT @ 0x0B8[E-] REG NA DefList: { } N393 ( 1, 1) [001257] ----------- * LCL_VAR int V18 loc14 u:5 NA REG NA DefList: { } N395 ( 1, 2) [001258] -c--------- * CNS_INT int 101 REG NA $d4 Contained DefList: { } N397 ( 3, 4) [001259] J------N--- * EQ void REG NA LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N399 ( 5, 6) [001260] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB14, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} ============================== use: {V18} def: {} NEW BLOCK BB15 Setting BB14 as the predecessor for determining incoming variable registers of BB15 DefList: { } N403 (???,???) [003803] ----------- * IL_OFFSET void INLRT @ 0x0C1[E-] REG NA DefList: { } N405 ( 1, 1) [001352] ----------- * LCL_VAR int V18 loc14 u:5 NA (last use) REG NA DefList: { } N407 ( 1, 4) [001353] ----------- * CNS_INT int 0x2030 REG NA $d5 Interval 164: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N407.t1353. CNS_INT } N409 ( 3, 6) [001354] J------N--- * NE void REG NA LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N411 ( 5, 8) [001355] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB15, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V18} def: {} NEW BLOCK BB16 Setting BB07 as the predecessor for determining incoming variable registers of BB16 DefList: { } N415 (???,???) [003804] ----------- * IL_OFFSET void INLRT @ 0x137[E-] REG NA DefList: { } N417 ( 1, 1) [001356] ----------- * LCL_VAR int V13 loc9 u:2 NA (last use) REG NA $289 DefList: { } N419 ( 1, 2) [001357] -c--------- * CNS_INT int 3 REG NA $c3 Contained DefList: { } N421 ( 3, 4) [001358] ----------- * ADD int REG NA $376 LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 165: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB16 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N421.t1358. ADD } N423 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 NA REG NA BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> CHECKING LAST USES for BB16, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V13} def: {V13} NEW BLOCK BB35 Setting BB13 as the predecessor for determining incoming variable registers of BB35 DefList: { } N427 (???,???) [003825] ----------- * IL_OFFSET void INLRT @ 0x175[E-] REG NA DefList: { } N429 ( 1, 1) [001234] ----------- * LCL_VAR int V16 loc12 u:17 NA REG NA $361 DefList: { } N431 ( 1, 1) [003694] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N433 ( 6, 3) [001239] -c-----N--- * GE int REG NA $36c Contained DefList: { } N435 ( 1, 1) [001241] ----------- * LCL_VAR long V22 loc18 u:1 NA REG NA $3c4 DefList: { } N437 ( 1, 1) [001242] ----------- * LCL_VAR int V16 loc12 u:17 NA REG NA $361 DefList: { } N439 ( 2, 3) [001243] -c--------- * CAST long <- int REG NA $3c8 Contained DefList: { } N441 ( 1, 2) [001245] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N443 ( 4, 6) [001246] -c--------- * BFIZ long REG NA Contained DefList: { } N445 ( 6, 8) [001247] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N447 ( 9, 10) [001248] ---XG------ * IND ushort REG NA LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=18400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 166: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N447.t1248. IND } N449 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 NA REG NA BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N451 ( 1, 1) [003646] ----------- * LCL_VAR int V174 cse3 NA (last use) REG NA DefList: { } N453 ( 1, 2) [001249] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N455 ( 15, 14) [001250] -c-XG--N--- * EQ int REG NA Contained DefList: { } N457 ( 22, 18) [003730] Jc-XG--N--- * AND void REG NA Contained DefList: { } N459 ( 24, 20) [001240] ---XG------ * JTRUE void REG NA $VN.Void LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> CHECKING LAST USES for BB35, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16 V22 V179} def: {V174} NEW BLOCK BB36 Setting BB07 as the predecessor for determining incoming variable registers of BB36 DefList: { } N463 (???,???) [003826] ----------- * IL_OFFSET void INLRT @ 0x183[E-] REG NA DefList: { } N465 (???,???) [003827] ----------- * IL_OFFSET void INLRT @ 0x18E[E-] REG NA DefList: { } N467 ( 1, 1) [001252] ----------- * LCL_VAR int V16 loc12 u:17 NA (last use) REG NA $361 DefList: { } N469 ( 1, 2) [001253] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N471 ( 3, 4) [001254] ----------- * ADD int REG NA $371 LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 167: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB36 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N471.t1254. ADD } N473 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 NA REG NA BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> CHECKING LAST USES for BB36, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16} def: {V16} NEW BLOCK BB38 Setting BB11 as the predecessor for determining incoming variable registers of BB38 DefList: { } N477 (???,???) [003828] ----------- * IL_OFFSET void INLRT @ 0x196[E-] REG NA DefList: { } N479 ( 1, 1) [001261] ----------- * LCL_VAR int V16 loc12 u:17 NA REG NA $361 DefList: { } N481 ( 1, 1) [003695] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N483 ( 3, 3) [001266] J------N--- * GE void REG NA $36c LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N485 ( 5, 5) [001267] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB38, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16 V179} def: {} NEW BLOCK BB39 Setting BB38 as the predecessor for determining incoming variable registers of BB39 DefList: { } N489 (???,???) [003829] ----------- * IL_OFFSET void INLRT @ 0x1A1[E-] REG NA DefList: { } N491 ( 1, 1) [001341] ----------- * LCL_VAR long V22 loc18 u:1 NA REG NA $3c4 DefList: { } N493 ( 1, 1) [001342] ----------- * LCL_VAR int V16 loc12 u:17 NA REG NA $361 DefList: { } N495 ( 2, 3) [001343] -c--------- * CAST long <- int REG NA $3c8 Contained DefList: { } N497 ( 1, 2) [001345] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N499 ( 4, 6) [001346] -c--------- * BFIZ long REG NA Contained DefList: { } N501 ( 6, 8) [001347] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N503 ( 9, 10) [001348] ---XG------ * IND ushort REG NA LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=18400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 168: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N503.t1348. IND } N505 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 NA REG NA BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N507 ( 1, 1) [003650] ----------- * LCL_VAR int V174 cse3 NA (last use) REG NA DefList: { } N509 ( 1, 2) [001349] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { } N511 ( 12, 14) [001350] J--XG--N--- * EQ void REG NA LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N513 ( 14, 16) [001351] ---XG------ * JTRUE void REG NA $311 CHECKING LAST USES for BB39, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16 V22} def: {V174} NEW BLOCK BB40 Setting BB38 as the predecessor for determining incoming variable registers of BB40 DefList: { } N517 (???,???) [003830] ----------- * IL_OFFSET void INLRT @ 0x1AE[E-] REG NA DefList: { } N519 ( 1, 1) [001268] ----------- * LCL_VAR int V16 loc12 u:17 NA REG NA $361 DefList: { } N521 ( 1, 2) [001269] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N523 ( 3, 4) [001270] ----------- * ADD int REG NA $371 LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 169: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N523.t1270. ADD } N525 ( 1, 1) [003696] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { N523.t1270. ADD } N527 ( 5, 6) [001275] J------N--- * GE void REG NA $681 BB40 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N529 ( 7, 8) [001276] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB40, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16 V179} def: {} NEW BLOCK BB41 Setting BB07 as the predecessor for determining incoming variable registers of BB41 DefList: { } N533 (???,???) [003831] ----------- * IL_OFFSET void INLRT @ 0x1BB[E-] REG NA DefList: { } N535 ( 1, 1) [001277] ----------- * LCL_VAR long V22 loc18 u:1 NA REG NA $3c4 DefList: { } N537 ( 1, 1) [001278] ----------- * LCL_VAR int V16 loc12 u:17 NA REG NA $361 DefList: { } N539 ( 2, 3) [001279] -c--------- * CAST long <- int REG NA $3c8 Contained DefList: { } N541 ( 1, 2) [001281] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N543 ( 4, 6) [001282] -c--------- * BFIZ long REG NA Contained DefList: { } N545 ( 6, 8) [001283] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N547 ( 9, 10) [001284] ---XG------ * IND ushort REG NA LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 last wt=18400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 170: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N547.t1284. IND } N549 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 NA REG NA BB41 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N551 ( 1, 1) [003654] ----------- * LCL_VAR int V174 cse3 NA REG NA DefList: { } N553 ( 1, 2) [001285] -c--------- * CNS_INT int 43 REG NA $d9 Contained DefList: { } N555 ( 12, 14) [001286] J--XG--N--- * EQ void REG NA LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N557 ( 14, 16) [001287] ---XG------ * JTRUE void REG NA $311 CHECKING LAST USES for BB41, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V174 V179 V180} ============================== use: {V16 V22} def: {V174} NEW BLOCK BB42 Setting BB41 as the predecessor for determining incoming variable registers of BB42 DefList: { } N561 (???,???) [003832] ----------- * IL_OFFSET void INLRT @ 0x1C8[E-] REG NA DefList: { } N563 ( 1, 1) [003656] ----------- * LCL_VAR int V174 cse3 NA (last use) REG NA DefList: { } N565 ( 1, 2) [001338] -c--------- * CNS_INT int 45 REG NA $da Contained DefList: { } N567 ( 3, 4) [001339] N---G--N-U- * NE void REG NA LCL_VAR BB42 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N569 ( 5, 6) [001340] ----G------ * JTRUE void REG NA $311 CHECKING LAST USES for BB42, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V174} def: {} NEW BLOCK BB43 Setting BB41 as the predecessor for determining incoming variable registers of BB43 DefList: { } N573 (???,???) [003833] ----------- * IL_OFFSET void INLRT @ 0x1D5[E-] REG NA DefList: { } N575 ( 1, 1) [001288] ----------- * LCL_VAR long V22 loc18 u:1 NA REG NA $3c4 DefList: { } N577 ( 1, 1) [001289] ----------- * LCL_VAR int V16 loc12 u:17 NA REG NA $361 DefList: { } N579 ( 1, 2) [001290] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N581 ( 3, 4) [001291] ----------- * ADD int REG NA $371 LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 171: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N581.t1291. ADD } N583 ( 4, 6) [001292] -c--------- * CAST long <- int REG NA $3cb Contained DefList: { N581.t1291. ADD } N585 ( 1, 2) [001294] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N581.t1291. ADD } N587 ( 6, 9) [001295] -c--------- * BFIZ long REG NA Contained DefList: { N581.t1291. ADD } N589 ( 8, 11) [001296] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { N581.t1291. ADD } N591 ( 11, 13) [001297] ---XG------ * IND ushort REG NA LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 last wt=18400.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Interval 172: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N591.t1297. IND } N593 ( 1, 2) [001298] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { N591.t1297. IND } N595 ( 13, 16) [001299] N--XG--N-U- * NE void REG NA BB43 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N597 ( 15, 18) [001300] ---XG------ * JTRUE void REG NA $313 Exposed uses: BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CHECKING LAST USES for BB43, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16 V22} def: {} NEW BLOCK BB44 Setting BB39 as the predecessor for determining incoming variable registers of BB44 DefList: { } N601 (???,???) [003834] ----------- * IL_OFFSET void INLRT @ 0x1E4[E-] REG NA DefList: { } N603 ( 1, 1) [001301] ----------- * LCL_VAR int V16 loc12 u:18 NA (last use) REG NA $2b2 DefList: { } N605 ( 1, 2) [001302] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N607 ( 3, 4) [001303] ----------- * ADD int REG NA $942 LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 173: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> DefList: { N607.t1303. ADD } N609 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 NA REG NA BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> Assigning related to STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> DefList: { } N611 ( 1, 1) [001307] ----------- * LCL_VAR int V73 tmp33 u:1 NA (last use) REG NA $942 DefList: { } N613 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 NA REG NA LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> Assigning related to STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N615 ( 1, 1) [001306] ----------- * LCL_VAR int V16 loc12 u:19 NA REG NA $942 DefList: { } N617 ( 1, 1) [003697] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N619 ( 3, 3) [001314] J------N--- * GE void REG NA $943 LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N621 ( 5, 5) [001315] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB44, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16 V179} def: {V16 V73} NEW BLOCK BB45 Setting BB44 as the predecessor for determining incoming variable registers of BB45 DefList: { } N625 (???,???) [003835] ----------- * IL_OFFSET void INLRT @ 0x1F4[E-] REG NA DefList: { } N627 ( 1, 1) [001319] ----------- * LCL_VAR long V22 loc18 u:1 NA REG NA $3c4 DefList: { } N629 ( 1, 1) [001320] ----------- * LCL_VAR int V16 loc12 u:19 NA REG NA $942 DefList: { } N631 ( 2, 3) [001321] -c--------- * CAST long <- int REG NA $3e1 Contained DefList: { } N633 ( 1, 2) [001323] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N635 ( 4, 6) [001324] -c--------- * BFIZ long REG NA Contained DefList: { } N637 ( 6, 8) [001325] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N639 ( 9, 10) [001326] ---XG------ * IND ushort REG NA LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 last wt=18400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 174: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> DefList: { N639.t1326. IND } N641 ( 1, 2) [001327] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { N639.t1326. IND } N643 ( 11, 13) [001328] J--XG--N--- * EQ void REG NA BB45 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> DefList: { } N645 ( 13, 15) [001329] ---XG------ * JTRUE void REG NA $878 CHECKING LAST USES for BB45, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V16 V22} def: {} NEW BLOCK BB46 Setting BB44 as the predecessor for determining incoming variable registers of BB46 DefList: { } N649 (???,???) [003836] ----------- * IL_OFFSET void INLRT @ 0x201[E-] REG NA DefList: { } N651 ( 1, 2) [002613] ----------- * CNS_INT int 1 REG NA $c1 Interval 175: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N651.t2613. CNS_INT } N653 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 NA REG NA BB46 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB46 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2500.00> Exposed uses: BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CHECKING LAST USES for BB46, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {} def: {V09} NEW BLOCK BB50 Setting BB47 as the predecessor for determining incoming variable registers of BB50 DefList: { } N657 (???,???) [003841] ----------- * IL_OFFSET void INLRT @ 0x22B[E-] REG NA DefList: { } N659 ( 1, 2) [000081] -c--------- * CNS_INT long 0 REG NA $205 Contained DefList: { } N661 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 NA REG NA DefList: { } N663 (???,???) [003842] ----------- * IL_OFFSET void INLRT @ 0x22F[E-] REG NA DefList: { } N665 ( 1, 1) [000084] ----------- * LCL_VAR int V05 loc1 u:2 NA REG NA $286 DefList: { } N667 ( 1, 2) [000085] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N669 ( 3, 4) [000086] J------N--- * GE void REG NA $690 LCL_VAR BB50 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N671 ( 5, 6) [000087] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB50, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} ============================== use: {V05} def: {} NEW BLOCK BB51 Setting BB50 as the predecessor for determining incoming variable registers of BB51 DefList: { } N675 (???,???) [003843] ----------- * IL_OFFSET void INLRT @ 0x233[E-] REG NA DefList: { } N677 ( 1, 1) [001194] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { } N679 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 NA REG NA LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> CHECKING LAST USES for BB51, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} ============================== use: {V04} def: {V05} NEW BLOCK BB52 Setting BB50 as the predecessor for determining incoming variable registers of BB52 DefList: { } N683 (???,???) [003844] ----------- * IL_OFFSET void INLRT @ 0x235[E-] REG NA DefList: { } N685 ( 1, 1) [000088] ----------- * LCL_VAR int V10 loc6 u:2 NA REG NA $287 DefList: { } N687 ( 1, 2) [000089] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N689 ( 3, 4) [000090] J------N--- * LT void REG NA $692 LCL_VAR BB52 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N691 ( 5, 6) [000091] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB52, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} ============================== use: {V10} def: {} NEW BLOCK BB53 Setting BB52 as the predecessor for determining incoming variable registers of BB53 DefList: { } N695 (???,???) [003845] ----------- * IL_OFFSET void INLRT @ 0x23A[E-] REG NA DefList: { } N697 ( 1, 1) [001180] ----------- * LCL_VAR int V10 loc6 u:2 NA (last use) REG NA $287 DefList: { } N699 ( 1, 1) [001181] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N701 ( 3, 3) [001182] N------N-U- * NE void REG NA $696 LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N703 ( 5, 5) [001183] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB53, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} ============================== use: {V05 V10} def: {} NEW BLOCK BB54 Setting BB53 as the predecessor for determining incoming variable registers of BB54 DefList: { } N707 (???,???) [003846] ----------- * IL_OFFSET void INLRT @ 0x23F[E-] REG NA DefList: { } N709 ( 1, 1) [001187] ----------- * LCL_VAR int V13 loc9 u:2 NA (last use) REG NA $289 DefList: { } N711 ( 1, 1) [001188] ----------- * LCL_VAR int V11 loc7 u:3 NA REG NA $288 DefList: { } N713 ( 1, 2) [001189] ----------- * CNS_INT int 3 REG NA $c3 Interval 176: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N713.t1189. CNS_INT } N715 ( 6, 6) [001190] -c--------- * MUL int REG NA $697 Contained DefList: { N713.t1189. CNS_INT } N717 ( 8, 8) [001191] ----------- * SUB int REG NA $698 LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 177: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SUB BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N717.t1191. SUB } N719 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 NA REG NA BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> CHECKING LAST USES for BB54, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} ============================== use: {V11 V13} def: {V13} NEW BLOCK BB55 Setting BB53 as the predecessor for determining incoming variable registers of BB55 DefList: { } N723 (???,???) [003847] ----------- * IL_OFFSET void INLRT @ 0x24A[E-] REG NA DefList: { } N725 ( 1, 2) [002615] ----------- * CNS_INT int 1 REG NA $c1 Interval 178: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB55 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N725.t2615. CNS_INT } N727 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 NA REG NA BB55 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB55 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2900.00> CHECKING LAST USES for BB55, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} ============================== use: {} def: {V12} NEW BLOCK BB56 Setting BB52 as the predecessor for determining incoming variable registers of BB56 DefList: { } N731 (???,???) [003848] ----------- * IL_OFFSET void INLRT @ 0x24D[E-] REG NA DefList: { } N733 ( 1, 1) [000092] ----------- * LCL_VAR long V17 loc13 u:1 NA REG NA DefList: { } N735 ( 4, 3) [000093] ---XG------ * IND ubyte REG NA LCL_VAR BB56 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1700.00> Interval 179: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB56 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N735.t93. IND } N737 ( 1, 2) [000094] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N735.t93. IND } N739 ( 6, 6) [000095] CEQ---XG--N--- * JCMP void REG NA BB56 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB56, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} ============================== use: {V17} def: {} NEW BLOCK BB57 Setting BB56 as the predecessor for determining incoming variable registers of BB57 DefList: { } N743 (???,???) [003849] ----------- * IL_OFFSET void INLRT @ 0x252[E-] REG NA DefList: { } N745 ( 1, 1) [002618] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N747 ( 1, 2) [002619] -c--------- * CNS_INT long 4 REG NA $207 Contained DefList: { } N749 ( 3, 4) [002620] -----O----- * ADD byref REG NA $24a LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 180: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N749.t2620. ADD } N751 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 NA REG NA BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N753 ( 1, 1) [001131] ----------- * LCL_VAR byref V69 tmp29 u:1 NA REG NA $24a DefList: { } N755 ( 3, 2) [001132] n---GO----- * IND int REG NA LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 181: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N755.t1132. IND } N757 ( 1, 1) [001133] ----------- * LCL_VAR int V13 loc9 u:3 NA (last use) REG NA $28e DefList: { N755.t1132. IND } N759 ( 5, 4) [001134] ----GO----- * ADD int REG NA BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 182: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N759.t1134. ADD } N761 ( 1, 1) [001130] ----------- * LCL_VAR byref V69 tmp29 u:1 NA (last use) REG NA $24a DefList: { N759.t1134. ADD } N763 (???,???) [003850] -A--GO----- * STOREIND int REG NA LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N765 (???,???) [003851] ----------- * IL_OFFSET void INLRT @ 0x25E[E-] REG NA DefList: { } N767 ( 1, 1) [001137] ----------- * LCL_VAR int V09 loc5 u:2 NA REG NA $4c1 DefList: { } N769 ( 1, 2) [001138] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N771 ( 3, 4) [001139] CNE-------N--- * JCMP void REG NA LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2500.00> CHECKING LAST USES for BB57, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} ============================== use: {V01 V09 V13} def: {V69} NEW BLOCK BB58 Setting BB57 as the predecessor for determining incoming variable registers of BB58 DefList: { } N775 (???,???) [003852] ----------- * IL_OFFSET void INLRT @ 0x262[E-] REG NA DefList: { } N777 ( 1, 1) [001171] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N779 ( 3, 4) [002623] -c--------- * LEA(b+4) byref REG NA Contained DefList: { } N781 ( 4, 3) [001172] n---GO----- * IND int REG NA LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 183: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N781.t1172. IND } N783 ( 1, 1) [001173] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { N781.t1172. IND } N785 ( 6, 5) [001174] ----GO----- * ADD int REG NA BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> Interval 184: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N785.t1174. ADD } N787 ( 1, 1) [001175] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { N785.t1174. ADD } N789 ( 8, 7) [001176] ----GO----- * SUB int REG NA BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> Interval 185: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SUB BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N789.t1176. SUB } N791 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 NA REG NA BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB58, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70 V179 V180} ============================== use: {V01 V04 V05} def: {V70} NEW BLOCK BB59 Setting BB57 as the predecessor for determining incoming variable registers of BB59 DefList: { } N795 (???,???) [003853] ----------- * IL_OFFSET void INLRT @ 0x26E[E-] REG NA DefList: { } N797 ( 1, 1) [001141] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { } N799 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 NA REG NA LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB59, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70 V179 V180} ============================== use: {V04} def: {V70} NEW BLOCK BB60 Setting BB58 as the predecessor for determining incoming variable registers of BB60 DefList: { } N803 (???,???) [003854] ----------- * IL_OFFSET void INLRT @ 0x271[E-] REG NA DefList: { } N805 ( 1, 1) [001145] ----------- * LCL_VAR int V70 tmp30 u:1 NA (last use) REG NA $291 DefList: { } N807 (???,???) [004213] ----------- * PUTARG_REG int REG x1 BB60 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB60 regmask=[x1] minReg=1 last fixed wt=800.00> Interval 186: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB60 regmask=[x1] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x1] minReg=1 fixed wt=1600.00> DefList: { N807.t4213. PUTARG_REG } N809 ( 1, 1) [001148] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { N807.t4213. PUTARG_REG } N811 (???,???) [004214] ----------- * PUTARG_REG byref REG x0 BB60 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB60 regmask=[x0] minReg=1 last fixed wt=2150.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 187: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB60 regmask=[x0] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x0] minReg=1 fixed wt=1600.00> Assigning related to DefList: { N807.t4213. PUTARG_REG; N811.t4214. PUTARG_REG } N813 ( 2, 8) [002624] H---------- * CNS_INT(h) long 0x400000000046acb8 ftn REG NA $45 Interval 188: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N807.t4213. PUTARG_REG; N811.t4214. PUTARG_REG; N813.t2624. CNS_INT } N815 (???,???) [004215] ----------- * PUTARG_REG long REG x11 BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 last fixed wt=400.00> Interval 189: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB60 regmask=[x11] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x11] minReg=1 fixed wt=1600.00> DefList: { N807.t4213. PUTARG_REG; N811.t4214. PUTARG_REG; N815.t4215. PUTARG_REG } N817 ( 1, 2) [001150] ----------- * CNS_INT int 0 REG NA $c0 Interval 190: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N807.t4213. PUTARG_REG; N811.t4214. PUTARG_REG; N815.t4215. PUTARG_REG; N817.t1150. CNS_INT } N819 (???,???) [004216] ----------- * PUTARG_REG int REG x2 BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 last fixed wt=400.00> Interval 191: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB60 regmask=[x2] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x2] minReg=1 fixed wt=1600.00> DefList: { N807.t4213. PUTARG_REG; N811.t4214. PUTARG_REG; N815.t4215. PUTARG_REG; N819.t4216. PUTARG_REG } N821 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 192: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB60 regmask=[x1] minReg=1 wt=400.00> BB60 regmask=[x1] minReg=1 last fixed wt=400.00> BB60 regmask=[x0] minReg=1 wt=400.00> BB60 regmask=[x0] minReg=1 last fixed wt=400.00> BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 last fixed wt=400.00> BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 last fixed wt=400.00> CALL BB60 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> BB60 regmask=[x0] minReg=1 wt=400.00> BB60 regmask=[x1] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x3] minReg=1 wt=400.00> BB60 regmask=[x4] minReg=1 wt=400.00> BB60 regmask=[x5] minReg=1 wt=400.00> BB60 regmask=[x6] minReg=1 wt=400.00> BB60 regmask=[x7] minReg=1 wt=400.00> BB60 regmask=[x8] minReg=1 wt=400.00> BB60 regmask=[x9] minReg=1 wt=400.00> BB60 regmask=[x10] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x12] minReg=1 wt=400.00> BB60 regmask=[x13] minReg=1 wt=400.00> BB60 regmask=[x14] minReg=1 wt=400.00> BB60 regmask=[x15] minReg=1 wt=400.00> BB60 regmask=[xip0] minReg=1 wt=400.00> BB60 regmask=[xip1] minReg=1 wt=400.00> BB60 regmask=[lr] minReg=1 wt=400.00> DefList: { } N823 (???,???) [003855] ----------- * IL_OFFSET void INLRT @ 0x27A[E-] REG NA DefList: { } N825 ( 1, 1) [001152] ----------- * LCL_VAR long V17 loc13 u:1 NA REG NA DefList: { } N827 ( 4, 3) [001153] ---XG------ * IND ubyte REG NA LCL_VAR BB60 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1700.00> Interval 193: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N827.t1153. IND } N829 ( 1, 2) [001154] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N827.t1153. IND } N831 ( 6, 6) [001155] CNE---XG--N--- * JCMP void REG NA BB60 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> CHECKING LAST USES for BB60, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} ============================== use: {V01 V17 V70} def: {} NEW BLOCK BB61 Setting BB60 as the predecessor for determining incoming variable registers of BB61 DefList: { } N835 (???,???) [003856] ----------- * IL_OFFSET void INLRT @ 0x27F[E-] REG NA DefList: { } N837 ( 1, 1) [003713] ----------- * LCL_VAR byref V180 cse9 u:1 NA REG NA $246 DefList: { } N839 (???,???) [004217] ----------- * PUTARG_REG byref REG x0 BB61 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB61 regmask=[x0] minReg=1 last fixed wt=1500.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 194: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB61 regmask=[x0] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x0] minReg=1 fixed wt=1600.00> Assigning related to DefList: { N839.t4217. PUTARG_REG } N841 ( 3, 4) [002628] ----------- * LCL_FLD long V02 arg2 u:1[+8] NA REG NA $3ce Interval 195: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_FLD BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N839.t4217. PUTARG_REG; N841.t2628. LCL_FLD } N843 (???,???) [004218] ----------- * PUTARG_REG long REG x1 BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 last fixed wt=400.00> Interval 196: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB61 regmask=[x1] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x1] minReg=1 fixed wt=1600.00> DefList: { N839.t4217. PUTARG_REG; N843.t4218. PUTARG_REG } N845 ( 4, 5) [002626] -c--------- * FIELD_LIST struct REG NA $142 Contained DefList: { N839.t4217. PUTARG_REG; N843.t4218. PUTARG_REG } N847 ( 2, 8) [002625] H---------- * CNS_INT(h) long 0x40000000005401e8 ftn REG NA $43 Interval 197: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N839.t4217. PUTARG_REG; N843.t4218. PUTARG_REG; N847.t2625. CNS_INT } N849 (???,???) [004219] ----------- * PUTARG_REG long REG x11 BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 last fixed wt=400.00> Interval 198: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB61 regmask=[x11] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x11] minReg=1 fixed wt=1600.00> DefList: { N839.t4217. PUTARG_REG; N843.t4218. PUTARG_REG; N849.t4219. PUTARG_REG } N851 ( 1, 2) [001158] ----------- * CNS_INT int 2 REG NA $c2 Interval 199: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N839.t4217. PUTARG_REG; N843.t4218. PUTARG_REG; N849.t4219. PUTARG_REG; N851.t1158. CNS_INT } N853 (???,???) [004220] ----------- * PUTARG_REG int REG x2 BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 last fixed wt=400.00> Interval 200: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB61 regmask=[x2] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x2] minReg=1 fixed wt=1600.00> DefList: { N839.t4217. PUTARG_REG; N843.t4218. PUTARG_REG; N849.t4219. PUTARG_REG; N853.t4220. PUTARG_REG } N855 ( 21, 20) [001159] --CXG------ * CALL r2r_ind int REG NA $2c4 Interval 201: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB61 regmask=[x0] minReg=1 wt=400.00> BB61 regmask=[x0] minReg=1 last fixed wt=400.00> BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 last fixed wt=400.00> BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 last fixed wt=400.00> BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 last fixed wt=400.00> CALL BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> BB61 regmask=[x0] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x3] minReg=1 wt=400.00> BB61 regmask=[x4] minReg=1 wt=400.00> BB61 regmask=[x5] minReg=1 wt=400.00> BB61 regmask=[x6] minReg=1 wt=400.00> BB61 regmask=[x7] minReg=1 wt=400.00> BB61 regmask=[x8] minReg=1 wt=400.00> BB61 regmask=[x9] minReg=1 wt=400.00> BB61 regmask=[x10] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x12] minReg=1 wt=400.00> BB61 regmask=[x13] minReg=1 wt=400.00> BB61 regmask=[x14] minReg=1 wt=400.00> BB61 regmask=[x15] minReg=1 wt=400.00> BB61 regmask=[xip0] minReg=1 wt=400.00> BB61 regmask=[xip1] minReg=1 wt=400.00> BB61 regmask=[lr] minReg=1 wt=400.00> Interval 202: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB61 regmask=[x0] minReg=1 wt=400.00> CALL BB61 regmask=[x0] minReg=1 fixed wt=1600.00> DefList: { N855.t1159. CALL } N857 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 NA REG NA BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N859 (???,???) [003857] ----------- * IL_OFFSET void INLRT @ 0x288[E-] REG NA DefList: { } N861 ( 1, 1) [001164] ----------- * LCL_VAR int V16 loc12 u:16 NA REG NA $2c4 DefList: { } N863 ( 1, 1) [001165] ----------- * LCL_VAR int V15 loc11 u:2 NA REG NA $283 DefList: { } N865 ( 3, 3) [001166] J------N--- * EQ void REG NA $6b6 LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> DefList: { } N867 ( 5, 5) [001167] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB61, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V16 V17 V179 V180} ============================== use: {V02 V15 V180} def: {V16} NEW BLOCK BB62 Setting BB61 as the predecessor for determining incoming variable registers of BB62 DefList: { } N871 (???,???) [003858] ----------- * IL_OFFSET void INLRT @ 0x28E[E-] REG NA DefList: { } N873 ( 1, 1) [001168] ----------- * LCL_VAR int V16 loc12 u:16 NA (last use) REG NA $2c4 DefList: { } N875 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 NA REG NA LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> Exposed uses: BB62 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> CHECKING LAST USES for BB62, liveout={V00 V01 V02 V03 V11 V15 V17 V179 V180} ============================== use: {V16} def: {V15} NEW BLOCK BB63 Setting BB56 as the predecessor for determining incoming variable registers of BB63 DefList: { } N879 (???,???) [003859] ----------- * IL_OFFSET void INLRT @ 0x297[E-] REG NA DefList: { } N881 ( 1, 1) [000097] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N883 ( 3, 4) [002630] -c--------- * LEA(b+10) byref REG NA Contained DefList: { } N885 ( 5, 4) [000098] n---GO----- * IND ubyte REG NA LCL_VAR BB63 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 203: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB63 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N885.t98. IND } N887 ( 1, 2) [000099] -c--------- * CNS_INT int 3 REG NA $c3 Contained DefList: { N885.t98. IND } N889 ( 7, 7) [000100] J---GO-N--- * EQ void REG NA BB63 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> DefList: { } N891 ( 9, 9) [000101] ----GO----- * JTRUE void REG NA $301 CHECKING LAST USES for BB63, liveout={V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} ============================== use: {V01} def: {} NEW BLOCK BB64 Setting BB63 as the predecessor for determining incoming variable registers of BB64 DefList: { } N895 (???,???) [003860] ----------- * IL_OFFSET void INLRT @ 0x2A0[E-] REG NA DefList: { } N897 ( 1, 1) [001122] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N899 ( 3, 4) [002632] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N901 ( 1, 2) [001123] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N903 (???,???) [003861] -A--GO----- * STOREIND bool REG NA LCL_VAR BB64 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> CHECKING LAST USES for BB64, liveout={V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} ============================== use: {V01} def: {} NEW BLOCK BB65 Setting BB63 as the predecessor for determining incoming variable registers of BB65 DefList: { } N907 (???,???) [003862] ----------- * IL_OFFSET void INLRT @ 0x2A7[E-] REG NA DefList: { } N909 ( 1, 1) [000102] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N911 ( 3, 4) [002634] -c--------- * LEA(b+4) byref REG NA Contained DefList: { } N913 ( 1, 2) [000103] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N915 (???,???) [003863] -A--GO----- * STOREIND int REG NA LCL_VAR BB65 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> CHECKING LAST USES for BB65, liveout={V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} ============================== use: {V01} def: {} NEW BLOCK BB66 Setting BB60 as the predecessor for determining incoming variable registers of BB66 DefList: { } N919 (???,???) [003864] ----------- * IL_OFFSET void INLRT @ 0x2AE[E-] REG NA DefList: { } N921 (???,???) [003865] ----------- * IL_OFFSET void INLRT @ 0x2B2[E-] REG NA DefList: { } N923 ( 1, 1) [000106] ----------- * LCL_VAR int V06 loc2 u:2 NA REG NA $284 DefList: { } N925 ( 1, 1) [000107] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N927 ( 3, 3) [000108] Jc-----N--- * LT int REG NA $6b7 Contained DefList: { } N929 ( 1, 1) [000110] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N931 ( 1, 1) [000111] ----------- * LCL_VAR int V06 loc2 u:2 NA (last use) REG NA $284 DefList: { } N933 ( 3, 3) [000112] ----------- * SUB int REG NA $6b8 LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> Interval 204: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SUB BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N933.t112. SUB } N935 ( 1, 2) [001118] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N933.t112. SUB } N937 ( 8, 9) [003777] ----------- * SELECT int REG NA LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Interval 205: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SELECT BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N937.t3777. SELECT } N939 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 NA REG NA BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N941 (???,???) [003866] ----------- * IL_OFFSET void INLRT @ 0x2B5[E-] REG NA DefList: { } N943 ( 3, 2) [000116] ----------- * LCL_VAR int V44 tmp4 u:1 NA (last use) REG NA $292 DefList: { } N945 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 NA REG NA LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> DefList: { } N947 (???,???) [003867] ----------- * IL_OFFSET void INLRT @ 0x2B9[E-] REG NA DefList: { } N949 (???,???) [003868] ----------- * IL_OFFSET void INLRT @ 0x2BD[E-] REG NA DefList: { } N951 ( 1, 1) [000119] ----------- * LCL_VAR int V07 loc3 u:2 NA REG NA $285 DefList: { } N953 ( 1, 1) [000120] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N955 ( 3, 3) [000121] Jc-----N--- * GT int REG NA $6b9 Contained DefList: { } N957 ( 1, 1) [000123] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N959 ( 1, 1) [000124] ----------- * LCL_VAR int V07 loc3 u:2 NA (last use) REG NA $285 DefList: { } N961 ( 3, 3) [000125] ----------- * SUB int REG NA $6ba LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> Interval 206: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SUB BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N961.t125. SUB } N963 ( 1, 2) [001114] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N961.t125. SUB } N965 ( 8, 9) [003774] ----------- * SELECT int REG NA LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Interval 207: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SELECT BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N965.t3774. SELECT } N967 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 NA REG NA BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N969 (???,???) [003869] ----------- * IL_OFFSET void INLRT @ 0x2C0[E-] REG NA DefList: { } N971 ( 3, 2) [000129] ----------- * LCL_VAR int V45 tmp5 u:1 NA (last use) REG NA $293 DefList: { } N973 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 NA REG NA LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> DefList: { } N975 (???,???) [003870] ----------- * IL_OFFSET void INLRT @ 0x2C4[E-] REG NA DefList: { } N977 ( 1, 1) [000132] ----------- * LCL_VAR int V09 loc5 u:2 NA REG NA $4c1 DefList: { } N979 ( 1, 2) [000133] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N981 ( 3, 4) [000134] CEQ-------N--- * JCMP void REG NA LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2500.00> CHECKING LAST USES for BB66, liveout={V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} ============================== use: {V05 V06 V07 V09} def: {V06 V07 V44 V45} NEW BLOCK BB73 Setting BB66 as the predecessor for determining incoming variable registers of BB73 DefList: { } N985 (???,???) [003871] ----------- * IL_OFFSET void INLRT @ 0x2C8[E-] REG NA DefList: { } N987 ( 1, 1) [001108] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N989 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 NA REG NA LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> DefList: { } N991 (???,???) [003872] ----------- * IL_OFFSET void INLRT @ 0x2CB[E-] REG NA DefList: { } N993 ( 1, 2) [001111] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N995 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 NA REG NA STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> CHECKING LAST USES for BB73, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V179 V180} ============================== use: {V05} def: {V08 V14} NEW BLOCK BB74 Setting BB66 as the predecessor for determining incoming variable registers of BB74 DefList: { } N999 (???,???) [003873] ----------- * IL_OFFSET void INLRT @ 0x2D0[E-] REG NA DefList: { } N1001 (???,???) [003874] ----------- * IL_OFFSET void INLRT @ 0x2D9[E-] REG NA DefList: { } N1003 ( 1, 1) [000136] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N1005 ( 3, 4) [002636] -c--------- * LEA(b+4) byref REG NA Contained DefList: { } N1007 ( 4, 3) [000137] n---GO----- * IND int REG NA LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 208: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1007.t137. IND } N1009 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 NA REG NA BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N1011 ( 3, 2) [003684] ----------- * LCL_VAR int V178 cse7 u:1 NA REG NA DefList: { } N1013 ( 1, 1) [000138] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N1015 ( 13, 10) [000139] Jc--GO-N--- * GT int REG NA Contained DefList: { } N1017 ( 3, 2) [003686] ----------- * LCL_VAR int V178 cse7 u:1 NA REG NA DefList: { } N1019 ( 1, 1) [001104] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N1021 ( 18, 14) [003771] ----GO----- * SELECT int REG NA LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> Interval 209: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SELECT BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1021.t3771. SELECT } N1023 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 NA REG NA BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> DefList: { } N1025 (???,???) [003875] ----------- * IL_OFFSET void INLRT @ 0x2DC[E-] REG NA DefList: { } N1027 ( 3, 2) [000146] ----------- * LCL_VAR int V46 tmp6 u:1 NA (last use) REG NA $295 DefList: { } N1029 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 NA REG NA LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> DefList: { } N1031 (???,???) [003876] ----------- * IL_OFFSET void INLRT @ 0x2E4[E-] REG NA DefList: { } N1033 ( 3, 2) [003687] ----------- * LCL_VAR int V178 cse7 u:1 NA (last use) REG NA DefList: { } N1035 ( 1, 1) [000151] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N1037 ( 5, 4) [000152] ----G------ * SUB int REG NA LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> Interval 210: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SUB BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1037.t152. SUB } N1039 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 NA REG NA BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> CHECKING LAST USES for BB74, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V179 V180} ============================== use: {V01 V05} def: {V08 V14 V46 V178} NEW BLOCK BB78 Setting BB73 as the predecessor for determining incoming variable registers of BB78 DefList: { } N1043 (???,???) [003877] ----------- * IL_OFFSET void INLRT @ 0x2EE[E-] REG NA DefList: { } N1045 ( 1, 1) [000155] ----------- * LCL_VAR int V15 loc11 u:2 NA REG NA $283 DefList: { } N1047 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 NA REG NA LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N1049 (???,???) [003878] ----------- * IL_OFFSET void INLRT @ 0x2F2[E-] REG NA DefList: { } N1051 (???,???) [003879] ----------- * IL_OFFSET void INL09 @ 0x01F[E-] <- INLRT @ ??? REG NA DefList: { } N1053 ( 3, 3) [001550] ----------- * LCL_VAR_ADDR long V47 tmp7 NA REG NA $740 Interval 211: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LCL_VAR_ADDR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N1053.t1550. LCL_VAR_ADDR } N1055 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 NA REG NA BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N1057 (???,???) [003880] ----------- * IL_OFFSET void INL09 @ 0x026[E-] <- INLRT @ ??? REG NA DefList: { } N1059 (???,???) [003881] ----------- * IL_OFFSET void INLRT @ 0x2FF[E-] REG NA DefList: { } N1061 ( 1, 1) [002649] ----------- * LCL_VAR byref V151 tmp111 u:1 NA (last use) REG NA $24b DefList: { } N1063 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 NA REG NA LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> DefList: { } N1065 ( 1, 2) [003720] ----------- * CNS_INT int 4 REG NA $c8 Interval 212: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N1065.t3720. CNS_INT } N1067 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 NA REG NA BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> DefList: { } N1069 (???,???) [003882] ----------- * IL_OFFSET void INLRT @ 0x303[E-] REG NA DefList: { } N1071 ( 1, 2) [000175] ----------- * CNS_INT int -1 REG NA $c4 Interval 213: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N1071.t175. CNS_INT } N1073 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 NA REG NA BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> DefList: { } N1075 (???,???) [003883] ----------- * IL_OFFSET void INLRT @ 0x306[E-] REG NA DefList: { } N1077 ( 1, 1) [000941] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { } N1079 ( 3, 4) [002656] -c--------- * LEA(b+56) byref REG NA Contained DefList: { } N1081 ( 4, 3) [001570] ---XG------ * IND ref REG NA LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 214: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N1081.t1570. IND } N1083 (???,???) [004156] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N1081.t1570. IND } N1085 ( 6, 5) [000944] ---XG------ * IND int REG NA BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Interval 215: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N1085.t944. IND } N1087 ( 1, 2) [000945] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N1085.t944. IND } N1089 ( 11, 8) [000946] -c-XG--N--- * LE int REG NA Contained DefList: { N1085.t944. IND } N1091 ( 1, 1) [000178] ----------- * LCL_VAR int V12 loc8 u:3 NA REG NA $4c4 DefList: { N1085.t944. IND } N1093 ( 1, 2) [000179] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N1085.t944. IND } N1095 ( 6, 4) [000180] -c-----N--- * EQ int REG NA $70a Contained DefList: { N1085.t944. IND } N1097 ( 18, 13) [003732] Jc-XG--N--- * AND void REG NA Contained DefList: { N1085.t944. IND } N1099 ( 20, 15) [000181] ---XG------ * JTRUE void REG NA $VN.Void BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2900.00> CHECKING LAST USES for BB78, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} ============================== use: {V03 V12 V15} def: {V16 V20 V143 V144 V151 V152} NEW BLOCK BB79 Setting BB78 as the predecessor for determining incoming variable registers of BB79 DefList: { } N1103 (???,???) [003884] ----------- * IL_OFFSET void INLRT @ 0x30D[E-] REG NA DefList: { } N1105 (???,???) [003885] ----------- * IL_OFFSET void INLRT @ 0x31E[E-] REG NA DefList: { } N1107 ( 1, 1) [000948] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { } N1109 ( 3, 4) [002658] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1111 ( 4, 3) [000949] n---GO----- * IND ref REG NA LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 216: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1111.t949. IND } N1113 ( 4, 3) [000951] DA--GO----- * STORE_LCL_VAR ref V26 loc22 d:1 NA REG NA BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=550.00> DefList: { } N1115 (???,???) [003886] ----------- * IL_OFFSET void INLRT @ 0x326[E-] REG NA DefList: { } N1117 ( 1, 2) [000952] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1119 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 NA REG NA STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> DefList: { } N1121 (???,???) [003887] ----------- * IL_OFFSET void INLRT @ 0x329[E-] REG NA DefList: { } N1123 ( 1, 2) [000955] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1125 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 NA REG NA STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> DefList: { } N1127 (???,???) [003888] ----------- * IL_OFFSET void INLRT @ 0x32C[E-] REG NA DefList: { } N1129 ( 1, 1) [000958] ----------- * LCL_VAR ref V26 loc22 u:1 NA REG NA DefList: { } N1131 (???,???) [004158] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1133 ( 3, 3) [000959] ---X------- * IND int REG NA LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=550.00> Interval 217: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1133.t959. IND } N1135 ( 3, 3) [000961] DA-X------- * STORE_LCL_VAR int V29 loc25 d:1 NA REG NA BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> DefList: { } N1137 (???,???) [003889] ----------- * IL_OFFSET void INLRT @ 0x332[E-] REG NA DefList: { } N1139 ( 1, 1) [000962] ----------- * LCL_VAR int V29 loc25 u:1 NA REG NA DefList: { } N1141 ( 1, 2) [000963] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1143 ( 3, 4) [000964] CEQ-------N--- * JCMP void REG NA LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> CHECKING LAST USES for BB79, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144 V179 V180} ============================== use: {V03} def: {V26 V27 V28 V29} NEW BLOCK BB81 Setting BB79 as the predecessor for determining incoming variable registers of BB81 DefList: { } N1147 (???,???) [003890] ----------- * IL_OFFSET void INLRT @ 0x336[E-] REG NA DefList: { } N1149 ( 1, 1) [002659] ----------- * LCL_VAR ref V26 loc22 u:1 NA REG NA DefList: { } N1151 ( 1, 1) [002667] -c--------- * LEA(b+16) byref REG NA Contained DefList: { } N1153 ( 4, 3) [002671] n---GO----- * IND int REG NA LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 last wt=550.00> Interval 218: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1153.t2671. IND } N1155 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 NA REG NA BB81 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> CHECKING LAST USES for BB81, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144 V179 V180} ============================== use: {V26} def: {V28} NEW BLOCK BB82 Setting BB79 as the predecessor for determining incoming variable registers of BB82 DefList: { } N1159 (???,???) [003891] ----------- * IL_OFFSET void INLRT @ 0x33D[E-] REG NA DefList: { } N1161 ( 1, 1) [000966] ----------- * LCL_VAR int V28 loc24 u:2 NA REG NA $298 DefList: { } N1163 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 NA REG NA LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1100.00> DefList: { } N1165 ( 1, 1) [000969] ----------- * LCL_VAR int V08 loc4 u:1 NA REG NA $297 DefList: { } N1167 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 NA REG NA LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N1169 (???,???) [003892] ----------- * IL_OFFSET void INLRT @ 0x341[E-] REG NA DefList: { } N1171 ( 1, 1) [000970] ----------- * LCL_VAR int V14 loc10 u:1 NA REG NA $296 DefList: { } N1173 ( 1, 2) [000971] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1175 ( 3, 4) [000972] J------N--- * LT void REG NA $719 LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N1177 ( 5, 6) [000973] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB82, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144 V179 V180} ============================== use: {V08 V14 V28} def: {V30 V64} NEW BLOCK BB83 Setting BB82 as the predecessor for determining incoming variable registers of BB83 DefList: { } N1181 ( 3, 2) [000977] ----------- * LCL_VAR int V64 tmp24 u:1 NA (last use) REG NA $297 DefList: { } N1183 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 NA REG NA LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> Assigning related to STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N1185 ( 1, 2) [001091] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1187 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 NA REG NA STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> CHECKING LAST USES for BB83, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144 V179 V180} ============================== use: {V64} def: {V65 V66} NEW BLOCK BB84 Setting BB82 as the predecessor for determining incoming variable registers of BB84 DefList: { } N1191 ( 3, 2) [000978] ----------- * LCL_VAR int V64 tmp24 u:1 NA (last use) REG NA $297 DefList: { } N1193 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 NA REG NA LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N1195 ( 1, 1) [000979] ----------- * LCL_VAR int V14 loc10 u:1 NA REG NA $296 DefList: { } N1197 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 NA REG NA LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> CHECKING LAST USES for BB84, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144 V179 V180} ============================== use: {V14 V64} def: {V65 V66} NEW BLOCK BB85 Setting BB83 as the predecessor for determining incoming variable registers of BB85 DefList: { } N1201 ( 3, 2) [000986] ----------- * LCL_VAR int V65 tmp25 u:1 NA (last use) REG NA $297 DefList: { } N1203 ( 3, 2) [000987] ----------- * LCL_VAR int V66 tmp26 u:1 NA (last use) REG NA $299 DefList: { } N1205 ( 7, 5) [000988] ----------- * ADD int REG NA $71a LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> Interval 219: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1205.t988. ADD } N1207 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 NA REG NA BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> DefList: { } N1209 (???,???) [003893] ----------- * IL_OFFSET void INLRT @ 0x350[E-] REG NA DefList: { } N1211 (???,???) [003894] ----------- * IL_OFFSET void INLRT @ 0x355[E-] REG NA DefList: { } N1213 ( 1, 1) [000991] ----------- * LCL_VAR int V06 loc2 u:3 NA REG NA $292 DefList: { } N1215 ( 3, 2) [000992] ----------- * LCL_VAR int V31 loc27 u:1 NA REG NA $71a DefList: { } N1217 ( 5, 4) [000993] Jc-----N--- * GT int REG NA $71b Contained DefList: { } N1219 ( 1, 1) [000995] ----------- * LCL_VAR int V06 loc2 u:3 NA REG NA $292 DefList: { } N1221 ( 3, 2) [001087] ----------- * LCL_VAR int V31 loc27 u:1 NA (last use) REG NA $71a DefList: { } N1223 ( 10, 8) [003768] ----------- * SELECT int REG NA LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> Interval 220: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SELECT BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1223.t3768. SELECT } N1225 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 NA REG NA BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> DefList: { } N1227 (???,???) [003895] ----------- * IL_OFFSET void INLRT @ 0x359[E-] REG NA DefList: { } N1229 ( 3, 2) [000999] ----------- * LCL_VAR int V67 tmp27 u:1 NA (last use) REG NA $29a DefList: { } N1231 ( 3, 3) [001001] DA--------- * STORE_LCL_VAR int V32 loc28 d:1 NA REG NA LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> DefList: { } N1233 (???,???) [003896] ----------- * IL_OFFSET void INLRT @ 0x3C2[E-] REG NA DefList: { } N1235 ( 1, 1) [003158] ----------- * LCL_VAR int V32 loc28 u:1 NA REG NA $29a DefList: { } N1237 ( 1, 1) [003159] ----------- * LCL_VAR int V30 loc26 u:1 NA REG NA $298 DefList: { } N1239 ( 3, 3) [003157] J------N--- * LE void REG NA $71c LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1100.00> DefList: { } N1241 ( 5, 5) [003156] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB85, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} ============================== use: {V06 V30 V65 V66} def: {V31 V32 V67} NEW BLOCK BB89 Setting BB85 as the predecessor for determining incoming variable registers of BB89 DefList: { } N1245 (???,???) [003897] ----------- * IL_OFFSET void INLRT @ 0x35E[E-] REG NA DefList: { } N1247 ( 1, 1) [001006] ----------- * LCL_VAR int V30 loc26 u:2 NA REG NA $29d DefList: { } N1249 ( 1, 2) [001007] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1251 ( 3, 4) [001008] CEQ-------N--- * JCMP void REG NA LCL_VAR BB89 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1100.00> CHECKING LAST USES for BB89, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} ============================== use: {V30} def: {} NEW BLOCK BB90 Setting BB89 as the predecessor for determining incoming variable registers of BB90 DefList: { } N1255 (???,???) [003898] ----------- * IL_OFFSET void INLRT @ 0x362[E-] REG NA DefList: { } N1257 ( 1, 1) [001010] ----------- * LCL_VAR int V20 loc16 u:10 NA (last use) REG NA $29b DefList: { } N1259 ( 1, 2) [001011] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1261 ( 3, 4) [001012] ----------- * ADD int REG NA $71f LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> Interval 221: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N1261.t1012. ADD } N1263 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 NA REG NA BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> DefList: { } N1265 (???,???) [003899] ----------- * IL_OFFSET void INLRT @ 0x368[E-] REG NA DefList: { } N1267 ( 1, 1) [001015] ----------- * LCL_VAR int V20 loc16 u:11 NA REG NA $71f DefList: { } N1269 ( 1, 1) [001574] ----------- * LCL_VAR int V144 tmp104 u:3 NA REG NA $29c DefList: { } N1271 ( 3, 3) [001020] J------N--- * LT void REG NA $720 LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> DefList: { } N1273 ( 5, 5) [001021] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB90, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} ============================== use: {V20 V144} def: {V20} NEW BLOCK BB91 Setting BB90 as the predecessor for determining incoming variable registers of BB91 DefList: { } N1277 (???,???) [003900] ----------- * IL_OFFSET void INLRT @ 0x373[E-] REG NA DefList: { } N1279 ( 1, 1) [001578] ----------- * LCL_VAR int V144 tmp104 u:3 NA REG NA $29c DefList: { } N1281 ( 1, 2) [001065] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1283 ( 3, 4) [001066] ----------- * LSH int REG NA $721 LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> Interval 222: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LSH BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1283.t1066. LSH } N1285 ( 4, 6) [001067] ----------- * CAST long <- int REG NA $3cf BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 223: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1285.t1067. CAST } N1287 (???,???) [004221] ----------- * PUTARG_REG long REG x0 BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x0] minReg=1 last fixed wt=200.00> Interval 224: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB91 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB91 regmask=[x0] minReg=1 fixed wt=800.00> DefList: { N1287.t4221. PUTARG_REG } N1289 ( 2, 8) [002672] H---------- * CNS_INT(h) long 0x4000000000421858 ftn REG NA $49 Interval 225: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1287.t4221. PUTARG_REG; N1289.t2672. CNS_INT } N1291 (???,???) [004222] ----------- * PUTARG_REG long REG x11 BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 226: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB91 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB91 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N1287.t4221. PUTARG_REG; N1291.t4222. PUTARG_REG } N1293 ( 20, 18) [001068] --CXG------ * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 REG NA $330 Interval 227: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x0] minReg=1 last fixed wt=200.00> BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x1] minReg=1 wt=200.00> BB91 regmask=[x2] minReg=1 wt=200.00> BB91 regmask=[x3] minReg=1 wt=200.00> BB91 regmask=[x4] minReg=1 wt=200.00> BB91 regmask=[x5] minReg=1 wt=200.00> BB91 regmask=[x6] minReg=1 wt=200.00> BB91 regmask=[x7] minReg=1 wt=200.00> BB91 regmask=[x8] minReg=1 wt=200.00> BB91 regmask=[x9] minReg=1 wt=200.00> BB91 regmask=[x10] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x12] minReg=1 wt=200.00> BB91 regmask=[x13] minReg=1 wt=200.00> BB91 regmask=[x14] minReg=1 wt=200.00> BB91 regmask=[x15] minReg=1 wt=200.00> BB91 regmask=[xip0] minReg=1 wt=200.00> BB91 regmask=[xip1] minReg=1 wt=200.00> BB91 regmask=[lr] minReg=1 wt=200.00> Interval 228: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB91 regmask=[x0] minReg=1 wt=200.00> CALL BB91 regmask=[x0] minReg=1 fixed wt=800.00> DefList: { N1293.t1068. CALL } N1295 ( 20, 18) [001070] DA-XG------ * STORE_LCL_VAR ref V33 loc29 d:1 NA REG NA BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N1297 (???,???) [003901] ----------- * IL_OFFSET void INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] REG NA DefList: { } N1299 (???,???) [003902] ----------- * IL_OFFSET void INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] REG NA DefList: { } N1301 ( 1, 1) [002689] ----------- * LCL_VAR ref V33 loc29 u:1 NA REG NA $800 DefList: { } N1303 ( 1, 2) [002690] -c--------- * CNS_INT long 16 Fseq[] REG NA $200 Contained DefList: { } N1305 ( 3, 4) [002691] -----O----- * ADD byref REG NA $253 LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 229: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1305.t2691. ADD } N1307 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 NA REG NA BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N1309 (???,???) [003903] ----------- * IL_OFFSET void INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] REG NA DefList: { } N1311 ( 1, 1) [001607] ----------- * LCL_VAR ref V33 loc29 u:1 NA REG NA $800 DefList: { } N1313 (???,???) [004160] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1315 ( 3, 3) [001608] ---X------- * IND int REG NA $2cc LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 230: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1315.t1608. IND } N1317 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 NA REG NA BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N1319 ( 1, 1) [002694] ----------- * LCL_VAR byref V159 tmp119 u:1 NA (last use) REG NA $382 DefList: { } N1321 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 NA REG NA LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N1323 ( 1, 1) [001620] ----------- * LCL_VAR int V144 tmp104 u:3 NA REG NA $29c DefList: { } N1325 ( 1, 1) [001647] ----------- * LCL_VAR int V160 tmp120 u:1 NA (last use) REG NA $2a0 DefList: { } N1327 ( 3, 3) [001628] N------N-U- * GT void REG NA $722 LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N1329 ( 5, 5) [001629] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB91, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V161 V179 V180} ============================== use: {V144} def: {V33 V159 V160 V161} NEW BLOCK BB95 Setting BB91 as the predecessor for determining incoming variable registers of BB95 DefList: { } N1333 (???,???) [003904] ----------- * IL_OFFSET void INL17 @ 0x00F[E-] <- INLRT @ ??? REG NA DefList: { } N1335 ( 1, 1) [001639] ----------- * LCL_VAR int V144 tmp104 u:3 NA (last use) REG NA $29c DefList: { } N1337 ( 2, 3) [001640] ---------U- * CAST long <- ulong <- uint REG NA $3d0 LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> Interval 231: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1337.t1640. CAST } N1339 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 NA REG NA BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N1341 (???,???) [003905] ----------- * IL_OFFSET void INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? REG NA DefList: { } N1343 ( 1, 1) [001663] ----------- * LCL_VAR long V83 tmp43 u:1 NA (last use) REG NA $3d0 DefList: { } N1345 ( 1, 2) [001665] -c--------- * CNS_INT long 2 REG NA $20a Contained DefList: { } N1347 ( 3, 4) [001666] ----------- * LSH long REG NA $3d1 LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Interval 232: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LSH BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1347.t1666. LSH } N1349 (???,???) [004223] ----------- * PUTARG_REG long REG x2 BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 last fixed wt=200.00> Interval 233: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB95 regmask=[x2] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x2] minReg=1 fixed wt=800.00> DefList: { N1349.t4223. PUTARG_REG } N1351 ( 1, 1) [001661] ----------- * LCL_VAR byref V161 tmp121 u:1 NA (last use) REG NA $382 DefList: { N1349.t4223. PUTARG_REG } N1353 (???,???) [004224] ----------- * PUTARG_REG byref REG x0 Last use of V161 between PUTARG and CALL. Removing occupied arg regs from preferences: [x2] BB95 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB95 regmask=[x0] minReg=1 last fixed wt=400.00> Interval 234: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB95 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x0] minReg=1 fixed wt=800.00> DefList: { N1349.t4223. PUTARG_REG; N1353.t4224. PUTARG_REG } N1355 ( 1, 1) [001662] ----------- * LCL_VAR byref V143 tmp103 u:3 NA (last use) REG NA $381 DefList: { N1349.t4223. PUTARG_REG; N1353.t4224. PUTARG_REG } N1357 (???,???) [004225] ----------- * PUTARG_REG byref REG x1 Last use of V143 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0 x2] BB95 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB95 regmask=[x1] minReg=1 last fixed wt=1900.00> Interval 235: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB95 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N1349.t4223. PUTARG_REG; N1353.t4224. PUTARG_REG; N1357.t4225. PUTARG_REG } N1359 ( 2, 8) [002700] H---------- * CNS_INT(h) long 0x4000000000420490 ftn REG NA $4b Interval 236: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1349.t4223. PUTARG_REG; N1353.t4224. PUTARG_REG; N1357.t4225. PUTARG_REG; N1359.t2700. CNS_INT } N1361 (???,???) [004226] ----------- * PUTARG_REG long REG x11 BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 237: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB95 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N1349.t4223. PUTARG_REG; N1353.t4224. PUTARG_REG; N1357.t4225. PUTARG_REG; N1361.t4226. PUTARG_REG } N1363 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 238: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 last fixed wt=200.00> BB95 regmask=[x0] minReg=1 wt=200.00> BB95 regmask=[x0] minReg=1 last fixed wt=200.00> BB95 regmask=[x1] minReg=1 wt=200.00> BB95 regmask=[x1] minReg=1 last fixed wt=200.00> BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB95 regmask=[x0] minReg=1 wt=200.00> BB95 regmask=[x1] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x3] minReg=1 wt=200.00> BB95 regmask=[x4] minReg=1 wt=200.00> BB95 regmask=[x5] minReg=1 wt=200.00> BB95 regmask=[x6] minReg=1 wt=200.00> BB95 regmask=[x7] minReg=1 wt=200.00> BB95 regmask=[x8] minReg=1 wt=200.00> BB95 regmask=[x9] minReg=1 wt=200.00> BB95 regmask=[x10] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x12] minReg=1 wt=200.00> BB95 regmask=[x13] minReg=1 wt=200.00> BB95 regmask=[x14] minReg=1 wt=200.00> BB95 regmask=[x15] minReg=1 wt=200.00> BB95 regmask=[xip0] minReg=1 wt=200.00> BB95 regmask=[xip1] minReg=1 wt=200.00> BB95 regmask=[lr] minReg=1 wt=200.00> DefList: { } N1365 (???,???) [003906] ----------- * IL_OFFSET void INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] REG NA DefList: { } N1367 (???,???) [003907] ----------- * IL_OFFSET void INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] REG NA DefList: { } N1369 ( 1, 1) [002718] ----------- * LCL_VAR ref V33 loc29 u:1 NA REG NA $800 DefList: { } N1371 ( 1, 2) [002719] -c--------- * CNS_INT long 16 Fseq[] REG NA $200 Contained DefList: { } N1373 ( 3, 4) [002720] -----O----- * ADD byref REG NA $253 LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 239: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1373.t2720. ADD } N1375 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 NA REG NA BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N1377 (???,???) [003908] ----------- * IL_OFFSET void INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] REG NA DefList: { } N1379 ( 1, 1) [001719] ----------- * LCL_VAR ref V33 loc29 u:1 NA (last use) REG NA $800 DefList: { } N1381 (???,???) [004162] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1383 ( 3, 3) [001720] ---X------- * IND int REG NA $2cc LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 240: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1383.t1720. IND } N1385 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 NA REG NA BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N1387 (???,???) [003909] ----------- * IL_OFFSET void INLRT @ 0x391[E-] REG NA DefList: { } N1389 ( 1, 1) [002723] ----------- * LCL_VAR byref V163 tmp123 u:1 NA (last use) REG NA $383 DefList: { } N1391 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 NA REG NA LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> DefList: { } N1393 ( 1, 1) [002726] ----------- * LCL_VAR int V164 tmp124 u:1 NA (last use) REG NA $2a1 DefList: { } N1395 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 NA REG NA LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> CHECKING LAST USES for BB95, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} ============================== use: {V33 V143 V144 V161} def: {V83 V143 V144 V163 V164} NEW BLOCK BB100 Setting BB90 as the predecessor for determining incoming variable registers of BB100 DefList: { } N1399 (???,???) [003910] ----------- * IL_OFFSET void INLRT @ 0x39A[E-] REG NA DefList: { } N1401 ( 1, 1) [001024] ----------- * LCL_VAR int V20 loc16 u:11 NA REG NA $71f DefList: { } N1403 ( 1, 1) [001028] ----------- * LCL_VAR int V144 tmp104 u:4 NA REG NA $2a2 DefList: { } N1405 ( 6, 9) [001029] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $334 LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> DefList: { } N1407 ( 1, 1) [001033] ----------- * LCL_VAR byref V143 tmp103 u:4 NA REG NA $384 DefList: { } N1409 ( 1, 1) [001025] ----------- * LCL_VAR int V20 loc16 u:11 NA REG NA $71f DefList: { } N1411 ( 2, 3) [001030] -c-------U- * CAST long <- uint REG NA $3d2 Contained DefList: { } N1413 ( 1, 2) [001031] -c--------- * CNS_INT long 2 REG NA $20a Contained DefList: { } N1415 ( 4, 6) [001032] -c--------- * BFIZ long REG NA Contained DefList: { } N1417 ( 6, 8) [001034] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { } N1419 ( 1, 1) [001036] ----------- * LCL_VAR int V28 loc24 u:3 NA REG NA $29f DefList: { } N1421 (???,???) [003911] -A-XGO----- * STOREIND int REG NA LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> DefList: { } N1423 (???,???) [003912] ----------- * IL_OFFSET void INLRT @ 0x3A6[E-] REG NA DefList: { } N1425 ( 1, 1) [001039] ----------- * LCL_VAR int V27 loc23 u:2 NA REG NA $29e DefList: { } N1427 ( 1, 1) [001040] ----------- * LCL_VAR int V29 loc25 u:1 NA REG NA DefList: { } N1429 ( 1, 2) [001041] -c--------- * CNS_INT int -1 REG NA $c4 Contained DefList: { } N1431 ( 3, 4) [001042] ----------- * ADD int REG NA LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> Interval 241: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N1431.t1042. ADD } N1433 ( 5, 6) [001043] J------N--- * GE void REG NA LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N1435 ( 7, 8) [001044] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB100, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} ============================== use: {V20 V27 V28 V29 V143 V144} def: {} NEW BLOCK BB101 Setting BB100 as the predecessor for determining incoming variable registers of BB101 DefList: { } N1439 (???,???) [003913] ----------- * IL_OFFSET void INLRT @ 0x3AE[E-] REG NA DefList: { } N1441 ( 1, 1) [001050] ----------- * LCL_VAR int V27 loc23 u:2 NA (last use) REG NA $29e DefList: { } N1443 ( 1, 2) [001051] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1445 ( 3, 4) [001052] ----------- * ADD int REG NA $727 LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> Interval 242: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1445.t1052. ADD } N1447 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 NA REG NA BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> DefList: { } N1449 (???,???) [003914] ----------- * IL_OFFSET void INLRT @ 0x3B4[E-] REG NA DefList: { } N1451 ( 1, 1) [001056] ----------- * LCL_VAR int V27 loc23 u:4 NA REG NA $727 DefList: { } N1453 ( 1, 1) [001055] ----------- * LCL_VAR ref V26 loc22 u:1 NA REG NA DefList: { } N1455 (???,???) [004164] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1457 ( 3, 3) [002732] ---X------- * IND int REG NA LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=550.00> Interval 243: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1457.t2732. IND } N1459 ( 8, 11) [002733] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N1461 ( 1, 1) [002730] ----------- * LCL_VAR ref V26 loc22 u:1 NA REG NA DefList: { } N1463 ( 1, 2) [002737] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N1465 ( 3, 4) [002738] ----------- * ADD byref REG NA LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=550.00> Interval 244: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1465.t2738. ADD } N1467 ( 1, 1) [002731] ----------- * LCL_VAR int V27 loc23 u:4 NA REG NA $727 DefList: { N1465.t2738. ADD } N1469 ( 2, 3) [002734] -c-------U- * CAST long <- uint REG NA $3d4 Contained DefList: { N1465.t2738. ADD } N1471 ( 1, 2) [002735] -c-----N--- * CNS_INT long 2 REG NA $20a Contained DefList: { N1465.t2738. ADD } N1473 ( 4, 6) [002736] -c--------- * BFIZ long REG NA Contained DefList: { N1465.t2738. ADD } N1475 ( 7, 10) [002739] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N1465.t2738. ADD } N1477 ( 10, 12) [002742] n---GO----- * IND int REG NA BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> Interval 245: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1477.t2742. IND } N1479 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 NA REG NA BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1100.00> CHECKING LAST USES for BB101, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} ============================== use: {V26 V27} def: {V27 V30} NEW BLOCK BB102 Setting BB100 as the predecessor for determining incoming variable registers of BB102 DefList: { } N1483 (???,???) [003915] ----------- * IL_OFFSET void INLRT @ 0x3BB[E-] REG NA DefList: { } N1485 ( 1, 1) [001045] ----------- * LCL_VAR int V28 loc24 u:3 NA (last use) REG NA $29f DefList: { } N1487 ( 1, 1) [001046] ----------- * LCL_VAR int V30 loc26 u:3 NA REG NA $2a3 DefList: { } N1489 ( 3, 3) [001047] ----------- * ADD int REG NA $72b LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1100.00> Interval 246: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N1489.t1047. ADD } N1491 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 NA REG NA BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> DefList: { } N1493 (???,???) [003916] ----------- * IL_OFFSET void INLRT @ 0x3C2[E-] REG NA DefList: { } N1495 ( 1, 1) [001002] ----------- * LCL_VAR int V32 loc28 u:1 NA REG NA $29a DefList: { } N1497 ( 1, 1) [001003] ----------- * LCL_VAR int V28 loc24 u:4 NA REG NA $72b DefList: { } N1499 ( 3, 3) [001004] J------N--- * GT void REG NA $72c LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> DefList: { } N1501 ( 5, 5) [001005] ----------- * JTRUE void REG NA $VN.Void Exposed uses: BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> CHECKING LAST USES for BB102, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} ============================== use: {V28 V30 V32} def: {V28} NEW BLOCK BB103 Setting BB89 as the predecessor for determining incoming variable registers of BB103 DefList: { } N1505 (???,???) [003917] ----------- * IL_OFFSET void INLRT @ 0x3C8[E-] REG NA DefList: { } N1507 ( 1, 1) [000182] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N1509 ( 3, 4) [002744] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1511 ( 5, 4) [000183] n---GO----- * IND bool REG NA LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 247: bool RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N1511.t183. IND } N1513 ( 1, 2) [000184] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N1511.t183. IND } N1515 ( 10, 7) [000185] -c--GO-N--- * EQ int REG NA Contained DefList: { N1511.t183. IND } N1517 ( 1, 1) [000927] ----------- * LCL_VAR int V16 loc12 u:3 NA REG NA $283 DefList: { N1511.t183. IND } N1519 ( 1, 2) [000928] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N1511.t183. IND } N1521 ( 6, 4) [000929] -c-----N--- * NE int REG NA $733 Contained DefList: { N1511.t183. IND } N1523 ( 17, 12) [003734] Jc--GO-N--- * AND void REG NA Contained DefList: { N1511.t183. IND } N1525 ( 19, 14) [000186] ----GO----- * JTRUE void REG NA $301 BB103 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> CHECKING LAST USES for BB103, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} ============================== use: {V01 V16} def: {} NEW BLOCK BB104 Setting BB103 as the predecessor for determining incoming variable registers of BB104 DefList: { } N1529 (???,???) [003918] ----------- * IL_OFFSET void INLRT @ 0x3D0[E-] REG NA DefList: { } N1531 (???,???) [003919] ----------- * IL_OFFSET void INLRT @ 0x3D4[E-] REG NA DefList: { } N1533 ( 1, 1) [000931] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N1535 ( 3, 4) [002746] -c--------- * LEA(b+4) byref REG NA Contained DefList: { } N1537 ( 4, 3) [000932] n---GO----- * IND int REG NA LCL_VAR BB104 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 248: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB104 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1537.t932. IND } N1539 ( 1, 2) [000933] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N1537.t932. IND } N1541 ( 6, 6) [000934] CEQ----GO-N--- * JCMP void REG NA BB104 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> CHECKING LAST USES for BB104, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} ============================== use: {V01} def: {} NEW BLOCK BB106 Setting BB104 as the predecessor for determining incoming variable registers of BB106 DefList: { } N1545 (???,???) [003920] ----------- * IL_OFFSET void INLRT @ 0x3DC[E-] REG NA DefList: { } N1547 ( 1, 1) [000937] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { } N1549 ( 3, 4) [002748] -c--------- * LEA(b+40) byref REG NA Contained DefList: { } N1551 ( 4, 3) [001730] ---XG------ * IND ref REG NA LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 249: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1551.t1730. IND } N1553 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 NA REG NA BB106 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> DefList: { } N1555 (???,???) [003921] ----------- * IL_OFFSET void INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] REG NA DefList: { } N1557 ( 1, 1) [001732] ----------- * LCL_VAR ref V86 tmp46 u:1 NA REG NA DefList: { } N1559 ( 1, 2) [001733] -c--------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N1561 ( 3, 4) [001734] CEQ-------N--- * JCMP void REG NA LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> CHECKING LAST USES for BB106, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144 V179 V180} ============================== use: {V03} def: {V86} NEW BLOCK BB107 Setting BB106 as the predecessor for determining incoming variable registers of BB107 DefList: { } N1565 (???,???) [003922] ----------- * IL_OFFSET void INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] REG NA DefList: { } N1567 ( 1, 1) [000936] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N1569 ( 3, 4) [002750] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1571 ( 4, 3) [001736] ---XG------ * IND int REG NA LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 250: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1571.t1736. IND } N1573 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 NA REG NA BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> DefList: { } N1575 (???,???) [003923] ----------- * IL_OFFSET void INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] REG NA DefList: { } N1577 ( 1, 1) [001739] ----------- * LCL_VAR ref V86 tmp46 u:1 NA REG NA DefList: { } N1579 (???,???) [004166] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1581 ( 3, 3) [001740] ---X------- * IND int REG NA LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> Interval 251: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1581.t1740. IND } N1583 ( 1, 2) [001741] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { N1581.t1740. IND } N1585 ( 8, 6) [001742] Nc-X---N-U- * NE int REG NA Contained DefList: { N1581.t1740. IND } N1587 ( 3, 2) [001747] ----------- * LCL_VAR int V87 tmp47 u:1 NA REG NA DefList: { N1581.t1740. IND } N1589 ( 1, 1) [001748] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N1581.t1740. IND } N1591 ( 3, 4) [002754] -c--------- * LEA(b+24) byref REG NA Contained DefList: { N1581.t1740. IND } N1593 ( 4, 3) [001786] n---GO----- * IND int REG NA LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 252: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1581.t1740. IND; N1593.t1786. IND } N1595 ( 11, 6) [001752] Nc--GO-N-U- * GE int REG NA Contained DefList: { N1581.t1740. IND; N1593.t1786. IND } N1597 ( 20, 13) [003736] Jc-XGO-N--- * AND void REG NA Contained DefList: { N1581.t1740. IND; N1593.t1786. IND } N1599 ( 22, 15) [001743] ---XGO----- * JTRUE void REG NA BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> CHECKING LAST USES for BB107, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144 V179 V180} ============================== use: {V00 V86} def: {V87} NEW BLOCK BB108 Setting BB107 as the predecessor for determining incoming variable registers of BB108 DefList: { } N1603 (???,???) [003924] ----------- * IL_OFFSET void INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] REG NA DefList: { } N1605 (???,???) [003925] ----------- * IL_OFFSET void INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] REG NA DefList: { } N1607 ( 1, 1) [002758] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N1609 ( 1, 2) [002759] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N1611 ( 3, 4) [002760] -----O----- * ADD byref REG NA $25c LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 253: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1611.t2760. ADD } N1613 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 NA REG NA BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Assigning related to STORE_LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> DefList: { } N1615 (???,???) [003926] ----------- * IL_OFFSET void INL26 @ ??? <- INLRT @ 0x3DC[E-] REG NA DefList: { } N1617 ( 3, 2) [001756] ----------- * LCL_VAR int V87 tmp47 u:1 NA REG NA DefList: { } N1619 ( 1, 1) [001761] ----------- * LCL_VAR byref V88 tmp48 u:1 NA REG NA $25c DefList: { } N1621 ( 3, 4) [002763] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1623 ( 4, 3) [001762] n---GO----- * IND int REG NA LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> Interval 254: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1623.t1762. IND } N1625 ( 11, 12) [001763] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> DefList: { } N1627 ( 1, 1) [001760] ----------- * LCL_VAR byref V88 tmp48 u:1 NA (last use) REG NA $25c DefList: { } N1629 ( 3, 2) [001767] n---GO----- * IND byref REG NA LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> Interval 255: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1629.t1767. IND } N1631 ( 3, 2) [001757] ----------- * LCL_VAR int V87 tmp47 u:1 NA REG NA DefList: { N1629.t1767. IND } N1633 ( 4, 4) [001764] -c-------U- * CAST long <- uint REG NA Contained DefList: { N1629.t1767. IND } N1635 ( 1, 2) [001765] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N1629.t1767. IND } N1637 ( 6, 7) [001766] ----------- * BFIZ long REG NA LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> Interval 256: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BFIZ BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1629.t1767. IND; N1637.t1766. BFIZ } N1639 ( 10, 10) [001768] ----GO-N--- * ADD byref REG NA BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Interval 257: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1639.t1768. ADD } N1641 ( 1, 1) [002765] ----------- * LCL_VAR ref V86 tmp46 u:1 NA (last use) REG NA DefList: { N1639.t1768. ADD } N1643 ( 1, 1) [002772] -c--------- * LEA(b+12) byref REG NA Contained DefList: { N1639.t1768. ADD } N1645 ( 5, 4) [002777] n---GO----- * IND ushort REG NA LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> Interval 258: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1639.t1768. ADD; N1645.t2777. IND } N1647 (???,???) [003927] -A-XGO----- * STOREIND short REG NA BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> DefList: { } N1649 (???,???) [003928] ----------- * IL_OFFSET void INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] REG NA DefList: { } N1651 ( 3, 2) [001777] ----------- * LCL_VAR int V87 tmp47 u:1 NA (last use) REG NA DefList: { } N1653 ( 1, 2) [001778] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1655 ( 5, 5) [001779] ----------- * ADD int REG NA LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> Interval 259: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1655.t1779. ADD } N1657 ( 1, 1) [001776] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N1655.t1779. ADD } N1659 ( 3, 4) [002779] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N1655.t1779. ADD } N1661 (???,???) [003929] -A--GO----- * STOREIND int REG NA LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> CHECKING LAST USES for BB108, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} ============================== use: {V00 V86 V87} def: {V88} NEW BLOCK BB111 Setting BB107 as the predecessor for determining incoming variable registers of BB111 DefList: { } N1665 (???,???) [003946] ----------- * IL_OFFSET void INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] REG NA DefList: { } N1667 ( 1, 1) [001744] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N1669 (???,???) [004231] ----------- * PUTARG_REG byref REG x0 BB111 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB111 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 260: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB111 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x0] minReg=1 fixed wt=200.00> Assigning related to DefList: { N1669.t4231. PUTARG_REG } N1671 ( 1, 1) [001745] ----------- * LCL_VAR ref V86 tmp46 u:1 NA (last use) REG NA DefList: { N1669.t4231. PUTARG_REG } N1673 (???,???) [004232] ----------- * PUTARG_REG ref REG x1 Last use of V86 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB111 regmask=[x1] minReg=1 wt=50.00> LCL_VAR BB111 regmask=[x1] minReg=1 last fixed wt=500.00> Interval 261: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB111 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x1] minReg=1 fixed wt=200.00> DefList: { N1669.t4231. PUTARG_REG; N1673.t4232. PUTARG_REG } N1675 ( 2, 8) [002780] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn REG NA $4f Interval 262: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB111 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N1669.t4231. PUTARG_REG; N1673.t4232. PUTARG_REG; N1675.t2780. CNS_INT } N1677 (???,???) [004233] ----------- * PUTARG_REG long REG x11 BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 last fixed wt=50.00> Interval 263: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB111 regmask=[x11] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x11] minReg=1 fixed wt=200.00> DefList: { N1669.t4231. PUTARG_REG; N1673.t4232. PUTARG_REG; N1677.t4233. PUTARG_REG } N1679 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void Interval 264: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB111 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB111 regmask=[x0] minReg=1 wt=50.00> BB111 regmask=[x0] minReg=1 last fixed wt=50.00> BB111 regmask=[x1] minReg=1 wt=50.00> BB111 regmask=[x1] minReg=1 last fixed wt=50.00> BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 last fixed wt=50.00> CALL BB111 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB111 regmask=[x0] minReg=1 wt=50.00> BB111 regmask=[x1] minReg=1 wt=50.00> BB111 regmask=[x2] minReg=1 wt=50.00> BB111 regmask=[x3] minReg=1 wt=50.00> BB111 regmask=[x4] minReg=1 wt=50.00> BB111 regmask=[x5] minReg=1 wt=50.00> BB111 regmask=[x6] minReg=1 wt=50.00> BB111 regmask=[x7] minReg=1 wt=50.00> BB111 regmask=[x8] minReg=1 wt=50.00> BB111 regmask=[x9] minReg=1 wt=50.00> BB111 regmask=[x10] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x12] minReg=1 wt=50.00> BB111 regmask=[x13] minReg=1 wt=50.00> BB111 regmask=[x14] minReg=1 wt=50.00> BB111 regmask=[x15] minReg=1 wt=50.00> BB111 regmask=[xip0] minReg=1 wt=50.00> BB111 regmask=[xip1] minReg=1 wt=50.00> BB111 regmask=[lr] minReg=1 wt=50.00> CHECKING LAST USES for BB111, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} ============================== use: {V00 V86} def: {} NEW BLOCK BB112 Setting BB103 as the predecessor for determining incoming variable registers of BB112 DefList: { } N1683 (???,???) [003930] ----------- * IL_OFFSET void INLRT @ 0x3E8[E-] REG NA DefList: { } N1685 ( 1, 2) [002781] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1687 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 NA REG NA STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> DefList: { } N1689 (???,???) [003931] ----------- * IL_OFFSET void INLRT @ 0x3EB[E-] REG NA DefList: { } N1691 ( 1, 1) [003714] ----------- * LCL_VAR byref V180 cse9 u:1 NA (last use) REG NA $246 DefList: { } N1693 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 NA REG NA LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1500.00> Assigning related to STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> DefList: { } N1695 (???,???) [003932] ----------- * IL_OFFSET void INLRT @ 0x3EB[E-] REG NA DefList: { } N1697 ( 1, 1) [001792] ----------- * LCL_VAR byref V165 tmp125 u:1 NA REG NA $246 DefList: { } N1699 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 NA REG NA LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> DefList: { } N1701 (???,???) [003933] ----------- * IL_OFFSET void INLRT @ 0x3F3[E-] REG NA DefList: { } N1703 ( 1, 1) [000197] ----------- * LCL_VAR byref V165 tmp125 u:1 NA (last use) REG NA $246 DefList: { } N1705 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 NA REG NA LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> Assigning related to STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> DefList: { } N1707 ( 1, 1) [002791] ----------- * LCL_VAR long V169 tmp129 u:1 NA (last use) REG NA $3c4 DefList: { } N1709 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 NA REG NA LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> DefList: { } N1711 (???,???) [003934] ----------- * IL_OFFSET void INLRT @ 0x3F8[E-] REG NA DefList: { } N1713 ( 1, 1) [000201] ----------- * LCL_VAR long V17 loc13 u:1 NA REG NA DefList: { } N1715 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 NA REG NA LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1700.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> CHECKING LAST USES for BB112, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V17 V180} def: {V21 V34 V36 V165 V169} NEW BLOCK BB245 Setting BB112 as the predecessor for determining incoming variable registers of BB245 DefList: { } N1719 (???,???) [003935] ----------- * IL_OFFSET void INLRT @ 0x7AA[E-] REG NA DefList: { } N1721 ( 1, 1) [000204] ----------- * LCL_VAR int V16 loc12 u:4 NA REG NA $2ae DefList: { } N1723 ( 1, 1) [003707] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N1725 ( 3, 3) [000209] J------N--- * GE void REG NA $897 LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N1727 ( 5, 5) [000210] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB245, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V16 V179} def: {} NEW BLOCK BB246 Setting BB245 as the predecessor for determining incoming variable registers of BB246 DefList: { } N1731 (???,???) [003936] ----------- * IL_OFFSET void INLRT @ 0x7B5[E-] REG NA DefList: { } N1733 ( 1, 1) [000243] ----------- * LCL_VAR int V16 loc12 u:4 NA (last use) REG NA $2ae DefList: { } N1735 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 NA REG NA LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N1737 (???,???) [003937] ----------- * IL_OFFSET void INLRT @ 0x7B5[E-] REG NA DefList: { } N1739 ( 1, 1) [000244] ----------- * LCL_VAR int V49 tmp9 u:1 NA REG NA $2ae DefList: { } N1741 ( 1, 2) [000245] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1743 ( 3, 4) [000246] ----------- * ADD int REG NA $898 LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 265: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N1743.t246. ADD } N1745 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 NA REG NA BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N1747 ( 1, 1) [000242] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N1749 ( 1, 1) [000251] ----------- * LCL_VAR int V49 tmp9 u:1 NA (last use) REG NA $2ae DefList: { } N1751 ( 2, 3) [000252] -c--------- * CAST long <- int REG NA $3db Contained DefList: { } N1753 ( 1, 2) [000254] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N1755 ( 4, 6) [000255] -c--------- * BFIZ long REG NA Contained DefList: { } N1757 ( 6, 8) [000256] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N1759 ( 9, 10) [000257] ---XG------ * IND ushort REG NA LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 266: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> DefList: { N1759.t257. IND } N1761 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 NA REG NA BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> DefList: { } N1763 ( 1, 1) [000261] ----------- * LCL_VAR int V50 tmp10 u:1 NA (last use) REG NA DefList: { } N1765 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 NA REG NA LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Assigning related to STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N1767 ( 1, 1) [000260] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N1769 ( 1, 2) [000264] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1771 ( 3, 4) [000265] CEQ-------N--- * JCMP void REG NA LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> CHECKING LAST USES for BB246, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V16 V34} def: {V16 V18 V49 V50} NEW BLOCK BB247 Setting BB246 as the predecessor for determining incoming variable registers of BB247 DefList: { } N1775 (???,???) [003938] ----------- * IL_OFFSET void INLRT @ 0x7C8[E-] REG NA DefList: { } N1777 ( 1, 1) [000267] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N1779 ( 1, 2) [000268] -c--------- * CNS_INT int 59 REG NA $d1 Contained DefList: { } N1781 ( 3, 4) [000269] N------N-U- * NE void REG NA LCL_VAR BB247 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N1783 ( 5, 6) [000270] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB247, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB113 Setting BB247 as the predecessor for determining incoming variable registers of BB113 DefList: { } N1787 (???,???) [003947] ----------- * IL_OFFSET void INLRT @ 0x401[E-] REG NA DefList: { } N1789 ( 1, 1) [000271] ----------- * LCL_VAR int V14 loc10 u:2 NA REG NA $2ab DefList: { } N1791 ( 1, 2) [000272] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1793 ( 3, 4) [000273] J------N--- * LE void REG NA $89f LCL_VAR BB113 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N1795 ( 5, 6) [000274] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB113, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V14} def: {} NEW BLOCK BB114 Setting BB113 as the predecessor for determining incoming variable registers of BB114 DefList: { } N1799 (???,???) [003948] ----------- * IL_OFFSET void INLRT @ 0x406[E-] REG NA DefList: { } N1801 ( 1, 1) [000821] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N1803 ( 1, 2) [000822] -c--------- * CNS_INT int 35 REG NA $ea Contained DefList: { } N1805 ( 6, 4) [000823] -c-----N--- * EQ int REG NA Contained DefList: { } N1807 ( 1, 1) [000919] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N1809 ( 1, 2) [000920] ----------- * CNS_INT int 46 REG NA $eb Interval 267: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N1809.t920. CNS_INT } N1811 ( 6, 4) [000921] -c-----N--- * EQ int REG NA Contained DefList: { N1809.t920. CNS_INT } N1813 ( 13, 9) [003738] Jc-----N--- * AND void REG NA Contained DefList: { N1809.t920. CNS_INT } N1815 ( 15, 11) [000824] ----------- * JTRUE void REG NA $VN.Void LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> BB114 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB114, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB115 Setting BB114 as the predecessor for determining incoming variable registers of BB115 DefList: { } N1819 (???,???) [003949] ----------- * IL_OFFSET void INLRT @ 0x40C[E-] REG NA DefList: { } N1821 (???,???) [003950] ----------- * IL_OFFSET void INLRT @ 0x412[E-] REG NA DefList: { } N1823 ( 1, 1) [000923] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N1825 ( 1, 2) [000924] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { } N1827 ( 3, 4) [000925] J------N--- * EQ void REG NA LCL_VAR BB115 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N1829 ( 5, 6) [000926] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB115, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB117 Setting BB115 as the predecessor for determining incoming variable registers of BB117 CHECKING LAST USES for BB117, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {} def: {} NEW BLOCK BB135 Setting BB114 as the predecessor for determining incoming variable registers of BB135 DefList: { } N1835 (???,???) [003977] ----------- * IL_OFFSET void INLRT @ 0x46D[E-] REG NA DefList: { } N1837 ( 1, 1) [000825] ----------- * LCL_VAR int V14 loc10 u:6 NA REG NA $b14 DefList: { } N1839 ( 1, 2) [000826] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1841 ( 3, 4) [000827] J------N--- * GT void REG NA $c6e LCL_VAR BB135 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N1843 ( 5, 6) [000828] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB135, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V14} def: {} NEW BLOCK BB118 Setting BB135 as the predecessor for determining incoming variable registers of BB118 DefList: { } N1847 (???,???) [003951] ----------- * IL_OFFSET void INLRT @ 0x41A[E-] REG NA DefList: { } N1849 ( 1, 1) [000830] ----------- * LCL_VAR long V36 loc32 u:7 NA REG NA $904 DefList: { } N1851 ( 4, 3) [000831] ---XG------ * IND ubyte REG NA LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> Interval 268: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1851.t831. IND } N1853 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 NA REG NA BB118 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N1855 ( 1, 1) [003679] ----------- * LCL_VAR int V177 cse6 u:1 NA REG NA DefList: { } N1857 ( 1, 2) [000832] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1859 ( 7, 7) [000833] CNE---XG--N--- * JCMP void REG NA LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB118, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V177 V179} ============================== use: {V00 V36} def: {V60 V177} NEW BLOCK BB119 Setting BB118 as the predecessor for determining incoming variable registers of BB119 DefList: { } N1863 ( 1, 2) [000912] ----------- * CNS_INT int 48 REG NA $d8 Interval 269: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB119 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1863.t912. CNS_INT } N1865 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 NA REG NA BB119 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB119 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB119, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V63 V143 V144 V179} ============================== use: {V00} def: {V62 V63} NEW BLOCK BB120 Setting BB118 as the predecessor for determining incoming variable registers of BB120 DefList: { } N1869 ( 1, 1) [000840] ----------- * LCL_VAR long V36 loc32 u:7 NA (last use) REG NA $904 DefList: { } N1871 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 NA REG NA LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> Assigning related to STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> DefList: { } N1873 ( 1, 1) [000841] ----------- * LCL_VAR long V61 tmp21 u:1 NA (last use) REG NA $904 DefList: { } N1875 ( 1, 2) [000843] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N1877 ( 3, 4) [000844] ----------- * ADD long REG NA $adc LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> Interval 270: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1877.t844. ADD } N1879 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 NA REG NA BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> DefList: { } N1881 ( 1, 1) [003681] ----------- * LCL_VAR int V177 cse6 u:1 NA (last use) REG NA DefList: { } N1883 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 NA REG NA LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Assigning related to STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB120, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V63 V143 V144 V179} ============================== use: {V00 V36 V177} def: {V36 V61 V62 V63} NEW BLOCK BB121 Setting BB119 as the predecessor for determining incoming variable registers of BB121 DefList: { } N1887 ( 1, 1) [000858] ----------- * LCL_VAR int V63 tmp23 u:1 NA (last use) REG NA $b16 DefList: { } N1889 ( 2, 3) [001796] ----------- * CAST int <- ushort <- int REG NA $c75 LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 271: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1889.t1796. CAST } N1891 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 NA REG NA BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N1893 (???,???) [003952] ----------- * IL_OFFSET void INL29 @ 0x000[E-] <- INLRT @ ??? REG NA DefList: { } N1895 ( 1, 1) [000857] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N1897 ( 3, 4) [002795] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1899 ( 4, 3) [001797] ---XG------ * IND int REG NA LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 272: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1899.t1797. IND } N1901 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 NA REG NA BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> DefList: { } N1903 (???,???) [003953] ----------- * IL_OFFSET void INL29 @ 0x007[E-] <- INLRT @ ??? REG NA DefList: { } N1905 ( 1, 1) [001800] ----------- * LCL_VAR int V91 tmp51 u:1 NA REG NA DefList: { } N1907 ( 1, 1) [001801] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N1909 ( 3, 4) [002799] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N1911 ( 4, 3) [001839] n---GO----- * IND int REG NA LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 273: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1911.t1839. IND } N1913 ( 6, 5) [001805] N---GO-N-U- * GE void REG NA LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N1915 ( 8, 7) [001806] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB121, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V91 V92 V143 V144 V179} ============================== use: {V00 V63} def: {V91 V92} NEW BLOCK BB122 Setting BB121 as the predecessor for determining incoming variable registers of BB122 DefList: { } N1919 (???,???) [003954] ----------- * IL_OFFSET void INL29 @ 0x015[E-] <- INLRT @ ??? REG NA DefList: { } N1921 ( 1, 1) [002803] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N1923 ( 1, 2) [002804] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N1925 ( 3, 4) [002805] -----O----- * ADD byref REG NA $25c LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 274: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1925.t2805. ADD } N1927 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 NA REG NA BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N1929 ( 1, 1) [001812] ----------- * LCL_VAR int V91 tmp51 u:1 NA REG NA DefList: { } N1931 ( 1, 1) [001817] ----------- * LCL_VAR byref V93 tmp53 u:1 NA REG NA $25c DefList: { } N1933 ( 3, 4) [002808] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N1935 ( 4, 3) [001818] n---GO----- * IND int REG NA LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 275: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1935.t1818. IND } N1937 ( 9, 11) [001819] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N1939 ( 1, 1) [001816] ----------- * LCL_VAR byref V93 tmp53 u:1 NA (last use) REG NA $25c DefList: { } N1941 ( 3, 2) [001823] n---GO----- * IND byref REG NA LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 276: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1941.t1823. IND } N1943 ( 1, 1) [001813] ----------- * LCL_VAR int V91 tmp51 u:1 NA REG NA DefList: { N1941.t1823. IND } N1945 ( 2, 3) [001820] -c-------U- * CAST long <- uint REG NA Contained DefList: { N1941.t1823. IND } N1947 ( 1, 2) [001821] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N1941.t1823. IND } N1949 ( 4, 6) [001822] -c--------- * BFIZ long REG NA Contained DefList: { N1941.t1823. IND } N1951 ( 8, 9) [001824] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N1941.t1823. IND } N1953 ( 1, 1) [001826] ----------- * LCL_VAR int V92 tmp52 u:1 NA (last use) REG NA $c75 DefList: { N1941.t1823. IND } N1955 (???,???) [003955] -A-XGO----- * STOREIND short REG NA BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N1957 (???,???) [003956] ----------- * IL_OFFSET void INL29 @ 0x023[E-] <- INLRT @ ??? REG NA DefList: { } N1959 ( 1, 1) [001830] ----------- * LCL_VAR int V91 tmp51 u:1 NA (last use) REG NA DefList: { } N1961 ( 1, 2) [001831] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1963 ( 3, 4) [001832] ----------- * ADD int REG NA LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> Interval 277: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1963.t1832. ADD } N1965 ( 1, 1) [001829] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N1963.t1832. ADD } N1967 ( 3, 4) [002811] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N1963.t1832. ADD } N1969 (???,???) [003957] -A--GO----- * STOREIND int REG NA LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB122, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V91 V92} def: {V93} NEW BLOCK BB123 Setting BB121 as the predecessor for determining incoming variable registers of BB123 DefList: { } N1973 (???,???) [003958] ----------- * IL_OFFSET void INL29 @ 0x02D[E-] <- INLRT @ ??? REG NA DefList: { } N1975 ( 1, 1) [001807] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N1977 (???,???) [004234] ----------- * PUTARG_REG byref REG x0 BB123 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB123 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 278: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB123 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x0] minReg=1 fixed wt=3200.00> Assigning related to DefList: { N1977.t4234. PUTARG_REG } N1979 ( 1, 1) [001808] ----------- * LCL_VAR int V92 tmp52 u:1 NA (last use) REG NA $c75 DefList: { N1977.t4234. PUTARG_REG } N1981 (???,???) [004235] ----------- * PUTARG_REG int REG x1 Last use of V92 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB123 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB123 regmask=[x1] minReg=1 last fixed wt=4800.00> Interval 279: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB123 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x1] minReg=1 fixed wt=3200.00> DefList: { N1977.t4234. PUTARG_REG; N1981.t4235. PUTARG_REG } N1983 ( 2, 8) [002812] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn REG NA $53 Interval 280: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB123 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N1977.t4234. PUTARG_REG; N1981.t4235. PUTARG_REG; N1983.t2812. CNS_INT } N1985 (???,???) [004236] ----------- * PUTARG_REG long REG x11 BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 last fixed wt=800.00> Interval 281: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB123 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x11] minReg=1 fixed wt=3200.00> DefList: { N1977.t4234. PUTARG_REG; N1981.t4235. PUTARG_REG; N1985.t4236. PUTARG_REG } N1987 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 282: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB123 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB123 regmask=[x0] minReg=1 wt=800.00> BB123 regmask=[x0] minReg=1 last fixed wt=800.00> BB123 regmask=[x1] minReg=1 wt=800.00> BB123 regmask=[x1] minReg=1 last fixed wt=800.00> BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB123 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB123 regmask=[x0] minReg=1 wt=800.00> BB123 regmask=[x1] minReg=1 wt=800.00> BB123 regmask=[x2] minReg=1 wt=800.00> BB123 regmask=[x3] minReg=1 wt=800.00> BB123 regmask=[x4] minReg=1 wt=800.00> BB123 regmask=[x5] minReg=1 wt=800.00> BB123 regmask=[x6] minReg=1 wt=800.00> BB123 regmask=[x7] minReg=1 wt=800.00> BB123 regmask=[x8] minReg=1 wt=800.00> BB123 regmask=[x9] minReg=1 wt=800.00> BB123 regmask=[x10] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x12] minReg=1 wt=800.00> BB123 regmask=[x13] minReg=1 wt=800.00> BB123 regmask=[x14] minReg=1 wt=800.00> BB123 regmask=[x15] minReg=1 wt=800.00> BB123 regmask=[xip0] minReg=1 wt=800.00> BB123 regmask=[xip1] minReg=1 wt=800.00> BB123 regmask=[lr] minReg=1 wt=800.00> CHECKING LAST USES for BB123, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V92} def: {} NEW BLOCK BB124 Setting BB122 as the predecessor for determining incoming variable registers of BB124 DefList: { } N1991 (???,???) [003959] ----------- * IL_OFFSET void INLRT @ 0x431[E-] REG NA DefList: { } N1993 ( 1, 1) [000860] ----------- * LCL_VAR int V12 loc8 u:3 NA REG NA $4c4 DefList: { } N1995 ( 1, 2) [000861] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1997 ( 6, 4) [000862] -c-----N--- * EQ int REG NA $70a Contained DefList: { } N1999 ( 1, 1) [000874] ----------- * LCL_VAR int V08 loc4 u:5 NA REG NA $b15 DefList: { } N2001 ( 1, 2) [000875] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2003 ( 6, 4) [000876] -c-----N--- * LE int REG NA $d03 Contained DefList: { } N2005 ( 13, 9) [003740] Jc-----N--- * AND void REG NA Contained DefList: { } N2007 ( 15, 11) [000863] ----------- * JTRUE void REG NA $VN.Void LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2900.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> CHECKING LAST USES for BB124, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V08 V12} def: {} NEW BLOCK BB125 Setting BB124 as the predecessor for determining incoming variable registers of BB125 DefList: { } N2011 (???,???) [003960] ----------- * IL_OFFSET void INLRT @ 0x435[E-] REG NA DefList: { } N2013 (???,???) [003961] ----------- * IL_OFFSET void INLRT @ 0x43A[E-] REG NA DefList: { } N2015 ( 1, 1) [000885] ----------- * LCL_VAR int V20 loc16 u:7 NA REG NA $b13 DefList: { } N2017 ( 1, 1) [000889] ----------- * LCL_VAR int V144 tmp104 u:2 NA REG NA $2a6 DefList: { } N2019 ( 6, 9) [000890] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $c31 LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> DefList: { } N2021 ( 1, 1) [000894] ----------- * LCL_VAR byref V143 tmp103 u:2 NA REG NA $385 DefList: { } N2023 ( 1, 1) [000886] ----------- * LCL_VAR int V20 loc16 u:7 NA REG NA $b13 DefList: { } N2025 ( 2, 3) [000891] -c-------U- * CAST long <- uint REG NA $ae2 Contained DefList: { } N2027 ( 1, 2) [000892] -c--------- * CNS_INT long 2 REG NA $20a Contained DefList: { } N2029 ( 4, 6) [000893] -c--------- * BFIZ long REG NA Contained DefList: { } N2031 ( 6, 8) [000895] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { } N2033 ( 8, 9) [002813] ---XGO----- * IND int REG NA LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> Interval 283: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2033.t2813. IND } N2035 ( 1, 2) [000898] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { N2033.t2813. IND } N2037 ( 16, 21) [000899] ---XGO----- * ADD int REG NA BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Interval 284: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2037.t899. ADD } N2039 ( 1, 1) [000882] ----------- * LCL_VAR int V08 loc4 u:5 NA REG NA $b15 DefList: { N2037.t899. ADD } N2041 ( 21, 23) [000900] Nc-XGO-N-U- * NE int REG NA Contained DefList: { N2037.t899. ADD } N2043 ( 1, 1) [000878] ----------- * LCL_VAR int V20 loc16 u:7 NA REG NA $b13 DefList: { N2037.t899. ADD } N2045 ( 1, 2) [000879] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N2037.t899. ADD } N2047 ( 6, 4) [000880] -c-----N--- * LT int REG NA $d04 Contained DefList: { N2037.t899. ADD } N2049 ( 28, 28) [003742] Jc-XGO-N--- * AND void REG NA Contained DefList: { N2037.t899. ADD } N2051 ( 30, 30) [000881] ---XGO----- * JTRUE void REG NA $VN.Void BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> CHECKING LAST USES for BB125, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V08 V20 V143 V144} def: {} NEW BLOCK BB127 Setting BB125 as the predecessor for determining incoming variable registers of BB127 DefList: { } N2055 (???,???) [003962] ----------- * IL_OFFSET void INLRT @ 0x43F[E-] REG NA DefList: { } N2057 (???,???) [003963] ----------- * IL_OFFSET void INLRT @ 0x44F[E-] REG NA DefList: { } N2059 ( 1, 1) [000903] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { } N2061 ( 3, 4) [002815] -c--------- * LEA(b+56) byref REG NA Contained DefList: { } N2063 ( 4, 3) [001843] ---XG------ * IND ref REG NA LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 285: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2063.t1843. IND } N2065 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 NA REG NA BB127 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 last wt=8000.00> DefList: { } N2067 (???,???) [003964] ----------- * IL_OFFSET void INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] REG NA DefList: { } N2069 ( 1, 1) [001845] ----------- * LCL_VAR ref V95 tmp55 u:1 NA REG NA DefList: { } N2071 ( 1, 2) [001846] -c--------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N2073 ( 3, 4) [001847] CEQ-------N--- * JCMP void REG NA LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 last wt=8000.00> CHECKING LAST USES for BB127, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144 V179} ============================== use: {V03} def: {V95} NEW BLOCK BB129 Setting BB127 as the predecessor for determining incoming variable registers of BB129 DefList: { } N2077 (???,???) [003965] ----------- * IL_OFFSET void INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] REG NA DefList: { } N2079 ( 1, 1) [000902] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2081 ( 3, 4) [002817] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2083 ( 4, 3) [001849] n---GO----- * IND int REG NA LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 286: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2083.t1849. IND } N2085 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 NA REG NA BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> DefList: { } N2087 (???,???) [003966] ----------- * IL_OFFSET void INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] REG NA DefList: { } N2089 ( 1, 1) [001852] ----------- * LCL_VAR ref V95 tmp55 u:1 NA REG NA DefList: { } N2091 (???,???) [004168] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2093 ( 3, 3) [001853] ---X------- * IND int REG NA LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=8000.00> Interval 287: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2093.t1853. IND } N2095 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 NA REG NA BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N2097 ( 1, 1) [003717] ----------- * LCL_VAR int V181 cse10 u:1 NA REG NA DefList: { } N2099 ( 1, 2) [001854] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2101 ( 9, 7) [001855] Nc-X---N-U- * NE int REG NA Contained DefList: { } N2103 ( 1, 1) [001860] ----------- * LCL_VAR int V96 tmp56 u:1 NA REG NA DefList: { } N2105 ( 1, 1) [001861] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2107 ( 3, 4) [002821] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N2109 ( 4, 3) [001899] n---GO----- * IND int REG NA LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 288: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2109.t1899. IND } N2111 ( 9, 5) [001865] Nc--GO-N-U- * GE int REG NA Contained DefList: { N2109.t1899. IND } N2113 ( 19, 13) [003744] Jc-XGO-N--- * AND void REG NA Contained DefList: { N2109.t1899. IND } N2115 ( 21, 15) [001856] ---XGO----- * JTRUE void REG NA LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB129, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144 V179 V181} ============================== use: {V00 V95} def: {V96 V181} NEW BLOCK BB130 Setting BB129 as the predecessor for determining incoming variable registers of BB130 DefList: { } N2119 (???,???) [003967] ----------- * IL_OFFSET void INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] REG NA DefList: { } N2121 (???,???) [003968] ----------- * IL_OFFSET void INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] REG NA DefList: { } N2123 ( 1, 1) [002825] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2125 ( 1, 2) [002826] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N2127 ( 3, 4) [002827] -----O----- * ADD byref REG NA $25c LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 289: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2127.t2827. ADD } N2129 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 NA REG NA BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N2131 (???,???) [003969] ----------- * IL_OFFSET void INL32 @ ??? <- INLRT @ 0x44F[E-] REG NA DefList: { } N2133 ( 1, 1) [001869] ----------- * LCL_VAR int V96 tmp56 u:1 NA REG NA DefList: { } N2135 ( 1, 1) [001874] ----------- * LCL_VAR byref V97 tmp57 u:1 NA REG NA $25c DefList: { } N2137 ( 3, 4) [002830] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2139 ( 4, 3) [001875] n---GO----- * IND int REG NA LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 290: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2139.t1875. IND } N2141 ( 9, 11) [001876] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N2143 ( 1, 1) [001873] ----------- * LCL_VAR byref V97 tmp57 u:1 NA (last use) REG NA $25c DefList: { } N2145 ( 3, 2) [001880] n---GO----- * IND byref REG NA LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 291: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2145.t1880. IND } N2147 ( 1, 1) [001870] ----------- * LCL_VAR int V96 tmp56 u:1 NA REG NA DefList: { N2145.t1880. IND } N2149 ( 2, 3) [001877] -c-------U- * CAST long <- uint REG NA Contained DefList: { N2145.t1880. IND } N2151 ( 1, 2) [001878] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N2145.t1880. IND } N2153 ( 4, 6) [001879] ----------- * BFIZ long REG NA LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> Interval 292: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BFIZ BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2145.t1880. IND; N2153.t1879. BFIZ } N2155 ( 8, 9) [001881] ----GO-N--- * ADD byref REG NA BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Interval 293: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2155.t1881. ADD } N2157 ( 1, 2) [001884] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N2155.t1881. ADD } N2159 ( 1, 1) [003719] ----------- * LCL_VAR int V181 cse10 u:1 NA (last use) REG NA DefList: { N2155.t1881. ADD } N2161 ( 6, 10) [002835] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { N2155.t1881. ADD } N2163 ( 1, 1) [002832] ----------- * LCL_VAR ref V95 tmp55 u:1 NA (last use) REG NA DefList: { N2155.t1881. ADD } N2165 ( 1, 1) [002839] -c--------- * LEA(b+12) byref REG NA Contained DefList: { N2155.t1881. ADD } N2167 ( 5, 4) [002844] n---GO----- * IND ushort REG NA LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=8000.00> Interval 294: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2155.t1881. ADD; N2167.t2844. IND } N2169 (???,???) [003970] -A-XGO----- * STOREIND short REG NA BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N2171 (???,???) [003971] ----------- * IL_OFFSET void INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] REG NA DefList: { } N2173 ( 1, 1) [001890] ----------- * LCL_VAR int V96 tmp56 u:1 NA (last use) REG NA DefList: { } N2175 ( 1, 2) [001891] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2177 ( 3, 4) [001892] ----------- * ADD int REG NA LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> Interval 295: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2177.t1892. ADD } N2179 ( 1, 1) [001889] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N2177.t1892. ADD } N2181 ( 3, 4) [002846] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N2177.t1892. ADD } N2183 (???,???) [003972] -A--GO----- * STOREIND int REG NA LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB130, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V95 V96 V181} def: {V97} NEW BLOCK BB132 Setting BB129 as the predecessor for determining incoming variable registers of BB132 DefList: { } N2187 (???,???) [003973] ----------- * IL_OFFSET void INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] REG NA DefList: { } N2189 ( 1, 1) [001857] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2191 (???,???) [004237] ----------- * PUTARG_REG byref REG x0 BB132 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB132 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 296: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB132 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x0] minReg=1 fixed wt=3200.00> Assigning related to DefList: { N2191.t4237. PUTARG_REG } N2193 ( 1, 1) [001858] ----------- * LCL_VAR ref V95 tmp55 u:1 NA (last use) REG NA DefList: { N2191.t4237. PUTARG_REG } N2195 (???,???) [004238] ----------- * PUTARG_REG ref REG x1 Last use of V95 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB132 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB132 regmask=[x1] minReg=1 last fixed wt=8000.00> Interval 297: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB132 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x1] minReg=1 fixed wt=3200.00> DefList: { N2191.t4237. PUTARG_REG; N2195.t4238. PUTARG_REG } N2197 ( 2, 8) [002847] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn REG NA $4f Interval 298: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB132 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2191.t4237. PUTARG_REG; N2195.t4238. PUTARG_REG; N2197.t2847. CNS_INT } N2199 (???,???) [004239] ----------- * PUTARG_REG long REG x11 BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 last fixed wt=800.00> Interval 299: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB132 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x11] minReg=1 fixed wt=3200.00> DefList: { N2191.t4237. PUTARG_REG; N2195.t4238. PUTARG_REG; N2199.t4239. PUTARG_REG } N2201 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void Interval 300: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB132 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB132 regmask=[x0] minReg=1 wt=800.00> BB132 regmask=[x0] minReg=1 last fixed wt=800.00> BB132 regmask=[x1] minReg=1 wt=800.00> BB132 regmask=[x1] minReg=1 last fixed wt=800.00> BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB132 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB132 regmask=[x0] minReg=1 wt=800.00> BB132 regmask=[x1] minReg=1 wt=800.00> BB132 regmask=[x2] minReg=1 wt=800.00> BB132 regmask=[x3] minReg=1 wt=800.00> BB132 regmask=[x4] minReg=1 wt=800.00> BB132 regmask=[x5] minReg=1 wt=800.00> BB132 regmask=[x6] minReg=1 wt=800.00> BB132 regmask=[x7] minReg=1 wt=800.00> BB132 regmask=[x8] minReg=1 wt=800.00> BB132 regmask=[x9] minReg=1 wt=800.00> BB132 regmask=[x10] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x12] minReg=1 wt=800.00> BB132 regmask=[x13] minReg=1 wt=800.00> BB132 regmask=[x14] minReg=1 wt=800.00> BB132 regmask=[x15] minReg=1 wt=800.00> BB132 regmask=[xip0] minReg=1 wt=800.00> BB132 regmask=[xip1] minReg=1 wt=800.00> BB132 regmask=[lr] minReg=1 wt=800.00> CHECKING LAST USES for BB132, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V95} def: {} NEW BLOCK BB133 Setting BB127 as the predecessor for determining incoming variable registers of BB133 DefList: { } N2205 (???,???) [003974] ----------- * IL_OFFSET void INLRT @ 0x45B[E-] REG NA DefList: { } N2207 ( 1, 1) [000907] ----------- * LCL_VAR int V20 loc16 u:7 NA (last use) REG NA $b13 DefList: { } N2209 ( 1, 2) [000908] -c--------- * CNS_INT int -1 REG NA $c4 Contained DefList: { } N2211 ( 3, 4) [000909] ----------- * ADD int REG NA $d27 LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> Interval 301: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB133 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2211.t909. ADD } N2213 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 NA REG NA BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> CHECKING LAST USES for BB133, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V20} def: {V20} NEW BLOCK BB134 Setting BB124 as the predecessor for determining incoming variable registers of BB134 DefList: { } N2217 (???,???) [003975] ----------- * IL_OFFSET void INLRT @ 0x461[E-] REG NA DefList: { } N2219 ( 1, 1) [000864] ----------- * LCL_VAR int V08 loc4 u:5 NA (last use) REG NA $b15 DefList: { } N2221 ( 1, 2) [000865] -c--------- * CNS_INT int -1 REG NA $c4 Contained DefList: { } N2223 ( 3, 4) [000866] ----------- * ADD int REG NA $d29 LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> Interval 302: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2223.t866. ADD } N2225 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 NA REG NA BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> DefList: { } N2227 (???,???) [003976] ----------- * IL_OFFSET void INLRT @ 0x467[E-] REG NA DefList: { } N2229 ( 1, 1) [000869] ----------- * LCL_VAR int V14 loc10 u:6 NA (last use) REG NA $b14 DefList: { } N2231 ( 1, 2) [000870] -c--------- * CNS_INT int -1 REG NA $c4 Contained DefList: { } N2233 ( 3, 4) [000871] ----------- * ADD int REG NA $d2a LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> Interval 303: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2233.t871. ADD } N2235 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 NA REG NA BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> CHECKING LAST USES for BB134, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V08 V14} def: {V08 V14} NEW BLOCK BB136 Setting BB135 as the predecessor for determining incoming variable registers of BB136 DefList: { } N2239 (???,???) [003978] ----------- * IL_OFFSET void INLRT @ 0x472[E-] REG NA DefList: { } N2241 ( 1, 1) [000275] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N2243 ( 1, 2) [000276] -c--------- * CNS_INT int 69 REG NA $d2 Contained DefList: { } N2245 ( 3, 4) [000277] N------N-U- * GT void REG NA LCL_VAR BB136 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N2247 ( 5, 6) [000278] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB136, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB137 Setting BB136 as the predecessor for determining incoming variable registers of BB137 DefList: { } N2251 (???,???) [003979] ----------- * IL_OFFSET void INLRT @ 0x478[E-] REG NA DefList: { } N2253 ( 1, 1) [000593] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N2255 ( 1, 2) [000594] -c--------- * CNS_INT int -34 REG NA $d6 Contained DefList: { } N2257 ( 3, 4) [000595] ----------- * ADD int REG NA LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> Interval 304: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2257.t595. ADD } N2259 (???,???) [004241] DA--------- * STORE_LCL_VAR int V184 rat2 NA REG NA BB137 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2261 ( 3, 2) [004243] ----------- * LCL_VAR int V184 rat2 NA REG NA DefList: { } N2263 ( 1, 2) [004244] -c--------- * CNS_INT int 5 REG NA Contained DefList: { } N2265 ( 8, 5) [004245] ---------U- * GT void REG NA LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2267 ( 10, 7) [004246] ----------- * JTRUE void REG NA CHECKING LAST USES for BB137, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V184} ============================== use: {V18} def: {V184} NEW BLOCK BB138 Setting BB137 as the predecessor for determining incoming variable registers of BB138 DefList: { } N2271 (???,???) [003980] ----------- * IL_OFFSET void INLRT @ 0x49A[E-] REG NA DefList: { } N2273 ( 1, 1) [000597] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N2275 ( 1, 2) [000598] -c--------- * CNS_INT int -44 REG NA $d7 Contained DefList: { } N2277 ( 3, 4) [000599] ----------- * ADD int REG NA LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> Interval 305: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2277.t599. ADD } N2279 (???,???) [004252] DA--------- * STORE_LCL_VAR int V185 rat3 NA REG NA BB138 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2281 ( 3, 2) [004254] ----------- * LCL_VAR int V185 rat3 NA REG NA DefList: { } N2283 ( 1, 2) [004255] -c--------- * CNS_INT int 4 REG NA Contained DefList: { } N2285 ( 8, 5) [004256] ---------U- * GT void REG NA LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2287 ( 10, 7) [004257] ----------- * JTRUE void REG NA CHECKING LAST USES for BB138, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V185} ============================== use: {V18} def: {V185} NEW BLOCK BB139 Setting BB138 as the predecessor for determining incoming variable registers of BB139 DefList: { } N2291 (???,???) [003981] ----------- * IL_OFFSET void INLRT @ 0x4B8[E-] REG NA DefList: { } N2293 ( 1, 1) [000601] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N2295 ( 1, 2) [000602] -c--------- * CNS_INT int 69 REG NA $d2 Contained DefList: { } N2297 ( 3, 4) [000603] J------N--- * EQ void REG NA LCL_VAR BB139 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N2299 ( 5, 6) [000604] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB139, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB140 Setting BB139 as the predecessor for determining incoming variable registers of BB140 CHECKING LAST USES for BB140, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {} def: {} NEW BLOCK BB141 Setting BB136 as the predecessor for determining incoming variable registers of BB141 DefList: { } N2305 (???,???) [003982] ----------- * IL_OFFSET void INLRT @ 0x4C6[E-] REG NA DefList: { } N2307 ( 1, 1) [000279] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N2309 ( 1, 2) [000280] -c--------- * CNS_INT int 92 REG NA $d3 Contained DefList: { } N2311 ( 3, 4) [000281] J------N--- * EQ void REG NA LCL_VAR BB141 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N2313 ( 5, 6) [000282] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB141, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB142 Setting BB141 as the predecessor for determining incoming variable registers of BB142 DefList: { } N2317 (???,???) [003983] ----------- * IL_OFFSET void INLRT @ 0x4CF[E-] REG NA DefList: { } N2319 ( 1, 1) [000319] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N2321 ( 1, 2) [000320] -c--------- * CNS_INT int 101 REG NA $d4 Contained DefList: { } N2323 ( 3, 4) [000321] J------N--- * EQ void REG NA LCL_VAR BB142 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N2325 ( 5, 6) [000322] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB142, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB143 Setting BB142 as the predecessor for determining incoming variable registers of BB143 DefList: { } N2329 (???,???) [003984] ----------- * IL_OFFSET void INLRT @ 0x4D8[E-] REG NA DefList: { } N2331 ( 1, 1) [000581] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N2333 ( 1, 4) [000582] ----------- * CNS_INT int 0x2030 REG NA $d5 Interval 306: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB143 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2333.t582. CNS_INT } N2335 ( 3, 6) [000583] J------N--- * NE void REG NA LCL_VAR BB143 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> BB143 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N2337 ( 5, 8) [000584] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB143, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB144 Setting BB143 as the predecessor for determining incoming variable registers of BB144 DefList: { } N2341 (???,???) [003985] ----------- * IL_OFFSET void INLRT @ 0x598[E-] REG NA DefList: { } N2343 ( 1, 1) [000586] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { } N2345 ( 3, 4) [002849] -c--------- * LEA(b+136) byref REG NA Contained DefList: { } N2347 ( 4, 3) [002066] ---XG------ * IND ref REG NA LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 307: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2347.t2066. IND } N2349 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 NA REG NA BB144 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB144, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} ============================== use: {V03} def: {V110} NEW BLOCK BB181 Setting BB144 as the predecessor for determining incoming variable registers of BB181 DefList: { } N2353 (???,???) [004039] ----------- * IL_OFFSET void INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] REG NA DefList: { } N2355 ( 1, 1) [002068] ----------- * LCL_VAR ref V110 tmp70 u:1 NA REG NA DefList: { } N2357 ( 1, 2) [002069] -c--------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N2359 ( 3, 4) [002070] CEQ-------N--- * JCMP void REG NA LCL_VAR BB181 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB181, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} ============================== use: {V110} def: {} NEW BLOCK BB182 Setting BB112 as the predecessor for determining incoming variable registers of BB182 Creating dummy definitions BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Finished creating dummy definitions DefList: { } N2363 (???,???) [004040] ----------- * IL_OFFSET void INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] REG NA DefList: { } N2365 ( 1, 1) [000585] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2367 ( 3, 4) [002942] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2369 ( 4, 3) [002072] ---XG------ * IND int REG NA LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 308: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2369.t2072. IND } N2371 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 NA REG NA BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N2373 (???,???) [004041] ----------- * IL_OFFSET void INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] REG NA DefList: { } N2375 ( 1, 1) [002075] ----------- * LCL_VAR ref V110 tmp70 u:1 NA REG NA DefList: { } N2377 (???,???) [004178] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2379 ( 3, 3) [002076] ---X------- * IND int REG NA LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 309: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2379.t2076. IND } N2381 ( 1, 2) [002077] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { N2379.t2076. IND } N2383 ( 8, 6) [002078] Nc-X---N-U- * NE int REG NA Contained DefList: { N2379.t2076. IND } N2385 ( 1, 1) [002083] ----------- * LCL_VAR int V111 tmp71 u:1 NA REG NA DefList: { N2379.t2076. IND } N2387 ( 1, 1) [002084] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N2379.t2076. IND } N2389 ( 3, 4) [002946] -c--------- * LEA(b+24) byref REG NA Contained DefList: { N2379.t2076. IND } N2391 ( 4, 3) [002122] n---GO----- * IND int REG NA LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 310: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2379.t2076. IND; N2391.t2122. IND } N2393 ( 9, 5) [002088] Nc--GO-N-U- * GE int REG NA Contained DefList: { N2379.t2076. IND; N2391.t2122. IND } N2395 ( 18, 12) [003756] Jc-XGO-N--- * AND void REG NA Contained DefList: { N2379.t2076. IND; N2391.t2122. IND } N2397 ( 20, 14) [002079] ---XGO----- * JTRUE void REG NA BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB182, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144 V179} ============================== use: {V00 V110} def: {V111} NEW BLOCK BB183 Setting BB182 as the predecessor for determining incoming variable registers of BB183 DefList: { } N2401 (???,???) [004042] ----------- * IL_OFFSET void INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] REG NA DefList: { } N2403 (???,???) [004043] ----------- * IL_OFFSET void INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] REG NA DefList: { } N2405 ( 1, 1) [002950] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2407 ( 1, 2) [002951] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N2409 ( 3, 4) [002952] -----O----- * ADD byref REG NA $25c LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 311: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2409.t2952. ADD } N2411 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 NA REG NA BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2413 (???,???) [004044] ----------- * IL_OFFSET void INL43 @ ??? <- INLRT @ 0x598[E-] REG NA DefList: { } N2415 ( 1, 1) [002092] ----------- * LCL_VAR int V111 tmp71 u:1 NA REG NA DefList: { } N2417 ( 1, 1) [002097] ----------- * LCL_VAR byref V112 tmp72 u:1 NA REG NA $25c DefList: { } N2419 ( 3, 4) [002955] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2421 ( 4, 3) [002098] n---GO----- * IND int REG NA LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 312: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2421.t2098. IND } N2423 ( 9, 11) [002099] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N2425 ( 1, 1) [002096] ----------- * LCL_VAR byref V112 tmp72 u:1 NA (last use) REG NA $25c DefList: { } N2427 ( 3, 2) [002103] n---GO----- * IND byref REG NA LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 313: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2427.t2103. IND } N2429 ( 1, 1) [002093] ----------- * LCL_VAR int V111 tmp71 u:1 NA REG NA DefList: { N2427.t2103. IND } N2431 ( 2, 3) [002100] -c-------U- * CAST long <- uint REG NA Contained DefList: { N2427.t2103. IND } N2433 ( 1, 2) [002101] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N2427.t2103. IND } N2435 ( 4, 6) [002102] ----------- * BFIZ long REG NA LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 314: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BFIZ BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2427.t2103. IND; N2435.t2102. BFIZ } N2437 ( 8, 9) [002104] ----GO-N--- * ADD byref REG NA BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 315: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2437.t2104. ADD } N2439 ( 1, 2) [002107] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N2437.t2104. ADD } N2441 ( 1, 1) [002106] ----------- * LCL_VAR ref V110 tmp70 u:1 NA REG NA DefList: { N2437.t2104. ADD } N2443 (???,???) [004180] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N2437.t2104. ADD } N2445 ( 3, 3) [002959] ---X------- * IND int REG NA LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 316: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2437.t2104. ADD; N2445.t2959. IND } N2447 ( 8, 12) [002960] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { N2437.t2104. ADD } N2449 ( 1, 1) [002957] ----------- * LCL_VAR ref V110 tmp70 u:1 NA (last use) REG NA DefList: { N2437.t2104. ADD } N2451 ( 1, 1) [002964] -c--------- * LEA(b+12) byref REG NA Contained DefList: { N2437.t2104. ADD } N2453 ( 5, 4) [002969] n---GO----- * IND ushort REG NA LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 317: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2437.t2104. ADD; N2453.t2969. IND } N2455 (???,???) [004045] -A-XGO----- * STOREIND short REG NA BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N2457 (???,???) [004046] ----------- * IL_OFFSET void INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] REG NA DefList: { } N2459 ( 1, 1) [002113] ----------- * LCL_VAR int V111 tmp71 u:1 NA (last use) REG NA DefList: { } N2461 ( 1, 2) [002114] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2463 ( 3, 4) [002115] ----------- * ADD int REG NA LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 318: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2463.t2115. ADD } N2465 ( 1, 1) [002112] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N2463.t2115. ADD } N2467 ( 3, 4) [002971] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N2463.t2115. ADD } N2469 (???,???) [004047] -A--GO----- * STOREIND int REG NA LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB183, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V110 V111} def: {V112} NEW BLOCK BB185 Setting BB182 as the predecessor for determining incoming variable registers of BB185 DefList: { } N2473 (???,???) [004048] ----------- * IL_OFFSET void INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] REG NA DefList: { } N2475 ( 1, 1) [002080] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2477 (???,???) [004271] ----------- * PUTARG_REG byref REG x0 BB185 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB185 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 319: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB185 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N2477.t4271. PUTARG_REG } N2479 ( 1, 1) [002081] ----------- * LCL_VAR ref V110 tmp70 u:1 NA (last use) REG NA DefList: { N2477.t4271. PUTARG_REG } N2481 (???,???) [004272] ----------- * PUTARG_REG ref REG x1 Last use of V110 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB185 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB185 regmask=[x1] minReg=1 last fixed wt=2400.00> Interval 320: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB185 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N2477.t4271. PUTARG_REG; N2481.t4272. PUTARG_REG } N2483 ( 2, 8) [002972] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn REG NA $4f Interval 321: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB185 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2477.t4271. PUTARG_REG; N2481.t4272. PUTARG_REG; N2483.t2972. CNS_INT } N2485 (???,???) [004273] ----------- * PUTARG_REG long REG x11 BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 322: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB185 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N2477.t4271. PUTARG_REG; N2481.t4272. PUTARG_REG; N2485.t4273. PUTARG_REG } N2487 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void Interval 323: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB185 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB185 regmask=[x0] minReg=1 wt=200.00> BB185 regmask=[x0] minReg=1 last fixed wt=200.00> BB185 regmask=[x1] minReg=1 wt=200.00> BB185 regmask=[x1] minReg=1 last fixed wt=200.00> BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB185 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB185 regmask=[x0] minReg=1 wt=200.00> BB185 regmask=[x1] minReg=1 wt=200.00> BB185 regmask=[x2] minReg=1 wt=200.00> BB185 regmask=[x3] minReg=1 wt=200.00> BB185 regmask=[x4] minReg=1 wt=200.00> BB185 regmask=[x5] minReg=1 wt=200.00> BB185 regmask=[x6] minReg=1 wt=200.00> BB185 regmask=[x7] minReg=1 wt=200.00> BB185 regmask=[x8] minReg=1 wt=200.00> BB185 regmask=[x9] minReg=1 wt=200.00> BB185 regmask=[x10] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x12] minReg=1 wt=200.00> BB185 regmask=[x13] minReg=1 wt=200.00> BB185 regmask=[x14] minReg=1 wt=200.00> BB185 regmask=[x15] minReg=1 wt=200.00> BB185 regmask=[xip0] minReg=1 wt=200.00> BB185 regmask=[xip1] minReg=1 wt=200.00> BB185 regmask=[lr] minReg=1 wt=200.00> CHECKING LAST USES for BB185, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V110} def: {} NEW BLOCK BB200 Setting BB141 as the predecessor for determining incoming variable registers of BB200 DefList: { } N2491 (???,???) [004075] ----------- * IL_OFFSET void INLRT @ 0x618[E-] REG NA DefList: { } N2493 ( 1, 1) [000283] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N2495 ( 1, 1) [003701] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N2497 ( 6, 3) [000288] -c-----N--- * GE int REG NA $94d Contained DefList: { } N2499 ( 1, 1) [000290] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N2501 ( 1, 1) [000291] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N2503 ( 2, 3) [000292] -c--------- * CAST long <- int REG NA $3e5 Contained DefList: { } N2505 ( 1, 2) [000294] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N2507 ( 4, 6) [000295] -c--------- * BFIZ long REG NA Contained DefList: { } N2509 ( 6, 8) [000296] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N2511 ( 9, 10) [000297] ---XG------ * IND ushort REG NA LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 324: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2511.t297. IND } N2513 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 NA REG NA BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> DefList: { } N2515 ( 1, 1) [003665] ----------- * LCL_VAR int V176 cse5 NA REG NA DefList: { } N2517 ( 1, 2) [000298] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N2519 ( 15, 14) [000299] -c-XG--N--- * EQ int REG NA Contained DefList: { } N2521 ( 22, 18) [003760] Jc-XG--N--- * AND void REG NA Contained DefList: { } N2523 ( 24, 20) [000289] ---XG------ * JTRUE void REG NA $VN.Void LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> CHECKING LAST USES for BB200, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V176 V179} ============================== use: {V16 V34 V179} def: {V176} NEW BLOCK BB201 Setting BB112 as the predecessor for determining incoming variable registers of BB201 Creating dummy definitions BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Finished creating dummy definitions DefList: { } N2527 (???,???) [004076] ----------- * IL_OFFSET void INLRT @ 0x626[E-] REG NA DefList: { } N2529 (???,???) [004077] ----------- * IL_OFFSET void INLRT @ 0x634[E-] REG NA DefList: { } N2531 ( 1, 1) [000303] ----------- * LCL_VAR int V16 loc12 u:5 NA (last use) REG NA $898 DefList: { } N2533 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 NA REG NA LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N2535 (???,???) [004078] ----------- * IL_OFFSET void INLRT @ 0x634[E-] REG NA DefList: { } N2537 ( 1, 1) [000304] ----------- * LCL_VAR int V51 tmp11 u:1 NA (last use) REG NA $898 DefList: { } N2539 ( 1, 2) [000305] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2541 ( 3, 4) [000306] ----------- * ADD int REG NA $952 LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Interval 325: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2541.t306. ADD } N2543 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 NA REG NA BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N2545 ( 1, 1) [003667] ----------- * LCL_VAR int V176 cse5 NA (last use) REG NA DefList: { } N2547 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 NA REG NA LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Assigning related to STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2549 (???,???) [004079] ----------- * IL_OFFSET void INL53 @ 0x000[E-] <- INLRT @ ??? REG NA DefList: { } N2551 ( 1, 1) [000301] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2553 ( 3, 4) [003027] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2555 ( 4, 3) [002244] ---XG------ * IND int REG NA LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 326: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2555.t2244. IND } N2557 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 NA REG NA BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N2559 (???,???) [004080] ----------- * IL_OFFSET void INL53 @ 0x007[E-] <- INLRT @ ??? REG NA DefList: { } N2561 ( 1, 1) [002247] ----------- * LCL_VAR int V122 tmp82 u:1 NA REG NA DefList: { } N2563 ( 1, 1) [002248] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2565 ( 3, 4) [003031] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N2567 ( 4, 3) [002286] n---GO----- * IND int REG NA LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 327: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2567.t2286. IND } N2569 ( 6, 5) [002252] N---GO-N-U- * GE void REG NA LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N2571 ( 8, 7) [002253] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB201, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144 V179} ============================== use: {V00 V16 V176} def: {V16 V51 V122 V123} NEW BLOCK BB203 Setting BB201 as the predecessor for determining incoming variable registers of BB203 DefList: { } N2575 (???,???) [004081] ----------- * IL_OFFSET void INL53 @ 0x015[E-] <- INLRT @ ??? REG NA DefList: { } N2577 ( 1, 1) [003035] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2579 ( 1, 2) [003036] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N2581 ( 3, 4) [003037] -----O----- * ADD byref REG NA $25c LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 328: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2581.t3037. ADD } N2583 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 NA REG NA BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2585 ( 1, 1) [002259] ----------- * LCL_VAR int V122 tmp82 u:1 NA REG NA DefList: { } N2587 ( 1, 1) [002264] ----------- * LCL_VAR byref V124 tmp84 u:1 NA REG NA $25c DefList: { } N2589 ( 3, 4) [003040] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2591 ( 4, 3) [002265] n---GO----- * IND int REG NA LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 329: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2591.t2265. IND } N2593 ( 9, 11) [002266] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N2595 ( 1, 1) [002263] ----------- * LCL_VAR byref V124 tmp84 u:1 NA (last use) REG NA $25c DefList: { } N2597 ( 3, 2) [002270] n---GO----- * IND byref REG NA LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 330: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2597.t2270. IND } N2599 ( 1, 1) [002260] ----------- * LCL_VAR int V122 tmp82 u:1 NA REG NA DefList: { N2597.t2270. IND } N2601 ( 2, 3) [002267] -c-------U- * CAST long <- uint REG NA Contained DefList: { N2597.t2270. IND } N2603 ( 1, 2) [002268] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N2597.t2270. IND } N2605 ( 4, 6) [002269] -c--------- * BFIZ long REG NA Contained DefList: { N2597.t2270. IND } N2607 ( 8, 9) [002271] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N2597.t2270. IND } N2609 ( 1, 1) [002273] ----------- * LCL_VAR int V123 tmp83 u:1 NA (last use) REG NA DefList: { N2597.t2270. IND } N2611 (???,???) [004082] -A-XGO----- * STOREIND short REG NA BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2613 (???,???) [004083] ----------- * IL_OFFSET void INL53 @ 0x023[E-] <- INLRT @ ??? REG NA DefList: { } N2615 ( 1, 1) [002277] ----------- * LCL_VAR int V122 tmp82 u:1 NA (last use) REG NA DefList: { } N2617 ( 1, 2) [002278] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2619 ( 3, 4) [002279] ----------- * ADD int REG NA LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 331: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2619.t2279. ADD } N2621 ( 1, 1) [002276] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N2619.t2279. ADD } N2623 ( 3, 4) [003043] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N2619.t2279. ADD } N2625 (???,???) [004084] -A--GO----- * STOREIND int REG NA LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB203, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V122 V123} def: {V124} NEW BLOCK BB204 Setting BB201 as the predecessor for determining incoming variable registers of BB204 DefList: { } N2629 (???,???) [004085] ----------- * IL_OFFSET void INL53 @ 0x02D[E-] <- INLRT @ ??? REG NA DefList: { } N2631 ( 1, 1) [002254] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2633 (???,???) [004280] ----------- * PUTARG_REG byref REG x0 BB204 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB204 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 332: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB204 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N2633.t4280. PUTARG_REG } N2635 ( 1, 1) [002255] ----------- * LCL_VAR int V123 tmp83 u:1 NA (last use) REG NA DefList: { N2633.t4280. PUTARG_REG } N2637 (???,???) [004281] ----------- * PUTARG_REG int REG x1 Last use of V123 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB204 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB204 regmask=[x1] minReg=1 last fixed wt=1200.00> Interval 333: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB204 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N2633.t4280. PUTARG_REG; N2637.t4281. PUTARG_REG } N2639 ( 2, 8) [003044] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn REG NA $53 Interval 334: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB204 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2633.t4280. PUTARG_REG; N2637.t4281. PUTARG_REG; N2639.t3044. CNS_INT } N2641 (???,???) [004282] ----------- * PUTARG_REG long REG x11 BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 335: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB204 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N2633.t4280. PUTARG_REG; N2637.t4281. PUTARG_REG; N2641.t4282. PUTARG_REG } N2643 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 336: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB204 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB204 regmask=[x0] minReg=1 wt=200.00> BB204 regmask=[x0] minReg=1 last fixed wt=200.00> BB204 regmask=[x1] minReg=1 wt=200.00> BB204 regmask=[x1] minReg=1 last fixed wt=200.00> BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB204 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB204 regmask=[x0] minReg=1 wt=200.00> BB204 regmask=[x1] minReg=1 wt=200.00> BB204 regmask=[x2] minReg=1 wt=200.00> BB204 regmask=[x3] minReg=1 wt=200.00> BB204 regmask=[x4] minReg=1 wt=200.00> BB204 regmask=[x5] minReg=1 wt=200.00> BB204 regmask=[x6] minReg=1 wt=200.00> BB204 regmask=[x7] minReg=1 wt=200.00> BB204 regmask=[x8] minReg=1 wt=200.00> BB204 regmask=[x9] minReg=1 wt=200.00> BB204 regmask=[x10] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x12] minReg=1 wt=200.00> BB204 regmask=[x13] minReg=1 wt=200.00> BB204 regmask=[x14] minReg=1 wt=200.00> BB204 regmask=[x15] minReg=1 wt=200.00> BB204 regmask=[xip0] minReg=1 wt=200.00> BB204 regmask=[xip1] minReg=1 wt=200.00> BB204 regmask=[lr] minReg=1 wt=200.00> CHECKING LAST USES for BB204, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V123} def: {} NEW BLOCK BB205 Setting BB139 as the predecessor for determining incoming variable registers of BB205 DefList: { } N2647 (???,???) [004086] ----------- * IL_OFFSET void INLRT @ 0x64D[E-] REG NA DefList: { } N2649 ( 1, 2) [003045] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N2651 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 NA REG NA STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> DefList: { } N2653 (???,???) [004087] ----------- * IL_OFFSET void INLRT @ 0x650[E-] REG NA DefList: { } N2655 ( 1, 2) [000326] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N2657 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 NA REG NA STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N2659 (???,???) [004088] ----------- * IL_OFFSET void INLRT @ 0x653[E-] REG NA DefList: { } N2661 ( 1, 1) [000329] ----------- * LCL_VAR int V09 loc5 u:3 NA REG NA $4c6 DefList: { } N2663 ( 1, 2) [000330] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N2665 ( 3, 4) [000331] CEQ-------N--- * JCMP void REG NA LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2500.00> CHECKING LAST USES for BB205, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V09} def: {V37 V38} NEW BLOCK BB206 Setting BB205 as the predecessor for determining incoming variable registers of BB206 DefList: { } N2669 (???,???) [004089] ----------- * IL_OFFSET void INLRT @ 0x65A[E-] REG NA DefList: { } N2671 ( 1, 1) [000419] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N2673 ( 1, 1) [003702] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N2675 ( 3, 3) [000424] J------N--- * GE void REG NA $94d LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N2677 ( 5, 5) [000425] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB206, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V16 V179} def: {} NEW BLOCK BB207 Setting BB206 as the predecessor for determining incoming variable registers of BB207 DefList: { } N2681 (???,???) [004090] ----------- * IL_OFFSET void INLRT @ 0x665[E-] REG NA DefList: { } N2683 ( 1, 1) [000565] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N2685 ( 1, 1) [000566] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N2687 ( 2, 3) [000567] -c--------- * CAST long <- int REG NA $3e5 Contained DefList: { } N2689 ( 1, 2) [000569] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N2691 ( 4, 6) [000570] -c--------- * BFIZ long REG NA Contained DefList: { } N2693 ( 6, 8) [000571] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N2695 ( 9, 10) [000572] ---XG------ * IND ushort REG NA LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 337: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2695.t572. IND } N2697 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 NA REG NA BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> DefList: { } N2699 ( 1, 1) [003670] ----------- * LCL_VAR int V176 cse5 NA (last use) REG NA DefList: { } N2701 ( 1, 2) [000573] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { } N2703 ( 12, 14) [000574] N--XG--N-U- * EQ void REG NA LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> DefList: { } N2705 ( 14, 16) [000575] ---XG------ * JTRUE void REG NA $87a CHECKING LAST USES for BB207, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V16 V34} def: {V176} NEW BLOCK BB208 Setting BB206 as the predecessor for determining incoming variable registers of BB208 DefList: { } N2709 (???,???) [004091] ----------- * IL_OFFSET void INLRT @ 0x67A[E-] REG NA DefList: { } N2711 ( 1, 1) [000426] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N2713 ( 1, 2) [000427] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2715 ( 3, 4) [000428] ----------- * ADD int REG NA $952 LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 338: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2715.t428. ADD } N2717 ( 1, 1) [003703] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { N2715.t428. ADD } N2719 ( 5, 6) [000433] J------N--- * GE void REG NA $9e2 BB208 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N2721 ( 7, 8) [000434] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB208, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V16 V179} def: {} NEW BLOCK BB209 Setting BB208 as the predecessor for determining incoming variable registers of BB209 DefList: { } N2725 (???,???) [004092] ----------- * IL_OFFSET void INLRT @ 0x687[E-] REG NA DefList: { } N2727 ( 1, 1) [000538] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N2729 ( 1, 1) [000539] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N2731 ( 2, 3) [000540] -c--------- * CAST long <- int REG NA $3e5 Contained DefList: { } N2733 ( 1, 2) [000542] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N2735 ( 4, 6) [000543] -c--------- * BFIZ long REG NA Contained DefList: { } N2737 ( 6, 8) [000544] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N2739 ( 9, 10) [000545] ---XG------ * IND ushort REG NA LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 339: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2739.t545. IND } N2741 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 NA REG NA BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> DefList: { } N2743 ( 1, 1) [003674] ----------- * LCL_VAR int V176 cse5 NA REG NA DefList: { } N2745 ( 1, 2) [000546] -c--------- * CNS_INT int 43 REG NA $d9 Contained DefList: { } N2747 ( 15, 14) [000547] N--XG--N-U- * NE int REG NA LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Interval 340: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2747.t547. NE } N2749 ( 1, 1) [000549] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { N2747.t547. NE } N2751 ( 1, 1) [000550] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { N2747.t547. NE } N2753 ( 1, 2) [000551] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { N2747.t547. NE } N2755 ( 3, 4) [000552] ----------- * ADD int REG NA $952 LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 341: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2747.t547. NE; N2755.t552. ADD } N2757 ( 4, 6) [000553] -c--------- * CAST long <- int REG NA $3f4 Contained DefList: { N2747.t547. NE; N2755.t552. ADD } N2759 ( 1, 2) [000555] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N2747.t547. NE; N2755.t552. ADD } N2761 ( 6, 9) [000556] -c--------- * BFIZ long REG NA Contained DefList: { N2747.t547. NE; N2755.t552. ADD } N2763 ( 8, 11) [000557] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { N2747.t547. NE; N2755.t552. ADD } N2765 ( 11, 13) [000558] ---XG------ * IND ushort REG NA LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 342: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2747.t547. NE; N2765.t558. IND } N2767 ( 1, 2) [000559] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { N2747.t547. NE; N2765.t558. IND } N2769 ( 16, 16) [000560] N--XG--N-U- * NE int REG NA BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 343: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2747.t547. NE; N2769.t560. NE } N2771 ( 32, 31) [003762] J--XG--N--- * AND int REG NA BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 344: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] AND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2771.t3762. AND } N2773 ( 34, 33) [000548] ---XG------ * JTRUE void REG NA $87a BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB209, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V176 V179} ============================== use: {V16 V34} def: {V176} NEW BLOCK BB210 Setting BB209 as the predecessor for determining incoming variable registers of BB210 DefList: { } N2777 (???,???) [004093] ----------- * IL_OFFSET void INLRT @ 0x694[E-] REG NA DefList: { } N2779 (???,???) [004094] ----------- * IL_OFFSET void INLRT @ 0x6A3[E-] REG NA DefList: { } N2781 ( 1, 2) [003046] ----------- * CNS_INT int 1 REG NA $c1 Interval 345: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB210 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2781.t3046. CNS_INT } N2783 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 NA REG NA BB210 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB210 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> CHECKING LAST USES for BB210, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {} def: {V37} NEW BLOCK BB213 Setting BB209 as the predecessor for determining incoming variable registers of BB213 DefList: { } N2787 (???,???) [004095] ----------- * IL_OFFSET void INLRT @ 0x6B5[E-] REG NA DefList: { } N2789 ( 1, 1) [003676] ----------- * LCL_VAR int V176 cse5 NA (last use) REG NA DefList: { } N2791 ( 1, 2) [000455] -c--------- * CNS_INT int 45 REG NA $da Contained DefList: { } N2793 ( 3, 4) [000456] N---G--N-U- * NE void REG NA LCL_VAR BB213 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> DefList: { } N2795 ( 5, 6) [000457] ----G------ * JTRUE void REG NA $87a CHECKING LAST USES for BB213, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V176} def: {} NEW BLOCK BB214 Setting BB213 as the predecessor for determining incoming variable registers of BB214 DefList: { } N2799 (???,???) [004096] ----------- * IL_OFFSET void INLRT @ 0x6C2[E-] REG NA DefList: { } N2801 ( 1, 1) [000458] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N2803 ( 1, 1) [000459] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N2805 ( 1, 2) [000460] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2807 ( 3, 4) [000461] ----------- * ADD int REG NA $952 LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 346: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2807.t461. ADD } N2809 ( 4, 6) [000462] -c--------- * CAST long <- int REG NA $3f4 Contained DefList: { N2807.t461. ADD } N2811 ( 1, 2) [000464] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N2807.t461. ADD } N2813 ( 6, 9) [000465] -c--------- * BFIZ long REG NA Contained DefList: { N2807.t461. ADD } N2815 ( 8, 11) [000466] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { N2807.t461. ADD } N2817 ( 11, 13) [000467] ---XG------ * IND ushort REG NA LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> BB214 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 347: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2817.t467. IND } N2819 ( 1, 2) [000468] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { N2817.t467. IND } N2821 ( 13, 16) [000469] J--XG--N--- * EQ void REG NA BB214 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N2823 ( 15, 18) [000470] ---XG------ * JTRUE void REG NA $a11 CHECKING LAST USES for BB214, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V16 V34} def: {} NEW BLOCK BB215 Setting BB208 as the predecessor for determining incoming variable registers of BB215 DefList: { } N2827 (???,???) [004097] ----------- * IL_OFFSET void INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] REG NA DefList: { } N2829 ( 1, 1) [000444] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2831 ( 3, 4) [003048] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2833 ( 4, 3) [002302] ---XG------ * IND int REG NA LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 348: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2833.t2302. IND } N2835 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 NA REG NA BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N2837 (???,???) [004098] ----------- * IL_OFFSET void INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] REG NA DefList: { } N2839 ( 1, 1) [002305] ----------- * LCL_VAR int V126 tmp86 u:1 NA REG NA DefList: { } N2841 ( 1, 1) [002306] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2843 ( 3, 4) [003052] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N2845 ( 4, 3) [002341] n---GO----- * IND int REG NA LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 349: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2845.t2341. IND } N2847 ( 6, 5) [002310] N---GO-N-U- * GE void REG NA LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N2849 ( 8, 7) [002311] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB215, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144 V179} ============================== use: {V00} def: {V126} NEW BLOCK BB216 Setting BB215 as the predecessor for determining incoming variable registers of BB216 DefList: { } N2853 (???,???) [004099] ----------- * IL_OFFSET void INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] REG NA DefList: { } N2855 ( 1, 1) [003056] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N2857 ( 1, 2) [003057] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N2859 ( 3, 4) [003058] -----O----- * ADD byref REG NA $25c LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 350: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2859.t3058. ADD } N2861 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 NA REG NA BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N2863 (???,???) [004100] ----------- * IL_OFFSET void INL58 @ ??? <- INLRT @ 0x6D1[E-] REG NA DefList: { } N2865 ( 1, 1) [002316] ----------- * LCL_VAR int V126 tmp86 u:1 NA REG NA DefList: { } N2867 ( 1, 1) [002321] ----------- * LCL_VAR byref V127 tmp87 u:1 NA REG NA $25c DefList: { } N2869 ( 3, 4) [003061] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N2871 ( 4, 3) [002322] n---GO----- * IND int REG NA LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 351: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2871.t2322. IND } N2873 ( 9, 11) [002323] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N2875 ( 1, 1) [002320] ----------- * LCL_VAR byref V127 tmp87 u:1 NA (last use) REG NA $25c DefList: { } N2877 ( 3, 2) [002327] n---GO----- * IND byref REG NA LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 352: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2877.t2327. IND } N2879 ( 1, 1) [002317] ----------- * LCL_VAR int V126 tmp86 u:1 NA REG NA DefList: { N2877.t2327. IND } N2881 ( 2, 3) [002324] -c-------U- * CAST long <- uint REG NA Contained DefList: { N2877.t2327. IND } N2883 ( 1, 2) [002325] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N2877.t2327. IND } N2885 ( 4, 6) [002326] -c--------- * BFIZ long REG NA Contained DefList: { N2877.t2327. IND } N2887 ( 8, 9) [002328] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N2877.t2327. IND } N2889 ( 1, 1) [002330] ----------- * LCL_VAR int V18 loc14 u:1 NA (last use) REG NA DefList: { N2877.t2327. IND } N2891 (???,???) [004101] -A-XGO----- * STOREIND short REG NA BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N2893 (???,???) [004102] ----------- * IL_OFFSET void INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] REG NA DefList: { } N2895 ( 1, 1) [002334] ----------- * LCL_VAR int V126 tmp86 u:1 NA (last use) REG NA DefList: { } N2897 ( 1, 2) [002335] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2899 ( 3, 4) [002336] ----------- * ADD int REG NA LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 353: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2899.t2336. ADD } N2901 ( 1, 1) [002333] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N2899.t2336. ADD } N2903 ( 3, 4) [003064] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N2899.t2336. ADD } N2905 (???,???) [004103] -A--GO----- * STOREIND int REG NA LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Exposed uses: BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> CHECKING LAST USES for BB216, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V18 V126} def: {V127} NEW BLOCK BB218 Setting BB207 as the predecessor for determining incoming variable registers of BB218 DefList: { } N2909 (???,???) [004104] ----------- * IL_OFFSET void INLRT @ 0x6DE[E-] REG NA DefList: { } N2911 ( 1, 1) [000533] ----------- * LCL_VAR int V38 loc34 u:5 NA (last use) REG NA $b0d DefList: { } N2913 ( 1, 2) [000534] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2915 ( 3, 4) [000535] ----------- * ADD int REG NA $c59 LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 354: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB218 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N2915.t535. ADD } N2917 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 NA REG NA BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB218, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V38} def: {V38} NEW BLOCK BB219 Setting BB218 as the predecessor for determining incoming variable registers of BB219 DefList: { } N2921 (???,???) [004105] ----------- * IL_OFFSET void INLRT @ 0x6E4[E-] REG NA DefList: { } N2923 ( 1, 1) [000471] ----------- * LCL_VAR int V16 loc12 u:9 NA (last use) REG NA $b0e DefList: { } N2925 ( 1, 2) [000472] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N2927 ( 3, 4) [000473] ----------- * ADD int REG NA $c5c LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 355: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> DefList: { N2927.t473. ADD } N2929 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 NA REG NA BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Assigning related to STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> DefList: { } N2931 ( 1, 1) [000477] ----------- * LCL_VAR int V54 tmp14 u:1 NA (last use) REG NA $c5c DefList: { } N2933 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 NA REG NA LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> Assigning related to STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N2935 ( 1, 1) [000476] ----------- * LCL_VAR int V16 loc12 u:10 NA REG NA $c5c DefList: { } N2937 ( 1, 1) [003704] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N2939 ( 3, 3) [000484] J------N--- * GE void REG NA $c5d LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N2941 ( 5, 5) [000485] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB219, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V16 V179} def: {V16 V54} NEW BLOCK BB220 Setting BB219 as the predecessor for determining incoming variable registers of BB220 DefList: { } N2945 (???,???) [004106] ----------- * IL_OFFSET void INLRT @ 0x6F4[E-] REG NA DefList: { } N2947 ( 1, 1) [000522] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N2949 ( 1, 1) [000523] ----------- * LCL_VAR int V16 loc12 u:10 NA REG NA $c5c DefList: { } N2951 ( 2, 3) [000524] -c--------- * CAST long <- int REG NA $ad8 Contained DefList: { } N2953 ( 1, 2) [000526] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N2955 ( 4, 6) [000527] -c--------- * BFIZ long REG NA Contained DefList: { } N2957 ( 6, 8) [000528] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N2959 ( 9, 10) [000529] ---XG------ * IND ushort REG NA LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 356: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> DefList: { N2959.t529. IND } N2961 ( 1, 2) [000530] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { N2959.t529. IND } N2963 ( 11, 13) [000531] J--XG--N--- * EQ void REG NA BB220 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> DefList: { } N2965 ( 13, 15) [000532] ---XG------ * JTRUE void REG NA $c18 CHECKING LAST USES for BB220, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V16 V34} def: {} NEW BLOCK BB221 Setting BB219 as the predecessor for determining incoming variable registers of BB221 DefList: { } N2969 (???,???) [004107] ----------- * IL_OFFSET void INLRT @ 0x701[E-] REG NA DefList: { } N2971 ( 1, 1) [000486] ----------- * LCL_VAR int V38 loc34 u:2 NA REG NA $b0f DefList: { } N2973 ( 1, 2) [000487] -c--------- * CNS_INT int 10 REG NA $e4 Contained DefList: { } N2975 ( 3, 4) [000488] J------N--- * LE void REG NA $c62 LCL_VAR BB221 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N2977 ( 5, 6) [000489] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB221, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V38} def: {} NEW BLOCK BB222 Setting BB221 as the predecessor for determining incoming variable registers of BB222 DefList: { } N2981 (???,???) [004108] ----------- * IL_OFFSET void INLRT @ 0x707[E-] REG NA DefList: { } N2983 ( 1, 2) [000519] ----------- * CNS_INT int 10 REG NA $e4 Interval 357: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB222 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2983.t519. CNS_INT } N2985 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 NA REG NA BB222 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB222 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB222, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {} def: {V38} NEW BLOCK BB223 Setting BB221 as the predecessor for determining incoming variable registers of BB223 DefList: { } N2989 (???,???) [004109] ----------- * IL_OFFSET void INLRT @ 0x70B[E-] REG NA DefList: { } N2991 ( 1, 1) [000490] ----------- * LCL_VAR long V17 loc13 u:1 NA REG NA DefList: { } N2993 ( 4, 3) [000491] ---XG------ * IND ubyte REG NA LCL_VAR BB223 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1700.00> Interval 358: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB223 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N2993.t491. IND } N2995 ( 1, 2) [000492] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N2993.t491. IND } N2997 ( 6, 6) [000493] CEQ---XG--N--- * JCMP void REG NA BB223 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB223, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} ============================== use: {V17} def: {} NEW BLOCK BB224 Setting BB223 as the predecessor for determining incoming variable registers of BB224 DefList: { } N3001 (???,???) [004110] ----------- * IL_OFFSET void INLRT @ 0x710[E-] REG NA DefList: { } N3003 ( 1, 1) [000512] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N3005 ( 3, 4) [003067] -c--------- * LEA(b+4) byref REG NA Contained DefList: { } N3007 ( 4, 3) [000513] n---GO----- * IND int REG NA LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 359: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3007.t513. IND } N3009 ( 1, 1) [000514] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { N3007.t513. IND } N3011 ( 6, 5) [000515] ----GO----- * SUB int REG NA BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> Interval 360: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SUB BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3011.t515. SUB } N3013 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 NA REG NA BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> CHECKING LAST USES for BB224, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144 V179} ============================== use: {V01 V05} def: {V55} NEW BLOCK BB225 Setting BB223 as the predecessor for determining incoming variable registers of BB225 DefList: { } N3017 (???,???) [004111] ----------- * IL_OFFSET void INLRT @ 0x71A[E-] REG NA DefList: { } N3019 ( 1, 2) [000495] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3021 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 NA REG NA STORE_LCL_VAR BB225 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> CHECKING LAST USES for BB225, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144 V179} ============================== use: {} def: {V55} NEW BLOCK BB226 Setting BB224 as the predecessor for determining incoming variable registers of BB226 DefList: { } N3025 (???,???) [004112] ----------- * IL_OFFSET void INLRT @ 0x71D[E-] REG NA DefList: { } N3027 ( 1, 1) [000507] ----------- * LCL_VAR int V37 loc33 u:2 NA (last use) REG NA $4ca DefList: { } N3029 (???,???) [004283] ----------- * PUTARG_REG int REG x5 BB226 regmask=[x5] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x5] minReg=1 last fixed wt=600.00> Interval 361: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB226 regmask=[x5] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x5] minReg=1 fixed wt=800.00> DefList: { N3029.t4283. PUTARG_REG } N3031 ( 1, 1) [000502] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N3029.t4283. PUTARG_REG } N3033 (???,???) [004284] ----------- * PUTARG_REG byref REG x0 BB226 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 362: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB226 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG } N3035 ( 1, 1) [000503] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG } N3037 (???,???) [004285] ----------- * PUTARG_REG ref REG x1 BB226 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x1] minReg=1 last fixed wt=2250.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 363: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB226 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x1] minReg=1 fixed wt=800.00> Assigning related to DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG } N3039 ( 1, 1) [000499] ----------- * LCL_VAR int V55 tmp15 u:1 NA (last use) REG NA $b12 DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG } N3041 (???,???) [004286] ----------- * PUTARG_REG int REG x2 Last use of V55 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0-x1 x5] BB226 regmask=[x2] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x2] minReg=1 last fixed wt=600.00> Interval 364: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB226 regmask=[x2] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x2] minReg=1 fixed wt=800.00> DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG; N3041.t4286. PUTARG_REG } N3043 ( 1, 1) [000505] ----------- * LCL_VAR int V18 loc14 u:1 NA (last use) REG NA DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG; N3041.t4286. PUTARG_REG } N3045 (???,???) [004287] ----------- * PUTARG_REG int REG x3 Last use of V18 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0-x2 x5] BB226 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x3] minReg=1 last fixed wt=23800.00> Interval 365: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB226 regmask=[x3] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x3] minReg=1 fixed wt=800.00> DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG; N3041.t4286. PUTARG_REG; N3045.t4287. PUTARG_REG } N3047 ( 1, 1) [000506] ----------- * LCL_VAR int V38 loc34 u:3 NA (last use) REG NA $b10 DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG; N3041.t4286. PUTARG_REG; N3045.t4287. PUTARG_REG } N3049 (???,???) [004288] ----------- * PUTARG_REG int REG x4 Last use of V38 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0-x3 x5] BB226 regmask=[x4] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x4] minReg=1 last fixed wt=2400.00> Interval 366: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB226 regmask=[x4] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x4] minReg=1 fixed wt=800.00> DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG; N3041.t4286. PUTARG_REG; N3045.t4287. PUTARG_REG; N3049.t4288. PUTARG_REG } N3051 ( 2, 8) [003068] H---------- * CNS_INT(h) long 0x4000000000540240 ftn REG NA $5e Interval 367: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB226 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG; N3041.t4286. PUTARG_REG; N3045.t4287. PUTARG_REG; N3049.t4288. PUTARG_REG; N3051.t3068. CNS_INT } N3053 (???,???) [004289] ----------- * PUTARG_REG long REG x11 BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 368: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB226 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N3029.t4283. PUTARG_REG; N3033.t4284. PUTARG_REG; N3037.t4285. PUTARG_REG; N3041.t4286. PUTARG_REG; N3045.t4287. PUTARG_REG; N3049.t4288. PUTARG_REG; N3053.t4289. PUTARG_REG } N3055 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) REG NA $VN.Void Interval 369: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB226 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB226 regmask=[x5] minReg=1 wt=200.00> BB226 regmask=[x5] minReg=1 last fixed wt=200.00> BB226 regmask=[x0] minReg=1 wt=200.00> BB226 regmask=[x0] minReg=1 last fixed wt=200.00> BB226 regmask=[x1] minReg=1 wt=200.00> BB226 regmask=[x1] minReg=1 last fixed wt=200.00> BB226 regmask=[x2] minReg=1 wt=200.00> BB226 regmask=[x2] minReg=1 last fixed wt=200.00> BB226 regmask=[x3] minReg=1 wt=200.00> BB226 regmask=[x3] minReg=1 last fixed wt=200.00> BB226 regmask=[x4] minReg=1 wt=200.00> BB226 regmask=[x4] minReg=1 last fixed wt=200.00> BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB226 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB226 regmask=[x0] minReg=1 wt=200.00> BB226 regmask=[x1] minReg=1 wt=200.00> BB226 regmask=[x2] minReg=1 wt=200.00> BB226 regmask=[x3] minReg=1 wt=200.00> BB226 regmask=[x4] minReg=1 wt=200.00> BB226 regmask=[x5] minReg=1 wt=200.00> BB226 regmask=[x6] minReg=1 wt=200.00> BB226 regmask=[x7] minReg=1 wt=200.00> BB226 regmask=[x8] minReg=1 wt=200.00> BB226 regmask=[x9] minReg=1 wt=200.00> BB226 regmask=[x10] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x12] minReg=1 wt=200.00> BB226 regmask=[x13] minReg=1 wt=200.00> BB226 regmask=[x14] minReg=1 wt=200.00> BB226 regmask=[x15] minReg=1 wt=200.00> BB226 regmask=[xip0] minReg=1 wt=200.00> BB226 regmask=[xip1] minReg=1 wt=200.00> BB226 regmask=[lr] minReg=1 wt=200.00> DefList: { } N3057 (???,???) [004113] ----------- * IL_OFFSET void INLRT @ 0x72C[E-] REG NA DefList: { } N3059 ( 1, 2) [003069] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3061 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 NA REG NA STORE_LCL_VAR BB226 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2500.00> CHECKING LAST USES for BB226, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V03 V18 V37 V38 V55} def: {V09} NEW BLOCK BB227 Setting BB205 as the predecessor for determining incoming variable registers of BB227 DefList: { } N3065 (???,???) [004114] ----------- * IL_OFFSET void INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] REG NA DefList: { } N3067 ( 1, 1) [000333] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3069 ( 3, 4) [003071] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3071 ( 4, 3) [002349] ---XG------ * IND int REG NA LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 370: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3071.t2349. IND } N3073 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 NA REG NA BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N3075 (???,???) [004115] ----------- * IL_OFFSET void INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] REG NA DefList: { } N3077 ( 1, 1) [002352] ----------- * LCL_VAR int V129 tmp89 u:1 NA REG NA DefList: { } N3079 ( 1, 1) [002353] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3081 ( 3, 4) [003075] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N3083 ( 4, 3) [002388] n---GO----- * IND int REG NA LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 371: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3083.t2388. IND } N3085 ( 6, 5) [002357] N---GO-N-U- * GE void REG NA LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N3087 ( 8, 7) [002358] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB227, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144 V179} ============================== use: {V00} def: {V129} NEW BLOCK BB228 Setting BB227 as the predecessor for determining incoming variable registers of BB228 DefList: { } N3091 (???,???) [004116] ----------- * IL_OFFSET void INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] REG NA DefList: { } N3093 ( 1, 1) [003079] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3095 ( 1, 2) [003080] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N3097 ( 3, 4) [003081] -----O----- * ADD byref REG NA $25c LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 372: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3097.t3081. ADD } N3099 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 NA REG NA BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N3101 (???,???) [004117] ----------- * IL_OFFSET void INL61 @ ??? <- INLRT @ 0x731[E-] REG NA DefList: { } N3103 ( 1, 1) [002363] ----------- * LCL_VAR int V129 tmp89 u:1 NA REG NA DefList: { } N3105 ( 1, 1) [002368] ----------- * LCL_VAR byref V130 tmp90 u:1 NA REG NA $25c DefList: { } N3107 ( 3, 4) [003084] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3109 ( 4, 3) [002369] n---GO----- * IND int REG NA LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 373: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3109.t2369. IND } N3111 ( 9, 11) [002370] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N3113 ( 1, 1) [002367] ----------- * LCL_VAR byref V130 tmp90 u:1 NA (last use) REG NA $25c DefList: { } N3115 ( 3, 2) [002374] n---GO----- * IND byref REG NA LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 374: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3115.t2374. IND } N3117 ( 1, 1) [002364] ----------- * LCL_VAR int V129 tmp89 u:1 NA REG NA DefList: { N3115.t2374. IND } N3119 ( 2, 3) [002371] -c-------U- * CAST long <- uint REG NA Contained DefList: { N3115.t2374. IND } N3121 ( 1, 2) [002372] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N3115.t2374. IND } N3123 ( 4, 6) [002373] -c--------- * BFIZ long REG NA Contained DefList: { N3115.t2374. IND } N3125 ( 8, 9) [002375] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N3115.t2374. IND } N3127 ( 1, 1) [002377] ----------- * LCL_VAR int V18 loc14 u:1 NA (last use) REG NA DefList: { N3115.t2374. IND } N3129 (???,???) [004118] -A-XGO----- * STOREIND short REG NA BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N3131 (???,???) [004119] ----------- * IL_OFFSET void INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] REG NA DefList: { } N3133 ( 1, 1) [002381] ----------- * LCL_VAR int V129 tmp89 u:1 NA (last use) REG NA DefList: { } N3135 ( 1, 2) [002382] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3137 ( 3, 4) [002383] ----------- * ADD int REG NA LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 375: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3137.t2383. ADD } N3139 ( 1, 1) [002380] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N3137.t2383. ADD } N3141 ( 3, 4) [003087] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N3137.t2383. ADD } N3143 (???,???) [004120] -A--GO----- * STOREIND int REG NA LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB228, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V18 V129} def: {V130} NEW BLOCK BB229 Setting BB227 as the predecessor for determining incoming variable registers of BB229 DefList: { } N3147 (???,???) [004121] ----------- * IL_OFFSET void INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] REG NA DefList: { } N3149 ( 1, 1) [002359] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3151 (???,???) [004290] ----------- * PUTARG_REG byref REG x0 BB229 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB229 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 376: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB229 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N3151.t4290. PUTARG_REG } N3153 ( 1, 1) [000334] ----------- * LCL_VAR int V18 loc14 u:1 NA (last use) REG NA DefList: { N3151.t4290. PUTARG_REG } N3155 (???,???) [004291] ----------- * PUTARG_REG int REG x1 Last use of V18 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB229 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB229 regmask=[x1] minReg=1 last fixed wt=23800.00> Interval 377: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB229 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N3151.t4290. PUTARG_REG; N3155.t4291. PUTARG_REG } N3157 ( 2, 8) [003088] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn REG NA $53 Interval 378: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB229 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3151.t4290. PUTARG_REG; N3155.t4291. PUTARG_REG; N3157.t3088. CNS_INT } N3159 (???,???) [004292] ----------- * PUTARG_REG long REG x11 BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 379: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB229 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N3151.t4290. PUTARG_REG; N3155.t4291. PUTARG_REG; N3159.t4292. PUTARG_REG } N3161 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 380: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB229 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB229 regmask=[x0] minReg=1 wt=200.00> BB229 regmask=[x0] minReg=1 last fixed wt=200.00> BB229 regmask=[x1] minReg=1 wt=200.00> BB229 regmask=[x1] minReg=1 last fixed wt=200.00> BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB229 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB229 regmask=[x0] minReg=1 wt=200.00> BB229 regmask=[x1] minReg=1 wt=200.00> BB229 regmask=[x2] minReg=1 wt=200.00> BB229 regmask=[x3] minReg=1 wt=200.00> BB229 regmask=[x4] minReg=1 wt=200.00> BB229 regmask=[x5] minReg=1 wt=200.00> BB229 regmask=[x6] minReg=1 wt=200.00> BB229 regmask=[x7] minReg=1 wt=200.00> BB229 regmask=[x8] minReg=1 wt=200.00> BB229 regmask=[x9] minReg=1 wt=200.00> BB229 regmask=[x10] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x12] minReg=1 wt=200.00> BB229 regmask=[x13] minReg=1 wt=200.00> BB229 regmask=[x14] minReg=1 wt=200.00> BB229 regmask=[x15] minReg=1 wt=200.00> BB229 regmask=[xip0] minReg=1 wt=200.00> BB229 regmask=[xip1] minReg=1 wt=200.00> BB229 regmask=[lr] minReg=1 wt=200.00> CHECKING LAST USES for BB229, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V18} def: {} NEW BLOCK BB230 Setting BB228 as the predecessor for determining incoming variable registers of BB230 DefList: { } N3165 (???,???) [004122] ----------- * IL_OFFSET void INLRT @ 0x739[E-] REG NA DefList: { } N3167 ( 1, 1) [000336] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N3169 ( 1, 1) [003705] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N3171 ( 3, 3) [000341] J------N--- * GE void REG NA $94d LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N3173 ( 5, 5) [000342] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB230, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V16 V179} def: {} NEW BLOCK BB231 Setting BB112 as the predecessor for determining incoming variable registers of BB231 DefList: { } N3177 (???,???) [004123] ----------- * IL_OFFSET void INLRT @ 0x744[E-] REG NA DefList: { } N3179 ( 1, 1) [000343] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N3181 ( 1, 1) [000344] ----------- * LCL_VAR int V16 loc12 u:5 NA REG NA $898 DefList: { } N3183 ( 2, 3) [000345] -c--------- * CAST long <- int REG NA $3e5 Contained DefList: { } N3185 ( 1, 2) [000347] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N3187 ( 4, 6) [000348] -c--------- * BFIZ long REG NA Contained DefList: { } N3189 ( 6, 8) [000349] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N3191 ( 9, 10) [000350] ---XG------ * IND ushort REG NA LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 381: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3191.t350. IND } N3193 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 NA REG NA BB231 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N3195 ( 1, 1) [003659] ----------- * LCL_VAR int V175 cse4 u:1 NA REG NA DefList: { } N3197 ( 1, 2) [000351] -c--------- * CNS_INT int 43 REG NA $d9 Contained DefList: { } N3199 ( 12, 14) [000352] J--XG--N--- * EQ void REG NA LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N3201 ( 14, 16) [000353] ---XG------ * JTRUE void REG NA $87a CHECKING LAST USES for BB231, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} ============================== use: {V16 V34} def: {V175} NEW BLOCK BB232 Setting BB231 as the predecessor for determining incoming variable registers of BB232 DefList: { } N3205 (???,???) [004124] ----------- * IL_OFFSET void INLRT @ 0x751[E-] REG NA DefList: { } N3207 ( 1, 1) [003661] ----------- * LCL_VAR int V175 cse4 u:1 NA REG NA DefList: { } N3209 ( 1, 2) [000416] -c--------- * CNS_INT int 45 REG NA $da Contained DefList: { } N3211 ( 3, 4) [000417] N---G--N-U- * NE void REG NA LCL_VAR BB232 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N3213 ( 5, 6) [000418] ----G------ * JTRUE void REG NA $87a CHECKING LAST USES for BB232, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} ============================== use: {V175} def: {} NEW BLOCK BB233 Setting BB231 as the predecessor for determining incoming variable registers of BB233 DefList: { } N3217 (???,???) [004125] ----------- * IL_OFFSET void INLRT @ 0x75E[E-] REG NA DefList: { } N3219 ( 1, 1) [000356] ----------- * LCL_VAR int V16 loc12 u:5 NA (last use) REG NA $898 DefList: { } N3221 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 NA REG NA LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N3223 (???,???) [004126] ----------- * IL_OFFSET void INLRT @ 0x75E[E-] REG NA DefList: { } N3225 ( 1, 1) [000357] ----------- * LCL_VAR int V52 tmp12 u:1 NA (last use) REG NA $898 DefList: { } N3227 ( 1, 2) [000358] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3229 ( 3, 4) [000359] ----------- * ADD int REG NA $952 LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Interval 382: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3229.t359. ADD } N3231 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 NA REG NA BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N3233 ( 1, 1) [003662] ----------- * LCL_VAR int V175 cse4 u:1 NA (last use) REG NA DefList: { } N3235 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 NA REG NA LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N3237 (???,???) [004127] ----------- * IL_OFFSET void INL64 @ 0x000[E-] <- INLRT @ ??? REG NA DefList: { } N3239 ( 1, 1) [000354] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3241 ( 3, 4) [003090] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3243 ( 4, 3) [002396] n---GO----- * IND int REG NA LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 383: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3243.t2396. IND } N3245 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 NA REG NA BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N3247 (???,???) [004128] ----------- * IL_OFFSET void INL64 @ 0x007[E-] <- INLRT @ ??? REG NA DefList: { } N3249 ( 1, 1) [002399] ----------- * LCL_VAR int V132 tmp92 u:1 NA REG NA DefList: { } N3251 ( 1, 1) [002400] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3253 ( 3, 4) [003094] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N3255 ( 4, 3) [002438] n---GO----- * IND int REG NA LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 384: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3255.t2438. IND } N3257 ( 6, 5) [002404] N---GO-N-U- * GE void REG NA LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N3259 ( 8, 7) [002405] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB233, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144 V179} ============================== use: {V00 V16 V175} def: {V16 V52 V132 V133} NEW BLOCK BB234 Setting BB233 as the predecessor for determining incoming variable registers of BB234 DefList: { } N3263 (???,???) [004129] ----------- * IL_OFFSET void INL64 @ 0x015[E-] <- INLRT @ ??? REG NA DefList: { } N3265 ( 1, 1) [003098] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3267 ( 1, 2) [003099] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N3269 ( 3, 4) [003100] -----O----- * ADD byref REG NA $25c LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 385: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3269.t3100. ADD } N3271 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 NA REG NA BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N3273 ( 1, 1) [002411] ----------- * LCL_VAR int V132 tmp92 u:1 NA REG NA DefList: { } N3275 ( 1, 1) [002416] ----------- * LCL_VAR byref V134 tmp94 u:1 NA REG NA $25c DefList: { } N3277 ( 3, 4) [003103] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3279 ( 4, 3) [002417] n---GO----- * IND int REG NA LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 386: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3279.t2417. IND } N3281 ( 9, 11) [002418] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N3283 ( 1, 1) [002415] ----------- * LCL_VAR byref V134 tmp94 u:1 NA (last use) REG NA $25c DefList: { } N3285 ( 3, 2) [002422] n---GO----- * IND byref REG NA LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 387: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3285.t2422. IND } N3287 ( 1, 1) [002412] ----------- * LCL_VAR int V132 tmp92 u:1 NA REG NA DefList: { N3285.t2422. IND } N3289 ( 2, 3) [002419] -c-------U- * CAST long <- uint REG NA Contained DefList: { N3285.t2422. IND } N3291 ( 1, 2) [002420] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N3285.t2422. IND } N3293 ( 4, 6) [002421] -c--------- * BFIZ long REG NA Contained DefList: { N3285.t2422. IND } N3295 ( 8, 9) [002423] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N3285.t2422. IND } N3297 ( 1, 1) [002425] ----------- * LCL_VAR int V133 tmp93 u:1 NA (last use) REG NA DefList: { N3285.t2422. IND } N3299 (???,???) [004130] -A-XGO----- * STOREIND short REG NA BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N3301 (???,???) [004131] ----------- * IL_OFFSET void INL64 @ 0x023[E-] <- INLRT @ ??? REG NA DefList: { } N3303 ( 1, 1) [002429] ----------- * LCL_VAR int V132 tmp92 u:1 NA (last use) REG NA DefList: { } N3305 ( 1, 2) [002430] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3307 ( 3, 4) [002431] ----------- * ADD int REG NA LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 388: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3307.t2431. ADD } N3309 ( 1, 1) [002428] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N3307.t2431. ADD } N3311 ( 3, 4) [003106] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N3307.t2431. ADD } N3313 (???,???) [004132] -A--GO----- * STOREIND int REG NA LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB234, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V132 V133} def: {V134} NEW BLOCK BB235 Setting BB233 as the predecessor for determining incoming variable registers of BB235 DefList: { } N3317 (???,???) [004133] ----------- * IL_OFFSET void INL64 @ 0x02D[E-] <- INLRT @ ??? REG NA DefList: { } N3319 ( 1, 1) [002406] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3321 (???,???) [004293] ----------- * PUTARG_REG byref REG x0 BB235 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB235 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 389: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB235 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N3321.t4293. PUTARG_REG } N3323 ( 1, 1) [002407] ----------- * LCL_VAR int V133 tmp93 u:1 NA (last use) REG NA DefList: { N3321.t4293. PUTARG_REG } N3325 (???,???) [004294] ----------- * PUTARG_REG int REG x1 Last use of V133 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB235 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB235 regmask=[x1] minReg=1 last fixed wt=1200.00> Interval 390: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB235 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N3321.t4293. PUTARG_REG; N3325.t4294. PUTARG_REG } N3327 ( 2, 8) [003107] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn REG NA $53 Interval 391: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB235 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3321.t4293. PUTARG_REG; N3325.t4294. PUTARG_REG; N3327.t3107. CNS_INT } N3329 (???,???) [004295] ----------- * PUTARG_REG long REG x11 BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 392: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB235 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N3321.t4293. PUTARG_REG; N3325.t4294. PUTARG_REG; N3329.t4295. PUTARG_REG } N3331 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 393: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB235 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB235 regmask=[x0] minReg=1 wt=200.00> BB235 regmask=[x0] minReg=1 last fixed wt=200.00> BB235 regmask=[x1] minReg=1 wt=200.00> BB235 regmask=[x1] minReg=1 last fixed wt=200.00> BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB235 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB235 regmask=[x0] minReg=1 wt=200.00> BB235 regmask=[x1] minReg=1 wt=200.00> BB235 regmask=[x2] minReg=1 wt=200.00> BB235 regmask=[x3] minReg=1 wt=200.00> BB235 regmask=[x4] minReg=1 wt=200.00> BB235 regmask=[x5] minReg=1 wt=200.00> BB235 regmask=[x6] minReg=1 wt=200.00> BB235 regmask=[x7] minReg=1 wt=200.00> BB235 regmask=[x8] minReg=1 wt=200.00> BB235 regmask=[x9] minReg=1 wt=200.00> BB235 regmask=[x10] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x12] minReg=1 wt=200.00> BB235 regmask=[x13] minReg=1 wt=200.00> BB235 regmask=[x14] minReg=1 wt=200.00> BB235 regmask=[x15] minReg=1 wt=200.00> BB235 regmask=[xip0] minReg=1 wt=200.00> BB235 regmask=[xip1] minReg=1 wt=200.00> BB235 regmask=[lr] minReg=1 wt=200.00> CHECKING LAST USES for BB235, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V133} def: {} NEW BLOCK BB239 Setting BB232 as the predecessor for determining incoming variable registers of BB239 DefList: { } N3335 (???,???) [004143] ----------- * IL_OFFSET void INLRT @ 0x788[E-] REG NA DefList: { } N3337 ( 1, 1) [000372] ----------- * LCL_VAR int V16 loc12 u:6 NA REG NA $b08 DefList: { } N3339 ( 1, 1) [003706] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N3341 ( 3, 3) [000377] J------N--- * GE void REG NA $c42 LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N3343 ( 5, 5) [000378] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB239, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V16 V179} def: {} NEW BLOCK BB240 Setting BB112 as the predecessor for determining incoming variable registers of BB240 DefList: { } N3347 (???,???) [004144] ----------- * IL_OFFSET void INLRT @ 0x793[E-] REG NA DefList: { } N3349 ( 1, 1) [000379] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N3351 ( 1, 1) [000380] ----------- * LCL_VAR int V16 loc12 u:6 NA REG NA $b08 DefList: { } N3353 ( 2, 3) [000381] -c--------- * CAST long <- int REG NA $ad1 Contained DefList: { } N3355 ( 1, 2) [000383] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N3357 ( 4, 6) [000384] -c--------- * BFIZ long REG NA Contained DefList: { } N3359 ( 6, 8) [000385] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N3361 ( 9, 10) [000386] ---XG------ * IND ushort REG NA LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 394: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> DefList: { N3361.t386. IND } N3363 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 NA REG NA BB240 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Assigning related to STORE_LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> DefList: { } N3365 ( 1, 1) [003642] ----------- * LCL_VAR int V173 cse2 u:1 NA REG NA DefList: { } N3367 ( 1, 2) [000387] -c--------- * CNS_INT int 48 REG NA $d8 Contained DefList: { } N3369 ( 12, 14) [000388] J--XG--N--- * EQ void REG NA LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> DefList: { } N3371 ( 14, 16) [000389] ---XG------ * JTRUE void REG NA $c02 CHECKING LAST USES for BB240, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V173 V179} ============================== use: {V16 V34} def: {V173} NEW BLOCK BB236 Setting BB240 as the predecessor for determining incoming variable registers of BB236 DefList: { } N3375 (???,???) [004134] ----------- * IL_OFFSET void INLRT @ 0x774[E-] REG NA DefList: { } N3377 ( 1, 1) [000392] ----------- * LCL_VAR int V16 loc12 u:6 NA (last use) REG NA $b08 DefList: { } N3379 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 NA REG NA LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> DefList: { } N3381 (???,???) [004135] ----------- * IL_OFFSET void INLRT @ 0x774[E-] REG NA DefList: { } N3383 ( 1, 1) [000393] ----------- * LCL_VAR int V53 tmp13 u:1 NA (last use) REG NA $b08 DefList: { } N3385 ( 1, 2) [000394] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3387 ( 3, 4) [000395] ----------- * ADD int REG NA $c47 LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> Interval 395: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3387.t395. ADD } N3389 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 NA REG NA BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N3391 ( 1, 1) [003639] ----------- * LCL_VAR int V173 cse2 u:1 NA (last use) REG NA DefList: { } N3393 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 NA REG NA LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> Assigning related to STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N3395 (???,???) [004136] ----------- * IL_OFFSET void INL66 @ 0x000[E-] <- INLRT @ ??? REG NA DefList: { } N3397 ( 1, 1) [000390] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3399 ( 3, 4) [003109] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3401 ( 4, 3) [002442] n---GO----- * IND int REG NA LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 396: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3401.t2442. IND } N3403 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 NA REG NA BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> DefList: { } N3405 (???,???) [004137] ----------- * IL_OFFSET void INL66 @ 0x007[E-] <- INLRT @ ??? REG NA DefList: { } N3407 ( 1, 1) [002445] ----------- * LCL_VAR int V136 tmp96 u:1 NA REG NA DefList: { } N3409 ( 1, 1) [002446] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3411 ( 3, 4) [003113] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N3413 ( 4, 3) [002484] n---GO----- * IND int REG NA LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 397: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3413.t2484. IND } N3415 ( 6, 5) [002450] N---GO-N-U- * GE void REG NA LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N3417 ( 8, 7) [002451] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB236, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144 V179} ============================== use: {V00 V16 V173} def: {V16 V53 V136 V137} NEW BLOCK BB237 Setting BB236 as the predecessor for determining incoming variable registers of BB237 DefList: { } N3421 (???,???) [004138] ----------- * IL_OFFSET void INL66 @ 0x015[E-] <- INLRT @ ??? REG NA DefList: { } N3423 ( 1, 1) [003117] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3425 ( 1, 2) [003118] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N3427 ( 3, 4) [003119] -----O----- * ADD byref REG NA $25c LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 398: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3427.t3119. ADD } N3429 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 NA REG NA BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N3431 ( 1, 1) [002457] ----------- * LCL_VAR int V136 tmp96 u:1 NA REG NA DefList: { } N3433 ( 1, 1) [002462] ----------- * LCL_VAR byref V138 tmp98 u:1 NA REG NA $25c DefList: { } N3435 ( 3, 4) [003122] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3437 ( 4, 3) [002463] n---GO----- * IND int REG NA LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 399: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3437.t2463. IND } N3439 ( 9, 11) [002464] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N3441 ( 1, 1) [002461] ----------- * LCL_VAR byref V138 tmp98 u:1 NA (last use) REG NA $25c DefList: { } N3443 ( 3, 2) [002468] n---GO----- * IND byref REG NA LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 400: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3443.t2468. IND } N3445 ( 1, 1) [002458] ----------- * LCL_VAR int V136 tmp96 u:1 NA REG NA DefList: { N3443.t2468. IND } N3447 ( 2, 3) [002465] -c-------U- * CAST long <- uint REG NA Contained DefList: { N3443.t2468. IND } N3449 ( 1, 2) [002466] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N3443.t2468. IND } N3451 ( 4, 6) [002467] -c--------- * BFIZ long REG NA Contained DefList: { N3443.t2468. IND } N3453 ( 8, 9) [002469] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N3443.t2468. IND } N3455 ( 1, 1) [002471] ----------- * LCL_VAR int V137 tmp97 u:1 NA (last use) REG NA DefList: { N3443.t2468. IND } N3457 (???,???) [004139] -A-XGO----- * STOREIND short REG NA BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N3459 (???,???) [004140] ----------- * IL_OFFSET void INL66 @ 0x023[E-] <- INLRT @ ??? REG NA DefList: { } N3461 ( 1, 1) [002475] ----------- * LCL_VAR int V136 tmp96 u:1 NA (last use) REG NA DefList: { } N3463 ( 1, 2) [002476] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3465 ( 3, 4) [002477] ----------- * ADD int REG NA LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> Interval 401: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3465.t2477. ADD } N3467 ( 1, 1) [002474] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N3465.t2477. ADD } N3469 ( 3, 4) [003125] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N3465.t2477. ADD } N3471 (???,???) [004141] -A--GO----- * STOREIND int REG NA LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB237, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V136 V137} def: {V138} NEW BLOCK BB238 Setting BB236 as the predecessor for determining incoming variable registers of BB238 DefList: { } N3475 (???,???) [004142] ----------- * IL_OFFSET void INL66 @ 0x02D[E-] <- INLRT @ ??? REG NA DefList: { } N3477 ( 1, 1) [002452] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3479 (???,???) [004296] ----------- * PUTARG_REG byref REG x0 BB238 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB238 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 402: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB238 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x0] minReg=1 fixed wt=3200.00> Assigning related to DefList: { N3479.t4296. PUTARG_REG } N3481 ( 1, 1) [002453] ----------- * LCL_VAR int V137 tmp97 u:1 NA (last use) REG NA DefList: { N3479.t4296. PUTARG_REG } N3483 (???,???) [004297] ----------- * PUTARG_REG int REG x1 Last use of V137 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB238 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB238 regmask=[x1] minReg=1 last fixed wt=4800.00> Interval 403: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB238 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x1] minReg=1 fixed wt=3200.00> DefList: { N3479.t4296. PUTARG_REG; N3483.t4297. PUTARG_REG } N3485 ( 2, 8) [003126] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn REG NA $53 Interval 404: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB238 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3479.t4296. PUTARG_REG; N3483.t4297. PUTARG_REG; N3485.t3126. CNS_INT } N3487 (???,???) [004298] ----------- * PUTARG_REG long REG x11 BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 last fixed wt=800.00> Interval 405: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB238 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x11] minReg=1 fixed wt=3200.00> DefList: { N3479.t4296. PUTARG_REG; N3483.t4297. PUTARG_REG; N3487.t4298. PUTARG_REG } N3489 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 406: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB238 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB238 regmask=[x0] minReg=1 wt=800.00> BB238 regmask=[x0] minReg=1 last fixed wt=800.00> BB238 regmask=[x1] minReg=1 wt=800.00> BB238 regmask=[x1] minReg=1 last fixed wt=800.00> BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB238 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB238 regmask=[x0] minReg=1 wt=800.00> BB238 regmask=[x1] minReg=1 wt=800.00> BB238 regmask=[x2] minReg=1 wt=800.00> BB238 regmask=[x3] minReg=1 wt=800.00> BB238 regmask=[x4] minReg=1 wt=800.00> BB238 regmask=[x5] minReg=1 wt=800.00> BB238 regmask=[x6] minReg=1 wt=800.00> BB238 regmask=[x7] minReg=1 wt=800.00> BB238 regmask=[x8] minReg=1 wt=800.00> BB238 regmask=[x9] minReg=1 wt=800.00> BB238 regmask=[x10] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x12] minReg=1 wt=800.00> BB238 regmask=[x13] minReg=1 wt=800.00> BB238 regmask=[x14] minReg=1 wt=800.00> BB238 regmask=[x15] minReg=1 wt=800.00> BB238 regmask=[xip0] minReg=1 wt=800.00> BB238 regmask=[xip1] minReg=1 wt=800.00> BB238 regmask=[lr] minReg=1 wt=800.00> CHECKING LAST USES for BB238, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V137} def: {} NEW BLOCK BB241 Setting BB240 as the predecessor for determining incoming variable registers of BB241 CHECKING LAST USES for BB241, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {} def: {} NEW BLOCK BB242 Setting BB140 as the predecessor for determining incoming variable registers of BB242 DefList: { } N3495 (???,???) [004145] ----------- * IL_OFFSET void INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] REG NA DefList: { } N3497 ( 1, 1) [000590] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3499 ( 3, 4) [003128] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3501 ( 4, 3) [002492] ---XG------ * IND int REG NA LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 407: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3501.t2492. IND } N3503 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 NA REG NA BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N3505 (???,???) [004146] ----------- * IL_OFFSET void INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] REG NA DefList: { } N3507 ( 1, 1) [002495] ----------- * LCL_VAR int V140 tmp100 u:1 NA REG NA DefList: { } N3509 ( 1, 1) [002496] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3511 ( 3, 4) [003132] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N3513 ( 4, 3) [002531] n---GO----- * IND int REG NA LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 408: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3513.t2531. IND } N3515 ( 6, 5) [002500] N---GO-N-U- * GE void REG NA LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N3517 ( 8, 7) [002501] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB242, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144 V179} ============================== use: {V00} def: {V140} NEW BLOCK BB243 Setting BB242 as the predecessor for determining incoming variable registers of BB243 DefList: { } N3521 (???,???) [004147] ----------- * IL_OFFSET void INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] REG NA DefList: { } N3523 ( 1, 1) [003136] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3525 ( 1, 2) [003137] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N3527 ( 3, 4) [003138] -----O----- * ADD byref REG NA $25c LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 409: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3527.t3138. ADD } N3529 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 NA REG NA BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N3531 (???,???) [004148] ----------- * IL_OFFSET void INL69 @ ??? <- INLRT @ 0x7A2[E-] REG NA DefList: { } N3533 ( 1, 1) [002506] ----------- * LCL_VAR int V140 tmp100 u:1 NA REG NA DefList: { } N3535 ( 1, 1) [002511] ----------- * LCL_VAR byref V141 tmp101 u:1 NA REG NA $25c DefList: { } N3537 ( 3, 4) [003141] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3539 ( 4, 3) [002512] n---GO----- * IND int REG NA LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 410: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3539.t2512. IND } N3541 ( 9, 11) [002513] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N3543 ( 1, 1) [002510] ----------- * LCL_VAR byref V141 tmp101 u:1 NA (last use) REG NA $25c DefList: { } N3545 ( 3, 2) [002517] n---GO----- * IND byref REG NA LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 411: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3545.t2517. IND } N3547 ( 1, 1) [002507] ----------- * LCL_VAR int V140 tmp100 u:1 NA REG NA DefList: { N3545.t2517. IND } N3549 ( 2, 3) [002514] -c-------U- * CAST long <- uint REG NA Contained DefList: { N3545.t2517. IND } N3551 ( 1, 2) [002515] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N3545.t2517. IND } N3553 ( 4, 6) [002516] -c--------- * BFIZ long REG NA Contained DefList: { N3545.t2517. IND } N3555 ( 8, 9) [002518] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N3545.t2517. IND } N3557 ( 1, 1) [002520] ----------- * LCL_VAR int V18 loc14 u:1 NA (last use) REG NA DefList: { N3545.t2517. IND } N3559 (???,???) [004149] -A-XGO----- * STOREIND short REG NA BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N3561 (???,???) [004150] ----------- * IL_OFFSET void INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] REG NA DefList: { } N3563 ( 1, 1) [002524] ----------- * LCL_VAR int V140 tmp100 u:1 NA (last use) REG NA DefList: { } N3565 ( 1, 2) [002525] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3567 ( 3, 4) [002526] ----------- * ADD int REG NA LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 412: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3567.t2526. ADD } N3569 ( 1, 1) [002523] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N3567.t2526. ADD } N3571 ( 3, 4) [003144] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N3567.t2526. ADD } N3573 (???,???) [004151] -A--GO----- * STOREIND int REG NA LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB243, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V18 V140} def: {V141} NEW BLOCK BB244 Setting BB215 as the predecessor for determining incoming variable registers of BB244 DefList: { } N3577 (???,???) [004152] ----------- * IL_OFFSET void INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] REG NA DefList: { } N3579 ( 1, 1) [002502] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N3581 (???,???) [004299] ----------- * PUTARG_REG byref REG x0 BB244 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB244 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 413: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB244 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N3581.t4299. PUTARG_REG } N3583 ( 1, 1) [000591] ----------- * LCL_VAR int V18 loc14 u:1 NA (last use) REG NA DefList: { N3581.t4299. PUTARG_REG } N3585 (???,???) [004300] ----------- * PUTARG_REG int REG x1 Last use of V18 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB244 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB244 regmask=[x1] minReg=1 last fixed wt=23800.00> Interval 414: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB244 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N3581.t4299. PUTARG_REG; N3585.t4300. PUTARG_REG } N3587 ( 2, 8) [003145] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn REG NA $53 Interval 415: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3581.t4299. PUTARG_REG; N3585.t4300. PUTARG_REG; N3587.t3145. CNS_INT } N3589 (???,???) [004301] ----------- * PUTARG_REG long REG x11 BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 416: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB244 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N3581.t4299. PUTARG_REG; N3585.t4300. PUTARG_REG; N3589.t4301. PUTARG_REG } N3591 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 417: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB244 regmask=[x0] minReg=1 wt=200.00> BB244 regmask=[x0] minReg=1 last fixed wt=200.00> BB244 regmask=[x1] minReg=1 wt=200.00> BB244 regmask=[x1] minReg=1 last fixed wt=200.00> BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB244 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB244 regmask=[x0] minReg=1 wt=200.00> BB244 regmask=[x1] minReg=1 wt=200.00> BB244 regmask=[x2] minReg=1 wt=200.00> BB244 regmask=[x3] minReg=1 wt=200.00> BB244 regmask=[x4] minReg=1 wt=200.00> BB244 regmask=[x5] minReg=1 wt=200.00> BB244 regmask=[x6] minReg=1 wt=200.00> BB244 regmask=[x7] minReg=1 wt=200.00> BB244 regmask=[x8] minReg=1 wt=200.00> BB244 regmask=[x9] minReg=1 wt=200.00> BB244 regmask=[x10] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x12] minReg=1 wt=200.00> BB244 regmask=[x13] minReg=1 wt=200.00> BB244 regmask=[x14] minReg=1 wt=200.00> BB244 regmask=[x15] minReg=1 wt=200.00> BB244 regmask=[xip0] minReg=1 wt=200.00> BB244 regmask=[xip1] minReg=1 wt=200.00> BB244 regmask=[lr] minReg=1 wt=200.00> Exposed uses: BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> CHECKING LAST USES for BB244, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V18} def: {} NEW BLOCK BB248 Setting BB245 as the predecessor for determining incoming variable registers of BB248 DefList: { } N3595 (???,???) [003939] ----------- * IL_OFFSET void INLRT @ 0x7D1[E-] REG NA DefList: { } N3597 ( 1, 2) [000212] -c--------- * CNS_INT long 0 REG NA $205 Contained DefList: { } N3599 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 NA REG NA DefList: { } N3601 (???,???) [003940] ----------- * IL_OFFSET void INLRT @ 0x7D5[E-] REG NA DefList: { } N3603 ( 1, 1) [000215] ----------- * LCL_VAR byref V01 arg1 u:1 NA REG NA $101 DefList: { } N3605 ( 3, 4) [003148] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N3607 ( 5, 4) [000216] n---GO----- * IND bool REG NA LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 418: bool RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB248 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N3607.t216. IND } N3609 ( 1, 2) [000217] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N3607.t216. IND } N3611 ( 10, 7) [000218] -c--GO-N--- * EQ int REG NA Contained DefList: { N3607.t216. IND } N3613 ( 1, 1) [000221] ----------- * LCL_VAR int V15 loc11 u:2 NA (last use) REG NA $283 DefList: { N3607.t216. IND } N3615 ( 1, 2) [000222] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N3607.t216. IND } N3617 ( 6, 4) [000223] -c-----N--- * NE int REG NA $733 Contained DefList: { N3607.t216. IND } N3619 ( 17, 12) [003764] Jc--GO-N--- * AND void REG NA Contained DefList: { N3607.t216. IND } N3621 ( 19, 14) [000219] ----GO----- * JTRUE void REG NA $301 BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> CHECKING LAST USES for BB248, liveout={V00 V01 V03} ============================== use: {V01 V15} def: {} NEW BLOCK BB249 Setting BB248 as the predecessor for determining incoming variable registers of BB249 DefList: { } N3625 (???,???) [003941] ----------- * IL_OFFSET void INLRT @ 0x7DD[E-] REG NA DefList: { } N3627 (???,???) [003942] ----------- * IL_OFFSET void INLRT @ 0x7E1[E-] REG NA DefList: { } N3629 ( 1, 1) [000225] ----------- * LCL_VAR byref V01 arg1 u:1 NA (last use) REG NA $101 DefList: { } N3631 ( 3, 4) [003150] -c--------- * LEA(b+4) byref REG NA Contained DefList: { } N3633 ( 4, 3) [000226] n---GO----- * IND int REG NA LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> Interval 419: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N3633.t226. IND } N3635 ( 1, 2) [000227] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N3633.t226. IND } N3637 ( 9, 6) [000228] ----GO-N--- * NE int REG NA BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Interval 420: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N3637.t228. NE } N3639 ( 1, 1) [000230] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N3637.t228. NE } N3641 ( 3, 4) [003152] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N3637.t228. NE } N3643 ( 4, 3) [002539] ---XG------ * IND int REG NA LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 421: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N3637.t228. NE; N3643.t2539. IND } N3645 ( 1, 2) [000233] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N3637.t228. NE; N3643.t2539. IND } N3647 ( 9, 6) [000234] ---XG--N--- * LE int REG NA BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Interval 422: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] LE BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N3637.t228. NE; N3647.t234. LE } N3649 ( 19, 13) [003766] J--XGO-N--- * AND int REG NA BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> Interval 423: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] AND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N3649.t3766. AND } N3651 ( 21, 15) [000229] ---XGO----- * JTRUE void REG NA $301 BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> CHECKING LAST USES for BB249, liveout={V00 V03} ============================== use: {V00 V01} def: {} NEW BLOCK BB251 Setting BB249 as the predecessor for determining incoming variable registers of BB251 DefList: { } N3655 (???,???) [003943] ----------- * IL_OFFSET void INLRT @ 0x7E9[E-] REG NA DefList: { } N3657 (???,???) [003944] ----------- * IL_OFFSET void INLRT @ 0x7F2[E-] REG NA DefList: { } N3659 ( 1, 1) [000238] ----------- * LCL_VAR ref V03 arg3 u:1 NA (last use) REG NA $180 DefList: { } N3661 ( 3, 4) [003155] -c--------- * LEA(b+40) byref REG NA Contained DefList: { } N3663 ( 4, 3) [002541] ---XG------ * IND ref REG NA LCL_VAR BB251 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 424: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB251 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N3663.t2541. IND } N3665 (???,???) [004227] ---XG------ * PUTARG_REG ref REG x2 BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 last fixed wt=50.00> Interval 425: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB251 regmask=[x2] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x2] minReg=1 fixed wt=200.00> DefList: { N3665.t4227. PUTARG_REG } N3667 ( 1, 1) [000236] ----------- * LCL_VAR byref V00 arg0 u:1 NA (last use) REG NA $100 DefList: { N3665.t4227. PUTARG_REG } N3669 (???,???) [004228] ----------- * PUTARG_REG byref REG x0 Last use of V00 between PUTARG and CALL. Removing occupied arg regs from preferences: [x2] BB251 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB251 regmask=[x0] minReg=1 last fixed wt=26550.00> Interval 426: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB251 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x0] minReg=1 fixed wt=200.00> DefList: { N3665.t4227. PUTARG_REG; N3669.t4228. PUTARG_REG } N3671 ( 2, 8) [003153] H---------- * CNS_INT(h) long 0x4000000000540210 ftn REG NA $51 Interval 427: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB251 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N3665.t4227. PUTARG_REG; N3669.t4228. PUTARG_REG; N3671.t3153. CNS_INT } N3673 (???,???) [004229] ----------- * PUTARG_REG long REG x11 BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 last fixed wt=50.00> Interval 428: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB251 regmask=[x11] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x11] minReg=1 fixed wt=200.00> DefList: { N3665.t4227. PUTARG_REG; N3669.t4228. PUTARG_REG; N3673.t4229. PUTARG_REG } N3675 ( 1, 2) [000237] ----------- * CNS_INT int 0 REG NA $c0 Interval 429: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB251 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> DefList: { N3665.t4227. PUTARG_REG; N3669.t4228. PUTARG_REG; N3673.t4229. PUTARG_REG; N3675.t237. CNS_INT } N3677 (???,???) [004230] ----------- * PUTARG_REG int REG x1 BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 last fixed wt=50.00> Interval 430: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB251 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x1] minReg=1 fixed wt=200.00> DefList: { N3665.t4227. PUTARG_REG; N3669.t4228. PUTARG_REG; N3673.t4229. PUTARG_REG; N3677.t4230. PUTARG_REG } N3679 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 431: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB251 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 last fixed wt=50.00> BB251 regmask=[x0] minReg=1 wt=50.00> BB251 regmask=[x0] minReg=1 last fixed wt=50.00> BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 last fixed wt=50.00> BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 last fixed wt=50.00> CALL BB251 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB251 regmask=[x0] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x3] minReg=1 wt=50.00> BB251 regmask=[x4] minReg=1 wt=50.00> BB251 regmask=[x5] minReg=1 wt=50.00> BB251 regmask=[x6] minReg=1 wt=50.00> BB251 regmask=[x7] minReg=1 wt=50.00> BB251 regmask=[x8] minReg=1 wt=50.00> BB251 regmask=[x9] minReg=1 wt=50.00> BB251 regmask=[x10] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x12] minReg=1 wt=50.00> BB251 regmask=[x13] minReg=1 wt=50.00> BB251 regmask=[x14] minReg=1 wt=50.00> BB251 regmask=[x15] minReg=1 wt=50.00> BB251 regmask=[xip0] minReg=1 wt=50.00> BB251 regmask=[xip1] minReg=1 wt=50.00> BB251 regmask=[lr] minReg=1 wt=50.00> CHECKING LAST USES for BB251, liveout={} ============================== use: {V00 V03} def: {} NEW BLOCK BB253 Setting BB248 as the predecessor for determining incoming variable registers of BB253 DefList: { } N3683 (???,???) [003945] ----------- * IL_OFFSET void INLRT @ 0x7FF[E-] REG NA DefList: { } N3685 ( 0, 0) [000220] ----------- * RETURN void REG NA $VN.Void CHECKING LAST USES for BB253, liveout={} ============================== use: {} def: {} NEW BLOCK BB255 Setting BB09 as the predecessor for determining incoming variable registers of BB255 DefList: { } N3689 (???,???) [004198] ----------- * LCL_VAR int V182 rat0 NA (last use) REG NA DefList: { } N3691 (???,???) [004199] ---------U- * CAST long <- ulong <- uint REG NA LCL_VAR BB255 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 432: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3691.t4199. CAST } N3693 (???,???) [004200] ----------- * JMPTABLE long REG NA Interval 433: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] JMPTABLE BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3691.t4199. CAST; N3693.t4200. JMPTABLE } N3695 (???,???) [004201] ----------- * SWITCH_TABLE void REG NA Interval 434: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SWITCH_TABLE BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB255 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB255 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB255, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} ============================== use: {V182} def: {} NEW BLOCK BB17 Setting BB255 as the predecessor for determining incoming variable registers of BB17 DefList: { } N3699 (???,???) [003805] ----------- * IL_OFFSET void INLRT @ 0x0CF[E-] REG NA DefList: { } N3701 ( 1, 1) [001430] ----------- * LCL_VAR int V04 loc0 u:2 NA (last use) REG NA $28a DefList: { } N3703 ( 1, 2) [001431] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3705 ( 3, 4) [001432] ----------- * ADD int REG NA $68f LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> Interval 435: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3705.t1432. ADD } N3707 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 NA REG NA BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> CHECKING LAST USES for BB17, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V04} def: {V04} NEW BLOCK BB30 Setting BB255 as the predecessor for determining incoming variable registers of BB30 DefList: { } N3711 (???,???) [003820] ----------- * IL_OFFSET void INLRT @ 0x12C[E-] REG NA DefList: { } N3713 ( 1, 1) [001425] ----------- * LCL_VAR int V13 loc9 u:2 NA (last use) REG NA $289 DefList: { } N3715 ( 1, 2) [001426] -c--------- * CNS_INT int 2 REG NA $c2 Contained DefList: { } N3717 ( 3, 4) [001427] ----------- * ADD int REG NA $695 LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 436: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB30 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3717.t1427. ADD } N3719 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 NA REG NA BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> CHECKING LAST USES for BB30, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V13} def: {V13} NEW BLOCK BB31 Setting BB255 as the predecessor for determining incoming variable registers of BB31 DefList: { } N3723 (???,???) [003821] ----------- * IL_OFFSET void INLRT @ 0x142[E-] REG NA DefList: { } N3725 ( 1, 1) [001435] ----------- * LCL_VAR int V16 loc12 u:21 NA REG NA $2b1 DefList: { } N3727 ( 1, 1) [003693] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N3729 ( 6, 3) [001440] -c-----N--- * GE int REG NA $8b7 Contained DefList: { } N3731 ( 1, 1) [001442] ----------- * LCL_VAR long V22 loc18 u:1 NA REG NA $3c4 DefList: { } N3733 ( 1, 1) [001443] ----------- * LCL_VAR int V16 loc12 u:21 NA REG NA $2b1 DefList: { } N3735 ( 2, 3) [001444] -c--------- * CAST long <- int REG NA $3de Contained DefList: { } N3737 ( 1, 2) [001446] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N3739 ( 4, 6) [001447] -c--------- * BFIZ long REG NA Contained DefList: { } N3741 ( 6, 8) [001448] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N3743 ( 9, 10) [001449] ---XG------ * IND ushort REG NA LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=18400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 437: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> DefList: { N3743.t1449. IND } N3745 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 NA REG NA BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> Assigning related to STORE_LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=19200.00> DefList: { } N3747 ( 1, 1) [003626] ----------- * LCL_VAR int V171 cse0 u:1 NA REG NA DefList: { } N3749 ( 1, 2) [001450] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3751 ( 15, 14) [001451] -c-XG--N--- * EQ int REG NA Contained DefList: { } N3753 ( 22, 18) [003728] Jc-XG--N--- * AND void REG NA Contained DefList: { } N3755 ( 24, 20) [001441] ---XG------ * JTRUE void REG NA $VN.Void LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=19200.00> CHECKING LAST USES for BB31, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} ============================== use: {V16 V22 V179} def: {V171} NEW BLOCK BB32 Setting BB07 as the predecessor for determining incoming variable registers of BB32 Creating dummy definitions BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> Finished creating dummy definitions DefList: { } N3759 (???,???) [003822] ----------- * IL_OFFSET void INLRT @ 0x150[E-] REG NA DefList: { } N3761 (???,???) [003823] ----------- * IL_OFFSET void INLRT @ 0x15E[E-] REG NA DefList: { } N3763 ( 1, 1) [001454] ----------- * LCL_VAR int V16 loc12 u:21 NA (last use) REG NA $2b1 DefList: { } N3765 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 NA REG NA LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> DefList: { } N3767 (???,???) [003824] ----------- * IL_OFFSET void INLRT @ 0x15E[E-] REG NA DefList: { } N3769 ( 1, 1) [001455] ----------- * LCL_VAR int V74 tmp34 u:1 NA (last use) REG NA $2b1 DefList: { } N3771 ( 1, 2) [001456] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3773 ( 3, 4) [001457] ----------- * ADD int REG NA $8bc LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> Interval 438: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> DefList: { N3773.t1457. ADD } N3775 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 NA REG NA BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> Assigning related to STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N3777 ( 1, 1) [003628] ----------- * LCL_VAR int V171 cse0 u:1 NA (last use) REG NA DefList: { } N3779 ( 1, 1) [001469] ----------- * LCL_VAR int V18 loc14 u:5 NA REG NA DefList: { } N3781 ( 3, 3) [001470] N---G--N-U- * NE void REG NA LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=19200.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N3783 ( 5, 5) [001471] ----G------ * JTRUE void REG NA $876 Exposed uses: BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> CHECKING LAST USES for BB32, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} ============================== use: {V16 V18 V171} def: {V16 V74} NEW BLOCK BB34 Setting BB255 as the predecessor for determining incoming variable registers of BB34 CHECKING LAST USES for BB34, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {} def: {} NEW BLOCK BB256 Setting BB10 as the predecessor for determining incoming variable registers of BB256 DefList: { } N3789 (???,???) [004209] ----------- * LCL_VAR int V183 rat1 NA (last use) REG NA DefList: { } N3791 (???,???) [004210] ---------U- * CAST long <- ulong <- uint REG NA LCL_VAR BB256 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 439: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3791.t4210. CAST } N3793 (???,???) [004211] ----------- * JMPTABLE long REG NA Interval 440: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] JMPTABLE BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3791.t4210. CAST; N3793.t4211. JMPTABLE } N3795 (???,???) [004212] ----------- * SWITCH_TABLE void REG NA Interval 441: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SWITCH_TABLE BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB256 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB256 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB256, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V183} def: {} NEW BLOCK BB18 Setting BB256 as the predecessor for determining incoming variable registers of BB18 DefList: { } N3799 (???,???) [003806] ----------- * IL_OFFSET void INLRT @ 0x0D8[E-] REG NA DefList: { } N3801 ( 1, 1) [001373] ----------- * LCL_VAR int V06 loc2 u:2 NA REG NA $284 DefList: { } N3803 ( 1, 4) [001374] ----------- * CNS_INT int 0x7FFFFFFF REG NA $c9 Interval 442: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB18 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3803.t1374. CNS_INT } N3805 ( 3, 6) [001375] N------N-U- * NE void REG NA $68e LCL_VAR BB18 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> BB18 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N3807 ( 5, 8) [001376] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB18, liveout={V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V06} def: {} NEW BLOCK BB19 Setting BB18 as the predecessor for determining incoming variable registers of BB19 DefList: { } N3811 (???,???) [003807] ----------- * IL_OFFSET void INLRT @ 0x0E0[E-] REG NA DefList: { } N3813 ( 1, 1) [001385] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { } N3815 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 NA REG NA LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> CHECKING LAST USES for BB19, liveout={V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V04} def: {V06} NEW BLOCK BB20 Setting BB18 as the predecessor for determining incoming variable registers of BB20 DefList: { } N3819 (???,???) [003808] ----------- * IL_OFFSET void INLRT @ 0x0E2[E-] REG NA DefList: { } N3821 ( 1, 1) [001377] ----------- * LCL_VAR int V04 loc0 u:2 NA (last use) REG NA $28a DefList: { } N3823 ( 1, 2) [001378] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3825 ( 3, 4) [001379] ----------- * ADD int REG NA $68f LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> Interval 443: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3825.t1379. ADD } N3827 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 NA REG NA BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> DefList: { } N3829 (???,???) [003809] ----------- * IL_OFFSET void INLRT @ 0x0E6[E-] REG NA DefList: { } N3831 ( 1, 1) [001382] ----------- * LCL_VAR int V04 loc0 u:4 NA REG NA $68f DefList: { } N3833 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 NA REG NA LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> CHECKING LAST USES for BB20, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V04} def: {V04 V07} NEW BLOCK BB21 Setting BB256 as the predecessor for determining incoming variable registers of BB21 DefList: { } N3837 (???,???) [003810] ----------- * IL_OFFSET void INLRT @ 0x0ED[E-] REG NA DefList: { } N3839 ( 1, 1) [001388] ----------- * LCL_VAR int V05 loc1 u:2 NA REG NA $286 DefList: { } N3841 ( 1, 2) [001389] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3843 ( 3, 4) [001390] J------N--- * GE void REG NA $690 LCL_VAR BB21 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> DefList: { } N3845 ( 5, 6) [001391] ----------- * JTRUE void REG NA $VN.Void Exposed uses: BB21 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CHECKING LAST USES for BB21, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V05} def: {} NEW BLOCK BB22 Setting BB07 as the predecessor for determining incoming variable registers of BB22 DefList: { } N3849 (???,???) [003811] ----------- * IL_OFFSET void INLRT @ 0x0F4[E-] REG NA DefList: { } N3851 ( 1, 1) [001392] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { } N3853 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 NA REG NA LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> CHECKING LAST USES for BB22, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V04} def: {V05} NEW BLOCK BB23 Setting BB256 as the predecessor for determining incoming variable registers of BB23 DefList: { } N3857 (???,???) [003812] ----------- * IL_OFFSET void INLRT @ 0x0FB[E-] REG NA DefList: { } N3859 ( 1, 1) [001395] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { } N3861 ( 1, 2) [001396] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3863 ( 6, 4) [001397] -c-----N--- * LE int REG NA $691 Contained DefList: { } N3865 ( 1, 1) [001399] ----------- * LCL_VAR int V05 loc1 u:2 NA REG NA $286 DefList: { } N3867 ( 1, 2) [001400] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3869 ( 6, 4) [001401] -c-----N--- * GE int REG NA $690 Contained DefList: { } N3871 ( 13, 9) [003726] Jc-----N--- * AND void REG NA Contained DefList: { } N3873 ( 15, 11) [001398] ----------- * JTRUE void REG NA $VN.Void LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> CHECKING LAST USES for BB23, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V04 V05} def: {} NEW BLOCK BB24 Setting BB07 as the predecessor for determining incoming variable registers of BB24 DefList: { } N3877 (???,???) [003813] ----------- * IL_OFFSET void INLRT @ 0x102[E-] REG NA DefList: { } N3879 (???,???) [003814] ----------- * IL_OFFSET void INLRT @ 0x109[E-] REG NA DefList: { } N3881 ( 1, 1) [001403] ----------- * LCL_VAR int V10 loc6 u:2 NA REG NA $287 DefList: { } N3883 ( 1, 2) [001404] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3885 ( 3, 4) [001405] J------N--- * LT void REG NA $692 LCL_VAR BB24 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N3887 ( 5, 6) [001406] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB24, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V10} def: {} NEW BLOCK BB26 Setting BB24 as the predecessor for determining incoming variable registers of BB26 DefList: { } N3891 (???,???) [003815] ----------- * IL_OFFSET void INLRT @ 0x10E[E-] REG NA DefList: { } N3893 ( 1, 1) [001413] ----------- * LCL_VAR int V10 loc6 u:2 NA REG NA $287 DefList: { } N3895 ( 1, 1) [001414] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { } N3897 ( 3, 3) [001415] N------N-U- * NE void REG NA $693 LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> DefList: { } N3899 ( 5, 5) [001416] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB26, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V04 V10} def: {} NEW BLOCK BB27 Setting BB26 as the predecessor for determining incoming variable registers of BB27 DefList: { } N3903 (???,???) [003816] ----------- * IL_OFFSET void INLRT @ 0x113[E-] REG NA DefList: { } N3905 ( 1, 1) [001420] ----------- * LCL_VAR int V11 loc7 u:3 NA (last use) REG NA $288 DefList: { } N3907 ( 1, 2) [001421] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3909 ( 3, 4) [001422] ----------- * ADD int REG NA $694 LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> Interval 444: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3909.t1422. ADD } N3911 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 NA REG NA BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> Exposed uses: BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CHECKING LAST USES for BB27, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V11} def: {V11} NEW BLOCK BB28 Setting BB26 as the predecessor for determining incoming variable registers of BB28 DefList: { } N3915 (???,???) [003817] ----------- * IL_OFFSET void INLRT @ 0x11E[E-] REG NA DefList: { } N3917 ( 1, 2) [002612] ----------- * CNS_INT int 1 REG NA $c1 Interval 445: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB28 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3917.t2612. CNS_INT } N3919 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 NA REG NA BB28 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB28 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2900.00> CHECKING LAST USES for BB28, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {} def: {V12} NEW BLOCK BB29 Setting BB24 as the predecessor for determining incoming variable registers of BB29 DefList: { } N3923 (???,???) [003818] ----------- * IL_OFFSET void INLRT @ 0x121[E-] REG NA DefList: { } N3925 ( 1, 1) [001407] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { } N3927 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 NA REG NA LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N3929 (???,???) [003819] ----------- * IL_OFFSET void INLRT @ 0x124[E-] REG NA DefList: { } N3931 ( 1, 2) [001410] ----------- * CNS_INT int 1 REG NA $c1 Interval 446: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N3931.t1410. CNS_INT } N3933 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 NA REG NA BB29 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> Exposed uses: BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CHECKING LAST USES for BB29, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} ============================== use: {V04} def: {V10 V11} NEW BLOCK BB257 Setting BB137 as the predecessor for determining incoming variable registers of BB257 DefList: { } N3937 (???,???) [004247] ----------- * LCL_VAR int V184 rat2 NA (last use) REG NA DefList: { } N3939 (???,???) [004248] ---------U- * CAST long <- ulong <- uint REG NA LCL_VAR BB257 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 447: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3939.t4248. CAST } N3941 (???,???) [004249] ----------- * JMPTABLE long REG NA Interval 448: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] JMPTABLE BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3939.t4248. CAST; N3941.t4249. JMPTABLE } N3943 (???,???) [004250] ----------- * SWITCH_TABLE void REG NA Interval 449: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SWITCH_TABLE BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB257 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB257 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB257, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V184} def: {} NEW BLOCK BB145 Setting BB257 as the predecessor for determining incoming variable registers of BB145 DefList: { } N3947 (???,???) [003986] ----------- * IL_OFFSET void INLRT @ 0x4E9[E-] REG NA DefList: { } N3949 ( 1, 1) [000639] ----------- * LCL_VAR int V14 loc10 u:3 NA REG NA $2b4 DefList: { } N3951 ( 1, 2) [000640] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3953 ( 3, 4) [000641] J------N--- * GE void REG NA $9ff LCL_VAR BB145 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N3955 ( 5, 6) [000642] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB145, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V14} def: {} NEW BLOCK BB146 Setting BB145 as the predecessor for determining incoming variable registers of BB146 DefList: { } N3959 (???,???) [003987] ----------- * IL_OFFSET void INLRT @ 0x4EE[E-] REG NA DefList: { } N3961 ( 1, 1) [000731] ----------- * LCL_VAR int V14 loc10 u:3 NA (last use) REG NA $2b4 DefList: { } N3963 ( 1, 2) [000732] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N3965 ( 3, 4) [000733] ----------- * ADD int REG NA $a88 LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> Interval 450: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3965.t733. ADD } N3967 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 NA REG NA BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> DefList: { } N3969 (???,???) [003988] ----------- * IL_OFFSET void INLRT @ 0x4F4[E-] REG NA DefList: { } N3971 ( 1, 1) [000736] ----------- * LCL_VAR int V08 loc4 u:3 NA REG NA $2b5 DefList: { } N3973 ( 1, 1) [000737] ----------- * LCL_VAR int V06 loc2 u:3 NA REG NA $292 DefList: { } N3975 ( 3, 3) [000738] J------N--- * LE void REG NA $a89 LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> DefList: { } N3977 ( 5, 5) [000739] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB146, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V06 V08 V14} def: {V14} NEW BLOCK BB147 Setting BB146 as the predecessor for determining incoming variable registers of BB147 DefList: { } N3981 (???,???) [003989] ----------- * IL_OFFSET void INLRT @ 0x4F9[E-] REG NA DefList: { } N3983 ( 1, 2) [000747] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N3985 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 NA REG NA STORE_LCL_VAR BB147 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> CHECKING LAST USES for BB147, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144 V179} ============================== use: {} def: {V58} NEW BLOCK BB148 Setting BB146 as the predecessor for determining incoming variable registers of BB148 DefList: { } N3989 (???,???) [003990] ----------- * IL_OFFSET void INLRT @ 0x4FC[E-] REG NA DefList: { } N3991 ( 1, 2) [000740] ----------- * CNS_INT int 48 REG NA $d8 Interval 451: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB148 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3991.t740. CNS_INT } N3993 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 NA REG NA BB148 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB148 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> CHECKING LAST USES for BB148, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144 V179} ============================== use: {} def: {V58} NEW BLOCK BB149 Setting BB147 as the predecessor for determining incoming variable registers of BB149 DefList: { } N3997 ( 1, 1) [000744] ----------- * LCL_VAR int V58 tmp18 u:1 NA (last use) REG NA $2bd DefList: { } N3999 ( 2, 3) [002850] ----------- * CAST int <- ushort <- int REG NA $a8a LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> Interval 452: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB149 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N3999.t2850. CAST } N4001 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 NA REG NA BB149 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> CHECKING LAST USES for BB149, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V58} def: {V18} NEW BLOCK BB150 Setting BB145 as the predecessor for determining incoming variable registers of BB150 DefList: { } N4005 (???,???) [003991] ----------- * IL_OFFSET void INLRT @ 0x502[E-] REG NA DefList: { } N4007 ( 1, 1) [000643] ----------- * LCL_VAR long V36 loc32 u:3 NA REG NA $901 DefList: { } N4009 ( 4, 3) [000644] ---XG------ * IND ubyte REG NA LCL_VAR BB150 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> Interval 453: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB150 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4009.t644. IND } N4011 ( 1, 2) [000645] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N4009.t644. IND } N4013 ( 6, 6) [000646] CNE---XG--N--- * JCMP void REG NA BB150 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB150, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V36} def: {} NEW BLOCK BB151 Setting BB150 as the predecessor for determining incoming variable registers of BB151 DefList: { } N4017 (???,???) [003992] ----------- * IL_OFFSET void INLRT @ 0x507[E-] REG NA DefList: { } N4019 ( 1, 1) [000719] ----------- * LCL_VAR int V08 loc4 u:3 NA REG NA $2b5 DefList: { } N4021 ( 1, 1) [000720] ----------- * LCL_VAR int V07 loc3 u:3 NA REG NA $293 DefList: { } N4023 ( 3, 3) [000721] J------N--- * GT void REG NA $a86 LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> DefList: { } N4025 ( 5, 5) [000722] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB151, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V07 V08} def: {} NEW BLOCK BB152 Setting BB151 as the predecessor for determining incoming variable registers of BB152 DefList: { } N4029 (???,???) [003993] ----------- * IL_OFFSET void INLRT @ 0x50C[E-] REG NA DefList: { } N4031 ( 1, 2) [000727] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N4033 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 NA REG NA STORE_LCL_VAR BB152 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB152, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} ============================== use: {} def: {V57} NEW BLOCK BB153 Setting BB151 as the predecessor for determining incoming variable registers of BB153 DefList: { } N4037 (???,???) [003994] ----------- * IL_OFFSET void INLRT @ 0x50F[E-] REG NA DefList: { } N4039 ( 1, 2) [000723] ----------- * CNS_INT int 48 REG NA $d8 Interval 454: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB153 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4039.t723. CNS_INT } N4041 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 NA REG NA BB153 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB153 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB153, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} ============================== use: {} def: {V57} NEW BLOCK BB154 Setting BB150 as the predecessor for determining incoming variable registers of BB154 DefList: { } N4045 (???,???) [003995] ----------- * IL_OFFSET void INLRT @ 0x513[E-] REG NA DefList: { } N4047 ( 1, 1) [000648] ----------- * LCL_VAR long V36 loc32 u:3 NA (last use) REG NA $901 DefList: { } N4049 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 NA REG NA LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N4051 (???,???) [003996] ----------- * IL_OFFSET void INLRT @ 0x513[E-] REG NA DefList: { } N4053 ( 1, 1) [000649] ----------- * LCL_VAR long V56 tmp16 u:1 NA REG NA $901 DefList: { } N4055 ( 1, 2) [000651] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N4057 ( 3, 4) [000652] ----------- * ADD long REG NA $3fb LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 455: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4057.t652. ADD } N4059 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 NA REG NA BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> DefList: { } N4061 ( 1, 1) [000657] ----------- * LCL_VAR long V56 tmp16 u:1 NA (last use) REG NA $901 DefList: { } N4063 ( 4, 3) [000658] ---XG------ * IND ubyte REG NA LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 456: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4063.t658. IND } N4065 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 NA REG NA BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB154, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} ============================== use: {V36} def: {V36 V56 V57} NEW BLOCK BB155 Setting BB152 as the predecessor for determining incoming variable registers of BB155 DefList: { } N4069 ( 1, 1) [000662] ----------- * LCL_VAR int V57 tmp17 u:1 NA (last use) REG NA $2bc DefList: { } N4071 ( 2, 3) [002851] ----------- * CAST int <- ushort <- int REG NA $a87 LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Interval 457: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB155 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4071.t2851. CAST } N4073 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 NA REG NA BB155 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> CHECKING LAST USES for BB155, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V57} def: {V18} NEW BLOCK BB156 Setting BB149 as the predecessor for determining incoming variable registers of BB156 DefList: { } N4077 (???,???) [003997] ----------- * IL_OFFSET void INLRT @ 0x51D[E-] REG NA DefList: { } N4079 ( 1, 1) [000665] ----------- * LCL_VAR int V18 loc14 u:2 NA REG NA $5c9 DefList: { } N4081 ( 1, 2) [000666] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N4083 ( 3, 4) [000667] CEQ-------N--- * JCMP void REG NA LCL_VAR BB156 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> CHECKING LAST USES for BB156, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V18} def: {} NEW BLOCK BB157 Setting BB156 as the predecessor for determining incoming variable registers of BB157 DefList: { } N4087 (???,???) [003998] ----------- * IL_OFFSET void INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] REG NA DefList: { } N4089 ( 1, 1) [000674] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4091 ( 3, 4) [002853] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4093 ( 4, 3) [001903] ---XG------ * IND int REG NA LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 458: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4093.t1903. IND } N4095 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 NA REG NA BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N4097 (???,???) [003999] ----------- * IL_OFFSET void INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] REG NA DefList: { } N4099 ( 1, 1) [001906] ----------- * LCL_VAR int V99 tmp59 u:1 NA REG NA DefList: { } N4101 ( 1, 1) [001907] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4103 ( 3, 4) [002857] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N4105 ( 4, 3) [001942] n---GO----- * IND int REG NA LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 459: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4105.t1942. IND } N4107 ( 6, 5) [001911] N---GO-N-U- * GE void REG NA LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N4109 ( 8, 7) [001912] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB157, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144 V179} ============================== use: {V00} def: {V99} NEW BLOCK BB158 Setting BB157 as the predecessor for determining incoming variable registers of BB158 DefList: { } N4113 (???,???) [004000] ----------- * IL_OFFSET void INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] REG NA DefList: { } N4115 ( 1, 1) [002861] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4117 ( 1, 2) [002862] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N4119 ( 3, 4) [002863] -----O----- * ADD byref REG NA $25c LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 460: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4119.t2863. ADD } N4121 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 NA REG NA BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N4123 (???,???) [004001] ----------- * IL_OFFSET void INL34 @ ??? <- INLRT @ 0x521[E-] REG NA DefList: { } N4125 ( 1, 1) [001917] ----------- * LCL_VAR int V99 tmp59 u:1 NA REG NA DefList: { } N4127 ( 1, 1) [001922] ----------- * LCL_VAR byref V100 tmp60 u:1 NA REG NA $25c DefList: { } N4129 ( 3, 4) [002866] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4131 ( 4, 3) [001923] n---GO----- * IND int REG NA LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 461: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4131.t1923. IND } N4133 ( 9, 11) [001924] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N4135 ( 1, 1) [001921] ----------- * LCL_VAR byref V100 tmp60 u:1 NA (last use) REG NA $25c DefList: { } N4137 ( 3, 2) [001928] n---GO----- * IND byref REG NA LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 462: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4137.t1928. IND } N4139 ( 1, 1) [001918] ----------- * LCL_VAR int V99 tmp59 u:1 NA REG NA DefList: { N4137.t1928. IND } N4141 ( 2, 3) [001925] -c-------U- * CAST long <- uint REG NA Contained DefList: { N4137.t1928. IND } N4143 ( 1, 2) [001926] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N4137.t1928. IND } N4145 ( 4, 6) [001927] -c--------- * BFIZ long REG NA Contained DefList: { N4137.t1928. IND } N4147 ( 8, 9) [001929] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N4137.t1928. IND } N4149 ( 1, 1) [001931] ----------- * LCL_VAR int V18 loc14 u:2 NA (last use) REG NA $5c9 DefList: { N4137.t1928. IND } N4151 (???,???) [004002] -A-XGO----- * STOREIND short REG NA BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N4153 (???,???) [004003] ----------- * IL_OFFSET void INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] REG NA DefList: { } N4155 ( 1, 1) [001935] ----------- * LCL_VAR int V99 tmp59 u:1 NA (last use) REG NA DefList: { } N4157 ( 1, 2) [001936] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N4159 ( 3, 4) [001937] ----------- * ADD int REG NA LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 463: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4159.t1937. ADD } N4161 ( 1, 1) [001934] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N4159.t1937. ADD } N4163 ( 3, 4) [002869] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N4159.t1937. ADD } N4165 (???,???) [004004] -A--GO----- * STOREIND int REG NA LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB158, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V18 V99} def: {V100} NEW BLOCK BB159 Setting BB157 as the predecessor for determining incoming variable registers of BB159 DefList: { } N4169 (???,???) [004005] ----------- * IL_OFFSET void INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] REG NA DefList: { } N4171 ( 1, 1) [001913] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4173 (???,???) [004262] ----------- * PUTARG_REG byref REG x0 BB159 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB159 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 464: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB159 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N4173.t4262. PUTARG_REG } N4175 ( 1, 1) [000675] ----------- * LCL_VAR int V18 loc14 u:2 NA (last use) REG NA $5c9 DefList: { N4173.t4262. PUTARG_REG } N4177 (???,???) [004263] ----------- * PUTARG_REG int REG x1 Last use of V18 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB159 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB159 regmask=[x1] minReg=1 last fixed wt=23800.00> Interval 465: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB159 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N4173.t4262. PUTARG_REG; N4177.t4263. PUTARG_REG } N4179 ( 2, 8) [002870] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn REG NA $53 Interval 466: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB159 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4173.t4262. PUTARG_REG; N4177.t4263. PUTARG_REG; N4179.t2870. CNS_INT } N4181 (???,???) [004264] ----------- * PUTARG_REG long REG x11 BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 467: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB159 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N4173.t4262. PUTARG_REG; N4177.t4263. PUTARG_REG; N4181.t4264. PUTARG_REG } N4183 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 468: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB159 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB159 regmask=[x0] minReg=1 wt=200.00> BB159 regmask=[x0] minReg=1 last fixed wt=200.00> BB159 regmask=[x1] minReg=1 wt=200.00> BB159 regmask=[x1] minReg=1 last fixed wt=200.00> BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB159 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB159 regmask=[x0] minReg=1 wt=200.00> BB159 regmask=[x1] minReg=1 wt=200.00> BB159 regmask=[x2] minReg=1 wt=200.00> BB159 regmask=[x3] minReg=1 wt=200.00> BB159 regmask=[x4] minReg=1 wt=200.00> BB159 regmask=[x5] minReg=1 wt=200.00> BB159 regmask=[x6] minReg=1 wt=200.00> BB159 regmask=[x7] minReg=1 wt=200.00> BB159 regmask=[x8] minReg=1 wt=200.00> BB159 regmask=[x9] minReg=1 wt=200.00> BB159 regmask=[x10] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x12] minReg=1 wt=200.00> BB159 regmask=[x13] minReg=1 wt=200.00> BB159 regmask=[x14] minReg=1 wt=200.00> BB159 regmask=[x15] minReg=1 wt=200.00> BB159 regmask=[xip0] minReg=1 wt=200.00> BB159 regmask=[xip1] minReg=1 wt=200.00> BB159 regmask=[lr] minReg=1 wt=200.00> CHECKING LAST USES for BB159, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V18} def: {} NEW BLOCK BB160 Setting BB158 as the predecessor for determining incoming variable registers of BB160 DefList: { } N4187 (???,???) [004006] ----------- * IL_OFFSET void INLRT @ 0x529[E-] REG NA DefList: { } N4189 ( 1, 1) [000677] ----------- * LCL_VAR int V12 loc8 u:3 NA REG NA $4c4 DefList: { } N4191 ( 1, 2) [000678] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N4193 ( 6, 4) [000679] -c-----N--- * EQ int REG NA $70a Contained DefList: { } N4195 ( 1, 1) [000681] ----------- * LCL_VAR int V08 loc4 u:3 NA REG NA $2b5 DefList: { } N4197 ( 1, 2) [000682] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N4199 ( 6, 4) [000683] -c-----N--- * LE int REG NA $a93 Contained DefList: { } N4201 ( 13, 9) [003746] Jc-----N--- * AND void REG NA Contained DefList: { } N4203 ( 15, 11) [000680] ----------- * JTRUE void REG NA $VN.Void LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2900.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> CHECKING LAST USES for BB160, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V08 V12} def: {} NEW BLOCK BB161 Setting BB160 as the predecessor for determining incoming variable registers of BB161 DefList: { } N4207 (???,???) [004007] ----------- * IL_OFFSET void INLRT @ 0x52D[E-] REG NA DefList: { } N4209 (???,???) [004008] ----------- * IL_OFFSET void INLRT @ 0x532[E-] REG NA DefList: { } N4211 ( 1, 1) [000692] ----------- * LCL_VAR int V20 loc16 u:4 NA REG NA $2b3 DefList: { } N4213 ( 1, 1) [000696] ----------- * LCL_VAR int V144 tmp104 u:2 NA REG NA $2a6 DefList: { } N4215 ( 6, 9) [000697] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $a34 LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> DefList: { } N4217 ( 1, 1) [000701] ----------- * LCL_VAR byref V143 tmp103 u:2 NA REG NA $385 DefList: { } N4219 ( 1, 1) [000693] ----------- * LCL_VAR int V20 loc16 u:4 NA REG NA $2b3 DefList: { } N4221 ( 2, 3) [000698] -c-------U- * CAST long <- uint REG NA $ac0 Contained DefList: { } N4223 ( 1, 2) [000699] -c--------- * CNS_INT long 2 REG NA $20a Contained DefList: { } N4225 ( 4, 6) [000700] -c--------- * BFIZ long REG NA Contained DefList: { } N4227 ( 6, 8) [000702] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { } N4229 ( 8, 9) [002871] ---XGO----- * IND int REG NA LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> Interval 469: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4229.t2871. IND } N4231 ( 1, 2) [000705] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { N4229.t2871. IND } N4233 ( 16, 21) [000706] ---XGO----- * ADD int REG NA BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 470: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4233.t706. ADD } N4235 ( 1, 1) [000689] ----------- * LCL_VAR int V08 loc4 u:3 NA REG NA $2b5 DefList: { N4233.t706. ADD } N4237 ( 21, 23) [000707] Nc-XGO-N-U- * NE int REG NA Contained DefList: { N4233.t706. ADD } N4239 ( 1, 1) [000685] ----------- * LCL_VAR int V20 loc16 u:4 NA REG NA $2b3 DefList: { N4233.t706. ADD } N4241 ( 1, 2) [000686] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N4233.t706. ADD } N4243 ( 6, 4) [000687] -c-----N--- * LT int REG NA $a94 Contained DefList: { N4233.t706. ADD } N4245 ( 28, 28) [003748] Jc-XGO-N--- * AND void REG NA Contained DefList: { N4233.t706. ADD } N4247 ( 30, 30) [000688] ---XGO----- * JTRUE void REG NA $VN.Void BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> CHECKING LAST USES for BB161, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V08 V20 V143 V144} def: {} NEW BLOCK BB163 Setting BB161 as the predecessor for determining incoming variable registers of BB163 DefList: { } N4251 (???,???) [004009] ----------- * IL_OFFSET void INLRT @ 0x537[E-] REG NA DefList: { } N4253 (???,???) [004010] ----------- * IL_OFFSET void INLRT @ 0x547[E-] REG NA DefList: { } N4255 ( 1, 1) [000710] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { } N4257 ( 3, 4) [002873] -c--------- * LEA(b+56) byref REG NA Contained DefList: { } N4259 ( 4, 3) [001946] ---XG------ * IND ref REG NA LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 471: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4259.t1946. IND } N4261 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 NA REG NA BB163 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N4263 (???,???) [004011] ----------- * IL_OFFSET void INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] REG NA DefList: { } N4265 ( 1, 1) [001948] ----------- * LCL_VAR ref V102 tmp62 u:1 NA REG NA DefList: { } N4267 ( 1, 2) [001949] -c--------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N4269 ( 3, 4) [001950] CEQ-------N--- * JCMP void REG NA LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB163, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144 V179} ============================== use: {V03} def: {V102} NEW BLOCK BB165 Setting BB163 as the predecessor for determining incoming variable registers of BB165 DefList: { } N4273 (???,???) [004012] ----------- * IL_OFFSET void INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] REG NA DefList: { } N4275 ( 1, 1) [000709] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4277 ( 3, 4) [002875] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4279 ( 4, 3) [001952] n---GO----- * IND int REG NA LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 472: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4279.t1952. IND } N4281 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 NA REG NA BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N4283 (???,???) [004013] ----------- * IL_OFFSET void INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] REG NA DefList: { } N4285 ( 1, 1) [001955] ----------- * LCL_VAR ref V102 tmp62 u:1 NA REG NA DefList: { } N4287 (???,???) [004170] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4289 ( 3, 3) [001956] ---X------- * IND int REG NA LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 473: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4289.t1956. IND } N4291 ( 1, 2) [001957] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { N4289.t1956. IND } N4293 ( 8, 6) [001958] Nc-X---N-U- * NE int REG NA Contained DefList: { N4289.t1956. IND } N4295 ( 1, 1) [001963] ----------- * LCL_VAR int V103 tmp63 u:1 NA REG NA DefList: { N4289.t1956. IND } N4297 ( 1, 1) [001964] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N4289.t1956. IND } N4299 ( 3, 4) [002879] -c--------- * LEA(b+24) byref REG NA Contained DefList: { N4289.t1956. IND } N4301 ( 4, 3) [002002] n---GO----- * IND int REG NA LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 474: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4289.t1956. IND; N4301.t2002. IND } N4303 ( 9, 5) [001968] Nc--GO-N-U- * GE int REG NA Contained DefList: { N4289.t1956. IND; N4301.t2002. IND } N4305 ( 18, 12) [003750] Jc-XGO-N--- * AND void REG NA Contained DefList: { N4289.t1956. IND; N4301.t2002. IND } N4307 ( 20, 14) [001959] ---XGO----- * JTRUE void REG NA BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB165, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144 V179} ============================== use: {V00 V102} def: {V103} NEW BLOCK BB166 Setting BB165 as the predecessor for determining incoming variable registers of BB166 DefList: { } N4311 (???,???) [004014] ----------- * IL_OFFSET void INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] REG NA DefList: { } N4313 (???,???) [004015] ----------- * IL_OFFSET void INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] REG NA DefList: { } N4315 ( 1, 1) [002883] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4317 ( 1, 2) [002884] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N4319 ( 3, 4) [002885] -----O----- * ADD byref REG NA $25c LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 475: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4319.t2885. ADD } N4321 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 NA REG NA BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N4323 (???,???) [004016] ----------- * IL_OFFSET void INL37 @ ??? <- INLRT @ 0x547[E-] REG NA DefList: { } N4325 ( 1, 1) [001972] ----------- * LCL_VAR int V103 tmp63 u:1 NA REG NA DefList: { } N4327 ( 1, 1) [001977] ----------- * LCL_VAR byref V104 tmp64 u:1 NA REG NA $25c DefList: { } N4329 ( 3, 4) [002888] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4331 ( 4, 3) [001978] n---GO----- * IND int REG NA LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 476: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4331.t1978. IND } N4333 ( 9, 11) [001979] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N4335 ( 1, 1) [001976] ----------- * LCL_VAR byref V104 tmp64 u:1 NA (last use) REG NA $25c DefList: { } N4337 ( 3, 2) [001983] n---GO----- * IND byref REG NA LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 477: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4337.t1983. IND } N4339 ( 1, 1) [001973] ----------- * LCL_VAR int V103 tmp63 u:1 NA REG NA DefList: { N4337.t1983. IND } N4341 ( 2, 3) [001980] -c-------U- * CAST long <- uint REG NA Contained DefList: { N4337.t1983. IND } N4343 ( 1, 2) [001981] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N4337.t1983. IND } N4345 ( 4, 6) [001982] ----------- * BFIZ long REG NA LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 478: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BFIZ BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4337.t1983. IND; N4345.t1982. BFIZ } N4347 ( 8, 9) [001984] ----GO-N--- * ADD byref REG NA BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 479: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4347.t1984. ADD } N4349 ( 1, 2) [001987] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N4347.t1984. ADD } N4351 ( 1, 1) [001986] ----------- * LCL_VAR ref V102 tmp62 u:1 NA REG NA DefList: { N4347.t1984. ADD } N4353 (???,???) [004172] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N4347.t1984. ADD } N4355 ( 3, 3) [002892] ---X------- * IND int REG NA LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 480: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4347.t1984. ADD; N4355.t2892. IND } N4357 ( 8, 12) [002893] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { N4347.t1984. ADD } N4359 ( 1, 1) [002890] ----------- * LCL_VAR ref V102 tmp62 u:1 NA (last use) REG NA DefList: { N4347.t1984. ADD } N4361 ( 1, 1) [002897] -c--------- * LEA(b+12) byref REG NA Contained DefList: { N4347.t1984. ADD } N4363 ( 5, 4) [002902] n---GO----- * IND ushort REG NA LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 481: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4347.t1984. ADD; N4363.t2902. IND } N4365 (???,???) [004017] -A-XGO----- * STOREIND short REG NA BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N4367 (???,???) [004018] ----------- * IL_OFFSET void INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] REG NA DefList: { } N4369 ( 1, 1) [001993] ----------- * LCL_VAR int V103 tmp63 u:1 NA (last use) REG NA DefList: { } N4371 ( 1, 2) [001994] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N4373 ( 3, 4) [001995] ----------- * ADD int REG NA LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 482: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4373.t1995. ADD } N4375 ( 1, 1) [001992] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N4373.t1995. ADD } N4377 ( 3, 4) [002904] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N4373.t1995. ADD } N4379 (???,???) [004019] -A--GO----- * STOREIND int REG NA LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB166, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V102 V103} def: {V104} NEW BLOCK BB168 Setting BB165 as the predecessor for determining incoming variable registers of BB168 DefList: { } N4383 (???,???) [004020] ----------- * IL_OFFSET void INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] REG NA DefList: { } N4385 ( 1, 1) [001960] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4387 (???,???) [004265] ----------- * PUTARG_REG byref REG x0 BB168 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB168 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 483: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB168 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N4387.t4265. PUTARG_REG } N4389 ( 1, 1) [001961] ----------- * LCL_VAR ref V102 tmp62 u:1 NA (last use) REG NA DefList: { N4387.t4265. PUTARG_REG } N4391 (???,???) [004266] ----------- * PUTARG_REG ref REG x1 Last use of V102 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB168 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB168 regmask=[x1] minReg=1 last fixed wt=2400.00> Interval 484: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB168 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N4387.t4265. PUTARG_REG; N4391.t4266. PUTARG_REG } N4393 ( 2, 8) [002905] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn REG NA $4f Interval 485: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB168 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4387.t4265. PUTARG_REG; N4391.t4266. PUTARG_REG; N4393.t2905. CNS_INT } N4395 (???,???) [004267] ----------- * PUTARG_REG long REG x11 BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 486: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB168 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N4387.t4265. PUTARG_REG; N4391.t4266. PUTARG_REG; N4395.t4267. PUTARG_REG } N4397 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void Interval 487: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB168 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB168 regmask=[x0] minReg=1 wt=200.00> BB168 regmask=[x0] minReg=1 last fixed wt=200.00> BB168 regmask=[x1] minReg=1 wt=200.00> BB168 regmask=[x1] minReg=1 last fixed wt=200.00> BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB168 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB168 regmask=[x0] minReg=1 wt=200.00> BB168 regmask=[x1] minReg=1 wt=200.00> BB168 regmask=[x2] minReg=1 wt=200.00> BB168 regmask=[x3] minReg=1 wt=200.00> BB168 regmask=[x4] minReg=1 wt=200.00> BB168 regmask=[x5] minReg=1 wt=200.00> BB168 regmask=[x6] minReg=1 wt=200.00> BB168 regmask=[x7] minReg=1 wt=200.00> BB168 regmask=[x8] minReg=1 wt=200.00> BB168 regmask=[x9] minReg=1 wt=200.00> BB168 regmask=[x10] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x12] minReg=1 wt=200.00> BB168 regmask=[x13] minReg=1 wt=200.00> BB168 regmask=[x14] minReg=1 wt=200.00> BB168 regmask=[x15] minReg=1 wt=200.00> BB168 regmask=[xip0] minReg=1 wt=200.00> BB168 regmask=[xip1] minReg=1 wt=200.00> BB168 regmask=[lr] minReg=1 wt=200.00> CHECKING LAST USES for BB168, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V102} def: {} NEW BLOCK BB169 Setting BB163 as the predecessor for determining incoming variable registers of BB169 DefList: { } N4401 (???,???) [004021] ----------- * IL_OFFSET void INLRT @ 0x553[E-] REG NA DefList: { } N4403 ( 1, 1) [000714] ----------- * LCL_VAR int V20 loc16 u:4 NA (last use) REG NA $2b3 DefList: { } N4405 ( 1, 2) [000715] -c--------- * CNS_INT int -1 REG NA $c4 Contained DefList: { } N4407 ( 3, 4) [000716] ----------- * ADD int REG NA $ab7 LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> Interval 488: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB169 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4407.t716. ADD } N4409 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 NA REG NA BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> CHECKING LAST USES for BB169, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V20} def: {V20} NEW BLOCK BB170 Setting BB156 as the predecessor for determining incoming variable registers of BB170 DefList: { } N4413 (???,???) [004022] ----------- * IL_OFFSET void INLRT @ 0x559[E-] REG NA DefList: { } N4415 ( 1, 1) [000669] ----------- * LCL_VAR int V08 loc4 u:3 NA (last use) REG NA $2b5 DefList: { } N4417 ( 1, 2) [000670] -c--------- * CNS_INT int -1 REG NA $c4 Contained DefList: { } N4419 ( 3, 4) [000671] ----------- * ADD int REG NA $ab9 LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> Interval 489: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB170 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4419.t671. ADD } N4421 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 NA REG NA BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> CHECKING LAST USES for BB170, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V08} def: {V08} NEW BLOCK BB186 Setting BB257 as the predecessor for determining incoming variable registers of BB186 DefList: { } N4425 (???,???) [004049] ----------- * IL_OFFSET void INLRT @ 0x5A9[E-] REG NA DefList: { } N4427 ( 1, 1) [000635] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { } N4429 ( 3, 4) [002974] -c--------- * LEA(b+128) byref REG NA Contained DefList: { } N4431 ( 4, 3) [002126] ---XG------ * IND ref REG NA LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 490: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4431.t2126. IND } N4433 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 NA REG NA BB186 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N4435 (???,???) [004050] ----------- * IL_OFFSET void INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] REG NA DefList: { } N4437 ( 1, 1) [002128] ----------- * LCL_VAR ref V114 tmp74 u:1 NA REG NA DefList: { } N4439 ( 1, 2) [002129] -c--------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N4441 ( 3, 4) [002130] CEQ-------N--- * JCMP void REG NA LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB186, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144 V179} ============================== use: {V03} def: {V114} NEW BLOCK BB187 Setting BB112 as the predecessor for determining incoming variable registers of BB187 Creating dummy definitions BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Finished creating dummy definitions DefList: { } N4445 (???,???) [004051] ----------- * IL_OFFSET void INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] REG NA DefList: { } N4447 ( 1, 1) [000634] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4449 ( 3, 4) [002976] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4451 ( 4, 3) [002132] ---XG------ * IND int REG NA LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 491: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4451.t2132. IND } N4453 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 NA REG NA BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N4455 (???,???) [004052] ----------- * IL_OFFSET void INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] REG NA DefList: { } N4457 ( 1, 1) [002135] ----------- * LCL_VAR ref V114 tmp74 u:1 NA REG NA DefList: { } N4459 (???,???) [004182] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4461 ( 3, 3) [002136] ---X------- * IND int REG NA LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 492: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4461.t2136. IND } N4463 ( 1, 2) [002137] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { N4461.t2136. IND } N4465 ( 8, 6) [002138] Nc-X---N-U- * NE int REG NA Contained DefList: { N4461.t2136. IND } N4467 ( 1, 1) [002143] ----------- * LCL_VAR int V115 tmp75 u:1 NA REG NA DefList: { N4461.t2136. IND } N4469 ( 1, 1) [002144] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N4461.t2136. IND } N4471 ( 3, 4) [002980] -c--------- * LEA(b+24) byref REG NA Contained DefList: { N4461.t2136. IND } N4473 ( 4, 3) [002182] n---GO----- * IND int REG NA LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 493: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4461.t2136. IND; N4473.t2182. IND } N4475 ( 9, 5) [002148] Nc--GO-N-U- * GE int REG NA Contained DefList: { N4461.t2136. IND; N4473.t2182. IND } N4477 ( 18, 12) [003758] Jc-XGO-N--- * AND void REG NA Contained DefList: { N4461.t2136. IND; N4473.t2182. IND } N4479 ( 20, 14) [002139] ---XGO----- * JTRUE void REG NA BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB187, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144 V179} ============================== use: {V00 V114} def: {V115} NEW BLOCK BB188 Setting BB187 as the predecessor for determining incoming variable registers of BB188 DefList: { } N4483 (???,???) [004053] ----------- * IL_OFFSET void INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] REG NA DefList: { } N4485 (???,???) [004054] ----------- * IL_OFFSET void INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] REG NA DefList: { } N4487 ( 1, 1) [002984] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4489 ( 1, 2) [002985] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N4491 ( 3, 4) [002986] -----O----- * ADD byref REG NA $25c LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 494: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4491.t2986. ADD } N4493 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 NA REG NA BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N4495 (???,???) [004055] ----------- * IL_OFFSET void INL46 @ ??? <- INLRT @ 0x5A9[E-] REG NA DefList: { } N4497 ( 1, 1) [002152] ----------- * LCL_VAR int V115 tmp75 u:1 NA REG NA DefList: { } N4499 ( 1, 1) [002157] ----------- * LCL_VAR byref V116 tmp76 u:1 NA REG NA $25c DefList: { } N4501 ( 3, 4) [002989] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4503 ( 4, 3) [002158] n---GO----- * IND int REG NA LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 495: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4503.t2158. IND } N4505 ( 9, 11) [002159] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N4507 ( 1, 1) [002156] ----------- * LCL_VAR byref V116 tmp76 u:1 NA (last use) REG NA $25c DefList: { } N4509 ( 3, 2) [002163] n---GO----- * IND byref REG NA LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 496: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4509.t2163. IND } N4511 ( 1, 1) [002153] ----------- * LCL_VAR int V115 tmp75 u:1 NA REG NA DefList: { N4509.t2163. IND } N4513 ( 2, 3) [002160] -c-------U- * CAST long <- uint REG NA Contained DefList: { N4509.t2163. IND } N4515 ( 1, 2) [002161] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N4509.t2163. IND } N4517 ( 4, 6) [002162] ----------- * BFIZ long REG NA LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 497: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BFIZ BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4509.t2163. IND; N4517.t2162. BFIZ } N4519 ( 8, 9) [002164] ----GO-N--- * ADD byref REG NA BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 498: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4519.t2164. ADD } N4521 ( 1, 2) [002167] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N4519.t2164. ADD } N4523 ( 1, 1) [002166] ----------- * LCL_VAR ref V114 tmp74 u:1 NA REG NA DefList: { N4519.t2164. ADD } N4525 (???,???) [004184] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N4519.t2164. ADD } N4527 ( 3, 3) [002993] ---X------- * IND int REG NA LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 499: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4519.t2164. ADD; N4527.t2993. IND } N4529 ( 8, 12) [002994] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { N4519.t2164. ADD } N4531 ( 1, 1) [002991] ----------- * LCL_VAR ref V114 tmp74 u:1 NA (last use) REG NA DefList: { N4519.t2164. ADD } N4533 ( 1, 1) [002998] -c--------- * LEA(b+12) byref REG NA Contained DefList: { N4519.t2164. ADD } N4535 ( 5, 4) [003003] n---GO----- * IND ushort REG NA LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 500: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4519.t2164. ADD; N4535.t3003. IND } N4537 (???,???) [004056] -A-XGO----- * STOREIND short REG NA BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N4539 (???,???) [004057] ----------- * IL_OFFSET void INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] REG NA DefList: { } N4541 ( 1, 1) [002173] ----------- * LCL_VAR int V115 tmp75 u:1 NA (last use) REG NA DefList: { } N4543 ( 1, 2) [002174] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N4545 ( 3, 4) [002175] ----------- * ADD int REG NA LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 501: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4545.t2175. ADD } N4547 ( 1, 1) [002172] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N4545.t2175. ADD } N4549 ( 3, 4) [003005] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N4545.t2175. ADD } N4551 (???,???) [004058] -A--GO----- * STOREIND int REG NA LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB188, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V114 V115} def: {V116} NEW BLOCK BB190 Setting BB187 as the predecessor for determining incoming variable registers of BB190 DefList: { } N4555 (???,???) [004059] ----------- * IL_OFFSET void INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] REG NA DefList: { } N4557 ( 1, 1) [002140] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4559 (???,???) [004274] ----------- * PUTARG_REG byref REG x0 BB190 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB190 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 502: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB190 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N4559.t4274. PUTARG_REG } N4561 ( 1, 1) [002141] ----------- * LCL_VAR ref V114 tmp74 u:1 NA (last use) REG NA DefList: { N4559.t4274. PUTARG_REG } N4563 (???,???) [004275] ----------- * PUTARG_REG ref REG x1 Last use of V114 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB190 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB190 regmask=[x1] minReg=1 last fixed wt=2400.00> Interval 503: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB190 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N4559.t4274. PUTARG_REG; N4563.t4275. PUTARG_REG } N4565 ( 2, 8) [003006] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn REG NA $4f Interval 504: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB190 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4559.t4274. PUTARG_REG; N4563.t4275. PUTARG_REG; N4565.t3006. CNS_INT } N4567 (???,???) [004276] ----------- * PUTARG_REG long REG x11 BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 505: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB190 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N4559.t4274. PUTARG_REG; N4563.t4275. PUTARG_REG; N4567.t4276. PUTARG_REG } N4569 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void Interval 506: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB190 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB190 regmask=[x0] minReg=1 wt=200.00> BB190 regmask=[x0] minReg=1 last fixed wt=200.00> BB190 regmask=[x1] minReg=1 wt=200.00> BB190 regmask=[x1] minReg=1 last fixed wt=200.00> BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB190 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB190 regmask=[x0] minReg=1 wt=200.00> BB190 regmask=[x1] minReg=1 wt=200.00> BB190 regmask=[x2] minReg=1 wt=200.00> BB190 regmask=[x3] minReg=1 wt=200.00> BB190 regmask=[x4] minReg=1 wt=200.00> BB190 regmask=[x5] minReg=1 wt=200.00> BB190 regmask=[x6] minReg=1 wt=200.00> BB190 regmask=[x7] minReg=1 wt=200.00> BB190 regmask=[x8] minReg=1 wt=200.00> BB190 regmask=[x9] minReg=1 wt=200.00> BB190 regmask=[x10] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x12] minReg=1 wt=200.00> BB190 regmask=[x13] minReg=1 wt=200.00> BB190 regmask=[x14] minReg=1 wt=200.00> BB190 regmask=[x15] minReg=1 wt=200.00> BB190 regmask=[xip0] minReg=1 wt=200.00> BB190 regmask=[xip1] minReg=1 wt=200.00> BB190 regmask=[lr] minReg=1 wt=200.00> CHECKING LAST USES for BB190, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V114} def: {} NEW BLOCK BB194 Setting BB257 as the predecessor for determining incoming variable registers of BB194 DefList: { } N4573 (???,???) [004069] ----------- * IL_OFFSET void INLRT @ 0x5CE[E-] REG NA DefList: { } N4575 ( 1, 1) [000751] ----------- * LCL_VAR int V16 loc12 u:13 NA REG NA $b04 DefList: { } N4577 ( 1, 1) [003699] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N4579 ( 3, 3) [000756] J------N--- * GE void REG NA $ba4 LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N4581 ( 5, 5) [000757] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB194, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V16 V179} def: {} NEW BLOCK BB195 Setting BB194 as the predecessor for determining incoming variable registers of BB195 DefList: { } N4585 (???,???) [004070] ----------- * IL_OFFSET void INLRT @ 0x5D9[E-] REG NA DefList: { } N4587 ( 1, 1) [000781] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N4589 ( 1, 1) [000782] ----------- * LCL_VAR int V16 loc12 u:13 NA REG NA $b04 DefList: { } N4591 ( 2, 3) [000783] -c--------- * CAST long <- int REG NA $aca Contained DefList: { } N4593 ( 1, 2) [000785] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N4595 ( 4, 6) [000786] -c--------- * BFIZ long REG NA Contained DefList: { } N4597 ( 6, 8) [000787] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N4599 ( 9, 10) [000788] ---XG------ * IND ushort REG NA LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 507: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> DefList: { N4599.t788. IND } N4601 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 NA REG NA BB195 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> Assigning related to STORE_LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> DefList: { } N4603 ( 1, 1) [003632] ----------- * LCL_VAR int V172 cse1 NA REG NA DefList: { } N4605 ( 1, 2) [000789] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N4607 ( 12, 14) [000790] CEQ---XG--N--- * JCMP void REG NA LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> CHECKING LAST USES for BB195, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} ============================== use: {V16 V34} def: {V172} NEW BLOCK BB196 Setting BB195 as the predecessor for determining incoming variable registers of BB196 DefList: { } N4611 (???,???) [004071] ----------- * IL_OFFSET void INLRT @ 0x5E4[E-] REG NA DefList: { } N4613 ( 1, 1) [003634] ----------- * LCL_VAR int V172 cse1 NA REG NA DefList: { } N4615 ( 1, 1) [000800] ----------- * LCL_VAR int V18 loc14 u:1 NA REG NA DefList: { } N4617 ( 3, 3) [000801] N---G--N-U- * NE void REG NA LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> DefList: { } N4619 ( 5, 5) [000802] ----G------ * JTRUE void REG NA $bec CHECKING LAST USES for BB196, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} ============================== use: {V18 V172} def: {} NEW BLOCK BB191 Setting BB196 as the predecessor for determining incoming variable registers of BB191 DefList: { } N4623 (???,???) [004060] ----------- * IL_OFFSET void INLRT @ 0x5BA[E-] REG NA DefList: { } N4625 ( 1, 1) [000805] ----------- * LCL_VAR int V16 loc12 u:13 NA (last use) REG NA $b04 DefList: { } N4627 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 NA REG NA LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> DefList: { } N4629 (???,???) [004061] ----------- * IL_OFFSET void INLRT @ 0x5BA[E-] REG NA DefList: { } N4631 ( 1, 1) [000806] ----------- * LCL_VAR int V59 tmp19 u:1 NA (last use) REG NA $b04 DefList: { } N4633 ( 1, 2) [000807] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N4635 ( 3, 4) [000808] ----------- * ADD int REG NA $bad LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> Interval 508: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N4635.t808. ADD } N4637 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 NA REG NA BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> DefList: { } N4639 ( 1, 1) [003629] ----------- * LCL_VAR int V172 cse1 NA (last use) REG NA DefList: { } N4641 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 NA REG NA LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> Assigning related to STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N4643 (???,???) [004062] ----------- * IL_OFFSET void INL48 @ 0x000[E-] <- INLRT @ ??? REG NA DefList: { } N4645 ( 1, 1) [000803] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4647 ( 3, 4) [003008] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4649 ( 4, 3) [002186] ---XG------ * IND int REG NA LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 509: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N4649.t2186. IND } N4651 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 NA REG NA BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> DefList: { } N4653 (???,???) [004063] ----------- * IL_OFFSET void INL48 @ 0x007[E-] <- INLRT @ ??? REG NA DefList: { } N4655 ( 1, 1) [002189] ----------- * LCL_VAR int V118 tmp78 u:1 NA REG NA DefList: { } N4657 ( 1, 1) [002190] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4659 ( 3, 4) [003012] -c--------- * LEA(b+24) byref REG NA Contained DefList: { } N4661 ( 4, 3) [002228] n---GO----- * IND int REG NA LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 510: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N4661.t2228. IND } N4663 ( 6, 5) [002194] N---GO-N-U- * GE void REG NA LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N4665 ( 8, 7) [002195] ----GO----- * JTRUE void REG NA $845 CHECKING LAST USES for BB191, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144 V179} ============================== use: {V00 V16 V172} def: {V16 V59 V118 V119} NEW BLOCK BB192 Setting BB191 as the predecessor for determining incoming variable registers of BB192 DefList: { } N4669 (???,???) [004064] ----------- * IL_OFFSET void INL48 @ 0x015[E-] <- INLRT @ ??? REG NA DefList: { } N4671 ( 1, 1) [003016] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4673 ( 1, 2) [003017] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N4675 ( 3, 4) [003018] -----O----- * ADD byref REG NA $25c LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 511: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N4675.t3018. ADD } N4677 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 NA REG NA BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> Assigning related to STORE_LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N4679 ( 1, 1) [002201] ----------- * LCL_VAR int V118 tmp78 u:1 NA REG NA DefList: { } N4681 ( 1, 1) [002206] ----------- * LCL_VAR byref V120 tmp80 u:1 NA REG NA $25c DefList: { } N4683 ( 3, 4) [003021] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4685 ( 4, 3) [002207] n---GO----- * IND int REG NA LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 512: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N4685.t2207. IND } N4687 ( 9, 11) [002208] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> DefList: { } N4689 ( 1, 1) [002205] ----------- * LCL_VAR byref V120 tmp80 u:1 NA (last use) REG NA $25c DefList: { } N4691 ( 3, 2) [002212] n---GO----- * IND byref REG NA LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> Interval 513: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N4691.t2212. IND } N4693 ( 1, 1) [002202] ----------- * LCL_VAR int V118 tmp78 u:1 NA REG NA DefList: { N4691.t2212. IND } N4695 ( 2, 3) [002209] -c-------U- * CAST long <- uint REG NA Contained DefList: { N4691.t2212. IND } N4697 ( 1, 2) [002210] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N4691.t2212. IND } N4699 ( 4, 6) [002211] -c--------- * BFIZ long REG NA Contained DefList: { N4691.t2212. IND } N4701 ( 8, 9) [002213] -c--------- * LEA(b+(i*1)+0) byref REG NA Contained DefList: { N4691.t2212. IND } N4703 ( 1, 1) [002215] ----------- * LCL_VAR int V119 tmp79 u:1 NA (last use) REG NA DefList: { N4691.t2212. IND } N4705 (???,???) [004065] -A-XGO----- * STOREIND short REG NA BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> DefList: { } N4707 (???,???) [004066] ----------- * IL_OFFSET void INL48 @ 0x023[E-] <- INLRT @ ??? REG NA DefList: { } N4709 ( 1, 1) [002219] ----------- * LCL_VAR int V118 tmp78 u:1 NA (last use) REG NA DefList: { } N4711 ( 1, 2) [002220] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N4713 ( 3, 4) [002221] ----------- * ADD int REG NA LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> Interval 514: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N4713.t2221. ADD } N4715 ( 1, 1) [002218] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N4713.t2221. ADD } N4717 ( 3, 4) [003024] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N4713.t2221. ADD } N4719 (???,???) [004067] -A--GO----- * STOREIND int REG NA LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CHECKING LAST USES for BB192, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V118 V119} def: {V120} NEW BLOCK BB193 Setting BB191 as the predecessor for determining incoming variable registers of BB193 DefList: { } N4723 (???,???) [004068] ----------- * IL_OFFSET void INL48 @ 0x02D[E-] <- INLRT @ ??? REG NA DefList: { } N4725 ( 1, 1) [002196] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4727 (???,???) [004277] ----------- * PUTARG_REG byref REG x0 BB193 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB193 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 515: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB193 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x0] minReg=1 fixed wt=3200.00> Assigning related to DefList: { N4727.t4277. PUTARG_REG } N4729 ( 1, 1) [002197] ----------- * LCL_VAR int V119 tmp79 u:1 NA (last use) REG NA DefList: { N4727.t4277. PUTARG_REG } N4731 (???,???) [004278] ----------- * PUTARG_REG int REG x1 Last use of V119 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB193 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB193 regmask=[x1] minReg=1 last fixed wt=4800.00> Interval 516: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB193 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x1] minReg=1 fixed wt=3200.00> DefList: { N4727.t4277. PUTARG_REG; N4731.t4278. PUTARG_REG } N4733 ( 2, 8) [003025] H---------- * CNS_INT(h) long 0x4000000000435c58 ftn REG NA $53 Interval 517: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB193 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> DefList: { N4727.t4277. PUTARG_REG; N4731.t4278. PUTARG_REG; N4733.t3025. CNS_INT } N4735 (???,???) [004279] ----------- * PUTARG_REG long REG x11 BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 last fixed wt=800.00> Interval 518: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB193 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x11] minReg=1 fixed wt=3200.00> DefList: { N4727.t4277. PUTARG_REG; N4731.t4278. PUTARG_REG; N4735.t4279. PUTARG_REG } N4737 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void REG NA $VN.Void Interval 519: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB193 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB193 regmask=[x0] minReg=1 wt=800.00> BB193 regmask=[x0] minReg=1 last fixed wt=800.00> BB193 regmask=[x1] minReg=1 wt=800.00> BB193 regmask=[x1] minReg=1 last fixed wt=800.00> BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB193 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB193 regmask=[x0] minReg=1 wt=800.00> BB193 regmask=[x1] minReg=1 wt=800.00> BB193 regmask=[x2] minReg=1 wt=800.00> BB193 regmask=[x3] minReg=1 wt=800.00> BB193 regmask=[x4] minReg=1 wt=800.00> BB193 regmask=[x5] minReg=1 wt=800.00> BB193 regmask=[x6] minReg=1 wt=800.00> BB193 regmask=[x7] minReg=1 wt=800.00> BB193 regmask=[x8] minReg=1 wt=800.00> BB193 regmask=[x9] minReg=1 wt=800.00> BB193 regmask=[x10] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x12] minReg=1 wt=800.00> BB193 regmask=[x13] minReg=1 wt=800.00> BB193 regmask=[x14] minReg=1 wt=800.00> BB193 regmask=[x15] minReg=1 wt=800.00> BB193 regmask=[xip0] minReg=1 wt=800.00> BB193 regmask=[xip1] minReg=1 wt=800.00> BB193 regmask=[lr] minReg=1 wt=800.00> Exposed uses: BB193 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CHECKING LAST USES for BB193, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V00 V119} def: {} NEW BLOCK BB197 Setting BB194 as the predecessor for determining incoming variable registers of BB197 DefList: { } N4741 (???,???) [004072] ----------- * IL_OFFSET void INLRT @ 0x5F1[E-] REG NA DefList: { } N4743 ( 1, 1) [000758] ----------- * LCL_VAR int V16 loc12 u:13 NA REG NA $b04 DefList: { } N4745 ( 1, 1) [003700] ----------- * LCL_VAR int V179 cse8 u:1 NA REG NA $342 DefList: { } N4747 ( 3, 3) [000763] J------N--- * GE void REG NA $ba4 LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 last wt=28400.00> DefList: { } N4749 ( 5, 5) [000764] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB197, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V16 V179} def: {} NEW BLOCK BB198 Setting BB195 as the predecessor for determining incoming variable registers of BB198 DefList: { } N4753 (???,???) [004073] ----------- * IL_OFFSET void INLRT @ 0x5FF[E-] REG NA DefList: { } N4755 ( 1, 1) [000765] ----------- * LCL_VAR long V34 loc30 u:1 NA REG NA $3c4 DefList: { } N4757 ( 1, 1) [000766] ----------- * LCL_VAR int V16 loc12 u:13 NA REG NA $b04 DefList: { } N4759 ( 2, 3) [000767] -c--------- * CAST long <- int REG NA $aca Contained DefList: { } N4761 ( 1, 2) [000769] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { } N4763 ( 4, 6) [000770] -c--------- * BFIZ long REG NA Contained DefList: { } N4765 ( 6, 8) [000771] -c--------- * LEA(b+(i*1)+0) long REG NA Contained DefList: { } N4767 ( 9, 10) [000772] ---XG------ * IND ushort REG NA LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6700.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 520: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4767.t772. IND } N4769 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 NA REG NA BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> DefList: { } N4771 ( 1, 1) [003637] ----------- * LCL_VAR int V172 cse1 NA (last use) REG NA DefList: { } N4773 ( 1, 2) [000773] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N4775 ( 12, 14) [000774] CEQ---XG--N--- * JCMP void REG NA LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> CHECKING LAST USES for BB198, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V16 V34} def: {V172} NEW BLOCK BB199 Setting BB112 as the predecessor for determining incoming variable registers of BB199 DefList: { } N4779 (???,???) [004074] ----------- * IL_OFFSET void INLRT @ 0x60D[E-] REG NA DefList: { } N4781 ( 1, 1) [000776] ----------- * LCL_VAR int V16 loc12 u:13 NA (last use) REG NA $b04 DefList: { } N4783 ( 1, 2) [000777] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N4785 ( 3, 4) [000778] ----------- * ADD int REG NA $bad LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> Interval 521: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB199 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4785.t778. ADD } N4787 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 NA REG NA BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> CHECKING LAST USES for BB199, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V16} def: {V16} NEW BLOCK BB258 Setting BB138 as the predecessor for determining incoming variable registers of BB258 DefList: { } N4791 (???,???) [004258] ----------- * LCL_VAR int V185 rat3 NA (last use) REG NA DefList: { } N4793 (???,???) [004259] ---------U- * CAST long <- ulong <- uint REG NA LCL_VAR BB258 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 522: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CAST BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4793.t4259. CAST } N4795 (???,???) [004260] ----------- * JMPTABLE long REG NA Interval 523: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] JMPTABLE BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4793.t4259. CAST; N4795.t4260. JMPTABLE } N4797 (???,???) [004261] ----------- * SWITCH_TABLE void REG NA Interval 524: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] SWITCH_TABLE BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Exposed uses: BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> CHECKING LAST USES for BB258, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V185} def: {} NEW BLOCK BB171 Setting BB258 as the predecessor for determining incoming variable registers of BB171 DefList: { } N4801 (???,???) [004023] ----------- * IL_OFFSET void INLRT @ 0x564[E-] REG NA DefList: { } N4803 ( 1, 1) [000605] ----------- * LCL_VAR int V08 loc4 u:3 NA REG NA $2b5 DefList: { } N4805 ( 1, 2) [000606] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N4807 ( 6, 4) [000607] ----------- * NE int REG NA $aba LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> Interval 525: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NE BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4807.t607. NE } N4809 ( 1, 1) [000608] ----------- * LCL_VAR int V21 loc17 u:2 NA REG NA $4c7 DefList: { N4807.t607. NE } N4811 ( 8, 6) [000609] ----------- * OR int REG NA $abb BB171 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> Interval 526: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] OR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4811.t609. OR } N4813 ( 1, 2) [000610] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N4811.t609. OR } N4815 ( 10, 9) [000611] CNE-------N--- * JCMP void REG NA BB171 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB171, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V08 V21} def: {} NEW BLOCK BB172 Setting BB112 as the predecessor for determining incoming variable registers of BB172 DefList: { } N4819 (???,???) [004024] ----------- * IL_OFFSET void INLRT @ 0x571[E-] REG NA DefList: { } N4821 ( 1, 1) [000613] ----------- * LCL_VAR int V07 loc3 u:3 NA REG NA $293 DefList: { } N4823 ( 1, 2) [000614] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N4825 ( 3, 4) [000615] J------N--- * LT void REG NA $abd LCL_VAR BB172 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> DefList: { } N4827 ( 5, 6) [000616] ----------- * JTRUE void REG NA $VN.Void CHECKING LAST USES for BB172, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V07} def: {} NEW BLOCK BB173 Setting BB172 as the predecessor for determining incoming variable registers of BB173 DefList: { } N4831 (???,???) [004025] ----------- * IL_OFFSET void INLRT @ 0x575[E-] REG NA DefList: { } N4833 ( 1, 1) [000625] ----------- * LCL_VAR int V05 loc1 u:3 NA REG NA $28d DefList: { } N4835 ( 1, 1) [000626] ----------- * LCL_VAR int V04 loc0 u:2 NA REG NA $28a DefList: { } N4837 ( 6, 3) [000627] -c-----N--- * GE int REG NA $abe Contained DefList: { } N4839 ( 1, 1) [000629] ----------- * LCL_VAR long V36 loc32 u:3 NA REG NA $901 DefList: { } N4841 ( 4, 3) [000630] ---XG------ * IND ubyte REG NA LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> Interval 527: ubyte RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4841.t630. IND } N4843 ( 1, 2) [000631] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N4841.t630. IND } N4845 ( 9, 6) [000632] -c-XG--N--- * EQ int REG NA Contained DefList: { N4841.t630. IND } N4847 ( 16, 10) [003752] Jc-XG--N--- * AND void REG NA Contained DefList: { N4841.t630. IND } N4849 ( 18, 12) [000628] ---XG------ * JTRUE void REG NA $VN.Void LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Exposed uses: BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> CHECKING LAST USES for BB173, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {V04 V05 V36} def: {} NEW BLOCK BB174 Setting BB172 as the predecessor for determining incoming variable registers of BB174 DefList: { } N4853 (???,???) [004026] ----------- * IL_OFFSET void INLRT @ 0x57C[E-] REG NA DefList: { } N4855 (???,???) [004027] ----------- * IL_OFFSET void INLRT @ 0x584[E-] REG NA DefList: { } N4857 ( 1, 1) [000618] ----------- * LCL_VAR ref V03 arg3 u:1 NA REG NA $180 DefList: { } N4859 ( 3, 4) [002907] -c--------- * LEA(b+48) byref REG NA Contained DefList: { } N4861 ( 4, 3) [002006] ---XG------ * IND ref REG NA LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> Interval 528: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4861.t2006. IND } N4863 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 NA REG NA BB174 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> DefList: { } N4865 (???,???) [004028] ----------- * IL_OFFSET void INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] REG NA DefList: { } N4867 ( 1, 1) [002008] ----------- * LCL_VAR ref V106 tmp66 u:1 NA REG NA DefList: { } N4869 ( 1, 2) [002009] -c--------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N4871 ( 3, 4) [002010] CEQ-------N--- * JCMP void REG NA LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> CHECKING LAST USES for BB174, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144 V179} ============================== use: {V03} def: {V106} NEW BLOCK BB176 Setting BB174 as the predecessor for determining incoming variable registers of BB176 DefList: { } N4875 (???,???) [004029] ----------- * IL_OFFSET void INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] REG NA DefList: { } N4877 ( 1, 1) [000617] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4879 ( 3, 4) [002909] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4881 ( 4, 3) [002012] ---XG------ * IND int REG NA LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 529: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4881.t2012. IND } N4883 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 NA REG NA BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> DefList: { } N4885 (???,???) [004030] ----------- * IL_OFFSET void INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] REG NA DefList: { } N4887 ( 1, 1) [002015] ----------- * LCL_VAR ref V106 tmp66 u:1 NA REG NA DefList: { } N4889 (???,???) [004174] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4891 ( 3, 3) [002016] ---X------- * IND int REG NA LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 530: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4891.t2016. IND } N4893 ( 1, 2) [002017] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { N4891.t2016. IND } N4895 ( 8, 6) [002018] Nc-X---N-U- * NE int REG NA Contained DefList: { N4891.t2016. IND } N4897 ( 1, 1) [002023] ----------- * LCL_VAR int V107 tmp67 u:1 NA REG NA DefList: { N4891.t2016. IND } N4899 ( 1, 1) [002024] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N4891.t2016. IND } N4901 ( 3, 4) [002913] -c--------- * LEA(b+24) byref REG NA Contained DefList: { N4891.t2016. IND } N4903 ( 4, 3) [002062] n---GO----- * IND int REG NA LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 531: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4891.t2016. IND; N4903.t2062. IND } N4905 ( 9, 5) [002028] Nc--GO-N-U- * GE int REG NA Contained DefList: { N4891.t2016. IND; N4903.t2062. IND } N4907 ( 18, 12) [003754] Jc-XGO-N--- * AND void REG NA Contained DefList: { N4891.t2016. IND; N4903.t2062. IND } N4909 ( 20, 14) [002019] ---XGO----- * JTRUE void REG NA BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB176, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144 V179} ============================== use: {V00 V106} def: {V107} NEW BLOCK BB177 Setting BB176 as the predecessor for determining incoming variable registers of BB177 DefList: { } N4913 (???,???) [004031] ----------- * IL_OFFSET void INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] REG NA DefList: { } N4915 (???,???) [004032] ----------- * IL_OFFSET void INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] REG NA DefList: { } N4917 ( 1, 1) [002917] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4919 ( 1, 2) [002918] -c--------- * CNS_INT long 16 REG NA $200 Contained DefList: { } N4921 ( 3, 4) [002919] -----O----- * ADD byref REG NA $25c LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> Interval 532: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4921.t2919. ADD } N4923 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 NA REG NA BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> DefList: { } N4925 (???,???) [004033] ----------- * IL_OFFSET void INL40 @ ??? <- INLRT @ 0x584[E-] REG NA DefList: { } N4927 ( 1, 1) [002032] ----------- * LCL_VAR int V107 tmp67 u:1 NA REG NA DefList: { } N4929 ( 1, 1) [002037] ----------- * LCL_VAR byref V108 tmp68 u:1 NA REG NA $25c DefList: { } N4931 ( 3, 4) [002922] -c--------- * LEA(b+8) byref REG NA Contained DefList: { } N4933 ( 4, 3) [002038] n---GO----- * IND int REG NA LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 533: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4933.t2038. IND } N4935 ( 9, 11) [002039] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N4937 ( 1, 1) [002036] ----------- * LCL_VAR byref V108 tmp68 u:1 NA (last use) REG NA $25c DefList: { } N4939 ( 3, 2) [002043] n---GO----- * IND byref REG NA LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> Interval 534: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4939.t2043. IND } N4941 ( 1, 1) [002033] ----------- * LCL_VAR int V107 tmp67 u:1 NA REG NA DefList: { N4939.t2043. IND } N4943 ( 2, 3) [002040] -c-------U- * CAST long <- uint REG NA Contained DefList: { N4939.t2043. IND } N4945 ( 1, 2) [002041] -c--------- * CNS_INT long 1 REG NA $204 Contained DefList: { N4939.t2043. IND } N4947 ( 4, 6) [002042] ----------- * BFIZ long REG NA LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 535: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BFIZ BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4939.t2043. IND; N4947.t2042. BFIZ } N4949 ( 8, 9) [002044] ----GO-N--- * ADD byref REG NA BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Interval 536: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4949.t2044. ADD } N4951 ( 1, 2) [002047] -c--------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N4949.t2044. ADD } N4953 ( 1, 1) [002046] ----------- * LCL_VAR ref V106 tmp66 u:1 NA REG NA DefList: { N4949.t2044. ADD } N4955 (???,???) [004176] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N4949.t2044. ADD } N4957 ( 3, 3) [002926] ---X------- * IND int REG NA LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 537: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4949.t2044. ADD; N4957.t2926. IND } N4959 ( 8, 12) [002927] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { N4949.t2044. ADD } N4961 ( 1, 1) [002924] ----------- * LCL_VAR ref V106 tmp66 u:1 NA (last use) REG NA DefList: { N4949.t2044. ADD } N4963 ( 1, 1) [002931] -c--------- * LEA(b+12) byref REG NA Contained DefList: { N4949.t2044. ADD } N4965 ( 5, 4) [002936] n---GO----- * IND ushort REG NA LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> Interval 538: ushort RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4949.t2044. ADD; N4965.t2936. IND } N4967 (???,???) [004034] -A-XGO----- * STOREIND short REG NA BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N4969 (???,???) [004035] ----------- * IL_OFFSET void INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] REG NA DefList: { } N4971 ( 1, 1) [002053] ----------- * LCL_VAR int V107 tmp67 u:1 NA (last use) REG NA DefList: { } N4973 ( 1, 2) [002054] -c--------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N4975 ( 3, 4) [002055] ----------- * ADD int REG NA LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> Interval 539: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4975.t2055. ADD } N4977 ( 1, 1) [002052] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { N4975.t2055. ADD } N4979 ( 3, 4) [002938] -c--------- * LEA(b+8) byref REG NA Contained DefList: { N4975.t2055. ADD } N4981 (???,???) [004036] -A--GO----- * STOREIND int REG NA LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=26550.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CHECKING LAST USES for BB177, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} ============================== use: {V00 V106 V107} def: {V108} NEW BLOCK BB179 Setting BB176 as the predecessor for determining incoming variable registers of BB179 DefList: { } N4985 (???,???) [004037] ----------- * IL_OFFSET void INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] REG NA DefList: { } N4987 ( 1, 1) [002020] ----------- * LCL_VAR byref V00 arg0 u:1 NA REG NA $100 DefList: { } N4989 (???,???) [004268] ----------- * PUTARG_REG byref REG x0 BB179 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB179 regmask=[x0] minReg=1 last fixed wt=26550.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 540: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB179 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x0] minReg=1 fixed wt=800.00> Assigning related to DefList: { N4989.t4268. PUTARG_REG } N4991 ( 1, 1) [002021] ----------- * LCL_VAR ref V106 tmp66 u:1 NA (last use) REG NA DefList: { N4989.t4268. PUTARG_REG } N4993 (???,???) [004269] ----------- * PUTARG_REG ref REG x1 Last use of V106 between PUTARG and CALL. Removing occupied arg regs from preferences: [x0] BB179 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB179 regmask=[x1] minReg=1 last fixed wt=2400.00> Interval 541: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB179 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x1] minReg=1 fixed wt=800.00> DefList: { N4989.t4268. PUTARG_REG; N4993.t4269. PUTARG_REG } N4995 ( 2, 8) [002939] H---------- * CNS_INT(h) long 0x4000000000431d58 ftn REG NA $4f Interval 542: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB179 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N4989.t4268. PUTARG_REG; N4993.t4269. PUTARG_REG; N4995.t2939. CNS_INT } N4997 (???,???) [004270] ----------- * PUTARG_REG long REG x11 BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 last fixed wt=200.00> Interval 543: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB179 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x11] minReg=1 fixed wt=800.00> DefList: { N4989.t4268. PUTARG_REG; N4993.t4269. PUTARG_REG; N4997.t4270. PUTARG_REG } N4999 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void Interval 544: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB179 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB179 regmask=[x0] minReg=1 wt=200.00> BB179 regmask=[x0] minReg=1 last fixed wt=200.00> BB179 regmask=[x1] minReg=1 wt=200.00> BB179 regmask=[x1] minReg=1 last fixed wt=200.00> BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB179 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB179 regmask=[x0] minReg=1 wt=200.00> BB179 regmask=[x1] minReg=1 wt=200.00> BB179 regmask=[x2] minReg=1 wt=200.00> BB179 regmask=[x3] minReg=1 wt=200.00> BB179 regmask=[x4] minReg=1 wt=200.00> BB179 regmask=[x5] minReg=1 wt=200.00> BB179 regmask=[x6] minReg=1 wt=200.00> BB179 regmask=[x7] minReg=1 wt=200.00> BB179 regmask=[x8] minReg=1 wt=200.00> BB179 regmask=[x9] minReg=1 wt=200.00> BB179 regmask=[x10] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x12] minReg=1 wt=200.00> BB179 regmask=[x13] minReg=1 wt=200.00> BB179 regmask=[x14] minReg=1 wt=200.00> BB179 regmask=[x15] minReg=1 wt=200.00> BB179 regmask=[xip0] minReg=1 wt=200.00> BB179 regmask=[xip1] minReg=1 wt=200.00> BB179 regmask=[lr] minReg=1 wt=200.00> CHECKING LAST USES for BB179, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} ============================== use: {V00 V106} def: {} NEW BLOCK BB180 Setting BB174 as the predecessor for determining incoming variable registers of BB180 DefList: { } N5003 (???,???) [004038] ----------- * IL_OFFSET void INLRT @ 0x590[E-] REG NA DefList: { } N5005 ( 1, 2) [002940] ----------- * CNS_INT int 1 REG NA $c1 Interval 545: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> DefList: { N5005.t2940. CNS_INT } N5007 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 NA REG NA BB180 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> Assigning related to STORE_LCL_VAR BB180 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> Exposed uses: BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> CHECKING LAST USES for BB180, liveout={V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} ============================== use: {} def: {V21} NEW BLOCK BB110 Setting BB91 as the predecessor for determining incoming variable registers of BB110 firstColdLoc = 5011 DefList: { } N5011 (???,???) [004153] ----------- * IL_OFFSET void INL17 @ 0x029[E-] <- INLRT @ ??? REG NA DefList: { } N5013 ( 2, 8) [002701] H---------- * CNS_INT(h) long 0x4000000000424a20 ftn REG NA $4a Interval 546: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB110 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> DefList: { N5013.t2701. CNS_INT } N5015 (???,???) [004302] ----------- * PUTARG_REG long REG x11 BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 last fixed wt=0.00> Interval 547: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB110 regmask=[x11] minReg=1 wt=0.00> PUTARG_REG BB110 regmask=[x11] minReg=1 fixed wt=0.00> DefList: { N5015.t4302. PUTARG_REG } N5017 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() REG NA $VN.Void Interval 548: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CALL BB110 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 last fixed wt=0.00> CALL BB110 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> BB110 regmask=[x0] minReg=1 wt=0.00> BB110 regmask=[x1] minReg=1 wt=0.00> BB110 regmask=[x2] minReg=1 wt=0.00> BB110 regmask=[x3] minReg=1 wt=0.00> BB110 regmask=[x4] minReg=1 wt=0.00> BB110 regmask=[x5] minReg=1 wt=0.00> BB110 regmask=[x6] minReg=1 wt=0.00> BB110 regmask=[x7] minReg=1 wt=0.00> BB110 regmask=[x8] minReg=1 wt=0.00> BB110 regmask=[x9] minReg=1 wt=0.00> BB110 regmask=[x10] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x12] minReg=1 wt=0.00> BB110 regmask=[x13] minReg=1 wt=0.00> BB110 regmask=[x14] minReg=1 wt=0.00> BB110 regmask=[x15] minReg=1 wt=0.00> BB110 regmask=[xip0] minReg=1 wt=0.00> BB110 regmask=[xip1] minReg=1 wt=0.00> BB110 regmask=[lr] minReg=1 wt=0.00> CHECKING LAST USES for BB110, liveout={} ============================== use: {} def: {} NEW BLOCK BB254 No predecessor; - throw block; DefList: { } N5021 ( 2, 8) [004303] H---------- * CNS_INT(h) long 0x4000000000421828 ftn REG NA Interval 549: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB254 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> DefList: { N5021.t4303. CNS_INT } N5023 ( 5, 10) [004304] ----------- * IND long REG NA BB254 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> Interval 550: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB254 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> DefList: { N5023.t4304. IND } N5025 ( 14, 2) [004154] --CXG------ * CALL help void CORINFO_HELP_RNGCHKFAIL REG NA BB254 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> BB254 regmask=[x0] minReg=1 wt=0.00> BB254 regmask=[x1] minReg=1 wt=0.00> BB254 regmask=[x2] minReg=1 wt=0.00> BB254 regmask=[x3] minReg=1 wt=0.00> BB254 regmask=[x4] minReg=1 wt=0.00> BB254 regmask=[x5] minReg=1 wt=0.00> BB254 regmask=[x6] minReg=1 wt=0.00> BB254 regmask=[x7] minReg=1 wt=0.00> BB254 regmask=[x8] minReg=1 wt=0.00> BB254 regmask=[x9] minReg=1 wt=0.00> BB254 regmask=[x10] minReg=1 wt=0.00> BB254 regmask=[x11] minReg=1 wt=0.00> BB254 regmask=[x12] minReg=1 wt=0.00> BB254 regmask=[x13] minReg=1 wt=0.00> BB254 regmask=[x14] minReg=1 wt=0.00> BB254 regmask=[x15] minReg=1 wt=0.00> BB254 regmask=[xip0] minReg=1 wt=0.00> BB254 regmask=[xip1] minReg=1 wt=0.00> BB254 regmask=[lr] minReg=1 wt=0.00> CHECKING LAST USES for BB254, liveout={} ============================== use: {} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) byref RefPositions {#0@0 #758@1571 #764@1593 #770@1611 #791@1661 #795@1669 #901@1899 #905@1911 #910@1925 #925@1969 #929@1977 #989@2083 #997@2109 #1003@2127 #1025@2183 #1029@2191 #1116@2369 #1122@2391 #1128@2409 #1152@2469 #1156@2477 #1214@2555 #1218@2567 #1223@2581 #1238@2625 #1242@2633 #1333@2833 #1337@2845 #1342@2859 #1357@2905 #1405@3033 #1466@3071 #1470@3083 #1475@3097 #1490@3143 #1494@3151 #1554@3243 #1558@3255 #1563@3269 #1578@3313 #1582@3321 #1640@3401 #1644@3413 #1649@3427 #1664@3471 #1668@3479 #1709@3501 #1713@3513 #1718@3527 #1733@3573 #1737@3581 #1803@3643 #1819@3669 #2018@4093 #2022@4105 #2027@4119 #2042@4165 #2046@4173 #2106@4279 #2112@4301 #2118@4319 #2142@4379 #2146@4387 #2203@4451 #2209@4473 #2215@4491 #2239@4551 #2243@4559 #2304@4649 #2308@4661 #2313@4675 #2328@4719 #2332@4727 #2418@4881 #2424@4903 #2430@4921 #2454@4981 #2458@4989 #2502@5009} physReg:x0 Preferences=[x19-x28] Interval 1: (V01) byref RefPositions {#2@0 #5@7 #39@27 #70@93 #313@749 #326@781 #345@811 #450@885 #454@903 #456@915 #486@1007 #743@1511 #748@1537 #1390@3007 #1794@3607 #1799@3633 #2516@5009} physReg:x1 Preferences=[x19-x28] Interval 2: (V03) ref RefPositions {#1@0 #518@1081 #525@1111 #752@1551 #983@2063 #1108@2347 #1409@3037 #1812@3663 #2100@4259 #2196@4431 #2412@4861 #2515@5009} physReg:x4 Preferences=[x19-x28] Interval 3: (V04) int RefPositions {#147@172 #289@679 #329@785 #337@799 #1778@3593 #1870@3705 #1873@3708 #1913@3815 #1916@3825 #1919@3828 #1920@3833 #1926@3853 #1929@3873 #1935@3897 #1949@3927 #2408@4849 #2504@5009} physReg:NA Preferences=[x19-x28] Interval 4: (V05) int RefPositions {#150@178 #287@669 #290@680 #295@701 #332@789 #458@933 #462@937 #469@961 #473@965 #482@989 #491@1021 #493@1021 #500@1037 #1393@3011 #1781@3593 #1923@3843 #1924@3847 #1927@3854 #1930@3873 #2407@4849 #2507@5009} physReg:NA Preferences=[x19-x28] Interval 5: (V06) int RefPositions {#153@184 #459@933 #461@937 #468@946 #562@1223 #564@1223 #1785@3593 #1910@3805 #1914@3816 #1974@3975 #2511@5009} physReg:NA Preferences=[x19-x28] Interval 6: (V07) int RefPositions {#154@190 #470@961 #472@965 #479@974 #1789@3593 #1921@3834 #1992@4023 #2403@4825 #2517@5009} physReg:NA Preferences=[x19-x28] Interval 7: (V08) int RefPositions {#483@990 #498@1030 #544@1167 #970@2007 #980@2051 #1074@2223 #1077@2226 #1782@3593 #1973@3975 #1991@4023 #2087@4203 #2097@4247 #2191@4419 #2194@4422 #2396@4807 #2508@5009} physReg:NA Preferences=[x19-x28] Interval 8: (V09) int RefPositions {#155@196 #265@599 #283@654 #324@771 #480@981 #1284@2665 #1359@2907 #1464@3062 #1788@3593 #2514@5009} physReg:NA Preferences=[x19-x28] Interval 9: (V10) int RefPositions {#158@202 #292@689 #294@701 #1932@3885 #1934@3897 #1941@3913 #1950@3928 #1956@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: (V11) int RefPositions {#38@20 #299@717 #448@877 #1937@3909 #1940@3912 #1943@3913 #1953@3934 #1957@3935} physReg:NA Preferences=[x19-x28] Interval 11: (V12) int RefPositions {#159@208 #307@728 #523@1099 #969@2007 #1786@3593 #1942@3913 #1947@3920 #2086@4203 #2512@5009} physReg:NA Preferences=[x19-x28] Interval 12: (V13) int RefPositions {#160@214 #216@421 #219@424 #298@717 #303@720 #320@759 #1875@3717 #1878@3720 #1955@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 13: (V14) int RefPositions {#484@996 #503@1040 #546@1175 #554@1197 #866@1793 #876@1841 #1078@2233 #1081@2236 #1783@3593 #1967@3953 #1969@3965 #1972@3968 #2509@5009} physReg:NA Preferences=[x19-x28] Interval 14: (V15) int RefPositions {#145@164 #161@219 #444@865 #447@876 #505@1047 #1797@3621 #2519@5009} physReg:NA Preferences=[x19-x28] Interval 15: (V16) int RefPositions {#162@220 #171@251 #174@261 #179@272 #222@447 #226@459 #230@471 #233@474 #235@483 #239@503 #245@523 #251@547 #259@581 #267@607 #272@614 #273@619 #277@639 #284@655 #442@858 #443@865 #446@875 #506@1048 #746@1525 #846@1725 #849@1735 #854@1746 #1197@2511 #1201@2523 #1206@2533 #1211@2544 #1286@2675 #1290@2695 #1296@2715 #1302@2739 #1308@2755 #1326@2807 #1366@2927 #1371@2934 #1372@2939 #1376@2959 #1534@3171 #1538@3191 #1546@3221 #1551@3232 #1622@3341 #1626@3361 #1632@3379 #1637@3390 #1776@3593 #1881@3743 #1885@3755 #1891@3765 #1896@3776 #2283@4579 #2287@4599 #2296@4627 #2301@4638 #2373@4747 #2377@4767 #2383@4785 #2386@4788 #2501@5009} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 16: (V17) long RefPositions {#51@52 #62@73 #309@735 #387@827 #843@1715 #1386@2993 #1791@3593 #2520@5009} physReg:NA Preferences=[x19-x28] Interval 17: (V18) int RefPositions {#186@292 #187@297 #189@307 #191@319 #193@331 #199@351 #205@371 #208@385 #210@397 #213@409 #861@1766 #862@1771 #864@1781 #869@1815 #870@1815 #873@1827 #1083@2245 #1085@2257 #1091@2277 #1097@2297 #1100@2311 #1102@2323 #1105@2335 #1354@2891 #1417@3045 #1487@3129 #1498@3155 #1730@3559 #1741@3585 #1888@3757 #1898@3781 #1899@3785 #1985@4002 #2014@4074 #2016@4083 #2039@4151 #2050@4177 #2294@4617 #2371@4739 #2394@4799} physReg:NA Preferences=[x19-x28] Interval 18: (V20) int RefPositions {#517@1074 #576@1261 #579@1264 #580@1271 #703@1405 #706@1421 #972@2019 #975@2033 #981@2051 #1069@2211 #1072@2214 #1779@3593 #2089@4215 #2092@4229 #2098@4247 #2186@4407 #2189@4410 #2505@5009} physReg:NA Preferences=[x19-x28] Interval 19: (V21) int RefPositions {#835@1688 #1792@3593 #2399@4811 #2410@4851 #2500@5008 #2521@5009} physReg:NA Preferences=[x19-x28] Interval 20: (V22) long RefPositions {#169@242 #180@285 #221@447 #238@503 #250@547 #261@591 #276@639 #285@655 #1880@3743 #1954@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 21: (V26) ref RefPositions {#528@1114 #531@1133 #537@1153 #717@1457 #721@1465 #739@1503} physReg:NA Preferences=[x19-x28] Interval 22: (V27) int RefPositions {#529@1120 #710@1433 #713@1445 #716@1448 #719@1459 #724@1477 #737@1503} physReg:NA Preferences=[x19-x28] Interval 23: (V28) int RefPositions {#530@1126 #540@1156 #542@1163 #707@1421 #729@1489 #733@1492 #735@1499 #736@1503} physReg:NA Preferences=[x19-x28] Interval 24: (V29) int RefPositions {#534@1136 #535@1143 #708@1431 #740@1503} physReg:NA Preferences=[x19-x28] Interval 25: (V30) int RefPositions {#543@1164 #572@1239 #574@1251 #727@1480 #730@1489 #738@1503} physReg:NA Preferences=[x19-x28] Interval 26: (V31) int RefPositions {#561@1208 #563@1223 #565@1223} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 27: (V32) int RefPositions {#570@1232 #571@1239 #734@1499 #741@1503} physReg:NA Preferences=[x19-x28] Interval 28: (V33) ref RefPositions {#624@1296 #625@1305 #629@1315 #690@1373 #694@1383} physReg:NA Preferences=[x19-x28] Interval 29: (V34) long RefPositions {#842@1710 #855@1759 #1196@2511 #1289@2695 #1301@2739 #1310@2765 #1328@2817 #1375@2959 #1537@3191 #1625@3361 #1780@3593 #2286@4599 #2376@4767 #2506@5009} physReg:NA Preferences=[x19-x28] Interval 30: (V36) long RefPositions {#844@1716 #878@1851 #888@1871 #893@1880 #1784@3593 #1987@4009 #2000@4049 #2005@4060 #2405@4841 #2510@5009} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 31: (V37) int RefPositions {#1282@2652 #1322@2784 #1401@3029} physReg:NA Preferences=[x5] Interval 32: (V38) int RefPositions {#1283@2658 #1361@2915 #1364@2918 #1380@2975 #1384@2986 #1421@3049} physReg:NA Preferences=[x4] Interval 33: (V43) int RefPositions {#78@112 #86@126 #94@140 #105@155} physReg:NA Preferences=[x2] Interval 34: (V44) int RefPositions {#466@940 #467@945} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 35: (V45) int RefPositions {#477@968 #478@973} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 36: (V46) int RefPositions {#496@1024 #497@1029} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 37: (V49) int RefPositions {#850@1736 #851@1743 #856@1759} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 38: (V50) int RefPositions {#859@1762 #860@1765} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 39: (V51) int RefPositions {#1207@2534 #1208@2541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 40: (V52) int RefPositions {#1547@3222 #1548@3229} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 41: (V53) int RefPositions {#1633@3380 #1634@3387} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 42: (V54) int RefPositions {#1369@2930 #1370@2933} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 43: (V55) int RefPositions {#1396@3014 #1398@3022 #1413@3041} physReg:NA Preferences=[x2] Interval 44: (V56) long RefPositions {#2001@4050 #2002@4057 #2006@4063} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 45: (V57) int RefPositions {#1994@4034 #1998@4042 #2009@4066 #2011@4071} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 46: (V58) int RefPositions {#1976@3986 #1980@3994 #1982@3999} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 47: (V59) int RefPositions {#2297@4628 #2298@4635} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 48: (V61) long RefPositions {#889@1872 #890@1877} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 49: (V63) int RefPositions {#886@1866 #895@1884 #897@1889} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 50: (V64) int RefPositions {#545@1168 #548@1183 #552@1193} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 51: (V65) int RefPositions {#549@1184 #553@1194 #557@1205} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 52: (V66) int RefPositions {#550@1188 #555@1198 #558@1205} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 53: (V67) int RefPositions {#568@1226 #569@1231} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 54: (V69) byref RefPositions {#316@752 #317@755 #322@763} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 55: (V70) int RefPositions {#335@792 #338@800 #341@807} physReg:NA Preferences=[x1] Interval 56: (V71) int RefPositions {#175@262 #176@269 #181@285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 57: (V72) int RefPositions {#184@288 #185@291} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 58: (V73) int RefPositions {#270@610 #271@613} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 59: (V74) int RefPositions {#1892@3766 #1893@3773} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 60: (V76) byref RefPositions {#42@30 #43@39 #46@45} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 61: (V83) long RefPositions {#641@1340 #642@1347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 62: (V86) ref RefPositions {#755@1554 #756@1561 #762@1581 #785@1645 #799@1673} physReg:NA Preferences=[x1] Interval 63: (V87) int RefPositions {#761@1574 #767@1599 #776@1625 #780@1637 #789@1655} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 64: (V88) byref RefPositions {#773@1614 #774@1623 #778@1629} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 65: (V91) int RefPositions {#904@1902 #907@1913 #916@1937 #921@1955 #923@1963} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 66: (V92) int RefPositions {#900@1892 #922@1955 #933@1981} physReg:NA Preferences=[x1] Interval 67: (V93) byref RefPositions {#913@1928 #914@1935 #918@1941} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 68: (V95) ref RefPositions {#986@2066 #987@2073 #993@2093 #1019@2167 #1033@2195} physReg:NA Preferences=[x1] Interval 69: (V96) int RefPositions {#992@2086 #1000@2115 #1009@2141 #1013@2153 #1023@2177} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 70: (V97) byref RefPositions {#1006@2130 #1007@2139 #1011@2145} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 71: (V99) int RefPositions {#2021@4096 #2024@4107 #2033@4133 #2038@4151 #2040@4159} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 72: (V100) byref RefPositions {#2030@4122 #2031@4131 #2035@4137} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 73: (V102) ref RefPositions {#2103@4262 #2104@4269 #2110@4289 #2133@4355 #2136@4363 #2150@4391} physReg:NA Preferences=[x1] Interval 74: (V103) int RefPositions {#2109@4282 #2115@4307 #2124@4333 #2128@4345 #2140@4373} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 75: (V104) byref RefPositions {#2121@4322 #2122@4331 #2126@4337} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 76: (V106) ref RefPositions {#2415@4864 #2416@4871 #2422@4891 #2445@4957 #2448@4965 #2462@4993} physReg:NA Preferences=[x1] Interval 77: (V107) int RefPositions {#2421@4884 #2427@4909 #2436@4935 #2440@4947 #2452@4975} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 78: (V108) byref RefPositions {#2433@4924 #2434@4933 #2438@4939} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 79: (V110) ref RefPositions {#1111@2350 #1113@2359 #1114@2361 #1120@2379 #1143@2445 #1146@2453 #1160@2481} physReg:NA Preferences=[x1] Interval 80: (V111) int RefPositions {#1119@2372 #1125@2397 #1134@2423 #1138@2435 #1150@2463} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 81: (V112) byref RefPositions {#1131@2412 #1132@2421 #1136@2427} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 82: (V114) ref RefPositions {#2199@4434 #2200@4441 #2201@4443 #2207@4461 #2230@4527 #2233@4535 #2247@4563} physReg:NA Preferences=[x1] Interval 83: (V115) int RefPositions {#2206@4454 #2212@4479 #2221@4505 #2225@4517 #2237@4545} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 84: (V116) byref RefPositions {#2218@4494 #2219@4503 #2223@4509} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 85: (V118) int RefPositions {#2307@4652 #2310@4663 #2319@4687 #2324@4705 #2326@4713} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 86: (V119) int RefPositions {#2303@4642 #2325@4705 #2336@4731} physReg:NA Preferences=[x1] Interval 87: (V120) byref RefPositions {#2316@4678 #2317@4685 #2321@4691} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 88: (V122) int RefPositions {#1217@2558 #1220@2569 #1229@2593 #1234@2611 #1236@2619} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 89: (V123) int RefPositions {#1213@2548 #1235@2611 #1246@2637} physReg:NA Preferences=[x1] Interval 90: (V124) byref RefPositions {#1226@2584 #1227@2591 #1231@2597} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 91: (V126) int RefPositions {#1336@2836 #1339@2847 #1348@2873 #1353@2891 #1355@2899} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 92: (V127) byref RefPositions {#1345@2862 #1346@2871 #1350@2877} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 93: (V129) int RefPositions {#1469@3074 #1472@3085 #1481@3111 #1486@3129 #1488@3137} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 94: (V130) byref RefPositions {#1478@3100 #1479@3109 #1483@3115} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 95: (V132) int RefPositions {#1557@3246 #1560@3257 #1569@3281 #1574@3299 #1576@3307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 96: (V133) int RefPositions {#1553@3236 #1575@3299 #1586@3325} physReg:NA Preferences=[x1] Interval 97: (V134) byref RefPositions {#1566@3272 #1567@3279 #1571@3285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 98: (V136) int RefPositions {#1643@3404 #1646@3415 #1655@3439 #1660@3457 #1662@3465} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 99: (V137) int RefPositions {#1639@3394 #1661@3457 #1672@3483} physReg:NA Preferences=[x1] Interval 100: (V138) byref RefPositions {#1652@3430 #1653@3437 #1657@3443} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 101: (V140) int RefPositions {#1712@3504 #1715@3515 #1724@3541 #1729@3559 #1731@3567} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 102: (V141) byref RefPositions {#1721@3530 #1722@3539 #1726@3545} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 103: (V143) byref (field) RefPositions {#511@1064 #653@1357 #699@1392 #705@1421 #974@2033 #1790@3593 #2091@4229 #2518@5009} physReg:NA Preferences=[x19-x28] Interval 104: (V144) int (field) RefPositions {#514@1068 #581@1271 #583@1283 #635@1327 #638@1337 #701@1396 #704@1405 #973@2019 #1787@3593 #2090@4215 #2513@5009} physReg:NA Preferences=[x19-x28] Interval 105: (V147) byref (field) RefPositions {#56@60 #66@83 #88@131} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 106: (V148) int (field) RefPositions {#61@68 #68@87 #90@135} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 107: (V149) byref (field) RefPositions {#75@104 #81@118 #89@132 #97@145} physReg:NA Preferences=[x0] Interval 108: (V150) int (field) RefPositions {#77@108 #83@122 #91@136 #101@149} physReg:NA Preferences=[x1] Interval 109: (V151) byref (field) RefPositions {#509@1056 #510@1063} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 110: (V155) byref (field) RefPositions {#67@84 #74@103 #80@117} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 111: (V156) int (field) RefPositions {#69@88 #76@107 #82@121} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 112: (V157) byref (field) RefPositions {#164@226 #165@231 #166@237} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 113: (V159) byref (field) RefPositions {#628@1308 #633@1321} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 114: (V160) int (field) RefPositions {#632@1318 #636@1327} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 115: (V161) byref (field) RefPositions {#634@1322 #649@1353} physReg:NA Preferences=[x0] Interval 116: (V163) byref (field) RefPositions {#693@1376 #698@1391} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 117: (V164) int (field) RefPositions {#697@1386 #700@1395} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 118: (V165) byref (field) RefPositions {#837@1694 #838@1699 #839@1705} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 119: (V167) long RefPositions {#49@48 #50@51} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 120: (V168) long RefPositions {#167@238 #168@241} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 121: (V169) long RefPositions {#840@1706 #841@1709} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 122: (V171) int RefPositions {#1884@3746 #1887@3755 #1889@3757 #1897@3781} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 123: (V172) int RefPositions {#2290@4602 #2291@4607 #2293@4617 #2302@4641 #2380@4770 #2381@4775} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 124: (V173) int RefPositions {#1629@3364 #1630@3369 #1638@3393} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 125: (V174) int RefPositions {#225@450 #228@459 #242@506 #243@511 #254@550 #255@555 #257@567} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 126: (V175) int RefPositions {#1541@3194 #1542@3199 #1544@3211 #1552@3235} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 127: (V176) int RefPositions {#1200@2514 #1203@2523 #1204@2525 #1212@2547 #1293@2698 #1294@2703 #1305@2742 #1306@2747 #1324@2793} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 128: (V177) int RefPositions {#881@1854 #882@1859 #894@1883} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 129: (V178) int RefPositions {#489@1010 #490@1021 #492@1021 #499@1037} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 130: (V179) int RefPositions {#59@64 #60@67 #172@251 #227@459 #236@483 #248@527 #274@619 #847@1725 #1202@2523 #1287@2675 #1299@2719 #1373@2939 #1535@3171 #1623@3341 #1777@3593 #1886@3755 #2284@4579 #2374@4747 #2503@5009} physReg:NA Preferences=[x19-x28] Interval 131: (V180) byref RefPositions {#54@56 #55@59 #163@225 #392@839 #836@1693 #1958@3935} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 132: (V181) int RefPositions {#996@2096 #999@2115 #1018@2161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 133: (V182) int RefPositions {#196@334 #197@339 #1863@3691} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 134: (V183) int RefPositions {#202@354 #203@359 #1902@3791} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 135: (V184) int RefPositions {#1088@2260 #1089@2265 #1960@3939} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 136: (V185) int RefPositions {#1094@2280 #1095@2285 #2388@4793} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 137: byref (specialPutArg) RefPositions {#7@8 #15@13} physReg:NA Preferences=[x0] RelatedInterval Interval 138: long (constant) RefPositions {#8@10 #10@11} physReg:NA Preferences=[x11] Interval 139: long RefPositions {#12@12 #17@13} physReg:NA Preferences=[x11] Interval 140: int (INTERNAL) RefPositions {#13@13 #18@13} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 141: byref RefPositions {#40@28 #41@29} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 142: int RefPositions {#44@40 #45@41} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 143: byref RefPositions {#47@46 #48@47} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 144: byref RefPositions {#52@54 #53@55} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 145: int RefPositions {#57@62 #58@63} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 146: ubyte RefPositions {#63@74 #64@77} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 147: bool RefPositions {#71@94 #72@97} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 148: int (constant) RefPositions {#84@124 #85@125} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 149: int (constant) RefPositions {#92@138 #93@139} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 150: byref RefPositions {#99@146 #115@161} physReg:NA Preferences=[x0] Interval 151: int RefPositions {#103@150 #117@161} physReg:NA Preferences=[x1] Interval 152: int RefPositions {#107@156 #119@161} physReg:NA Preferences=[x2] Interval 153: long (constant) RefPositions {#108@158 #110@159} physReg:NA Preferences=[x11] Interval 154: long RefPositions {#112@160 #121@161} physReg:NA Preferences=[x11] Interval 155: int (INTERNAL) RefPositions {#113@161 #122@161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 156: int RefPositions {#143@162 #144@163} physReg:NA Preferences=[x0] RelatedInterval Interval 157: int (constant) RefPositions {#148@176 #149@177} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 158: int (constant) RefPositions {#151@182 #152@183} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 159: int (constant) RefPositions {#156@200 #157@201} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 160: int RefPositions {#177@270 #178@271} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 161: ushort RefPositions {#182@286 #183@287} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 162: int RefPositions {#194@332 #195@333} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 163: int RefPositions {#200@352 #201@353} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 164: int (constant) RefPositions {#212@408 #214@409} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 165: int RefPositions {#217@422 #218@423} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 166: ushort RefPositions {#223@448 #224@449} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 167: int RefPositions {#231@472 #232@473} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 168: ushort RefPositions {#240@504 #241@505} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 169: int RefPositions {#246@524 #247@527} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 170: ushort RefPositions {#252@548 #253@549} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 171: int RefPositions {#260@582 #262@591} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 172: ushort RefPositions {#263@592 #264@595} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 173: int RefPositions {#268@608 #269@609} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 174: ushort RefPositions {#278@640 #279@643} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 175: int (constant) RefPositions {#281@652 #282@653} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 176: int (constant) RefPositions {#297@714 #300@717} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 177: int RefPositions {#301@718 #302@719} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 178: int (constant) RefPositions {#305@726 #306@727} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 179: ubyte RefPositions {#310@736 #311@739} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 180: byref RefPositions {#314@750 #315@751} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 181: int RefPositions {#318@756 #319@759} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 182: int RefPositions {#321@760 #323@763} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 183: int RefPositions {#327@782 #328@785} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 184: int RefPositions {#330@786 #331@789} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 185: int RefPositions {#333@790 #334@791} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 186: int RefPositions {#343@808 #360@821} physReg:NA Preferences=[x1] Interval 187: byref (specialPutArg) RefPositions {#347@812 #362@821} physReg:NA Preferences=[x0] RelatedInterval Interval 188: long (constant) RefPositions {#348@814 #350@815} physReg:NA Preferences=[x11] Interval 189: long RefPositions {#352@816 #364@821} physReg:NA Preferences=[x11] Interval 190: int (constant) RefPositions {#353@818 #355@819} physReg:NA Preferences=[x2] Interval 191: int RefPositions {#357@820 #366@821} physReg:NA Preferences=[x2] Interval 192: int (INTERNAL) RefPositions {#358@821 #367@821} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 193: ubyte RefPositions {#388@828 #389@831} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 194: byref (specialPutArg) RefPositions {#394@840 #412@855} physReg:NA Preferences=[x0] RelatedInterval Interval 195: long RefPositions {#395@842 #397@843} physReg:NA Preferences=[x1] Interval 196: long RefPositions {#399@844 #414@855} physReg:NA Preferences=[x1] Interval 197: long (constant) RefPositions {#400@848 #402@849} physReg:NA Preferences=[x11] Interval 198: long RefPositions {#404@850 #416@855} physReg:NA Preferences=[x11] Interval 199: int (constant) RefPositions {#405@852 #407@853} physReg:NA Preferences=[x2] Interval 200: int RefPositions {#409@854 #418@855} physReg:NA Preferences=[x2] Interval 201: int (INTERNAL) RefPositions {#410@855 #419@855} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 202: int RefPositions {#440@856 #441@857} physReg:NA Preferences=[x0] RelatedInterval Interval 203: ubyte RefPositions {#451@886 #452@889} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 204: int RefPositions {#460@934 #463@937} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 205: int RefPositions {#464@938 #465@939} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 206: int RefPositions {#471@962 #474@965} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 207: int RefPositions {#475@966 #476@967} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 208: int RefPositions {#487@1008 #488@1009} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 209: int RefPositions {#494@1022 #495@1023} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 210: int RefPositions {#501@1038 #502@1039} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 211: long RefPositions {#507@1054 #508@1055} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 212: int (constant) RefPositions {#512@1066 #513@1067} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 213: int (constant) RefPositions {#515@1072 #516@1073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 214: ref RefPositions {#519@1082 #520@1085} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 215: int RefPositions {#521@1086 #522@1099} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 216: ref RefPositions {#526@1112 #527@1113} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 217: int RefPositions {#532@1134 #533@1135} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 218: int RefPositions {#538@1154 #539@1155} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 219: int RefPositions {#559@1206 #560@1207} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 220: int RefPositions {#566@1224 #567@1225} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 221: int RefPositions {#577@1262 #578@1263} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 222: int RefPositions {#584@1284 #585@1285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 223: long RefPositions {#586@1286 #588@1287} physReg:NA Preferences=[x0] Interval 224: long RefPositions {#590@1288 #598@1293} physReg:NA Preferences=[x0] Interval 225: long (constant) RefPositions {#591@1290 #593@1291} physReg:NA Preferences=[x11] Interval 226: long RefPositions {#595@1292 #600@1293} physReg:NA Preferences=[x11] Interval 227: int (INTERNAL) RefPositions {#596@1293 #601@1293} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 228: ref RefPositions {#622@1294 #623@1295} physReg:NA Preferences=[x0] RelatedInterval Interval 229: byref RefPositions {#626@1306 #627@1307} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 230: int RefPositions {#630@1316 #631@1317} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 231: long RefPositions {#639@1338 #640@1339} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 232: long RefPositions {#643@1348 #645@1349} physReg:NA Preferences=[x2] Interval 233: long RefPositions {#647@1350 #663@1363} physReg:NA Preferences=[x2] Interval 234: byref RefPositions {#651@1354 #665@1363} physReg:NA Preferences=[x0] Interval 235: byref RefPositions {#655@1358 #667@1363} physReg:NA Preferences=[x1] Interval 236: long (constant) RefPositions {#656@1360 #658@1361} physReg:NA Preferences=[x11] Interval 237: long RefPositions {#660@1362 #669@1363} physReg:NA Preferences=[x11] Interval 238: int (INTERNAL) RefPositions {#661@1363 #670@1363} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 239: byref RefPositions {#691@1374 #692@1375} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 240: int RefPositions {#695@1384 #696@1385} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 241: int RefPositions {#709@1432 #711@1433} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 242: int RefPositions {#714@1446 #715@1447} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 243: int RefPositions {#718@1458 #720@1459} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 244: byref RefPositions {#722@1466 #723@1477} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 245: int RefPositions {#725@1478 #726@1479} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 246: int RefPositions {#731@1490 #732@1491} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 247: bool RefPositions {#744@1512 #745@1525} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 248: int RefPositions {#749@1538 #750@1541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 249: ref RefPositions {#753@1552 #754@1553} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 250: int RefPositions {#759@1572 #760@1573} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 251: int RefPositions {#763@1582 #766@1599} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 252: int RefPositions {#765@1594 #768@1599} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 253: byref RefPositions {#771@1612 #772@1613} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 254: int RefPositions {#775@1624 #777@1625} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 255: byref RefPositions {#779@1630 #782@1639} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 256: long RefPositions {#781@1638 #783@1639} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 257: byref RefPositions {#784@1640 #787@1647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 258: ushort RefPositions {#786@1646 #788@1647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 259: int RefPositions {#790@1656 #792@1661} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 260: byref (specialPutArg) RefPositions {#797@1670 #809@1679} physReg:NA Preferences=[x0] RelatedInterval Interval 261: ref RefPositions {#801@1674 #811@1679} physReg:NA Preferences=[x1] Interval 262: long (constant) RefPositions {#802@1676 #804@1677} physReg:NA Preferences=[x11] Interval 263: long RefPositions {#806@1678 #813@1679} physReg:NA Preferences=[x11] Interval 264: int (INTERNAL) RefPositions {#807@1679 #814@1679} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 265: int RefPositions {#852@1744 #853@1745} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 266: ushort RefPositions {#857@1760 #858@1761} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 267: int (constant) RefPositions {#868@1810 #871@1815} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 268: ubyte RefPositions {#879@1852 #880@1853} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 269: int (constant) RefPositions {#884@1864 #885@1865} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 270: long RefPositions {#891@1878 #892@1879} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 271: int RefPositions {#898@1890 #899@1891} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 272: int RefPositions {#902@1900 #903@1901} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 273: int RefPositions {#906@1912 #908@1913} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 274: byref RefPositions {#911@1926 #912@1927} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 275: int RefPositions {#915@1936 #917@1937} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 276: byref RefPositions {#919@1942 #920@1955} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 277: int RefPositions {#924@1964 #926@1969} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 278: byref (specialPutArg) RefPositions {#931@1978 #943@1987} physReg:NA Preferences=[x0] RelatedInterval Interval 279: int RefPositions {#935@1982 #945@1987} physReg:NA Preferences=[x1] Interval 280: long (constant) RefPositions {#936@1984 #938@1985} physReg:NA Preferences=[x11] Interval 281: long RefPositions {#940@1986 #947@1987} physReg:NA Preferences=[x11] Interval 282: int (INTERNAL) RefPositions {#941@1987 #948@1987} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 283: int RefPositions {#976@2034 #977@2037} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 284: int RefPositions {#978@2038 #979@2051} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 285: ref RefPositions {#984@2064 #985@2065} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 286: int RefPositions {#990@2084 #991@2085} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 287: int RefPositions {#994@2094 #995@2095} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 288: int RefPositions {#998@2110 #1001@2115} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 289: byref RefPositions {#1004@2128 #1005@2129} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 290: int RefPositions {#1008@2140 #1010@2141} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 291: byref RefPositions {#1012@2146 #1015@2155} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 292: long RefPositions {#1014@2154 #1016@2155} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 293: byref RefPositions {#1017@2156 #1021@2169} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 294: ushort RefPositions {#1020@2168 #1022@2169} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 295: int RefPositions {#1024@2178 #1026@2183} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 296: byref (specialPutArg) RefPositions {#1031@2192 #1043@2201} physReg:NA Preferences=[x0] RelatedInterval Interval 297: ref RefPositions {#1035@2196 #1045@2201} physReg:NA Preferences=[x1] Interval 298: long (constant) RefPositions {#1036@2198 #1038@2199} physReg:NA Preferences=[x11] Interval 299: long RefPositions {#1040@2200 #1047@2201} physReg:NA Preferences=[x11] Interval 300: int (INTERNAL) RefPositions {#1041@2201 #1048@2201} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 301: int RefPositions {#1070@2212 #1071@2213} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 302: int RefPositions {#1075@2224 #1076@2225} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 303: int RefPositions {#1079@2234 #1080@2235} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 304: int RefPositions {#1086@2258 #1087@2259} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 305: int RefPositions {#1092@2278 #1093@2279} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 306: int (constant) RefPositions {#1104@2334 #1106@2335} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 307: ref RefPositions {#1109@2348 #1110@2349} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 308: int RefPositions {#1117@2370 #1118@2371} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 309: int RefPositions {#1121@2380 #1124@2397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 310: int RefPositions {#1123@2392 #1126@2397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 311: byref RefPositions {#1129@2410 #1130@2411} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 312: int RefPositions {#1133@2422 #1135@2423} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 313: byref RefPositions {#1137@2428 #1140@2437} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 314: long RefPositions {#1139@2436 #1141@2437} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 315: byref RefPositions {#1142@2438 #1148@2455} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 316: int RefPositions {#1144@2446 #1145@2447} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 317: ushort RefPositions {#1147@2454 #1149@2455} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 318: int RefPositions {#1151@2464 #1153@2469} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 319: byref (specialPutArg) RefPositions {#1158@2478 #1170@2487} physReg:NA Preferences=[x0] RelatedInterval Interval 320: ref RefPositions {#1162@2482 #1172@2487} physReg:NA Preferences=[x1] Interval 321: long (constant) RefPositions {#1163@2484 #1165@2485} physReg:NA Preferences=[x11] Interval 322: long RefPositions {#1167@2486 #1174@2487} physReg:NA Preferences=[x11] Interval 323: int (INTERNAL) RefPositions {#1168@2487 #1175@2487} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 324: ushort RefPositions {#1198@2512 #1199@2513} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 325: int RefPositions {#1209@2542 #1210@2543} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 326: int RefPositions {#1215@2556 #1216@2557} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 327: int RefPositions {#1219@2568 #1221@2569} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 328: byref RefPositions {#1224@2582 #1225@2583} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 329: int RefPositions {#1228@2592 #1230@2593} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 330: byref RefPositions {#1232@2598 #1233@2611} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 331: int RefPositions {#1237@2620 #1239@2625} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 332: byref (specialPutArg) RefPositions {#1244@2634 #1256@2643} physReg:NA Preferences=[x0] RelatedInterval Interval 333: int RefPositions {#1248@2638 #1258@2643} physReg:NA Preferences=[x1] Interval 334: long (constant) RefPositions {#1249@2640 #1251@2641} physReg:NA Preferences=[x11] Interval 335: long RefPositions {#1253@2642 #1260@2643} physReg:NA Preferences=[x11] Interval 336: int (INTERNAL) RefPositions {#1254@2643 #1261@2643} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 337: ushort RefPositions {#1291@2696 #1292@2697} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 338: int RefPositions {#1297@2716 #1298@2719} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 339: ushort RefPositions {#1303@2740 #1304@2741} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 340: int RefPositions {#1307@2748 #1315@2771} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 341: int RefPositions {#1309@2756 #1311@2765} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 342: ushort RefPositions {#1312@2766 #1313@2769} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 343: int RefPositions {#1314@2770 #1316@2771} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 344: int RefPositions {#1317@2772 #1318@2773} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 345: int (constant) RefPositions {#1320@2782 #1321@2783} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 346: int RefPositions {#1327@2808 #1329@2817} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 347: ushort RefPositions {#1330@2818 #1331@2821} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 348: int RefPositions {#1334@2834 #1335@2835} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 349: int RefPositions {#1338@2846 #1340@2847} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 350: byref RefPositions {#1343@2860 #1344@2861} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 351: int RefPositions {#1347@2872 #1349@2873} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 352: byref RefPositions {#1351@2878 #1352@2891} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 353: int RefPositions {#1356@2900 #1358@2905} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 354: int RefPositions {#1362@2916 #1363@2917} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 355: int RefPositions {#1367@2928 #1368@2929} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 356: ushort RefPositions {#1377@2960 #1378@2963} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 357: int (constant) RefPositions {#1382@2984 #1383@2985} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 358: ubyte RefPositions {#1387@2994 #1388@2997} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 359: int RefPositions {#1391@3008 #1392@3011} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 360: int RefPositions {#1394@3012 #1395@3013} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 361: int RefPositions {#1403@3030 #1431@3055} physReg:NA Preferences=[x5] Interval 362: byref (specialPutArg) RefPositions {#1407@3034 #1433@3055} physReg:NA Preferences=[x0] RelatedInterval Interval 363: ref (specialPutArg) RefPositions {#1411@3038 #1435@3055} physReg:NA Preferences=[x1] RelatedInterval Interval 364: int RefPositions {#1415@3042 #1437@3055} physReg:NA Preferences=[x2] Interval 365: int RefPositions {#1419@3046 #1439@3055} physReg:NA Preferences=[x3] Interval 366: int RefPositions {#1423@3050 #1441@3055} physReg:NA Preferences=[x4] Interval 367: long (constant) RefPositions {#1424@3052 #1426@3053} physReg:NA Preferences=[x11] Interval 368: long RefPositions {#1428@3054 #1443@3055} physReg:NA Preferences=[x11] Interval 369: int (INTERNAL) RefPositions {#1429@3055 #1444@3055} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 370: int RefPositions {#1467@3072 #1468@3073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 371: int RefPositions {#1471@3084 #1473@3085} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 372: byref RefPositions {#1476@3098 #1477@3099} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 373: int RefPositions {#1480@3110 #1482@3111} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 374: byref RefPositions {#1484@3116 #1485@3129} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 375: int RefPositions {#1489@3138 #1491@3143} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 376: byref (specialPutArg) RefPositions {#1496@3152 #1508@3161} physReg:NA Preferences=[x0] RelatedInterval Interval 377: int RefPositions {#1500@3156 #1510@3161} physReg:NA Preferences=[x1] Interval 378: long (constant) RefPositions {#1501@3158 #1503@3159} physReg:NA Preferences=[x11] Interval 379: long RefPositions {#1505@3160 #1512@3161} physReg:NA Preferences=[x11] Interval 380: int (INTERNAL) RefPositions {#1506@3161 #1513@3161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 381: ushort RefPositions {#1539@3192 #1540@3193} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 382: int RefPositions {#1549@3230 #1550@3231} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 383: int RefPositions {#1555@3244 #1556@3245} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 384: int RefPositions {#1559@3256 #1561@3257} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 385: byref RefPositions {#1564@3270 #1565@3271} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 386: int RefPositions {#1568@3280 #1570@3281} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 387: byref RefPositions {#1572@3286 #1573@3299} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 388: int RefPositions {#1577@3308 #1579@3313} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 389: byref (specialPutArg) RefPositions {#1584@3322 #1596@3331} physReg:NA Preferences=[x0] RelatedInterval Interval 390: int RefPositions {#1588@3326 #1598@3331} physReg:NA Preferences=[x1] Interval 391: long (constant) RefPositions {#1589@3328 #1591@3329} physReg:NA Preferences=[x11] Interval 392: long RefPositions {#1593@3330 #1600@3331} physReg:NA Preferences=[x11] Interval 393: int (INTERNAL) RefPositions {#1594@3331 #1601@3331} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 394: ushort RefPositions {#1627@3362 #1628@3363} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 395: int RefPositions {#1635@3388 #1636@3389} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 396: int RefPositions {#1641@3402 #1642@3403} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 397: int RefPositions {#1645@3414 #1647@3415} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 398: byref RefPositions {#1650@3428 #1651@3429} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 399: int RefPositions {#1654@3438 #1656@3439} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 400: byref RefPositions {#1658@3444 #1659@3457} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 401: int RefPositions {#1663@3466 #1665@3471} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 402: byref (specialPutArg) RefPositions {#1670@3480 #1682@3489} physReg:NA Preferences=[x0] RelatedInterval Interval 403: int RefPositions {#1674@3484 #1684@3489} physReg:NA Preferences=[x1] Interval 404: long (constant) RefPositions {#1675@3486 #1677@3487} physReg:NA Preferences=[x11] Interval 405: long RefPositions {#1679@3488 #1686@3489} physReg:NA Preferences=[x11] Interval 406: int (INTERNAL) RefPositions {#1680@3489 #1687@3489} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 407: int RefPositions {#1710@3502 #1711@3503} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 408: int RefPositions {#1714@3514 #1716@3515} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 409: byref RefPositions {#1719@3528 #1720@3529} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 410: int RefPositions {#1723@3540 #1725@3541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 411: byref RefPositions {#1727@3546 #1728@3559} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 412: int RefPositions {#1732@3568 #1734@3573} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 413: byref (specialPutArg) RefPositions {#1739@3582 #1751@3591} physReg:NA Preferences=[x0] RelatedInterval Interval 414: int RefPositions {#1743@3586 #1753@3591} physReg:NA Preferences=[x1] Interval 415: long (constant) RefPositions {#1744@3588 #1746@3589} physReg:NA Preferences=[x11] Interval 416: long RefPositions {#1748@3590 #1755@3591} physReg:NA Preferences=[x11] Interval 417: int (INTERNAL) RefPositions {#1749@3591 #1756@3591} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 418: bool RefPositions {#1795@3608 #1796@3621} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 419: int RefPositions {#1800@3634 #1801@3637} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 420: int RefPositions {#1802@3638 #1807@3649} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 421: int RefPositions {#1804@3644 #1805@3647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 422: int RefPositions {#1806@3648 #1808@3649} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 423: int RefPositions {#1809@3650 #1810@3651} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 424: ref RefPositions {#1813@3664 #1815@3665} physReg:NA Preferences=[x2] Interval 425: ref RefPositions {#1817@3666 #1834@3679} physReg:NA Preferences=[x2] Interval 426: byref RefPositions {#1821@3670 #1836@3679} physReg:NA Preferences=[x0] Interval 427: long (constant) RefPositions {#1822@3672 #1824@3673} physReg:NA Preferences=[x11] Interval 428: long RefPositions {#1826@3674 #1838@3679} physReg:NA Preferences=[x11] Interval 429: int (constant) RefPositions {#1827@3676 #1829@3677} physReg:NA Preferences=[x1] Interval 430: int RefPositions {#1831@3678 #1840@3679} physReg:NA Preferences=[x1] Interval 431: int (INTERNAL) RefPositions {#1832@3679 #1841@3679} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 432: long RefPositions {#1864@3692 #1867@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 433: long RefPositions {#1865@3694 #1868@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 434: int (INTERNAL) RefPositions {#1866@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 435: int RefPositions {#1871@3706 #1872@3707} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 436: int RefPositions {#1876@3718 #1877@3719} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 437: ushort RefPositions {#1882@3744 #1883@3745} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 438: int RefPositions {#1894@3774 #1895@3775} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 439: long RefPositions {#1903@3792 #1906@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 440: long RefPositions {#1904@3794 #1907@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 441: int (INTERNAL) RefPositions {#1905@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 442: int (constant) RefPositions {#1909@3804 #1911@3805} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 443: int RefPositions {#1917@3826 #1918@3827} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 444: int RefPositions {#1938@3910 #1939@3911} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 445: int (constant) RefPositions {#1945@3918 #1946@3919} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 446: int (constant) RefPositions {#1951@3932 #1952@3933} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 447: long RefPositions {#1961@3940 #1964@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 448: long RefPositions {#1962@3942 #1965@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 449: int (INTERNAL) RefPositions {#1963@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 450: int RefPositions {#1970@3966 #1971@3967} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 451: int (constant) RefPositions {#1978@3992 #1979@3993} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 452: int RefPositions {#1983@4000 #1984@4001} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 453: ubyte RefPositions {#1988@4010 #1989@4013} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 454: int (constant) RefPositions {#1996@4040 #1997@4041} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 455: long RefPositions {#2003@4058 #2004@4059} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 456: ubyte RefPositions {#2007@4064 #2008@4065} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 457: int RefPositions {#2012@4072 #2013@4073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 458: int RefPositions {#2019@4094 #2020@4095} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 459: int RefPositions {#2023@4106 #2025@4107} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 460: byref RefPositions {#2028@4120 #2029@4121} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 461: int RefPositions {#2032@4132 #2034@4133} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 462: byref RefPositions {#2036@4138 #2037@4151} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 463: int RefPositions {#2041@4160 #2043@4165} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 464: byref (specialPutArg) RefPositions {#2048@4174 #2060@4183} physReg:NA Preferences=[x0] RelatedInterval Interval 465: int RefPositions {#2052@4178 #2062@4183} physReg:NA Preferences=[x1] Interval 466: long (constant) RefPositions {#2053@4180 #2055@4181} physReg:NA Preferences=[x11] Interval 467: long RefPositions {#2057@4182 #2064@4183} physReg:NA Preferences=[x11] Interval 468: int (INTERNAL) RefPositions {#2058@4183 #2065@4183} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 469: int RefPositions {#2093@4230 #2094@4233} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 470: int RefPositions {#2095@4234 #2096@4247} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 471: ref RefPositions {#2101@4260 #2102@4261} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 472: int RefPositions {#2107@4280 #2108@4281} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 473: int RefPositions {#2111@4290 #2114@4307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 474: int RefPositions {#2113@4302 #2116@4307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 475: byref RefPositions {#2119@4320 #2120@4321} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 476: int RefPositions {#2123@4332 #2125@4333} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 477: byref RefPositions {#2127@4338 #2130@4347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 478: long RefPositions {#2129@4346 #2131@4347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 479: byref RefPositions {#2132@4348 #2138@4365} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 480: int RefPositions {#2134@4356 #2135@4357} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 481: ushort RefPositions {#2137@4364 #2139@4365} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 482: int RefPositions {#2141@4374 #2143@4379} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 483: byref (specialPutArg) RefPositions {#2148@4388 #2160@4397} physReg:NA Preferences=[x0] RelatedInterval Interval 484: ref RefPositions {#2152@4392 #2162@4397} physReg:NA Preferences=[x1] Interval 485: long (constant) RefPositions {#2153@4394 #2155@4395} physReg:NA Preferences=[x11] Interval 486: long RefPositions {#2157@4396 #2164@4397} physReg:NA Preferences=[x11] Interval 487: int (INTERNAL) RefPositions {#2158@4397 #2165@4397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 488: int RefPositions {#2187@4408 #2188@4409} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 489: int RefPositions {#2192@4420 #2193@4421} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 490: ref RefPositions {#2197@4432 #2198@4433} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 491: int RefPositions {#2204@4452 #2205@4453} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 492: int RefPositions {#2208@4462 #2211@4479} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 493: int RefPositions {#2210@4474 #2213@4479} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 494: byref RefPositions {#2216@4492 #2217@4493} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 495: int RefPositions {#2220@4504 #2222@4505} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 496: byref RefPositions {#2224@4510 #2227@4519} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 497: long RefPositions {#2226@4518 #2228@4519} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 498: byref RefPositions {#2229@4520 #2235@4537} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 499: int RefPositions {#2231@4528 #2232@4529} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 500: ushort RefPositions {#2234@4536 #2236@4537} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 501: int RefPositions {#2238@4546 #2240@4551} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 502: byref (specialPutArg) RefPositions {#2245@4560 #2257@4569} physReg:NA Preferences=[x0] RelatedInterval Interval 503: ref RefPositions {#2249@4564 #2259@4569} physReg:NA Preferences=[x1] Interval 504: long (constant) RefPositions {#2250@4566 #2252@4567} physReg:NA Preferences=[x11] Interval 505: long RefPositions {#2254@4568 #2261@4569} physReg:NA Preferences=[x11] Interval 506: int (INTERNAL) RefPositions {#2255@4569 #2262@4569} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 507: ushort RefPositions {#2288@4600 #2289@4601} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 508: int RefPositions {#2299@4636 #2300@4637} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 509: int RefPositions {#2305@4650 #2306@4651} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 510: int RefPositions {#2309@4662 #2311@4663} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 511: byref RefPositions {#2314@4676 #2315@4677} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 512: int RefPositions {#2318@4686 #2320@4687} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 513: byref RefPositions {#2322@4692 #2323@4705} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 514: int RefPositions {#2327@4714 #2329@4719} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 515: byref (specialPutArg) RefPositions {#2334@4728 #2346@4737} physReg:NA Preferences=[x0] RelatedInterval Interval 516: int RefPositions {#2338@4732 #2348@4737} physReg:NA Preferences=[x1] Interval 517: long (constant) RefPositions {#2339@4734 #2341@4735} physReg:NA Preferences=[x11] Interval 518: long RefPositions {#2343@4736 #2350@4737} physReg:NA Preferences=[x11] Interval 519: int (INTERNAL) RefPositions {#2344@4737 #2351@4737} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 520: ushort RefPositions {#2378@4768 #2379@4769} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 521: int RefPositions {#2384@4786 #2385@4787} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 522: long RefPositions {#2389@4794 #2392@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 523: long RefPositions {#2390@4796 #2393@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 524: int (INTERNAL) RefPositions {#2391@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 525: int RefPositions {#2397@4808 #2398@4811} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 526: int RefPositions {#2400@4812 #2401@4815} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 527: ubyte RefPositions {#2406@4842 #2409@4849} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 528: ref RefPositions {#2413@4862 #2414@4863} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 529: int RefPositions {#2419@4882 #2420@4883} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 530: int RefPositions {#2423@4892 #2426@4909} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 531: int RefPositions {#2425@4904 #2428@4909} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 532: byref RefPositions {#2431@4922 #2432@4923} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 533: int RefPositions {#2435@4934 #2437@4935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 534: byref RefPositions {#2439@4940 #2442@4949} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 535: long RefPositions {#2441@4948 #2443@4949} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 536: byref RefPositions {#2444@4950 #2450@4967} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 537: int RefPositions {#2446@4958 #2447@4959} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 538: ushort RefPositions {#2449@4966 #2451@4967} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 539: int RefPositions {#2453@4976 #2455@4981} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 540: byref (specialPutArg) RefPositions {#2460@4990 #2472@4999} physReg:NA Preferences=[x0] RelatedInterval Interval 541: ref RefPositions {#2464@4994 #2474@4999} physReg:NA Preferences=[x1] Interval 542: long (constant) RefPositions {#2465@4996 #2467@4997} physReg:NA Preferences=[x11] Interval 543: long RefPositions {#2469@4998 #2476@4999} physReg:NA Preferences=[x11] Interval 544: int (INTERNAL) RefPositions {#2470@4999 #2477@4999} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 545: int (constant) RefPositions {#2498@5006 #2499@5007} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 546: long (constant) RefPositions {#2523@5014 #2525@5015} physReg:NA Preferences=[x11] Interval 547: long RefPositions {#2527@5016 #2530@5017} physReg:NA Preferences=[x11] Interval 548: int (INTERNAL) RefPositions {#2528@5017 #2531@5017} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 549: long (constant) RefPositions {#2552@5022 #2553@5023} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 550: long RefPositions {#2554@5024 #2555@5025} physReg:NA Preferences=[x0-xip0 x19-x28] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> BB00 regmask=[x4] minReg=1 fixed regOptional wt=100.00> BB00 regmask=[x1] minReg=1 fixed regOptional wt=100.00> BB01 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 fixed wt=2150.00> BB01 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00> CNS_INT BB01 regmask=[x11] minReg=1 wt=400.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 last fixed wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x11] minReg=1 fixed wt=400.00> CALL BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 last fixed wt=100.00> CALL BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> BB01 regmask=[x0] minReg=1 last wt=100.00> BB01 regmask=[x1] minReg=1 last wt=100.00> BB01 regmask=[x2] minReg=1 last wt=100.00> BB01 regmask=[x3] minReg=1 last wt=100.00> BB01 regmask=[x4] minReg=1 last wt=100.00> BB01 regmask=[x5] minReg=1 last wt=100.00> BB01 regmask=[x6] minReg=1 last wt=100.00> BB01 regmask=[x7] minReg=1 last wt=100.00> BB01 regmask=[x8] minReg=1 last wt=100.00> BB01 regmask=[x9] minReg=1 last wt=100.00> BB01 regmask=[x10] minReg=1 last wt=100.00> BB01 regmask=[x11] minReg=1 last wt=100.00> BB01 regmask=[x12] minReg=1 last wt=100.00> BB01 regmask=[x13] minReg=1 last wt=100.00> BB01 regmask=[x14] minReg=1 last wt=100.00> BB01 regmask=[x15] minReg=1 last wt=100.00> BB01 regmask=[xip0] minReg=1 last wt=100.00> BB01 regmask=[xip1] minReg=1 last wt=100.00> BB01 regmask=[lr] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_FLD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_FLD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> CNS_INT BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> CNS_INT BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> BB06 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x0] minReg=1 last fixed wt=250.00> BB06 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x0] minReg=1 fixed wt=400.00> BB06 regmask=[x1] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x1] minReg=1 last fixed wt=250.00> BB06 regmask=[x1] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x1] minReg=1 fixed wt=400.00> BB06 regmask=[x2] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x2] minReg=1 last fixed wt=250.00> BB06 regmask=[x2] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x2] minReg=1 fixed wt=400.00> CNS_INT BB06 regmask=[x11] minReg=1 wt=400.00> BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 last fixed wt=100.00> BB06 regmask=[x11] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x11] minReg=1 fixed wt=400.00> CALL BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB06 regmask=[x0] minReg=1 wt=100.00> BB06 regmask=[x0] minReg=1 last fixed wt=100.00> BB06 regmask=[x1] minReg=1 wt=100.00> BB06 regmask=[x1] minReg=1 last fixed wt=100.00> BB06 regmask=[x2] minReg=1 wt=100.00> BB06 regmask=[x2] minReg=1 last fixed wt=100.00> BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 last fixed wt=100.00> CALL BB06 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> BB06 regmask=[x0] minReg=1 last wt=100.00> BB06 regmask=[x1] minReg=1 last wt=100.00> BB06 regmask=[x2] minReg=1 last wt=100.00> BB06 regmask=[x3] minReg=1 last wt=100.00> BB06 regmask=[x4] minReg=1 last wt=100.00> BB06 regmask=[x5] minReg=1 last wt=100.00> BB06 regmask=[x6] minReg=1 last wt=100.00> BB06 regmask=[x7] minReg=1 last wt=100.00> BB06 regmask=[x8] minReg=1 last wt=100.00> BB06 regmask=[x9] minReg=1 last wt=100.00> BB06 regmask=[x10] minReg=1 last wt=100.00> BB06 regmask=[x11] minReg=1 last wt=100.00> BB06 regmask=[x12] minReg=1 last wt=100.00> BB06 regmask=[x13] minReg=1 last wt=100.00> BB06 regmask=[x14] minReg=1 last wt=100.00> BB06 regmask=[x15] minReg=1 last wt=100.00> BB06 regmask=[xip0] minReg=1 last wt=100.00> BB06 regmask=[xip1] minReg=1 last wt=100.00> BB06 regmask=[lr] minReg=1 last wt=100.00> BB06 regmask=[x0] minReg=1 wt=100.00> CALL BB06 regmask=[x0] minReg=1 fixed wt=400.00> BB06 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> ADD BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> IND BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB49 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> ADD BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> ADD BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB13 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> CNS_INT BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ADD BB16 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> ADD BB36 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB40 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB41 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB42 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> IND BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> ADD BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> BB45 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> CNS_INT BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB50 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB52 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> CNS_INT BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> SUB BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> CNS_INT BB55 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB55 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB55 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB56 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> IND BB56 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB56 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> ADD BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ADD BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> ADD BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> SUB BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB60 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB60 regmask=[x1] minReg=1 last fixed wt=800.00> BB60 regmask=[x1] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x1] minReg=1 fixed wt=1600.00> BB60 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB60 regmask=[x0] minReg=1 fixed wt=2150.00> BB60 regmask=[x0] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x0] minReg=1 fixed wt=1600.00> CNS_INT BB60 regmask=[x11] minReg=1 wt=1600.00> BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 last fixed wt=400.00> BB60 regmask=[x11] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x11] minReg=1 fixed wt=1600.00> CNS_INT BB60 regmask=[x2] minReg=1 wt=1600.00> BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 last fixed wt=400.00> BB60 regmask=[x2] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x2] minReg=1 fixed wt=1600.00> CALL BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB60 regmask=[x1] minReg=1 wt=400.00> BB60 regmask=[x1] minReg=1 last fixed wt=400.00> BB60 regmask=[x0] minReg=1 wt=400.00> BB60 regmask=[x0] minReg=1 last fixed wt=400.00> BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 last fixed wt=400.00> BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 last fixed wt=400.00> CALL BB60 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> BB60 regmask=[x0] minReg=1 last wt=400.00> BB60 regmask=[x1] minReg=1 last wt=400.00> BB60 regmask=[x2] minReg=1 last wt=400.00> BB60 regmask=[x3] minReg=1 last wt=400.00> BB60 regmask=[x4] minReg=1 last wt=400.00> BB60 regmask=[x5] minReg=1 last wt=400.00> BB60 regmask=[x6] minReg=1 last wt=400.00> BB60 regmask=[x7] minReg=1 last wt=400.00> BB60 regmask=[x8] minReg=1 last wt=400.00> BB60 regmask=[x9] minReg=1 last wt=400.00> BB60 regmask=[x10] minReg=1 last wt=400.00> BB60 regmask=[x11] minReg=1 last wt=400.00> BB60 regmask=[x12] minReg=1 last wt=400.00> BB60 regmask=[x13] minReg=1 last wt=400.00> BB60 regmask=[x14] minReg=1 last wt=400.00> BB60 regmask=[x15] minReg=1 last wt=400.00> BB60 regmask=[xip0] minReg=1 last wt=400.00> BB60 regmask=[xip1] minReg=1 last wt=400.00> BB60 regmask=[lr] minReg=1 last wt=400.00> LCL_VAR BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> IND BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB60 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> BB61 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB61 regmask=[x0] minReg=1 fixed wt=1500.00> BB61 regmask=[x0] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x0] minReg=1 fixed wt=1600.00> LCL_FLD BB61 regmask=[x1] minReg=1 wt=1600.00> BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 last fixed wt=400.00> BB61 regmask=[x1] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x1] minReg=1 fixed wt=1600.00> CNS_INT BB61 regmask=[x11] minReg=1 wt=1600.00> BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 last fixed wt=400.00> BB61 regmask=[x11] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x11] minReg=1 fixed wt=1600.00> CNS_INT BB61 regmask=[x2] minReg=1 wt=1600.00> BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 last fixed wt=400.00> BB61 regmask=[x2] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x2] minReg=1 fixed wt=1600.00> CALL BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB61 regmask=[x0] minReg=1 wt=400.00> BB61 regmask=[x0] minReg=1 last fixed wt=400.00> BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 last fixed wt=400.00> BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 last fixed wt=400.00> BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 last fixed wt=400.00> CALL BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> BB61 regmask=[x0] minReg=1 last wt=400.00> BB61 regmask=[x1] minReg=1 last wt=400.00> BB61 regmask=[x2] minReg=1 last wt=400.00> BB61 regmask=[x3] minReg=1 last wt=400.00> BB61 regmask=[x4] minReg=1 last wt=400.00> BB61 regmask=[x5] minReg=1 last wt=400.00> BB61 regmask=[x6] minReg=1 last wt=400.00> BB61 regmask=[x7] minReg=1 last wt=400.00> BB61 regmask=[x8] minReg=1 last wt=400.00> BB61 regmask=[x9] minReg=1 last wt=400.00> BB61 regmask=[x10] minReg=1 last wt=400.00> BB61 regmask=[x11] minReg=1 last wt=400.00> BB61 regmask=[x12] minReg=1 last wt=400.00> BB61 regmask=[x13] minReg=1 last wt=400.00> BB61 regmask=[x14] minReg=1 last wt=400.00> BB61 regmask=[x15] minReg=1 last wt=400.00> BB61 regmask=[xip0] minReg=1 last wt=400.00> BB61 regmask=[xip1] minReg=1 last wt=400.00> BB61 regmask=[lr] minReg=1 last wt=400.00> BB61 regmask=[x0] minReg=1 wt=400.00> CALL BB61 regmask=[x0] minReg=1 fixed wt=1600.00> BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> BB62 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB63 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB63 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB63 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB64 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB65 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> SUB BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> SELECT BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> SUB BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> SELECT BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> SELECT BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> SUB BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR_ADDR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> CNS_INT BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> CNS_INT BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> IND BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> IND BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> IND BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB81 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ADD BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> SELECT BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB89 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> ADD BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LSH BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=200.00> CAST BB91 regmask=[x0] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x0] minReg=1 last fixed wt=200.00> BB91 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB91 regmask=[x0] minReg=1 fixed wt=800.00> CNS_INT BB91 regmask=[x11] minReg=1 wt=800.00> BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 last fixed wt=200.00> BB91 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB91 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x0] minReg=1 last fixed wt=200.00> BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB91 regmask=[x0] minReg=1 last wt=200.00> BB91 regmask=[x1] minReg=1 last wt=200.00> BB91 regmask=[x2] minReg=1 last wt=200.00> BB91 regmask=[x3] minReg=1 last wt=200.00> BB91 regmask=[x4] minReg=1 last wt=200.00> BB91 regmask=[x5] minReg=1 last wt=200.00> BB91 regmask=[x6] minReg=1 last wt=200.00> BB91 regmask=[x7] minReg=1 last wt=200.00> BB91 regmask=[x8] minReg=1 last wt=200.00> BB91 regmask=[x9] minReg=1 last wt=200.00> BB91 regmask=[x10] minReg=1 last wt=200.00> BB91 regmask=[x11] minReg=1 last wt=200.00> BB91 regmask=[x12] minReg=1 last wt=200.00> BB91 regmask=[x13] minReg=1 last wt=200.00> BB91 regmask=[x14] minReg=1 last wt=200.00> BB91 regmask=[x15] minReg=1 last wt=200.00> BB91 regmask=[xip0] minReg=1 last wt=200.00> BB91 regmask=[xip1] minReg=1 last wt=200.00> BB91 regmask=[lr] minReg=1 last wt=200.00> BB91 regmask=[x0] minReg=1 wt=200.00> CALL BB91 regmask=[x0] minReg=1 fixed wt=800.00> BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> ADD BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> IND BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=2700.00> CAST BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LSH BB95 regmask=[x2] minReg=1 wt=800.00> BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 last fixed wt=200.00> BB95 regmask=[x2] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x2] minReg=1 fixed wt=800.00> BB95 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB95 regmask=[x0] minReg=1 last fixed wt=400.00> BB95 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x0] minReg=1 fixed wt=800.00> BB95 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB95 regmask=[x1] minReg=1 last fixed wt=1900.00> BB95 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB95 regmask=[x11] minReg=1 wt=800.00> BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 last fixed wt=200.00> BB95 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 last fixed wt=200.00> BB95 regmask=[x0] minReg=1 wt=200.00> BB95 regmask=[x0] minReg=1 last fixed wt=200.00> BB95 regmask=[x1] minReg=1 wt=200.00> BB95 regmask=[x1] minReg=1 last fixed wt=200.00> BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB95 regmask=[x0] minReg=1 last wt=200.00> BB95 regmask=[x1] minReg=1 last wt=200.00> BB95 regmask=[x2] minReg=1 last wt=200.00> BB95 regmask=[x3] minReg=1 last wt=200.00> BB95 regmask=[x4] minReg=1 last wt=200.00> BB95 regmask=[x5] minReg=1 last wt=200.00> BB95 regmask=[x6] minReg=1 last wt=200.00> BB95 regmask=[x7] minReg=1 last wt=200.00> BB95 regmask=[x8] minReg=1 last wt=200.00> BB95 regmask=[x9] minReg=1 last wt=200.00> BB95 regmask=[x10] minReg=1 last wt=200.00> BB95 regmask=[x11] minReg=1 last wt=200.00> BB95 regmask=[x12] minReg=1 last wt=200.00> BB95 regmask=[x13] minReg=1 last wt=200.00> BB95 regmask=[x14] minReg=1 last wt=200.00> BB95 regmask=[x15] minReg=1 last wt=200.00> BB95 regmask=[xip0] minReg=1 last wt=200.00> BB95 regmask=[xip1] minReg=1 last wt=200.00> BB95 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> ADD BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> IND BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> ADD BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> ADD BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> IND BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> ADD BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> IND BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> ADD BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB103 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB104 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB104 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB104 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB106 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> BFIZ BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB111 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB111 regmask=[x0] minReg=1 fixed wt=26550.00> BB111 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x0] minReg=1 fixed wt=200.00> BB111 regmask=[x1] minReg=1 wt=50.00> LCL_VAR BB111 regmask=[x1] minReg=1 last fixed wt=500.00> BB111 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x1] minReg=1 fixed wt=200.00> CNS_INT BB111 regmask=[x11] minReg=1 wt=200.00> BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 last fixed wt=50.00> BB111 regmask=[x11] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x11] minReg=1 fixed wt=200.00> CALL BB111 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB111 regmask=[x0] minReg=1 wt=50.00> BB111 regmask=[x0] minReg=1 last fixed wt=50.00> BB111 regmask=[x1] minReg=1 wt=50.00> BB111 regmask=[x1] minReg=1 last fixed wt=50.00> BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 last fixed wt=50.00> CALL BB111 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB111 regmask=[x0] minReg=1 last wt=50.00> BB111 regmask=[x1] minReg=1 last wt=50.00> BB111 regmask=[x2] minReg=1 last wt=50.00> BB111 regmask=[x3] minReg=1 last wt=50.00> BB111 regmask=[x4] minReg=1 last wt=50.00> BB111 regmask=[x5] minReg=1 last wt=50.00> BB111 regmask=[x6] minReg=1 last wt=50.00> BB111 regmask=[x7] minReg=1 last wt=50.00> BB111 regmask=[x8] minReg=1 last wt=50.00> BB111 regmask=[x9] minReg=1 last wt=50.00> BB111 regmask=[x10] minReg=1 last wt=50.00> BB111 regmask=[x11] minReg=1 last wt=50.00> BB111 regmask=[x12] minReg=1 last wt=50.00> BB111 regmask=[x13] minReg=1 last wt=50.00> BB111 regmask=[x14] minReg=1 last wt=50.00> BB111 regmask=[x15] minReg=1 last wt=50.00> BB111 regmask=[xip0] minReg=1 last wt=50.00> BB111 regmask=[xip1] minReg=1 last wt=50.00> BB111 regmask=[lr] minReg=1 last wt=50.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1500.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> ADD BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB247 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB113 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> CNS_INT BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB114 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB115 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB135 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> IND BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB118 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> CNS_INT BB119 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB119 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB119 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ADD BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=2400.00> CAST BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> IND BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> IND BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ADD BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB123 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB123 regmask=[x0] minReg=1 fixed wt=26550.00> BB123 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x0] minReg=1 fixed wt=3200.00> BB123 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB123 regmask=[x1] minReg=1 last fixed wt=4800.00> BB123 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB123 regmask=[x11] minReg=1 wt=3200.00> BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 last fixed wt=800.00> BB123 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB123 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB123 regmask=[x0] minReg=1 wt=800.00> BB123 regmask=[x0] minReg=1 last fixed wt=800.00> BB123 regmask=[x1] minReg=1 wt=800.00> BB123 regmask=[x1] minReg=1 last fixed wt=800.00> BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB123 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB123 regmask=[x0] minReg=1 last wt=800.00> BB123 regmask=[x1] minReg=1 last wt=800.00> BB123 regmask=[x2] minReg=1 last wt=800.00> BB123 regmask=[x3] minReg=1 last wt=800.00> BB123 regmask=[x4] minReg=1 last wt=800.00> BB123 regmask=[x5] minReg=1 last wt=800.00> BB123 regmask=[x6] minReg=1 last wt=800.00> BB123 regmask=[x7] minReg=1 last wt=800.00> BB123 regmask=[x8] minReg=1 last wt=800.00> BB123 regmask=[x9] minReg=1 last wt=800.00> BB123 regmask=[x10] minReg=1 last wt=800.00> BB123 regmask=[x11] minReg=1 last wt=800.00> BB123 regmask=[x12] minReg=1 last wt=800.00> BB123 regmask=[x13] minReg=1 last wt=800.00> BB123 regmask=[x14] minReg=1 last wt=800.00> BB123 regmask=[x15] minReg=1 last wt=800.00> BB123 regmask=[xip0] minReg=1 last wt=800.00> BB123 regmask=[xip1] minReg=1 last wt=800.00> BB123 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> IND BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ADD BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB127 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BFIZ BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=8000.00> IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB132 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB132 regmask=[x0] minReg=1 fixed wt=26550.00> BB132 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x0] minReg=1 fixed wt=3200.00> BB132 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB132 regmask=[x1] minReg=1 last fixed wt=8000.00> BB132 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB132 regmask=[x11] minReg=1 wt=3200.00> BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 last fixed wt=800.00> BB132 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB132 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB132 regmask=[x0] minReg=1 wt=800.00> BB132 regmask=[x0] minReg=1 last fixed wt=800.00> BB132 regmask=[x1] minReg=1 wt=800.00> BB132 regmask=[x1] minReg=1 last fixed wt=800.00> BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB132 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB132 regmask=[x0] minReg=1 last wt=800.00> BB132 regmask=[x1] minReg=1 last wt=800.00> BB132 regmask=[x2] minReg=1 last wt=800.00> BB132 regmask=[x3] minReg=1 last wt=800.00> BB132 regmask=[x4] minReg=1 last wt=800.00> BB132 regmask=[x5] minReg=1 last wt=800.00> BB132 regmask=[x6] minReg=1 last wt=800.00> BB132 regmask=[x7] minReg=1 last wt=800.00> BB132 regmask=[x8] minReg=1 last wt=800.00> BB132 regmask=[x9] minReg=1 last wt=800.00> BB132 regmask=[x10] minReg=1 last wt=800.00> BB132 regmask=[x11] minReg=1 last wt=800.00> BB132 regmask=[x12] minReg=1 last wt=800.00> BB132 regmask=[x13] minReg=1 last wt=800.00> BB132 regmask=[x14] minReg=1 last wt=800.00> BB132 regmask=[x15] minReg=1 last wt=800.00> BB132 regmask=[xip0] minReg=1 last wt=800.00> BB132 regmask=[xip1] minReg=1 last wt=800.00> BB132 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> ADD BB133 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> ADD BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> ADD BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB136 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> ADD BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB137 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> ADD BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB138 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB139 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB141 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB142 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> CNS_INT BB143 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB143 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB143 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB144 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB181 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BFIZ BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB185 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB185 regmask=[x0] minReg=1 fixed wt=26550.00> BB185 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x0] minReg=1 fixed wt=800.00> BB185 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB185 regmask=[x1] minReg=1 last fixed wt=2400.00> BB185 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB185 regmask=[x11] minReg=1 wt=800.00> BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 last fixed wt=200.00> BB185 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB185 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB185 regmask=[x0] minReg=1 wt=200.00> BB185 regmask=[x0] minReg=1 last fixed wt=200.00> BB185 regmask=[x1] minReg=1 wt=200.00> BB185 regmask=[x1] minReg=1 last fixed wt=200.00> BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB185 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB185 regmask=[x0] minReg=1 last wt=200.00> BB185 regmask=[x1] minReg=1 last wt=200.00> BB185 regmask=[x2] minReg=1 last wt=200.00> BB185 regmask=[x3] minReg=1 last wt=200.00> BB185 regmask=[x4] minReg=1 last wt=200.00> BB185 regmask=[x5] minReg=1 last wt=200.00> BB185 regmask=[x6] minReg=1 last wt=200.00> BB185 regmask=[x7] minReg=1 last wt=200.00> BB185 regmask=[x8] minReg=1 last wt=200.00> BB185 regmask=[x9] minReg=1 last wt=200.00> BB185 regmask=[x10] minReg=1 last wt=200.00> BB185 regmask=[x11] minReg=1 last wt=200.00> BB185 regmask=[x12] minReg=1 last wt=200.00> BB185 regmask=[x13] minReg=1 last wt=200.00> BB185 regmask=[x14] minReg=1 last wt=200.00> BB185 regmask=[x15] minReg=1 last wt=200.00> BB185 regmask=[xip0] minReg=1 last wt=200.00> BB185 regmask=[xip1] minReg=1 last wt=200.00> BB185 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ADD BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB204 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB204 regmask=[x0] minReg=1 fixed wt=26550.00> BB204 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x0] minReg=1 fixed wt=800.00> BB204 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB204 regmask=[x1] minReg=1 last fixed wt=1200.00> BB204 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB204 regmask=[x11] minReg=1 wt=800.00> BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 last fixed wt=200.00> BB204 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB204 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB204 regmask=[x0] minReg=1 wt=200.00> BB204 regmask=[x0] minReg=1 last fixed wt=200.00> BB204 regmask=[x1] minReg=1 wt=200.00> BB204 regmask=[x1] minReg=1 last fixed wt=200.00> BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB204 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB204 regmask=[x0] minReg=1 last wt=200.00> BB204 regmask=[x1] minReg=1 last wt=200.00> BB204 regmask=[x2] minReg=1 last wt=200.00> BB204 regmask=[x3] minReg=1 last wt=200.00> BB204 regmask=[x4] minReg=1 last wt=200.00> BB204 regmask=[x5] minReg=1 last wt=200.00> BB204 regmask=[x6] minReg=1 last wt=200.00> BB204 regmask=[x7] minReg=1 last wt=200.00> BB204 regmask=[x8] minReg=1 last wt=200.00> BB204 regmask=[x9] minReg=1 last wt=200.00> BB204 regmask=[x10] minReg=1 last wt=200.00> BB204 regmask=[x11] minReg=1 last wt=200.00> BB204 regmask=[x12] minReg=1 last wt=200.00> BB204 regmask=[x13] minReg=1 last wt=200.00> BB204 regmask=[x14] minReg=1 last wt=200.00> BB204 regmask=[x15] minReg=1 last wt=200.00> BB204 regmask=[xip0] minReg=1 last wt=200.00> BB204 regmask=[xip1] minReg=1 last wt=200.00> BB204 regmask=[lr] minReg=1 last wt=200.00> STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB208 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> NE BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> IND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> NE BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> AND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CNS_INT BB210 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB210 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB210 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB213 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> BB214 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> IND BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB214 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> ADD BB218 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> ADD BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB220 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> LCL_VAR BB221 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> CNS_INT BB222 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB222 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB222 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB223 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> IND BB223 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB223 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> SUB BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB225 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> BB226 regmask=[x5] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x5] minReg=1 last fixed wt=600.00> BB226 regmask=[x5] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x5] minReg=1 fixed wt=800.00> BB226 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x0] minReg=1 fixed wt=26550.00> BB226 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x0] minReg=1 fixed wt=800.00> BB226 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x1] minReg=1 fixed wt=2250.00> BB226 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x1] minReg=1 fixed wt=800.00> BB226 regmask=[x2] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x2] minReg=1 last fixed wt=600.00> BB226 regmask=[x2] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x2] minReg=1 fixed wt=800.00> BB226 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x3] minReg=1 last fixed wt=23800.00> BB226 regmask=[x3] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x3] minReg=1 fixed wt=800.00> BB226 regmask=[x4] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x4] minReg=1 last fixed wt=2400.00> BB226 regmask=[x4] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x4] minReg=1 fixed wt=800.00> CNS_INT BB226 regmask=[x11] minReg=1 wt=800.00> BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 last fixed wt=200.00> BB226 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB226 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB226 regmask=[x5] minReg=1 wt=200.00> BB226 regmask=[x5] minReg=1 last fixed wt=200.00> BB226 regmask=[x0] minReg=1 wt=200.00> BB226 regmask=[x0] minReg=1 last fixed wt=200.00> BB226 regmask=[x1] minReg=1 wt=200.00> BB226 regmask=[x1] minReg=1 last fixed wt=200.00> BB226 regmask=[x2] minReg=1 wt=200.00> BB226 regmask=[x2] minReg=1 last fixed wt=200.00> BB226 regmask=[x3] minReg=1 wt=200.00> BB226 regmask=[x3] minReg=1 last fixed wt=200.00> BB226 regmask=[x4] minReg=1 wt=200.00> BB226 regmask=[x4] minReg=1 last fixed wt=200.00> BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB226 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB226 regmask=[x0] minReg=1 last wt=200.00> BB226 regmask=[x1] minReg=1 last wt=200.00> BB226 regmask=[x2] minReg=1 last wt=200.00> BB226 regmask=[x3] minReg=1 last wt=200.00> BB226 regmask=[x4] minReg=1 last wt=200.00> BB226 regmask=[x5] minReg=1 last wt=200.00> BB226 regmask=[x6] minReg=1 last wt=200.00> BB226 regmask=[x7] minReg=1 last wt=200.00> BB226 regmask=[x8] minReg=1 last wt=200.00> BB226 regmask=[x9] minReg=1 last wt=200.00> BB226 regmask=[x10] minReg=1 last wt=200.00> BB226 regmask=[x11] minReg=1 last wt=200.00> BB226 regmask=[x12] minReg=1 last wt=200.00> BB226 regmask=[x13] minReg=1 last wt=200.00> BB226 regmask=[x14] minReg=1 last wt=200.00> BB226 regmask=[x15] minReg=1 last wt=200.00> BB226 regmask=[xip0] minReg=1 last wt=200.00> BB226 regmask=[xip1] minReg=1 last wt=200.00> BB226 regmask=[lr] minReg=1 last wt=200.00> STORE_LCL_VAR BB226 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB229 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB229 regmask=[x0] minReg=1 fixed wt=26550.00> BB229 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x0] minReg=1 fixed wt=800.00> BB229 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB229 regmask=[x1] minReg=1 last fixed wt=23800.00> BB229 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB229 regmask=[x11] minReg=1 wt=800.00> BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 last fixed wt=200.00> BB229 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB229 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB229 regmask=[x0] minReg=1 wt=200.00> BB229 regmask=[x0] minReg=1 last fixed wt=200.00> BB229 regmask=[x1] minReg=1 wt=200.00> BB229 regmask=[x1] minReg=1 last fixed wt=200.00> BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB229 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB229 regmask=[x0] minReg=1 last wt=200.00> BB229 regmask=[x1] minReg=1 last wt=200.00> BB229 regmask=[x2] minReg=1 last wt=200.00> BB229 regmask=[x3] minReg=1 last wt=200.00> BB229 regmask=[x4] minReg=1 last wt=200.00> BB229 regmask=[x5] minReg=1 last wt=200.00> BB229 regmask=[x6] minReg=1 last wt=200.00> BB229 regmask=[x7] minReg=1 last wt=200.00> BB229 regmask=[x8] minReg=1 last wt=200.00> BB229 regmask=[x9] minReg=1 last wt=200.00> BB229 regmask=[x10] minReg=1 last wt=200.00> BB229 regmask=[x11] minReg=1 last wt=200.00> BB229 regmask=[x12] minReg=1 last wt=200.00> BB229 regmask=[x13] minReg=1 last wt=200.00> BB229 regmask=[x14] minReg=1 last wt=200.00> BB229 regmask=[x15] minReg=1 last wt=200.00> BB229 regmask=[xip0] minReg=1 last wt=200.00> BB229 regmask=[xip1] minReg=1 last wt=200.00> BB229 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB231 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB232 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ADD BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB235 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB235 regmask=[x0] minReg=1 fixed wt=26550.00> BB235 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x0] minReg=1 fixed wt=800.00> BB235 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB235 regmask=[x1] minReg=1 last fixed wt=1200.00> BB235 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB235 regmask=[x11] minReg=1 wt=800.00> BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 last fixed wt=200.00> BB235 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB235 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB235 regmask=[x0] minReg=1 wt=200.00> BB235 regmask=[x0] minReg=1 last fixed wt=200.00> BB235 regmask=[x1] minReg=1 wt=200.00> BB235 regmask=[x1] minReg=1 last fixed wt=200.00> BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB235 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB235 regmask=[x0] minReg=1 last wt=200.00> BB235 regmask=[x1] minReg=1 last wt=200.00> BB235 regmask=[x2] minReg=1 last wt=200.00> BB235 regmask=[x3] minReg=1 last wt=200.00> BB235 regmask=[x4] minReg=1 last wt=200.00> BB235 regmask=[x5] minReg=1 last wt=200.00> BB235 regmask=[x6] minReg=1 last wt=200.00> BB235 regmask=[x7] minReg=1 last wt=200.00> BB235 regmask=[x8] minReg=1 last wt=200.00> BB235 regmask=[x9] minReg=1 last wt=200.00> BB235 regmask=[x10] minReg=1 last wt=200.00> BB235 regmask=[x11] minReg=1 last wt=200.00> BB235 regmask=[x12] minReg=1 last wt=200.00> BB235 regmask=[x13] minReg=1 last wt=200.00> BB235 regmask=[x14] minReg=1 last wt=200.00> BB235 regmask=[x15] minReg=1 last wt=200.00> BB235 regmask=[xip0] minReg=1 last wt=200.00> BB235 regmask=[xip1] minReg=1 last wt=200.00> BB235 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB240 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ADD BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> IND BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> IND BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ADD BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB238 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB238 regmask=[x0] minReg=1 fixed wt=26550.00> BB238 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x0] minReg=1 fixed wt=3200.00> BB238 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB238 regmask=[x1] minReg=1 last fixed wt=4800.00> BB238 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB238 regmask=[x11] minReg=1 wt=3200.00> BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 last fixed wt=800.00> BB238 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB238 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB238 regmask=[x0] minReg=1 wt=800.00> BB238 regmask=[x0] minReg=1 last fixed wt=800.00> BB238 regmask=[x1] minReg=1 wt=800.00> BB238 regmask=[x1] minReg=1 last fixed wt=800.00> BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB238 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB238 regmask=[x0] minReg=1 last wt=800.00> BB238 regmask=[x1] minReg=1 last wt=800.00> BB238 regmask=[x2] minReg=1 last wt=800.00> BB238 regmask=[x3] minReg=1 last wt=800.00> BB238 regmask=[x4] minReg=1 last wt=800.00> BB238 regmask=[x5] minReg=1 last wt=800.00> BB238 regmask=[x6] minReg=1 last wt=800.00> BB238 regmask=[x7] minReg=1 last wt=800.00> BB238 regmask=[x8] minReg=1 last wt=800.00> BB238 regmask=[x9] minReg=1 last wt=800.00> BB238 regmask=[x10] minReg=1 last wt=800.00> BB238 regmask=[x11] minReg=1 last wt=800.00> BB238 regmask=[x12] minReg=1 last wt=800.00> BB238 regmask=[x13] minReg=1 last wt=800.00> BB238 regmask=[x14] minReg=1 last wt=800.00> BB238 regmask=[x15] minReg=1 last wt=800.00> BB238 regmask=[xip0] minReg=1 last wt=800.00> BB238 regmask=[xip1] minReg=1 last wt=800.00> BB238 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB244 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB244 regmask=[x0] minReg=1 fixed wt=26550.00> BB244 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x0] minReg=1 fixed wt=800.00> BB244 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB244 regmask=[x1] minReg=1 last fixed wt=23800.00> BB244 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB244 regmask=[x11] minReg=1 wt=800.00> BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 last fixed wt=200.00> BB244 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB244 regmask=[x0] minReg=1 wt=200.00> BB244 regmask=[x0] minReg=1 last fixed wt=200.00> BB244 regmask=[x1] minReg=1 wt=200.00> BB244 regmask=[x1] minReg=1 last fixed wt=200.00> BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB244 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB244 regmask=[x0] minReg=1 last wt=200.00> BB244 regmask=[x1] minReg=1 last wt=200.00> BB244 regmask=[x2] minReg=1 last wt=200.00> BB244 regmask=[x3] minReg=1 last wt=200.00> BB244 regmask=[x4] minReg=1 last wt=200.00> BB244 regmask=[x5] minReg=1 last wt=200.00> BB244 regmask=[x6] minReg=1 last wt=200.00> BB244 regmask=[x7] minReg=1 last wt=200.00> BB244 regmask=[x8] minReg=1 last wt=200.00> BB244 regmask=[x9] minReg=1 last wt=200.00> BB244 regmask=[x10] minReg=1 last wt=200.00> BB244 regmask=[x11] minReg=1 last wt=200.00> BB244 regmask=[x12] minReg=1 last wt=200.00> BB244 regmask=[x13] minReg=1 last wt=200.00> BB244 regmask=[x14] minReg=1 last wt=200.00> BB244 regmask=[x15] minReg=1 last wt=200.00> BB244 regmask=[xip0] minReg=1 last wt=200.00> BB244 regmask=[xip1] minReg=1 last wt=200.00> BB244 regmask=[lr] minReg=1 last wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB248 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> IND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> NE BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LE BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> AND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB251 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> IND BB251 regmask=[x2] minReg=1 wt=200.00> BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 last fixed wt=50.00> BB251 regmask=[x2] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x2] minReg=1 fixed wt=200.00> BB251 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB251 regmask=[x0] minReg=1 last fixed wt=26550.00> BB251 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x0] minReg=1 fixed wt=200.00> CNS_INT BB251 regmask=[x11] minReg=1 wt=200.00> BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 last fixed wt=50.00> BB251 regmask=[x11] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x11] minReg=1 fixed wt=200.00> CNS_INT BB251 regmask=[x1] minReg=1 wt=200.00> BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 last fixed wt=50.00> BB251 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x1] minReg=1 fixed wt=200.00> CALL BB251 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 last fixed wt=50.00> BB251 regmask=[x0] minReg=1 wt=50.00> BB251 regmask=[x0] minReg=1 last fixed wt=50.00> BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 last fixed wt=50.00> BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 last fixed wt=50.00> CALL BB251 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB251 regmask=[x0] minReg=1 last wt=50.00> BB251 regmask=[x1] minReg=1 last wt=50.00> BB251 regmask=[x2] minReg=1 last wt=50.00> BB251 regmask=[x3] minReg=1 last wt=50.00> BB251 regmask=[x4] minReg=1 last wt=50.00> BB251 regmask=[x5] minReg=1 last wt=50.00> BB251 regmask=[x6] minReg=1 last wt=50.00> BB251 regmask=[x7] minReg=1 last wt=50.00> BB251 regmask=[x8] minReg=1 last wt=50.00> BB251 regmask=[x9] minReg=1 last wt=50.00> BB251 regmask=[x10] minReg=1 last wt=50.00> BB251 regmask=[x11] minReg=1 last wt=50.00> BB251 regmask=[x12] minReg=1 last wt=50.00> BB251 regmask=[x13] minReg=1 last wt=50.00> BB251 regmask=[x14] minReg=1 last wt=50.00> BB251 regmask=[x15] minReg=1 last wt=50.00> BB251 regmask=[xip0] minReg=1 last wt=50.00> BB251 regmask=[xip1] minReg=1 last wt=50.00> BB251 regmask=[lr] minReg=1 last wt=50.00> LCL_VAR BB255 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=4800.00> CAST BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> JMPTABLE BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> SWITCH_TABLE BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB255 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB255 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> ADD BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ADD BB30 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=19200.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=19200.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> ADD BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=19200.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB256 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=4800.00> CAST BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> JMPTABLE BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> SWITCH_TABLE BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB256 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB256 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CNS_INT BB18 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB18 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> BB18 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB21 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB21 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB24 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> ADD BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> CNS_INT BB28 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB28 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB28 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> CNS_INT BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB257 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=1200.00> CAST BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> JMPTABLE BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> SWITCH_TABLE BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB257 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB257 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB145 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> ADD BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> STORE_LCL_VAR BB147 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> CNS_INT BB148 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB148 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB148 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=600.00> CAST BB149 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB149 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB150 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> IND BB150 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB150 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> STORE_LCL_VAR BB152 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CNS_INT BB153 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB153 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB153 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> ADD BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=800.00> CAST BB155 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB155 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB156 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB159 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB159 regmask=[x0] minReg=1 fixed wt=26550.00> BB159 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x0] minReg=1 fixed wt=800.00> BB159 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB159 regmask=[x1] minReg=1 last fixed wt=23800.00> BB159 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB159 regmask=[x11] minReg=1 wt=800.00> BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 last fixed wt=200.00> BB159 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB159 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB159 regmask=[x0] minReg=1 wt=200.00> BB159 regmask=[x0] minReg=1 last fixed wt=200.00> BB159 regmask=[x1] minReg=1 wt=200.00> BB159 regmask=[x1] minReg=1 last fixed wt=200.00> BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB159 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB159 regmask=[x0] minReg=1 last wt=200.00> BB159 regmask=[x1] minReg=1 last wt=200.00> BB159 regmask=[x2] minReg=1 last wt=200.00> BB159 regmask=[x3] minReg=1 last wt=200.00> BB159 regmask=[x4] minReg=1 last wt=200.00> BB159 regmask=[x5] minReg=1 last wt=200.00> BB159 regmask=[x6] minReg=1 last wt=200.00> BB159 regmask=[x7] minReg=1 last wt=200.00> BB159 regmask=[x8] minReg=1 last wt=200.00> BB159 regmask=[x9] minReg=1 last wt=200.00> BB159 regmask=[x10] minReg=1 last wt=200.00> BB159 regmask=[x11] minReg=1 last wt=200.00> BB159 regmask=[x12] minReg=1 last wt=200.00> BB159 regmask=[x13] minReg=1 last wt=200.00> BB159 regmask=[x14] minReg=1 last wt=200.00> BB159 regmask=[x15] minReg=1 last wt=200.00> BB159 regmask=[xip0] minReg=1 last wt=200.00> BB159 regmask=[xip1] minReg=1 last wt=200.00> BB159 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> IND BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB163 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BFIZ BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB168 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB168 regmask=[x0] minReg=1 fixed wt=26550.00> BB168 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x0] minReg=1 fixed wt=800.00> BB168 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB168 regmask=[x1] minReg=1 last fixed wt=2400.00> BB168 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB168 regmask=[x11] minReg=1 wt=800.00> BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 last fixed wt=200.00> BB168 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB168 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB168 regmask=[x0] minReg=1 wt=200.00> BB168 regmask=[x0] minReg=1 last fixed wt=200.00> BB168 regmask=[x1] minReg=1 wt=200.00> BB168 regmask=[x1] minReg=1 last fixed wt=200.00> BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB168 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB168 regmask=[x0] minReg=1 last wt=200.00> BB168 regmask=[x1] minReg=1 last wt=200.00> BB168 regmask=[x2] minReg=1 last wt=200.00> BB168 regmask=[x3] minReg=1 last wt=200.00> BB168 regmask=[x4] minReg=1 last wt=200.00> BB168 regmask=[x5] minReg=1 last wt=200.00> BB168 regmask=[x6] minReg=1 last wt=200.00> BB168 regmask=[x7] minReg=1 last wt=200.00> BB168 regmask=[x8] minReg=1 last wt=200.00> BB168 regmask=[x9] minReg=1 last wt=200.00> BB168 regmask=[x10] minReg=1 last wt=200.00> BB168 regmask=[x11] minReg=1 last wt=200.00> BB168 regmask=[x12] minReg=1 last wt=200.00> BB168 regmask=[x13] minReg=1 last wt=200.00> BB168 regmask=[x14] minReg=1 last wt=200.00> BB168 regmask=[x15] minReg=1 last wt=200.00> BB168 regmask=[xip0] minReg=1 last wt=200.00> BB168 regmask=[xip1] minReg=1 last wt=200.00> BB168 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> ADD BB169 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> ADD BB170 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB186 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BFIZ BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB190 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB190 regmask=[x0] minReg=1 fixed wt=26550.00> BB190 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x0] minReg=1 fixed wt=800.00> BB190 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB190 regmask=[x1] minReg=1 last fixed wt=2400.00> BB190 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB190 regmask=[x11] minReg=1 wt=800.00> BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 last fixed wt=200.00> BB190 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB190 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB190 regmask=[x0] minReg=1 wt=200.00> BB190 regmask=[x0] minReg=1 last fixed wt=200.00> BB190 regmask=[x1] minReg=1 wt=200.00> BB190 regmask=[x1] minReg=1 last fixed wt=200.00> BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB190 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB190 regmask=[x0] minReg=1 last wt=200.00> BB190 regmask=[x1] minReg=1 last wt=200.00> BB190 regmask=[x2] minReg=1 last wt=200.00> BB190 regmask=[x3] minReg=1 last wt=200.00> BB190 regmask=[x4] minReg=1 last wt=200.00> BB190 regmask=[x5] minReg=1 last wt=200.00> BB190 regmask=[x6] minReg=1 last wt=200.00> BB190 regmask=[x7] minReg=1 last wt=200.00> BB190 regmask=[x8] minReg=1 last wt=200.00> BB190 regmask=[x9] minReg=1 last wt=200.00> BB190 regmask=[x10] minReg=1 last wt=200.00> BB190 regmask=[x11] minReg=1 last wt=200.00> BB190 regmask=[x12] minReg=1 last wt=200.00> BB190 regmask=[x13] minReg=1 last wt=200.00> BB190 regmask=[x14] minReg=1 last wt=200.00> BB190 regmask=[x15] minReg=1 last wt=200.00> BB190 regmask=[xip0] minReg=1 last wt=200.00> BB190 regmask=[xip1] minReg=1 last wt=200.00> BB190 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB195 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ADD BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> IND BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> IND BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ADD BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB193 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB193 regmask=[x0] minReg=1 fixed wt=26550.00> BB193 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x0] minReg=1 fixed wt=3200.00> BB193 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB193 regmask=[x1] minReg=1 last fixed wt=4800.00> BB193 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB193 regmask=[x11] minReg=1 wt=3200.00> BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 last fixed wt=800.00> BB193 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB193 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB193 regmask=[x0] minReg=1 wt=800.00> BB193 regmask=[x0] minReg=1 last fixed wt=800.00> BB193 regmask=[x1] minReg=1 wt=800.00> BB193 regmask=[x1] minReg=1 last fixed wt=800.00> BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB193 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB193 regmask=[x0] minReg=1 last wt=800.00> BB193 regmask=[x1] minReg=1 last wt=800.00> BB193 regmask=[x2] minReg=1 last wt=800.00> BB193 regmask=[x3] minReg=1 last wt=800.00> BB193 regmask=[x4] minReg=1 last wt=800.00> BB193 regmask=[x5] minReg=1 last wt=800.00> BB193 regmask=[x6] minReg=1 last wt=800.00> BB193 regmask=[x7] minReg=1 last wt=800.00> BB193 regmask=[x8] minReg=1 last wt=800.00> BB193 regmask=[x9] minReg=1 last wt=800.00> BB193 regmask=[x10] minReg=1 last wt=800.00> BB193 regmask=[x11] minReg=1 last wt=800.00> BB193 regmask=[x12] minReg=1 last wt=800.00> BB193 regmask=[x13] minReg=1 last wt=800.00> BB193 regmask=[x14] minReg=1 last wt=800.00> BB193 regmask=[x15] minReg=1 last wt=800.00> BB193 regmask=[xip0] minReg=1 last wt=800.00> BB193 regmask=[xip1] minReg=1 last wt=800.00> BB193 regmask=[lr] minReg=1 last wt=800.00> BB193 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> ADD BB199 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB258 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=1200.00> CAST BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> JMPTABLE BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> SWITCH_TABLE BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> NE BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB171 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> OR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB171 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB172 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> IND BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB174 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BFIZ BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB179 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB179 regmask=[x0] minReg=1 fixed wt=26550.00> BB179 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x0] minReg=1 fixed wt=800.00> BB179 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB179 regmask=[x1] minReg=1 last fixed wt=2400.00> BB179 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB179 regmask=[x11] minReg=1 wt=800.00> BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 last fixed wt=200.00> BB179 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB179 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB179 regmask=[x0] minReg=1 wt=200.00> BB179 regmask=[x0] minReg=1 last fixed wt=200.00> BB179 regmask=[x1] minReg=1 wt=200.00> BB179 regmask=[x1] minReg=1 last fixed wt=200.00> BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB179 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB179 regmask=[x0] minReg=1 last wt=200.00> BB179 regmask=[x1] minReg=1 last wt=200.00> BB179 regmask=[x2] minReg=1 last wt=200.00> BB179 regmask=[x3] minReg=1 last wt=200.00> BB179 regmask=[x4] minReg=1 last wt=200.00> BB179 regmask=[x5] minReg=1 last wt=200.00> BB179 regmask=[x6] minReg=1 last wt=200.00> BB179 regmask=[x7] minReg=1 last wt=200.00> BB179 regmask=[x8] minReg=1 last wt=200.00> BB179 regmask=[x9] minReg=1 last wt=200.00> BB179 regmask=[x10] minReg=1 last wt=200.00> BB179 regmask=[x11] minReg=1 last wt=200.00> BB179 regmask=[x12] minReg=1 last wt=200.00> BB179 regmask=[x13] minReg=1 last wt=200.00> BB179 regmask=[x14] minReg=1 last wt=200.00> BB179 regmask=[x15] minReg=1 last wt=200.00> BB179 regmask=[xip0] minReg=1 last wt=200.00> BB179 regmask=[xip1] minReg=1 last wt=200.00> BB179 regmask=[lr] minReg=1 last wt=200.00> CNS_INT BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> CNS_INT BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 last fixed wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> PUTARG_REG BB110 regmask=[x11] minReg=1 fixed wt=0.00> CALL BB110 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 last fixed wt=0.00> CALL BB110 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> BB110 regmask=[x0] minReg=1 last wt=0.00> BB110 regmask=[x1] minReg=1 last wt=0.00> BB110 regmask=[x2] minReg=1 last wt=0.00> BB110 regmask=[x3] minReg=1 last wt=0.00> BB110 regmask=[x4] minReg=1 last wt=0.00> BB110 regmask=[x5] minReg=1 last wt=0.00> BB110 regmask=[x6] minReg=1 last wt=0.00> BB110 regmask=[x7] minReg=1 last wt=0.00> BB110 regmask=[x8] minReg=1 last wt=0.00> BB110 regmask=[x9] minReg=1 last wt=0.00> BB110 regmask=[x10] minReg=1 last wt=0.00> BB110 regmask=[x11] minReg=1 last wt=0.00> BB110 regmask=[x12] minReg=1 last wt=0.00> BB110 regmask=[x13] minReg=1 last wt=0.00> BB110 regmask=[x14] minReg=1 last wt=0.00> BB110 regmask=[x15] minReg=1 last wt=0.00> BB110 regmask=[xip0] minReg=1 last wt=0.00> BB110 regmask=[xip1] minReg=1 last wt=0.00> BB110 regmask=[lr] minReg=1 last wt=0.00> CNS_INT BB254 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB254 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> IND BB254 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB254 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> BB254 regmask=[x0] minReg=1 last wt=0.00> BB254 regmask=[x1] minReg=1 last wt=0.00> BB254 regmask=[x2] minReg=1 last wt=0.00> BB254 regmask=[x3] minReg=1 last wt=0.00> BB254 regmask=[x4] minReg=1 last wt=0.00> BB254 regmask=[x5] minReg=1 last wt=0.00> BB254 regmask=[x6] minReg=1 last wt=0.00> BB254 regmask=[x7] minReg=1 last wt=0.00> BB254 regmask=[x8] minReg=1 last wt=0.00> BB254 regmask=[x9] minReg=1 last wt=0.00> BB254 regmask=[x10] minReg=1 last wt=0.00> BB254 regmask=[x11] minReg=1 last wt=0.00> BB254 regmask=[x12] minReg=1 last wt=0.00> BB254 regmask=[x13] minReg=1 last wt=0.00> BB254 regmask=[x14] minReg=1 last wt=0.00> BB254 regmask=[x15] minReg=1 last wt=0.00> BB254 regmask=[xip0] minReg=1 last wt=0.00> BB254 regmask=[xip1] minReg=1 last wt=0.00> BB254 regmask=[lr] minReg=1 last wt=0.00> ------------ REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval) ------------ ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB111 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB123 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB132 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB185 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB204 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB226 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB229 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB235 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB238 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB244 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB251 regmask=[x0] minReg=1 last fixed wt=26550.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB159 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB168 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB190 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB193 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB179 regmask=[x0] minReg=1 fixed wt=26550.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> ----------------- STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> ----------------- STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB49 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB13 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB247 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB115 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB136 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB139 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB141 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB142 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB143 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB226 regmask=[x3] minReg=1 last fixed wt=23800.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB229 regmask=[x1] minReg=1 last fixed wt=23800.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB244 regmask=[x1] minReg=1 last fixed wt=23800.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> STORE_LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> STORE_LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB156 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB159 regmask=[x1] minReg=1 last fixed wt=23800.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB193 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=19200.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=19200.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=19200.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> ----------------- STORE_LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=8000.00> LCL_VAR BB132 regmask=[x1] minReg=1 last fixed wt=8000.00> ----------------- STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> STORE_LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> STORE_LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> STORE_LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> ----------------- STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> ----------------- STORE_LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> STORE_LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB50 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> STORE_LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB21 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB21 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> STORE_LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> STORE_LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB42 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> STORE_LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> STORE_LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> STORE_LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> ----------------- STORE_LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ----------------- STORE_LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ----------------- STORE_LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ----------------- STORE_LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ----------------- STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB123 regmask=[x1] minReg=1 last fixed wt=4800.00> ----------------- STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB193 regmask=[x1] minReg=1 last fixed wt=4800.00> ----------------- STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB238 regmask=[x1] minReg=1 last fixed wt=4800.00> ----------------- STORE_LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB255 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=4800.00> ----------------- STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB256 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=4800.00> ----------------- STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> STORE_LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB113 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB135 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB145 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> STORE_LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB52 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> LCL_VAR BB24 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> ----------------- STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ----------------- STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ----------------- STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ----------------- STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ----------------- STORE_LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ----------------- STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB150 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ----------------- STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ----------------- STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB18 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> STORE_LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> STORE_LCL_VAR BB55 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB28 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=2700.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB62 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> STORE_LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB226 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- BB00 regmask=[x4] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB226 regmask=[x1] minReg=1 fixed wt=2250.00> LCL_VAR BB251 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB168 regmask=[x1] minReg=1 last fixed wt=2400.00> ----------------- STORE_LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB179 regmask=[x1] minReg=1 last fixed wt=2400.00> ----------------- STORE_LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB181 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB185 regmask=[x1] minReg=1 last fixed wt=2400.00> ----------------- STORE_LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB190 regmask=[x1] minReg=1 last fixed wt=2400.00> ----------------- STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> STORE_LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB221 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> STORE_LCL_VAR BB222 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB226 regmask=[x4] minReg=1 last fixed wt=2400.00> ----------------- STORE_LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> ----------------- STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> ----------------- STORE_LCL_VAR BB119 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=2400.00> ----------------- STORE_LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> ----------------- STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> ----------------- BB00 regmask=[x1] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 fixed wt=2150.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB60 regmask=[x0] minReg=1 fixed wt=2150.00> LCL_VAR BB63 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB64 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB65 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB104 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB172 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB95 regmask=[x1] minReg=1 last fixed wt=1900.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> STORE_LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> STORE_LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> STORE_LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB56 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB223 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB213 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> ----------------- STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> LCL_VAR BB61 regmask=[x0] minReg=1 fixed wt=1500.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1500.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> ----------------- STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> ----------------- STORE_LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> ----------------- STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> LCL_VAR BB204 regmask=[x1] minReg=1 last fixed wt=1200.00> ----------------- STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> LCL_VAR BB235 regmask=[x1] minReg=1 last fixed wt=1200.00> ----------------- STORE_LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB257 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=1200.00> ----------------- STORE_LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB258 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=1200.00> ----------------- STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB89 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> ----------------- STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ----------------- STORE_LCL_VAR BB152 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> STORE_LCL_VAR BB153 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=800.00> ----------------- STORE_LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB232 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ----------------- STORE_LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> STORE_LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB60 regmask=[x1] minReg=1 last fixed wt=800.00> ----------------- STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ----------------- STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ----------------- STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> ----------------- STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB210 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB226 regmask=[x5] minReg=1 last fixed wt=600.00> ----------------- STORE_LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB225 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB226 regmask=[x2] minReg=1 last fixed wt=600.00> ----------------- STORE_LCL_VAR BB147 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB148 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=600.00> ----------------- STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> ----------------- STORE_LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> LCL_VAR BB111 regmask=[x1] minReg=1 last fixed wt=500.00> ----------------- STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> ----------------- STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> ----------------- STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> ----------------- STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0] minReg=1 last fixed wt=400.00> ----------------- STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> ----------------- STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> ----------------- STORE_LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> ----------------- STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x0] minReg=1 last fixed wt=250.00> ----------------- STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x2] minReg=1 last fixed wt=250.00> ----------------- STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x1] minReg=1 last fixed wt=250.00> ----------------- STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ----------------- STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ----------------- STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ----------------- STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ----------------- STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ----------------- STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ----------------- STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ----------------- STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ----------------- STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ----------------- STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ----------------- STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> ----------------- STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 V03 V01 BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ===== N003. IL_OFFSET INLRT @ 0x000[E-] N005. V01(L1) N007. PUTARG_REG Use:(#5) Fixed:x0(#4) Def:(#7) x0 Pref: N009. CNS_INT(h) 0x400000000046ac80 ftn Def:(#8) N011. PUTARG_REG Use:(#10) Fixed:x11(#9) * Def:(#12) x11 N013. CALL r2r_ind Def:(#13) Use:(#15) Fixed:x0(#14) * Use:(#17) Fixed:x11(#16) * Use:(#18) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr N015. IL_OFFSET INLRT @ 0x006[E-] N017. CNS_INT 0 N019. V11(L10) Def:(#38) N021. IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] N023. V01(L1) N025. CNS_INT 16 N027. ADD Use:(#39) Def:(#40) Pref: N029. V76(L60) Use:(#41) * Def:(#42) N031. IL_OFFSET INLRT @ 0x009[E-] N033. CNS_INT 0 N035. V76(L60) N037. LEA(b+8) N039. IND Use:(#43) Def:(#44) N041. BOUNDS_CHECK_Rng -> BB254 Use:(#45) * N043. V76(L60) N045. IND Use:(#46) * Def:(#47) Pref: N047. V167(L119) Use:(#48) * Def:(#49) Pref: N049. V167(L119) N051. V17(L16) Use:(#50) * Def:(#51) N053. V02 MEM Def:(#52) Pref: N055. V180(L131) Use:(#53) * Def:(#54) Pref: N057. V180(L131) N059. V147(L105) Use:(#55) Def:(#56) Pref: N061. V02 MEM Def:(#57) Pref: N063. V179(L130) Use:(#58) * Def:(#59) N065. V179(L130) N067. V148(L106) Use:(#60) Def:(#61) Pref: N069. IL_OFFSET INLRT @ 0x011[E-] N071. V17(L16) N073. IND Use:(#62) Def:(#63) N075. CNS_INT 0 N077. JCMP Use:(#64) * BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N081. V147(L105) N083. V155(L110) Use:(#66) * Def:(#67) Pref: N085. V148(L106) N087. V156(L111) Use:(#68) * Def:(#69) Pref: N089. V01(L1) N091. LEA(b+8) N093. IND Use:(#70) Def:(#71) N095. CNS_INT 0 N097. JCMP Use:(#72) * BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ===== N101. V155(L110) N103. V149(L107) Use:(#74) * Def:(#75) N105. V156(L111) N107. V150(L108) Use:(#76) * Def:(#77) N109. CNS_INT 0 N111. V43(L33) Def:(#78) BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ===== N115. V155(L110) N117. V149(L107) Use:(#80) * Def:(#81) N119. V156(L111) N121. V150(L108) Use:(#82) * Def:(#83) N123. CNS_INT 1 Def:(#84) Pref: N125. V43(L33) Use:(#85) * Def:(#86) BB05 [025..026), preds={BB01} succs={BB06} ===== N129. V147(L105) N131. V149(L107) Use:(#88) * Def:(#89) N133. V148(L106) N135. V150(L108) Use:(#90) * Def:(#91) N137. CNS_INT 2 Def:(#92) Pref: N139. V43(L33) Use:(#93) * Def:(#94) BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ===== N143. V149(L107) N145. PUTARG_REG Use:(#97) Fixed:x0(#96) * Def:(#99) x0 N147. V150(L108) N149. PUTARG_REG Use:(#101) Fixed:x1(#100) * Def:(#103) x1 N151. FIELD_LIST N153. V43(L33) N155. PUTARG_REG Use:(#105) Fixed:x2(#104) * Def:(#107) x2 N157. CNS_INT(h) 0x40000000005401e8 ftn Def:(#108) N159. PUTARG_REG Use:(#110) Fixed:x11(#109) * Def:(#112) x11 N161. CALL r2r_ind Def:(#113) Use:(#115) Fixed:x0(#114) * Use:(#117) Fixed:x1(#116) * Use:(#119) Fixed:x2(#118) * Use:(#121) Fixed:x11(#120) * Use:(#122) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr Def:(#143) x0 Pref: N163. V15(L14) Use:(#144) * Def:(#145) BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ===== N167. IL_OFFSET INLRT @ 0x02D[E-] N169. CNS_INT 0 N171. V04(L3) Def:(#147) N173. IL_OFFSET INLRT @ 0x02F[E-] N175. CNS_INT -1 Def:(#148) Pref: N177. V05(L4) Use:(#149) * Def:(#150) N179. IL_OFFSET INLRT @ 0x031[E-] N181. CNS_INT 0x7FFFFFFF Def:(#151) Pref: N183. V06(L5) Use:(#152) * Def:(#153) N185. IL_OFFSET INLRT @ 0x037[E-] N187. CNS_INT 0 N189. V07(L6) Def:(#154) N191. IL_OFFSET INLRT @ 0x039[E-] N193. CNS_INT 0 N195. V09(L8) Def:(#155) N197. IL_OFFSET INLRT @ 0x03C[E-] N199. CNS_INT -1 Def:(#156) Pref: N201. V10(L9) Use:(#157) * Def:(#158) N203. IL_OFFSET INLRT @ 0x03F[E-] N205. CNS_INT 0 N207. V12(L11) Def:(#159) N209. IL_OFFSET INLRT @ 0x042[E-] N211. CNS_INT 0 N213. V13(L12) Def:(#160) N215. IL_OFFSET INLRT @ 0x045[E-] N217. V15(L14) N219. V16(L15) Use:(#161) Def:(#162) Pref: N221. IL_OFFSET INLRT @ 0x049[E-] N223. V180(L131) N225. V157(L112) Use:(#163) Def:(#164) Pref: N227. IL_OFFSET INLRT @ 0x049[E-] N229. V157(L112) N231. V23 MEM Use:(#165) N233. IL_OFFSET INLRT @ 0x051[E-] N235. V157(L112) N237. V168(L120) Use:(#166) * Def:(#167) Pref: N239. V168(L120) N241. V22(L20) Use:(#168) * Def:(#169) BB47 [204..20F) -> BB50 (cond), preds={BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB255(2),BB256(2)} succs={BB48,BB50} ===== N245. IL_OFFSET INLRT @ 0x204[E-] N247. V16(L15) N249. V179(L130) N251. GE Use:(#171) Use:(#172) N253. JTRUE BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ===== N257. IL_OFFSET INLRT @ 0x20F[E-] N259. V16(L15) N261. V71(L56) Use:(#174) * Def:(#175) N263. IL_OFFSET INLRT @ 0x20F[E-] N265. V71(L56) N267. CNS_INT 1 N269. ADD Use:(#176) Def:(#177) Pref: N271. V16(L15) Use:(#178) * Def:(#179) Pref: N273. V22(L20) N275. V71(L56) N277. CAST N279. CNS_INT 1 N281. BFIZ N283. LEA(b+(i*1)+0) N285. IND Use:(#180) Use:(#181) * Def:(#182) Pref: N287. V72(L57) Use:(#183) * Def:(#184) Pref: N289. V72(L57) N291. V18(L17) Use:(#185) * Def:(#186) N293. V18(L17) N295. CNS_INT 0 N297. JCMP Use:(#187) BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ===== N301. IL_OFFSET INLRT @ 0x222[E-] N303. V18(L17) N305. CNS_INT 59 N307. NE Use:(#189) N309. JTRUE BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ===== N313. IL_OFFSET INLRT @ 0x05B[E-] N315. V18(L17) N317. CNS_INT 69 N319. GT Use:(#191) N321. JTRUE BB09 [061..061) -> BB10 (cond), preds={BB08} succs={BB255,BB10} ===== N325. IL_OFFSET INLRT @ 0x061[E-] N327. V18(L17) N329. CNS_INT -34 N331. ADD Use:(#193) Def:(#194) Pref: N333. V182(L133) Use:(#195) * Def:(#196) N335. V182(L133) N337. CNS_INT 5 N339. GT Use:(#197) N341. JTRUE BB10 [083..083) -> BB11 (cond), preds={BB09} succs={BB256,BB11} ===== N345. IL_OFFSET INLRT @ 0x083[E-] N347. V18(L17) N349. CNS_INT -44 N351. ADD Use:(#199) Def:(#200) Pref: N353. V183(L134) Use:(#201) * Def:(#202) N355. V183(L134) N357. CNS_INT 4 N359. GT Use:(#203) N361. JTRUE BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ===== N365. IL_OFFSET INLRT @ 0x0A1[E-] N367. V18(L17) N369. CNS_INT 69 N371. EQ Use:(#205) * N373. JTRUE BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ===== BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ===== N379. IL_OFFSET INLRT @ 0x0AF[E-] N381. V18(L17) N383. CNS_INT 92 N385. EQ Use:(#208) N387. JTRUE BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ===== N391. IL_OFFSET INLRT @ 0x0B8[E-] N393. V18(L17) N395. CNS_INT 101 N397. EQ Use:(#210) N399. JTRUE BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ===== N403. IL_OFFSET INLRT @ 0x0C1[E-] N405. V18(L17) N407. CNS_INT 0x2030 Def:(#212) N409. NE Use:(#213) * Use:(#214) * N411. JTRUE BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ===== N415. IL_OFFSET INLRT @ 0x137[E-] N417. V13(L12) N419. CNS_INT 3 N421. ADD Use:(#216) * Def:(#217) Pref: N423. V13(L12) Use:(#218) * Def:(#219) BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ===== N427. IL_OFFSET INLRT @ 0x175[E-] N429. V16(L15) N431. V179(L130) N433. GE N435. V22(L20) N437. V16(L15) N439. CAST N441. CNS_INT 1 N443. BFIZ N445. LEA(b+(i*1)+0) N447. IND Use:(#221) Use:(#222) Def:(#223) Pref: N449. V174(L125) Use:(#224) * Def:(#225) N451. V174(L125) N453. CNS_INT 0 N455. EQ N457. AND N459. JTRUE Use:(#226) Use:(#227) Use:(#228) * BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} ===== N463. IL_OFFSET INLRT @ 0x183[E-] N465. IL_OFFSET INLRT @ 0x18E[E-] N467. V16(L15) N469. CNS_INT 1 N471. ADD Use:(#230) * Def:(#231) Pref: N473. V16(L15) Use:(#232) * Def:(#233) Pref: BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ===== N477. IL_OFFSET INLRT @ 0x196[E-] N479. V16(L15) N481. V179(L130) N483. GE Use:(#235) Use:(#236) N485. JTRUE BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ===== N489. IL_OFFSET INLRT @ 0x1A1[E-] N491. V22(L20) N493. V16(L15) N495. CAST N497. CNS_INT 1 N499. BFIZ N501. LEA(b+(i*1)+0) N503. IND Use:(#238) Use:(#239) Def:(#240) Pref: N505. V174(L125) Use:(#241) * Def:(#242) N507. V174(L125) N509. CNS_INT 48 N511. EQ Use:(#243) * N513. JTRUE BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ===== N517. IL_OFFSET INLRT @ 0x1AE[E-] N519. V16(L15) N521. CNS_INT 1 N523. ADD Use:(#245) Def:(#246) N525. V179(L130) N527. GE Use:(#247) * Use:(#248) N529. JTRUE BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ===== N533. IL_OFFSET INLRT @ 0x1BB[E-] N535. V22(L20) N537. V16(L15) N539. CAST N541. CNS_INT 1 N543. BFIZ N545. LEA(b+(i*1)+0) N547. IND Use:(#250) Use:(#251) Def:(#252) Pref: N549. V174(L125) Use:(#253) * Def:(#254) N551. V174(L125) N553. CNS_INT 43 N555. EQ Use:(#255) N557. JTRUE BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ===== N561. IL_OFFSET INLRT @ 0x1C8[E-] N563. V174(L125) N565. CNS_INT 45 N567. NE Use:(#257) * N569. JTRUE BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB44,BB47} ===== N573. IL_OFFSET INLRT @ 0x1D5[E-] N575. V22(L20) N577. V16(L15) N579. CNS_INT 1 N581. ADD Use:(#259) Def:(#260) N583. CAST N585. CNS_INT 1 N587. BFIZ N589. LEA(b+(i*1)+0) N591. IND Use:(#261) Use:(#262) * Def:(#263) N593. CNS_INT 48 N595. NE Use:(#264) * N597. JTRUE Exposed use of V09 at #265 BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB43,BB45} succs={BB45,BB46} ===== N601. IL_OFFSET INLRT @ 0x1E4[E-] N603. V16(L15) N605. CNS_INT 1 N607. ADD Use:(#267) * Def:(#268) Pref: N609. V73(L58) Use:(#269) * Def:(#270) Pref: N611. V73(L58) N613. V16(L15) Use:(#271) * Def:(#272) Pref: N615. V16(L15) N617. V179(L130) N619. GE Use:(#273) Use:(#274) N621. JTRUE BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ===== N625. IL_OFFSET INLRT @ 0x1F4[E-] N627. V22(L20) N629. V16(L15) N631. CAST N633. CNS_INT 1 N635. BFIZ N637. LEA(b+(i*1)+0) N639. IND Use:(#276) Use:(#277) Def:(#278) N641. CNS_INT 48 N643. EQ Use:(#279) * N645. JTRUE BB46 [201..204), preds={BB44,BB45} succs={BB47} ===== N649. IL_OFFSET INLRT @ 0x201[E-] N651. CNS_INT 1 Def:(#281) Pref: N653. V09(L8) Use:(#282) * Def:(#283) Exposed use of V16 at #284 Exposed use of V22 at #285 BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ===== N657. IL_OFFSET INLRT @ 0x22B[E-] N659. CNS_INT 0 N661. V23 MEM N663. IL_OFFSET INLRT @ 0x22F[E-] N665. V05(L4) N667. CNS_INT 0 N669. GE Use:(#287) N671. JTRUE BB51 [233..235), preds={BB50} succs={BB52} ===== N675. IL_OFFSET INLRT @ 0x233[E-] N677. V04(L3) N679. V05(L4) Use:(#289) Def:(#290) BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ===== N683. IL_OFFSET INLRT @ 0x235[E-] N685. V10(L9) N687. CNS_INT 0 N689. LT Use:(#292) N691. JTRUE BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ===== N695. IL_OFFSET INLRT @ 0x23A[E-] N697. V10(L9) N699. V05(L4) N701. NE Use:(#294) * Use:(#295) N703. JTRUE BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ===== N707. IL_OFFSET INLRT @ 0x23F[E-] N709. V13(L12) N711. V11(L10) N713. CNS_INT 3 Def:(#297) N715. MUL N717. SUB Use:(#298) * Use:(#299) Use:(#300) * Def:(#301) Pref: N719. V13(L12) Use:(#302) * Def:(#303) BB55 [24A..24D), preds={BB53} succs={BB56} ===== N723. IL_OFFSET INLRT @ 0x24A[E-] N725. CNS_INT 1 Def:(#305) Pref: N727. V12(L11) Use:(#306) * Def:(#307) BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ===== N731. IL_OFFSET INLRT @ 0x24D[E-] N733. V17(L16) N735. IND Use:(#309) Def:(#310) N737. CNS_INT 0 N739. JCMP Use:(#311) * BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ===== N743. IL_OFFSET INLRT @ 0x252[E-] N745. V01(L1) N747. CNS_INT 4 N749. ADD Use:(#313) Def:(#314) Pref: N751. V69(L54) Use:(#315) * Def:(#316) N753. V69(L54) N755. IND Use:(#317) Def:(#318) N757. V13(L12) N759. ADD Use:(#319) * Use:(#320) * Def:(#321) N761. V69(L54) N763. STOREIND Use:(#322) * Use:(#323) * N765. IL_OFFSET INLRT @ 0x25E[E-] N767. V09(L8) N769. CNS_INT 0 N771. JCMP Use:(#324) BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ===== N775. IL_OFFSET INLRT @ 0x262[E-] N777. V01(L1) N779. LEA(b+4) N781. IND Use:(#326) Def:(#327) N783. V04(L3) N785. ADD Use:(#328) * Use:(#329) Def:(#330) N787. V05(L4) N789. SUB Use:(#331) * Use:(#332) Def:(#333) Pref: N791. V70(L55) Use:(#334) * Def:(#335) BB59 [26E..26F), preds={BB57} succs={BB60} ===== N795. IL_OFFSET INLRT @ 0x26E[E-] N797. V04(L3) N799. V70(L55) Use:(#337) Def:(#338) BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ===== N803. IL_OFFSET INLRT @ 0x271[E-] N805. V70(L55) N807. PUTARG_REG Use:(#341) Fixed:x1(#340) * Def:(#343) x1 N809. V01(L1) N811. PUTARG_REG Use:(#345) Fixed:x0(#344) Def:(#347) x0 Pref: N813. CNS_INT(h) 0x400000000046acb8 ftn Def:(#348) N815. PUTARG_REG Use:(#350) Fixed:x11(#349) * Def:(#352) x11 N817. CNS_INT 0 Def:(#353) N819. PUTARG_REG Use:(#355) Fixed:x2(#354) * Def:(#357) x2 N821. CALL r2r_ind Def:(#358) Use:(#360) Fixed:x1(#359) * Use:(#362) Fixed:x0(#361) * Use:(#364) Fixed:x11(#363) * Use:(#366) Fixed:x2(#365) * Use:(#367) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr N823. IL_OFFSET INLRT @ 0x27A[E-] N825. V17(L16) N827. IND Use:(#387) Def:(#388) N829. CNS_INT 0 N831. JCMP Use:(#389) * BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ===== N835. IL_OFFSET INLRT @ 0x27F[E-] N837. V180(L131) N839. PUTARG_REG Use:(#392) Fixed:x0(#391) Def:(#394) x0 Pref: N841. V02 MEM Def:(#395) N843. PUTARG_REG Use:(#397) Fixed:x1(#396) * Def:(#399) x1 N845. FIELD_LIST N847. CNS_INT(h) 0x40000000005401e8 ftn Def:(#400) N849. PUTARG_REG Use:(#402) Fixed:x11(#401) * Def:(#404) x11 N851. CNS_INT 2 Def:(#405) N853. PUTARG_REG Use:(#407) Fixed:x2(#406) * Def:(#409) x2 N855. CALL r2r_ind Def:(#410) Use:(#412) Fixed:x0(#411) * Use:(#414) Fixed:x1(#413) * Use:(#416) Fixed:x11(#415) * Use:(#418) Fixed:x2(#417) * Use:(#419) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr Def:(#440) x0 Pref: N857. V16(L15) Use:(#441) * Def:(#442) Pref: N859. IL_OFFSET INLRT @ 0x288[E-] N861. V16(L15) N863. V15(L14) N865. EQ Use:(#443) Use:(#444) N867. JTRUE BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ===== N871. IL_OFFSET INLRT @ 0x28E[E-] N873. V16(L15) N875. V15(L14) Use:(#446) * Def:(#447) Exposed use of V11 at #448 BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ===== N879. IL_OFFSET INLRT @ 0x297[E-] N881. V01(L1) N883. LEA(b+10) N885. IND Use:(#450) Def:(#451) N887. CNS_INT 3 N889. EQ Use:(#452) * N891. JTRUE BB64 [2A0..2A7), preds={BB63} succs={BB65} ===== N895. IL_OFFSET INLRT @ 0x2A0[E-] N897. V01(L1) N899. LEA(b+8) N901. CNS_INT 0 N903. STOREIND Use:(#454) BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ===== N907. IL_OFFSET INLRT @ 0x2A7[E-] N909. V01(L1) N911. LEA(b+4) N913. CNS_INT 0 N915. STOREIND Use:(#456) BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} ===== N919. IL_OFFSET INLRT @ 0x2AE[E-] N921. IL_OFFSET INLRT @ 0x2B2[E-] N923. V06(L5) N925. V05(L4) N927. LT N929. V05(L4) N931. V06(L5) N933. SUB Use:(#458) Use:(#459) Def:(#460) N935. CNS_INT 0 N937. SELECT Use:(#461) * Use:(#462) Use:(#463) * Def:(#464) Pref: N939. V44(L34) Use:(#465) * Def:(#466) Pref: N941. IL_OFFSET INLRT @ 0x2B5[E-] N943. V44(L34) N945. V06(L5) Use:(#467) * Def:(#468) N947. IL_OFFSET INLRT @ 0x2B9[E-] N949. IL_OFFSET INLRT @ 0x2BD[E-] N951. V07(L6) N953. V05(L4) N955. GT N957. V05(L4) N959. V07(L6) N961. SUB Use:(#469) Use:(#470) Def:(#471) N963. CNS_INT 0 N965. SELECT Use:(#472) * Use:(#473) Use:(#474) * Def:(#475) Pref: N967. V45(L35) Use:(#476) * Def:(#477) Pref: N969. IL_OFFSET INLRT @ 0x2C0[E-] N971. V45(L35) N973. V07(L6) Use:(#478) * Def:(#479) N975. IL_OFFSET INLRT @ 0x2C4[E-] N977. V09(L8) N979. CNS_INT 0 N981. JCMP Use:(#480) BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} ===== N985. IL_OFFSET INLRT @ 0x2C8[E-] N987. V05(L4) N989. V08(L7) Use:(#482) Def:(#483) N991. IL_OFFSET INLRT @ 0x2CB[E-] N993. CNS_INT 0 N995. V14(L13) Def:(#484) BB74 [2D0..2EE), preds={BB66} succs={BB78} ===== N999. IL_OFFSET INLRT @ 0x2D0[E-] N1001. IL_OFFSET INLRT @ 0x2D9[E-] N1003. V01(L1) N1005. LEA(b+4) N1007. IND Use:(#486) Def:(#487) Pref: N1009. V178(L129) Use:(#488) * Def:(#489) N1011. V178(L129) N1013. V05(L4) N1015. GT N1017. V178(L129) N1019. V05(L4) N1021. SELECT Use:(#490) Use:(#491) Use:(#492) Use:(#493) Def:(#494) Pref: N1023. V46(L36) Use:(#495) * Def:(#496) Pref: N1025. IL_OFFSET INLRT @ 0x2DC[E-] N1027. V46(L36) N1029. V08(L7) Use:(#497) * Def:(#498) N1031. IL_OFFSET INLRT @ 0x2E4[E-] N1033. V178(L129) N1035. V05(L4) N1037. SUB Use:(#499) * Use:(#500) Def:(#501) Pref: N1039. V14(L13) Use:(#502) * Def:(#503) BB78 [000..30D) -> BB103 (cond), preds={BB73,BB74} succs={BB79,BB103} ===== N1043. IL_OFFSET INLRT @ 0x2EE[E-] N1045. V15(L14) N1047. V16(L15) Use:(#505) Def:(#506) Pref: N1049. IL_OFFSET INLRT @ 0x2F2[E-] N1051. IL_OFFSET INL09 @ 0x01F[E-] <- INLRT @ ??? N1053. LCL_VAR_ADDR V47 tmp7 NA Def:(#507) Pref: N1055. V151(L109) Use:(#508) * Def:(#509) Pref: N1057. IL_OFFSET INL09 @ 0x026[E-] <- INLRT @ ??? N1059. IL_OFFSET INLRT @ 0x2FF[E-] N1061. V151(L109) N1063. V143(L103) Use:(#510) * Def:(#511) N1065. CNS_INT 4 Def:(#512) Pref: N1067. V144(L104) Use:(#513) * Def:(#514) N1069. IL_OFFSET INLRT @ 0x303[E-] N1071. CNS_INT -1 Def:(#515) Pref: N1073. V20(L18) Use:(#516) * Def:(#517) N1075. IL_OFFSET INLRT @ 0x306[E-] N1077. V03(L2) N1079. LEA(b+56) N1081. IND Use:(#518) Def:(#519) N1083. LEA(b+8) N1085. IND Use:(#520) * Def:(#521) N1087. CNS_INT 0 N1089. LE N1091. V12(L11) N1093. CNS_INT 0 N1095. EQ N1097. AND N1099. JTRUE Use:(#522) * Use:(#523) BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} ===== N1103. IL_OFFSET INLRT @ 0x30D[E-] N1105. IL_OFFSET INLRT @ 0x31E[E-] N1107. V03(L2) N1109. LEA(b+8) N1111. IND Use:(#525) Def:(#526) Pref: N1113. V26(L21) Use:(#527) * Def:(#528) N1115. IL_OFFSET INLRT @ 0x326[E-] N1117. CNS_INT 0 N1119. V27(L22) Def:(#529) N1121. IL_OFFSET INLRT @ 0x329[E-] N1123. CNS_INT 0 N1125. V28(L23) Def:(#530) N1127. IL_OFFSET INLRT @ 0x32C[E-] N1129. V26(L21) N1131. LEA(b+8) N1133. IND Use:(#531) Def:(#532) Pref: N1135. V29(L24) Use:(#533) * Def:(#534) N1137. IL_OFFSET INLRT @ 0x332[E-] N1139. V29(L24) N1141. CNS_INT 0 N1143. JCMP Use:(#535) BB81 [336..33D), preds={BB79} succs={BB82} ===== N1147. IL_OFFSET INLRT @ 0x336[E-] N1149. V26(L21) N1151. LEA(b+16) N1153. IND Use:(#537) Def:(#538) Pref: N1155. V28(L23) Use:(#539) * Def:(#540) BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} ===== N1159. IL_OFFSET INLRT @ 0x33D[E-] N1161. V28(L23) N1163. V30(L25) Use:(#542) Def:(#543) N1165. V08(L7) N1167. V64(L50) Use:(#544) Def:(#545) Pref: N1169. IL_OFFSET INLRT @ 0x341[E-] N1171. V14(L13) N1173. CNS_INT 0 N1175. LT Use:(#546) N1177. JTRUE BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ===== N1181. V64(L50) N1183. V65(L51) Use:(#548) * Def:(#549) N1185. CNS_INT 0 N1187. V66(L52) Def:(#550) BB84 [34B..34D), preds={BB82} succs={BB85} ===== N1191. V64(L50) N1193. V65(L51) Use:(#552) * Def:(#553) N1195. V14(L13) N1197. V66(L52) Use:(#554) Def:(#555) BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} ===== N1201. V65(L51) N1203. V66(L52) N1205. ADD Use:(#557) * Use:(#558) * Def:(#559) Pref: N1207. V31(L26) Use:(#560) * Def:(#561) N1209. IL_OFFSET INLRT @ 0x350[E-] N1211. IL_OFFSET INLRT @ 0x355[E-] N1213. V06(L5) N1215. V31(L26) N1217. GT N1219. V06(L5) N1221. V31(L26) N1223. SELECT Use:(#562) Use:(#563) Use:(#564) Use:(#565) * Def:(#566) Pref: N1225. V67(L53) Use:(#567) * Def:(#568) Pref: N1227. IL_OFFSET INLRT @ 0x359[E-] N1229. V67(L53) N1231. V32(L27) Use:(#569) * Def:(#570) N1233. IL_OFFSET INLRT @ 0x3C2[E-] N1235. V32(L27) N1237. V30(L25) N1239. LE Use:(#571) Use:(#572) N1241. JTRUE BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} ===== N1245. IL_OFFSET INLRT @ 0x35E[E-] N1247. V30(L25) N1249. CNS_INT 0 N1251. JCMP Use:(#574) BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ===== N1255. IL_OFFSET INLRT @ 0x362[E-] N1257. V20(L18) N1259. CNS_INT 1 N1261. ADD Use:(#576) * Def:(#577) Pref: N1263. V20(L18) Use:(#578) * Def:(#579) N1265. IL_OFFSET INLRT @ 0x368[E-] N1267. V20(L18) N1269. V144(L104) N1271. LT Use:(#580) Use:(#581) N1273. JTRUE BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} ===== N1277. IL_OFFSET INLRT @ 0x373[E-] N1279. V144(L104) N1281. CNS_INT 1 N1283. LSH Use:(#583) Def:(#584) N1285. CAST Use:(#585) * Def:(#586) N1287. PUTARG_REG Use:(#588) Fixed:x0(#587) * Def:(#590) x0 N1289. CNS_INT(h) 0x4000000000421858 ftn Def:(#591) N1291. PUTARG_REG Use:(#593) Fixed:x11(#592) * Def:(#595) x11 N1293. CALL help r2r_ind Def:(#596) Use:(#598) Fixed:x0(#597) * Use:(#600) Fixed:x11(#599) * Use:(#601) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr Def:(#622) x0 Pref: N1295. V33(L28) Use:(#623) * Def:(#624) N1297. IL_OFFSET INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] N1299. IL_OFFSET INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N1301. V33(L28) N1303. CNS_INT 16 Fseq[] N1305. ADD Use:(#625) Def:(#626) Pref: N1307. V159(L113) Use:(#627) * Def:(#628) Pref: N1309. IL_OFFSET INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N1311. V33(L28) N1313. LEA(b+8) N1315. IND Use:(#629) Def:(#630) Pref: N1317. V160(L114) Use:(#631) * Def:(#632) N1319. V159(L113) N1321. V161(L115) Use:(#633) * Def:(#634) N1323. V144(L104) N1325. V160(L114) N1327. GT Use:(#635) Use:(#636) * N1329. JTRUE BB95 [000..392), preds={BB91} succs={BB100} ===== N1333. IL_OFFSET INL17 @ 0x00F[E-] <- INLRT @ ??? N1335. V144(L104) N1337. CAST Use:(#638) * Def:(#639) Pref: N1339. V83(L61) Use:(#640) * Def:(#641) N1341. IL_OFFSET INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? N1343. V83(L61) N1345. CNS_INT 2 N1347. LSH Use:(#642) * Def:(#643) N1349. PUTARG_REG Use:(#645) Fixed:x2(#644) * Def:(#647) x2 N1351. V161(L115) N1353. PUTARG_REG Use:(#649) Fixed:x0(#648) * Def:(#651) x0 N1355. V143(L103) N1357. PUTARG_REG Use:(#653) Fixed:x1(#652) * Def:(#655) x1 N1359. CNS_INT(h) 0x4000000000420490 ftn Def:(#656) N1361. PUTARG_REG Use:(#658) Fixed:x11(#657) * Def:(#660) x11 N1363. CALL r2r_ind Def:(#661) Use:(#663) Fixed:x2(#662) * Use:(#665) Fixed:x0(#664) * Use:(#667) Fixed:x1(#666) * Use:(#669) Fixed:x11(#668) * Use:(#670) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr N1365. IL_OFFSET INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] N1367. IL_OFFSET INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N1369. V33(L28) N1371. CNS_INT 16 Fseq[] N1373. ADD Use:(#690) Def:(#691) Pref: N1375. V163(L116) Use:(#692) * Def:(#693) Pref: N1377. IL_OFFSET INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N1379. V33(L28) N1381. LEA(b+8) N1383. IND Use:(#694) * Def:(#695) Pref: N1385. V164(L117) Use:(#696) * Def:(#697) Pref: N1387. IL_OFFSET INLRT @ 0x391[E-] N1389. V163(L116) N1391. V143(L103) Use:(#698) * Def:(#699) N1393. V164(L117) N1395. V144(L104) Use:(#700) * Def:(#701) BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} ===== N1399. IL_OFFSET INLRT @ 0x39A[E-] N1401. V20(L18) N1403. V144(L104) N1405. BOUNDS_CHECK_Rng -> BB254 Use:(#703) Use:(#704) N1407. V143(L103) N1409. V20(L18) N1411. CAST N1413. CNS_INT 2 N1415. BFIZ N1417. LEA(b+(i*1)+0) N1419. V28(L23) N1421. STOREIND Use:(#705) Use:(#706) Use:(#707) N1423. IL_OFFSET INLRT @ 0x3A6[E-] N1425. V27(L22) N1427. V29(L24) N1429. CNS_INT -1 N1431. ADD Use:(#708) Def:(#709) N1433. GE Use:(#710) Use:(#711) * N1435. JTRUE BB101 [3AE..3BB), preds={BB100} succs={BB102} ===== N1439. IL_OFFSET INLRT @ 0x3AE[E-] N1441. V27(L22) N1443. CNS_INT 1 N1445. ADD Use:(#713) * Def:(#714) Pref: N1447. V27(L22) Use:(#715) * Def:(#716) N1449. IL_OFFSET INLRT @ 0x3B4[E-] N1451. V27(L22) N1453. V26(L21) N1455. LEA(b+8) N1457. IND Use:(#717) Def:(#718) N1459. BOUNDS_CHECK_Rng -> BB254 Use:(#719) Use:(#720) * N1461. V26(L21) N1463. CNS_INT 16 N1465. ADD Use:(#721) Def:(#722) N1467. V27(L22) N1469. CAST N1471. CNS_INT 2 N1473. BFIZ N1475. LEA(b+(i*1)+0) N1477. IND Use:(#723) * Use:(#724) Def:(#725) Pref: N1479. V30(L25) Use:(#726) * Def:(#727) BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ===== N1483. IL_OFFSET INLRT @ 0x3BB[E-] N1485. V28(L23) N1487. V30(L25) N1489. ADD Use:(#729) * Use:(#730) Def:(#731) Pref: N1491. V28(L23) Use:(#732) * Def:(#733) N1493. IL_OFFSET INLRT @ 0x3C2[E-] N1495. V32(L27) N1497. V28(L23) N1499. GT Use:(#734) Use:(#735) N1501. JTRUE Exposed use of V28 at #736 Exposed use of V27 at #737 Exposed use of V30 at #738 Exposed use of V26 at #739 Exposed use of V29 at #740 Exposed use of V32 at #741 BB103 [3C8..3D0) -> BB112 (cond), preds={BB78,BB85,BB89,BB102} succs={BB104,BB112} ===== N1505. IL_OFFSET INLRT @ 0x3C8[E-] N1507. V01(L1) N1509. LEA(b+8) N1511. IND Use:(#743) Def:(#744) N1513. CNS_INT 0 N1515. EQ N1517. V16(L15) N1519. CNS_INT 0 N1521. NE N1523. AND N1525. JTRUE Use:(#745) * Use:(#746) BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} ===== N1529. IL_OFFSET INLRT @ 0x3D0[E-] N1531. IL_OFFSET INLRT @ 0x3D4[E-] N1533. V01(L1) N1535. LEA(b+4) N1537. IND Use:(#748) Def:(#749) N1539. CNS_INT 0 N1541. JCMP Use:(#750) * BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} ===== N1545. IL_OFFSET INLRT @ 0x3DC[E-] N1547. V03(L2) N1549. LEA(b+40) N1551. IND Use:(#752) Def:(#753) Pref: N1553. V86(L62) Use:(#754) * Def:(#755) N1555. IL_OFFSET INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] N1557. V86(L62) N1559. CNS_INT null N1561. JCMP Use:(#756) BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ===== N1565. IL_OFFSET INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] N1567. V00(L0) N1569. LEA(b+8) N1571. IND Use:(#758) Def:(#759) Pref: N1573. V87(L63) Use:(#760) * Def:(#761) N1575. IL_OFFSET INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] N1577. V86(L62) N1579. LEA(b+8) N1581. IND Use:(#762) Def:(#763) N1583. CNS_INT 1 N1585. NE N1587. V87(L63) N1589. V00(L0) N1591. LEA(b+24) N1593. IND Use:(#764) Def:(#765) N1595. GE N1597. AND N1599. JTRUE Use:(#766) * Use:(#767) Use:(#768) * BB108 [3DC..3DD), preds={BB107} succs={BB112} ===== N1603. IL_OFFSET INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] N1605. IL_OFFSET INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] N1607. V00(L0) N1609. CNS_INT 16 N1611. ADD Use:(#770) Def:(#771) Pref: N1613. V88(L64) Use:(#772) * Def:(#773) N1615. IL_OFFSET INL26 @ ??? <- INLRT @ 0x3DC[E-] N1617. V87(L63) N1619. V88(L64) N1621. LEA(b+8) N1623. IND Use:(#774) Def:(#775) N1625. BOUNDS_CHECK_Rng -> BB254 Use:(#776) Use:(#777) * N1627. V88(L64) N1629. IND Use:(#778) * Def:(#779) N1631. V87(L63) N1633. CAST N1635. CNS_INT 1 N1637. BFIZ Use:(#780) Def:(#781) N1639. ADD Use:(#782) * Use:(#783) * Def:(#784) N1641. V86(L62) N1643. LEA(b+12) N1645. IND Use:(#785) * Def:(#786) N1647. STOREIND Use:(#787) * Use:(#788) * N1649. IL_OFFSET INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] N1651. V87(L63) N1653. CNS_INT 1 N1655. ADD Use:(#789) * Def:(#790) N1657. V00(L0) N1659. LEA(b+8) N1661. STOREIND Use:(#791) Use:(#792) * BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} ===== N1665. IL_OFFSET INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] N1667. V00(L0) N1669. PUTARG_REG Use:(#795) Fixed:x0(#794) Def:(#797) x0 Pref: N1671. V86(L62) N1673. PUTARG_REG Use:(#799) Fixed:x1(#798) * Def:(#801) x1 N1675. CNS_INT(h) 0x4000000000431d58 ftn Def:(#802) N1677. PUTARG_REG Use:(#804) Fixed:x11(#803) * Def:(#806) x11 N1679. CALL r2r_ind Def:(#807) Use:(#809) Fixed:x0(#808) * Use:(#811) Fixed:x1(#810) * Use:(#813) Fixed:x11(#812) * Use:(#814) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} ===== N1683. IL_OFFSET INLRT @ 0x3E8[E-] N1685. CNS_INT 0 N1687. V21(L19) Def:(#835) N1689. IL_OFFSET INLRT @ 0x3EB[E-] N1691. V180(L131) N1693. V165(L118) Use:(#836) * Def:(#837) Pref: N1695. IL_OFFSET INLRT @ 0x3EB[E-] N1697. V165(L118) N1699. V35 MEM Use:(#838) N1701. IL_OFFSET INLRT @ 0x3F3[E-] N1703. V165(L118) N1705. V169(L121) Use:(#839) * Def:(#840) Pref: N1707. V169(L121) N1709. V34(L29) Use:(#841) * Def:(#842) N1711. IL_OFFSET INLRT @ 0x3F8[E-] N1713. V17(L16) N1715. V36(L30) Use:(#843) Def:(#844) Pref: BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB197,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB258} succs={BB246,BB248} ===== N1719. IL_OFFSET INLRT @ 0x7AA[E-] N1721. V16(L15) N1723. V179(L130) N1725. GE Use:(#846) Use:(#847) N1727. JTRUE BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ===== N1731. IL_OFFSET INLRT @ 0x7B5[E-] N1733. V16(L15) N1735. V49(L37) Use:(#849) * Def:(#850) N1737. IL_OFFSET INLRT @ 0x7B5[E-] N1739. V49(L37) N1741. CNS_INT 1 N1743. ADD Use:(#851) Def:(#852) Pref: N1745. V16(L15) Use:(#853) * Def:(#854) Pref: N1747. V34(L29) N1749. V49(L37) N1751. CAST N1753. CNS_INT 1 N1755. BFIZ N1757. LEA(b+(i*1)+0) N1759. IND Use:(#855) Use:(#856) * Def:(#857) Pref: N1761. V50(L38) Use:(#858) * Def:(#859) Pref: N1763. V50(L38) N1765. V18(L17) Use:(#860) * Def:(#861) N1767. V18(L17) N1769. CNS_INT 0 N1771. JCMP Use:(#862) BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ===== N1775. IL_OFFSET INLRT @ 0x7C8[E-] N1777. V18(L17) N1779. CNS_INT 59 N1781. NE Use:(#864) N1783. JTRUE BB113 [401..406) -> BB136 (cond), preds={BB247} succs={BB114,BB136} ===== N1787. IL_OFFSET INLRT @ 0x401[E-] N1789. V14(L13) N1791. CNS_INT 0 N1793. LE Use:(#866) N1795. JTRUE BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ===== N1799. IL_OFFSET INLRT @ 0x406[E-] N1801. V18(L17) N1803. CNS_INT 35 N1805. EQ N1807. V18(L17) N1809. CNS_INT 46 Def:(#868) N1811. EQ N1813. AND N1815. JTRUE Use:(#869) Use:(#870) Use:(#871) * BB115 [40C..418) -> BB135 (cond), preds={BB114} succs={BB117,BB135} ===== N1819. IL_OFFSET INLRT @ 0x40C[E-] N1821. IL_OFFSET INLRT @ 0x412[E-] N1823. V18(L17) N1825. CNS_INT 48 N1827. EQ Use:(#873) N1829. JTRUE BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} ===== BB135 [46D..472) -> BB118 (cond), preds={BB114,BB115,BB134} succs={BB136,BB118} ===== N1835. IL_OFFSET INLRT @ 0x46D[E-] N1837. V14(L13) N1839. CNS_INT 0 N1841. GT Use:(#876) N1843. JTRUE BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ===== N1847. IL_OFFSET INLRT @ 0x41A[E-] N1849. V36(L30) N1851. IND Use:(#878) Def:(#879) Pref: N1853. V177(L128) Use:(#880) * Def:(#881) Pref: N1855. V177(L128) N1857. CNS_INT 0 N1859. JCMP Use:(#882) BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ===== N1863. CNS_INT 48 Def:(#884) Pref: N1865. V63(L49) Use:(#885) * Def:(#886) BB120 [424..42C), preds={BB118} succs={BB121} ===== N1869. V36(L30) N1871. V61(L48) Use:(#888) * Def:(#889) N1873. V61(L48) N1875. CNS_INT 1 N1877. ADD Use:(#890) * Def:(#891) Pref: N1879. V36(L30) Use:(#892) * Def:(#893) Pref: N1881. V177(L128) N1883. V63(L49) Use:(#894) * Def:(#895) BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ===== N1887. V63(L49) N1889. CAST Use:(#897) * Def:(#898) Pref: N1891. V92(L66) Use:(#899) * Def:(#900) N1893. IL_OFFSET INL29 @ 0x000[E-] <- INLRT @ ??? N1895. V00(L0) N1897. LEA(b+8) N1899. IND Use:(#901) Def:(#902) Pref: N1901. V91(L65) Use:(#903) * Def:(#904) N1903. IL_OFFSET INL29 @ 0x007[E-] <- INLRT @ ??? N1905. V91(L65) N1907. V00(L0) N1909. LEA(b+24) N1911. IND Use:(#905) Def:(#906) N1913. GE Use:(#907) Use:(#908) * N1915. JTRUE BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ===== N1919. IL_OFFSET INL29 @ 0x015[E-] <- INLRT @ ??? N1921. V00(L0) N1923. CNS_INT 16 N1925. ADD Use:(#910) Def:(#911) Pref: N1927. V93(L67) Use:(#912) * Def:(#913) N1929. V91(L65) N1931. V93(L67) N1933. LEA(b+8) N1935. IND Use:(#914) Def:(#915) N1937. BOUNDS_CHECK_Rng -> BB254 Use:(#916) Use:(#917) * N1939. V93(L67) N1941. IND Use:(#918) * Def:(#919) N1943. V91(L65) N1945. CAST N1947. CNS_INT 1 N1949. BFIZ N1951. LEA(b+(i*1)+0) N1953. V92(L66) N1955. STOREIND Use:(#920) * Use:(#921) Use:(#922) * N1957. IL_OFFSET INL29 @ 0x023[E-] <- INLRT @ ??? N1959. V91(L65) N1961. CNS_INT 1 N1963. ADD Use:(#923) * Def:(#924) N1965. V00(L0) N1967. LEA(b+8) N1969. STOREIND Use:(#925) Use:(#926) * BB123 [000..000), preds={BB121} succs={BB124} ===== N1973. IL_OFFSET INL29 @ 0x02D[E-] <- INLRT @ ??? N1975. V00(L0) N1977. PUTARG_REG Use:(#929) Fixed:x0(#928) Def:(#931) x0 Pref: N1979. V92(L66) N1981. PUTARG_REG Use:(#933) Fixed:x1(#932) * Def:(#935) x1 N1983. CNS_INT(h) 0x4000000000435c58 ftn Def:(#936) N1985. PUTARG_REG Use:(#938) Fixed:x11(#937) * Def:(#940) x11 N1987. CALL r2r_ind Def:(#941) Use:(#943) Fixed:x0(#942) * Use:(#945) Fixed:x1(#944) * Use:(#947) Fixed:x11(#946) * Use:(#948) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ===== N1991. IL_OFFSET INLRT @ 0x431[E-] N1993. V12(L11) N1995. CNS_INT 0 N1997. EQ N1999. V08(L7) N2001. CNS_INT 1 N2003. LE N2005. AND N2007. JTRUE Use:(#969) Use:(#970) BB125 [435..43F) -> BB134 (cond), preds={BB124} succs={BB127,BB134} ===== N2011. IL_OFFSET INLRT @ 0x435[E-] N2013. IL_OFFSET INLRT @ 0x43A[E-] N2015. V20(L18) N2017. V144(L104) N2019. BOUNDS_CHECK_Rng -> BB254 Use:(#972) Use:(#973) N2021. V143(L103) N2023. V20(L18) N2025. CAST N2027. CNS_INT 2 N2029. BFIZ N2031. LEA(b+(i*1)+0) N2033. IND Use:(#974) Use:(#975) Def:(#976) N2035. CNS_INT 1 N2037. ADD Use:(#977) * Def:(#978) N2039. V08(L7) N2041. NE N2043. V20(L18) N2045. CNS_INT 0 N2047. LT N2049. AND N2051. JTRUE Use:(#979) * Use:(#980) Use:(#981) BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} ===== N2055. IL_OFFSET INLRT @ 0x43F[E-] N2057. IL_OFFSET INLRT @ 0x44F[E-] N2059. V03(L2) N2061. LEA(b+56) N2063. IND Use:(#983) Def:(#984) Pref: N2065. V95(L68) Use:(#985) * Def:(#986) N2067. IL_OFFSET INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] N2069. V95(L68) N2071. CNS_INT null N2073. JCMP Use:(#987) BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} ===== N2077. IL_OFFSET INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] N2079. V00(L0) N2081. LEA(b+8) N2083. IND Use:(#989) Def:(#990) Pref: N2085. V96(L69) Use:(#991) * Def:(#992) N2087. IL_OFFSET INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] N2089. V95(L68) N2091. LEA(b+8) N2093. IND Use:(#993) Def:(#994) Pref: N2095. V181(L132) Use:(#995) * Def:(#996) N2097. V181(L132) N2099. CNS_INT 1 N2101. NE N2103. V96(L69) N2105. V00(L0) N2107. LEA(b+24) N2109. IND Use:(#997) Def:(#998) N2111. GE N2113. AND N2115. JTRUE Use:(#999) Use:(#1000) Use:(#1001) * BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} ===== N2119. IL_OFFSET INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] N2121. IL_OFFSET INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] N2123. V00(L0) N2125. CNS_INT 16 N2127. ADD Use:(#1003) Def:(#1004) Pref: N2129. V97(L70) Use:(#1005) * Def:(#1006) N2131. IL_OFFSET INL32 @ ??? <- INLRT @ 0x44F[E-] N2133. V96(L69) N2135. V97(L70) N2137. LEA(b+8) N2139. IND Use:(#1007) Def:(#1008) N2141. BOUNDS_CHECK_Rng -> BB254 Use:(#1009) Use:(#1010) * N2143. V97(L70) N2145. IND Use:(#1011) * Def:(#1012) N2147. V96(L69) N2149. CAST N2151. CNS_INT 1 N2153. BFIZ Use:(#1013) Def:(#1014) N2155. ADD Use:(#1015) * Use:(#1016) * Def:(#1017) N2157. CNS_INT 0 N2159. V181(L132) N2161. BOUNDS_CHECK_Rng -> BB254 Use:(#1018) * N2163. V95(L68) N2165. LEA(b+12) N2167. IND Use:(#1019) * Def:(#1020) N2169. STOREIND Use:(#1021) * Use:(#1022) * N2171. IL_OFFSET INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] N2173. V96(L69) N2175. CNS_INT 1 N2177. ADD Use:(#1023) * Def:(#1024) N2179. V00(L0) N2181. LEA(b+8) N2183. STOREIND Use:(#1025) Use:(#1026) * BB132 [44F..450), preds={BB129} succs={BB133} ===== N2187. IL_OFFSET INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] N2189. V00(L0) N2191. PUTARG_REG Use:(#1029) Fixed:x0(#1028) Def:(#1031) x0 Pref: N2193. V95(L68) N2195. PUTARG_REG Use:(#1033) Fixed:x1(#1032) * Def:(#1035) x1 N2197. CNS_INT(h) 0x4000000000431d58 ftn Def:(#1036) N2199. PUTARG_REG Use:(#1038) Fixed:x11(#1037) * Def:(#1040) x11 N2201. CALL r2r_ind Def:(#1041) Use:(#1043) Fixed:x0(#1042) * Use:(#1045) Fixed:x1(#1044) * Use:(#1047) Fixed:x11(#1046) * Use:(#1048) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} ===== N2205. IL_OFFSET INLRT @ 0x45B[E-] N2207. V20(L18) N2209. CNS_INT -1 N2211. ADD Use:(#1069) * Def:(#1070) Pref: N2213. V20(L18) Use:(#1071) * Def:(#1072) BB134 [461..46D), preds={BB124,BB125,BB133} succs={BB135} ===== N2217. IL_OFFSET INLRT @ 0x461[E-] N2219. V08(L7) N2221. CNS_INT -1 N2223. ADD Use:(#1074) * Def:(#1075) Pref: N2225. V08(L7) Use:(#1076) * Def:(#1077) N2227. IL_OFFSET INLRT @ 0x467[E-] N2229. V14(L13) N2231. CNS_INT -1 N2233. ADD Use:(#1078) * Def:(#1079) Pref: N2235. V14(L13) Use:(#1080) * Def:(#1081) BB136 [472..478) -> BB141 (cond), preds={BB113,BB117,BB135} succs={BB137,BB141} ===== N2239. IL_OFFSET INLRT @ 0x472[E-] N2241. V18(L17) N2243. CNS_INT 69 N2245. GT Use:(#1083) N2247. JTRUE BB137 [478..478) -> BB138 (cond), preds={BB136} succs={BB257,BB138} ===== N2251. IL_OFFSET INLRT @ 0x478[E-] N2253. V18(L17) N2255. CNS_INT -34 N2257. ADD Use:(#1085) Def:(#1086) Pref: N2259. V184(L135) Use:(#1087) * Def:(#1088) N2261. V184(L135) N2263. CNS_INT 5 N2265. GT Use:(#1089) N2267. JTRUE BB138 [49A..49A) -> BB139 (cond), preds={BB137} succs={BB258,BB139} ===== N2271. IL_OFFSET INLRT @ 0x49A[E-] N2273. V18(L17) N2275. CNS_INT -44 N2277. ADD Use:(#1091) Def:(#1092) Pref: N2279. V185(L136) Use:(#1093) * Def:(#1094) N2281. V185(L136) N2283. CNS_INT 4 N2285. GT Use:(#1095) N2287. JTRUE BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ===== N2291. IL_OFFSET INLRT @ 0x4B8[E-] N2293. V18(L17) N2295. CNS_INT 69 N2297. EQ Use:(#1097) N2299. JTRUE BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ===== BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ===== N2305. IL_OFFSET INLRT @ 0x4C6[E-] N2307. V18(L17) N2309. CNS_INT 92 N2311. EQ Use:(#1100) N2313. JTRUE BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ===== N2317. IL_OFFSET INLRT @ 0x4CF[E-] N2319. V18(L17) N2321. CNS_INT 101 N2323. EQ Use:(#1102) N2325. JTRUE BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ===== N2329. IL_OFFSET INLRT @ 0x4D8[E-] N2331. V18(L17) N2333. CNS_INT 0x2030 Def:(#1104) N2335. NE Use:(#1105) Use:(#1106) * N2337. JTRUE BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ===== N2341. IL_OFFSET INLRT @ 0x598[E-] N2343. V03(L2) N2345. LEA(b+136) N2347. IND Use:(#1108) Def:(#1109) Pref: N2349. V110(L79) Use:(#1110) * Def:(#1111) BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ===== N2353. IL_OFFSET INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] N2355. V110(L79) N2357. CNS_INT null N2359. JCMP Use:(#1113) Dummy def of V110 at #1114 BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ===== N2363. IL_OFFSET INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] N2365. V00(L0) N2367. LEA(b+8) N2369. IND Use:(#1116) Def:(#1117) Pref: N2371. V111(L80) Use:(#1118) * Def:(#1119) N2373. IL_OFFSET INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] N2375. V110(L79) N2377. LEA(b+8) N2379. IND Use:(#1120) Def:(#1121) N2381. CNS_INT 1 N2383. NE N2385. V111(L80) N2387. V00(L0) N2389. LEA(b+24) N2391. IND Use:(#1122) Def:(#1123) N2393. GE N2395. AND N2397. JTRUE Use:(#1124) * Use:(#1125) Use:(#1126) * BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ===== N2401. IL_OFFSET INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] N2403. IL_OFFSET INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] N2405. V00(L0) N2407. CNS_INT 16 N2409. ADD Use:(#1128) Def:(#1129) Pref: N2411. V112(L81) Use:(#1130) * Def:(#1131) N2413. IL_OFFSET INL43 @ ??? <- INLRT @ 0x598[E-] N2415. V111(L80) N2417. V112(L81) N2419. LEA(b+8) N2421. IND Use:(#1132) Def:(#1133) N2423. BOUNDS_CHECK_Rng -> BB254 Use:(#1134) Use:(#1135) * N2425. V112(L81) N2427. IND Use:(#1136) * Def:(#1137) N2429. V111(L80) N2431. CAST N2433. CNS_INT 1 N2435. BFIZ Use:(#1138) Def:(#1139) N2437. ADD Use:(#1140) * Use:(#1141) * Def:(#1142) N2439. CNS_INT 0 N2441. V110(L79) N2443. LEA(b+8) N2445. IND Use:(#1143) Def:(#1144) N2447. BOUNDS_CHECK_Rng -> BB254 Use:(#1145) * N2449. V110(L79) N2451. LEA(b+12) N2453. IND Use:(#1146) * Def:(#1147) N2455. STOREIND Use:(#1148) * Use:(#1149) * N2457. IL_OFFSET INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] N2459. V111(L80) N2461. CNS_INT 1 N2463. ADD Use:(#1150) * Def:(#1151) N2465. V00(L0) N2467. LEA(b+8) N2469. STOREIND Use:(#1152) Use:(#1153) * BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ===== N2473. IL_OFFSET INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] N2475. V00(L0) N2477. PUTARG_REG Use:(#1156) Fixed:x0(#1155) Def:(#1158) x0 Pref: N2479. V110(L79) N2481. PUTARG_REG Use:(#1160) Fixed:x1(#1159) * Def:(#1162) x1 N2483. CNS_INT(h) 0x4000000000431d58 ftn Def:(#1163) N2485. PUTARG_REG Use:(#1165) Fixed:x11(#1164) * Def:(#1167) x11 N2487. CALL r2r_ind Def:(#1168) Use:(#1170) Fixed:x0(#1169) * Use:(#1172) Fixed:x1(#1171) * Use:(#1174) Fixed:x11(#1173) * Use:(#1175) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ===== N2491. IL_OFFSET INLRT @ 0x618[E-] N2493. V16(L15) N2495. V179(L130) N2497. GE N2499. V34(L29) N2501. V16(L15) N2503. CAST N2505. CNS_INT 1 N2507. BFIZ N2509. LEA(b+(i*1)+0) N2511. IND Use:(#1196) Use:(#1197) Def:(#1198) Pref: N2513. V176(L127) Use:(#1199) * Def:(#1200) Pref: N2515. V176(L127) N2517. CNS_INT 0 N2519. EQ N2521. AND N2523. JTRUE Use:(#1201) Use:(#1202) Use:(#1203) Dummy def of V176 at #1204 BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} ===== N2527. IL_OFFSET INLRT @ 0x626[E-] N2529. IL_OFFSET INLRT @ 0x634[E-] N2531. V16(L15) N2533. V51(L39) Use:(#1206) * Def:(#1207) N2535. IL_OFFSET INLRT @ 0x634[E-] N2537. V51(L39) N2539. CNS_INT 1 N2541. ADD Use:(#1208) * Def:(#1209) Pref: N2543. V16(L15) Use:(#1210) * Def:(#1211) Pref: N2545. V176(L127) N2547. V123(L89) Use:(#1212) * Def:(#1213) N2549. IL_OFFSET INL53 @ 0x000[E-] <- INLRT @ ??? N2551. V00(L0) N2553. LEA(b+8) N2555. IND Use:(#1214) Def:(#1215) Pref: N2557. V122(L88) Use:(#1216) * Def:(#1217) N2559. IL_OFFSET INL53 @ 0x007[E-] <- INLRT @ ??? N2561. V122(L88) N2563. V00(L0) N2565. LEA(b+24) N2567. IND Use:(#1218) Def:(#1219) N2569. GE Use:(#1220) Use:(#1221) * N2571. JTRUE BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} ===== N2575. IL_OFFSET INL53 @ 0x015[E-] <- INLRT @ ??? N2577. V00(L0) N2579. CNS_INT 16 N2581. ADD Use:(#1223) Def:(#1224) Pref: N2583. V124(L90) Use:(#1225) * Def:(#1226) N2585. V122(L88) N2587. V124(L90) N2589. LEA(b+8) N2591. IND Use:(#1227) Def:(#1228) N2593. BOUNDS_CHECK_Rng -> BB254 Use:(#1229) Use:(#1230) * N2595. V124(L90) N2597. IND Use:(#1231) * Def:(#1232) N2599. V122(L88) N2601. CAST N2603. CNS_INT 1 N2605. BFIZ N2607. LEA(b+(i*1)+0) N2609. V123(L89) N2611. STOREIND Use:(#1233) * Use:(#1234) Use:(#1235) * N2613. IL_OFFSET INL53 @ 0x023[E-] <- INLRT @ ??? N2615. V122(L88) N2617. CNS_INT 1 N2619. ADD Use:(#1236) * Def:(#1237) N2621. V00(L0) N2623. LEA(b+8) N2625. STOREIND Use:(#1238) Use:(#1239) * BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} ===== N2629. IL_OFFSET INL53 @ 0x02D[E-] <- INLRT @ ??? N2631. V00(L0) N2633. PUTARG_REG Use:(#1242) Fixed:x0(#1241) Def:(#1244) x0 Pref: N2635. V123(L89) N2637. PUTARG_REG Use:(#1246) Fixed:x1(#1245) * Def:(#1248) x1 N2639. CNS_INT(h) 0x4000000000435c58 ftn Def:(#1249) N2641. PUTARG_REG Use:(#1251) Fixed:x11(#1250) * Def:(#1253) x11 N2643. CALL r2r_ind Def:(#1254) Use:(#1256) Fixed:x0(#1255) * Use:(#1258) Fixed:x1(#1257) * Use:(#1260) Fixed:x11(#1259) * Use:(#1261) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ===== N2647. IL_OFFSET INLRT @ 0x64D[E-] N2649. CNS_INT 0 N2651. V37(L31) Def:(#1282) N2653. IL_OFFSET INLRT @ 0x650[E-] N2655. CNS_INT 0 N2657. V38(L32) Def:(#1283) N2659. IL_OFFSET INLRT @ 0x653[E-] N2661. V09(L8) N2663. CNS_INT 0 N2665. JCMP Use:(#1284) BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ===== N2669. IL_OFFSET INLRT @ 0x65A[E-] N2671. V16(L15) N2673. V179(L130) N2675. GE Use:(#1286) Use:(#1287) N2677. JTRUE BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ===== N2681. IL_OFFSET INLRT @ 0x665[E-] N2683. V34(L29) N2685. V16(L15) N2687. CAST N2689. CNS_INT 1 N2691. BFIZ N2693. LEA(b+(i*1)+0) N2695. IND Use:(#1289) Use:(#1290) Def:(#1291) Pref: N2697. V176(L127) Use:(#1292) * Def:(#1293) Pref: N2699. V176(L127) N2701. CNS_INT 48 N2703. EQ Use:(#1294) * N2705. JTRUE BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} ===== N2709. IL_OFFSET INLRT @ 0x67A[E-] N2711. V16(L15) N2713. CNS_INT 1 N2715. ADD Use:(#1296) Def:(#1297) N2717. V179(L130) N2719. GE Use:(#1298) * Use:(#1299) N2721. JTRUE BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ===== N2725. IL_OFFSET INLRT @ 0x687[E-] N2727. V34(L29) N2729. V16(L15) N2731. CAST N2733. CNS_INT 1 N2735. BFIZ N2737. LEA(b+(i*1)+0) N2739. IND Use:(#1301) Use:(#1302) Def:(#1303) Pref: N2741. V176(L127) Use:(#1304) * Def:(#1305) Pref: N2743. V176(L127) N2745. CNS_INT 43 N2747. NE Use:(#1306) Def:(#1307) N2749. V34(L29) N2751. V16(L15) N2753. CNS_INT 1 N2755. ADD Use:(#1308) Def:(#1309) N2757. CAST N2759. CNS_INT 1 N2761. BFIZ N2763. LEA(b+(i*1)+0) N2765. IND Use:(#1310) Use:(#1311) * Def:(#1312) N2767. CNS_INT 48 N2769. NE Use:(#1313) * Def:(#1314) N2771. AND Use:(#1315) * Use:(#1316) * Def:(#1317) N2773. JTRUE Use:(#1318) * BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} ===== N2777. IL_OFFSET INLRT @ 0x694[E-] N2779. IL_OFFSET INLRT @ 0x6A3[E-] N2781. CNS_INT 1 Def:(#1320) Pref: N2783. V37(L31) Use:(#1321) * Def:(#1322) BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} ===== N2787. IL_OFFSET INLRT @ 0x6B5[E-] N2789. V176(L127) N2791. CNS_INT 45 N2793. NE Use:(#1324) * N2795. JTRUE BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ===== N2799. IL_OFFSET INLRT @ 0x6C2[E-] N2801. V34(L29) N2803. V16(L15) N2805. CNS_INT 1 N2807. ADD Use:(#1326) Def:(#1327) N2809. CAST N2811. CNS_INT 1 N2813. BFIZ N2815. LEA(b+(i*1)+0) N2817. IND Use:(#1328) Use:(#1329) * Def:(#1330) N2819. CNS_INT 48 N2821. EQ Use:(#1331) * N2823. JTRUE BB215 [6D1..6DE) -> BB244 (cond), preds={BB208,BB213,BB214} succs={BB216,BB244} ===== N2827. IL_OFFSET INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] N2829. V00(L0) N2831. LEA(b+8) N2833. IND Use:(#1333) Def:(#1334) Pref: N2835. V126(L91) Use:(#1335) * Def:(#1336) N2837. IL_OFFSET INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] N2839. V126(L91) N2841. V00(L0) N2843. LEA(b+24) N2845. IND Use:(#1337) Def:(#1338) N2847. GE Use:(#1339) Use:(#1340) * N2849. JTRUE BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ===== N2853. IL_OFFSET INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] N2855. V00(L0) N2857. CNS_INT 16 N2859. ADD Use:(#1342) Def:(#1343) Pref: N2861. V127(L92) Use:(#1344) * Def:(#1345) N2863. IL_OFFSET INL58 @ ??? <- INLRT @ 0x6D1[E-] N2865. V126(L91) N2867. V127(L92) N2869. LEA(b+8) N2871. IND Use:(#1346) Def:(#1347) N2873. BOUNDS_CHECK_Rng -> BB254 Use:(#1348) Use:(#1349) * N2875. V127(L92) N2877. IND Use:(#1350) * Def:(#1351) N2879. V126(L91) N2881. CAST N2883. CNS_INT 1 N2885. BFIZ N2887. LEA(b+(i*1)+0) N2889. V18(L17) N2891. STOREIND Use:(#1352) * Use:(#1353) Use:(#1354) * N2893. IL_OFFSET INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] N2895. V126(L91) N2897. CNS_INT 1 N2899. ADD Use:(#1355) * Def:(#1356) N2901. V00(L0) N2903. LEA(b+8) N2905. STOREIND Use:(#1357) Use:(#1358) * Exposed use of V09 at #1359 BB218 [6DE..6E4), preds={BB207,BB220} succs={BB219} ===== N2909. IL_OFFSET INLRT @ 0x6DE[E-] N2911. V38(L32) N2913. CNS_INT 1 N2915. ADD Use:(#1361) * Def:(#1362) Pref: N2917. V38(L32) Use:(#1363) * Def:(#1364) BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} ===== N2921. IL_OFFSET INLRT @ 0x6E4[E-] N2923. V16(L15) N2925. CNS_INT 1 N2927. ADD Use:(#1366) * Def:(#1367) Pref: N2929. V54(L42) Use:(#1368) * Def:(#1369) Pref: N2931. V54(L42) N2933. V16(L15) Use:(#1370) * Def:(#1371) Pref: N2935. V16(L15) N2937. V179(L130) N2939. GE Use:(#1372) Use:(#1373) N2941. JTRUE BB220 [6F4..701) -> BB218 (cond), preds={BB219} succs={BB221,BB218} ===== N2945. IL_OFFSET INLRT @ 0x6F4[E-] N2947. V34(L29) N2949. V16(L15) N2951. CAST N2953. CNS_INT 1 N2955. BFIZ N2957. LEA(b+(i*1)+0) N2959. IND Use:(#1375) Use:(#1376) Def:(#1377) N2961. CNS_INT 48 N2963. EQ Use:(#1378) * N2965. JTRUE BB221 [701..707) -> BB223 (cond), preds={BB219,BB220} succs={BB222,BB223} ===== N2969. IL_OFFSET INLRT @ 0x701[E-] N2971. V38(L32) N2973. CNS_INT 10 N2975. LE Use:(#1380) N2977. JTRUE BB222 [707..70B), preds={BB221} succs={BB223} ===== N2981. IL_OFFSET INLRT @ 0x707[E-] N2983. CNS_INT 10 Def:(#1382) Pref: N2985. V38(L32) Use:(#1383) * Def:(#1384) BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ===== N2989. IL_OFFSET INLRT @ 0x70B[E-] N2991. V17(L16) N2993. IND Use:(#1386) Def:(#1387) N2995. CNS_INT 0 N2997. JCMP Use:(#1388) * BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ===== N3001. IL_OFFSET INLRT @ 0x710[E-] N3003. V01(L1) N3005. LEA(b+4) N3007. IND Use:(#1390) Def:(#1391) N3009. V05(L4) N3011. SUB Use:(#1392) * Use:(#1393) Def:(#1394) Pref: N3013. V55(L43) Use:(#1395) * Def:(#1396) BB225 [71A..71B), preds={BB223} succs={BB226} ===== N3017. IL_OFFSET INLRT @ 0x71A[E-] N3019. CNS_INT 0 N3021. V55(L43) Def:(#1398) BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ===== N3025. IL_OFFSET INLRT @ 0x71D[E-] N3027. V37(L31) N3029. PUTARG_REG Use:(#1401) Fixed:x5(#1400) * Def:(#1403) x5 N3031. V00(L0) N3033. PUTARG_REG Use:(#1405) Fixed:x0(#1404) Def:(#1407) x0 Pref: N3035. V03(L2) N3037. PUTARG_REG Use:(#1409) Fixed:x1(#1408) Def:(#1411) x1 Pref: N3039. V55(L43) N3041. PUTARG_REG Use:(#1413) Fixed:x2(#1412) * Def:(#1415) x2 N3043. V18(L17) N3045. PUTARG_REG Use:(#1417) Fixed:x3(#1416) * Def:(#1419) x3 N3047. V38(L32) N3049. PUTARG_REG Use:(#1421) Fixed:x4(#1420) * Def:(#1423) x4 N3051. CNS_INT(h) 0x4000000000540240 ftn Def:(#1424) N3053. PUTARG_REG Use:(#1426) Fixed:x11(#1425) * Def:(#1428) x11 N3055. CALL r2r_ind Def:(#1429) Use:(#1431) Fixed:x5(#1430) * Use:(#1433) Fixed:x0(#1432) * Use:(#1435) Fixed:x1(#1434) * Use:(#1437) Fixed:x2(#1436) * Use:(#1439) Fixed:x3(#1438) * Use:(#1441) Fixed:x4(#1440) * Use:(#1443) Fixed:x11(#1442) * Use:(#1444) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr N3057. IL_OFFSET INLRT @ 0x72C[E-] N3059. CNS_INT 0 N3061. V09(L8) Def:(#1464) BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ===== N3065. IL_OFFSET INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] N3067. V00(L0) N3069. LEA(b+8) N3071. IND Use:(#1466) Def:(#1467) Pref: N3073. V129(L93) Use:(#1468) * Def:(#1469) N3075. IL_OFFSET INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] N3077. V129(L93) N3079. V00(L0) N3081. LEA(b+24) N3083. IND Use:(#1470) Def:(#1471) N3085. GE Use:(#1472) Use:(#1473) * N3087. JTRUE BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ===== N3091. IL_OFFSET INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] N3093. V00(L0) N3095. CNS_INT 16 N3097. ADD Use:(#1475) Def:(#1476) Pref: N3099. V130(L94) Use:(#1477) * Def:(#1478) N3101. IL_OFFSET INL61 @ ??? <- INLRT @ 0x731[E-] N3103. V129(L93) N3105. V130(L94) N3107. LEA(b+8) N3109. IND Use:(#1479) Def:(#1480) N3111. BOUNDS_CHECK_Rng -> BB254 Use:(#1481) Use:(#1482) * N3113. V130(L94) N3115. IND Use:(#1483) * Def:(#1484) N3117. V129(L93) N3119. CAST N3121. CNS_INT 1 N3123. BFIZ N3125. LEA(b+(i*1)+0) N3127. V18(L17) N3129. STOREIND Use:(#1485) * Use:(#1486) Use:(#1487) * N3131. IL_OFFSET INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] N3133. V129(L93) N3135. CNS_INT 1 N3137. ADD Use:(#1488) * Def:(#1489) N3139. V00(L0) N3141. LEA(b+8) N3143. STOREIND Use:(#1490) Use:(#1491) * BB229 [731..732), preds={BB227} succs={BB230} ===== N3147. IL_OFFSET INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] N3149. V00(L0) N3151. PUTARG_REG Use:(#1494) Fixed:x0(#1493) Def:(#1496) x0 Pref: N3153. V18(L17) N3155. PUTARG_REG Use:(#1498) Fixed:x1(#1497) * Def:(#1500) x1 N3157. CNS_INT(h) 0x4000000000435c58 ftn Def:(#1501) N3159. PUTARG_REG Use:(#1503) Fixed:x11(#1502) * Def:(#1505) x11 N3161. CALL r2r_ind Def:(#1506) Use:(#1508) Fixed:x0(#1507) * Use:(#1510) Fixed:x1(#1509) * Use:(#1512) Fixed:x11(#1511) * Use:(#1513) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ===== N3165. IL_OFFSET INLRT @ 0x739[E-] N3167. V16(L15) N3169. V179(L130) N3171. GE Use:(#1534) Use:(#1535) N3173. JTRUE BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ===== N3177. IL_OFFSET INLRT @ 0x744[E-] N3179. V34(L29) N3181. V16(L15) N3183. CAST N3185. CNS_INT 1 N3187. BFIZ N3189. LEA(b+(i*1)+0) N3191. IND Use:(#1537) Use:(#1538) Def:(#1539) Pref: N3193. V175(L126) Use:(#1540) * Def:(#1541) Pref: N3195. V175(L126) N3197. CNS_INT 43 N3199. EQ Use:(#1542) N3201. JTRUE BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ===== N3205. IL_OFFSET INLRT @ 0x751[E-] N3207. V175(L126) N3209. CNS_INT 45 N3211. NE Use:(#1544) N3213. JTRUE BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ===== N3217. IL_OFFSET INLRT @ 0x75E[E-] N3219. V16(L15) N3221. V52(L40) Use:(#1546) * Def:(#1547) N3223. IL_OFFSET INLRT @ 0x75E[E-] N3225. V52(L40) N3227. CNS_INT 1 N3229. ADD Use:(#1548) * Def:(#1549) Pref: N3231. V16(L15) Use:(#1550) * Def:(#1551) Pref: N3233. V175(L126) N3235. V133(L96) Use:(#1552) * Def:(#1553) N3237. IL_OFFSET INL64 @ 0x000[E-] <- INLRT @ ??? N3239. V00(L0) N3241. LEA(b+8) N3243. IND Use:(#1554) Def:(#1555) Pref: N3245. V132(L95) Use:(#1556) * Def:(#1557) N3247. IL_OFFSET INL64 @ 0x007[E-] <- INLRT @ ??? N3249. V132(L95) N3251. V00(L0) N3253. LEA(b+24) N3255. IND Use:(#1558) Def:(#1559) N3257. GE Use:(#1560) Use:(#1561) * N3259. JTRUE BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ===== N3263. IL_OFFSET INL64 @ 0x015[E-] <- INLRT @ ??? N3265. V00(L0) N3267. CNS_INT 16 N3269. ADD Use:(#1563) Def:(#1564) Pref: N3271. V134(L97) Use:(#1565) * Def:(#1566) N3273. V132(L95) N3275. V134(L97) N3277. LEA(b+8) N3279. IND Use:(#1567) Def:(#1568) N3281. BOUNDS_CHECK_Rng -> BB254 Use:(#1569) Use:(#1570) * N3283. V134(L97) N3285. IND Use:(#1571) * Def:(#1572) N3287. V132(L95) N3289. CAST N3291. CNS_INT 1 N3293. BFIZ N3295. LEA(b+(i*1)+0) N3297. V133(L96) N3299. STOREIND Use:(#1573) * Use:(#1574) Use:(#1575) * N3301. IL_OFFSET INL64 @ 0x023[E-] <- INLRT @ ??? N3303. V132(L95) N3305. CNS_INT 1 N3307. ADD Use:(#1576) * Def:(#1577) N3309. V00(L0) N3311. LEA(b+8) N3313. STOREIND Use:(#1578) Use:(#1579) * BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ===== N3317. IL_OFFSET INL64 @ 0x02D[E-] <- INLRT @ ??? N3319. V00(L0) N3321. PUTARG_REG Use:(#1582) Fixed:x0(#1581) Def:(#1584) x0 Pref: N3323. V133(L96) N3325. PUTARG_REG Use:(#1586) Fixed:x1(#1585) * Def:(#1588) x1 N3327. CNS_INT(h) 0x4000000000435c58 ftn Def:(#1589) N3329. PUTARG_REG Use:(#1591) Fixed:x11(#1590) * Def:(#1593) x11 N3331. CALL r2r_ind Def:(#1594) Use:(#1596) Fixed:x0(#1595) * Use:(#1598) Fixed:x1(#1597) * Use:(#1600) Fixed:x11(#1599) * Use:(#1601) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ===== N3335. IL_OFFSET INLRT @ 0x788[E-] N3337. V16(L15) N3339. V179(L130) N3341. GE Use:(#1622) Use:(#1623) N3343. JTRUE BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ===== N3347. IL_OFFSET INLRT @ 0x793[E-] N3349. V34(L29) N3351. V16(L15) N3353. CAST N3355. CNS_INT 1 N3357. BFIZ N3359. LEA(b+(i*1)+0) N3361. IND Use:(#1625) Use:(#1626) Def:(#1627) Pref: N3363. V173(L124) Use:(#1628) * Def:(#1629) Pref: N3365. V173(L124) N3367. CNS_INT 48 N3369. EQ Use:(#1630) N3371. JTRUE BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ===== N3375. IL_OFFSET INLRT @ 0x774[E-] N3377. V16(L15) N3379. V53(L41) Use:(#1632) * Def:(#1633) N3381. IL_OFFSET INLRT @ 0x774[E-] N3383. V53(L41) N3385. CNS_INT 1 N3387. ADD Use:(#1634) * Def:(#1635) Pref: N3389. V16(L15) Use:(#1636) * Def:(#1637) Pref: N3391. V173(L124) N3393. V137(L99) Use:(#1638) * Def:(#1639) N3395. IL_OFFSET INL66 @ 0x000[E-] <- INLRT @ ??? N3397. V00(L0) N3399. LEA(b+8) N3401. IND Use:(#1640) Def:(#1641) Pref: N3403. V136(L98) Use:(#1642) * Def:(#1643) N3405. IL_OFFSET INL66 @ 0x007[E-] <- INLRT @ ??? N3407. V136(L98) N3409. V00(L0) N3411. LEA(b+24) N3413. IND Use:(#1644) Def:(#1645) N3415. GE Use:(#1646) Use:(#1647) * N3417. JTRUE BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ===== N3421. IL_OFFSET INL66 @ 0x015[E-] <- INLRT @ ??? N3423. V00(L0) N3425. CNS_INT 16 N3427. ADD Use:(#1649) Def:(#1650) Pref: N3429. V138(L100) Use:(#1651) * Def:(#1652) N3431. V136(L98) N3433. V138(L100) N3435. LEA(b+8) N3437. IND Use:(#1653) Def:(#1654) N3439. BOUNDS_CHECK_Rng -> BB254 Use:(#1655) Use:(#1656) * N3441. V138(L100) N3443. IND Use:(#1657) * Def:(#1658) N3445. V136(L98) N3447. CAST N3449. CNS_INT 1 N3451. BFIZ N3453. LEA(b+(i*1)+0) N3455. V137(L99) N3457. STOREIND Use:(#1659) * Use:(#1660) Use:(#1661) * N3459. IL_OFFSET INL66 @ 0x023[E-] <- INLRT @ ??? N3461. V136(L98) N3463. CNS_INT 1 N3465. ADD Use:(#1662) * Def:(#1663) N3467. V00(L0) N3469. LEA(b+8) N3471. STOREIND Use:(#1664) Use:(#1665) * BB238 [000..000), preds={BB236} succs={BB239} ===== N3475. IL_OFFSET INL66 @ 0x02D[E-] <- INLRT @ ??? N3477. V00(L0) N3479. PUTARG_REG Use:(#1668) Fixed:x0(#1667) Def:(#1670) x0 Pref: N3481. V137(L99) N3483. PUTARG_REG Use:(#1672) Fixed:x1(#1671) * Def:(#1674) x1 N3485. CNS_INT(h) 0x4000000000435c58 ftn Def:(#1675) N3487. PUTARG_REG Use:(#1677) Fixed:x11(#1676) * Def:(#1679) x11 N3489. CALL r2r_ind Def:(#1680) Use:(#1682) Fixed:x0(#1681) * Use:(#1684) Fixed:x1(#1683) * Use:(#1686) Fixed:x11(#1685) * Use:(#1687) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ===== BB242 [7A2..7AA) -> BB244 (cond), preds={BB140,BB143,BB257(2),BB258(2)} succs={BB243,BB244} ===== N3495. IL_OFFSET INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] N3497. V00(L0) N3499. LEA(b+8) N3501. IND Use:(#1709) Def:(#1710) Pref: N3503. V140(L101) Use:(#1711) * Def:(#1712) N3505. IL_OFFSET INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] N3507. V140(L101) N3509. V00(L0) N3511. LEA(b+24) N3513. IND Use:(#1713) Def:(#1714) N3515. GE Use:(#1715) Use:(#1716) * N3517. JTRUE BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ===== N3521. IL_OFFSET INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] N3523. V00(L0) N3525. CNS_INT 16 N3527. ADD Use:(#1718) Def:(#1719) Pref: N3529. V141(L102) Use:(#1720) * Def:(#1721) N3531. IL_OFFSET INL69 @ ??? <- INLRT @ 0x7A2[E-] N3533. V140(L101) N3535. V141(L102) N3537. LEA(b+8) N3539. IND Use:(#1722) Def:(#1723) N3541. BOUNDS_CHECK_Rng -> BB254 Use:(#1724) Use:(#1725) * N3543. V141(L102) N3545. IND Use:(#1726) * Def:(#1727) N3547. V140(L101) N3549. CAST N3551. CNS_INT 1 N3553. BFIZ N3555. LEA(b+(i*1)+0) N3557. V18(L17) N3559. STOREIND Use:(#1728) * Use:(#1729) Use:(#1730) * N3561. IL_OFFSET INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] N3563. V140(L101) N3565. CNS_INT 1 N3567. ADD Use:(#1731) * Def:(#1732) N3569. V00(L0) N3571. LEA(b+8) N3573. STOREIND Use:(#1733) Use:(#1734) * BB244 [7A2..7A3) -> BB245 (always), preds={BB215,BB242} succs={BB245} ===== N3577. IL_OFFSET INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] N3579. V00(L0) N3581. PUTARG_REG Use:(#1737) Fixed:x0(#1736) Def:(#1739) x0 Pref: N3583. V18(L17) N3585. PUTARG_REG Use:(#1741) Fixed:x1(#1740) * Def:(#1743) x1 N3587. CNS_INT(h) 0x4000000000435c58 ftn Def:(#1744) N3589. PUTARG_REG Use:(#1746) Fixed:x11(#1745) * Def:(#1748) x11 N3591. CALL r2r_ind Def:(#1749) Use:(#1751) Fixed:x0(#1750) * Use:(#1753) Fixed:x1(#1752) * Use:(#1755) Fixed:x11(#1754) * Use:(#1756) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr Exposed use of V16 at #1776 Exposed use of V179 at #1777 Exposed use of V04 at #1778 Exposed use of V20 at #1779 Exposed use of V34 at #1780 Exposed use of V05 at #1781 Exposed use of V08 at #1782 Exposed use of V14 at #1783 Exposed use of V36 at #1784 Exposed use of V06 at #1785 Exposed use of V12 at #1786 Exposed use of V144 at #1787 Exposed use of V09 at #1788 Exposed use of V07 at #1789 Exposed use of V143 at #1790 Exposed use of V17 at #1791 Exposed use of V21 at #1792 BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ===== N3595. IL_OFFSET INLRT @ 0x7D1[E-] N3597. CNS_INT 0 N3599. V35 MEM N3601. IL_OFFSET INLRT @ 0x7D5[E-] N3603. V01(L1) N3605. LEA(b+8) N3607. IND Use:(#1794) Def:(#1795) N3609. CNS_INT 0 N3611. EQ N3613. V15(L14) N3615. CNS_INT 0 N3617. NE N3619. AND N3621. JTRUE Use:(#1796) * Use:(#1797) * BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} ===== N3625. IL_OFFSET INLRT @ 0x7DD[E-] N3627. IL_OFFSET INLRT @ 0x7E1[E-] N3629. V01(L1) N3631. LEA(b+4) N3633. IND Use:(#1799) * Def:(#1800) N3635. CNS_INT 0 N3637. NE Use:(#1801) * Def:(#1802) N3639. V00(L0) N3641. LEA(b+8) N3643. IND Use:(#1803) Def:(#1804) N3645. CNS_INT 0 N3647. LE Use:(#1805) * Def:(#1806) N3649. AND Use:(#1807) * Use:(#1808) * Def:(#1809) N3651. JTRUE Use:(#1810) * BB251 [7E9..7FF), preds={BB249} succs={BB253} ===== N3655. IL_OFFSET INLRT @ 0x7E9[E-] N3657. IL_OFFSET INLRT @ 0x7F2[E-] N3659. V03(L2) N3661. LEA(b+40) N3663. IND Use:(#1812) * Def:(#1813) N3665. PUTARG_REG Use:(#1815) Fixed:x2(#1814) * Def:(#1817) x2 N3667. V00(L0) N3669. PUTARG_REG Use:(#1819) Fixed:x0(#1818) * Def:(#1821) x0 N3671. CNS_INT(h) 0x4000000000540210 ftn Def:(#1822) N3673. PUTARG_REG Use:(#1824) Fixed:x11(#1823) * Def:(#1826) x11 N3675. CNS_INT 0 Def:(#1827) N3677. PUTARG_REG Use:(#1829) Fixed:x1(#1828) * Def:(#1831) x1 N3679. CALL r2r_ind Def:(#1832) Use:(#1834) Fixed:x2(#1833) * Use:(#1836) Fixed:x0(#1835) * Use:(#1838) Fixed:x11(#1837) * Use:(#1840) Fixed:x1(#1839) * Use:(#1841) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} ===== N3683. IL_OFFSET INLRT @ 0x7FF[E-] N3685. RETURN BB255 [061..083) -> BB31,BB17,BB47,BB30,BB47,BB31 (switch), preds={BB09} succs={BB17,BB30,BB31,BB47} ===== N3689. V182(L133) N3691. CAST Use:(#1863) * Def:(#1864) N3693. JMPTABLE Def:(#1865) N3695. SWITCH_TABLE Def:(#1866) Use:(#1867) * Use:(#1868) * BB17 [0CF..0D8) -> BB47 (always), preds={BB255} succs={BB47} ===== N3699. IL_OFFSET INLRT @ 0x0CF[E-] N3701. V04(L3) N3703. CNS_INT 1 N3705. ADD Use:(#1870) * Def:(#1871) Pref: N3707. V04(L3) Use:(#1872) * Def:(#1873) BB30 [12C..137) -> BB47 (always), preds={BB255} succs={BB47} ===== N3711. IL_OFFSET INLRT @ 0x12C[E-] N3713. V13(L12) N3715. CNS_INT 2 N3717. ADD Use:(#1875) * Def:(#1876) Pref: N3719. V13(L12) Use:(#1877) * Def:(#1878) BB31 [142..150) -> BB47 (cond), preds={BB32,BB255(2)} succs={BB32,BB47} ===== N3723. IL_OFFSET INLRT @ 0x142[E-] N3725. V16(L15) N3727. V179(L130) N3729. GE N3731. V22(L20) N3733. V16(L15) N3735. CAST N3737. CNS_INT 1 N3739. BFIZ N3741. LEA(b+(i*1)+0) N3743. IND Use:(#1880) Use:(#1881) Def:(#1882) Pref: N3745. V171(L122) Use:(#1883) * Def:(#1884) N3747. V171(L122) N3749. CNS_INT 0 N3751. EQ N3753. AND N3755. JTRUE Use:(#1885) Use:(#1886) Use:(#1887) Dummy def of V18 at #1888 Dummy def of V171 at #1889 BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} ===== N3759. IL_OFFSET INLRT @ 0x150[E-] N3761. IL_OFFSET INLRT @ 0x15E[E-] N3763. V16(L15) N3765. V74(L59) Use:(#1891) * Def:(#1892) N3767. IL_OFFSET INLRT @ 0x15E[E-] N3769. V74(L59) N3771. CNS_INT 1 N3773. ADD Use:(#1893) * Def:(#1894) Pref: N3775. V16(L15) Use:(#1895) * Def:(#1896) Pref: N3777. V171(L122) N3779. V18(L17) N3781. NE Use:(#1897) * Use:(#1898) N3783. JTRUE Exposed use of V18 at #1899 BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} ===== BB256 [083..0A1) -> BB23,BB47,BB21,BB47,BB18 (switch), preds={BB10} succs={BB18,BB21,BB23,BB47} ===== N3789. V183(L134) N3791. CAST Use:(#1902) * Def:(#1903) N3793. JMPTABLE Def:(#1904) N3795. SWITCH_TABLE Def:(#1905) Use:(#1906) * Use:(#1907) * BB18 [0D8..0E0) -> BB20 (cond), preds={BB256} succs={BB19,BB20} ===== N3799. IL_OFFSET INLRT @ 0x0D8[E-] N3801. V06(L5) N3803. CNS_INT 0x7FFFFFFF Def:(#1909) N3805. NE Use:(#1910) Use:(#1911) * N3807. JTRUE BB19 [0E0..0E2), preds={BB18} succs={BB20} ===== N3811. IL_OFFSET INLRT @ 0x0E0[E-] N3813. V04(L3) N3815. V06(L5) Use:(#1913) Def:(#1914) BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ===== N3819. IL_OFFSET INLRT @ 0x0E2[E-] N3821. V04(L3) N3823. CNS_INT 1 N3825. ADD Use:(#1916) * Def:(#1917) Pref: N3827. V04(L3) Use:(#1918) * Def:(#1919) N3829. IL_OFFSET INLRT @ 0x0E6[E-] N3831. V04(L3) N3833. V07(L6) Use:(#1920) Def:(#1921) BB21 [0ED..0F4) -> BB47 (cond), preds={BB256} succs={BB22,BB47} ===== N3837. IL_OFFSET INLRT @ 0x0ED[E-] N3839. V05(L4) N3841. CNS_INT 0 N3843. GE Use:(#1923) N3845. JTRUE Exposed use of V05 at #1924 BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ===== N3849. IL_OFFSET INLRT @ 0x0F4[E-] N3851. V04(L3) N3853. V05(L4) Use:(#1926) Def:(#1927) BB23 [0FB..102) -> BB47 (cond), preds={BB256} succs={BB24,BB47} ===== N3857. IL_OFFSET INLRT @ 0x0FB[E-] N3859. V04(L3) N3861. CNS_INT 0 N3863. LE N3865. V05(L4) N3867. CNS_INT 0 N3869. GE N3871. AND N3873. JTRUE Use:(#1929) Use:(#1930) BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} ===== N3877. IL_OFFSET INLRT @ 0x102[E-] N3879. IL_OFFSET INLRT @ 0x109[E-] N3881. V10(L9) N3883. CNS_INT 0 N3885. LT Use:(#1932) N3887. JTRUE BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} ===== N3891. IL_OFFSET INLRT @ 0x10E[E-] N3893. V10(L9) N3895. V04(L3) N3897. NE Use:(#1934) Use:(#1935) N3899. JTRUE BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ===== N3903. IL_OFFSET INLRT @ 0x113[E-] N3905. V11(L10) N3907. CNS_INT 1 N3909. ADD Use:(#1937) * Def:(#1938) Pref: N3911. V11(L10) Use:(#1939) * Def:(#1940) Exposed use of V10 at #1941 Exposed use of V12 at #1942 Exposed use of V11 at #1943 BB28 [11E..121), preds={BB26} succs={BB29} ===== N3915. IL_OFFSET INLRT @ 0x11E[E-] N3917. CNS_INT 1 Def:(#1945) Pref: N3919. V12(L11) Use:(#1946) * Def:(#1947) BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} ===== N3923. IL_OFFSET INLRT @ 0x121[E-] N3925. V04(L3) N3927. V10(L9) Use:(#1949) Def:(#1950) N3929. IL_OFFSET INLRT @ 0x124[E-] N3931. CNS_INT 1 Def:(#1951) Pref: N3933. V11(L10) Use:(#1952) * Def:(#1953) Exposed use of V22 at #1954 Exposed use of V13 at #1955 Exposed use of V10 at #1956 Exposed use of V11 at #1957 Exposed use of V180 at #1958 BB257 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194 (switch), preds={BB137} succs={BB145,BB186,BB194,BB242} ===== N3937. V184(L135) N3939. CAST Use:(#1960) * Def:(#1961) N3941. JMPTABLE Def:(#1962) N3943. SWITCH_TABLE Def:(#1963) Use:(#1964) * Use:(#1965) * BB145 [4E9..4EE) -> BB150 (cond), preds={BB257,BB258} succs={BB146,BB150} ===== N3947. IL_OFFSET INLRT @ 0x4E9[E-] N3949. V14(L13) N3951. CNS_INT 0 N3953. GE Use:(#1967) N3955. JTRUE BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ===== N3959. IL_OFFSET INLRT @ 0x4EE[E-] N3961. V14(L13) N3963. CNS_INT 1 N3965. ADD Use:(#1969) * Def:(#1970) Pref: N3967. V14(L13) Use:(#1971) * Def:(#1972) N3969. IL_OFFSET INLRT @ 0x4F4[E-] N3971. V08(L7) N3973. V06(L5) N3975. LE Use:(#1973) Use:(#1974) N3977. JTRUE BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ===== N3981. IL_OFFSET INLRT @ 0x4F9[E-] N3983. CNS_INT 0 N3985. V58(L46) Def:(#1976) BB148 [4FC..4FE), preds={BB146} succs={BB149} ===== N3989. IL_OFFSET INLRT @ 0x4FC[E-] N3991. CNS_INT 48 Def:(#1978) Pref: N3993. V58(L46) Use:(#1979) * Def:(#1980) BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ===== N3997. V58(L46) N3999. CAST Use:(#1982) * Def:(#1983) Pref: N4001. V18(L17) Use:(#1984) * Def:(#1985) BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ===== N4005. IL_OFFSET INLRT @ 0x502[E-] N4007. V36(L30) N4009. IND Use:(#1987) Def:(#1988) N4011. CNS_INT 0 N4013. JCMP Use:(#1989) * BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ===== N4017. IL_OFFSET INLRT @ 0x507[E-] N4019. V08(L7) N4021. V07(L6) N4023. GT Use:(#1991) Use:(#1992) N4025. JTRUE BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ===== N4029. IL_OFFSET INLRT @ 0x50C[E-] N4031. CNS_INT 0 N4033. V57(L45) Def:(#1994) BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ===== N4037. IL_OFFSET INLRT @ 0x50F[E-] N4039. CNS_INT 48 Def:(#1996) Pref: N4041. V57(L45) Use:(#1997) * Def:(#1998) BB154 [513..51B), preds={BB150} succs={BB155} ===== N4045. IL_OFFSET INLRT @ 0x513[E-] N4047. V36(L30) N4049. V56(L44) Use:(#2000) * Def:(#2001) N4051. IL_OFFSET INLRT @ 0x513[E-] N4053. V56(L44) N4055. CNS_INT 1 N4057. ADD Use:(#2002) Def:(#2003) Pref: N4059. V36(L30) Use:(#2004) * Def:(#2005) Pref: N4061. V56(L44) N4063. IND Use:(#2006) * Def:(#2007) Pref: N4065. V57(L45) Use:(#2008) * Def:(#2009) BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ===== N4069. V57(L45) N4071. CAST Use:(#2011) * Def:(#2012) Pref: N4073. V18(L17) Use:(#2013) * Def:(#2014) BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ===== N4077. IL_OFFSET INLRT @ 0x51D[E-] N4079. V18(L17) N4081. CNS_INT 0 N4083. JCMP Use:(#2016) BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ===== N4087. IL_OFFSET INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] N4089. V00(L0) N4091. LEA(b+8) N4093. IND Use:(#2018) Def:(#2019) Pref: N4095. V99(L71) Use:(#2020) * Def:(#2021) N4097. IL_OFFSET INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] N4099. V99(L71) N4101. V00(L0) N4103. LEA(b+24) N4105. IND Use:(#2022) Def:(#2023) N4107. GE Use:(#2024) Use:(#2025) * N4109. JTRUE BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ===== N4113. IL_OFFSET INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] N4115. V00(L0) N4117. CNS_INT 16 N4119. ADD Use:(#2027) Def:(#2028) Pref: N4121. V100(L72) Use:(#2029) * Def:(#2030) N4123. IL_OFFSET INL34 @ ??? <- INLRT @ 0x521[E-] N4125. V99(L71) N4127. V100(L72) N4129. LEA(b+8) N4131. IND Use:(#2031) Def:(#2032) N4133. BOUNDS_CHECK_Rng -> BB254 Use:(#2033) Use:(#2034) * N4135. V100(L72) N4137. IND Use:(#2035) * Def:(#2036) N4139. V99(L71) N4141. CAST N4143. CNS_INT 1 N4145. BFIZ N4147. LEA(b+(i*1)+0) N4149. V18(L17) N4151. STOREIND Use:(#2037) * Use:(#2038) Use:(#2039) * N4153. IL_OFFSET INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] N4155. V99(L71) N4157. CNS_INT 1 N4159. ADD Use:(#2040) * Def:(#2041) N4161. V00(L0) N4163. LEA(b+8) N4165. STOREIND Use:(#2042) Use:(#2043) * BB159 [521..522), preds={BB157} succs={BB160} ===== N4169. IL_OFFSET INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] N4171. V00(L0) N4173. PUTARG_REG Use:(#2046) Fixed:x0(#2045) Def:(#2048) x0 Pref: N4175. V18(L17) N4177. PUTARG_REG Use:(#2050) Fixed:x1(#2049) * Def:(#2052) x1 N4179. CNS_INT(h) 0x4000000000435c58 ftn Def:(#2053) N4181. PUTARG_REG Use:(#2055) Fixed:x11(#2054) * Def:(#2057) x11 N4183. CALL r2r_ind Def:(#2058) Use:(#2060) Fixed:x0(#2059) * Use:(#2062) Fixed:x1(#2061) * Use:(#2064) Fixed:x11(#2063) * Use:(#2065) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ===== N4187. IL_OFFSET INLRT @ 0x529[E-] N4189. V12(L11) N4191. CNS_INT 0 N4193. EQ N4195. V08(L7) N4197. CNS_INT 1 N4199. LE N4201. AND N4203. JTRUE Use:(#2086) Use:(#2087) BB161 [52D..537) -> BB170 (cond), preds={BB160} succs={BB163,BB170} ===== N4207. IL_OFFSET INLRT @ 0x52D[E-] N4209. IL_OFFSET INLRT @ 0x532[E-] N4211. V20(L18) N4213. V144(L104) N4215. BOUNDS_CHECK_Rng -> BB254 Use:(#2089) Use:(#2090) N4217. V143(L103) N4219. V20(L18) N4221. CAST N4223. CNS_INT 2 N4225. BFIZ N4227. LEA(b+(i*1)+0) N4229. IND Use:(#2091) Use:(#2092) Def:(#2093) N4231. CNS_INT 1 N4233. ADD Use:(#2094) * Def:(#2095) N4235. V08(L7) N4237. NE N4239. V20(L18) N4241. CNS_INT 0 N4243. LT N4245. AND N4247. JTRUE Use:(#2096) * Use:(#2097) Use:(#2098) BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} ===== N4251. IL_OFFSET INLRT @ 0x537[E-] N4253. IL_OFFSET INLRT @ 0x547[E-] N4255. V03(L2) N4257. LEA(b+56) N4259. IND Use:(#2100) Def:(#2101) Pref: N4261. V102(L73) Use:(#2102) * Def:(#2103) N4263. IL_OFFSET INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] N4265. V102(L73) N4267. CNS_INT null N4269. JCMP Use:(#2104) BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} ===== N4273. IL_OFFSET INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] N4275. V00(L0) N4277. LEA(b+8) N4279. IND Use:(#2106) Def:(#2107) Pref: N4281. V103(L74) Use:(#2108) * Def:(#2109) N4283. IL_OFFSET INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] N4285. V102(L73) N4287. LEA(b+8) N4289. IND Use:(#2110) Def:(#2111) N4291. CNS_INT 1 N4293. NE N4295. V103(L74) N4297. V00(L0) N4299. LEA(b+24) N4301. IND Use:(#2112) Def:(#2113) N4303. GE N4305. AND N4307. JTRUE Use:(#2114) * Use:(#2115) Use:(#2116) * BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} ===== N4311. IL_OFFSET INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] N4313. IL_OFFSET INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] N4315. V00(L0) N4317. CNS_INT 16 N4319. ADD Use:(#2118) Def:(#2119) Pref: N4321. V104(L75) Use:(#2120) * Def:(#2121) N4323. IL_OFFSET INL37 @ ??? <- INLRT @ 0x547[E-] N4325. V103(L74) N4327. V104(L75) N4329. LEA(b+8) N4331. IND Use:(#2122) Def:(#2123) N4333. BOUNDS_CHECK_Rng -> BB254 Use:(#2124) Use:(#2125) * N4335. V104(L75) N4337. IND Use:(#2126) * Def:(#2127) N4339. V103(L74) N4341. CAST N4343. CNS_INT 1 N4345. BFIZ Use:(#2128) Def:(#2129) N4347. ADD Use:(#2130) * Use:(#2131) * Def:(#2132) N4349. CNS_INT 0 N4351. V102(L73) N4353. LEA(b+8) N4355. IND Use:(#2133) Def:(#2134) N4357. BOUNDS_CHECK_Rng -> BB254 Use:(#2135) * N4359. V102(L73) N4361. LEA(b+12) N4363. IND Use:(#2136) * Def:(#2137) N4365. STOREIND Use:(#2138) * Use:(#2139) * N4367. IL_OFFSET INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] N4369. V103(L74) N4371. CNS_INT 1 N4373. ADD Use:(#2140) * Def:(#2141) N4375. V00(L0) N4377. LEA(b+8) N4379. STOREIND Use:(#2142) Use:(#2143) * BB168 [547..548), preds={BB165} succs={BB169} ===== N4383. IL_OFFSET INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] N4385. V00(L0) N4387. PUTARG_REG Use:(#2146) Fixed:x0(#2145) Def:(#2148) x0 Pref: N4389. V102(L73) N4391. PUTARG_REG Use:(#2150) Fixed:x1(#2149) * Def:(#2152) x1 N4393. CNS_INT(h) 0x4000000000431d58 ftn Def:(#2153) N4395. PUTARG_REG Use:(#2155) Fixed:x11(#2154) * Def:(#2157) x11 N4397. CALL r2r_ind Def:(#2158) Use:(#2160) Fixed:x0(#2159) * Use:(#2162) Fixed:x1(#2161) * Use:(#2164) Fixed:x11(#2163) * Use:(#2165) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} ===== N4401. IL_OFFSET INLRT @ 0x553[E-] N4403. V20(L18) N4405. CNS_INT -1 N4407. ADD Use:(#2186) * Def:(#2187) Pref: N4409. V20(L18) Use:(#2188) * Def:(#2189) BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB161,BB169} succs={BB245} ===== N4413. IL_OFFSET INLRT @ 0x559[E-] N4415. V08(L7) N4417. CNS_INT -1 N4419. ADD Use:(#2191) * Def:(#2192) Pref: N4421. V08(L7) Use:(#2193) * Def:(#2194) BB186 [5A9..5BA) -> BB245 (cond), preds={BB257} succs={BB187,BB245} ===== N4425. IL_OFFSET INLRT @ 0x5A9[E-] N4427. V03(L2) N4429. LEA(b+128) N4431. IND Use:(#2196) Def:(#2197) Pref: N4433. V114(L82) Use:(#2198) * Def:(#2199) N4435. IL_OFFSET INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] N4437. V114(L82) N4439. CNS_INT null N4441. JCMP Use:(#2200) Dummy def of V114 at #2201 BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ===== N4445. IL_OFFSET INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] N4447. V00(L0) N4449. LEA(b+8) N4451. IND Use:(#2203) Def:(#2204) Pref: N4453. V115(L83) Use:(#2205) * Def:(#2206) N4455. IL_OFFSET INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] N4457. V114(L82) N4459. LEA(b+8) N4461. IND Use:(#2207) Def:(#2208) N4463. CNS_INT 1 N4465. NE N4467. V115(L83) N4469. V00(L0) N4471. LEA(b+24) N4473. IND Use:(#2209) Def:(#2210) N4475. GE N4477. AND N4479. JTRUE Use:(#2211) * Use:(#2212) Use:(#2213) * BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ===== N4483. IL_OFFSET INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] N4485. IL_OFFSET INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] N4487. V00(L0) N4489. CNS_INT 16 N4491. ADD Use:(#2215) Def:(#2216) Pref: N4493. V116(L84) Use:(#2217) * Def:(#2218) N4495. IL_OFFSET INL46 @ ??? <- INLRT @ 0x5A9[E-] N4497. V115(L83) N4499. V116(L84) N4501. LEA(b+8) N4503. IND Use:(#2219) Def:(#2220) N4505. BOUNDS_CHECK_Rng -> BB254 Use:(#2221) Use:(#2222) * N4507. V116(L84) N4509. IND Use:(#2223) * Def:(#2224) N4511. V115(L83) N4513. CAST N4515. CNS_INT 1 N4517. BFIZ Use:(#2225) Def:(#2226) N4519. ADD Use:(#2227) * Use:(#2228) * Def:(#2229) N4521. CNS_INT 0 N4523. V114(L82) N4525. LEA(b+8) N4527. IND Use:(#2230) Def:(#2231) N4529. BOUNDS_CHECK_Rng -> BB254 Use:(#2232) * N4531. V114(L82) N4533. LEA(b+12) N4535. IND Use:(#2233) * Def:(#2234) N4537. STOREIND Use:(#2235) * Use:(#2236) * N4539. IL_OFFSET INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] N4541. V115(L83) N4543. CNS_INT 1 N4545. ADD Use:(#2237) * Def:(#2238) N4547. V00(L0) N4549. LEA(b+8) N4551. STOREIND Use:(#2239) Use:(#2240) * BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ===== N4555. IL_OFFSET INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] N4557. V00(L0) N4559. PUTARG_REG Use:(#2243) Fixed:x0(#2242) Def:(#2245) x0 Pref: N4561. V114(L82) N4563. PUTARG_REG Use:(#2247) Fixed:x1(#2246) * Def:(#2249) x1 N4565. CNS_INT(h) 0x4000000000431d58 ftn Def:(#2250) N4567. PUTARG_REG Use:(#2252) Fixed:x11(#2251) * Def:(#2254) x11 N4569. CALL r2r_ind Def:(#2255) Use:(#2257) Fixed:x0(#2256) * Use:(#2259) Fixed:x1(#2258) * Use:(#2261) Fixed:x11(#2260) * Use:(#2262) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB194 [5CE..5D9) -> BB197 (cond), preds={BB192,BB193,BB257(2)} succs={BB195,BB197} ===== N4573. IL_OFFSET INLRT @ 0x5CE[E-] N4575. V16(L15) N4577. V179(L130) N4579. GE Use:(#2283) Use:(#2284) N4581. JTRUE BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ===== N4585. IL_OFFSET INLRT @ 0x5D9[E-] N4587. V34(L29) N4589. V16(L15) N4591. CAST N4593. CNS_INT 1 N4595. BFIZ N4597. LEA(b+(i*1)+0) N4599. IND Use:(#2286) Use:(#2287) Def:(#2288) Pref: N4601. V172(L123) Use:(#2289) * Def:(#2290) Pref: N4603. V172(L123) N4605. CNS_INT 0 N4607. JCMP Use:(#2291) BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ===== N4611. IL_OFFSET INLRT @ 0x5E4[E-] N4613. V172(L123) N4615. V18(L17) N4617. NE Use:(#2293) Use:(#2294) N4619. JTRUE BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ===== N4623. IL_OFFSET INLRT @ 0x5BA[E-] N4625. V16(L15) N4627. V59(L47) Use:(#2296) * Def:(#2297) N4629. IL_OFFSET INLRT @ 0x5BA[E-] N4631. V59(L47) N4633. CNS_INT 1 N4635. ADD Use:(#2298) * Def:(#2299) Pref: N4637. V16(L15) Use:(#2300) * Def:(#2301) Pref: N4639. V172(L123) N4641. V119(L86) Use:(#2302) * Def:(#2303) N4643. IL_OFFSET INL48 @ 0x000[E-] <- INLRT @ ??? N4645. V00(L0) N4647. LEA(b+8) N4649. IND Use:(#2304) Def:(#2305) Pref: N4651. V118(L85) Use:(#2306) * Def:(#2307) N4653. IL_OFFSET INL48 @ 0x007[E-] <- INLRT @ ??? N4655. V118(L85) N4657. V00(L0) N4659. LEA(b+24) N4661. IND Use:(#2308) Def:(#2309) N4663. GE Use:(#2310) Use:(#2311) * N4665. JTRUE BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ===== N4669. IL_OFFSET INL48 @ 0x015[E-] <- INLRT @ ??? N4671. V00(L0) N4673. CNS_INT 16 N4675. ADD Use:(#2313) Def:(#2314) Pref: N4677. V120(L87) Use:(#2315) * Def:(#2316) N4679. V118(L85) N4681. V120(L87) N4683. LEA(b+8) N4685. IND Use:(#2317) Def:(#2318) N4687. BOUNDS_CHECK_Rng -> BB254 Use:(#2319) Use:(#2320) * N4689. V120(L87) N4691. IND Use:(#2321) * Def:(#2322) N4693. V118(L85) N4695. CAST N4697. CNS_INT 1 N4699. BFIZ N4701. LEA(b+(i*1)+0) N4703. V119(L86) N4705. STOREIND Use:(#2323) * Use:(#2324) Use:(#2325) * N4707. IL_OFFSET INL48 @ 0x023[E-] <- INLRT @ ??? N4709. V118(L85) N4711. CNS_INT 1 N4713. ADD Use:(#2326) * Def:(#2327) N4715. V00(L0) N4717. LEA(b+8) N4719. STOREIND Use:(#2328) Use:(#2329) * BB193 [000..000), preds={BB191} succs={BB194} ===== N4723. IL_OFFSET INL48 @ 0x02D[E-] <- INLRT @ ??? N4725. V00(L0) N4727. PUTARG_REG Use:(#2332) Fixed:x0(#2331) Def:(#2334) x0 Pref: N4729. V119(L86) N4731. PUTARG_REG Use:(#2336) Fixed:x1(#2335) * Def:(#2338) x1 N4733. CNS_INT(h) 0x4000000000435c58 ftn Def:(#2339) N4735. PUTARG_REG Use:(#2341) Fixed:x11(#2340) * Def:(#2343) x11 N4737. CALL r2r_ind Def:(#2344) Use:(#2346) Fixed:x0(#2345) * Use:(#2348) Fixed:x1(#2347) * Use:(#2350) Fixed:x11(#2349) * Use:(#2351) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr Exposed use of V18 at #2371 BB197 [5F1..5FF) -> BB245 (cond), preds={BB194,BB196} succs={BB198,BB245} ===== N4741. IL_OFFSET INLRT @ 0x5F1[E-] N4743. V16(L15) N4745. V179(L130) N4747. GE Use:(#2373) Use:(#2374) N4749. JTRUE BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ===== N4753. IL_OFFSET INLRT @ 0x5FF[E-] N4755. V34(L29) N4757. V16(L15) N4759. CAST N4761. CNS_INT 1 N4763. BFIZ N4765. LEA(b+(i*1)+0) N4767. IND Use:(#2376) Use:(#2377) Def:(#2378) Pref: N4769. V172(L123) Use:(#2379) * Def:(#2380) Pref: N4771. V172(L123) N4773. CNS_INT 0 N4775. JCMP Use:(#2381) * BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ===== N4779. IL_OFFSET INLRT @ 0x60D[E-] N4781. V16(L15) N4783. CNS_INT 1 N4785. ADD Use:(#2383) * Def:(#2384) Pref: N4787. V16(L15) Use:(#2385) * Def:(#2386) Pref: BB258 [49A..4B8) -> BB245,BB242,BB171,BB242,BB145 (switch), preds={BB138} succs={BB145,BB171,BB242,BB245} ===== N4791. V185(L136) N4793. CAST Use:(#2388) * Def:(#2389) N4795. JMPTABLE Def:(#2390) N4797. SWITCH_TABLE Def:(#2391) Use:(#2392) * Use:(#2393) * Exposed use of V18 at #2394 BB171 [564..571) -> BB245 (cond), preds={BB258} succs={BB172,BB245} ===== N4801. IL_OFFSET INLRT @ 0x564[E-] N4803. V08(L7) N4805. CNS_INT 0 N4807. NE Use:(#2396) Def:(#2397) N4809. V21(L19) N4811. OR Use:(#2398) * Use:(#2399) Def:(#2400) N4813. CNS_INT 0 N4815. JCMP Use:(#2401) * BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ===== N4819. IL_OFFSET INLRT @ 0x571[E-] N4821. V07(L6) N4823. CNS_INT 0 N4825. LT Use:(#2403) N4827. JTRUE BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ===== N4831. IL_OFFSET INLRT @ 0x575[E-] N4833. V05(L4) N4835. V04(L3) N4837. GE N4839. V36(L30) N4841. IND Use:(#2405) Def:(#2406) N4843. CNS_INT 0 N4845. EQ N4847. AND N4849. JTRUE Use:(#2407) Use:(#2408) Use:(#2409) * Exposed use of V21 at #2410 BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} ===== N4853. IL_OFFSET INLRT @ 0x57C[E-] N4855. IL_OFFSET INLRT @ 0x584[E-] N4857. V03(L2) N4859. LEA(b+48) N4861. IND Use:(#2412) Def:(#2413) Pref: N4863. V106(L76) Use:(#2414) * Def:(#2415) N4865. IL_OFFSET INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] N4867. V106(L76) N4869. CNS_INT null N4871. JCMP Use:(#2416) BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} ===== N4875. IL_OFFSET INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] N4877. V00(L0) N4879. LEA(b+8) N4881. IND Use:(#2418) Def:(#2419) Pref: N4883. V107(L77) Use:(#2420) * Def:(#2421) N4885. IL_OFFSET INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] N4887. V106(L76) N4889. LEA(b+8) N4891. IND Use:(#2422) Def:(#2423) N4893. CNS_INT 1 N4895. NE N4897. V107(L77) N4899. V00(L0) N4901. LEA(b+24) N4903. IND Use:(#2424) Def:(#2425) N4905. GE N4907. AND N4909. JTRUE Use:(#2426) * Use:(#2427) Use:(#2428) * BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} ===== N4913. IL_OFFSET INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] N4915. IL_OFFSET INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] N4917. V00(L0) N4919. CNS_INT 16 N4921. ADD Use:(#2430) Def:(#2431) Pref: N4923. V108(L78) Use:(#2432) * Def:(#2433) N4925. IL_OFFSET INL40 @ ??? <- INLRT @ 0x584[E-] N4927. V107(L77) N4929. V108(L78) N4931. LEA(b+8) N4933. IND Use:(#2434) Def:(#2435) N4935. BOUNDS_CHECK_Rng -> BB254 Use:(#2436) Use:(#2437) * N4937. V108(L78) N4939. IND Use:(#2438) * Def:(#2439) N4941. V107(L77) N4943. CAST N4945. CNS_INT 1 N4947. BFIZ Use:(#2440) Def:(#2441) N4949. ADD Use:(#2442) * Use:(#2443) * Def:(#2444) N4951. CNS_INT 0 N4953. V106(L76) N4955. LEA(b+8) N4957. IND Use:(#2445) Def:(#2446) N4959. BOUNDS_CHECK_Rng -> BB254 Use:(#2447) * N4961. V106(L76) N4963. LEA(b+12) N4965. IND Use:(#2448) * Def:(#2449) N4967. STOREIND Use:(#2450) * Use:(#2451) * N4969. IL_OFFSET INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] N4971. V107(L77) N4973. CNS_INT 1 N4975. ADD Use:(#2452) * Def:(#2453) N4977. V00(L0) N4979. LEA(b+8) N4981. STOREIND Use:(#2454) Use:(#2455) * BB179 [584..585), preds={BB176} succs={BB180} ===== N4985. IL_OFFSET INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] N4987. V00(L0) N4989. PUTARG_REG Use:(#2458) Fixed:x0(#2457) Def:(#2460) x0 Pref: N4991. V106(L76) N4993. PUTARG_REG Use:(#2462) Fixed:x1(#2461) * Def:(#2464) x1 N4995. CNS_INT(h) 0x4000000000431d58 ftn Def:(#2465) N4997. PUTARG_REG Use:(#2467) Fixed:x11(#2466) * Def:(#2469) x11 N4999. CALL r2r_ind Def:(#2470) Use:(#2472) Fixed:x0(#2471) * Use:(#2474) Fixed:x1(#2473) * Use:(#2476) Fixed:x11(#2475) * Use:(#2477) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} ===== N5003. IL_OFFSET INLRT @ 0x590[E-] N5005. CNS_INT 1 Def:(#2498) Pref: N5007. V21(L19) Use:(#2499) * Def:(#2500) Exposed use of V16 at #2501 Exposed use of V00 at #2502 Exposed use of V179 at #2503 Exposed use of V04 at #2504 Exposed use of V20 at #2505 Exposed use of V34 at #2506 Exposed use of V05 at #2507 Exposed use of V08 at #2508 Exposed use of V14 at #2509 Exposed use of V36 at #2510 Exposed use of V06 at #2511 Exposed use of V12 at #2512 Exposed use of V144 at #2513 Exposed use of V09 at #2514 Exposed use of V03 at #2515 Exposed use of V01 at #2516 Exposed use of V07 at #2517 Exposed use of V143 at #2518 Exposed use of V15 at #2519 Exposed use of V17 at #2520 Exposed use of V21 at #2521 BB110 [000..000) (throw), preds={BB91} succs={} ===== N5011. IL_OFFSET INL17 @ 0x029[E-] <- INLRT @ ??? N5013. CNS_INT(h) 0x4000000000424a20 ftn Def:(#2523) N5015. PUTARG_REG Use:(#2525) Fixed:x11(#2524) * Def:(#2527) x11 N5017. CALL r2r_ind Def:(#2528) Use:(#2530) Fixed:x11(#2529) * Use:(#2531) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr BB254 [???..???) (throw), preds={} succs={} ===== N5021. CNS_INT(h) 0x4000000000421828 ftn Def:(#2552) N5023. IND Use:(#2553) * Def:(#2554) N5025. CALL help Use:(#2555) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr Linear scan intervals after buildIntervals: Interval 0: (V00) byref RefPositions {#0@0 #758@1571 #764@1593 #770@1611 #791@1661 #795@1669 #901@1899 #905@1911 #910@1925 #925@1969 #929@1977 #989@2083 #997@2109 #1003@2127 #1025@2183 #1029@2191 #1116@2369 #1122@2391 #1128@2409 #1152@2469 #1156@2477 #1214@2555 #1218@2567 #1223@2581 #1238@2625 #1242@2633 #1333@2833 #1337@2845 #1342@2859 #1357@2905 #1405@3033 #1466@3071 #1470@3083 #1475@3097 #1490@3143 #1494@3151 #1554@3243 #1558@3255 #1563@3269 #1578@3313 #1582@3321 #1640@3401 #1644@3413 #1649@3427 #1664@3471 #1668@3479 #1709@3501 #1713@3513 #1718@3527 #1733@3573 #1737@3581 #1803@3643 #1819@3669 #2018@4093 #2022@4105 #2027@4119 #2042@4165 #2046@4173 #2106@4279 #2112@4301 #2118@4319 #2142@4379 #2146@4387 #2203@4451 #2209@4473 #2215@4491 #2239@4551 #2243@4559 #2304@4649 #2308@4661 #2313@4675 #2328@4719 #2332@4727 #2418@4881 #2424@4903 #2430@4921 #2454@4981 #2458@4989 #2502@5009} physReg:x0 Preferences=[x19-x28] Interval 1: (V01) byref RefPositions {#2@0 #5@7 #39@27 #70@93 #313@749 #326@781 #345@811 #450@885 #454@903 #456@915 #486@1007 #743@1511 #748@1537 #1390@3007 #1794@3607 #1799@3633 #2516@5009} physReg:x1 Preferences=[x19-x28] Interval 2: (V03) ref RefPositions {#1@0 #518@1081 #525@1111 #752@1551 #983@2063 #1108@2347 #1409@3037 #1812@3663 #2100@4259 #2196@4431 #2412@4861 #2515@5009} physReg:x4 Preferences=[x19-x28] Interval 3: (V04) int RefPositions {#147@172 #289@679 #329@785 #337@799 #1778@3593 #1870@3705 #1873@3708 #1913@3815 #1916@3825 #1919@3828 #1920@3833 #1926@3853 #1929@3873 #1935@3897 #1949@3927 #2408@4849 #2504@5009} physReg:NA Preferences=[x19-x28] Interval 4: (V05) int RefPositions {#150@178 #287@669 #290@680 #295@701 #332@789 #458@933 #462@937 #469@961 #473@965 #482@989 #491@1021 #493@1021 #500@1037 #1393@3011 #1781@3593 #1923@3843 #1924@3847 #1927@3854 #1930@3873 #2407@4849 #2507@5009} physReg:NA Preferences=[x19-x28] Interval 5: (V06) int RefPositions {#153@184 #459@933 #461@937 #468@946 #562@1223 #564@1223 #1785@3593 #1910@3805 #1914@3816 #1974@3975 #2511@5009} physReg:NA Preferences=[x19-x28] Interval 6: (V07) int RefPositions {#154@190 #470@961 #472@965 #479@974 #1789@3593 #1921@3834 #1992@4023 #2403@4825 #2517@5009} physReg:NA Preferences=[x19-x28] Interval 7: (V08) int RefPositions {#483@990 #498@1030 #544@1167 #970@2007 #980@2051 #1074@2223 #1077@2226 #1782@3593 #1973@3975 #1991@4023 #2087@4203 #2097@4247 #2191@4419 #2194@4422 #2396@4807 #2508@5009} physReg:NA Preferences=[x19-x28] Interval 8: (V09) int RefPositions {#155@196 #265@599 #283@654 #324@771 #480@981 #1284@2665 #1359@2907 #1464@3062 #1788@3593 #2514@5009} physReg:NA Preferences=[x19-x28] Interval 9: (V10) int RefPositions {#158@202 #292@689 #294@701 #1932@3885 #1934@3897 #1941@3913 #1950@3928 #1956@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: (V11) int RefPositions {#38@20 #299@717 #448@877 #1937@3909 #1940@3912 #1943@3913 #1953@3934 #1957@3935} physReg:NA Preferences=[x19-x28] Interval 11: (V12) int RefPositions {#159@208 #307@728 #523@1099 #969@2007 #1786@3593 #1942@3913 #1947@3920 #2086@4203 #2512@5009} physReg:NA Preferences=[x19-x28] Interval 12: (V13) int RefPositions {#160@214 #216@421 #219@424 #298@717 #303@720 #320@759 #1875@3717 #1878@3720 #1955@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 13: (V14) int RefPositions {#484@996 #503@1040 #546@1175 #554@1197 #866@1793 #876@1841 #1078@2233 #1081@2236 #1783@3593 #1967@3953 #1969@3965 #1972@3968 #2509@5009} physReg:NA Preferences=[x19-x28] Interval 14: (V15) int RefPositions {#145@164 #161@219 #444@865 #447@876 #505@1047 #1797@3621 #2519@5009} physReg:NA Preferences=[x19-x28] Interval 15: (V16) int RefPositions {#162@220 #171@251 #174@261 #179@272 #222@447 #226@459 #230@471 #233@474 #235@483 #239@503 #245@523 #251@547 #259@581 #267@607 #272@614 #273@619 #277@639 #284@655 #442@858 #443@865 #446@875 #506@1048 #746@1525 #846@1725 #849@1735 #854@1746 #1197@2511 #1201@2523 #1206@2533 #1211@2544 #1286@2675 #1290@2695 #1296@2715 #1302@2739 #1308@2755 #1326@2807 #1366@2927 #1371@2934 #1372@2939 #1376@2959 #1534@3171 #1538@3191 #1546@3221 #1551@3232 #1622@3341 #1626@3361 #1632@3379 #1637@3390 #1776@3593 #1881@3743 #1885@3755 #1891@3765 #1896@3776 #2283@4579 #2287@4599 #2296@4627 #2301@4638 #2373@4747 #2377@4767 #2383@4785 #2386@4788 #2501@5009} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 16: (V17) long RefPositions {#51@52 #62@73 #309@735 #387@827 #843@1715 #1386@2993 #1791@3593 #2520@5009} physReg:NA Preferences=[x19-x28] Interval 17: (V18) int RefPositions {#186@292 #187@297 #189@307 #191@319 #193@331 #199@351 #205@371 #208@385 #210@397 #213@409 #861@1766 #862@1771 #864@1781 #869@1815 #870@1815 #873@1827 #1083@2245 #1085@2257 #1091@2277 #1097@2297 #1100@2311 #1102@2323 #1105@2335 #1354@2891 #1417@3045 #1487@3129 #1498@3155 #1730@3559 #1741@3585 #1888@3757 #1898@3781 #1899@3785 #1985@4002 #2014@4074 #2016@4083 #2039@4151 #2050@4177 #2294@4617 #2371@4739 #2394@4799} physReg:NA Preferences=[x19-x28] Interval 18: (V20) int RefPositions {#517@1074 #576@1261 #579@1264 #580@1271 #703@1405 #706@1421 #972@2019 #975@2033 #981@2051 #1069@2211 #1072@2214 #1779@3593 #2089@4215 #2092@4229 #2098@4247 #2186@4407 #2189@4410 #2505@5009} physReg:NA Preferences=[x19-x28] Interval 19: (V21) int RefPositions {#835@1688 #1792@3593 #2399@4811 #2410@4851 #2500@5008 #2521@5009} physReg:NA Preferences=[x19-x28] Interval 20: (V22) long RefPositions {#169@242 #180@285 #221@447 #238@503 #250@547 #261@591 #276@639 #285@655 #1880@3743 #1954@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 21: (V26) ref RefPositions {#528@1114 #531@1133 #537@1153 #717@1457 #721@1465 #739@1503} physReg:NA Preferences=[x19-x28] Interval 22: (V27) int RefPositions {#529@1120 #710@1433 #713@1445 #716@1448 #719@1459 #724@1477 #737@1503} physReg:NA Preferences=[x19-x28] Interval 23: (V28) int RefPositions {#530@1126 #540@1156 #542@1163 #707@1421 #729@1489 #733@1492 #735@1499 #736@1503} physReg:NA Preferences=[x19-x28] Interval 24: (V29) int RefPositions {#534@1136 #535@1143 #708@1431 #740@1503} physReg:NA Preferences=[x19-x28] Interval 25: (V30) int RefPositions {#543@1164 #572@1239 #574@1251 #727@1480 #730@1489 #738@1503} physReg:NA Preferences=[x19-x28] Interval 26: (V31) int RefPositions {#561@1208 #563@1223 #565@1223} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 27: (V32) int RefPositions {#570@1232 #571@1239 #734@1499 #741@1503} physReg:NA Preferences=[x19-x28] Interval 28: (V33) ref RefPositions {#624@1296 #625@1305 #629@1315 #690@1373 #694@1383} physReg:NA Preferences=[x19-x28] Interval 29: (V34) long RefPositions {#842@1710 #855@1759 #1196@2511 #1289@2695 #1301@2739 #1310@2765 #1328@2817 #1375@2959 #1537@3191 #1625@3361 #1780@3593 #2286@4599 #2376@4767 #2506@5009} physReg:NA Preferences=[x19-x28] Interval 30: (V36) long RefPositions {#844@1716 #878@1851 #888@1871 #893@1880 #1784@3593 #1987@4009 #2000@4049 #2005@4060 #2405@4841 #2510@5009} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 31: (V37) int RefPositions {#1282@2652 #1322@2784 #1401@3029} physReg:NA Preferences=[x5] Interval 32: (V38) int RefPositions {#1283@2658 #1361@2915 #1364@2918 #1380@2975 #1384@2986 #1421@3049} physReg:NA Preferences=[x4] Interval 33: (V43) int RefPositions {#78@112 #86@126 #94@140 #105@155} physReg:NA Preferences=[x2] Interval 34: (V44) int RefPositions {#466@940 #467@945} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 35: (V45) int RefPositions {#477@968 #478@973} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 36: (V46) int RefPositions {#496@1024 #497@1029} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 37: (V49) int RefPositions {#850@1736 #851@1743 #856@1759} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 38: (V50) int RefPositions {#859@1762 #860@1765} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 39: (V51) int RefPositions {#1207@2534 #1208@2541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 40: (V52) int RefPositions {#1547@3222 #1548@3229} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 41: (V53) int RefPositions {#1633@3380 #1634@3387} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 42: (V54) int RefPositions {#1369@2930 #1370@2933} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 43: (V55) int RefPositions {#1396@3014 #1398@3022 #1413@3041} physReg:NA Preferences=[x2] Interval 44: (V56) long RefPositions {#2001@4050 #2002@4057 #2006@4063} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 45: (V57) int RefPositions {#1994@4034 #1998@4042 #2009@4066 #2011@4071} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 46: (V58) int RefPositions {#1976@3986 #1980@3994 #1982@3999} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 47: (V59) int RefPositions {#2297@4628 #2298@4635} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 48: (V61) long RefPositions {#889@1872 #890@1877} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 49: (V63) int RefPositions {#886@1866 #895@1884 #897@1889} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 50: (V64) int RefPositions {#545@1168 #548@1183 #552@1193} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 51: (V65) int RefPositions {#549@1184 #553@1194 #557@1205} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 52: (V66) int RefPositions {#550@1188 #555@1198 #558@1205} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 53: (V67) int RefPositions {#568@1226 #569@1231} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 54: (V69) byref RefPositions {#316@752 #317@755 #322@763} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 55: (V70) int RefPositions {#335@792 #338@800 #341@807} physReg:NA Preferences=[x1] Interval 56: (V71) int RefPositions {#175@262 #176@269 #181@285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 57: (V72) int RefPositions {#184@288 #185@291} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 58: (V73) int RefPositions {#270@610 #271@613} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 59: (V74) int RefPositions {#1892@3766 #1893@3773} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 60: (V76) byref RefPositions {#42@30 #43@39 #46@45} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 61: (V83) long RefPositions {#641@1340 #642@1347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 62: (V86) ref RefPositions {#755@1554 #756@1561 #762@1581 #785@1645 #799@1673} physReg:NA Preferences=[x1] Interval 63: (V87) int RefPositions {#761@1574 #767@1599 #776@1625 #780@1637 #789@1655} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 64: (V88) byref RefPositions {#773@1614 #774@1623 #778@1629} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 65: (V91) int RefPositions {#904@1902 #907@1913 #916@1937 #921@1955 #923@1963} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 66: (V92) int RefPositions {#900@1892 #922@1955 #933@1981} physReg:NA Preferences=[x1] Interval 67: (V93) byref RefPositions {#913@1928 #914@1935 #918@1941} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 68: (V95) ref RefPositions {#986@2066 #987@2073 #993@2093 #1019@2167 #1033@2195} physReg:NA Preferences=[x1] Interval 69: (V96) int RefPositions {#992@2086 #1000@2115 #1009@2141 #1013@2153 #1023@2177} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 70: (V97) byref RefPositions {#1006@2130 #1007@2139 #1011@2145} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 71: (V99) int RefPositions {#2021@4096 #2024@4107 #2033@4133 #2038@4151 #2040@4159} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 72: (V100) byref RefPositions {#2030@4122 #2031@4131 #2035@4137} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 73: (V102) ref RefPositions {#2103@4262 #2104@4269 #2110@4289 #2133@4355 #2136@4363 #2150@4391} physReg:NA Preferences=[x1] Interval 74: (V103) int RefPositions {#2109@4282 #2115@4307 #2124@4333 #2128@4345 #2140@4373} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 75: (V104) byref RefPositions {#2121@4322 #2122@4331 #2126@4337} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 76: (V106) ref RefPositions {#2415@4864 #2416@4871 #2422@4891 #2445@4957 #2448@4965 #2462@4993} physReg:NA Preferences=[x1] Interval 77: (V107) int RefPositions {#2421@4884 #2427@4909 #2436@4935 #2440@4947 #2452@4975} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 78: (V108) byref RefPositions {#2433@4924 #2434@4933 #2438@4939} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 79: (V110) ref RefPositions {#1111@2350 #1113@2359 #1114@2361 #1120@2379 #1143@2445 #1146@2453 #1160@2481} physReg:NA Preferences=[x1] Interval 80: (V111) int RefPositions {#1119@2372 #1125@2397 #1134@2423 #1138@2435 #1150@2463} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 81: (V112) byref RefPositions {#1131@2412 #1132@2421 #1136@2427} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 82: (V114) ref RefPositions {#2199@4434 #2200@4441 #2201@4443 #2207@4461 #2230@4527 #2233@4535 #2247@4563} physReg:NA Preferences=[x1] Interval 83: (V115) int RefPositions {#2206@4454 #2212@4479 #2221@4505 #2225@4517 #2237@4545} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 84: (V116) byref RefPositions {#2218@4494 #2219@4503 #2223@4509} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 85: (V118) int RefPositions {#2307@4652 #2310@4663 #2319@4687 #2324@4705 #2326@4713} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 86: (V119) int RefPositions {#2303@4642 #2325@4705 #2336@4731} physReg:NA Preferences=[x1] Interval 87: (V120) byref RefPositions {#2316@4678 #2317@4685 #2321@4691} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 88: (V122) int RefPositions {#1217@2558 #1220@2569 #1229@2593 #1234@2611 #1236@2619} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 89: (V123) int RefPositions {#1213@2548 #1235@2611 #1246@2637} physReg:NA Preferences=[x1] Interval 90: (V124) byref RefPositions {#1226@2584 #1227@2591 #1231@2597} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 91: (V126) int RefPositions {#1336@2836 #1339@2847 #1348@2873 #1353@2891 #1355@2899} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 92: (V127) byref RefPositions {#1345@2862 #1346@2871 #1350@2877} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 93: (V129) int RefPositions {#1469@3074 #1472@3085 #1481@3111 #1486@3129 #1488@3137} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 94: (V130) byref RefPositions {#1478@3100 #1479@3109 #1483@3115} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 95: (V132) int RefPositions {#1557@3246 #1560@3257 #1569@3281 #1574@3299 #1576@3307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 96: (V133) int RefPositions {#1553@3236 #1575@3299 #1586@3325} physReg:NA Preferences=[x1] Interval 97: (V134) byref RefPositions {#1566@3272 #1567@3279 #1571@3285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 98: (V136) int RefPositions {#1643@3404 #1646@3415 #1655@3439 #1660@3457 #1662@3465} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 99: (V137) int RefPositions {#1639@3394 #1661@3457 #1672@3483} physReg:NA Preferences=[x1] Interval 100: (V138) byref RefPositions {#1652@3430 #1653@3437 #1657@3443} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 101: (V140) int RefPositions {#1712@3504 #1715@3515 #1724@3541 #1729@3559 #1731@3567} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 102: (V141) byref RefPositions {#1721@3530 #1722@3539 #1726@3545} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 103: (V143) byref (field) RefPositions {#511@1064 #653@1357 #699@1392 #705@1421 #974@2033 #1790@3593 #2091@4229 #2518@5009} physReg:NA Preferences=[x19-x28] Interval 104: (V144) int (field) RefPositions {#514@1068 #581@1271 #583@1283 #635@1327 #638@1337 #701@1396 #704@1405 #973@2019 #1787@3593 #2090@4215 #2513@5009} physReg:NA Preferences=[x19-x28] Interval 105: (V147) byref (field) RefPositions {#56@60 #66@83 #88@131} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 106: (V148) int (field) RefPositions {#61@68 #68@87 #90@135} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 107: (V149) byref (field) RefPositions {#75@104 #81@118 #89@132 #97@145} physReg:NA Preferences=[x0] Interval 108: (V150) int (field) RefPositions {#77@108 #83@122 #91@136 #101@149} physReg:NA Preferences=[x1] Interval 109: (V151) byref (field) RefPositions {#509@1056 #510@1063} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 110: (V155) byref (field) RefPositions {#67@84 #74@103 #80@117} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 111: (V156) int (field) RefPositions {#69@88 #76@107 #82@121} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 112: (V157) byref (field) RefPositions {#164@226 #165@231 #166@237} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 113: (V159) byref (field) RefPositions {#628@1308 #633@1321} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 114: (V160) int (field) RefPositions {#632@1318 #636@1327} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 115: (V161) byref (field) RefPositions {#634@1322 #649@1353} physReg:NA Preferences=[x0] Interval 116: (V163) byref (field) RefPositions {#693@1376 #698@1391} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 117: (V164) int (field) RefPositions {#697@1386 #700@1395} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 118: (V165) byref (field) RefPositions {#837@1694 #838@1699 #839@1705} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 119: (V167) long RefPositions {#49@48 #50@51} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 120: (V168) long RefPositions {#167@238 #168@241} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 121: (V169) long RefPositions {#840@1706 #841@1709} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 122: (V171) int RefPositions {#1884@3746 #1887@3755 #1889@3757 #1897@3781} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 123: (V172) int RefPositions {#2290@4602 #2291@4607 #2293@4617 #2302@4641 #2380@4770 #2381@4775} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 124: (V173) int RefPositions {#1629@3364 #1630@3369 #1638@3393} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 125: (V174) int RefPositions {#225@450 #228@459 #242@506 #243@511 #254@550 #255@555 #257@567} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 126: (V175) int RefPositions {#1541@3194 #1542@3199 #1544@3211 #1552@3235} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 127: (V176) int RefPositions {#1200@2514 #1203@2523 #1204@2525 #1212@2547 #1293@2698 #1294@2703 #1305@2742 #1306@2747 #1324@2793} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 128: (V177) int RefPositions {#881@1854 #882@1859 #894@1883} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 129: (V178) int RefPositions {#489@1010 #490@1021 #492@1021 #499@1037} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 130: (V179) int RefPositions {#59@64 #60@67 #172@251 #227@459 #236@483 #248@527 #274@619 #847@1725 #1202@2523 #1287@2675 #1299@2719 #1373@2939 #1535@3171 #1623@3341 #1777@3593 #1886@3755 #2284@4579 #2374@4747 #2503@5009} physReg:NA Preferences=[x19-x28] Interval 131: (V180) byref RefPositions {#54@56 #55@59 #163@225 #392@839 #836@1693 #1958@3935} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 132: (V181) int RefPositions {#996@2096 #999@2115 #1018@2161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 133: (V182) int RefPositions {#196@334 #197@339 #1863@3691} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 134: (V183) int RefPositions {#202@354 #203@359 #1902@3791} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 135: (V184) int RefPositions {#1088@2260 #1089@2265 #1960@3939} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 136: (V185) int RefPositions {#1094@2280 #1095@2285 #2388@4793} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 137: byref (specialPutArg) RefPositions {#7@8 #15@13} physReg:NA Preferences=[x0] RelatedInterval Interval 138: long (constant) RefPositions {#8@10 #10@11} physReg:NA Preferences=[x11] Interval 139: long RefPositions {#12@12 #17@13} physReg:NA Preferences=[x11] Interval 140: int (INTERNAL) RefPositions {#13@13 #18@13} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 141: byref RefPositions {#40@28 #41@29} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 142: int RefPositions {#44@40 #45@41} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 143: byref RefPositions {#47@46 #48@47} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 144: byref RefPositions {#52@54 #53@55} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 145: int RefPositions {#57@62 #58@63} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 146: ubyte RefPositions {#63@74 #64@77} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 147: bool RefPositions {#71@94 #72@97} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 148: int (constant) RefPositions {#84@124 #85@125} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 149: int (constant) RefPositions {#92@138 #93@139} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 150: byref RefPositions {#99@146 #115@161} physReg:NA Preferences=[x0] Interval 151: int RefPositions {#103@150 #117@161} physReg:NA Preferences=[x1] Interval 152: int RefPositions {#107@156 #119@161} physReg:NA Preferences=[x2] Interval 153: long (constant) RefPositions {#108@158 #110@159} physReg:NA Preferences=[x11] Interval 154: long RefPositions {#112@160 #121@161} physReg:NA Preferences=[x11] Interval 155: int (INTERNAL) RefPositions {#113@161 #122@161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 156: int RefPositions {#143@162 #144@163} physReg:NA Preferences=[x0] RelatedInterval Interval 157: int (constant) RefPositions {#148@176 #149@177} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 158: int (constant) RefPositions {#151@182 #152@183} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 159: int (constant) RefPositions {#156@200 #157@201} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 160: int RefPositions {#177@270 #178@271} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 161: ushort RefPositions {#182@286 #183@287} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 162: int RefPositions {#194@332 #195@333} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 163: int RefPositions {#200@352 #201@353} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 164: int (constant) RefPositions {#212@408 #214@409} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 165: int RefPositions {#217@422 #218@423} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 166: ushort RefPositions {#223@448 #224@449} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 167: int RefPositions {#231@472 #232@473} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 168: ushort RefPositions {#240@504 #241@505} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 169: int RefPositions {#246@524 #247@527} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 170: ushort RefPositions {#252@548 #253@549} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 171: int RefPositions {#260@582 #262@591} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 172: ushort RefPositions {#263@592 #264@595} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 173: int RefPositions {#268@608 #269@609} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 174: ushort RefPositions {#278@640 #279@643} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 175: int (constant) RefPositions {#281@652 #282@653} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 176: int (constant) RefPositions {#297@714 #300@717} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 177: int RefPositions {#301@718 #302@719} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 178: int (constant) RefPositions {#305@726 #306@727} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 179: ubyte RefPositions {#310@736 #311@739} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 180: byref RefPositions {#314@750 #315@751} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 181: int RefPositions {#318@756 #319@759} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 182: int RefPositions {#321@760 #323@763} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 183: int RefPositions {#327@782 #328@785} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 184: int RefPositions {#330@786 #331@789} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 185: int RefPositions {#333@790 #334@791} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 186: int RefPositions {#343@808 #360@821} physReg:NA Preferences=[x1] Interval 187: byref (specialPutArg) RefPositions {#347@812 #362@821} physReg:NA Preferences=[x0] RelatedInterval Interval 188: long (constant) RefPositions {#348@814 #350@815} physReg:NA Preferences=[x11] Interval 189: long RefPositions {#352@816 #364@821} physReg:NA Preferences=[x11] Interval 190: int (constant) RefPositions {#353@818 #355@819} physReg:NA Preferences=[x2] Interval 191: int RefPositions {#357@820 #366@821} physReg:NA Preferences=[x2] Interval 192: int (INTERNAL) RefPositions {#358@821 #367@821} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 193: ubyte RefPositions {#388@828 #389@831} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 194: byref (specialPutArg) RefPositions {#394@840 #412@855} physReg:NA Preferences=[x0] RelatedInterval Interval 195: long RefPositions {#395@842 #397@843} physReg:NA Preferences=[x1] Interval 196: long RefPositions {#399@844 #414@855} physReg:NA Preferences=[x1] Interval 197: long (constant) RefPositions {#400@848 #402@849} physReg:NA Preferences=[x11] Interval 198: long RefPositions {#404@850 #416@855} physReg:NA Preferences=[x11] Interval 199: int (constant) RefPositions {#405@852 #407@853} physReg:NA Preferences=[x2] Interval 200: int RefPositions {#409@854 #418@855} physReg:NA Preferences=[x2] Interval 201: int (INTERNAL) RefPositions {#410@855 #419@855} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 202: int RefPositions {#440@856 #441@857} physReg:NA Preferences=[x0] RelatedInterval Interval 203: ubyte RefPositions {#451@886 #452@889} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 204: int RefPositions {#460@934 #463@937} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 205: int RefPositions {#464@938 #465@939} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 206: int RefPositions {#471@962 #474@965} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 207: int RefPositions {#475@966 #476@967} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 208: int RefPositions {#487@1008 #488@1009} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 209: int RefPositions {#494@1022 #495@1023} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 210: int RefPositions {#501@1038 #502@1039} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 211: long RefPositions {#507@1054 #508@1055} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 212: int (constant) RefPositions {#512@1066 #513@1067} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 213: int (constant) RefPositions {#515@1072 #516@1073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 214: ref RefPositions {#519@1082 #520@1085} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 215: int RefPositions {#521@1086 #522@1099} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 216: ref RefPositions {#526@1112 #527@1113} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 217: int RefPositions {#532@1134 #533@1135} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 218: int RefPositions {#538@1154 #539@1155} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 219: int RefPositions {#559@1206 #560@1207} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 220: int RefPositions {#566@1224 #567@1225} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 221: int RefPositions {#577@1262 #578@1263} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 222: int RefPositions {#584@1284 #585@1285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 223: long RefPositions {#586@1286 #588@1287} physReg:NA Preferences=[x0] Interval 224: long RefPositions {#590@1288 #598@1293} physReg:NA Preferences=[x0] Interval 225: long (constant) RefPositions {#591@1290 #593@1291} physReg:NA Preferences=[x11] Interval 226: long RefPositions {#595@1292 #600@1293} physReg:NA Preferences=[x11] Interval 227: int (INTERNAL) RefPositions {#596@1293 #601@1293} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 228: ref RefPositions {#622@1294 #623@1295} physReg:NA Preferences=[x0] RelatedInterval Interval 229: byref RefPositions {#626@1306 #627@1307} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 230: int RefPositions {#630@1316 #631@1317} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 231: long RefPositions {#639@1338 #640@1339} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 232: long RefPositions {#643@1348 #645@1349} physReg:NA Preferences=[x2] Interval 233: long RefPositions {#647@1350 #663@1363} physReg:NA Preferences=[x2] Interval 234: byref RefPositions {#651@1354 #665@1363} physReg:NA Preferences=[x0] Interval 235: byref RefPositions {#655@1358 #667@1363} physReg:NA Preferences=[x1] Interval 236: long (constant) RefPositions {#656@1360 #658@1361} physReg:NA Preferences=[x11] Interval 237: long RefPositions {#660@1362 #669@1363} physReg:NA Preferences=[x11] Interval 238: int (INTERNAL) RefPositions {#661@1363 #670@1363} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 239: byref RefPositions {#691@1374 #692@1375} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 240: int RefPositions {#695@1384 #696@1385} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 241: int RefPositions {#709@1432 #711@1433} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 242: int RefPositions {#714@1446 #715@1447} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 243: int RefPositions {#718@1458 #720@1459} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 244: byref RefPositions {#722@1466 #723@1477} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 245: int RefPositions {#725@1478 #726@1479} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 246: int RefPositions {#731@1490 #732@1491} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 247: bool RefPositions {#744@1512 #745@1525} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 248: int RefPositions {#749@1538 #750@1541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 249: ref RefPositions {#753@1552 #754@1553} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 250: int RefPositions {#759@1572 #760@1573} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 251: int RefPositions {#763@1582 #766@1599} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 252: int RefPositions {#765@1594 #768@1599} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 253: byref RefPositions {#771@1612 #772@1613} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 254: int RefPositions {#775@1624 #777@1625} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 255: byref RefPositions {#779@1630 #782@1639} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 256: long RefPositions {#781@1638 #783@1639} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 257: byref RefPositions {#784@1640 #787@1647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 258: ushort RefPositions {#786@1646 #788@1647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 259: int RefPositions {#790@1656 #792@1661} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 260: byref (specialPutArg) RefPositions {#797@1670 #809@1679} physReg:NA Preferences=[x0] RelatedInterval Interval 261: ref RefPositions {#801@1674 #811@1679} physReg:NA Preferences=[x1] Interval 262: long (constant) RefPositions {#802@1676 #804@1677} physReg:NA Preferences=[x11] Interval 263: long RefPositions {#806@1678 #813@1679} physReg:NA Preferences=[x11] Interval 264: int (INTERNAL) RefPositions {#807@1679 #814@1679} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 265: int RefPositions {#852@1744 #853@1745} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 266: ushort RefPositions {#857@1760 #858@1761} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 267: int (constant) RefPositions {#868@1810 #871@1815} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 268: ubyte RefPositions {#879@1852 #880@1853} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 269: int (constant) RefPositions {#884@1864 #885@1865} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 270: long RefPositions {#891@1878 #892@1879} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 271: int RefPositions {#898@1890 #899@1891} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 272: int RefPositions {#902@1900 #903@1901} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 273: int RefPositions {#906@1912 #908@1913} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 274: byref RefPositions {#911@1926 #912@1927} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 275: int RefPositions {#915@1936 #917@1937} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 276: byref RefPositions {#919@1942 #920@1955} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 277: int RefPositions {#924@1964 #926@1969} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 278: byref (specialPutArg) RefPositions {#931@1978 #943@1987} physReg:NA Preferences=[x0] RelatedInterval Interval 279: int RefPositions {#935@1982 #945@1987} physReg:NA Preferences=[x1] Interval 280: long (constant) RefPositions {#936@1984 #938@1985} physReg:NA Preferences=[x11] Interval 281: long RefPositions {#940@1986 #947@1987} physReg:NA Preferences=[x11] Interval 282: int (INTERNAL) RefPositions {#941@1987 #948@1987} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 283: int RefPositions {#976@2034 #977@2037} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 284: int RefPositions {#978@2038 #979@2051} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 285: ref RefPositions {#984@2064 #985@2065} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 286: int RefPositions {#990@2084 #991@2085} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 287: int RefPositions {#994@2094 #995@2095} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 288: int RefPositions {#998@2110 #1001@2115} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 289: byref RefPositions {#1004@2128 #1005@2129} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 290: int RefPositions {#1008@2140 #1010@2141} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 291: byref RefPositions {#1012@2146 #1015@2155} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 292: long RefPositions {#1014@2154 #1016@2155} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 293: byref RefPositions {#1017@2156 #1021@2169} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 294: ushort RefPositions {#1020@2168 #1022@2169} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 295: int RefPositions {#1024@2178 #1026@2183} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 296: byref (specialPutArg) RefPositions {#1031@2192 #1043@2201} physReg:NA Preferences=[x0] RelatedInterval Interval 297: ref RefPositions {#1035@2196 #1045@2201} physReg:NA Preferences=[x1] Interval 298: long (constant) RefPositions {#1036@2198 #1038@2199} physReg:NA Preferences=[x11] Interval 299: long RefPositions {#1040@2200 #1047@2201} physReg:NA Preferences=[x11] Interval 300: int (INTERNAL) RefPositions {#1041@2201 #1048@2201} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 301: int RefPositions {#1070@2212 #1071@2213} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 302: int RefPositions {#1075@2224 #1076@2225} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 303: int RefPositions {#1079@2234 #1080@2235} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 304: int RefPositions {#1086@2258 #1087@2259} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 305: int RefPositions {#1092@2278 #1093@2279} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 306: int (constant) RefPositions {#1104@2334 #1106@2335} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 307: ref RefPositions {#1109@2348 #1110@2349} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 308: int RefPositions {#1117@2370 #1118@2371} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 309: int RefPositions {#1121@2380 #1124@2397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 310: int RefPositions {#1123@2392 #1126@2397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 311: byref RefPositions {#1129@2410 #1130@2411} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 312: int RefPositions {#1133@2422 #1135@2423} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 313: byref RefPositions {#1137@2428 #1140@2437} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 314: long RefPositions {#1139@2436 #1141@2437} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 315: byref RefPositions {#1142@2438 #1148@2455} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 316: int RefPositions {#1144@2446 #1145@2447} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 317: ushort RefPositions {#1147@2454 #1149@2455} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 318: int RefPositions {#1151@2464 #1153@2469} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 319: byref (specialPutArg) RefPositions {#1158@2478 #1170@2487} physReg:NA Preferences=[x0] RelatedInterval Interval 320: ref RefPositions {#1162@2482 #1172@2487} physReg:NA Preferences=[x1] Interval 321: long (constant) RefPositions {#1163@2484 #1165@2485} physReg:NA Preferences=[x11] Interval 322: long RefPositions {#1167@2486 #1174@2487} physReg:NA Preferences=[x11] Interval 323: int (INTERNAL) RefPositions {#1168@2487 #1175@2487} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 324: ushort RefPositions {#1198@2512 #1199@2513} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 325: int RefPositions {#1209@2542 #1210@2543} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 326: int RefPositions {#1215@2556 #1216@2557} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 327: int RefPositions {#1219@2568 #1221@2569} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 328: byref RefPositions {#1224@2582 #1225@2583} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 329: int RefPositions {#1228@2592 #1230@2593} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 330: byref RefPositions {#1232@2598 #1233@2611} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 331: int RefPositions {#1237@2620 #1239@2625} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 332: byref (specialPutArg) RefPositions {#1244@2634 #1256@2643} physReg:NA Preferences=[x0] RelatedInterval Interval 333: int RefPositions {#1248@2638 #1258@2643} physReg:NA Preferences=[x1] Interval 334: long (constant) RefPositions {#1249@2640 #1251@2641} physReg:NA Preferences=[x11] Interval 335: long RefPositions {#1253@2642 #1260@2643} physReg:NA Preferences=[x11] Interval 336: int (INTERNAL) RefPositions {#1254@2643 #1261@2643} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 337: ushort RefPositions {#1291@2696 #1292@2697} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 338: int RefPositions {#1297@2716 #1298@2719} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 339: ushort RefPositions {#1303@2740 #1304@2741} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 340: int RefPositions {#1307@2748 #1315@2771} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 341: int RefPositions {#1309@2756 #1311@2765} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 342: ushort RefPositions {#1312@2766 #1313@2769} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 343: int RefPositions {#1314@2770 #1316@2771} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 344: int RefPositions {#1317@2772 #1318@2773} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 345: int (constant) RefPositions {#1320@2782 #1321@2783} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 346: int RefPositions {#1327@2808 #1329@2817} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 347: ushort RefPositions {#1330@2818 #1331@2821} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 348: int RefPositions {#1334@2834 #1335@2835} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 349: int RefPositions {#1338@2846 #1340@2847} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 350: byref RefPositions {#1343@2860 #1344@2861} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 351: int RefPositions {#1347@2872 #1349@2873} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 352: byref RefPositions {#1351@2878 #1352@2891} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 353: int RefPositions {#1356@2900 #1358@2905} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 354: int RefPositions {#1362@2916 #1363@2917} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 355: int RefPositions {#1367@2928 #1368@2929} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 356: ushort RefPositions {#1377@2960 #1378@2963} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 357: int (constant) RefPositions {#1382@2984 #1383@2985} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 358: ubyte RefPositions {#1387@2994 #1388@2997} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 359: int RefPositions {#1391@3008 #1392@3011} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 360: int RefPositions {#1394@3012 #1395@3013} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 361: int RefPositions {#1403@3030 #1431@3055} physReg:NA Preferences=[x5] Interval 362: byref (specialPutArg) RefPositions {#1407@3034 #1433@3055} physReg:NA Preferences=[x0] RelatedInterval Interval 363: ref (specialPutArg) RefPositions {#1411@3038 #1435@3055} physReg:NA Preferences=[x1] RelatedInterval Interval 364: int RefPositions {#1415@3042 #1437@3055} physReg:NA Preferences=[x2] Interval 365: int RefPositions {#1419@3046 #1439@3055} physReg:NA Preferences=[x3] Interval 366: int RefPositions {#1423@3050 #1441@3055} physReg:NA Preferences=[x4] Interval 367: long (constant) RefPositions {#1424@3052 #1426@3053} physReg:NA Preferences=[x11] Interval 368: long RefPositions {#1428@3054 #1443@3055} physReg:NA Preferences=[x11] Interval 369: int (INTERNAL) RefPositions {#1429@3055 #1444@3055} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 370: int RefPositions {#1467@3072 #1468@3073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 371: int RefPositions {#1471@3084 #1473@3085} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 372: byref RefPositions {#1476@3098 #1477@3099} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 373: int RefPositions {#1480@3110 #1482@3111} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 374: byref RefPositions {#1484@3116 #1485@3129} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 375: int RefPositions {#1489@3138 #1491@3143} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 376: byref (specialPutArg) RefPositions {#1496@3152 #1508@3161} physReg:NA Preferences=[x0] RelatedInterval Interval 377: int RefPositions {#1500@3156 #1510@3161} physReg:NA Preferences=[x1] Interval 378: long (constant) RefPositions {#1501@3158 #1503@3159} physReg:NA Preferences=[x11] Interval 379: long RefPositions {#1505@3160 #1512@3161} physReg:NA Preferences=[x11] Interval 380: int (INTERNAL) RefPositions {#1506@3161 #1513@3161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 381: ushort RefPositions {#1539@3192 #1540@3193} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 382: int RefPositions {#1549@3230 #1550@3231} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 383: int RefPositions {#1555@3244 #1556@3245} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 384: int RefPositions {#1559@3256 #1561@3257} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 385: byref RefPositions {#1564@3270 #1565@3271} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 386: int RefPositions {#1568@3280 #1570@3281} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 387: byref RefPositions {#1572@3286 #1573@3299} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 388: int RefPositions {#1577@3308 #1579@3313} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 389: byref (specialPutArg) RefPositions {#1584@3322 #1596@3331} physReg:NA Preferences=[x0] RelatedInterval Interval 390: int RefPositions {#1588@3326 #1598@3331} physReg:NA Preferences=[x1] Interval 391: long (constant) RefPositions {#1589@3328 #1591@3329} physReg:NA Preferences=[x11] Interval 392: long RefPositions {#1593@3330 #1600@3331} physReg:NA Preferences=[x11] Interval 393: int (INTERNAL) RefPositions {#1594@3331 #1601@3331} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 394: ushort RefPositions {#1627@3362 #1628@3363} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 395: int RefPositions {#1635@3388 #1636@3389} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 396: int RefPositions {#1641@3402 #1642@3403} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 397: int RefPositions {#1645@3414 #1647@3415} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 398: byref RefPositions {#1650@3428 #1651@3429} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 399: int RefPositions {#1654@3438 #1656@3439} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 400: byref RefPositions {#1658@3444 #1659@3457} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 401: int RefPositions {#1663@3466 #1665@3471} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 402: byref (specialPutArg) RefPositions {#1670@3480 #1682@3489} physReg:NA Preferences=[x0] RelatedInterval Interval 403: int RefPositions {#1674@3484 #1684@3489} physReg:NA Preferences=[x1] Interval 404: long (constant) RefPositions {#1675@3486 #1677@3487} physReg:NA Preferences=[x11] Interval 405: long RefPositions {#1679@3488 #1686@3489} physReg:NA Preferences=[x11] Interval 406: int (INTERNAL) RefPositions {#1680@3489 #1687@3489} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 407: int RefPositions {#1710@3502 #1711@3503} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 408: int RefPositions {#1714@3514 #1716@3515} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 409: byref RefPositions {#1719@3528 #1720@3529} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 410: int RefPositions {#1723@3540 #1725@3541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 411: byref RefPositions {#1727@3546 #1728@3559} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 412: int RefPositions {#1732@3568 #1734@3573} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 413: byref (specialPutArg) RefPositions {#1739@3582 #1751@3591} physReg:NA Preferences=[x0] RelatedInterval Interval 414: int RefPositions {#1743@3586 #1753@3591} physReg:NA Preferences=[x1] Interval 415: long (constant) RefPositions {#1744@3588 #1746@3589} physReg:NA Preferences=[x11] Interval 416: long RefPositions {#1748@3590 #1755@3591} physReg:NA Preferences=[x11] Interval 417: int (INTERNAL) RefPositions {#1749@3591 #1756@3591} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 418: bool RefPositions {#1795@3608 #1796@3621} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 419: int RefPositions {#1800@3634 #1801@3637} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 420: int RefPositions {#1802@3638 #1807@3649} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 421: int RefPositions {#1804@3644 #1805@3647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 422: int RefPositions {#1806@3648 #1808@3649} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 423: int RefPositions {#1809@3650 #1810@3651} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 424: ref RefPositions {#1813@3664 #1815@3665} physReg:NA Preferences=[x2] Interval 425: ref RefPositions {#1817@3666 #1834@3679} physReg:NA Preferences=[x2] Interval 426: byref RefPositions {#1821@3670 #1836@3679} physReg:NA Preferences=[x0] Interval 427: long (constant) RefPositions {#1822@3672 #1824@3673} physReg:NA Preferences=[x11] Interval 428: long RefPositions {#1826@3674 #1838@3679} physReg:NA Preferences=[x11] Interval 429: int (constant) RefPositions {#1827@3676 #1829@3677} physReg:NA Preferences=[x1] Interval 430: int RefPositions {#1831@3678 #1840@3679} physReg:NA Preferences=[x1] Interval 431: int (INTERNAL) RefPositions {#1832@3679 #1841@3679} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 432: long RefPositions {#1864@3692 #1867@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 433: long RefPositions {#1865@3694 #1868@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 434: int (INTERNAL) RefPositions {#1866@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 435: int RefPositions {#1871@3706 #1872@3707} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 436: int RefPositions {#1876@3718 #1877@3719} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 437: ushort RefPositions {#1882@3744 #1883@3745} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 438: int RefPositions {#1894@3774 #1895@3775} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 439: long RefPositions {#1903@3792 #1906@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 440: long RefPositions {#1904@3794 #1907@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 441: int (INTERNAL) RefPositions {#1905@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 442: int (constant) RefPositions {#1909@3804 #1911@3805} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 443: int RefPositions {#1917@3826 #1918@3827} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 444: int RefPositions {#1938@3910 #1939@3911} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 445: int (constant) RefPositions {#1945@3918 #1946@3919} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 446: int (constant) RefPositions {#1951@3932 #1952@3933} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 447: long RefPositions {#1961@3940 #1964@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 448: long RefPositions {#1962@3942 #1965@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 449: int (INTERNAL) RefPositions {#1963@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 450: int RefPositions {#1970@3966 #1971@3967} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 451: int (constant) RefPositions {#1978@3992 #1979@3993} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 452: int RefPositions {#1983@4000 #1984@4001} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 453: ubyte RefPositions {#1988@4010 #1989@4013} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 454: int (constant) RefPositions {#1996@4040 #1997@4041} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 455: long RefPositions {#2003@4058 #2004@4059} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 456: ubyte RefPositions {#2007@4064 #2008@4065} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 457: int RefPositions {#2012@4072 #2013@4073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 458: int RefPositions {#2019@4094 #2020@4095} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 459: int RefPositions {#2023@4106 #2025@4107} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 460: byref RefPositions {#2028@4120 #2029@4121} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 461: int RefPositions {#2032@4132 #2034@4133} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 462: byref RefPositions {#2036@4138 #2037@4151} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 463: int RefPositions {#2041@4160 #2043@4165} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 464: byref (specialPutArg) RefPositions {#2048@4174 #2060@4183} physReg:NA Preferences=[x0] RelatedInterval Interval 465: int RefPositions {#2052@4178 #2062@4183} physReg:NA Preferences=[x1] Interval 466: long (constant) RefPositions {#2053@4180 #2055@4181} physReg:NA Preferences=[x11] Interval 467: long RefPositions {#2057@4182 #2064@4183} physReg:NA Preferences=[x11] Interval 468: int (INTERNAL) RefPositions {#2058@4183 #2065@4183} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 469: int RefPositions {#2093@4230 #2094@4233} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 470: int RefPositions {#2095@4234 #2096@4247} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 471: ref RefPositions {#2101@4260 #2102@4261} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 472: int RefPositions {#2107@4280 #2108@4281} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 473: int RefPositions {#2111@4290 #2114@4307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 474: int RefPositions {#2113@4302 #2116@4307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 475: byref RefPositions {#2119@4320 #2120@4321} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 476: int RefPositions {#2123@4332 #2125@4333} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 477: byref RefPositions {#2127@4338 #2130@4347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 478: long RefPositions {#2129@4346 #2131@4347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 479: byref RefPositions {#2132@4348 #2138@4365} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 480: int RefPositions {#2134@4356 #2135@4357} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 481: ushort RefPositions {#2137@4364 #2139@4365} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 482: int RefPositions {#2141@4374 #2143@4379} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 483: byref (specialPutArg) RefPositions {#2148@4388 #2160@4397} physReg:NA Preferences=[x0] RelatedInterval Interval 484: ref RefPositions {#2152@4392 #2162@4397} physReg:NA Preferences=[x1] Interval 485: long (constant) RefPositions {#2153@4394 #2155@4395} physReg:NA Preferences=[x11] Interval 486: long RefPositions {#2157@4396 #2164@4397} physReg:NA Preferences=[x11] Interval 487: int (INTERNAL) RefPositions {#2158@4397 #2165@4397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 488: int RefPositions {#2187@4408 #2188@4409} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 489: int RefPositions {#2192@4420 #2193@4421} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 490: ref RefPositions {#2197@4432 #2198@4433} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 491: int RefPositions {#2204@4452 #2205@4453} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 492: int RefPositions {#2208@4462 #2211@4479} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 493: int RefPositions {#2210@4474 #2213@4479} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 494: byref RefPositions {#2216@4492 #2217@4493} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 495: int RefPositions {#2220@4504 #2222@4505} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 496: byref RefPositions {#2224@4510 #2227@4519} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 497: long RefPositions {#2226@4518 #2228@4519} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 498: byref RefPositions {#2229@4520 #2235@4537} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 499: int RefPositions {#2231@4528 #2232@4529} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 500: ushort RefPositions {#2234@4536 #2236@4537} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 501: int RefPositions {#2238@4546 #2240@4551} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 502: byref (specialPutArg) RefPositions {#2245@4560 #2257@4569} physReg:NA Preferences=[x0] RelatedInterval Interval 503: ref RefPositions {#2249@4564 #2259@4569} physReg:NA Preferences=[x1] Interval 504: long (constant) RefPositions {#2250@4566 #2252@4567} physReg:NA Preferences=[x11] Interval 505: long RefPositions {#2254@4568 #2261@4569} physReg:NA Preferences=[x11] Interval 506: int (INTERNAL) RefPositions {#2255@4569 #2262@4569} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 507: ushort RefPositions {#2288@4600 #2289@4601} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 508: int RefPositions {#2299@4636 #2300@4637} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 509: int RefPositions {#2305@4650 #2306@4651} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 510: int RefPositions {#2309@4662 #2311@4663} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 511: byref RefPositions {#2314@4676 #2315@4677} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 512: int RefPositions {#2318@4686 #2320@4687} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 513: byref RefPositions {#2322@4692 #2323@4705} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 514: int RefPositions {#2327@4714 #2329@4719} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 515: byref (specialPutArg) RefPositions {#2334@4728 #2346@4737} physReg:NA Preferences=[x0] RelatedInterval Interval 516: int RefPositions {#2338@4732 #2348@4737} physReg:NA Preferences=[x1] Interval 517: long (constant) RefPositions {#2339@4734 #2341@4735} physReg:NA Preferences=[x11] Interval 518: long RefPositions {#2343@4736 #2350@4737} physReg:NA Preferences=[x11] Interval 519: int (INTERNAL) RefPositions {#2344@4737 #2351@4737} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 520: ushort RefPositions {#2378@4768 #2379@4769} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 521: int RefPositions {#2384@4786 #2385@4787} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 522: long RefPositions {#2389@4794 #2392@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 523: long RefPositions {#2390@4796 #2393@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 524: int (INTERNAL) RefPositions {#2391@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 525: int RefPositions {#2397@4808 #2398@4811} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 526: int RefPositions {#2400@4812 #2401@4815} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 527: ubyte RefPositions {#2406@4842 #2409@4849} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 528: ref RefPositions {#2413@4862 #2414@4863} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 529: int RefPositions {#2419@4882 #2420@4883} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 530: int RefPositions {#2423@4892 #2426@4909} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 531: int RefPositions {#2425@4904 #2428@4909} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 532: byref RefPositions {#2431@4922 #2432@4923} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 533: int RefPositions {#2435@4934 #2437@4935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 534: byref RefPositions {#2439@4940 #2442@4949} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 535: long RefPositions {#2441@4948 #2443@4949} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 536: byref RefPositions {#2444@4950 #2450@4967} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 537: int RefPositions {#2446@4958 #2447@4959} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 538: ushort RefPositions {#2449@4966 #2451@4967} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 539: int RefPositions {#2453@4976 #2455@4981} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 540: byref (specialPutArg) RefPositions {#2460@4990 #2472@4999} physReg:NA Preferences=[x0] RelatedInterval Interval 541: ref RefPositions {#2464@4994 #2474@4999} physReg:NA Preferences=[x1] Interval 542: long (constant) RefPositions {#2465@4996 #2467@4997} physReg:NA Preferences=[x11] Interval 543: long RefPositions {#2469@4998 #2476@4999} physReg:NA Preferences=[x11] Interval 544: int (INTERNAL) RefPositions {#2470@4999 #2477@4999} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 545: int (constant) RefPositions {#2498@5006 #2499@5007} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 546: long (constant) RefPositions {#2523@5014 #2525@5015} physReg:NA Preferences=[x11] Interval 547: long RefPositions {#2527@5016 #2530@5017} physReg:NA Preferences=[x11] Interval 548: int (INTERNAL) RefPositions {#2528@5017 #2531@5017} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 549: long (constant) RefPositions {#2552@5022 #2553@5023} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 550: long RefPositions {#2554@5024 #2555@5025} physReg:NA Preferences=[x0-xip0 x19-x28] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) byref RefPositions {#0@0 #758@1571 #764@1593 #770@1611 #791@1661 #795@1669 #901@1899 #905@1911 #910@1925 #925@1969 #929@1977 #989@2083 #997@2109 #1003@2127 #1025@2183 #1029@2191 #1116@2369 #1122@2391 #1128@2409 #1152@2469 #1156@2477 #1214@2555 #1218@2567 #1223@2581 #1238@2625 #1242@2633 #1333@2833 #1337@2845 #1342@2859 #1357@2905 #1405@3033 #1466@3071 #1470@3083 #1475@3097 #1490@3143 #1494@3151 #1554@3243 #1558@3255 #1563@3269 #1578@3313 #1582@3321 #1640@3401 #1644@3413 #1649@3427 #1664@3471 #1668@3479 #1709@3501 #1713@3513 #1718@3527 #1733@3573 #1737@3581 #1803@3643 #1819@3669 #2018@4093 #2022@4105 #2027@4119 #2042@4165 #2046@4173 #2106@4279 #2112@4301 #2118@4319 #2142@4379 #2146@4387 #2203@4451 #2209@4473 #2215@4491 #2239@4551 #2243@4559 #2304@4649 #2308@4661 #2313@4675 #2328@4719 #2332@4727 #2418@4881 #2424@4903 #2430@4921 #2454@4981 #2458@4989 #2502@5009} physReg:x0 Preferences=[x19-x28] Interval 1: (V01) byref RefPositions {#2@0 #5@7 #39@27 #70@93 #313@749 #326@781 #345@811 #450@885 #454@903 #456@915 #486@1007 #743@1511 #748@1537 #1390@3007 #1794@3607 #1799@3633 #2516@5009} physReg:x1 Preferences=[x19-x28] Interval 2: (V03) ref RefPositions {#1@0 #518@1081 #525@1111 #752@1551 #983@2063 #1108@2347 #1409@3037 #1812@3663 #2100@4259 #2196@4431 #2412@4861 #2515@5009} physReg:x4 Preferences=[x19-x28] Interval 3: (V04) int RefPositions {#147@172 #289@679 #329@785 #337@799 #1778@3593 #1870@3705 #1873@3708 #1913@3815 #1916@3825 #1919@3828 #1920@3833 #1926@3853 #1929@3873 #1935@3897 #1949@3927 #2408@4849 #2504@5009} physReg:NA Preferences=[x19-x28] Interval 4: (V05) int RefPositions {#150@178 #287@669 #290@680 #295@701 #332@789 #458@933 #462@937 #469@961 #473@965 #482@989 #491@1021 #493@1021 #500@1037 #1393@3011 #1781@3593 #1923@3843 #1924@3847 #1927@3854 #1930@3873 #2407@4849 #2507@5009} physReg:NA Preferences=[x19-x28] Interval 5: (V06) int RefPositions {#153@184 #459@933 #461@937 #468@946 #562@1223 #564@1223 #1785@3593 #1910@3805 #1914@3816 #1974@3975 #2511@5009} physReg:NA Preferences=[x19-x28] Interval 6: (V07) int RefPositions {#154@190 #470@961 #472@965 #479@974 #1789@3593 #1921@3834 #1992@4023 #2403@4825 #2517@5009} physReg:NA Preferences=[x19-x28] Interval 7: (V08) int RefPositions {#483@990 #498@1030 #544@1167 #970@2007 #980@2051 #1074@2223 #1077@2226 #1782@3593 #1973@3975 #1991@4023 #2087@4203 #2097@4247 #2191@4419 #2194@4422 #2396@4807 #2508@5009} physReg:NA Preferences=[x19-x28] Interval 8: (V09) int RefPositions {#155@196 #265@599 #283@654 #324@771 #480@981 #1284@2665 #1359@2907 #1464@3062 #1788@3593 #2514@5009} physReg:NA Preferences=[x19-x28] Interval 9: (V10) int RefPositions {#158@202 #292@689 #294@701 #1932@3885 #1934@3897 #1941@3913 #1950@3928 #1956@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: (V11) int RefPositions {#38@20 #299@717 #448@877 #1937@3909 #1940@3912 #1943@3913 #1953@3934 #1957@3935} physReg:NA Preferences=[x19-x28] Interval 11: (V12) int RefPositions {#159@208 #307@728 #523@1099 #969@2007 #1786@3593 #1942@3913 #1947@3920 #2086@4203 #2512@5009} physReg:NA Preferences=[x19-x28] Interval 12: (V13) int RefPositions {#160@214 #216@421 #219@424 #298@717 #303@720 #320@759 #1875@3717 #1878@3720 #1955@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 13: (V14) int RefPositions {#484@996 #503@1040 #546@1175 #554@1197 #866@1793 #876@1841 #1078@2233 #1081@2236 #1783@3593 #1967@3953 #1969@3965 #1972@3968 #2509@5009} physReg:NA Preferences=[x19-x28] Interval 14: (V15) int RefPositions {#145@164 #161@219 #444@865 #447@876 #505@1047 #1797@3621 #2519@5009} physReg:NA Preferences=[x19-x28] Interval 15: (V16) int RefPositions {#162@220 #171@251 #174@261 #179@272 #222@447 #226@459 #230@471 #233@474 #235@483 #239@503 #245@523 #251@547 #259@581 #267@607 #272@614 #273@619 #277@639 #284@655 #442@858 #443@865 #446@875 #506@1048 #746@1525 #846@1725 #849@1735 #854@1746 #1197@2511 #1201@2523 #1206@2533 #1211@2544 #1286@2675 #1290@2695 #1296@2715 #1302@2739 #1308@2755 #1326@2807 #1366@2927 #1371@2934 #1372@2939 #1376@2959 #1534@3171 #1538@3191 #1546@3221 #1551@3232 #1622@3341 #1626@3361 #1632@3379 #1637@3390 #1776@3593 #1881@3743 #1885@3755 #1891@3765 #1896@3776 #2283@4579 #2287@4599 #2296@4627 #2301@4638 #2373@4747 #2377@4767 #2383@4785 #2386@4788 #2501@5009} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 16: (V17) long RefPositions {#51@52 #62@73 #309@735 #387@827 #843@1715 #1386@2993 #1791@3593 #2520@5009} physReg:NA Preferences=[x19-x28] Interval 17: (V18) int RefPositions {#186@292 #187@297 #189@307 #191@319 #193@331 #199@351 #205@371 #208@385 #210@397 #213@409 #861@1766 #862@1771 #864@1781 #869@1815 #870@1815 #873@1827 #1083@2245 #1085@2257 #1091@2277 #1097@2297 #1100@2311 #1102@2323 #1105@2335 #1354@2891 #1417@3045 #1487@3129 #1498@3155 #1730@3559 #1741@3585 #1888@3757 #1898@3781 #1899@3785 #1985@4002 #2014@4074 #2016@4083 #2039@4151 #2050@4177 #2294@4617 #2371@4739 #2394@4799} physReg:NA Preferences=[x19-x28] Interval 18: (V20) int RefPositions {#517@1074 #576@1261 #579@1264 #580@1271 #703@1405 #706@1421 #972@2019 #975@2033 #981@2051 #1069@2211 #1072@2214 #1779@3593 #2089@4215 #2092@4229 #2098@4247 #2186@4407 #2189@4410 #2505@5009} physReg:NA Preferences=[x19-x28] Interval 19: (V21) int RefPositions {#835@1688 #1792@3593 #2399@4811 #2410@4851 #2500@5008 #2521@5009} physReg:NA Preferences=[x19-x28] Interval 20: (V22) long RefPositions {#169@242 #180@285 #221@447 #238@503 #250@547 #261@591 #276@639 #285@655 #1880@3743 #1954@3935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 21: (V26) ref RefPositions {#528@1114 #531@1133 #537@1153 #717@1457 #721@1465 #739@1503} physReg:NA Preferences=[x19-x28] Interval 22: (V27) int RefPositions {#529@1120 #710@1433 #713@1445 #716@1448 #719@1459 #724@1477 #737@1503} physReg:NA Preferences=[x19-x28] Interval 23: (V28) int RefPositions {#530@1126 #540@1156 #542@1163 #707@1421 #729@1489 #733@1492 #735@1499 #736@1503} physReg:NA Preferences=[x19-x28] Interval 24: (V29) int RefPositions {#534@1136 #535@1143 #708@1431 #740@1503} physReg:NA Preferences=[x19-x28] Interval 25: (V30) int RefPositions {#543@1164 #572@1239 #574@1251 #727@1480 #730@1489 #738@1503} physReg:NA Preferences=[x19-x28] Interval 26: (V31) int RefPositions {#561@1208 #563@1223 #565@1223} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 27: (V32) int RefPositions {#570@1232 #571@1239 #734@1499 #741@1503} physReg:NA Preferences=[x19-x28] Interval 28: (V33) ref RefPositions {#624@1296 #625@1305 #629@1315 #690@1373 #694@1383} physReg:NA Preferences=[x19-x28] Interval 29: (V34) long RefPositions {#842@1710 #855@1759 #1196@2511 #1289@2695 #1301@2739 #1310@2765 #1328@2817 #1375@2959 #1537@3191 #1625@3361 #1780@3593 #2286@4599 #2376@4767 #2506@5009} physReg:NA Preferences=[x19-x28] Interval 30: (V36) long RefPositions {#844@1716 #878@1851 #888@1871 #893@1880 #1784@3593 #1987@4009 #2000@4049 #2005@4060 #2405@4841 #2510@5009} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 31: (V37) int RefPositions {#1282@2652 #1322@2784 #1401@3029} physReg:NA Preferences=[x5] Interval 32: (V38) int RefPositions {#1283@2658 #1361@2915 #1364@2918 #1380@2975 #1384@2986 #1421@3049} physReg:NA Preferences=[x4] Interval 33: (V43) int RefPositions {#78@112 #86@126 #94@140 #105@155} physReg:NA Preferences=[x2] Interval 34: (V44) int RefPositions {#466@940 #467@945} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 35: (V45) int RefPositions {#477@968 #478@973} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 36: (V46) int RefPositions {#496@1024 #497@1029} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 37: (V49) int RefPositions {#850@1736 #851@1743 #856@1759} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 38: (V50) int RefPositions {#859@1762 #860@1765} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 39: (V51) int RefPositions {#1207@2534 #1208@2541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 40: (V52) int RefPositions {#1547@3222 #1548@3229} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 41: (V53) int RefPositions {#1633@3380 #1634@3387} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 42: (V54) int RefPositions {#1369@2930 #1370@2933} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 43: (V55) int RefPositions {#1396@3014 #1398@3022 #1413@3041} physReg:NA Preferences=[x2] Interval 44: (V56) long RefPositions {#2001@4050 #2002@4057 #2006@4063} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 45: (V57) int RefPositions {#1994@4034 #1998@4042 #2009@4066 #2011@4071} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 46: (V58) int RefPositions {#1976@3986 #1980@3994 #1982@3999} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 47: (V59) int RefPositions {#2297@4628 #2298@4635} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 48: (V61) long RefPositions {#889@1872 #890@1877} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 49: (V63) int RefPositions {#886@1866 #895@1884 #897@1889} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 50: (V64) int RefPositions {#545@1168 #548@1183 #552@1193} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 51: (V65) int RefPositions {#549@1184 #553@1194 #557@1205} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 52: (V66) int RefPositions {#550@1188 #555@1198 #558@1205} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 53: (V67) int RefPositions {#568@1226 #569@1231} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 54: (V69) byref RefPositions {#316@752 #317@755 #322@763} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 55: (V70) int RefPositions {#335@792 #338@800 #341@807} physReg:NA Preferences=[x1] Interval 56: (V71) int RefPositions {#175@262 #176@269 #181@285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 57: (V72) int RefPositions {#184@288 #185@291} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 58: (V73) int RefPositions {#270@610 #271@613} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 59: (V74) int RefPositions {#1892@3766 #1893@3773} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 60: (V76) byref RefPositions {#42@30 #43@39 #46@45} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 61: (V83) long RefPositions {#641@1340 #642@1347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 62: (V86) ref RefPositions {#755@1554 #756@1561 #762@1581 #785@1645 #799@1673} physReg:NA Preferences=[x1] Interval 63: (V87) int RefPositions {#761@1574 #767@1599 #776@1625 #780@1637 #789@1655} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 64: (V88) byref RefPositions {#773@1614 #774@1623 #778@1629} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 65: (V91) int RefPositions {#904@1902 #907@1913 #916@1937 #921@1955 #923@1963} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 66: (V92) int RefPositions {#900@1892 #922@1955 #933@1981} physReg:NA Preferences=[x1] Interval 67: (V93) byref RefPositions {#913@1928 #914@1935 #918@1941} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 68: (V95) ref RefPositions {#986@2066 #987@2073 #993@2093 #1019@2167 #1033@2195} physReg:NA Preferences=[x1] Interval 69: (V96) int RefPositions {#992@2086 #1000@2115 #1009@2141 #1013@2153 #1023@2177} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 70: (V97) byref RefPositions {#1006@2130 #1007@2139 #1011@2145} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 71: (V99) int RefPositions {#2021@4096 #2024@4107 #2033@4133 #2038@4151 #2040@4159} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 72: (V100) byref RefPositions {#2030@4122 #2031@4131 #2035@4137} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 73: (V102) ref RefPositions {#2103@4262 #2104@4269 #2110@4289 #2133@4355 #2136@4363 #2150@4391} physReg:NA Preferences=[x1] Interval 74: (V103) int RefPositions {#2109@4282 #2115@4307 #2124@4333 #2128@4345 #2140@4373} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 75: (V104) byref RefPositions {#2121@4322 #2122@4331 #2126@4337} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 76: (V106) ref RefPositions {#2415@4864 #2416@4871 #2422@4891 #2445@4957 #2448@4965 #2462@4993} physReg:NA Preferences=[x1] Interval 77: (V107) int RefPositions {#2421@4884 #2427@4909 #2436@4935 #2440@4947 #2452@4975} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 78: (V108) byref RefPositions {#2433@4924 #2434@4933 #2438@4939} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 79: (V110) ref RefPositions {#1111@2350 #1113@2359 #1114@2361 #1120@2379 #1143@2445 #1146@2453 #1160@2481} physReg:NA Preferences=[x1] Interval 80: (V111) int RefPositions {#1119@2372 #1125@2397 #1134@2423 #1138@2435 #1150@2463} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 81: (V112) byref RefPositions {#1131@2412 #1132@2421 #1136@2427} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 82: (V114) ref RefPositions {#2199@4434 #2200@4441 #2201@4443 #2207@4461 #2230@4527 #2233@4535 #2247@4563} physReg:NA Preferences=[x1] Interval 83: (V115) int RefPositions {#2206@4454 #2212@4479 #2221@4505 #2225@4517 #2237@4545} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 84: (V116) byref RefPositions {#2218@4494 #2219@4503 #2223@4509} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 85: (V118) int RefPositions {#2307@4652 #2310@4663 #2319@4687 #2324@4705 #2326@4713} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 86: (V119) int RefPositions {#2303@4642 #2325@4705 #2336@4731} physReg:NA Preferences=[x1] Interval 87: (V120) byref RefPositions {#2316@4678 #2317@4685 #2321@4691} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 88: (V122) int RefPositions {#1217@2558 #1220@2569 #1229@2593 #1234@2611 #1236@2619} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 89: (V123) int RefPositions {#1213@2548 #1235@2611 #1246@2637} physReg:NA Preferences=[x1] Interval 90: (V124) byref RefPositions {#1226@2584 #1227@2591 #1231@2597} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 91: (V126) int RefPositions {#1336@2836 #1339@2847 #1348@2873 #1353@2891 #1355@2899} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 92: (V127) byref RefPositions {#1345@2862 #1346@2871 #1350@2877} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 93: (V129) int RefPositions {#1469@3074 #1472@3085 #1481@3111 #1486@3129 #1488@3137} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 94: (V130) byref RefPositions {#1478@3100 #1479@3109 #1483@3115} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 95: (V132) int RefPositions {#1557@3246 #1560@3257 #1569@3281 #1574@3299 #1576@3307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 96: (V133) int RefPositions {#1553@3236 #1575@3299 #1586@3325} physReg:NA Preferences=[x1] Interval 97: (V134) byref RefPositions {#1566@3272 #1567@3279 #1571@3285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 98: (V136) int RefPositions {#1643@3404 #1646@3415 #1655@3439 #1660@3457 #1662@3465} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 99: (V137) int RefPositions {#1639@3394 #1661@3457 #1672@3483} physReg:NA Preferences=[x1] Interval 100: (V138) byref RefPositions {#1652@3430 #1653@3437 #1657@3443} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 101: (V140) int RefPositions {#1712@3504 #1715@3515 #1724@3541 #1729@3559 #1731@3567} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 102: (V141) byref RefPositions {#1721@3530 #1722@3539 #1726@3545} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 103: (V143) byref (field) RefPositions {#511@1064 #653@1357 #699@1392 #705@1421 #974@2033 #1790@3593 #2091@4229 #2518@5009} physReg:NA Preferences=[x19-x28] Interval 104: (V144) int (field) RefPositions {#514@1068 #581@1271 #583@1283 #635@1327 #638@1337 #701@1396 #704@1405 #973@2019 #1787@3593 #2090@4215 #2513@5009} physReg:NA Preferences=[x19-x28] Interval 105: (V147) byref (field) RefPositions {#56@60 #66@83 #88@131} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 106: (V148) int (field) RefPositions {#61@68 #68@87 #90@135} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 107: (V149) byref (field) RefPositions {#75@104 #81@118 #89@132 #97@145} physReg:NA Preferences=[x0] Interval 108: (V150) int (field) RefPositions {#77@108 #83@122 #91@136 #101@149} physReg:NA Preferences=[x1] Interval 109: (V151) byref (field) RefPositions {#509@1056 #510@1063} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 110: (V155) byref (field) RefPositions {#67@84 #74@103 #80@117} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 111: (V156) int (field) RefPositions {#69@88 #76@107 #82@121} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 112: (V157) byref (field) RefPositions {#164@226 #165@231 #166@237} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 113: (V159) byref (field) RefPositions {#628@1308 #633@1321} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 114: (V160) int (field) RefPositions {#632@1318 #636@1327} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 115: (V161) byref (field) RefPositions {#634@1322 #649@1353} physReg:NA Preferences=[x0] Interval 116: (V163) byref (field) RefPositions {#693@1376 #698@1391} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 117: (V164) int (field) RefPositions {#697@1386 #700@1395} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 118: (V165) byref (field) RefPositions {#837@1694 #838@1699 #839@1705} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 119: (V167) long RefPositions {#49@48 #50@51} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 120: (V168) long RefPositions {#167@238 #168@241} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 121: (V169) long RefPositions {#840@1706 #841@1709} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 122: (V171) int RefPositions {#1884@3746 #1887@3755 #1889@3757 #1897@3781} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 123: (V172) int RefPositions {#2290@4602 #2291@4607 #2293@4617 #2302@4641 #2380@4770 #2381@4775} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 124: (V173) int RefPositions {#1629@3364 #1630@3369 #1638@3393} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 125: (V174) int RefPositions {#225@450 #228@459 #242@506 #243@511 #254@550 #255@555 #257@567} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 126: (V175) int RefPositions {#1541@3194 #1542@3199 #1544@3211 #1552@3235} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 127: (V176) int RefPositions {#1200@2514 #1203@2523 #1204@2525 #1212@2547 #1293@2698 #1294@2703 #1305@2742 #1306@2747 #1324@2793} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 128: (V177) int RefPositions {#881@1854 #882@1859 #894@1883} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 129: (V178) int RefPositions {#489@1010 #490@1021 #492@1021 #499@1037} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 130: (V179) int RefPositions {#59@64 #60@67 #172@251 #227@459 #236@483 #248@527 #274@619 #847@1725 #1202@2523 #1287@2675 #1299@2719 #1373@2939 #1535@3171 #1623@3341 #1777@3593 #1886@3755 #2284@4579 #2374@4747 #2503@5009} physReg:NA Preferences=[x19-x28] Interval 131: (V180) byref RefPositions {#54@56 #55@59 #163@225 #392@839 #836@1693 #1958@3935} physReg:NA Preferences=[x19-x28] RelatedInterval Interval 132: (V181) int RefPositions {#996@2096 #999@2115 #1018@2161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 133: (V182) int RefPositions {#196@334 #197@339 #1863@3691} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 134: (V183) int RefPositions {#202@354 #203@359 #1902@3791} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 135: (V184) int RefPositions {#1088@2260 #1089@2265 #1960@3939} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 136: (V185) int RefPositions {#1094@2280 #1095@2285 #2388@4793} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 137: byref (specialPutArg) RefPositions {#7@8 #15@13} physReg:NA Preferences=[x0] RelatedInterval Interval 138: long (constant) RefPositions {#8@10 #10@11} physReg:NA Preferences=[x11] Interval 139: long RefPositions {#12@12 #17@13} physReg:NA Preferences=[x11] Interval 140: int (INTERNAL) RefPositions {#13@13 #18@13} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 141: byref RefPositions {#40@28 #41@29} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 142: int RefPositions {#44@40 #45@41} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 143: byref RefPositions {#47@46 #48@47} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 144: byref RefPositions {#52@54 #53@55} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 145: int RefPositions {#57@62 #58@63} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 146: ubyte RefPositions {#63@74 #64@77} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 147: bool RefPositions {#71@94 #72@97} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 148: int (constant) RefPositions {#84@124 #85@125} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 149: int (constant) RefPositions {#92@138 #93@139} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 150: byref RefPositions {#99@146 #115@161} physReg:NA Preferences=[x0] Interval 151: int RefPositions {#103@150 #117@161} physReg:NA Preferences=[x1] Interval 152: int RefPositions {#107@156 #119@161} physReg:NA Preferences=[x2] Interval 153: long (constant) RefPositions {#108@158 #110@159} physReg:NA Preferences=[x11] Interval 154: long RefPositions {#112@160 #121@161} physReg:NA Preferences=[x11] Interval 155: int (INTERNAL) RefPositions {#113@161 #122@161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 156: int RefPositions {#143@162 #144@163} physReg:NA Preferences=[x0] RelatedInterval Interval 157: int (constant) RefPositions {#148@176 #149@177} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 158: int (constant) RefPositions {#151@182 #152@183} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 159: int (constant) RefPositions {#156@200 #157@201} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 160: int RefPositions {#177@270 #178@271} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 161: ushort RefPositions {#182@286 #183@287} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 162: int RefPositions {#194@332 #195@333} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 163: int RefPositions {#200@352 #201@353} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 164: int (constant) RefPositions {#212@408 #214@409} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 165: int RefPositions {#217@422 #218@423} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 166: ushort RefPositions {#223@448 #224@449} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 167: int RefPositions {#231@472 #232@473} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 168: ushort RefPositions {#240@504 #241@505} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 169: int RefPositions {#246@524 #247@527} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 170: ushort RefPositions {#252@548 #253@549} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 171: int RefPositions {#260@582 #262@591} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 172: ushort RefPositions {#263@592 #264@595} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 173: int RefPositions {#268@608 #269@609} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 174: ushort RefPositions {#278@640 #279@643} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 175: int (constant) RefPositions {#281@652 #282@653} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 176: int (constant) RefPositions {#297@714 #300@717} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 177: int RefPositions {#301@718 #302@719} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 178: int (constant) RefPositions {#305@726 #306@727} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 179: ubyte RefPositions {#310@736 #311@739} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 180: byref RefPositions {#314@750 #315@751} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 181: int RefPositions {#318@756 #319@759} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 182: int RefPositions {#321@760 #323@763} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 183: int RefPositions {#327@782 #328@785} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 184: int RefPositions {#330@786 #331@789} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 185: int RefPositions {#333@790 #334@791} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 186: int RefPositions {#343@808 #360@821} physReg:NA Preferences=[x1] Interval 187: byref (specialPutArg) RefPositions {#347@812 #362@821} physReg:NA Preferences=[x0] RelatedInterval Interval 188: long (constant) RefPositions {#348@814 #350@815} physReg:NA Preferences=[x11] Interval 189: long RefPositions {#352@816 #364@821} physReg:NA Preferences=[x11] Interval 190: int (constant) RefPositions {#353@818 #355@819} physReg:NA Preferences=[x2] Interval 191: int RefPositions {#357@820 #366@821} physReg:NA Preferences=[x2] Interval 192: int (INTERNAL) RefPositions {#358@821 #367@821} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 193: ubyte RefPositions {#388@828 #389@831} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 194: byref (specialPutArg) RefPositions {#394@840 #412@855} physReg:NA Preferences=[x0] RelatedInterval Interval 195: long RefPositions {#395@842 #397@843} physReg:NA Preferences=[x1] Interval 196: long RefPositions {#399@844 #414@855} physReg:NA Preferences=[x1] Interval 197: long (constant) RefPositions {#400@848 #402@849} physReg:NA Preferences=[x11] Interval 198: long RefPositions {#404@850 #416@855} physReg:NA Preferences=[x11] Interval 199: int (constant) RefPositions {#405@852 #407@853} physReg:NA Preferences=[x2] Interval 200: int RefPositions {#409@854 #418@855} physReg:NA Preferences=[x2] Interval 201: int (INTERNAL) RefPositions {#410@855 #419@855} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 202: int RefPositions {#440@856 #441@857} physReg:NA Preferences=[x0] RelatedInterval Interval 203: ubyte RefPositions {#451@886 #452@889} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 204: int RefPositions {#460@934 #463@937} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 205: int RefPositions {#464@938 #465@939} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 206: int RefPositions {#471@962 #474@965} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 207: int RefPositions {#475@966 #476@967} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 208: int RefPositions {#487@1008 #488@1009} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 209: int RefPositions {#494@1022 #495@1023} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 210: int RefPositions {#501@1038 #502@1039} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 211: long RefPositions {#507@1054 #508@1055} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 212: int (constant) RefPositions {#512@1066 #513@1067} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 213: int (constant) RefPositions {#515@1072 #516@1073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 214: ref RefPositions {#519@1082 #520@1085} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 215: int RefPositions {#521@1086 #522@1099} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 216: ref RefPositions {#526@1112 #527@1113} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 217: int RefPositions {#532@1134 #533@1135} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 218: int RefPositions {#538@1154 #539@1155} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 219: int RefPositions {#559@1206 #560@1207} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 220: int RefPositions {#566@1224 #567@1225} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 221: int RefPositions {#577@1262 #578@1263} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 222: int RefPositions {#584@1284 #585@1285} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 223: long RefPositions {#586@1286 #588@1287} physReg:NA Preferences=[x0] Interval 224: long RefPositions {#590@1288 #598@1293} physReg:NA Preferences=[x0] Interval 225: long (constant) RefPositions {#591@1290 #593@1291} physReg:NA Preferences=[x11] Interval 226: long RefPositions {#595@1292 #600@1293} physReg:NA Preferences=[x11] Interval 227: int (INTERNAL) RefPositions {#596@1293 #601@1293} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 228: ref RefPositions {#622@1294 #623@1295} physReg:NA Preferences=[x0] RelatedInterval Interval 229: byref RefPositions {#626@1306 #627@1307} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 230: int RefPositions {#630@1316 #631@1317} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 231: long RefPositions {#639@1338 #640@1339} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 232: long RefPositions {#643@1348 #645@1349} physReg:NA Preferences=[x2] Interval 233: long RefPositions {#647@1350 #663@1363} physReg:NA Preferences=[x2] Interval 234: byref RefPositions {#651@1354 #665@1363} physReg:NA Preferences=[x0] Interval 235: byref RefPositions {#655@1358 #667@1363} physReg:NA Preferences=[x1] Interval 236: long (constant) RefPositions {#656@1360 #658@1361} physReg:NA Preferences=[x11] Interval 237: long RefPositions {#660@1362 #669@1363} physReg:NA Preferences=[x11] Interval 238: int (INTERNAL) RefPositions {#661@1363 #670@1363} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 239: byref RefPositions {#691@1374 #692@1375} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 240: int RefPositions {#695@1384 #696@1385} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 241: int RefPositions {#709@1432 #711@1433} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 242: int RefPositions {#714@1446 #715@1447} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 243: int RefPositions {#718@1458 #720@1459} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 244: byref RefPositions {#722@1466 #723@1477} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 245: int RefPositions {#725@1478 #726@1479} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 246: int RefPositions {#731@1490 #732@1491} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 247: bool RefPositions {#744@1512 #745@1525} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 248: int RefPositions {#749@1538 #750@1541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 249: ref RefPositions {#753@1552 #754@1553} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 250: int RefPositions {#759@1572 #760@1573} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 251: int RefPositions {#763@1582 #766@1599} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 252: int RefPositions {#765@1594 #768@1599} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 253: byref RefPositions {#771@1612 #772@1613} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 254: int RefPositions {#775@1624 #777@1625} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 255: byref RefPositions {#779@1630 #782@1639} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 256: long RefPositions {#781@1638 #783@1639} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 257: byref RefPositions {#784@1640 #787@1647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 258: ushort RefPositions {#786@1646 #788@1647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 259: int RefPositions {#790@1656 #792@1661} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 260: byref (specialPutArg) RefPositions {#797@1670 #809@1679} physReg:NA Preferences=[x0] RelatedInterval Interval 261: ref RefPositions {#801@1674 #811@1679} physReg:NA Preferences=[x1] Interval 262: long (constant) RefPositions {#802@1676 #804@1677} physReg:NA Preferences=[x11] Interval 263: long RefPositions {#806@1678 #813@1679} physReg:NA Preferences=[x11] Interval 264: int (INTERNAL) RefPositions {#807@1679 #814@1679} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 265: int RefPositions {#852@1744 #853@1745} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 266: ushort RefPositions {#857@1760 #858@1761} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 267: int (constant) RefPositions {#868@1810 #871@1815} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 268: ubyte RefPositions {#879@1852 #880@1853} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 269: int (constant) RefPositions {#884@1864 #885@1865} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 270: long RefPositions {#891@1878 #892@1879} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 271: int RefPositions {#898@1890 #899@1891} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 272: int RefPositions {#902@1900 #903@1901} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 273: int RefPositions {#906@1912 #908@1913} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 274: byref RefPositions {#911@1926 #912@1927} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 275: int RefPositions {#915@1936 #917@1937} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 276: byref RefPositions {#919@1942 #920@1955} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 277: int RefPositions {#924@1964 #926@1969} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 278: byref (specialPutArg) RefPositions {#931@1978 #943@1987} physReg:NA Preferences=[x0] RelatedInterval Interval 279: int RefPositions {#935@1982 #945@1987} physReg:NA Preferences=[x1] Interval 280: long (constant) RefPositions {#936@1984 #938@1985} physReg:NA Preferences=[x11] Interval 281: long RefPositions {#940@1986 #947@1987} physReg:NA Preferences=[x11] Interval 282: int (INTERNAL) RefPositions {#941@1987 #948@1987} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 283: int RefPositions {#976@2034 #977@2037} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 284: int RefPositions {#978@2038 #979@2051} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 285: ref RefPositions {#984@2064 #985@2065} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 286: int RefPositions {#990@2084 #991@2085} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 287: int RefPositions {#994@2094 #995@2095} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 288: int RefPositions {#998@2110 #1001@2115} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 289: byref RefPositions {#1004@2128 #1005@2129} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 290: int RefPositions {#1008@2140 #1010@2141} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 291: byref RefPositions {#1012@2146 #1015@2155} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 292: long RefPositions {#1014@2154 #1016@2155} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 293: byref RefPositions {#1017@2156 #1021@2169} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 294: ushort RefPositions {#1020@2168 #1022@2169} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 295: int RefPositions {#1024@2178 #1026@2183} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 296: byref (specialPutArg) RefPositions {#1031@2192 #1043@2201} physReg:NA Preferences=[x0] RelatedInterval Interval 297: ref RefPositions {#1035@2196 #1045@2201} physReg:NA Preferences=[x1] Interval 298: long (constant) RefPositions {#1036@2198 #1038@2199} physReg:NA Preferences=[x11] Interval 299: long RefPositions {#1040@2200 #1047@2201} physReg:NA Preferences=[x11] Interval 300: int (INTERNAL) RefPositions {#1041@2201 #1048@2201} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 301: int RefPositions {#1070@2212 #1071@2213} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 302: int RefPositions {#1075@2224 #1076@2225} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 303: int RefPositions {#1079@2234 #1080@2235} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 304: int RefPositions {#1086@2258 #1087@2259} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 305: int RefPositions {#1092@2278 #1093@2279} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 306: int (constant) RefPositions {#1104@2334 #1106@2335} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 307: ref RefPositions {#1109@2348 #1110@2349} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 308: int RefPositions {#1117@2370 #1118@2371} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 309: int RefPositions {#1121@2380 #1124@2397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 310: int RefPositions {#1123@2392 #1126@2397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 311: byref RefPositions {#1129@2410 #1130@2411} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 312: int RefPositions {#1133@2422 #1135@2423} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 313: byref RefPositions {#1137@2428 #1140@2437} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 314: long RefPositions {#1139@2436 #1141@2437} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 315: byref RefPositions {#1142@2438 #1148@2455} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 316: int RefPositions {#1144@2446 #1145@2447} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 317: ushort RefPositions {#1147@2454 #1149@2455} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 318: int RefPositions {#1151@2464 #1153@2469} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 319: byref (specialPutArg) RefPositions {#1158@2478 #1170@2487} physReg:NA Preferences=[x0] RelatedInterval Interval 320: ref RefPositions {#1162@2482 #1172@2487} physReg:NA Preferences=[x1] Interval 321: long (constant) RefPositions {#1163@2484 #1165@2485} physReg:NA Preferences=[x11] Interval 322: long RefPositions {#1167@2486 #1174@2487} physReg:NA Preferences=[x11] Interval 323: int (INTERNAL) RefPositions {#1168@2487 #1175@2487} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 324: ushort RefPositions {#1198@2512 #1199@2513} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 325: int RefPositions {#1209@2542 #1210@2543} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 326: int RefPositions {#1215@2556 #1216@2557} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 327: int RefPositions {#1219@2568 #1221@2569} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 328: byref RefPositions {#1224@2582 #1225@2583} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 329: int RefPositions {#1228@2592 #1230@2593} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 330: byref RefPositions {#1232@2598 #1233@2611} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 331: int RefPositions {#1237@2620 #1239@2625} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 332: byref (specialPutArg) RefPositions {#1244@2634 #1256@2643} physReg:NA Preferences=[x0] RelatedInterval Interval 333: int RefPositions {#1248@2638 #1258@2643} physReg:NA Preferences=[x1] Interval 334: long (constant) RefPositions {#1249@2640 #1251@2641} physReg:NA Preferences=[x11] Interval 335: long RefPositions {#1253@2642 #1260@2643} physReg:NA Preferences=[x11] Interval 336: int (INTERNAL) RefPositions {#1254@2643 #1261@2643} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 337: ushort RefPositions {#1291@2696 #1292@2697} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 338: int RefPositions {#1297@2716 #1298@2719} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 339: ushort RefPositions {#1303@2740 #1304@2741} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 340: int RefPositions {#1307@2748 #1315@2771} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 341: int RefPositions {#1309@2756 #1311@2765} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 342: ushort RefPositions {#1312@2766 #1313@2769} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 343: int RefPositions {#1314@2770 #1316@2771} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 344: int RefPositions {#1317@2772 #1318@2773} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 345: int (constant) RefPositions {#1320@2782 #1321@2783} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 346: int RefPositions {#1327@2808 #1329@2817} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 347: ushort RefPositions {#1330@2818 #1331@2821} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 348: int RefPositions {#1334@2834 #1335@2835} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 349: int RefPositions {#1338@2846 #1340@2847} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 350: byref RefPositions {#1343@2860 #1344@2861} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 351: int RefPositions {#1347@2872 #1349@2873} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 352: byref RefPositions {#1351@2878 #1352@2891} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 353: int RefPositions {#1356@2900 #1358@2905} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 354: int RefPositions {#1362@2916 #1363@2917} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 355: int RefPositions {#1367@2928 #1368@2929} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 356: ushort RefPositions {#1377@2960 #1378@2963} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 357: int (constant) RefPositions {#1382@2984 #1383@2985} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 358: ubyte RefPositions {#1387@2994 #1388@2997} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 359: int RefPositions {#1391@3008 #1392@3011} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 360: int RefPositions {#1394@3012 #1395@3013} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 361: int RefPositions {#1403@3030 #1431@3055} physReg:NA Preferences=[x5] Interval 362: byref (specialPutArg) RefPositions {#1407@3034 #1433@3055} physReg:NA Preferences=[x0] RelatedInterval Interval 363: ref (specialPutArg) RefPositions {#1411@3038 #1435@3055} physReg:NA Preferences=[x1] RelatedInterval Interval 364: int RefPositions {#1415@3042 #1437@3055} physReg:NA Preferences=[x2] Interval 365: int RefPositions {#1419@3046 #1439@3055} physReg:NA Preferences=[x3] Interval 366: int RefPositions {#1423@3050 #1441@3055} physReg:NA Preferences=[x4] Interval 367: long (constant) RefPositions {#1424@3052 #1426@3053} physReg:NA Preferences=[x11] Interval 368: long RefPositions {#1428@3054 #1443@3055} physReg:NA Preferences=[x11] Interval 369: int (INTERNAL) RefPositions {#1429@3055 #1444@3055} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 370: int RefPositions {#1467@3072 #1468@3073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 371: int RefPositions {#1471@3084 #1473@3085} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 372: byref RefPositions {#1476@3098 #1477@3099} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 373: int RefPositions {#1480@3110 #1482@3111} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 374: byref RefPositions {#1484@3116 #1485@3129} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 375: int RefPositions {#1489@3138 #1491@3143} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 376: byref (specialPutArg) RefPositions {#1496@3152 #1508@3161} physReg:NA Preferences=[x0] RelatedInterval Interval 377: int RefPositions {#1500@3156 #1510@3161} physReg:NA Preferences=[x1] Interval 378: long (constant) RefPositions {#1501@3158 #1503@3159} physReg:NA Preferences=[x11] Interval 379: long RefPositions {#1505@3160 #1512@3161} physReg:NA Preferences=[x11] Interval 380: int (INTERNAL) RefPositions {#1506@3161 #1513@3161} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 381: ushort RefPositions {#1539@3192 #1540@3193} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 382: int RefPositions {#1549@3230 #1550@3231} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 383: int RefPositions {#1555@3244 #1556@3245} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 384: int RefPositions {#1559@3256 #1561@3257} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 385: byref RefPositions {#1564@3270 #1565@3271} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 386: int RefPositions {#1568@3280 #1570@3281} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 387: byref RefPositions {#1572@3286 #1573@3299} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 388: int RefPositions {#1577@3308 #1579@3313} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 389: byref (specialPutArg) RefPositions {#1584@3322 #1596@3331} physReg:NA Preferences=[x0] RelatedInterval Interval 390: int RefPositions {#1588@3326 #1598@3331} physReg:NA Preferences=[x1] Interval 391: long (constant) RefPositions {#1589@3328 #1591@3329} physReg:NA Preferences=[x11] Interval 392: long RefPositions {#1593@3330 #1600@3331} physReg:NA Preferences=[x11] Interval 393: int (INTERNAL) RefPositions {#1594@3331 #1601@3331} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 394: ushort RefPositions {#1627@3362 #1628@3363} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 395: int RefPositions {#1635@3388 #1636@3389} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 396: int RefPositions {#1641@3402 #1642@3403} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 397: int RefPositions {#1645@3414 #1647@3415} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 398: byref RefPositions {#1650@3428 #1651@3429} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 399: int RefPositions {#1654@3438 #1656@3439} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 400: byref RefPositions {#1658@3444 #1659@3457} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 401: int RefPositions {#1663@3466 #1665@3471} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 402: byref (specialPutArg) RefPositions {#1670@3480 #1682@3489} physReg:NA Preferences=[x0] RelatedInterval Interval 403: int RefPositions {#1674@3484 #1684@3489} physReg:NA Preferences=[x1] Interval 404: long (constant) RefPositions {#1675@3486 #1677@3487} physReg:NA Preferences=[x11] Interval 405: long RefPositions {#1679@3488 #1686@3489} physReg:NA Preferences=[x11] Interval 406: int (INTERNAL) RefPositions {#1680@3489 #1687@3489} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 407: int RefPositions {#1710@3502 #1711@3503} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 408: int RefPositions {#1714@3514 #1716@3515} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 409: byref RefPositions {#1719@3528 #1720@3529} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 410: int RefPositions {#1723@3540 #1725@3541} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 411: byref RefPositions {#1727@3546 #1728@3559} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 412: int RefPositions {#1732@3568 #1734@3573} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 413: byref (specialPutArg) RefPositions {#1739@3582 #1751@3591} physReg:NA Preferences=[x0] RelatedInterval Interval 414: int RefPositions {#1743@3586 #1753@3591} physReg:NA Preferences=[x1] Interval 415: long (constant) RefPositions {#1744@3588 #1746@3589} physReg:NA Preferences=[x11] Interval 416: long RefPositions {#1748@3590 #1755@3591} physReg:NA Preferences=[x11] Interval 417: int (INTERNAL) RefPositions {#1749@3591 #1756@3591} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 418: bool RefPositions {#1795@3608 #1796@3621} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 419: int RefPositions {#1800@3634 #1801@3637} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 420: int RefPositions {#1802@3638 #1807@3649} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 421: int RefPositions {#1804@3644 #1805@3647} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 422: int RefPositions {#1806@3648 #1808@3649} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 423: int RefPositions {#1809@3650 #1810@3651} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 424: ref RefPositions {#1813@3664 #1815@3665} physReg:NA Preferences=[x2] Interval 425: ref RefPositions {#1817@3666 #1834@3679} physReg:NA Preferences=[x2] Interval 426: byref RefPositions {#1821@3670 #1836@3679} physReg:NA Preferences=[x0] Interval 427: long (constant) RefPositions {#1822@3672 #1824@3673} physReg:NA Preferences=[x11] Interval 428: long RefPositions {#1826@3674 #1838@3679} physReg:NA Preferences=[x11] Interval 429: int (constant) RefPositions {#1827@3676 #1829@3677} physReg:NA Preferences=[x1] Interval 430: int RefPositions {#1831@3678 #1840@3679} physReg:NA Preferences=[x1] Interval 431: int (INTERNAL) RefPositions {#1832@3679 #1841@3679} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 432: long RefPositions {#1864@3692 #1867@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 433: long RefPositions {#1865@3694 #1868@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 434: int (INTERNAL) RefPositions {#1866@3695} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 435: int RefPositions {#1871@3706 #1872@3707} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 436: int RefPositions {#1876@3718 #1877@3719} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 437: ushort RefPositions {#1882@3744 #1883@3745} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 438: int RefPositions {#1894@3774 #1895@3775} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 439: long RefPositions {#1903@3792 #1906@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 440: long RefPositions {#1904@3794 #1907@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 441: int (INTERNAL) RefPositions {#1905@3795} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 442: int (constant) RefPositions {#1909@3804 #1911@3805} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 443: int RefPositions {#1917@3826 #1918@3827} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 444: int RefPositions {#1938@3910 #1939@3911} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 445: int (constant) RefPositions {#1945@3918 #1946@3919} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 446: int (constant) RefPositions {#1951@3932 #1952@3933} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 447: long RefPositions {#1961@3940 #1964@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 448: long RefPositions {#1962@3942 #1965@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 449: int (INTERNAL) RefPositions {#1963@3943} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 450: int RefPositions {#1970@3966 #1971@3967} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 451: int (constant) RefPositions {#1978@3992 #1979@3993} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 452: int RefPositions {#1983@4000 #1984@4001} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 453: ubyte RefPositions {#1988@4010 #1989@4013} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 454: int (constant) RefPositions {#1996@4040 #1997@4041} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 455: long RefPositions {#2003@4058 #2004@4059} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 456: ubyte RefPositions {#2007@4064 #2008@4065} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 457: int RefPositions {#2012@4072 #2013@4073} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 458: int RefPositions {#2019@4094 #2020@4095} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 459: int RefPositions {#2023@4106 #2025@4107} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 460: byref RefPositions {#2028@4120 #2029@4121} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 461: int RefPositions {#2032@4132 #2034@4133} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 462: byref RefPositions {#2036@4138 #2037@4151} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 463: int RefPositions {#2041@4160 #2043@4165} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 464: byref (specialPutArg) RefPositions {#2048@4174 #2060@4183} physReg:NA Preferences=[x0] RelatedInterval Interval 465: int RefPositions {#2052@4178 #2062@4183} physReg:NA Preferences=[x1] Interval 466: long (constant) RefPositions {#2053@4180 #2055@4181} physReg:NA Preferences=[x11] Interval 467: long RefPositions {#2057@4182 #2064@4183} physReg:NA Preferences=[x11] Interval 468: int (INTERNAL) RefPositions {#2058@4183 #2065@4183} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 469: int RefPositions {#2093@4230 #2094@4233} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 470: int RefPositions {#2095@4234 #2096@4247} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 471: ref RefPositions {#2101@4260 #2102@4261} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 472: int RefPositions {#2107@4280 #2108@4281} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 473: int RefPositions {#2111@4290 #2114@4307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 474: int RefPositions {#2113@4302 #2116@4307} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 475: byref RefPositions {#2119@4320 #2120@4321} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 476: int RefPositions {#2123@4332 #2125@4333} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 477: byref RefPositions {#2127@4338 #2130@4347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 478: long RefPositions {#2129@4346 #2131@4347} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 479: byref RefPositions {#2132@4348 #2138@4365} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 480: int RefPositions {#2134@4356 #2135@4357} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 481: ushort RefPositions {#2137@4364 #2139@4365} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 482: int RefPositions {#2141@4374 #2143@4379} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 483: byref (specialPutArg) RefPositions {#2148@4388 #2160@4397} physReg:NA Preferences=[x0] RelatedInterval Interval 484: ref RefPositions {#2152@4392 #2162@4397} physReg:NA Preferences=[x1] Interval 485: long (constant) RefPositions {#2153@4394 #2155@4395} physReg:NA Preferences=[x11] Interval 486: long RefPositions {#2157@4396 #2164@4397} physReg:NA Preferences=[x11] Interval 487: int (INTERNAL) RefPositions {#2158@4397 #2165@4397} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 488: int RefPositions {#2187@4408 #2188@4409} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 489: int RefPositions {#2192@4420 #2193@4421} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 490: ref RefPositions {#2197@4432 #2198@4433} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 491: int RefPositions {#2204@4452 #2205@4453} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 492: int RefPositions {#2208@4462 #2211@4479} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 493: int RefPositions {#2210@4474 #2213@4479} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 494: byref RefPositions {#2216@4492 #2217@4493} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 495: int RefPositions {#2220@4504 #2222@4505} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 496: byref RefPositions {#2224@4510 #2227@4519} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 497: long RefPositions {#2226@4518 #2228@4519} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 498: byref RefPositions {#2229@4520 #2235@4537} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 499: int RefPositions {#2231@4528 #2232@4529} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 500: ushort RefPositions {#2234@4536 #2236@4537} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 501: int RefPositions {#2238@4546 #2240@4551} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 502: byref (specialPutArg) RefPositions {#2245@4560 #2257@4569} physReg:NA Preferences=[x0] RelatedInterval Interval 503: ref RefPositions {#2249@4564 #2259@4569} physReg:NA Preferences=[x1] Interval 504: long (constant) RefPositions {#2250@4566 #2252@4567} physReg:NA Preferences=[x11] Interval 505: long RefPositions {#2254@4568 #2261@4569} physReg:NA Preferences=[x11] Interval 506: int (INTERNAL) RefPositions {#2255@4569 #2262@4569} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 507: ushort RefPositions {#2288@4600 #2289@4601} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 508: int RefPositions {#2299@4636 #2300@4637} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 509: int RefPositions {#2305@4650 #2306@4651} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 510: int RefPositions {#2309@4662 #2311@4663} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 511: byref RefPositions {#2314@4676 #2315@4677} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 512: int RefPositions {#2318@4686 #2320@4687} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 513: byref RefPositions {#2322@4692 #2323@4705} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 514: int RefPositions {#2327@4714 #2329@4719} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 515: byref (specialPutArg) RefPositions {#2334@4728 #2346@4737} physReg:NA Preferences=[x0] RelatedInterval Interval 516: int RefPositions {#2338@4732 #2348@4737} physReg:NA Preferences=[x1] Interval 517: long (constant) RefPositions {#2339@4734 #2341@4735} physReg:NA Preferences=[x11] Interval 518: long RefPositions {#2343@4736 #2350@4737} physReg:NA Preferences=[x11] Interval 519: int (INTERNAL) RefPositions {#2344@4737 #2351@4737} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 520: ushort RefPositions {#2378@4768 #2379@4769} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 521: int RefPositions {#2384@4786 #2385@4787} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 522: long RefPositions {#2389@4794 #2392@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 523: long RefPositions {#2390@4796 #2393@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 524: int (INTERNAL) RefPositions {#2391@4797} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 525: int RefPositions {#2397@4808 #2398@4811} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 526: int RefPositions {#2400@4812 #2401@4815} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 527: ubyte RefPositions {#2406@4842 #2409@4849} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 528: ref RefPositions {#2413@4862 #2414@4863} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 529: int RefPositions {#2419@4882 #2420@4883} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 530: int RefPositions {#2423@4892 #2426@4909} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 531: int RefPositions {#2425@4904 #2428@4909} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 532: byref RefPositions {#2431@4922 #2432@4923} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 533: int RefPositions {#2435@4934 #2437@4935} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 534: byref RefPositions {#2439@4940 #2442@4949} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 535: long RefPositions {#2441@4948 #2443@4949} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 536: byref RefPositions {#2444@4950 #2450@4967} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 537: int RefPositions {#2446@4958 #2447@4959} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 538: ushort RefPositions {#2449@4966 #2451@4967} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 539: int RefPositions {#2453@4976 #2455@4981} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 540: byref (specialPutArg) RefPositions {#2460@4990 #2472@4999} physReg:NA Preferences=[x0] RelatedInterval Interval 541: ref RefPositions {#2464@4994 #2474@4999} physReg:NA Preferences=[x1] Interval 542: long (constant) RefPositions {#2465@4996 #2467@4997} physReg:NA Preferences=[x11] Interval 543: long RefPositions {#2469@4998 #2476@4999} physReg:NA Preferences=[x11] Interval 544: int (INTERNAL) RefPositions {#2470@4999 #2477@4999} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 545: int (constant) RefPositions {#2498@5006 #2499@5007} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 546: long (constant) RefPositions {#2523@5014 #2525@5015} physReg:NA Preferences=[x11] Interval 547: long RefPositions {#2527@5016 #2530@5017} physReg:NA Preferences=[x11] Interval 548: int (INTERNAL) RefPositions {#2528@5017 #2531@5017} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 549: long (constant) RefPositions {#2552@5022 #2553@5023} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 550: long RefPositions {#2554@5024 #2555@5025} physReg:NA Preferences=[x0-xip0 x19-x28] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> BB00 regmask=[x4] minReg=1 fixed regOptional wt=100.00> BB00 regmask=[x1] minReg=1 fixed regOptional wt=100.00> BB01 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 fixed wt=2150.00> BB01 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00> CNS_INT BB01 regmask=[x11] minReg=1 wt=400.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 last fixed wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x11] minReg=1 fixed wt=400.00> CALL BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 last fixed wt=100.00> CALL BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> BB01 regmask=[x0] minReg=1 last wt=100.00> BB01 regmask=[x1] minReg=1 last wt=100.00> BB01 regmask=[x2] minReg=1 last wt=100.00> BB01 regmask=[x3] minReg=1 last wt=100.00> BB01 regmask=[x4] minReg=1 last wt=100.00> BB01 regmask=[x5] minReg=1 last wt=100.00> BB01 regmask=[x6] minReg=1 last wt=100.00> BB01 regmask=[x7] minReg=1 last wt=100.00> BB01 regmask=[x8] minReg=1 last wt=100.00> BB01 regmask=[x9] minReg=1 last wt=100.00> BB01 regmask=[x10] minReg=1 last wt=100.00> BB01 regmask=[x11] minReg=1 last wt=100.00> BB01 regmask=[x12] minReg=1 last wt=100.00> BB01 regmask=[x13] minReg=1 last wt=100.00> BB01 regmask=[x14] minReg=1 last wt=100.00> BB01 regmask=[x15] minReg=1 last wt=100.00> BB01 regmask=[xip0] minReg=1 last wt=100.00> BB01 regmask=[xip1] minReg=1 last wt=100.00> BB01 regmask=[lr] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_FLD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_FLD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> CNS_INT BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> CNS_INT BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> BB06 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x0] minReg=1 last fixed wt=250.00> BB06 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x0] minReg=1 fixed wt=400.00> BB06 regmask=[x1] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x1] minReg=1 last fixed wt=250.00> BB06 regmask=[x1] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x1] minReg=1 fixed wt=400.00> BB06 regmask=[x2] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x2] minReg=1 last fixed wt=250.00> BB06 regmask=[x2] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x2] minReg=1 fixed wt=400.00> CNS_INT BB06 regmask=[x11] minReg=1 wt=400.00> BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 last fixed wt=100.00> BB06 regmask=[x11] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x11] minReg=1 fixed wt=400.00> CALL BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB06 regmask=[x0] minReg=1 wt=100.00> BB06 regmask=[x0] minReg=1 last fixed wt=100.00> BB06 regmask=[x1] minReg=1 wt=100.00> BB06 regmask=[x1] minReg=1 last fixed wt=100.00> BB06 regmask=[x2] minReg=1 wt=100.00> BB06 regmask=[x2] minReg=1 last fixed wt=100.00> BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 last fixed wt=100.00> CALL BB06 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> BB06 regmask=[x0] minReg=1 last wt=100.00> BB06 regmask=[x1] minReg=1 last wt=100.00> BB06 regmask=[x2] minReg=1 last wt=100.00> BB06 regmask=[x3] minReg=1 last wt=100.00> BB06 regmask=[x4] minReg=1 last wt=100.00> BB06 regmask=[x5] minReg=1 last wt=100.00> BB06 regmask=[x6] minReg=1 last wt=100.00> BB06 regmask=[x7] minReg=1 last wt=100.00> BB06 regmask=[x8] minReg=1 last wt=100.00> BB06 regmask=[x9] minReg=1 last wt=100.00> BB06 regmask=[x10] minReg=1 last wt=100.00> BB06 regmask=[x11] minReg=1 last wt=100.00> BB06 regmask=[x12] minReg=1 last wt=100.00> BB06 regmask=[x13] minReg=1 last wt=100.00> BB06 regmask=[x14] minReg=1 last wt=100.00> BB06 regmask=[x15] minReg=1 last wt=100.00> BB06 regmask=[xip0] minReg=1 last wt=100.00> BB06 regmask=[xip1] minReg=1 last wt=100.00> BB06 regmask=[lr] minReg=1 last wt=100.00> BB06 regmask=[x0] minReg=1 wt=100.00> CALL BB06 regmask=[x0] minReg=1 fixed wt=400.00> BB06 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> CNS_INT BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> ADD BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> IND BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB49 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> ADD BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB09 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> ADD BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB10 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB13 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> CNS_INT BB15 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ADD BB16 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> ADD BB36 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB40 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB41 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB42 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> IND BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> ADD BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> BB45 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> CNS_INT BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB50 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB52 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> CNS_INT BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> SUB BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> CNS_INT BB55 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB55 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB55 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB56 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> IND BB56 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB56 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> ADD BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ADD BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> ADD BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> SUB BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB58 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB60 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB60 regmask=[x1] minReg=1 last fixed wt=800.00> BB60 regmask=[x1] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x1] minReg=1 fixed wt=1600.00> BB60 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB60 regmask=[x0] minReg=1 fixed wt=2150.00> BB60 regmask=[x0] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x0] minReg=1 fixed wt=1600.00> CNS_INT BB60 regmask=[x11] minReg=1 wt=1600.00> BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 last fixed wt=400.00> BB60 regmask=[x11] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x11] minReg=1 fixed wt=1600.00> CNS_INT BB60 regmask=[x2] minReg=1 wt=1600.00> BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 last fixed wt=400.00> BB60 regmask=[x2] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x2] minReg=1 fixed wt=1600.00> CALL BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB60 regmask=[x1] minReg=1 wt=400.00> BB60 regmask=[x1] minReg=1 last fixed wt=400.00> BB60 regmask=[x0] minReg=1 wt=400.00> BB60 regmask=[x0] minReg=1 last fixed wt=400.00> BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 last fixed wt=400.00> BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 last fixed wt=400.00> CALL BB60 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> BB60 regmask=[x0] minReg=1 last wt=400.00> BB60 regmask=[x1] minReg=1 last wt=400.00> BB60 regmask=[x2] minReg=1 last wt=400.00> BB60 regmask=[x3] minReg=1 last wt=400.00> BB60 regmask=[x4] minReg=1 last wt=400.00> BB60 regmask=[x5] minReg=1 last wt=400.00> BB60 regmask=[x6] minReg=1 last wt=400.00> BB60 regmask=[x7] minReg=1 last wt=400.00> BB60 regmask=[x8] minReg=1 last wt=400.00> BB60 regmask=[x9] minReg=1 last wt=400.00> BB60 regmask=[x10] minReg=1 last wt=400.00> BB60 regmask=[x11] minReg=1 last wt=400.00> BB60 regmask=[x12] minReg=1 last wt=400.00> BB60 regmask=[x13] minReg=1 last wt=400.00> BB60 regmask=[x14] minReg=1 last wt=400.00> BB60 regmask=[x15] minReg=1 last wt=400.00> BB60 regmask=[xip0] minReg=1 last wt=400.00> BB60 regmask=[xip1] minReg=1 last wt=400.00> BB60 regmask=[lr] minReg=1 last wt=400.00> LCL_VAR BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> IND BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB60 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> BB61 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB61 regmask=[x0] minReg=1 fixed wt=1500.00> BB61 regmask=[x0] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x0] minReg=1 fixed wt=1600.00> LCL_FLD BB61 regmask=[x1] minReg=1 wt=1600.00> BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 last fixed wt=400.00> BB61 regmask=[x1] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x1] minReg=1 fixed wt=1600.00> CNS_INT BB61 regmask=[x11] minReg=1 wt=1600.00> BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 last fixed wt=400.00> BB61 regmask=[x11] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x11] minReg=1 fixed wt=1600.00> CNS_INT BB61 regmask=[x2] minReg=1 wt=1600.00> BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 last fixed wt=400.00> BB61 regmask=[x2] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x2] minReg=1 fixed wt=1600.00> CALL BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB61 regmask=[x0] minReg=1 wt=400.00> BB61 regmask=[x0] minReg=1 last fixed wt=400.00> BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 last fixed wt=400.00> BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 last fixed wt=400.00> BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 last fixed wt=400.00> CALL BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> BB61 regmask=[x0] minReg=1 last wt=400.00> BB61 regmask=[x1] minReg=1 last wt=400.00> BB61 regmask=[x2] minReg=1 last wt=400.00> BB61 regmask=[x3] minReg=1 last wt=400.00> BB61 regmask=[x4] minReg=1 last wt=400.00> BB61 regmask=[x5] minReg=1 last wt=400.00> BB61 regmask=[x6] minReg=1 last wt=400.00> BB61 regmask=[x7] minReg=1 last wt=400.00> BB61 regmask=[x8] minReg=1 last wt=400.00> BB61 regmask=[x9] minReg=1 last wt=400.00> BB61 regmask=[x10] minReg=1 last wt=400.00> BB61 regmask=[x11] minReg=1 last wt=400.00> BB61 regmask=[x12] minReg=1 last wt=400.00> BB61 regmask=[x13] minReg=1 last wt=400.00> BB61 regmask=[x14] minReg=1 last wt=400.00> BB61 regmask=[x15] minReg=1 last wt=400.00> BB61 regmask=[xip0] minReg=1 last wt=400.00> BB61 regmask=[xip1] minReg=1 last wt=400.00> BB61 regmask=[lr] minReg=1 last wt=400.00> BB61 regmask=[x0] minReg=1 wt=400.00> CALL BB61 regmask=[x0] minReg=1 fixed wt=1600.00> BB61 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> BB62 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB63 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB63 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB63 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB64 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB65 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> SUB BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> SELECT BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> SUB BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> SELECT BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> SELECT BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> SUB BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR_ADDR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> CNS_INT BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> CNS_INT BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> IND BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> IND BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB79 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> IND BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB81 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> ADD BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> SELECT BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB89 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> ADD BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LSH BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=200.00> CAST BB91 regmask=[x0] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x0] minReg=1 last fixed wt=200.00> BB91 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB91 regmask=[x0] minReg=1 fixed wt=800.00> CNS_INT BB91 regmask=[x11] minReg=1 wt=800.00> BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 last fixed wt=200.00> BB91 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB91 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x0] minReg=1 last fixed wt=200.00> BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB91 regmask=[x0] minReg=1 last wt=200.00> BB91 regmask=[x1] minReg=1 last wt=200.00> BB91 regmask=[x2] minReg=1 last wt=200.00> BB91 regmask=[x3] minReg=1 last wt=200.00> BB91 regmask=[x4] minReg=1 last wt=200.00> BB91 regmask=[x5] minReg=1 last wt=200.00> BB91 regmask=[x6] minReg=1 last wt=200.00> BB91 regmask=[x7] minReg=1 last wt=200.00> BB91 regmask=[x8] minReg=1 last wt=200.00> BB91 regmask=[x9] minReg=1 last wt=200.00> BB91 regmask=[x10] minReg=1 last wt=200.00> BB91 regmask=[x11] minReg=1 last wt=200.00> BB91 regmask=[x12] minReg=1 last wt=200.00> BB91 regmask=[x13] minReg=1 last wt=200.00> BB91 regmask=[x14] minReg=1 last wt=200.00> BB91 regmask=[x15] minReg=1 last wt=200.00> BB91 regmask=[xip0] minReg=1 last wt=200.00> BB91 regmask=[xip1] minReg=1 last wt=200.00> BB91 regmask=[lr] minReg=1 last wt=200.00> BB91 regmask=[x0] minReg=1 wt=200.00> CALL BB91 regmask=[x0] minReg=1 fixed wt=800.00> BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> ADD BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> IND BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=2700.00> CAST BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LSH BB95 regmask=[x2] minReg=1 wt=800.00> BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 last fixed wt=200.00> BB95 regmask=[x2] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x2] minReg=1 fixed wt=800.00> BB95 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB95 regmask=[x0] minReg=1 last fixed wt=400.00> BB95 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x0] minReg=1 fixed wt=800.00> BB95 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB95 regmask=[x1] minReg=1 last fixed wt=1900.00> BB95 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB95 regmask=[x11] minReg=1 wt=800.00> BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 last fixed wt=200.00> BB95 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 last fixed wt=200.00> BB95 regmask=[x0] minReg=1 wt=200.00> BB95 regmask=[x0] minReg=1 last fixed wt=200.00> BB95 regmask=[x1] minReg=1 wt=200.00> BB95 regmask=[x1] minReg=1 last fixed wt=200.00> BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB95 regmask=[x0] minReg=1 last wt=200.00> BB95 regmask=[x1] minReg=1 last wt=200.00> BB95 regmask=[x2] minReg=1 last wt=200.00> BB95 regmask=[x3] minReg=1 last wt=200.00> BB95 regmask=[x4] minReg=1 last wt=200.00> BB95 regmask=[x5] minReg=1 last wt=200.00> BB95 regmask=[x6] minReg=1 last wt=200.00> BB95 regmask=[x7] minReg=1 last wt=200.00> BB95 regmask=[x8] minReg=1 last wt=200.00> BB95 regmask=[x9] minReg=1 last wt=200.00> BB95 regmask=[x10] minReg=1 last wt=200.00> BB95 regmask=[x11] minReg=1 last wt=200.00> BB95 regmask=[x12] minReg=1 last wt=200.00> BB95 regmask=[x13] minReg=1 last wt=200.00> BB95 regmask=[x14] minReg=1 last wt=200.00> BB95 regmask=[x15] minReg=1 last wt=200.00> BB95 regmask=[xip0] minReg=1 last wt=200.00> BB95 regmask=[xip1] minReg=1 last wt=200.00> BB95 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> ADD BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> IND BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> ADD BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> BB100 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> ADD BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> IND BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> ADD BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> IND BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> ADD BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB103 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB104 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB104 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB104 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB106 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> BB107 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> STORE_LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> BFIZ BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> IND BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> ADD BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB111 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB111 regmask=[x0] minReg=1 fixed wt=26550.00> BB111 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x0] minReg=1 fixed wt=200.00> BB111 regmask=[x1] minReg=1 wt=50.00> LCL_VAR BB111 regmask=[x1] minReg=1 last fixed wt=500.00> BB111 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x1] minReg=1 fixed wt=200.00> CNS_INT BB111 regmask=[x11] minReg=1 wt=200.00> BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 last fixed wt=50.00> BB111 regmask=[x11] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x11] minReg=1 fixed wt=200.00> CALL BB111 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB111 regmask=[x0] minReg=1 wt=50.00> BB111 regmask=[x0] minReg=1 last fixed wt=50.00> BB111 regmask=[x1] minReg=1 wt=50.00> BB111 regmask=[x1] minReg=1 last fixed wt=50.00> BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 last fixed wt=50.00> CALL BB111 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB111 regmask=[x0] minReg=1 last wt=50.00> BB111 regmask=[x1] minReg=1 last wt=50.00> BB111 regmask=[x2] minReg=1 last wt=50.00> BB111 regmask=[x3] minReg=1 last wt=50.00> BB111 regmask=[x4] minReg=1 last wt=50.00> BB111 regmask=[x5] minReg=1 last wt=50.00> BB111 regmask=[x6] minReg=1 last wt=50.00> BB111 regmask=[x7] minReg=1 last wt=50.00> BB111 regmask=[x8] minReg=1 last wt=50.00> BB111 regmask=[x9] minReg=1 last wt=50.00> BB111 regmask=[x10] minReg=1 last wt=50.00> BB111 regmask=[x11] minReg=1 last wt=50.00> BB111 regmask=[x12] minReg=1 last wt=50.00> BB111 regmask=[x13] minReg=1 last wt=50.00> BB111 regmask=[x14] minReg=1 last wt=50.00> BB111 regmask=[x15] minReg=1 last wt=50.00> BB111 regmask=[xip0] minReg=1 last wt=50.00> BB111 regmask=[xip1] minReg=1 last wt=50.00> BB111 regmask=[lr] minReg=1 last wt=50.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1500.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> ADD BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB247 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB113 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> CNS_INT BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB114 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB115 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB135 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> IND BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB118 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> CNS_INT BB119 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB119 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB119 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ADD BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=2400.00> CAST BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB121 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> IND BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> IND BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ADD BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB123 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB123 regmask=[x0] minReg=1 fixed wt=26550.00> BB123 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x0] minReg=1 fixed wt=3200.00> BB123 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB123 regmask=[x1] minReg=1 last fixed wt=4800.00> BB123 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB123 regmask=[x11] minReg=1 wt=3200.00> BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 last fixed wt=800.00> BB123 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB123 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB123 regmask=[x0] minReg=1 wt=800.00> BB123 regmask=[x0] minReg=1 last fixed wt=800.00> BB123 regmask=[x1] minReg=1 wt=800.00> BB123 regmask=[x1] minReg=1 last fixed wt=800.00> BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB123 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB123 regmask=[x0] minReg=1 last wt=800.00> BB123 regmask=[x1] minReg=1 last wt=800.00> BB123 regmask=[x2] minReg=1 last wt=800.00> BB123 regmask=[x3] minReg=1 last wt=800.00> BB123 regmask=[x4] minReg=1 last wt=800.00> BB123 regmask=[x5] minReg=1 last wt=800.00> BB123 regmask=[x6] minReg=1 last wt=800.00> BB123 regmask=[x7] minReg=1 last wt=800.00> BB123 regmask=[x8] minReg=1 last wt=800.00> BB123 regmask=[x9] minReg=1 last wt=800.00> BB123 regmask=[x10] minReg=1 last wt=800.00> BB123 regmask=[x11] minReg=1 last wt=800.00> BB123 regmask=[x12] minReg=1 last wt=800.00> BB123 regmask=[x13] minReg=1 last wt=800.00> BB123 regmask=[x14] minReg=1 last wt=800.00> BB123 regmask=[x15] minReg=1 last wt=800.00> BB123 regmask=[xip0] minReg=1 last wt=800.00> BB123 regmask=[xip1] minReg=1 last wt=800.00> BB123 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> IND BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ADD BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB125 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB127 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB129 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BFIZ BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=8000.00> IND BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ADD BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB132 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB132 regmask=[x0] minReg=1 fixed wt=26550.00> BB132 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x0] minReg=1 fixed wt=3200.00> BB132 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB132 regmask=[x1] minReg=1 last fixed wt=8000.00> BB132 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB132 regmask=[x11] minReg=1 wt=3200.00> BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 last fixed wt=800.00> BB132 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB132 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB132 regmask=[x0] minReg=1 wt=800.00> BB132 regmask=[x0] minReg=1 last fixed wt=800.00> BB132 regmask=[x1] minReg=1 wt=800.00> BB132 regmask=[x1] minReg=1 last fixed wt=800.00> BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB132 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB132 regmask=[x0] minReg=1 last wt=800.00> BB132 regmask=[x1] minReg=1 last wt=800.00> BB132 regmask=[x2] minReg=1 last wt=800.00> BB132 regmask=[x3] minReg=1 last wt=800.00> BB132 regmask=[x4] minReg=1 last wt=800.00> BB132 regmask=[x5] minReg=1 last wt=800.00> BB132 regmask=[x6] minReg=1 last wt=800.00> BB132 regmask=[x7] minReg=1 last wt=800.00> BB132 regmask=[x8] minReg=1 last wt=800.00> BB132 regmask=[x9] minReg=1 last wt=800.00> BB132 regmask=[x10] minReg=1 last wt=800.00> BB132 regmask=[x11] minReg=1 last wt=800.00> BB132 regmask=[x12] minReg=1 last wt=800.00> BB132 regmask=[x13] minReg=1 last wt=800.00> BB132 regmask=[x14] minReg=1 last wt=800.00> BB132 regmask=[x15] minReg=1 last wt=800.00> BB132 regmask=[xip0] minReg=1 last wt=800.00> BB132 regmask=[xip1] minReg=1 last wt=800.00> BB132 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> ADD BB133 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> ADD BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> ADD BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB136 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> ADD BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB137 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> ADD BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB138 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB139 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB141 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB142 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> CNS_INT BB143 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB143 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB143 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB144 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB181 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BFIZ BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB185 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB185 regmask=[x0] minReg=1 fixed wt=26550.00> BB185 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x0] minReg=1 fixed wt=800.00> BB185 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB185 regmask=[x1] minReg=1 last fixed wt=2400.00> BB185 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB185 regmask=[x11] minReg=1 wt=800.00> BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 last fixed wt=200.00> BB185 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB185 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB185 regmask=[x0] minReg=1 wt=200.00> BB185 regmask=[x0] minReg=1 last fixed wt=200.00> BB185 regmask=[x1] minReg=1 wt=200.00> BB185 regmask=[x1] minReg=1 last fixed wt=200.00> BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB185 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB185 regmask=[x0] minReg=1 last wt=200.00> BB185 regmask=[x1] minReg=1 last wt=200.00> BB185 regmask=[x2] minReg=1 last wt=200.00> BB185 regmask=[x3] minReg=1 last wt=200.00> BB185 regmask=[x4] minReg=1 last wt=200.00> BB185 regmask=[x5] minReg=1 last wt=200.00> BB185 regmask=[x6] minReg=1 last wt=200.00> BB185 regmask=[x7] minReg=1 last wt=200.00> BB185 regmask=[x8] minReg=1 last wt=200.00> BB185 regmask=[x9] minReg=1 last wt=200.00> BB185 regmask=[x10] minReg=1 last wt=200.00> BB185 regmask=[x11] minReg=1 last wt=200.00> BB185 regmask=[x12] minReg=1 last wt=200.00> BB185 regmask=[x13] minReg=1 last wt=200.00> BB185 regmask=[x14] minReg=1 last wt=200.00> BB185 regmask=[x15] minReg=1 last wt=200.00> BB185 regmask=[xip0] minReg=1 last wt=200.00> BB185 regmask=[xip1] minReg=1 last wt=200.00> BB185 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB200 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ADD BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB204 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB204 regmask=[x0] minReg=1 fixed wt=26550.00> BB204 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x0] minReg=1 fixed wt=800.00> BB204 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB204 regmask=[x1] minReg=1 last fixed wt=1200.00> BB204 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB204 regmask=[x11] minReg=1 wt=800.00> BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 last fixed wt=200.00> BB204 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB204 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB204 regmask=[x0] minReg=1 wt=200.00> BB204 regmask=[x0] minReg=1 last fixed wt=200.00> BB204 regmask=[x1] minReg=1 wt=200.00> BB204 regmask=[x1] minReg=1 last fixed wt=200.00> BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB204 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB204 regmask=[x0] minReg=1 last wt=200.00> BB204 regmask=[x1] minReg=1 last wt=200.00> BB204 regmask=[x2] minReg=1 last wt=200.00> BB204 regmask=[x3] minReg=1 last wt=200.00> BB204 regmask=[x4] minReg=1 last wt=200.00> BB204 regmask=[x5] minReg=1 last wt=200.00> BB204 regmask=[x6] minReg=1 last wt=200.00> BB204 regmask=[x7] minReg=1 last wt=200.00> BB204 regmask=[x8] minReg=1 last wt=200.00> BB204 regmask=[x9] minReg=1 last wt=200.00> BB204 regmask=[x10] minReg=1 last wt=200.00> BB204 regmask=[x11] minReg=1 last wt=200.00> BB204 regmask=[x12] minReg=1 last wt=200.00> BB204 regmask=[x13] minReg=1 last wt=200.00> BB204 regmask=[x14] minReg=1 last wt=200.00> BB204 regmask=[x15] minReg=1 last wt=200.00> BB204 regmask=[xip0] minReg=1 last wt=200.00> BB204 regmask=[xip1] minReg=1 last wt=200.00> BB204 regmask=[lr] minReg=1 last wt=200.00> STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB208 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> NE BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> IND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> NE BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> AND BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB209 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> CNS_INT BB210 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB210 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB210 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB213 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> ADD BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> BB214 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> IND BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB214 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB215 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> ADD BB218 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> ADD BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB220 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> LCL_VAR BB221 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> CNS_INT BB222 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB222 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB222 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB223 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> IND BB223 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB223 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> SUB BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB224 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB225 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> BB226 regmask=[x5] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x5] minReg=1 last fixed wt=600.00> BB226 regmask=[x5] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x5] minReg=1 fixed wt=800.00> BB226 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x0] minReg=1 fixed wt=26550.00> BB226 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x0] minReg=1 fixed wt=800.00> BB226 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x1] minReg=1 fixed wt=2250.00> BB226 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x1] minReg=1 fixed wt=800.00> BB226 regmask=[x2] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x2] minReg=1 last fixed wt=600.00> BB226 regmask=[x2] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x2] minReg=1 fixed wt=800.00> BB226 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x3] minReg=1 last fixed wt=23800.00> BB226 regmask=[x3] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x3] minReg=1 fixed wt=800.00> BB226 regmask=[x4] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x4] minReg=1 last fixed wt=2400.00> BB226 regmask=[x4] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x4] minReg=1 fixed wt=800.00> CNS_INT BB226 regmask=[x11] minReg=1 wt=800.00> BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 last fixed wt=200.00> BB226 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB226 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB226 regmask=[x5] minReg=1 wt=200.00> BB226 regmask=[x5] minReg=1 last fixed wt=200.00> BB226 regmask=[x0] minReg=1 wt=200.00> BB226 regmask=[x0] minReg=1 last fixed wt=200.00> BB226 regmask=[x1] minReg=1 wt=200.00> BB226 regmask=[x1] minReg=1 last fixed wt=200.00> BB226 regmask=[x2] minReg=1 wt=200.00> BB226 regmask=[x2] minReg=1 last fixed wt=200.00> BB226 regmask=[x3] minReg=1 wt=200.00> BB226 regmask=[x3] minReg=1 last fixed wt=200.00> BB226 regmask=[x4] minReg=1 wt=200.00> BB226 regmask=[x4] minReg=1 last fixed wt=200.00> BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB226 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB226 regmask=[x0] minReg=1 last wt=200.00> BB226 regmask=[x1] minReg=1 last wt=200.00> BB226 regmask=[x2] minReg=1 last wt=200.00> BB226 regmask=[x3] minReg=1 last wt=200.00> BB226 regmask=[x4] minReg=1 last wt=200.00> BB226 regmask=[x5] minReg=1 last wt=200.00> BB226 regmask=[x6] minReg=1 last wt=200.00> BB226 regmask=[x7] minReg=1 last wt=200.00> BB226 regmask=[x8] minReg=1 last wt=200.00> BB226 regmask=[x9] minReg=1 last wt=200.00> BB226 regmask=[x10] minReg=1 last wt=200.00> BB226 regmask=[x11] minReg=1 last wt=200.00> BB226 regmask=[x12] minReg=1 last wt=200.00> BB226 regmask=[x13] minReg=1 last wt=200.00> BB226 regmask=[x14] minReg=1 last wt=200.00> BB226 regmask=[x15] minReg=1 last wt=200.00> BB226 regmask=[xip0] minReg=1 last wt=200.00> BB226 regmask=[xip1] minReg=1 last wt=200.00> BB226 regmask=[lr] minReg=1 last wt=200.00> STORE_LCL_VAR BB226 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB227 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB229 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB229 regmask=[x0] minReg=1 fixed wt=26550.00> BB229 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x0] minReg=1 fixed wt=800.00> BB229 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB229 regmask=[x1] minReg=1 last fixed wt=23800.00> BB229 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB229 regmask=[x11] minReg=1 wt=800.00> BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 last fixed wt=200.00> BB229 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB229 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB229 regmask=[x0] minReg=1 wt=200.00> BB229 regmask=[x0] minReg=1 last fixed wt=200.00> BB229 regmask=[x1] minReg=1 wt=200.00> BB229 regmask=[x1] minReg=1 last fixed wt=200.00> BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB229 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB229 regmask=[x0] minReg=1 last wt=200.00> BB229 regmask=[x1] minReg=1 last wt=200.00> BB229 regmask=[x2] minReg=1 last wt=200.00> BB229 regmask=[x3] minReg=1 last wt=200.00> BB229 regmask=[x4] minReg=1 last wt=200.00> BB229 regmask=[x5] minReg=1 last wt=200.00> BB229 regmask=[x6] minReg=1 last wt=200.00> BB229 regmask=[x7] minReg=1 last wt=200.00> BB229 regmask=[x8] minReg=1 last wt=200.00> BB229 regmask=[x9] minReg=1 last wt=200.00> BB229 regmask=[x10] minReg=1 last wt=200.00> BB229 regmask=[x11] minReg=1 last wt=200.00> BB229 regmask=[x12] minReg=1 last wt=200.00> BB229 regmask=[x13] minReg=1 last wt=200.00> BB229 regmask=[x14] minReg=1 last wt=200.00> BB229 regmask=[x15] minReg=1 last wt=200.00> BB229 regmask=[xip0] minReg=1 last wt=200.00> BB229 regmask=[xip1] minReg=1 last wt=200.00> BB229 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB231 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB232 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> ADD BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB235 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB235 regmask=[x0] minReg=1 fixed wt=26550.00> BB235 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x0] minReg=1 fixed wt=800.00> BB235 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB235 regmask=[x1] minReg=1 last fixed wt=1200.00> BB235 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB235 regmask=[x11] minReg=1 wt=800.00> BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 last fixed wt=200.00> BB235 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB235 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB235 regmask=[x0] minReg=1 wt=200.00> BB235 regmask=[x0] minReg=1 last fixed wt=200.00> BB235 regmask=[x1] minReg=1 wt=200.00> BB235 regmask=[x1] minReg=1 last fixed wt=200.00> BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB235 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB235 regmask=[x0] minReg=1 last wt=200.00> BB235 regmask=[x1] minReg=1 last wt=200.00> BB235 regmask=[x2] minReg=1 last wt=200.00> BB235 regmask=[x3] minReg=1 last wt=200.00> BB235 regmask=[x4] minReg=1 last wt=200.00> BB235 regmask=[x5] minReg=1 last wt=200.00> BB235 regmask=[x6] minReg=1 last wt=200.00> BB235 regmask=[x7] minReg=1 last wt=200.00> BB235 regmask=[x8] minReg=1 last wt=200.00> BB235 regmask=[x9] minReg=1 last wt=200.00> BB235 regmask=[x10] minReg=1 last wt=200.00> BB235 regmask=[x11] minReg=1 last wt=200.00> BB235 regmask=[x12] minReg=1 last wt=200.00> BB235 regmask=[x13] minReg=1 last wt=200.00> BB235 regmask=[x14] minReg=1 last wt=200.00> BB235 regmask=[x15] minReg=1 last wt=200.00> BB235 regmask=[xip0] minReg=1 last wt=200.00> BB235 regmask=[xip1] minReg=1 last wt=200.00> BB235 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB240 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ADD BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> IND BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> IND BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ADD BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB238 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB238 regmask=[x0] minReg=1 fixed wt=26550.00> BB238 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x0] minReg=1 fixed wt=3200.00> BB238 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB238 regmask=[x1] minReg=1 last fixed wt=4800.00> BB238 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB238 regmask=[x11] minReg=1 wt=3200.00> BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 last fixed wt=800.00> BB238 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB238 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB238 regmask=[x0] minReg=1 wt=800.00> BB238 regmask=[x0] minReg=1 last fixed wt=800.00> BB238 regmask=[x1] minReg=1 wt=800.00> BB238 regmask=[x1] minReg=1 last fixed wt=800.00> BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB238 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB238 regmask=[x0] minReg=1 last wt=800.00> BB238 regmask=[x1] minReg=1 last wt=800.00> BB238 regmask=[x2] minReg=1 last wt=800.00> BB238 regmask=[x3] minReg=1 last wt=800.00> BB238 regmask=[x4] minReg=1 last wt=800.00> BB238 regmask=[x5] minReg=1 last wt=800.00> BB238 regmask=[x6] minReg=1 last wt=800.00> BB238 regmask=[x7] minReg=1 last wt=800.00> BB238 regmask=[x8] minReg=1 last wt=800.00> BB238 regmask=[x9] minReg=1 last wt=800.00> BB238 regmask=[x10] minReg=1 last wt=800.00> BB238 regmask=[x11] minReg=1 last wt=800.00> BB238 regmask=[x12] minReg=1 last wt=800.00> BB238 regmask=[x13] minReg=1 last wt=800.00> BB238 regmask=[x14] minReg=1 last wt=800.00> BB238 regmask=[x15] minReg=1 last wt=800.00> BB238 regmask=[xip0] minReg=1 last wt=800.00> BB238 regmask=[xip1] minReg=1 last wt=800.00> BB238 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB242 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB244 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB244 regmask=[x0] minReg=1 fixed wt=26550.00> BB244 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x0] minReg=1 fixed wt=800.00> BB244 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB244 regmask=[x1] minReg=1 last fixed wt=23800.00> BB244 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB244 regmask=[x11] minReg=1 wt=800.00> BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 last fixed wt=200.00> BB244 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB244 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB244 regmask=[x0] minReg=1 wt=200.00> BB244 regmask=[x0] minReg=1 last fixed wt=200.00> BB244 regmask=[x1] minReg=1 wt=200.00> BB244 regmask=[x1] minReg=1 last fixed wt=200.00> BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB244 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB244 regmask=[x0] minReg=1 last wt=200.00> BB244 regmask=[x1] minReg=1 last wt=200.00> BB244 regmask=[x2] minReg=1 last wt=200.00> BB244 regmask=[x3] minReg=1 last wt=200.00> BB244 regmask=[x4] minReg=1 last wt=200.00> BB244 regmask=[x5] minReg=1 last wt=200.00> BB244 regmask=[x6] minReg=1 last wt=200.00> BB244 regmask=[x7] minReg=1 last wt=200.00> BB244 regmask=[x8] minReg=1 last wt=200.00> BB244 regmask=[x9] minReg=1 last wt=200.00> BB244 regmask=[x10] minReg=1 last wt=200.00> BB244 regmask=[x11] minReg=1 last wt=200.00> BB244 regmask=[x12] minReg=1 last wt=200.00> BB244 regmask=[x13] minReg=1 last wt=200.00> BB244 regmask=[x14] minReg=1 last wt=200.00> BB244 regmask=[x15] minReg=1 last wt=200.00> BB244 regmask=[xip0] minReg=1 last wt=200.00> BB244 regmask=[xip1] minReg=1 last wt=200.00> BB244 regmask=[lr] minReg=1 last wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> IND BB248 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> IND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> NE BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LE BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> AND BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=50.00> LCL_VAR BB251 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> IND BB251 regmask=[x2] minReg=1 wt=200.00> BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 last fixed wt=50.00> BB251 regmask=[x2] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x2] minReg=1 fixed wt=200.00> BB251 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB251 regmask=[x0] minReg=1 last fixed wt=26550.00> BB251 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x0] minReg=1 fixed wt=200.00> CNS_INT BB251 regmask=[x11] minReg=1 wt=200.00> BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 last fixed wt=50.00> BB251 regmask=[x11] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x11] minReg=1 fixed wt=200.00> CNS_INT BB251 regmask=[x1] minReg=1 wt=200.00> BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 last fixed wt=50.00> BB251 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x1] minReg=1 fixed wt=200.00> CALL BB251 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 last fixed wt=50.00> BB251 regmask=[x0] minReg=1 wt=50.00> BB251 regmask=[x0] minReg=1 last fixed wt=50.00> BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 last fixed wt=50.00> BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 last fixed wt=50.00> CALL BB251 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB251 regmask=[x0] minReg=1 last wt=50.00> BB251 regmask=[x1] minReg=1 last wt=50.00> BB251 regmask=[x2] minReg=1 last wt=50.00> BB251 regmask=[x3] minReg=1 last wt=50.00> BB251 regmask=[x4] minReg=1 last wt=50.00> BB251 regmask=[x5] minReg=1 last wt=50.00> BB251 regmask=[x6] minReg=1 last wt=50.00> BB251 regmask=[x7] minReg=1 last wt=50.00> BB251 regmask=[x8] minReg=1 last wt=50.00> BB251 regmask=[x9] minReg=1 last wt=50.00> BB251 regmask=[x10] minReg=1 last wt=50.00> BB251 regmask=[x11] minReg=1 last wt=50.00> BB251 regmask=[x12] minReg=1 last wt=50.00> BB251 regmask=[x13] minReg=1 last wt=50.00> BB251 regmask=[x14] minReg=1 last wt=50.00> BB251 regmask=[x15] minReg=1 last wt=50.00> BB251 regmask=[xip0] minReg=1 last wt=50.00> BB251 regmask=[xip1] minReg=1 last wt=50.00> BB251 regmask=[lr] minReg=1 last wt=50.00> LCL_VAR BB255 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=4800.00> CAST BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> JMPTABLE BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> SWITCH_TABLE BB255 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB255 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB255 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> ADD BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> ADD BB30 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> BB31 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=19200.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=19200.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> ADD BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=19200.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB256 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=4800.00> CAST BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> JMPTABLE BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> SWITCH_TABLE BB256 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB256 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB256 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> CNS_INT BB18 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB18 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> BB18 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> ADD BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB21 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB21 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB24 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> ADD BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> CNS_INT BB28 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB28 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB28 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> CNS_INT BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB257 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=1200.00> CAST BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> JMPTABLE BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> SWITCH_TABLE BB257 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB257 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB257 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB145 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> ADD BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> STORE_LCL_VAR BB147 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> CNS_INT BB148 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB148 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB148 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=600.00> CAST BB149 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB149 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB150 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> IND BB150 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB150 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> STORE_LCL_VAR BB152 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> CNS_INT BB153 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB153 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB153 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> ADD BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=800.00> CAST BB155 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB155 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB156 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB157 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB159 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB159 regmask=[x0] minReg=1 fixed wt=26550.00> BB159 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x0] minReg=1 fixed wt=800.00> BB159 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB159 regmask=[x1] minReg=1 last fixed wt=23800.00> BB159 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB159 regmask=[x11] minReg=1 wt=800.00> BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 last fixed wt=200.00> BB159 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB159 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB159 regmask=[x0] minReg=1 wt=200.00> BB159 regmask=[x0] minReg=1 last fixed wt=200.00> BB159 regmask=[x1] minReg=1 wt=200.00> BB159 regmask=[x1] minReg=1 last fixed wt=200.00> BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB159 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB159 regmask=[x0] minReg=1 last wt=200.00> BB159 regmask=[x1] minReg=1 last wt=200.00> BB159 regmask=[x2] minReg=1 last wt=200.00> BB159 regmask=[x3] minReg=1 last wt=200.00> BB159 regmask=[x4] minReg=1 last wt=200.00> BB159 regmask=[x5] minReg=1 last wt=200.00> BB159 regmask=[x6] minReg=1 last wt=200.00> BB159 regmask=[x7] minReg=1 last wt=200.00> BB159 regmask=[x8] minReg=1 last wt=200.00> BB159 regmask=[x9] minReg=1 last wt=200.00> BB159 regmask=[x10] minReg=1 last wt=200.00> BB159 regmask=[x11] minReg=1 last wt=200.00> BB159 regmask=[x12] minReg=1 last wt=200.00> BB159 regmask=[x13] minReg=1 last wt=200.00> BB159 regmask=[x14] minReg=1 last wt=200.00> BB159 regmask=[x15] minReg=1 last wt=200.00> BB159 regmask=[xip0] minReg=1 last wt=200.00> BB159 regmask=[xip1] minReg=1 last wt=200.00> BB159 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> IND BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB161 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB163 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB165 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BFIZ BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB168 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB168 regmask=[x0] minReg=1 fixed wt=26550.00> BB168 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x0] minReg=1 fixed wt=800.00> BB168 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB168 regmask=[x1] minReg=1 last fixed wt=2400.00> BB168 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB168 regmask=[x11] minReg=1 wt=800.00> BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 last fixed wt=200.00> BB168 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB168 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB168 regmask=[x0] minReg=1 wt=200.00> BB168 regmask=[x0] minReg=1 last fixed wt=200.00> BB168 regmask=[x1] minReg=1 wt=200.00> BB168 regmask=[x1] minReg=1 last fixed wt=200.00> BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB168 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB168 regmask=[x0] minReg=1 last wt=200.00> BB168 regmask=[x1] minReg=1 last wt=200.00> BB168 regmask=[x2] minReg=1 last wt=200.00> BB168 regmask=[x3] minReg=1 last wt=200.00> BB168 regmask=[x4] minReg=1 last wt=200.00> BB168 regmask=[x5] minReg=1 last wt=200.00> BB168 regmask=[x6] minReg=1 last wt=200.00> BB168 regmask=[x7] minReg=1 last wt=200.00> BB168 regmask=[x8] minReg=1 last wt=200.00> BB168 regmask=[x9] minReg=1 last wt=200.00> BB168 regmask=[x10] minReg=1 last wt=200.00> BB168 regmask=[x11] minReg=1 last wt=200.00> BB168 regmask=[x12] minReg=1 last wt=200.00> BB168 regmask=[x13] minReg=1 last wt=200.00> BB168 regmask=[x14] minReg=1 last wt=200.00> BB168 regmask=[x15] minReg=1 last wt=200.00> BB168 regmask=[xip0] minReg=1 last wt=200.00> BB168 regmask=[xip1] minReg=1 last wt=200.00> BB168 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> ADD BB169 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> ADD BB170 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB186 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BFIZ BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB190 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB190 regmask=[x0] minReg=1 fixed wt=26550.00> BB190 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x0] minReg=1 fixed wt=800.00> BB190 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB190 regmask=[x1] minReg=1 last fixed wt=2400.00> BB190 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB190 regmask=[x11] minReg=1 wt=800.00> BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 last fixed wt=200.00> BB190 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB190 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB190 regmask=[x0] minReg=1 wt=200.00> BB190 regmask=[x0] minReg=1 last fixed wt=200.00> BB190 regmask=[x1] minReg=1 wt=200.00> BB190 regmask=[x1] minReg=1 last fixed wt=200.00> BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB190 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB190 regmask=[x0] minReg=1 last wt=200.00> BB190 regmask=[x1] minReg=1 last wt=200.00> BB190 regmask=[x2] minReg=1 last wt=200.00> BB190 regmask=[x3] minReg=1 last wt=200.00> BB190 regmask=[x4] minReg=1 last wt=200.00> BB190 regmask=[x5] minReg=1 last wt=200.00> BB190 regmask=[x6] minReg=1 last wt=200.00> BB190 regmask=[x7] minReg=1 last wt=200.00> BB190 regmask=[x8] minReg=1 last wt=200.00> BB190 regmask=[x9] minReg=1 last wt=200.00> BB190 regmask=[x10] minReg=1 last wt=200.00> BB190 regmask=[x11] minReg=1 last wt=200.00> BB190 regmask=[x12] minReg=1 last wt=200.00> BB190 regmask=[x13] minReg=1 last wt=200.00> BB190 regmask=[x14] minReg=1 last wt=200.00> BB190 regmask=[x15] minReg=1 last wt=200.00> BB190 regmask=[xip0] minReg=1 last wt=200.00> BB190 regmask=[xip1] minReg=1 last wt=200.00> BB190 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> BB195 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> ADD BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> IND BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> IND BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> ADD BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB193 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB193 regmask=[x0] minReg=1 fixed wt=26550.00> BB193 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x0] minReg=1 fixed wt=3200.00> BB193 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB193 regmask=[x1] minReg=1 last fixed wt=4800.00> BB193 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB193 regmask=[x11] minReg=1 wt=3200.00> BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 last fixed wt=800.00> BB193 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB193 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> BB193 regmask=[x0] minReg=1 wt=800.00> BB193 regmask=[x0] minReg=1 last fixed wt=800.00> BB193 regmask=[x1] minReg=1 wt=800.00> BB193 regmask=[x1] minReg=1 last fixed wt=800.00> BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB193 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> BB193 regmask=[x0] minReg=1 last wt=800.00> BB193 regmask=[x1] minReg=1 last wt=800.00> BB193 regmask=[x2] minReg=1 last wt=800.00> BB193 regmask=[x3] minReg=1 last wt=800.00> BB193 regmask=[x4] minReg=1 last wt=800.00> BB193 regmask=[x5] minReg=1 last wt=800.00> BB193 regmask=[x6] minReg=1 last wt=800.00> BB193 regmask=[x7] minReg=1 last wt=800.00> BB193 regmask=[x8] minReg=1 last wt=800.00> BB193 regmask=[x9] minReg=1 last wt=800.00> BB193 regmask=[x10] minReg=1 last wt=800.00> BB193 regmask=[x11] minReg=1 last wt=800.00> BB193 regmask=[x12] minReg=1 last wt=800.00> BB193 regmask=[x13] minReg=1 last wt=800.00> BB193 regmask=[x14] minReg=1 last wt=800.00> BB193 regmask=[x15] minReg=1 last wt=800.00> BB193 regmask=[xip0] minReg=1 last wt=800.00> BB193 regmask=[xip1] minReg=1 last wt=800.00> BB193 regmask=[lr] minReg=1 last wt=800.00> BB193 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> IND BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> ADD BB199 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB258 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=1200.00> CAST BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> JMPTABLE BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> SWITCH_TABLE BB258 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> NE BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB171 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> OR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB171 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB172 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> IND BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> IND BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB174 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> IND BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB176 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> BFIZ BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> IND BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> ADD BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> BB179 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB179 regmask=[x0] minReg=1 fixed wt=26550.00> BB179 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x0] minReg=1 fixed wt=800.00> BB179 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB179 regmask=[x1] minReg=1 last fixed wt=2400.00> BB179 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB179 regmask=[x11] minReg=1 wt=800.00> BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 last fixed wt=200.00> BB179 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB179 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB179 regmask=[x0] minReg=1 wt=200.00> BB179 regmask=[x0] minReg=1 last fixed wt=200.00> BB179 regmask=[x1] minReg=1 wt=200.00> BB179 regmask=[x1] minReg=1 last fixed wt=200.00> BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB179 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> BB179 regmask=[x0] minReg=1 last wt=200.00> BB179 regmask=[x1] minReg=1 last wt=200.00> BB179 regmask=[x2] minReg=1 last wt=200.00> BB179 regmask=[x3] minReg=1 last wt=200.00> BB179 regmask=[x4] minReg=1 last wt=200.00> BB179 regmask=[x5] minReg=1 last wt=200.00> BB179 regmask=[x6] minReg=1 last wt=200.00> BB179 regmask=[x7] minReg=1 last wt=200.00> BB179 regmask=[x8] minReg=1 last wt=200.00> BB179 regmask=[x9] minReg=1 last wt=200.00> BB179 regmask=[x10] minReg=1 last wt=200.00> BB179 regmask=[x11] minReg=1 last wt=200.00> BB179 regmask=[x12] minReg=1 last wt=200.00> BB179 regmask=[x13] minReg=1 last wt=200.00> BB179 regmask=[x14] minReg=1 last wt=200.00> BB179 regmask=[x15] minReg=1 last wt=200.00> BB179 regmask=[xip0] minReg=1 last wt=200.00> BB179 regmask=[xip1] minReg=1 last wt=200.00> BB179 regmask=[lr] minReg=1 last wt=200.00> CNS_INT BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> STORE_LCL_VAR BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> CNS_INT BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 last fixed wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> PUTARG_REG BB110 regmask=[x11] minReg=1 fixed wt=0.00> CALL BB110 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 last fixed wt=0.00> CALL BB110 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> BB110 regmask=[x0] minReg=1 last wt=0.00> BB110 regmask=[x1] minReg=1 last wt=0.00> BB110 regmask=[x2] minReg=1 last wt=0.00> BB110 regmask=[x3] minReg=1 last wt=0.00> BB110 regmask=[x4] minReg=1 last wt=0.00> BB110 regmask=[x5] minReg=1 last wt=0.00> BB110 regmask=[x6] minReg=1 last wt=0.00> BB110 regmask=[x7] minReg=1 last wt=0.00> BB110 regmask=[x8] minReg=1 last wt=0.00> BB110 regmask=[x9] minReg=1 last wt=0.00> BB110 regmask=[x10] minReg=1 last wt=0.00> BB110 regmask=[x11] minReg=1 last wt=0.00> BB110 regmask=[x12] minReg=1 last wt=0.00> BB110 regmask=[x13] minReg=1 last wt=0.00> BB110 regmask=[x14] minReg=1 last wt=0.00> BB110 regmask=[x15] minReg=1 last wt=0.00> BB110 regmask=[xip0] minReg=1 last wt=0.00> BB110 regmask=[xip1] minReg=1 last wt=0.00> BB110 regmask=[lr] minReg=1 last wt=0.00> CNS_INT BB254 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB254 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> IND BB254 regmask=[x0-xip0 x19-x28] minReg=1 wt=0.00> BB254 regmask=[x0-xip0 x19-x28] minReg=1 last wt=0.00> BB254 regmask=[x0] minReg=1 last wt=0.00> BB254 regmask=[x1] minReg=1 last wt=0.00> BB254 regmask=[x2] minReg=1 last wt=0.00> BB254 regmask=[x3] minReg=1 last wt=0.00> BB254 regmask=[x4] minReg=1 last wt=0.00> BB254 regmask=[x5] minReg=1 last wt=0.00> BB254 regmask=[x6] minReg=1 last wt=0.00> BB254 regmask=[x7] minReg=1 last wt=0.00> BB254 regmask=[x8] minReg=1 last wt=0.00> BB254 regmask=[x9] minReg=1 last wt=0.00> BB254 regmask=[x10] minReg=1 last wt=0.00> BB254 regmask=[x11] minReg=1 last wt=0.00> BB254 regmask=[x12] minReg=1 last wt=0.00> BB254 regmask=[x13] minReg=1 last wt=0.00> BB254 regmask=[x14] minReg=1 last wt=0.00> BB254 regmask=[x15] minReg=1 last wt=0.00> BB254 regmask=[xip0] minReg=1 last wt=0.00> BB254 regmask=[xip1] minReg=1 last wt=0.00> BB254 regmask=[lr] minReg=1 last wt=0.00> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB111 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB123 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB132 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB185 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB204 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB226 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB229 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB235 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB238 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB244 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB251 regmask=[x0] minReg=1 last fixed wt=26550.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB159 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB168 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB190 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB193 regmask=[x0] minReg=1 fixed wt=26550.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=26550.00> LCL_VAR BB179 regmask=[x0] minReg=1 fixed wt=26550.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V01 (Interval 1) BB00 regmask=[x1] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 fixed wt=2150.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB60 regmask=[x0] minReg=1 fixed wt=2150.00> LCL_VAR BB63 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB64 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB65 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB104 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 wt=2150.00> LCL_VAR BB249 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2150.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V02 --- V03 (Interval 2) BB00 regmask=[x4] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB226 regmask=[x1] minReg=1 fixed wt=2250.00> LCL_VAR BB251 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2250.00> LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2250.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V04 (Interval 3) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB17 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V05 (Interval 4) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB50 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> STORE_LCL_VAR BB51 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB21 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB21 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB22 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB23 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V06 (Interval 5) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3000.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB18 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> STORE_LCL_VAR BB19 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=3000.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V07 (Interval 6) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2300.00> STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB20 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> LCL_VAR BB172 regmask=[x0-xip0 x19-x28] minReg=1 wt=2300.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V08 (Interval 7) STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB151 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4750.00> STORE_LCL_VAR BB170 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=4750.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V09 (Interval 8) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB46 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB226 regmask=[x0-xip0 x19-x28] minReg=1 wt=2500.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V10 (Interval 9) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB52 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB53 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> LCL_VAR BB24 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V11 (Interval 10) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB62 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2700.00> STORE_LCL_VAR BB27 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB29 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V12 (Interval 11) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> STORE_LCL_VAR BB55 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB124 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB28 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> LCL_VAR BB160 regmask=[x0-xip0 x19-x28] minReg=1 wt=2900.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V13 (Interval 12) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> STORE_LCL_VAR BB16 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> STORE_LCL_VAR BB54 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> STORE_LCL_VAR BB30 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V14 (Interval 13) STORE_LCL_VAR BB73 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB113 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB135 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> STORE_LCL_VAR BB134 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB145 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4200.00> STORE_LCL_VAR BB146 regmask=[x0-xip0 x19-x28] minReg=1 wt=4200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V15 (Interval 14) STORE_LCL_VAR BB06 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> STORE_LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB248 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1900.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V16 (Interval 15) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB36 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB61 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB62 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB103 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 last wt=91400.00> STORE_LCL_VAR BB199 regmask=[x0-xip0 x19-x28] minReg=1 wt=91400.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V17 (Interval 16) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB56 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB60 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> LCL_VAR BB223 regmask=[x0-xip0 x19-x28] minReg=1 wt=1700.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V18 (Interval 17) STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB49 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB08 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB11 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB13 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB14 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB15 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB247 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB114 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB115 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB136 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB139 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB141 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB142 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB143 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB226 regmask=[x3] minReg=1 last fixed wt=23800.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB229 regmask=[x1] minReg=1 last fixed wt=23800.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB244 regmask=[x1] minReg=1 last fixed wt=23800.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> STORE_LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> STORE_LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB156 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=23800.00> LCL_VAR BB159 regmask=[x1] minReg=1 last fixed wt=23800.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 wt=23800.00> BB193 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V19 --- V20 (Interval 18) STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> STORE_LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> STORE_LCL_VAR BB133 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 last wt=7100.00> STORE_LCL_VAR BB169 regmask=[x0-xip0 x19-x28] minReg=1 wt=7100.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V21 (Interval 19) STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB171 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB180 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V22 (Interval 20) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB43 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> LCL_VAR BB45 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=18400.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V23 --- V24 --- V25 --- V26 (Interval 21) STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=550.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V27 (Interval 22) STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1250.00> STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1250.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V28 (Interval 23) STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> STORE_LCL_VAR BB81 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1750.00> STORE_LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1750.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V29 (Interval 24) STORE_LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB79 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V30 (Interval 25) STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB89 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> STORE_LCL_VAR BB101 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=1100.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V31 (Interval 26) STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> --- V32 (Interval 27) STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB102 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V33 (Interval 28) STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V34 (Interval 29) STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB214 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB220 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=6700.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V35 --- V36 (Interval 30) STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB150 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3300.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> LCL_VAR BB173 regmask=[x0-xip0 x19-x28] minReg=1 wt=3300.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V37 (Interval 31) STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB210 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB226 regmask=[x5] minReg=1 last fixed wt=600.00> --- V38 (Interval 32) STORE_LCL_VAR BB205 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> STORE_LCL_VAR BB218 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB221 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> STORE_LCL_VAR BB222 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB226 regmask=[x4] minReg=1 last fixed wt=2400.00> --- V39 --- V40 --- V41 --- V42 --- V43 (Interval 33) STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x2] minReg=1 last fixed wt=250.00> --- V44 (Interval 34) STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> --- V45 (Interval 35) STORE_LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> --- V46 (Interval 36) STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> --- V47 --- V48 --- V49 (Interval 37) STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> --- V50 (Interval 38) STORE_LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB246 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> --- V51 (Interval 39) STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> --- V52 (Interval 40) STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> --- V53 (Interval 41) STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> --- V54 (Interval 42) STORE_LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> --- V55 (Interval 43) STORE_LCL_VAR BB224 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB225 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB226 regmask=[x2] minReg=1 last fixed wt=600.00> --- V56 (Interval 44) STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V57 (Interval 45) STORE_LCL_VAR BB152 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> STORE_LCL_VAR BB153 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> STORE_LCL_VAR BB154 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB155 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=800.00> --- V58 (Interval 46) STORE_LCL_VAR BB147 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> STORE_LCL_VAR BB148 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB149 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=600.00> --- V59 (Interval 47) STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> --- V60 --- V61 (Interval 48) STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> --- V62 --- V63 (Interval 49) STORE_LCL_VAR BB119 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> STORE_LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=2400.00> --- V64 (Interval 50) STORE_LCL_VAR BB82 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> --- V65 (Interval 51) STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> --- V66 (Interval 52) STORE_LCL_VAR BB83 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> STORE_LCL_VAR BB84 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> --- V67 (Interval 53) STORE_LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 wt=100.00> LCL_VAR BB85 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> --- V68 --- V69 (Interval 54) STORE_LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> --- V70 (Interval 55) STORE_LCL_VAR BB58 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> STORE_LCL_VAR BB59 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB60 regmask=[x1] minReg=1 last fixed wt=800.00> --- V71 (Interval 56) STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=9600.00> --- V72 (Interval 57) STORE_LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 wt=6400.00> LCL_VAR BB48 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6400.00> --- V73 (Interval 58) STORE_LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> --- V74 (Interval 59) STORE_LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 wt=25600.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=25600.00> --- V75 --- V76 (Interval 60) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=600.00> --- V77 --- V78 --- V79 --- V80 --- V81 --- V82 --- V83 (Interval 61) STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> --- V84 --- V85 --- V86 (Interval 62) STORE_LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB106 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> LCL_VAR BB111 regmask=[x1] minReg=1 last fixed wt=500.00> --- V87 (Interval 63) STORE_LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB107 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=250.00> --- V88 (Interval 64) STORE_LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> --- V89 --- V90 --- V91 (Interval 65) STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> --- V92 (Interval 66) STORE_LCL_VAR BB121 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB123 regmask=[x1] minReg=1 last fixed wt=4800.00> --- V93 (Interval 67) STORE_LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> --- V94 --- V95 (Interval 68) STORE_LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB127 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=8000.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=8000.00> LCL_VAR BB132 regmask=[x1] minReg=1 last fixed wt=8000.00> --- V96 (Interval 69) STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> --- V97 (Interval 70) STORE_LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> --- V98 --- V99 (Interval 71) STORE_LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB157 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V100 (Interval 72) STORE_LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V101 --- V102 (Interval 73) STORE_LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB163 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB168 regmask=[x1] minReg=1 last fixed wt=2400.00> --- V103 (Interval 74) STORE_LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB165 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V104 (Interval 75) STORE_LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V105 --- V106 (Interval 76) STORE_LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB174 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB179 regmask=[x1] minReg=1 last fixed wt=2400.00> --- V107 (Interval 77) STORE_LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB176 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V108 (Interval 78) STORE_LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V109 --- V110 (Interval 79) STORE_LCL_VAR BB144 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB181 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> BB182 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB185 regmask=[x1] minReg=1 last fixed wt=2400.00> --- V111 (Interval 80) STORE_LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB182 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V112 (Interval 81) STORE_LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V113 --- V114 (Interval 82) STORE_LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB186 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> BB187 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> LCL_VAR BB190 regmask=[x1] minReg=1 last fixed wt=2400.00> --- V115 (Interval 83) STORE_LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB187 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V116 (Interval 84) STORE_LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V117 --- V118 (Interval 85) STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> --- V119 (Interval 86) STORE_LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB193 regmask=[x1] minReg=1 last fixed wt=4800.00> --- V120 (Interval 87) STORE_LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> --- V121 --- V122 (Interval 88) STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V123 (Interval 89) STORE_LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> LCL_VAR BB204 regmask=[x1] minReg=1 last fixed wt=1200.00> --- V124 (Interval 90) STORE_LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V125 --- V126 (Interval 91) STORE_LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB215 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V127 (Interval 92) STORE_LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V128 --- V129 (Interval 93) STORE_LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB227 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V130 (Interval 94) STORE_LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V131 --- V132 (Interval 95) STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V133 (Interval 96) STORE_LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> LCL_VAR BB235 regmask=[x1] minReg=1 last fixed wt=1200.00> --- V134 (Interval 97) STORE_LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V135 --- V136 (Interval 98) STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> --- V137 (Interval 99) STORE_LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> LCL_VAR BB238 regmask=[x1] minReg=1 last fixed wt=4800.00> --- V138 (Interval 100) STORE_LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4800.00> --- V139 --- V140 (Interval 101) STORE_LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB242 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1000.00> --- V141 (Interval 102) STORE_LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1200.00> --- V142 --- V143 (Interval 103) STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB95 regmask=[x1] minReg=1 last fixed wt=1900.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=1900.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V144 (Interval 104) STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB90 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=2700.00> STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB100 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> LCL_VAR BB125 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x0-xip0 x19-x28] minReg=1 wt=2700.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V145 --- V146 --- V147 (Interval 105) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> --- V148 (Interval 106) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> --- V149 (Interval 107) STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x0] minReg=1 last fixed wt=250.00> --- V150 (Interval 108) STORE_LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x0-xip0 x19-x28] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x1] minReg=1 last fixed wt=250.00> --- V151 (Interval 109) STORE_LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB78 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> --- V152 --- V153 --- V154 --- V155 (Interval 110) STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> --- V156 (Interval 111) STORE_LCL_VAR BB02 regmask=[x0-xip0 x19-x28] minReg=1 wt=150.00> LCL_VAR BB03 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> LCL_VAR BB04 regmask=[x0-xip0 x19-x28] minReg=1 last wt=150.00> --- V157 (Interval 112) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> --- V158 --- V159 (Interval 113) STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> --- V160 (Interval 114) STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> --- V161 (Interval 115) STORE_LCL_VAR BB91 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0] minReg=1 last fixed wt=400.00> --- V162 --- V163 (Interval 116) STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> --- V164 (Interval 117) STORE_LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> --- V165 (Interval 118) STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> --- V166 --- V167 (Interval 119) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> --- V168 (Interval 120) STORE_LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=3200.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 last wt=3200.00> --- V169 (Interval 121) STORE_LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=400.00> --- V170 --- V171 (Interval 122) STORE_LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=19200.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=19200.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x0-xip0 x19-x28] minReg=1 last wt=19200.00> --- V172 (Interval 123) STORE_LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB195 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB191 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> STORE_LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 wt=6000.00> LCL_VAR BB198 regmask=[x0-xip0 x19-x28] minReg=1 last wt=6000.00> --- V173 (Interval 124) STORE_LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB240 regmask=[x0-xip0 x19-x28] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x0-xip0 x19-x28] minReg=1 last wt=4000.00> --- V174 (Interval 125) STORE_LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> STORE_LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB39 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> STORE_LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB41 regmask=[x0-xip0 x19-x28] minReg=1 wt=5600.00> LCL_VAR BB42 regmask=[x0-xip0 x19-x28] minReg=1 last wt=5600.00> --- V175 (Interval 126) STORE_LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB231 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB232 regmask=[x0-xip0 x19-x28] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x0-xip0 x19-x28] minReg=1 last wt=800.00> --- V176 (Interval 127) STORE_LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> BB201 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB201 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB207 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> STORE_LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB209 regmask=[x0-xip0 x19-x28] minReg=1 wt=1600.00> LCL_VAR BB213 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1600.00> --- V177 (Interval 128) STORE_LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB118 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB120 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> --- V178 (Interval 129) STORE_LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> --- V179 (Interval 130) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB47 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB35 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB38 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB40 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB44 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB245 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB200 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB206 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB208 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB219 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB230 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB239 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB31 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB194 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> LCL_VAR BB197 regmask=[x0-xip0 x19-x28] minReg=1 wt=28400.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V180 (Interval 131) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> LCL_VAR BB07 regmask=[x0-xip0 x19-x28] minReg=1 wt=1500.00> LCL_VAR BB61 regmask=[x0] minReg=1 fixed wt=1500.00> LCL_VAR BB112 regmask=[x0-xip0 x19-x28] minReg=1 last wt=1500.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V181 (Interval 132) STORE_LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x0-xip0 x19-x28] minReg=1 wt=2400.00> LCL_VAR BB130 regmask=[x0-xip0 x19-x28] minReg=1 last wt=2400.00> --- V182 (Interval 133) STORE_LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB09 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB255 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=4800.00> --- V183 (Interval 134) STORE_LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x0-xip0 x19-x28] minReg=1 wt=4800.00> LCL_VAR BB256 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=4800.00> --- V184 (Interval 135) STORE_LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB137 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB257 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=1200.00> --- V185 (Interval 136) STORE_LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x0-xip0 x19-x28] minReg=1 wt=1200.00> LCL_VAR BB258 regmask=[x0-xip0 x19-x28] minReg=1 last regOptional wt=1200.00> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use, Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register, (b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc, '(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive. Columns are only printed up to the last modified register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ |V0 a|V1 a| | |V3 a| | | | | | 0.#0 V0 Parm ORDER(A) x19 | |V1 a| | |V3 a| | | |V0 a| | 0.#1 V3 Parm ORDER(A) x20 | |V1 a| | | | | | |V0 a|V3 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 |x21 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#2 V1 Parm ORDER(A) x21 | | | | | | | | |V0 a|V3 a|V1 a| 1.#3 BB1 PredBB0 | | | | | | | | |V0 a|V3 a|V1 a| [004185] 7.#4 x0 Fixd Keep x0 | | | | | | | | |V0 a|V3 a|V1 a| 7.#5 V1 Use Copy x0 |V1 a| | | | | | | |V0 a|V3 a|V1 a| 8.#6 x0 Fixd Keep x0 |V1 a| | | | | | | |V0 a|V3 a|V1 a| 8.#7 I137 Def Alloc x0 |I137a| | | | | | | |V0 a|V3 a|V1 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [002543] 10.#8 C138 Def Alloc x11 |I137a| | | | | | | |C138a|V0 a|V3 a|V1 a| [004186] 11.#9 x11 Fixd Keep x11 |I137a| | | | | | | |C138a|V0 a|V3 a|V1 a| 11.#10 C138 Use * Keep x11 |I137a| | | | | | | |C138a|V0 a|V3 a|V1 a| 12.#11 x11 Fixd Keep x11 |I137a| | | | | | | | |V0 a|V3 a|V1 a| 12.#12 I139 Def Alloc x11 |I137a| | | | | | | |I139a|V0 a|V3 a|V1 a| [000001] 13.#13 I140 Def ORDER(A) x1 |I137a|I140a| | | | | | |I139a|V0 a|V3 a|V1 a| 13.#14 x0 Fixd Keep x0 |I137a|I140a| | | | | | |I139a|V0 a|V3 a|V1 a| 13.#15 I137 Use * Keep x0 |I137a|I140a| | | | | | |I139a|V0 a|V3 a|V1 a| 13.#16 x11 Fixd Keep x11 |I137a|I140a| | | | | | |I139a|V0 a|V3 a|V1 a| 13.#17 I139 Use * Keep x11 |I137a|I140a| | | | | | |I139a|V0 a|V3 a|V1 a| 13.#18 I140 Use * Keep x1 |I137a|I140a| | | | | | |I139a|V0 a|V3 a|V1 a| 14.#19 x0 Kill Keep x0 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#20 x1 Kill Keep x1 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#21 x2 Kill Keep x2 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#22 x3 Kill Keep x3 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#23 x4 Kill Keep x4 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#24 x5 Kill Keep x5 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#25 x6 Kill Keep x6 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#26 x7 Kill Keep x7 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#27 x8 Kill Keep x8 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#28 x9 Kill Keep x9 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#29 x10 Kill Keep x10 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#30 x11 Kill Keep x11 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#31 x12 Kill Keep x12 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#32 x13 Kill Keep x13 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#33 x14 Kill Keep x14 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#34 x15 Kill Keep x15 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#35 xip0 Kill Keep xip0 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#36 xip1 Kill Keep xip1 | | | | | | | | | |V0 a|V3 a|V1 a| 14.#37 lr Kill Keep lr | | | | | | | | | |V0 a|V3 a|V1 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [000004] 20.#38 V11 Def ORDER(A) x22 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| [002548] 27.#39 V1 Use Keep x21 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| 28.#40 I141 Def BSFIT(A) x0 |I141a| | | | | | | | |V0 a|V3 a|V1 a|V11 a| [001500] 29.#41 I141 Use * Keep x0 |I141a| | | | | | | | |V0 a|V3 a|V1 a|V11 a| 30.#42 V76 Def COVRS(A) x0 |V76 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a| [001503] 39.#43 V76 Use Keep x0 |V76 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a| 40.#44 I142 Def BSFIT(A) x1 |V76 a|I142a| | | | | | | |V0 a|V3 a|V1 a|V11 a| [001504] 41.#45 I142 Use * Keep x1 |V76 a|I142a| | | | | | | |V0 a|V3 a|V1 a|V11 a| [001505] 45.#46 V76 Use * Keep x0 |V76 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 46.#47 I143 Def ORDER(A) x23 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|I143a| [002551] 47.#48 I143 Use * Keep x23 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|I143a| 48.#49 V167 Def COVRS(A) x23 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V167a| [000009] 51.#50 V167 Use * Keep x23 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V167a| 52.#51 V17 Def COVRS(A) x23 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [002558] 54.#52 I144 Def ORDER(A) x24 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|I144a| [003709] 55.#53 I144 Use * Keep x24 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|I144a| 56.#54 V180 Def COVRS(A) x24 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a| [002559] 59.#55 V180 Use Keep x24 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a| 60.#56 V147 Def COREL(A) x0 |V147a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [002561] 62.#57 I145 Def ORDER(A) x25 |V147a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|I145a| [003689] 63.#58 I145 Use * Keep x25 |V147a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|I145a| 64.#59 V179 Def COVRS(A) x25 |V147a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002562] 67.#60 V179 Use Keep x25 |V147a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 68.#61 V148 Def COREL(A) x1 |V147a|V148a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [000012] 73.#62 V17 Use Keep x23 |V147a|V148a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 74.#63 I146 Def BSFIT(A) x2 |V147a|V148a|I146a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [000014] 77.#64 I146 Use * Keep x2 |V147a|V148a|I146a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 79.#65 BB2 PredBB1 |V147a|V148a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002566] 83.#66 V147 Use * Keep x0 |V147i|V148a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 84.#67 V155 Def COVRS(A) x0 |V155a|V148a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002569] 87.#68 V148 Use * Keep x1 |V155a|V148i| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 88.#69 V156 Def COVRS(A) x1 |V155a|V156a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [001473] 93.#70 V1 Use Keep x21 |V155a|V156a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 94.#71 I147 Def BSFIT(A) x2 |V155a|V156a|I147a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [001475] 97.#72 I147 Use * Keep x2 |V155a|V156a|I147a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 99.#73 BB3 PredBB2 |V155a|V156a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002575] 103.#74 V155 Use * Keep x0 |V155i|V156a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 104.#75 V149 Def OWNPR(A) x0 |V149a|V156a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002578] 107.#76 V156 Use * Keep x1 |V149a|V156i| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 108.#77 V150 Def OWNPR(A) x1 |V149a|V150a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [001494] 112.#78 V43 Def COVRS(A) x2 |V149a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 113.#79 BB4 PredBB2 |V155a|V156a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002582] 117.#80 V155 Use * Keep x0 |V155a|V156a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 118.#81 V149 Def THISA(A) x0 |V149a|V156a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002585] 121.#82 V156 Use * Keep x1 |V149a|V156a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 122.#83 V150 Def THISA(A) x1 |V149a|V150a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [001482] 124.#84 C148 Def RELPR(A) x2 |V149a|V150a|C148a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [001487] 125.#85 C148 Use * Keep x2 |V149a|V150a|C148a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 126.#86 V43 Def Restr x2 |V149a|V150a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| THISA(A) x2 |V149a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 127.#87 BB5 PredBB1 |V147a|V148a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002589] 131.#88 V147 Use * Keep x0 |V147a|V148a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 132.#89 V149 Def THISA(A) x0 |V149a|V148a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002592] 135.#90 V148 Use * Keep x1 |V149a|V148a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 136.#91 V150 Def THISA(A) x1 |V149a|V150a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [000021] 138.#92 C149 Def RELPR(A) x2 |V149a|V150a|C149a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [000026] 139.#93 C149 Use * Keep x2 |V149a|V150a|C149a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 140.#94 V43 Def Restr x2 |V149a|V150a|V43 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| THISA(A) x2 |V149a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 141.#95 BB6 PredBB3 |V149a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [004187] 145.#96 x0 Fixd Keep x0 |V149a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 145.#97 V149 Use * Keep x0 |V149a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 146.#98 x0 Fixd Keep x0 | |V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 146.#99 I150 Def Alloc x0 |I150a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [004188] 149.#100 x1 Fixd Keep x1 |I150a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 149.#101 V150 Use * Keep x1 |I150a|V150a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 150.#102 x1 Fixd Keep x1 |I150a| |V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 150.#103 I151 Def Alloc x1 |I150a|I151a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [004189] 155.#104 x2 Fixd Keep x2 |I150a|I151a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 155.#105 V43 Use * Keep x2 |I150a|I151a|V43 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 156.#106 x2 Fixd Keep x2 |I150a|I151a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 156.#107 I152 Def Alloc x2 |I150a|I151a|I152a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [002594] 158.#108 C153 Def Alloc x11 |I150a|I151a|I152a| | | | | |C153a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [004190] 159.#109 x11 Fixd Keep x11 |I150a|I151a|I152a| | | | | |C153a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 159.#110 C153 Use * Keep x11 |I150a|I151a|I152a| | | | | |C153a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 160.#111 x11 Fixd Keep x11 |I150a|I151a|I152a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 160.#112 I154 Def Alloc x11 |I150a|I151a|I152a| | | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [000030] 161.#113 I155 Def ORDER(A) x3 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#114 x0 Fixd Keep x0 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#115 I150 Use * Keep x0 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#116 x1 Fixd Keep x1 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#117 I151 Use * Keep x1 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#118 x2 Fixd Keep x2 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#119 I152 Use * Keep x2 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#120 x11 Fixd Keep x11 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#121 I154 Use * Keep x11 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 161.#122 I155 Use * Keep x3 |I150a|I151a|I152a|I155a| | | | |I154a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#123 x0 Kill Keep x0 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#124 x1 Kill Keep x1 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#125 x2 Kill Keep x2 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#126 x3 Kill Keep x3 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#127 x4 Kill Keep x4 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#128 x5 Kill Keep x5 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#129 x6 Kill Keep x6 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#130 x7 Kill Keep x7 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#131 x8 Kill Keep x8 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#132 x9 Kill Keep x9 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#133 x10 Kill Keep x10 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#134 x11 Kill Keep x11 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#135 x12 Kill Keep x12 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#136 x13 Kill Keep x13 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#137 x14 Kill Keep x14 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#138 x15 Kill Keep x15 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#139 xip0 Kill Keep xip0 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#140 xip1 Kill Keep xip1 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#141 lr Kill Keep lr | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#142 x0 Fixd Keep x0 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| 162.#143 I156 Def Alloc x0 |I156a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| [000034] 163.#144 I156 Use * Keep x0 |I156a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 164.#145 V15 Def ORDER(A) x26 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 165.#146 BB7 PredBB6 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [000037] 172.#147 V4 Def ORDER(A) x27 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [000038] 176.#148 C157 Def COREL(A) x28 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|C157a| [000040] 177.#149 C157 Use * Keep x28 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|C157a| 178.#150 V5 Def COVRS(A) x28 | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000041] 182.#151 C158 Def ORDER(A) x3 | | | |C158a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000043] 183.#152 C158 Use * Keep x3 | | | |C158a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 184.#153 V6 Def ORDER(A) x3 | | | |V6 a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000046] 190.#154 V7 Def ORDER(A) x4 | | | |V6 a|V7 a| | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000049] 196.#155 V9 Def ORDER(A) x5 | | | |V6 a|V7 a|V9 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000050] 200.#156 C159 Def ORDER(A) x6 | | | |V6 a|V7 a|V9 a|C159a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000052] 201.#157 C159 Use * Keep x6 | | | |V6 a|V7 a|V9 a|C159a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 202.#158 V10 Def COVRS(A) x6 | | | |V6 a|V7 a|V9 a|V10 a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000055] 208.#159 V12 Def ORDER(A) x7 | | | |V6 a|V7 a|V9 a|V10 a|V12 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [000058] 214.#160 V13 Def ORDER(A) x8 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000061] 219.#161 V15 Use Keep x26 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 220.#162 V16 Def BSFIT(A) x1 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002602] 225.#163 V180 Use Keep x24 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 226.#164 V157 Def ORDER(A) x9 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V157a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000068] 231.#165 V157 Use Keep x9 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V157a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002608] 237.#166 V157 Use * Keep x9 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V157a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 238.#167 V168 Def COVRS(A) x9 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V168a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000072] 241.#168 V168 Use * Keep x9 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V168a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 242.#169 V22 Def COVRS(A) x9 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 243.#170 BB47 PredBB7 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000078] 251.#171 V16 Use Keep x1 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 251.#172 V179 Use Keep x25 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 255.#173 BB48 PredBB47 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001205] 261.#174 V16 Use * Keep x1 | |V16 i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 262.#175 V71 Def COVRS(A) x1 | |V71 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001201] 269.#176 V71 Use Keep x1 | |V71 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 270.#177 I160 Def BSFIT(A) x0 |I160a|V71 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001203] 271.#178 I160 Use * Keep x0 |I160a|V71 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 272.#179 V16 Def ORDER(A) x10 | |V71 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001212] 285.#180 V22 Use Keep x9 | |V71 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 285.#181 V71 Use * Keep x1 | |V71 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x13 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 286.#182 I161 Def ORDER(A) x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |I161a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001214] 287.#183 I161 Use * Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |I161a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 288.#184 V72 Def ORDER(A) x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V72 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001218] 291.#185 V72 Use * Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V72 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 292.#186 V18 Def ORDER(A) x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001220] 297.#187 V18 Use Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x13 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 299.#188 BB49 PredBB48 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001224] 307.#189 V18 Use Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x13 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 311.#190 BB8 PredBB49 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001228] 319.#191 V18 Use Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x13 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 323.#192 BB9 PredBB8 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001363] 331.#193 V18 Use Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 332.#194 I162 Def ORDER(A) x14 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|I162a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004192] 333.#195 I162 Use * Keep x14 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|I162a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 334.#196 V182 Def COVRS(A) x14 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V182a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004196] 339.#197 V182 Use Keep x14 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V182a|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 343.#198 BB10 PredBB9 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001367] 351.#199 V18 Use Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 352.#200 I163 Def ORDER(A) x12 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |I163a|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004203] 353.#201 I163 Use * Keep x12 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |I163a|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 354.#202 V183 Def COVRS(A) x12 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183a|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004207] 359.#203 V183 Use Keep x12 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183a|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 363.#204 BB11 PredBB10 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001371] 371.#205 V18 Use * Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 375.#206 BB12 PredBB11 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 377.#207 BB13 PredBB8 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001232] 385.#208 V18 Use Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 389.#209 BB14 PredBB13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001259] 397.#210 V18 Use Keep x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 401.#211 BB15 PredBB14 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001353] 408.#212 C164 Def BSFIT(A) x1 | |C164a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 a|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001354] 409.#213 V18 Use * Keep x13 | |C164a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 409.#214 C164 Use * Keep x1 | |C164a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 413.#215 BB16 PredBB7 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001358] 421.#216 V13 Use * Keep x8 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 i|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 422.#217 I165 Def RELPR(A) x8 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|I165a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001360] 423.#218 I165 Use * Keep x8 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|I165a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x8 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 i|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 424.#219 V13 Def THISA(A) x8 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 425.#220 BB35 PredBB13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001248] 447.#221 V22 Use Keep x9 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 447.#222 V16 Use Keep x10 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 448.#223 I166 Def BSFIT(A) x1 | |I166a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003645] 449.#224 I166 Use * Keep x1 | |I166a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 450.#225 V174 Def COVRS(A) x1 | |V174a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001240] 459.#226 V16 Use Keep x10 | |V174a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 459.#227 V179 Use Keep x25 | |V174a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 459.#228 V174 Use * Keep x1 | |V174i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 461.#229 BB36 PredBB7 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001254] 471.#230 V16 Use * Keep x1 | |V16 i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 472.#231 I167 Def RELPR(A) x1 | |I167a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001256] 473.#232 I167 Use * Keep x1 | |I167a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x1 | |V16 i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 474.#233 V16 Def THISA(A) x1 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 475.#234 BB38 PredBB11 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001266] 483.#235 V16 Use Keep x10 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 483.#236 V179 Use Keep x25 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 487.#237 BB39 PredBB38 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001348] 503.#238 V22 Use Keep x9 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 503.#239 V16 Use Keep x10 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 504.#240 I168 Def COREL(A) x1 | |I168a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003649] 505.#241 I168 Use * Keep x1 | |I168a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 506.#242 V174 Def THISA(A) x1 | |V174a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001350] 511.#243 V174 Use * Keep x1 | |V174i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 515.#244 BB40 PredBB38 | |V174i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001270] 523.#245 V16 Use Keep x10 | |V174i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 524.#246 I169 Def BSFIT(A) x1 | |I169a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001275] 527.#247 I169 Use * Keep x1 | |I169a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 527.#248 V179 Use Keep x25 | |I169a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x1 | |V174i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 531.#249 BB41 PredBB7 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001284] 547.#250 V22 Use Keep x9 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 547.#251 V16 Use Keep x1 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 548.#252 I170 Def BSFIT(A) x0 |I170a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003653] 549.#253 I170 Use * Keep x0 |I170a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 550.#254 V174 Def COVRS(A) x0 |V174a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001286] 555.#255 V174 Use Keep x0 |V174a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 559.#256 BB42 PredBB41 |V174a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001339] 567.#257 V174 Use * Keep x0 |V174a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 571.#258 BB43 PredBB41 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001291] 581.#259 V16 Use Keep x1 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 582.#260 I171 Def BSFIT(A) x0 |I171a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001297] 591.#261 V22 Use Keep x9 |I171a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 591.#262 I171 Use * Keep x0 |I171a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 592.#263 I172 Def BSFIT(A) x0 |I172a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001299] 595.#264 I172 Use * Keep x0 |I172a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001300] 599.#265 V9 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 599.#266 BB44 PredBB39 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001303] 607.#267 V16 Use * Keep x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 608.#268 I173 Def COREL(A) x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|I173a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001305] 609.#269 I173 Use * Keep x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|I173a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 610.#270 V73 Def COVRS(A) x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V73 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001309] 613.#271 V73 Use * Keep x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V73 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 614.#272 V16 Def ORDER(A) x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001314] 619.#273 V16 Use Keep x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 619.#274 V179 Use Keep x25 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 623.#275 BB45 PredBB44 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001326] 639.#276 V22 Use Keep x9 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 639.#277 V16 Use Keep x10 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 640.#278 I174 Def BSFIT(A) x5 | | | |V6 a|V7 a|I174a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001328] 643.#279 I174 Use * Keep x5 | | | |V6 a|V7 a|I174a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x5 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 647.#280 BB46 PredBB44 | | | |V6 a|V7 a|V9 i|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002613] 652.#281 C175 Def RELPR(A) x5 | | | |V6 a|V7 a|C175a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001318] 653.#282 C175 Use * Keep x5 | | | |V6 a|V7 a|C175a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 654.#283 V9 Def ORDER(A) x5 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 655.#284 V16 ExpU Keep NA | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 655.#285 V22 ExpU Keep NA | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 655.#286 BB50 PredBB47 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000086] 669.#287 V5 Use Keep x28 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 673.#288 BB51 PredBB50 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 i| [001196] 679.#289 V4 Use Keep x27 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 i| 680.#290 V5 Def Keep x28 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 681.#291 BB52 PredBB50 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000090] 689.#292 V10 Use Keep x6 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 693.#293 BB53 PredBB52 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001182] 701.#294 V10 Use * Keep x6 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 701.#295 V5 Use Keep x28 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 705.#296 BB54 PredBB53 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001189] 714.#297 C176 Def BSFIT(A) x1 | |C176a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001191] 717.#298 V13 Use * Keep x8 | |C176a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 717.#299 V11 Use Keep x22 | |C176a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 717.#300 C176 Use * Keep x1 | |C176a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 718.#301 I177 Def RELPR(A) x8 | |C176i| |V6 a|V7 a|V9 a|V10 i|V12 a|I177a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001193] 719.#302 I177 Use * Keep x8 | |C176i| |V6 a|V7 a|V9 a|V10 i|V12 a|I177a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x8 | |C176i| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 720.#303 V13 Def THISA(A) x8 | |C176i| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 721.#304 BB55 PredBB53 | | | |V6 a|V7 a|V9 a|V10 i|V12 i|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002615] 726.#305 C178 Def RELPR(A) x7 | | | |V6 a|V7 a|V9 a|V10 i|C178a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001186] 727.#306 C178 Use * Keep x7 | | | |V6 a|V7 a|V9 a|V10 i|C178a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 728.#307 V12 Def Restr x7 | | | |V6 a|V7 a|V9 a|V10 i|V12 i|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| ORDER(A) x7 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 729.#308 BB56 PredBB52 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000093] 735.#309 V17 Use Keep x23 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 736.#310 I179 Def BSFIT(A) x1 | |I179a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000095] 739.#311 I179 Use * Keep x1 | |I179a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 741.#312 BB57 PredBB56 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002620] 749.#313 V1 Use Keep x21 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 750.#314 I180 Def BSFIT(A) x1 | |I180a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001129] 751.#315 I180 Use * Keep x1 | |I180a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 752.#316 V69 Def COVRS(A) x1 | |V69 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001132] 755.#317 V69 Use Keep x1 | |V69 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 756.#318 I181 Def BSFIT(A) x0 |I181a|V69 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001134] 759.#319 I181 Use * Keep x0 |I181a|V69 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 759.#320 V13 Use * Keep x8 |I181a|V69 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 760.#321 I182 Def BSFIT(A) x0 |I182a|V69 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003850] 763.#322 V69 Use * Keep x1 |I182a|V69 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 763.#323 I182 Use * Keep x0 |I182a|V69 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001139] 771.#324 V9 Use Keep x5 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 773.#325 BB58 PredBB57 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001172] 781.#326 V1 Use Keep x21 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 782.#327 I183 Def BSFIT(A) x1 | |I183a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001174] 785.#328 I183 Use * Keep x1 | |I183a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 785.#329 V4 Use Keep x27 | |I183a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 786.#330 I184 Def BSFIT(A) x1 | |I184a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001176] 789.#331 I184 Use * Keep x1 | |I184a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 789.#332 V5 Use Keep x28 | |I184a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 790.#333 I185 Def RELPR(A) x1 | |I185a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001178] 791.#334 I185 Use * Keep x1 | |I185a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 792.#335 V70 Def COVRS(A) x1 | |V70 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 793.#336 BB59 PredBB57 | |V70 i| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001143] 799.#337 V4 Use Keep x27 | |V70 i| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 800.#338 V70 Def Keep x1 | |V70 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 801.#339 BB60 PredBB58 | |V70 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004213] 807.#340 x1 Fixd Keep x1 | |V70 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 807.#341 V70 Use * Keep x1 | |V70 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 808.#342 x1 Fixd Keep x1 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 808.#343 I186 Def Alloc x1 | |I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004214] 811.#344 x0 Fixd Keep x0 | |I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 811.#345 V1 Use Copy x0 |V1 a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 812.#346 x0 Fixd Keep x0 |V1 a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 812.#347 I187 Def Alloc x0 |I187a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002624] 814.#348 C188 Def Alloc x11 |I187a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|C188a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004215] 815.#349 x11 Fixd Keep x11 |I187a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|C188a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 815.#350 C188 Use * Keep x11 |I187a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|C188a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 816.#351 x11 Fixd Keep x11 |I187a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 816.#352 I189 Def Alloc x11 |I187a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001150] 818.#353 C190 Def Alloc x2 |I187a|I186a|C190a|V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004216] 819.#354 x2 Fixd Keep x2 |I187a|I186a|C190a|V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 819.#355 C190 Use * Keep x2 |I187a|I186a|C190a|V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 820.#356 x2 Fixd Keep x2 |I187a|I186a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 820.#357 I191 Def Alloc x2 |I187a|I186a|I191a|V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001151] 821.#358 I192 Def ORDER(A) x6 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#359 x1 Fixd Keep x1 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#360 I186 Use * Keep x1 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#361 x0 Fixd Keep x0 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#362 I187 Use * Keep x0 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#363 x11 Fixd Keep x11 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#364 I189 Use * Keep x11 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#365 x2 Fixd Keep x2 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#366 I191 Use * Keep x2 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#367 I192 Use * Keep x6 |I187a|I186a|I191a|V6 a|V7 a|V9 a|I192a|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x6 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i|I189a|V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#368 x0 Kill Keep x0 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#369 x1 Kill Keep x1 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#370 x2 Kill Keep x2 | | | |V6 a|V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#371 x3 Kill Spill x3 | | | | |V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V7 a|V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#372 x4 Kill Spill x4 | | | | | |V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#373 x5 Kill Spill x5 | | | | | | |V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V10 i|V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#374 x6 Kill Keep x6 | | | | | | | |V12 a|V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#375 x7 Kill Spill x7 | | | | | | | | |V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V13 i|V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#376 x8 Kill Keep x8 | | | | | | | | | |V22 i|V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#377 x9 Kill Keep x9 | | | | | | | | | | |V16 i| |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#378 x10 Kill Keep x10 | | | | | | | | | | | | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#379 x11 Kill Keep x11 | | | | | | | | | | | | |V183i|V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#380 x12 Kill Keep x12 | | | | | | | | | | | | | |V18 i|V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#381 x13 Kill Keep x13 | | | | | | | | | | | | | | |V182i|V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#382 x14 Kill Keep x14 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#383 x15 Kill Keep x15 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#384 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#385 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#386 lr Kill Keep lr | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [001153] 827.#387 V17 Use Keep x23 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 828.#388 I193 Def BSFIT(A) x0 |I193a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001155] 831.#389 I193 Use * Keep x0 |I193a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 833.#390 BB61 PredBB60 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004217] 839.#391 x0 Fixd Keep x0 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 839.#392 V180 Use Copy x0 |V180a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 840.#393 x0 Fixd Keep x0 |V180a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 840.#394 I194 Def Alloc x0 |I194a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002628] 842.#395 I195 Def Alloc x1 |I194a|I195a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004218] 843.#396 x1 Fixd Keep x1 |I194a|I195a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 843.#397 I195 Use * Keep x1 |I194a|I195a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 844.#398 x1 Fixd Keep x1 |I194a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 844.#399 I196 Def Alloc x1 |I194a|I196a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002625] 848.#400 C197 Def Alloc x11 |I194a|I196a| | | | | | | | | |C197a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004219] 849.#401 x11 Fixd Keep x11 |I194a|I196a| | | | | | | | | |C197a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 849.#402 C197 Use * Keep x11 |I194a|I196a| | | | | | | | | |C197a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 850.#403 x11 Fixd Keep x11 |I194a|I196a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 850.#404 I198 Def Alloc x11 |I194a|I196a| | | | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001158] 852.#405 C199 Def Alloc x2 |I194a|I196a|C199a| | | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004220] 853.#406 x2 Fixd Keep x2 |I194a|I196a|C199a| | | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 853.#407 C199 Use * Keep x2 |I194a|I196a|C199a| | | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 854.#408 x2 Fixd Keep x2 |I194a|I196a| | | | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 854.#409 I200 Def Alloc x2 |I194a|I196a|I200a| | | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001159] 855.#410 I201 Def ORDER(A) x3 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#411 x0 Fixd Keep x0 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#412 I194 Use * Keep x0 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#413 x1 Fixd Keep x1 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#414 I196 Use * Keep x1 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#415 x11 Fixd Keep x11 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#416 I198 Use * Keep x11 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#417 x2 Fixd Keep x2 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#418 I200 Use * Keep x2 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#419 I201 Use * Keep x3 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#420 x0 Kill Keep x0 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#421 x1 Kill Keep x1 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#422 x2 Kill Keep x2 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#423 x3 Kill Keep x3 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#424 x4 Kill Keep x4 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#425 x5 Kill Keep x5 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#426 x6 Kill Keep x6 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#427 x7 Kill Keep x7 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#428 x8 Kill Keep x8 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#429 x9 Kill Keep x9 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#430 x10 Kill Keep x10 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#431 x11 Kill Keep x11 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#432 x12 Kill Keep x12 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#433 x13 Kill Keep x13 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#434 x14 Kill Keep x14 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#435 x15 Kill Keep x15 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#436 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#437 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#438 lr Kill Keep lr | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#439 x0 Fixd Keep x0 | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#440 I202 Def Alloc x0 |I202a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [001163] 857.#441 I202 Use * Keep x0 |I202a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 858.#442 V16 Def ORDER(A) x1 | |V16 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001166] 865.#443 V16 Use Keep x1 | |V16 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 865.#444 V15 Use Keep x26 | |V16 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 869.#445 BB62 PredBB61 | |V16 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 i|V4 i|V5 i| [001170] 875.#446 V16 Use * Keep x1 | |V16 i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 i|V4 i|V5 i| 876.#447 V15 Def Keep x26 | |V16 i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 i|V5 i| 877.#448 V11 ExpU Keep NA | |V16 i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 i|V5 i| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 877.#449 BB63 PredBB56 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000098] 885.#450 V1 Use Keep x21 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 886.#451 I203 Def BSFIT(A) x1 | |I203a| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000100] 889.#452 I203 Use * Keep x1 | |I203a| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x1 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 893.#453 BB64 PredBB63 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003861] 903.#454 V1 Use Keep x21 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 905.#455 BB65 PredBB63 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003863] 915.#456 V1 Use Keep x21 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 917.#457 BB66 PredBB60 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000112] 933.#458 V5 Use Keep x28 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 933.#459 V6 Use Keep x3 | |V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 934.#460 I204 Def BSFIT(A) x0 |I204a|V16 i| |V6 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003777] 937.#461 V6 Use * Keep x3 |I204a|V16 i| |V6 i|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 937.#462 V5 Use Keep x28 |I204a|V16 i| |V6 i|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 937.#463 I204 Use * Keep x0 |I204a|V16 i| |V6 i|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 938.#464 I205 Def COREL(A) x3 | |V16 i| |I205a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001120] 939.#465 I205 Use * Keep x3 | |V16 i| |I205a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x3 | |V16 i| |V6 i|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 940.#466 V44 Def COVRS(A) x3 | |V16 i| |V44 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000118] 945.#467 V44 Use * Keep x3 | |V16 i| |V44 a|V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 946.#468 V6 Def COVRS(A) x22 | |V16 i| | |V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000125] 961.#469 V5 Use Keep x28 | |V16 i| | |V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 961.#470 V7 Use Keep x4 | |V16 i| | |V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 962.#471 I206 Def BSFIT(A) x0 |I206a|V16 i| | |V7 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003774] 965.#472 V7 Use * Keep x4 |I206a|V16 i| | |V7 i|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 965.#473 V5 Use Keep x28 |I206a|V16 i| | |V7 i|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 965.#474 I206 Use * Keep x0 |I206a|V16 i| | |V7 i|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 966.#475 I207 Def COREL(A) x4 | |V16 i| | |I207a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001116] 967.#476 I207 Use * Keep x4 | |V16 i| | |I207a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x4 | |V16 i| | |V7 i|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 968.#477 V45 Def COVRS(A) x4 | |V16 i| | |V45 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000131] 973.#478 V45 Use * Keep x4 | |V16 i| | |V45 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 974.#479 V7 Def ORDER(A) x1 | |V7 a| | | |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000134] 981.#480 V9 Use Keep x5 | |V7 a| | | |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 983.#481 BB73 PredBB66 | |V7 a| | | |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001110] 989.#482 V5 Use Keep x28 | |V7 a| | | |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 990.#483 V8 Def ORDER(A) x2 | |V7 a|V8 a| | |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001113] 996.#484 V14 Def ORDER(A) x3 | |V7 a|V8 a|V14 a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 997.#485 BB74 PredBB66 | |V7 a|V8 i|V14 i| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000137] 1007.#486 V1 Use Keep x21 | |V7 a|V8 i|V14 i| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1008.#487 I208 Def BSFIT(A) x3 | |V7 a|V8 i|I208a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003683] 1009.#488 I208 Use * Keep x3 | |V7 a|V8 i|I208a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x3 | |V7 a|V8 i|V14 i| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1010.#489 V178 Def COVRS(A) x3 | |V7 a|V8 i|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003771] 1021.#490 V178 Use Keep x3 | |V7 a|V8 i|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1021.#491 V5 Use Keep x28 | |V7 a|V8 i|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1021.#492 V178 Use Keep x3 | |V7 a|V8 i|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1021.#493 V5 Use Keep x28 | |V7 a|V8 i|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1022.#494 I209 Def COREL(A) x2 | |V7 a|I209a|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001106] 1023.#495 I209 Use * Keep x2 | |V7 a|I209a|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x2 | |V7 a|V8 i|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1024.#496 V46 Def COVRS(A) x2 | |V7 a|V46 a|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000148] 1029.#497 V46 Use * Keep x2 | |V7 a|V46 a|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1030.#498 V8 Def ORDER(A) x2 | |V7 a|V8 a|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000152] 1037.#499 V178 Use * Keep x3 | |V7 a|V8 a|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1037.#500 V5 Use Keep x28 | |V7 a|V8 a|V178a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1038.#501 I210 Def RELPR(A) x3 | |V7 a|V8 a|I210a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000154] 1039.#502 I210 Use * Keep x3 | |V7 a|V8 a|I210a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1040.#503 V14 Def ORDER(A) x3 | |V7 a|V8 a|V14 a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1041.#504 BB78 PredBB73 | |V7 a|V8 a|V14 a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000157] 1047.#505 V15 Use Keep x26 | |V7 a|V8 a|V14 a| |V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1048.#506 V16 Def ORDER(A) x4 | |V7 a|V8 a|V14 a|V16 a|V9 a| |V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001550] 1054.#507 I211 Def ORDER(A) x6 | |V7 a|V8 a|V14 a|V16 a|V9 a|I211a|V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001553] 1055.#508 I211 Use * Keep x6 | |V7 a|V8 a|V14 a|V16 a|V9 a|I211a|V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1056.#509 V151 Def ORDER(A) x6 | |V7 a|V8 a|V14 a|V16 a|V9 a|V151a|V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002650] 1063.#510 V151 Use * Keep x6 | |V7 a|V8 a|V14 a|V16 a|V9 a|V151a|V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1064.#511 V143 Def ORDER(A) x6 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003720] 1066.#512 C212 Def ORDER(A) x8 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|C212a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002653] 1067.#513 C212 Use * Keep x8 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|C212a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1068.#514 V144 Def ORDER(A) x8 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000175] 1072.#515 C213 Def ORDER(A) x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|C213a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000177] 1073.#516 C213 Use * Keep x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|C213a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1074.#517 V20 Def ORDER(A) x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001570] 1081.#518 V3 Use Keep x20 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1082.#519 I214 Def BSFIT(A) x0 |I214a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000944] 1085.#520 I214 Use * Keep x0 |I214a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1086.#521 I215 Def BSFIT(A) x0 |I215a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000181] 1099.#522 I215 Use * Keep x0 |I215a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1099.#523 V12 Use Keep x7 |I215a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1101.#524 BB79 PredBB78 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000949] 1111.#525 V3 Use Keep x20 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1112.#526 I216 Def ORDER(A) x10 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I216a| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000951] 1113.#527 I216 Use * Keep x10 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I216a| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1114.#528 V26 Def ORDER(A) x10 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000954] 1120.#529 V27 Def ORDER(A) x13 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000957] 1126.#530 V28 Def ORDER(A) x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000959] 1133.#531 V26 Use Keep x10 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1134.#532 I217 Def ORDER(A) x12 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |I217a|V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000961] 1135.#533 I217 Use * Keep x12 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |I217a|V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1136.#534 V29 Def ORDER(A) x12 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000964] 1143.#535 V29 Use Keep x12 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1145.#536 BB81 PredBB79 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 i|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002671] 1153.#537 V26 Use Keep x10 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 i|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1154.#538 I218 Def RELPR(A) x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|I218a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001103] 1155.#539 I218 Use * Keep x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|I218a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 i|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1156.#540 V28 Def THISA(A) x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1157.#541 BB82 PredBB79 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000968] 1163.#542 V28 Use Keep x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1164.#543 V30 Def ORDER(A) x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000975] 1167.#544 V8 Use Keep x2 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1168.#545 V64 Def BSFIT(A) x0 |V64 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000972] 1175.#546 V14 Use Keep x3 |V64 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1179.#547 BB83 PredBB82 |V64 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001093] 1183.#548 V64 Use * Keep x0 |V64 i|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1184.#549 V65 Def OWNPR(A) x0 |V65 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001096] 1188.#550 V66 Def BSFIT(A) x11 |V65 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 a|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1189.#551 BB84 PredBB82 |V64 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 i|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000981] 1193.#552 V64 Use * Keep x0 |V64 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 i|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1194.#553 V65 Def THISA(A) x0 |V65 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 i|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000984] 1197.#554 V14 Use Keep x3 |V65 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 i|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1198.#555 V66 Def Keep x11 |V65 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 a|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1199.#556 BB85 PredBB83 |V65 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 a|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000988] 1205.#557 V65 Use * Keep x0 |V65 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 a|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1205.#558 V66 Use * Keep x11 |V65 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|V66 a|V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1206.#559 I219 Def BSFIT(A) x0 |I219a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000990] 1207.#560 I219 Use * Keep x0 |I219a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1208.#561 V31 Def COVRS(A) x0 |V31 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003768] 1223.#562 V6 Use Keep x22 |V31 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1223.#563 V31 Use Keep x0 |V31 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1223.#564 V6 Use Keep x22 |V31 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1223.#565 V31 Use * Keep x0 |V31 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1224.#566 I220 Def BSFIT(A) xip0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|I220a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001089] 1225.#567 I220 Use * Keep xip0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|I220a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1226.#568 V67 Def BSFIT(A) xip0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V67 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001001] 1231.#569 V67 Use * Keep xip0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V67 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1232.#570 V32 Def BSFIT(A) xip0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003157] 1239.#571 V32 Use Keep xip0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1239.#572 V30 Use Keep x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1243.#573 BB89 PredBB85 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001008] 1251.#574 V30 Use Keep x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1253.#575 BB90 PredBB89 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001012] 1261.#576 V20 Use * Keep x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 i|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1262.#577 I221 Def RELPR(A) x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|I221a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001014] 1263.#578 I221 Use * Keep x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|I221a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 i|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1264.#579 V20 Def THISA(A) x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001020] 1271.#580 V20 Use Keep x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1271.#581 V144 Use Keep x8 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1275.#582 BB91 PredBB90 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001066] 1283.#583 V144 Use Keep x8 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1284.#584 I222 Def BSFIT(A) x0 |I222a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001067] 1285.#585 I222 Use * Keep x0 |I222a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1286.#586 I223 Def Alloc x0 |I223a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004221] 1287.#587 x0 Fixd Keep x0 |I223a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1287.#588 I223 Use * Keep x0 |I223a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1288.#589 x0 Fixd Keep x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1288.#590 I224 Def Alloc x0 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002672] 1290.#591 C225 Def Alloc x11 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|C225a|V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004222] 1291.#592 x11 Fixd Keep x11 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|C225a|V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1291.#593 C225 Use * Keep x11 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|C225a|V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1292.#594 x11 Fixd Keep x11 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1292.#595 I226 Def Alloc x11 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|I226a|V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001068] 1293.#596 I227 Def Spill x12 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|I226a| |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| RGNUM(A) x12 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|I226a|I227a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#597 x0 Fixd Keep x0 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|I226a|I227a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#598 I224 Use * Keep x0 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|I226a|I227a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#599 x11 Fixd Keep x11 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|I226a|I227a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#600 I226 Use * Keep x11 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|I226a|I227a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#601 I227 Use * Keep x12 |I224a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a|I226a|I227a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#602 x0 Kill Keep x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#603 x1 Kill Spill x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#604 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#605 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#606 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#607 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#608 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#609 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#610 x8 Kill Spill x8 | | | | | | | | | |V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#611 x9 Kill Spill x9 | | | | | | | | | | |V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V26 a| | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#612 x10 Kill Spill x10 | | | | | | | | | | | | | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#613 x11 Kill Keep x11 | | | | | | | | | | | | | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#614 x12 Kill Keep x12 | | | | | | | | | | | | | |V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#615 x13 Kill Spill x13 | | | | | | | | | | | | | | |V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x13 | | | | | | | | | | | | | | |V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#616 x14 Kill Spill x14 | | | | | | | | | | | | | | | |V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x14 | | | | | | | | | | | | | | | |V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#617 x15 Kill Spill x15 | | | | | | | | | | | | | | | | |V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x15 | | | | | | | | | | | | | | | | |V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#618 xip0 Kill Spill xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#619 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#620 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#621 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1294.#622 I228 Def Alloc x0 |I228a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001070] 1295.#623 I228 Use * Keep x0 |I228a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1296.#624 V33 Def ORDER(A) x3 | | | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002691] 1305.#625 V33 Use Keep x3 | | | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1306.#626 I229 Def COREL(A) x0 |I229a| | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001604] 1307.#627 I229 Use * Keep x0 |I229a| | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1308.#628 V159 Def COVRS(A) x0 |V159a| | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001608] 1315.#629 V33 Use Keep x3 |V159a| | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1316.#630 I230 Def BSFIT(A) x2 |V159a| |I230a|V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001610] 1317.#631 I230 Use * Keep x2 |V159a| |I230a|V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1318.#632 V160 Def COVRS(A) x2 |V159a| |V160a|V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002695] 1321.#633 V159 Use * Keep x0 |V159a| |V160a|V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1322.#634 V161 Def COVRS(A) x0 |V161a| |V160a|V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001628] 1327.#635 V144 Use ReLod NA |V161a| |V160a|V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| ORDER(A) x4 |V161a| |V160a|V33 a|V144a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1327.#636 V160 Use * Keep x2 |V161a| |V160a|V33 a|V144a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1331.#637 BB95 PredBB91 |V161a| | |V33 a|V144a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001640] 1337.#638 V144 Use * Keep x4 |V161a| | |V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1338.#639 I231 Def BSFIT(A) x2 |V161a| |I231a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001673] 1339.#640 I231 Use * Keep x2 |V161a| |I231a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1340.#641 V83 Def COVRS(A) x2 |V161a| |V83 a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001666] 1347.#642 V83 Use * Keep x2 |V161a| |V83 a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1348.#643 I232 Def Alloc x2 |V161a| |I232a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004223] 1349.#644 x2 Fixd Keep x2 |V161a| |I232a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1349.#645 I232 Use * Keep x2 |V161a| |I232a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1350.#646 x2 Fixd Keep x2 |V161a| | |V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1350.#647 I233 Def Alloc x2 |V161a| |I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004224] 1353.#648 x0 Fixd Keep x0 |V161a| |I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1353.#649 V161 Use * Keep x0 |V161a| |I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1354.#650 x0 Fixd Keep x0 | | |I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1354.#651 I234 Def Alloc x0 |I234a| |I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004225] 1357.#652 x1 Fixd Keep x1 |I234a| |I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1357.#653 V143 Use * ReLod NA |I234a| |I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Alloc x1 |I234a|V143i|I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1358.#654 x1 Fixd Keep x1 |I234a|V143i|I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1358.#655 I235 Def Alloc x1 |I234a|I235a|I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002700] 1360.#656 C236 Def Alloc x11 |I234a|I235a|I233a|V33 a|V144i| | | | | | |C236a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004226] 1361.#657 x11 Fixd Keep x11 |I234a|I235a|I233a|V33 a|V144i| | | | | | |C236a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1361.#658 C236 Use * Keep x11 |I234a|I235a|I233a|V33 a|V144i| | | | | | |C236a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1362.#659 x11 Fixd Keep x11 |I234a|I235a|I233a|V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1362.#660 I237 Def Alloc x11 |I234a|I235a|I233a|V33 a|V144i| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001667] 1363.#661 I238 Def ORDER(A) x4 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#662 x2 Fixd Keep x2 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#663 I233 Use * Keep x2 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#664 x0 Fixd Keep x0 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#665 I234 Use * Keep x0 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#666 x1 Fixd Keep x1 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#667 I235 Use * Keep x1 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#668 x11 Fixd Keep x11 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#669 I237 Use * Keep x11 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#670 I238 Use * Keep x4 |I234a|I235a|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x1 | |V143i|I233a|V33 a|I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x4 | |V143i| |V33 a|V144i| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#671 x0 Kill Keep x0 | |V143i| |V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#672 x1 Kill Keep x1 | | | |V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#673 x2 Kill Keep x2 | | | |V33 a|V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#674 x3 Kill Spill x3 | | | | |V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#675 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#676 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#677 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#678 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#679 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#680 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#681 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#682 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#683 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#684 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#685 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#686 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#687 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#688 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#689 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002720] 1373.#690 V33 Use ReLod NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ BSFIT(A) x0 |V33 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1374.#691 I239 Def COREL(A) x1 |V33 a|I239a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001716] 1375.#692 I239 Use * Keep x1 |V33 a|I239a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1376.#693 V163 Def COVRS(A) x1 |V33 a|V163a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001720] 1383.#694 V33 Use * Keep x0 |V33 a|V163a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1384.#695 I240 Def COREL(A) x4 | |V163a| | |I240a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001722] 1385.#696 I240 Use * Keep x4 | |V163a| | |I240a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1386.#697 V164 Def COVRS(A) x4 | |V163a| | |V164a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002724] 1391.#698 V163 Use * Keep x1 | |V163a| | |V164a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1392.#699 V143 Def ORDER(A) x2 | | |V143a| |V164a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002727] 1395.#700 V164 Use * Keep x4 | | |V143a| |V164a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1396.#701 V144 Def ORDER(A) x3 | | |V143a|V144a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1397.#702 BB100 PredBB90 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001029] 1405.#703 V20 Use Keep x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1405.#704 V144 Use Keep x8 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003911] 1421.#705 V143 Use Keep x6 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1421.#706 V20 Use Keep x9 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1421.#707 V28 Use Keep x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001042] 1431.#708 V29 Use Keep x12 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1432.#709 I241 Def BSFIT(A) x0 |I241a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001043] 1433.#710 V27 Use Keep x13 |I241a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1433.#711 I241 Use * Keep x0 |I241a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1437.#712 BB101 PredBB100 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001052] 1445.#713 V27 Use * Keep x13 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 i|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1446.#714 I242 Def RELPR(A) x13 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|I242a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001054] 1447.#715 I242 Use * Keep x13 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|I242a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x13 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 i|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1448.#716 V27 Def THISA(A) x13 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002732] 1457.#717 V26 Use Keep x10 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1458.#718 I243 Def BSFIT(A) x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|I243a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002733] 1459.#719 V27 Use Keep x13 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|I243a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1459.#720 I243 Use * Keep x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|I243a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002738] 1465.#721 V26 Use Keep x10 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1466.#722 I244 Def BSFIT(A) x0 |I244a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002742] 1477.#723 I244 Use * Keep x0 |I244a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1477.#724 V27 Use Keep x13 |I244a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 i|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1478.#725 I245 Def COREL(A) x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|I245a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001060] 1479.#726 I245 Use * Keep x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|I245a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1480.#727 V30 Def BSFIT(A) x0 |V30 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a| |V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1481.#728 BB102 PredBB100 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001047] 1489.#729 V28 Use * Keep x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 i|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1489.#730 V30 Use Keep x15 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 i|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1490.#731 I246 Def RELPR(A) x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|I246a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001049] 1491.#732 I246 Use * Keep x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|I246a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 i|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1492.#733 V28 Def THISA(A) x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001004] 1499.#734 V32 Use Keep xip0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1499.#735 V28 Use Keep x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001005] 1503.#736 V28 ExpU Keep NA | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#737 V27 ExpU Keep NA | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#738 V30 ExpU Keep NA | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#739 V26 ExpU Keep NA | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#740 V29 ExpU Keep NA | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#741 V32 ExpU Keep NA | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1503.#742 BB103 PredBB89 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000183] 1511.#743 V1 Use Keep x21 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1512.#744 I247 Def BSFIT(A) x0 |I247a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000186] 1525.#745 I247 Use * Keep x0 |I247a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1525.#746 V16 Use Keep x4 |I247a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1527.#747 BB104 PredBB103 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000932] 1537.#748 V1 Use Keep x21 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1538.#749 I248 Def BSFIT(A) x0 |I248a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000934] 1541.#750 I248 Use * Keep x0 |I248a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1543.#751 BB106 PredBB104 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001730] 1551.#752 V3 Use Keep x20 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1552.#753 I249 Def BSFIT(A) x11 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |I249a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001783] 1553.#754 I249 Use * Keep x11 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |I249a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1554.#755 V86 Def COVRS(A) x11 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001734] 1561.#756 V86 Use Keep x11 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1563.#757 BB107 PredBB106 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001736] 1571.#758 V0 Use Keep x19 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1572.#759 I250 Def BSFIT(A) x0 |I250a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001738] 1573.#760 I250 Use * Keep x0 |I250a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1574.#761 V87 Def COVRS(A) x0 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001740] 1581.#762 V86 Use Keep x11 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1582.#763 I251 Def ORDER(A) x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I251a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001786] 1593.#764 V0 Use Keep x19 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I251a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1594.#765 I252 Def ORDER(A) x13 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I251a|V86 a| |I252a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001743] 1599.#766 I251 Use * Keep x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I251a|V86 a| |I252a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1599.#767 V87 Use Keep x0 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I251a|V86 a| |I252a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1599.#768 I252 Use * Keep x13 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I251a|V86 a| |I252a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1601.#769 BB108 PredBB107 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002760] 1611.#770 V0 Use Keep x19 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1612.#771 I253 Def ORDER(A) x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I253a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001759] 1613.#772 I253 Use * Keep x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I253a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1614.#773 V88 Def COVRS(A) x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V88 a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001762] 1623.#774 V88 Use Keep x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V88 a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1624.#775 I254 Def ORDER(A) x13 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V88 a|V86 a| |I254a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001763] 1625.#776 V87 Use Keep x0 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V88 a|V86 a| |I254a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1625.#777 I254 Use * Keep x13 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V88 a|V86 a| |I254a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001767] 1629.#778 V88 Use * Keep x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V88 a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1630.#779 I255 Def ORDER(A) x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I255a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001766] 1637.#780 V87 Use Keep x0 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I255a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1638.#781 I256 Def ORDER(A) x13 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I255a|V86 a| |I256a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001768] 1639.#782 I255 Use * Keep x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I255a|V86 a| |I256a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1639.#783 I256 Use * Keep x13 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I255a|V86 a| |I256a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1640.#784 I257 Def ORDER(A) x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I257a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002777] 1645.#785 V86 Use * Keep x11 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I257a|V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1646.#786 I258 Def BSFIT(A) x11 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I257a|I258a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003927] 1647.#787 I257 Use * Keep x10 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I257a|I258a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1647.#788 I258 Use * Keep x11 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I257a|I258a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x11 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001779] 1655.#789 V87 Use * Keep x0 |V87 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1656.#790 I259 Def BSFIT(A) x0 |I259a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003929] 1661.#791 V0 Use Keep x19 |I259a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1661.#792 I259 Use * Keep x0 |I259a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1663.#793 BB111 PredBB107 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004231] 1669.#794 x0 Fixd Keep x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1669.#795 V0 Use Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1670.#796 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1670.#797 I260 Def Alloc x0 |I260a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004232] 1673.#798 x1 Fixd Keep x1 |I260a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1673.#799 V86 Use * Spill x1 |I260a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Copy x1 |I260a|V86 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1674.#800 x1 Fixd Keep x1 |I260a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1674.#801 I261 Def Alloc x1 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002780] 1676.#802 C262 Def Alloc x11 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |C262a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004233] 1677.#803 x11 Fixd Keep x11 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |C262a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1677.#804 C262 Use * Keep x11 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |C262a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1678.#805 x11 Fixd Keep x11 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1678.#806 I263 Def Alloc x11 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001746] 1679.#807 I264 Def ORDER(A) x10 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#808 x0 Fixd Keep x0 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#809 I260 Use * Keep x0 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#810 x1 Fixd Keep x1 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#811 I261 Use * Keep x1 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#812 x11 Fixd Keep x11 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#813 I263 Use * Keep x11 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#814 I264 Use * Keep x10 |I260a|I261a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#815 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#816 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#817 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#818 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#819 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#820 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#821 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#822 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#823 x8 Kill Spill x8 | | | | | | | | | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#824 x9 Kill Spill x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#825 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#826 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#827 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#828 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#829 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#830 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#831 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#832 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#833 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1681.#834 BB112 PredBB103 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000189] 1688.#835 V21 Def ORDER(A) x10 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002784] 1693.#836 V180 Use * Keep x24 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180i|V179a|V15 a|V4 a|V5 a| 1694.#837 V165 Def COVRS(A) x24 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V165a|V179a|V15 a|V4 a|V5 a| [000196] 1699.#838 V165 Use Keep x24 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V165a|V179a|V15 a|V4 a|V5 a| [002790] 1705.#839 V165 Use * Keep x24 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V165a|V179a|V15 a|V4 a|V5 a| 1706.#840 V169 Def COVRS(A) x24 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V169a|V179a|V15 a|V4 a|V5 a| [000200] 1709.#841 V169 Use * Keep x24 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V169a|V179a|V15 a|V4 a|V5 a| 1710.#842 V34 Def COVRS(A) x24 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000203] 1715.#843 V17 Use Keep x23 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1716.#844 V36 Def BSFIT(A) x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1717.#845 BB245 PredBB112 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000209] 1725.#846 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1725.#847 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1729.#848 BB246 PredBB245 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000250] 1735.#849 V16 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1736.#850 V49 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000246] 1743.#851 V49 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1744.#852 I265 Def RELPR(A) x4 |V36 a|V7 a|V8 a|V14 a|I265a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000248] 1745.#853 I265 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|I265a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1746.#854 V16 Def THISA(A) x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000257] 1759.#855 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1759.#856 V49 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1760.#857 I266 Def COREL(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I266a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000259] 1761.#858 I266 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I266a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1762.#859 V50 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V50 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000263] 1765.#860 V50 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V50 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1766.#861 V18 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000265] 1771.#862 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1773.#863 BB247 PredBB246 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000269] 1781.#864 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1785.#865 BB113 PredBB247 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000273] 1793.#866 V14 Use Keep x3 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1797.#867 BB114 PredBB113 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000920] 1810.#868 C267 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C267a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000824] 1815.#869 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C267a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1815.#870 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C267a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1815.#871 C267 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C267a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1817.#872 BB115 PredBB114 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000925] 1827.#873 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1831.#874 BB117 PredBB115 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1833.#875 BB135 PredBB114 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000827] 1841.#876 V14 Use Keep x3 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1845.#877 BB118 PredBB135 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000831] 1851.#878 V36 Use Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1852.#879 I268 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I268a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003678] 1853.#880 I268 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I268a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1854.#881 V177 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000833] 1859.#882 V177 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1861.#883 BB119 PredBB118 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000912] 1864.#884 C269 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177i| |V18 a|C269a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000917] 1865.#885 C269 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177i| |V18 a|C269a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1866.#886 V63 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177i| |V18 a|V63 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1867.#887 BB120 PredBB118 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000848] 1871.#888 V36 Use * Keep x0 |V36 i|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1872.#889 V61 Def COVRS(A) x0 |V61 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000844] 1877.#890 V61 Use * Keep x0 |V61 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x0 |V36 i|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1878.#891 I270 Def RELPR(A) x0 |I270a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000846] 1879.#892 I270 Use * Keep x0 |I270a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a| |V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1880.#893 V36 Def ORDER(A) x12 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a|V36 a|V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000855] 1883.#894 V177 Use * Keep x11 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V177a|V36 a|V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1884.#895 V63 Def Keep x14 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V36 a|V18 a|V63 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1885.#896 BB121 PredBB119 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V63 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001796] 1889.#897 V63 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V63 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1890.#898 I271 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I271a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001836] 1891.#899 I271 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I271a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1892.#900 V92 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001797] 1899.#901 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1900.#902 I272 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a|I272a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001799] 1901.#903 I272 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a|I272a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1902.#904 V91 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001839] 1911.#905 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1912.#906 I273 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|I273a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001805] 1913.#907 V91 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|I273a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1913.#908 I273 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|I273a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1917.#909 BB122 PredBB121 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002805] 1925.#910 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1926.#911 I274 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|I274a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001815] 1927.#912 I274 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|I274a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1928.#913 V93 Def COVRS(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|V93 a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001818] 1935.#914 V93 Use Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|V93 a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1936.#915 I275 Def ORDER(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|V93 a|V18 a|V91 a|I275a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001819] 1937.#916 V91 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|V93 a|V18 a|V91 a|I275a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1937.#917 I275 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|V93 a|V18 a|V91 a|I275a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001823] 1941.#918 V93 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|V93 a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1942.#919 I276 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|I276a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003955] 1955.#920 I276 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|I276a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1955.#921 V91 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a|I276a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1955.#922 V92 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 i|I276a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001832] 1963.#923 V91 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 i| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1964.#924 I277 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I277a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003957] 1969.#925 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I277a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1969.#926 I277 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I277a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1971.#927 BB123 PredBB121 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004234] 1977.#928 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1977.#929 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1978.#930 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1978.#931 I278 Def Alloc x0 |I278a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004235] 1981.#932 x1 Fixd Keep x1 |I278a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1981.#933 V92 Use * Spill x1 |I278a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I278a|V92 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1982.#934 x1 Fixd Keep x1 |I278a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1982.#935 I279 Def Alloc x1 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002812] 1984.#936 C280 Def Alloc x11 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C280a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004236] 1985.#937 x11 Fixd Keep x11 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C280a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1985.#938 C280 Use * Keep x11 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C280a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1986.#939 x11 Fixd Keep x11 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1986.#940 I281 Def Alloc x11 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001809] 1987.#941 I282 Def ORDER(A) x14 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a|I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#942 x0 Fixd Keep x0 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a|I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#943 I278 Use * Keep x0 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a|I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#944 x1 Fixd Keep x1 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a|I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#945 I279 Use * Keep x1 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a|I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#946 x11 Fixd Keep x11 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a|I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#947 I281 Use * Keep x11 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a|I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#948 I282 Use * Keep x14 |I278a|I279a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I281a| |V18 a|I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#949 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#950 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#951 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#952 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#953 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#954 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#955 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#956 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#957 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#958 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#959 x10 Kill Spill x10 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#960 x11 Kill Keep x11 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#961 x12 Kill Keep x12 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#962 x13 Kill Spill x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#963 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#964 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#965 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#966 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#967 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1989.#968 BB124 PredBB122 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000863] 2007.#969 V12 Use Keep x7 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2007.#970 V8 Use Keep x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2009.#971 BB125 PredBB124 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000890] 2019.#972 V20 Use Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2019.#973 V144 Use Keep x8 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002813] 2033.#974 V143 Use Keep x6 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2033.#975 V20 Use Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2034.#976 I283 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I283a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000899] 2037.#977 I283 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I283a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2038.#978 I284 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I284a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000881] 2051.#979 I284 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I284a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2051.#980 V8 Use Keep x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I284a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2051.#981 V20 Use Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I284a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2053.#982 BB127 PredBB125 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001843] 2063.#983 V3 Use Keep x20 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2064.#984 I285 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I285a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001896] 2065.#985 I285 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I285a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2066.#986 V95 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001847] 2073.#987 V95 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2075.#988 BB129 PredBB127 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001849] 2083.#989 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2084.#990 I286 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a|I286a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001851] 2085.#991 I286 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a|I286a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2086.#992 V96 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001853] 2093.#993 V95 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2094.#994 I287 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|I287a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003716] 2095.#995 I287 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|I287a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2096.#996 V181 Def COVRS(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001899] 2109.#997 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2110.#998 I288 Def ORDER(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I288a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001856] 2115.#999 V181 Use Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I288a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2115.#1000 V96 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I288a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2115.#1001 I288 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I288a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2117.#1002 BB130 PredBB129 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002827] 2127.#1003 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2128.#1004 I289 Def ORDER(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I289a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001872] 2129.#1005 I289 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I289a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2130.#1006 V97 Def COVRS(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|V97 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001875] 2139.#1007 V97 Use Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|V97 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2140.#1008 I290 Def FREE (A) xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|V97 a|I290a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001876] 2141.#1009 V96 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|V97 a|I290a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2141.#1010 I290 Use * Keep xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|V97 a|I290a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001880] 2145.#1011 V97 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|V97 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2146.#1012 I291 Def ORDER(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I291a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001879] 2153.#1013 V96 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I291a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2154.#1014 I292 Def FREE (A) xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I291a|I292a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001881] 2155.#1015 I291 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I291a|I292a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2155.#1016 I292 Use * Keep xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I291a|I292a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2156.#1017 I293 Def ORDER(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002835] 2161.#1018 V181 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a|V181a|V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002844] 2167.#1019 V95 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 i| |V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2168.#1020 I294 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I294a| |V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003970] 2169.#1021 I293 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I294a| |V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2169.#1022 I294 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I294a| |V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 i| |V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001892] 2177.#1023 V96 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 i| |V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2178.#1024 I295 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I295a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003972] 2183.#1025 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I295a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2183.#1026 I295 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I295a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2185.#1027 BB132 PredBB129 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004237] 2191.#1028 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2191.#1029 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2192.#1030 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2192.#1031 I296 Def Alloc x0 |I296a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004238] 2195.#1032 x1 Fixd Keep x1 |I296a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2195.#1033 V95 Use * Spill x1 |I296a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I296a|V95 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2196.#1034 x1 Fixd Keep x1 |I296a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2196.#1035 I297 Def Alloc x1 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002847] 2198.#1036 C298 Def Alloc x11 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C298a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004239] 2199.#1037 x11 Fixd Keep x11 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C298a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2199.#1038 C298 Use * Keep x11 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C298a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2200.#1039 x11 Fixd Keep x11 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2200.#1040 I299 Def Alloc x11 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001859] 2201.#1041 I300 Def ORDER(A) x14 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a|I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1042 x0 Fixd Keep x0 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a|I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1043 I296 Use * Keep x0 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a|I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1044 x1 Fixd Keep x1 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a|I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1045 I297 Use * Keep x1 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a|I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1046 x11 Fixd Keep x11 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a|I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1047 I299 Use * Keep x11 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a|I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1048 I300 Use * Keep x14 |I296a|I297a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I299a| |V18 a|I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1049 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1050 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1051 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1052 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1053 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1054 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1055 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1056 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1057 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1058 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1059 x10 Kill Spill x10 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1060 x11 Kill Keep x11 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1061 x12 Kill Keep x12 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1062 x13 Kill Spill x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1063 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1064 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1065 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1066 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1067 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2203.#1068 BB133 PredBB127 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000909] 2211.#1069 V20 Use * Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 i|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2212.#1070 I301 Def RELPR(A) x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|I301a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000911] 2213.#1071 I301 Use * Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|I301a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 i|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2214.#1072 V20 Def THISA(A) x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2215.#1073 BB134 PredBB124 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000866] 2223.#1074 V8 Use * Keep x2 |V36 a|V7 a|V8 i|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2224.#1075 I302 Def RELPR(A) x2 |V36 a|V7 a|I302a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000868] 2225.#1076 I302 Use * Keep x2 |V36 a|V7 a|I302a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x2 |V36 a|V7 a|V8 i|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2226.#1077 V8 Def THISA(A) x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000871] 2233.#1078 V14 Use * Keep x3 |V36 a|V7 a|V8 a|V14 i|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2234.#1079 I303 Def RELPR(A) x3 |V36 a|V7 a|V8 a|I303a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000873] 2235.#1080 I303 Use * Keep x3 |V36 a|V7 a|V8 a|I303a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x3 |V36 a|V7 a|V8 a|V14 i|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2236.#1081 V14 Def THISA(A) x3 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2237.#1082 BB136 PredBB135 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000277] 2245.#1083 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2249.#1084 BB137 PredBB136 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000595] 2257.#1085 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2258.#1086 I304 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|I304a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004241] 2259.#1087 I304 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|I304a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2260.#1088 V184 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V184a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004245] 2265.#1089 V184 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V184a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2269.#1090 BB138 PredBB137 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000599] 2277.#1091 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2278.#1092 I305 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |I305a|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004252] 2279.#1093 I305 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |I305a|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2280.#1094 V185 Def COVRS(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185a|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004256] 2285.#1095 V185 Use Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185a|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2289.#1096 BB139 PredBB138 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000603] 2297.#1097 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2301.#1098 BB140 PredBB139 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2303.#1099 BB141 PredBB136 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000281] 2311.#1100 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2315.#1101 BB142 PredBB141 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000321] 2323.#1102 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2327.#1103 BB143 PredBB142 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000582] 2334.#1104 C306 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C306a|V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000583] 2335.#1105 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C306a|V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2335.#1106 C306 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C306a|V185i|V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2339.#1107 BB144 PredBB143 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002066] 2347.#1108 V3 Use Keep x20 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2348.#1109 I307 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I307a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002119] 2349.#1110 I307 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I307a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2350.#1111 V110 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2351.#1112 BB181 PredBB144 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002070] 2359.#1113 V110 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ DDefs |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2361.#1114 V110 DDef Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2361.#1115 BB182 PredBB112 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002072] 2369.#1116 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2370.#1117 I308 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|I308a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002074] 2371.#1118 I308 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|I308a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V18 i|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2372.#1119 V111 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002076] 2379.#1120 V110 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2380.#1121 I309 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002122] 2391.#1122 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2392.#1123 I310 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I310a|V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002079] 2397.#1124 I309 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I310a|V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2397.#1125 V111 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I310a|V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2397.#1126 I310 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I310a|V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2399.#1127 BB183 PredBB182 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002952] 2409.#1128 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2410.#1129 I311 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|I311a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002095] 2411.#1130 I311 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|I311a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2412.#1131 V112 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002098] 2421.#1132 V112 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|V185i|V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2422.#1133 I312 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I312a|V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002099] 2423.#1134 V111 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I312a|V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2423.#1135 I312 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I312a|V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002103] 2427.#1136 V112 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| |V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2428.#1137 I313 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| |V111a|I313a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002102] 2435.#1138 V111 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| |V111a|I313a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2436.#1139 I314 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I314a|V111a|I313a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002104] 2437.#1140 I313 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I314a|V111a|I313a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2437.#1141 I314 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I314a|V111a|I313a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2438.#1142 I315 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002959] 2445.#1143 V110 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2446.#1144 I316 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I316a|V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002960] 2447.#1145 I316 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a|I316a|V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002969] 2453.#1146 V110 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110i| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2454.#1147 I317 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I317a| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004045] 2455.#1148 I315 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I317a| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2455.#1149 I317 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I317a| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110i| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002115] 2463.#1150 V111 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110i| |V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2464.#1151 I318 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I318a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004047] 2469.#1152 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I318a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2469.#1153 I318 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I318a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2471.#1154 BB185 PredBB182 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004271] 2477.#1155 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2477.#1156 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| | | | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2478.#1157 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2478.#1158 I319 Def Alloc x0 |I319a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004272] 2481.#1159 x1 Fixd Keep x1 |I319a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2481.#1160 V110 Use * Spill x1 |I319a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I319a|V110a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2482.#1161 x1 Fixd Keep x1 |I319a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2482.#1162 I320 Def Alloc x1 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002972] 2484.#1163 C321 Def Alloc x11 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C321a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004273] 2485.#1164 x11 Fixd Keep x11 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C321a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2485.#1165 C321 Use * Keep x11 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C321a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2486.#1166 x11 Fixd Keep x11 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2486.#1167 I322 Def Alloc x11 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002082] 2487.#1168 I323 Def ORDER(A) x13 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1169 x0 Fixd Keep x0 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1170 I319 Use * Keep x0 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1171 x1 Fixd Keep x1 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1172 I320 Use * Keep x1 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1173 x11 Fixd Keep x11 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1174 I322 Use * Keep x11 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1175 I323 Use * Keep x13 |I319a|I320a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1176 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1177 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1178 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1179 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1180 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1181 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1182 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1183 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1184 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1185 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1186 x10 Kill Spill x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1187 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1188 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1189 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1190 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1191 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1192 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1193 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1194 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2489.#1195 BB200 PredBB141 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000297] 2511.#1196 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2511.#1197 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2512.#1198 I324 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I324a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003664] 2513.#1199 I324 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I324a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2514.#1200 V176 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000289] 2523.#1201 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2523.#1202 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2523.#1203 V176 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ DDefs |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2525.#1204 V176 DDef Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2525.#1205 BB201 PredBB112 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000310] 2533.#1206 V16 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2534.#1207 V51 Def BSFIT(A) x4 |V36 a|V7 a|V8 a|V14 a|V51 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000306] 2541.#1208 V51 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V51 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2542.#1209 I325 Def RELPR(A) x4 |V36 a|V7 a|V8 a|V14 a|I325a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000308] 2543.#1210 I325 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|I325a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2544.#1211 V16 Def ORDER(A) x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002283] 2547.#1212 V176 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V176i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2548.#1213 V123 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002244] 2555.#1214 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2556.#1215 I326 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I326a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002246] 2557.#1216 I326 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I326a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2558.#1217 V122 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002286] 2567.#1218 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2568.#1219 I327 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|I327a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002252] 2569.#1220 V122 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|I327a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2569.#1221 I327 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|I327a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2573.#1222 BB203 PredBB201 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003037] 2581.#1223 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2582.#1224 I328 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|I328a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002262] 2583.#1225 I328 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|I328a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2584.#1226 V124 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002265] 2591.#1227 V124 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2592.#1228 I329 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a|I329a|V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002266] 2593.#1229 V122 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a|I329a|V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2593.#1230 I329 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a|I329a|V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002270] 2597.#1231 V124 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2598.#1232 I330 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|I330a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004082] 2611.#1233 I330 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|I330a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2611.#1234 V122 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123a|I330a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2611.#1235 V123 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123i|I330a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002279] 2619.#1236 V122 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V122a| |V123i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2620.#1237 I331 Def BSFIT(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I331a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004084] 2625.#1238 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I331a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2625.#1239 I331 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I331a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2627.#1240 BB204 PredBB201 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004280] 2633.#1241 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2633.#1242 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2634.#1243 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2634.#1244 I332 Def Alloc x0 |I332a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004281] 2637.#1245 x1 Fixd Keep x1 |I332a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2637.#1246 V123 Use * Spill x1 |I332a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I332a|V123a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2638.#1247 x1 Fixd Keep x1 |I332a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2638.#1248 I333 Def Alloc x1 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003044] 2640.#1249 C334 Def Alloc x11 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C334a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004282] 2641.#1250 x11 Fixd Keep x11 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C334a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2641.#1251 C334 Use * Keep x11 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C334a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2642.#1252 x11 Fixd Keep x11 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2642.#1253 I335 Def Alloc x11 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002256] 2643.#1254 I336 Def ORDER(A) x13 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1255 x0 Fixd Keep x0 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1256 I332 Use * Keep x0 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1257 x1 Fixd Keep x1 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1258 I333 Use * Keep x1 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1259 x11 Fixd Keep x11 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1260 I335 Use * Keep x11 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1261 I336 Use * Keep x13 |I332a|I333a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1262 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1263 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1264 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1265 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1266 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1267 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1268 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1269 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1270 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1271 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1272 x10 Kill Spill x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1273 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1274 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1275 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1276 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1277 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1278 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1279 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1280 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2645.#1281 BB205 PredBB139 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000325] 2652.#1282 V37 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000328] 2658.#1283 V38 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000331] 2665.#1284 V9 Use Keep x5 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2667.#1285 BB206 PredBB205 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000424] 2675.#1286 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2675.#1287 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2679.#1288 BB207 PredBB206 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000572] 2695.#1289 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2695.#1290 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2696.#1291 I337 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I337a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003669] 2697.#1292 I337 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I337a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2698.#1293 V176 Def COVRS(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000574] 2703.#1294 V176 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2707.#1295 BB208 PredBB206 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000428] 2715.#1296 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2716.#1297 I338 Def BSFIT(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I338a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000433] 2719.#1298 I338 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I338a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2719.#1299 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I338a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2723.#1300 BB209 PredBB208 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000545] 2739.#1301 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2739.#1302 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2740.#1303 I339 Def COREL(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I339a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003673] 2741.#1304 I339 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I339a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2742.#1305 V176 Def THISA(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000547] 2747.#1306 V176 Use Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2748.#1307 I340 Def ORDER(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000552] 2755.#1308 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2756.#1309 I341 Def FREE (A) xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a|I341a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000558] 2765.#1310 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a|I341a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2765.#1311 I341 Use * Keep xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a|I341a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2766.#1312 I342 Def FREE (A) xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a|I342a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000560] 2769.#1313 I342 Use * Keep xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a|I342a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2770.#1314 I343 Def FREE (A) xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a|I343a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003762] 2771.#1315 I340 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a|I343a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2771.#1316 I343 Use * Keep xip0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I340a|I343a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2772.#1317 I344 Def ORDER(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I344a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000548] 2773.#1318 I344 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a|I344a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2775.#1319 BB210 PredBB209 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 i|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003046] 2782.#1320 C345 Def RELPR(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|C345a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000564] 2783.#1321 C345 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|C345a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2784.#1322 V37 Def Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 i|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| THISA(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2785.#1323 BB213 PredBB209 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000456] 2793.#1324 V176 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2797.#1325 BB214 PredBB213 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000461] 2807.#1326 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2808.#1327 I346 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I346a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000467] 2817.#1328 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I346a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2817.#1329 I346 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I346a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2818.#1330 I347 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I347a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000469] 2821.#1331 I347 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|I347a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2825.#1332 BB215 PredBB208 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002302] 2833.#1333 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2834.#1334 I348 Def BSFIT(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|I348a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002304] 2835.#1335 I348 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|I348a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2836.#1336 V126 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002341] 2845.#1337 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2846.#1338 I349 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I349a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002310] 2847.#1339 V126 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I349a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2847.#1340 I349 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I349a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2851.#1341 BB216 PredBB215 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003058] 2859.#1342 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V37 i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2860.#1343 I350 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I350a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002319] 2861.#1344 I350 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I350a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2862.#1345 V127 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V127a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002322] 2871.#1346 V127 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V127a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2872.#1347 I351 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V127a|I351a|V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002323] 2873.#1348 V126 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V127a|I351a|V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2873.#1349 I351 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V127a|I351a|V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002327] 2877.#1350 V127 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V127a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2878.#1351 I352 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I352a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004101] 2891.#1352 I352 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I352a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2891.#1353 V126 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I352a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2891.#1354 V18 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I352a| |V18 i|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002336] 2899.#1355 V126 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2900.#1356 I353 Def BSFIT(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I353a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004103] 2905.#1357 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I353a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2905.#1358 I353 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I353a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2907.#1359 V9 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2907.#1360 BB218 PredBB207 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000535] 2915.#1361 V38 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2916.#1362 I354 Def RELPR(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|I354a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000537] 2917.#1363 I354 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|I354a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2918.#1364 V38 Def THISA(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2919.#1365 BB219 PredBB218 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000473] 2927.#1366 V16 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2928.#1367 I355 Def COREL(A) x4 |V36 a|V7 a|V8 a|V14 a|I355a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000475] 2929.#1368 I355 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|I355a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2930.#1369 V54 Def COVRS(A) x4 |V36 a|V7 a|V8 a|V14 a|V54 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000479] 2933.#1370 V54 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V54 a|V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2934.#1371 V16 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000484] 2939.#1372 V16 Use Keep x12 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2939.#1373 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2943.#1374 BB220 PredBB219 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000529] 2959.#1375 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2959.#1376 V16 Use Keep x12 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2960.#1377 I356 Def BSFIT(A) x5 |V36 a|V7 a|V8 a|V14 a| |I356a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000531] 2963.#1378 I356 Use * Keep x5 |V36 a|V7 a|V8 a|V14 a| |I356a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x5 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2967.#1379 BB221 PredBB219 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000488] 2975.#1380 V38 Use Keep x14 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2979.#1381 BB222 PredBB221 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000519] 2984.#1382 C357 Def RELPR(A) x14 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|C357a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000521] 2985.#1383 C357 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|C357a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2986.#1384 V38 Def Restr x14 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| THISA(A) x14 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2987.#1385 BB223 PredBB221 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000491] 2993.#1386 V17 Use Keep x23 |V36 a|V7 a|V8 a|V14 a| |V9 i|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2994.#1387 I358 Def BSFIT(A) x5 |V36 a|V7 a|V8 a|V14 a| |I358a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000493] 2997.#1388 I358 Use * Keep x5 |V36 a|V7 a|V8 a|V14 a| |I358a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2999.#1389 BB224 PredBB223 |V36 a|V7 a|V8 a|V14 a| | |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000513] 3007.#1390 V1 Use Keep x21 |V36 a|V7 a|V8 a|V14 a| | |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3008.#1391 I359 Def BSFIT(A) x5 |V36 a|V7 a|V8 a|V14 a| |I359a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000515] 3011.#1392 I359 Use * Keep x5 |V36 a|V7 a|V8 a|V14 a| |I359a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3011.#1393 V5 Use Keep x28 |V36 a|V7 a|V8 a|V14 a| |I359a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3012.#1394 I360 Def BSFIT(A) x4 |V36 a|V7 a|V8 a|V14 a|I360a| |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000517] 3013.#1395 I360 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|I360a| |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3014.#1396 V55 Def COVRS(A) x4 |V36 a|V7 a|V8 a|V14 a|V55 a| |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3015.#1397 BB225 PredBB223 |V36 a|V7 a|V8 a|V14 a|V55 i| |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000497] 3022.#1398 V55 Def Keep x4 |V36 a|V7 a|V8 a|V14 a|V55 a| |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3023.#1399 BB226 PredBB224 |V36 a|V7 a|V8 a|V14 a|V55 a| |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004283] 3029.#1400 x5 Fixd Keep x5 |V36 a|V7 a|V8 a|V14 a|V55 a| |V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3029.#1401 V37 Use * Copy x5 |V36 a|V7 a|V8 a|V14 a|V55 a|V37 a|V143a|V12 a|V144a|V20 a|V21 a|V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3030.#1402 x5 Fixd Keep x5 |V36 a|V7 a|V8 a|V14 a|V55 a| |V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3030.#1403 I361 Def Alloc x5 |V36 a|V7 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004284] 3033.#1404 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3033.#1405 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3034.#1406 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3034.#1407 I362 Def Alloc x0 |I362a|V7 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004285] 3037.#1408 x1 Fixd Keep x1 |I362a|V7 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3037.#1409 V3 Use Spill x1 |I362a| |V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 i|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I362a|V3 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3038.#1410 x1 Fixd Keep x1 |I362a|V3 a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3038.#1411 I363 Def Alloc x1 |I362a|I363a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004286] 3041.#1412 x2 Fixd Keep x2 |I362a|I363a|V8 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3041.#1413 V55 Use * Spill x2 |I362a|I363a| |V14 a|V55 i|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x2 |I362a|I363a|V55 a|V14 a|V55 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3042.#1414 x2 Fixd Keep x2 |I362a|I363a| |V14 a| |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3042.#1415 I364 Def Alloc x2 |I362a|I363a|I364a|V14 a| |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004287] 3045.#1416 x3 Fixd Keep x3 |I362a|I363a|I364a|V14 a| |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3045.#1417 V18 Use * Spill x3 |I362a|I363a|I364a| | |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x3 |I362a|I363a|I364a|V18 a| |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3046.#1418 x3 Fixd Keep x3 |I362a|I363a|I364a|V18 i| |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3046.#1419 I365 Def Alloc x3 |I362a|I363a|I364a|I365a| |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004288] 3049.#1420 x4 Fixd Keep x4 |I362a|I363a|I364a|I365a| |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3049.#1421 V38 Use * Copy x4 |I362a|I363a|I364a|I365a|V38 a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3050.#1422 x4 Fixd Keep x4 |I362a|I363a|I364a|I365a| |I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3050.#1423 I366 Def Alloc x4 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003068] 3052.#1424 C367 Def Alloc x11 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|C367a|V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004289] 3053.#1425 x11 Fixd Keep x11 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|C367a|V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3053.#1426 C367 Use * Keep x11 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|C367a|V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3054.#1427 x11 Fixd Keep x11 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3054.#1428 I368 Def Alloc x11 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000508] 3055.#1429 I369 Def ORDER(A) x13 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1430 x5 Fixd Keep x5 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1431 I361 Use * Keep x5 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1432 x0 Fixd Keep x0 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1433 I362 Use * Keep x0 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1434 x1 Fixd Keep x1 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1435 I363 Use * Keep x1 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1436 x2 Fixd Keep x2 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1437 I364 Use * Keep x2 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1438 x3 Fixd Keep x3 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1439 I365 Use * Keep x3 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1440 x4 Fixd Keep x4 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1441 I366 Use * Keep x4 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1442 x11 Fixd Keep x11 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1443 I368 Use * Keep x11 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1444 I369 Use * Keep x13 |I362a|I363a|I364a|I365a|I366a|I361a|V143a|V12 a|V144a|V20 a|V21 a|I368a|V16 a|I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1445 x0 Kill Keep x0 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1446 x1 Kill Keep x1 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1447 x2 Kill Keep x2 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1448 x3 Kill Keep x3 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1449 x4 Kill Keep x4 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1450 x5 Kill Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1451 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1452 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1453 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1454 x9 Kill Spill x9 | | | | | | | | | | |V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1455 x10 Kill Spill x10 | | | | | | | | | | | | |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1456 x11 Kill Keep x11 | | | | | | | | | | | | |V16 a|V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1457 x12 Kill Spill x12 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x12 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1458 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1459 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1460 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1461 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1462 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1463 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ [000511] 3062.#1464 V9 Def ORDER(A) x2 | | |V9 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3063.#1465 BB227 PredBB205 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002349] 3071.#1466 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3072.#1467 I370 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I370a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002351] 3073.#1468 I370 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I370a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3074.#1469 V129 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002388] 3083.#1470 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3084.#1471 I371 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|I371a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002357] 3085.#1472 V129 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|I371a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3085.#1473 I371 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|I371a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3089.#1474 BB228 PredBB227 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003081] 3097.#1475 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3098.#1476 I372 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|I372a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002366] 3099.#1477 I372 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|I372a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3100.#1478 V130 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002369] 3109.#1479 V130 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3110.#1480 I373 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a|I373a|V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002370] 3111.#1481 V129 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a|I373a|V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3111.#1482 I373 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a|I373a|V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002374] 3115.#1483 V130 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3116.#1484 I374 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|I374a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004118] 3129.#1485 I374 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|I374a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3129.#1486 V129 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 a|I374a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3129.#1487 V18 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 i|I374a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002383] 3137.#1488 V129 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V129a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3138.#1489 I375 Def BSFIT(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I375a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004120] 3143.#1490 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I375a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3143.#1491 I375 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I375a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3145.#1492 BB229 PredBB227 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004290] 3151.#1493 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3151.#1494 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3152.#1495 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3152.#1496 I376 Def Alloc x0 |I376a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004291] 3155.#1497 x1 Fixd Keep x1 |I376a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3155.#1498 V18 Use * Spill x1 |I376a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I376a|V18 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3156.#1499 x1 Fixd Keep x1 |I376a|V18 i|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3156.#1500 I377 Def Alloc x1 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003088] 3158.#1501 C378 Def Alloc x11 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C378a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004292] 3159.#1502 x11 Fixd Keep x11 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C378a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3159.#1503 C378 Use * Keep x11 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C378a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3160.#1504 x11 Fixd Keep x11 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3160.#1505 I379 Def Alloc x11 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002360] 3161.#1506 I380 Def ORDER(A) x13 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1507 x0 Fixd Keep x0 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1508 I376 Use * Keep x0 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1509 x1 Fixd Keep x1 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1510 I377 Use * Keep x1 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1511 x11 Fixd Keep x11 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1512 I379 Use * Keep x11 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1513 I380 Use * Keep x13 |I376a|I377a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1514 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1515 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1516 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1517 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1518 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1519 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1520 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1521 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1522 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1523 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1524 x10 Kill Spill x10 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1525 x11 Kill Keep x11 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1526 x12 Kill Keep x12 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1527 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1528 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1529 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1530 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1531 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1532 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3163.#1533 BB230 PredBB228 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000341] 3171.#1534 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3171.#1535 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3175.#1536 BB231 PredBB112 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000350] 3191.#1537 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3191.#1538 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3192.#1539 I381 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I381a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003658] 3193.#1540 I381 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I381a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3194.#1541 V175 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000352] 3199.#1542 V175 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3203.#1543 BB232 PredBB231 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000417] 3211.#1544 V175 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3215.#1545 BB233 PredBB231 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000363] 3221.#1546 V16 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3222.#1547 V52 Def BSFIT(A) x4 |V36 a|V7 a|V8 a|V14 a|V52 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000359] 3229.#1548 V52 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V52 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3230.#1549 I382 Def RELPR(A) x4 |V36 a|V7 a|V8 a|V14 a|I382a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000361] 3231.#1550 I382 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|I382a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3232.#1551 V16 Def ORDER(A) x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002435] 3235.#1552 V175 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3236.#1553 V133 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002396] 3243.#1554 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3244.#1555 I383 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |I383a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002398] 3245.#1556 I383 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |I383a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3246.#1557 V132 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002438] 3255.#1558 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3256.#1559 I384 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|I384a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002404] 3257.#1560 V132 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|I384a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3257.#1561 I384 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|I384a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3261.#1562 BB234 PredBB233 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003100] 3269.#1563 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3270.#1564 I385 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|I385a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002414] 3271.#1565 I385 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|I385a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3272.#1566 V134 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002417] 3279.#1567 V134 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3280.#1568 I386 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a|I386a|V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002418] 3281.#1569 V132 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a|I386a|V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3281.#1570 I386 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a|I386a|V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002422] 3285.#1571 V134 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3286.#1572 I387 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|I387a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004130] 3299.#1573 I387 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|I387a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3299.#1574 V132 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| |V132a|I387a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3299.#1575 V133 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133i| |V132a|I387a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002431] 3307.#1576 V132 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133i| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3308.#1577 I388 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I388a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004132] 3313.#1578 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I388a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3313.#1579 I388 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I388a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3315.#1580 BB235 PredBB233 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004293] 3321.#1581 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3321.#1582 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3322.#1583 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3322.#1584 I389 Def Alloc x0 |I389a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004294] 3325.#1585 x1 Fixd Keep x1 |I389a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3325.#1586 V133 Use * Spill x1 |I389a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I389a|V133a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3326.#1587 x1 Fixd Keep x1 |I389a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3326.#1588 I390 Def Alloc x1 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003107] 3328.#1589 C391 Def Alloc x11 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C391a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004295] 3329.#1590 x11 Fixd Keep x11 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C391a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3329.#1591 C391 Use * Keep x11 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C391a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3330.#1592 x11 Fixd Keep x11 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3330.#1593 I392 Def Alloc x11 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002408] 3331.#1594 I393 Def ORDER(A) x13 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1595 x0 Fixd Keep x0 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1596 I389 Use * Keep x0 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1597 x1 Fixd Keep x1 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1598 I390 Use * Keep x1 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1599 x11 Fixd Keep x11 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1600 I392 Use * Keep x11 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1601 I393 Use * Keep x13 |I389a|I390a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1602 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1603 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1604 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1605 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1606 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1607 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1608 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1609 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1610 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1611 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1612 x10 Kill Spill x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1613 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1614 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1615 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1616 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1617 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1618 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1619 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1620 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3333.#1621 BB239 PredBB232 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000377] 3341.#1622 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3341.#1623 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3345.#1624 BB240 PredBB112 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000386] 3361.#1625 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3361.#1626 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3362.#1627 I394 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I394a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003641] 3363.#1628 I394 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I394a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3364.#1629 V173 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000388] 3369.#1630 V173 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3373.#1631 BB236 PredBB240 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000399] 3379.#1632 V16 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3380.#1633 V53 Def BSFIT(A) x4 |V36 a|V7 a|V8 a|V14 a|V53 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000395] 3387.#1634 V53 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V53 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3388.#1635 I395 Def RELPR(A) x4 |V36 a|V7 a|V8 a|V14 a|I395a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000397] 3389.#1636 I395 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|I395a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3390.#1637 V16 Def ORDER(A) x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002481] 3393.#1638 V173 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3394.#1639 V137 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002442] 3401.#1640 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3402.#1641 I396 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |I396a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002444] 3403.#1642 I396 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |I396a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3404.#1643 V136 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002484] 3413.#1644 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3414.#1645 I397 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|I397a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002450] 3415.#1646 V136 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|I397a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3415.#1647 I397 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|I397a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3419.#1648 BB237 PredBB236 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003119] 3427.#1649 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3428.#1650 I398 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|I398a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002460] 3429.#1651 I398 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|I398a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3430.#1652 V138 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002463] 3437.#1653 V138 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3438.#1654 I399 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a|I399a|V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002464] 3439.#1655 V136 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a|I399a|V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3439.#1656 I399 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a|I399a|V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002468] 3443.#1657 V138 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3444.#1658 I400 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|I400a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004139] 3457.#1659 I400 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|I400a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3457.#1660 V136 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| |V136a|I400a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3457.#1661 V137 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137i| |V136a|I400a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002477] 3465.#1662 V136 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137i| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3466.#1663 I401 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I401a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004141] 3471.#1664 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I401a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3471.#1665 I401 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I401a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3473.#1666 BB238 PredBB236 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004296] 3479.#1667 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3479.#1668 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3480.#1669 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3480.#1670 I402 Def Alloc x0 |I402a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004297] 3483.#1671 x1 Fixd Keep x1 |I402a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3483.#1672 V137 Use * Spill x1 |I402a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I402a|V137a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3484.#1673 x1 Fixd Keep x1 |I402a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3484.#1674 I403 Def Alloc x1 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003126] 3486.#1675 C404 Def Alloc x11 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C404a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004298] 3487.#1676 x11 Fixd Keep x11 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C404a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3487.#1677 C404 Use * Keep x11 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C404a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3488.#1678 x11 Fixd Keep x11 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3488.#1679 I405 Def Alloc x11 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002454] 3489.#1680 I406 Def ORDER(A) x13 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1681 x0 Fixd Keep x0 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1682 I402 Use * Keep x0 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1683 x1 Fixd Keep x1 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1684 I403 Use * Keep x1 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1685 x11 Fixd Keep x11 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1686 I405 Use * Keep x11 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1687 I406 Use * Keep x13 |I402a|I403a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1688 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1689 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1690 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1691 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1692 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1693 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1694 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1695 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1696 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1697 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1698 x10 Kill Spill x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1699 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1700 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1701 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1702 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1703 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1704 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1705 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1706 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3491.#1707 BB241 PredBB240 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3493.#1708 BB242 PredBB140 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002492] 3501.#1709 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3502.#1710 I407 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I407a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002494] 3503.#1711 I407 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I407a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3504.#1712 V140 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002531] 3513.#1713 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3514.#1714 I408 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|I408a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002500] 3515.#1715 V140 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|I408a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3515.#1716 I408 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|I408a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3519.#1717 BB243 PredBB242 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003138] 3527.#1718 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3528.#1719 I409 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|I409a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002509] 3529.#1720 I409 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|I409a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3530.#1721 V141 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002512] 3539.#1722 V141 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3540.#1723 I410 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a|I410a|V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002513] 3541.#1724 V140 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a|I410a|V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3541.#1725 I410 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a|I410a|V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002517] 3545.#1726 V141 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3546.#1727 I411 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|I411a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004149] 3559.#1728 I411 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|I411a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3559.#1729 V140 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 a|I411a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3559.#1730 V18 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 i|I411a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002526] 3567.#1731 V140 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V140a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3568.#1732 I412 Def BSFIT(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I412a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004151] 3573.#1733 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I412a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3573.#1734 I412 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I412a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3575.#1735 BB244 PredBB215 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004299] 3581.#1736 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3581.#1737 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3582.#1738 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3582.#1739 I413 Def Alloc x0 |I413a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004300] 3585.#1740 x1 Fixd Keep x1 |I413a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3585.#1741 V18 Use * Spill x1 |I413a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I413a|V18 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3586.#1742 x1 Fixd Keep x1 |I413a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3586.#1743 I414 Def Alloc x1 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003145] 3588.#1744 C415 Def Alloc x11 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C415a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004301] 3589.#1745 x11 Fixd Keep x11 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C415a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3589.#1746 C415 Use * Keep x11 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C415a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3590.#1747 x11 Fixd Keep x11 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3590.#1748 I416 Def Alloc x11 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002503] 3591.#1749 I417 Def ORDER(A) x13 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1750 x0 Fixd Keep x0 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1751 I413 Use * Keep x0 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1752 x1 Fixd Keep x1 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1753 I414 Use * Keep x1 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1754 x11 Fixd Keep x11 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1755 I416 Use * Keep x11 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1756 I417 Use * Keep x13 |I413a|I414a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1757 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1758 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1759 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1760 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1761 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1762 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1763 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1764 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1765 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1766 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1767 x10 Kill Spill x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1768 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1769 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1770 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1771 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1772 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1773 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1774 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1775 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1776 V16 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1777 V179 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1778 V4 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1779 V20 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1780 V34 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1781 V5 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1782 V8 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1783 V14 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1784 V36 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1785 V6 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1786 V12 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1787 V144 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1788 V9 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1789 V7 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1790 V143 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1791 V17 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1792 V21 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3593.#1793 BB248 PredBB245 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 i|V17 i|V34 i|V179i|V15 a|V4 i|V5 i| [000216] 3607.#1794 V1 Use Keep x21 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 i|V17 i|V34 i|V179i|V15 a|V4 i|V5 i| 3608.#1795 I418 Def BSFIT(A) x2 | | |I418a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 i|V17 i|V34 i|V179i|V15 a|V4 i|V5 i| [000219] 3621.#1796 I418 Use * Keep x2 | | |I418a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 i|V17 i|V34 i|V179i|V15 a|V4 i|V5 i| 3621.#1797 V15 Use * Keep x26 | | |I418a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3623.#1798 BB249 PredBB248 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [000226] 3633.#1799 V1 Use * Keep x21 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3634.#1800 I419 Def BSFIT(A) x2 | | |I419a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [000228] 3637.#1801 I419 Use * Keep x2 | | |I419a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3638.#1802 I420 Def BSFIT(A) x2 | | |I420a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [002539] 3643.#1803 V0 Use Keep x19 | | |I420a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3644.#1804 I421 Def BSFIT(A) x0 |I421a| |I420a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [000234] 3647.#1805 I421 Use * Keep x0 |I421a| |I420a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3648.#1806 I422 Def BSFIT(A) x0 |I422a| |I420a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [003766] 3649.#1807 I420 Use * Keep x2 |I422a| |I420a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3649.#1808 I422 Use * Keep x0 |I422a| |I420a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3650.#1809 I423 Def BSFIT(A) x2 | | |I423a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [000229] 3651.#1810 I423 Use * Keep x2 | | |I423a| | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3653.#1811 BB251 PredBB249 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [002541] 3663.#1812 V3 Use * Keep x20 | | | | | | | | | | | | | | | | | |V0 a|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3664.#1813 I424 Def Alloc x2 | | |I424a| | | | | | | | | | | | | | |V0 a|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004227] 3665.#1814 x2 Fixd Keep x2 | | |I424a| | | | | | | | | | | | | | |V0 a|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3665.#1815 I424 Use * Keep x2 | | |I424a| | | | | | | | | | | | | | |V0 a|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3666.#1816 x2 Fixd Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3666.#1817 I425 Def Alloc x2 | | |I425a| | | | | | | | | | | | | | |V0 a|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004228] 3669.#1818 x0 Fixd Keep x0 | | |I425a| | | | | | | | | | | | | | |V0 a|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3669.#1819 V0 Use * Copy x0 |V0 a| |I425a| | | | | | | | | | | | | | |V0 a|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3670.#1820 x0 Fixd Keep x0 |V0 i| |I425a| | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3670.#1821 I426 Def Alloc x0 |I426a| |I425a| | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [003153] 3672.#1822 C427 Def Alloc x11 |I426a| |I425a| | | | | | | | |C427a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004229] 3673.#1823 x11 Fixd Keep x11 |I426a| |I425a| | | | | | | | |C427a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3673.#1824 C427 Use * Keep x11 |I426a| |I425a| | | | | | | | |C427a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3674.#1825 x11 Fixd Keep x11 |I426a| |I425a| | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3674.#1826 I428 Def Alloc x11 |I426a| |I425a| | | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [000237] 3676.#1827 C429 Def Alloc x1 |I426a|C429a|I425a| | | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004230] 3677.#1828 x1 Fixd Keep x1 |I426a|C429a|I425a| | | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3677.#1829 C429 Use * Keep x1 |I426a|C429a|I425a| | | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3678.#1830 x1 Fixd Keep x1 |I426a| |I425a| | | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3678.#1831 I430 Def Alloc x1 |I426a|I430a|I425a| | | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [000241] 3679.#1832 I431 Def ORDER(A) x3 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1833 x2 Fixd Keep x2 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1834 I425 Use * Keep x2 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1835 x0 Fixd Keep x0 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1836 I426 Use * Keep x0 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1837 x11 Fixd Keep x11 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1838 I428 Use * Keep x11 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1839 x1 Fixd Keep x1 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1840 I430 Use * Keep x1 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3679.#1841 I431 Use * Keep x3 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1842 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1843 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1844 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1845 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1846 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1847 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1848 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1849 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1850 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1851 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1852 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1853 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1854 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1855 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1856 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1857 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1858 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1859 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| 3680.#1860 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3681.#1861 BB253 PredBB248 | | | | | | | | | | | | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3687.#1862 BB255 PredBB9 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a|V182a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004199] 3691.#1863 V182 Use * Keep x14 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a|V182a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3692.#1864 I432 Def BSFIT(A) x0 |I432a| | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004200] 3694.#1865 I433 Def BSFIT(A) x1 |I432a|I433a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004201] 3695.#1866 I434 Def BSFIT(A) x11 |I432a|I433a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a|I434a| |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3695.#1867 I432 Use * Keep x0 |I432a|I433a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a|I434a| |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3695.#1868 I433 Use * Keep x1 |I432a|I433a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a|I434a| |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3697.#1869 BB17 PredBB255 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001432] 3705.#1870 V4 Use * Keep x27 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 i|V5 a| 3706.#1871 I435 Def RELPR(A) x27 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|I435a|V5 a| [001434] 3707.#1872 I435 Use * Keep x27 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|I435a|V5 a| Restr x27 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 i|V5 a| 3708.#1873 V4 Def THISA(A) x27 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3709.#1874 BB30 PredBB255 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001427] 3717.#1875 V13 Use * Keep x8 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 i|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3718.#1876 I436 Def RELPR(A) x8 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|I436a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001429] 3719.#1877 I436 Use * Keep x8 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|I436a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x8 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 i|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3720.#1878 V13 Def THISA(A) x8 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3721.#1879 BB31 PredBB255 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001449] 3743.#1880 V22 Use Keep x9 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3743.#1881 V16 Use Keep x10 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3744.#1882 I437 Def BSFIT(A) x0 |I437a| | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003625] 3745.#1883 I437 Use * Keep x0 |I437a| | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3746.#1884 V171 Def COVRS(A) x0 |V171a| | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001441] 3755.#1885 V16 Use Keep x10 |V171a| | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3755.#1886 V179 Use Keep x25 |V171a| | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3755.#1887 V171 Use Keep x0 |V171a| | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ DDefs |V171a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3757.#1888 V18 DDef Keep x13 |V171a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3757.#1889 V171 DDef Keep x0 |V171a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3757.#1890 BB32 PredBB7 |V171a|V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001461] 3765.#1891 V16 Use * Keep x1 |V171a|V16 i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3766.#1892 V74 Def BSFIT(A) x1 |V171a|V74 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001457] 3773.#1893 V74 Use * Keep x1 |V171a|V74 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x1 |V171a|V16 i| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3774.#1894 I438 Def RELPR(A) x1 |V171a|I438a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001459] 3775.#1895 I438 Use * Keep x1 |V171a|I438a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3776.#1896 V16 Def ORDER(A) x2 |V171a| |V16 a|V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001470] 3781.#1897 V171 Use * Keep x0 |V171a| |V16 a|V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3781.#1898 V18 Use Keep x13 |V171a| |V16 a|V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001471] 3785.#1899 V18 ExpU Keep NA | | |V16 a|V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3785.#1900 BB34 PredBB255 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3787.#1901 BB256 PredBB10 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183a|V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004210] 3791.#1902 V183 Use * Keep x12 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183a|V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3792.#1903 I439 Def BSFIT(A) x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004211] 3794.#1904 I440 Def BSFIT(A) x0 |I440a| | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004212] 3795.#1905 I441 Def BSFIT(A) x1 |I440a|I441a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3795.#1906 I439 Use * Keep x13 |I440a|I441a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3795.#1907 I440 Use * Keep x0 |I440a|I441a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x13 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3797.#1908 BB18 PredBB256 | | | |V6 a|V7 i|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001374] 3804.#1909 C442 Def BSFIT(A) x4 | | | |V6 a|C442a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001375] 3805.#1910 V6 Use Keep x3 | | | |V6 a|C442a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3805.#1911 C442 Use * Keep x4 | | | |V6 a|C442a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3809.#1912 BB19 PredBB18 | | | |V6 i| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001387] 3815.#1913 V4 Use Keep x27 | | | |V6 i| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3816.#1914 V6 Def Keep x3 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3817.#1915 BB20 PredBB18 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001379] 3825.#1916 V4 Use * Keep x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 i|V5 a| 3826.#1917 I443 Def RELPR(A) x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|I443a|V5 a| [001381] 3827.#1918 I443 Use * Keep x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|I443a|V5 a| Restr x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 i|V5 a| 3828.#1919 V4 Def THISA(A) x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001384] 3833.#1920 V4 Use Keep x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3834.#1921 V7 Def ORDER(A) x2 | | |V7 a|V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3835.#1922 BB21 PredBB256 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001390] 3843.#1923 V5 Use Keep x28 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001391] 3847.#1924 V5 ExpU Keep NA | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3847.#1925 BB22 PredBB7 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 i| [001394] 3853.#1926 V4 Use Keep x27 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 i| 3854.#1927 V5 Def Keep x28 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3855.#1928 BB23 PredBB256 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001398] 3873.#1929 V4 Use Keep x27 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3873.#1930 V5 Use Keep x28 | | | |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3875.#1931 BB24 PredBB7 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001405] 3885.#1932 V10 Use Keep x6 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3889.#1933 BB26 PredBB24 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001415] 3897.#1934 V10 Use Keep x6 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3897.#1935 V4 Use Keep x27 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3901.#1936 BB27 PredBB26 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001422] 3909.#1937 V11 Use * Keep x22 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3910.#1938 I444 Def RELPR(A) x22 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|I444a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001424] 3911.#1939 I444 Use * Keep x22 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|I444a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x22 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3912.#1940 V11 Def THISA(A) x22 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3913.#1941 V10 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3913.#1942 V12 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3913.#1943 V11 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3913.#1944 BB28 PredBB26 | |V16 a| |V6 a|V7 a|V9 a|V10 i|V12 i|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002612] 3918.#1945 C445 Def RELPR(A) x7 | |V16 a| |V6 a|V7 a|V9 a|V10 i|C445a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001419] 3919.#1946 C445 Use * Keep x7 | |V16 a| |V6 a|V7 a|V9 a|V10 i|C445a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3920.#1947 V12 Def OWNPR(A) x22 | |V16 a| |V6 a|V7 a|V9 a|V10 i|C445i|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V12 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Restr x7 | |V16 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3921.#1948 BB29 PredBB24 | |V16 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001409] 3927.#1949 V4 Use Keep x27 | |V16 a| |V6 a|V7 a|V9 a|V10 i|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3928.#1950 V10 Def Keep x6 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001410] 3932.#1951 C446 Def COREL(A) x22 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|C446a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001412] 3933.#1952 C446 Use * Keep x22 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|C446a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3934.#1953 V11 Def THISA(A) x22 | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1954 V22 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1955 V13 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1956 V10 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1957 V11 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1958 V180 ExpU Keep NA | |V16 a| |V6 a|V7 a|V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3935.#1959 BB257 PredBB137 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V184a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004248] 3939.#1960 V184 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V184a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3940.#1961 I447 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I447a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004249] 3942.#1962 I448 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I447a| |V18 a|I448a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004250] 3943.#1963 I449 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I447a|I449a|V18 a|I448a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3943.#1964 I447 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I447a|I449a|V18 a|I448a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3943.#1965 I448 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I447a|I449a|V18 a|I448a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3945.#1966 BB145 PredBB257 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000641] 3953.#1967 V14 Use Keep x3 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3957.#1968 BB146 PredBB145 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000733] 3965.#1969 V14 Use * Keep x3 |V36 a|V7 a|V8 a|V14 i|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3966.#1970 I450 Def RELPR(A) x3 |V36 a|V7 a|V8 a|I450a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000735] 3967.#1971 I450 Use * Keep x3 |V36 a|V7 a|V8 a|I450a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x3 |V36 a|V7 a|V8 a|V14 i|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3968.#1972 V14 Def THISA(A) x3 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000738] 3975.#1973 V8 Use Keep x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3975.#1974 V6 Use Keep x22 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3979.#1975 BB147 PredBB146 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000749] 3986.#1976 V58 Def BSFIT(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V58 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3987.#1977 BB148 PredBB146 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V58 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000740] 3992.#1978 C451 Def RELPR(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |C451a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000742] 3993.#1979 C451 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |C451a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3994.#1980 V58 Def Restr x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V58 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| THISA(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V58 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3995.#1981 BB149 PredBB147 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V58 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002850] 3999.#1982 V58 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V58 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4000.#1983 I452 Def RELPR(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I452a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000746] 4001.#1984 I452 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I452a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4002.#1985 V18 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4003.#1986 BB150 PredBB145 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000644] 4009.#1987 V36 Use Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4010.#1988 I453 Def BSFIT(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I453a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000646] 4013.#1989 I453 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I453a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4015.#1990 BB151 PredBB150 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000721] 4023.#1991 V8 Use Keep x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4023.#1992 V7 Use Keep x1 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4027.#1993 BB152 PredBB151 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000729] 4034.#1994 V57 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4035.#1995 BB153 PredBB151 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 i| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000723] 4040.#1996 C454 Def RELPR(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C454a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000725] 4041.#1997 C454 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C454a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4042.#1998 V57 Def Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 i| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| THISA(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4043.#1999 BB154 PredBB150 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 i| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000656] 4049.#2000 V36 Use * Keep x0 |V36 i|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 i| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4050.#2001 V56 Def BSFIT(A) x11 |V36 i|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V56 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000652] 4057.#2002 V56 Use Keep x11 |V36 i|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V56 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4058.#2003 I455 Def RELPR(A) x0 |I455a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V56 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000654] 4059.#2004 I455 Use * Keep x0 |I455a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V56 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x0 |V36 i|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V56 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4060.#2005 V36 Def THISA(A) x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V56 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000658] 4063.#2006 V56 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V56 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 i| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4064.#2007 I456 Def COREL(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I456a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000660] 4065.#2008 I456 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I456a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4066.#2009 V57 Def THISA(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4067.#2010 BB155 PredBB152 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002851] 4071.#2011 V57 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V57 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4072.#2012 I457 Def RELPR(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I457a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000664] 4073.#2013 I457 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I457a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4074.#2014 V18 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4075.#2015 BB156 PredBB149 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000667] 4083.#2016 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4085.#2017 BB157 PredBB156 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001903] 4093.#2018 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4094.#2019 I458 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I458a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001905] 4095.#2020 I458 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I458a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4096.#2021 V99 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001942] 4105.#2022 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4106.#2023 I459 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|I459a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001911] 4107.#2024 V99 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|I459a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4107.#2025 I459 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|I459a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4111.#2026 BB158 PredBB157 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002863] 4119.#2027 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4120.#2028 I460 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|I460a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001920] 4121.#2029 I460 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|I460a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4122.#2030 V100 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001923] 4131.#2031 V100 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4132.#2032 I461 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a|I461a|V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001924] 4133.#2033 V99 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a|I461a|V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4133.#2034 I461 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a|I461a|V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001928] 4137.#2035 V100 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4138.#2036 I462 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|I462a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004002] 4151.#2037 I462 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|I462a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4151.#2038 V99 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 a|I462a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4151.#2039 V18 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 i|I462a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001937] 4159.#2040 V99 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V99 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4160.#2041 I463 Def BSFIT(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I463a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004004] 4165.#2042 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I463a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4165.#2043 I463 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |I463a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4167.#2044 BB159 PredBB157 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004262] 4173.#2045 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4173.#2046 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4174.#2047 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4174.#2048 I464 Def Alloc x0 |I464a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004263] 4177.#2049 x1 Fixd Keep x1 |I464a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4177.#2050 V18 Use * Spill x1 |I464a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I464a|V18 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4178.#2051 x1 Fixd Keep x1 |I464a|V18 i|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4178.#2052 I465 Def Alloc x1 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002870] 4180.#2053 C466 Def Alloc x11 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C466a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004264] 4181.#2054 x11 Fixd Keep x11 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C466a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4181.#2055 C466 Use * Keep x11 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C466a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4182.#2056 x11 Fixd Keep x11 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4182.#2057 I467 Def Alloc x11 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001914] 4183.#2058 I468 Def ORDER(A) x13 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2059 x0 Fixd Keep x0 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2060 I464 Use * Keep x0 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2061 x1 Fixd Keep x1 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2062 I465 Use * Keep x1 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2063 x11 Fixd Keep x11 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2064 I467 Use * Keep x11 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2065 I468 Use * Keep x13 |I464a|I465a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x13 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2066 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2067 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2068 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2069 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2070 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2071 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2072 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2073 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2074 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2075 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2076 x10 Kill Spill x10 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2077 x11 Kill Keep x11 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2078 x12 Kill Keep x12 | | | | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2079 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2080 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2081 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2082 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2083 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2084 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4185.#2085 BB160 PredBB158 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000680] 4203.#2086 V12 Use Keep x7 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4203.#2087 V8 Use Keep x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4205.#2088 BB161 PredBB160 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000697] 4215.#2089 V20 Use Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4215.#2090 V144 Use Keep x8 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002871] 4229.#2091 V143 Use Keep x6 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4229.#2092 V20 Use Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4230.#2093 I469 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I469a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000706] 4233.#2094 I469 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I469a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4234.#2095 I470 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I470a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000688] 4247.#2096 I470 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I470a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4247.#2097 V8 Use Keep x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I470a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4247.#2098 V20 Use Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I470a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4249.#2099 BB163 PredBB161 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001946] 4259.#2100 V3 Use Keep x20 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4260.#2101 I471 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I471a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001999] 4261.#2102 I471 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I471a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4262.#2103 V102 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001950] 4269.#2104 V102 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4271.#2105 BB165 PredBB163 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001952] 4279.#2106 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4280.#2107 I472 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |I472a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001954] 4281.#2108 I472 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |I472a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4282.#2109 V103 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001956] 4289.#2110 V102 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4290.#2111 I473 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002002] 4301.#2112 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4302.#2113 I474 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I474a|V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001959] 4307.#2114 I473 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I474a|V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4307.#2115 V103 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I474a|V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4307.#2116 I474 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I474a|V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4309.#2117 BB166 PredBB165 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002885] 4319.#2118 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4320.#2119 I475 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|I475a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001975] 4321.#2120 I475 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|I475a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4322.#2121 V104 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001978] 4331.#2122 V104 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4332.#2123 I476 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I476a|V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001979] 4333.#2124 V103 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I476a|V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4333.#2125 I476 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I476a|V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001983] 4337.#2126 V104 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4338.#2127 I477 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|I477a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001982] 4345.#2128 V103 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|I477a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4346.#2129 I478 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I478a|V103a|I477a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001984] 4347.#2130 I477 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I478a|V103a|I477a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4347.#2131 I478 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I478a|V103a|I477a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4348.#2132 I479 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002892] 4355.#2133 V102 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4356.#2134 I480 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I480a|V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002893] 4357.#2135 I480 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a|I480a|V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002902] 4363.#2136 V102 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102i| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4364.#2137 I481 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I481a| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004017] 4365.#2138 I479 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I481a| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4365.#2139 I481 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I481a| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102i| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001995] 4373.#2140 V103 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102i| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4374.#2141 I482 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I482a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004019] 4379.#2142 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I482a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4379.#2143 I482 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I482a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4381.#2144 BB168 PredBB165 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004265] 4387.#2145 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4387.#2146 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4388.#2147 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4388.#2148 I483 Def Alloc x0 |I483a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004266] 4391.#2149 x1 Fixd Keep x1 |I483a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4391.#2150 V102 Use * Spill x1 |I483a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I483a|V102a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4392.#2151 x1 Fixd Keep x1 |I483a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4392.#2152 I484 Def Alloc x1 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002905] 4394.#2153 C485 Def Alloc x11 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C485a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004267] 4395.#2154 x11 Fixd Keep x11 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C485a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4395.#2155 C485 Use * Keep x11 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C485a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4396.#2156 x11 Fixd Keep x11 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4396.#2157 I486 Def Alloc x11 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001962] 4397.#2158 I487 Def ORDER(A) x13 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2159 x0 Fixd Keep x0 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2160 I483 Use * Keep x0 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2161 x1 Fixd Keep x1 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2162 I484 Use * Keep x1 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2163 x11 Fixd Keep x11 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2164 I486 Use * Keep x11 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2165 I487 Use * Keep x13 |I483a|I484a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2166 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2167 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2168 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2169 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2170 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2171 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2172 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2173 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2174 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2175 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2176 x10 Kill Spill x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2177 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2178 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2179 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2180 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2181 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2182 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2183 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2184 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4399.#2185 BB169 PredBB163 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000716] 4407.#2186 V20 Use * Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 i|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4408.#2187 I488 Def RELPR(A) x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|I488a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000718] 4409.#2188 I488 Use * Keep x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|I488a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 i|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4410.#2189 V20 Def THISA(A) x9 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4411.#2190 BB170 PredBB156 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000671] 4419.#2191 V8 Use * Keep x2 |V36 a|V7 a|V8 i|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4420.#2192 I489 Def RELPR(A) x2 |V36 a|V7 a|I489a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000673] 4421.#2193 I489 Use * Keep x2 |V36 a|V7 a|I489a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x2 |V36 a|V7 a|V8 i|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4422.#2194 V8 Def THISA(A) x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4423.#2195 BB186 PredBB257 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002126] 4431.#2196 V3 Use Keep x20 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4432.#2197 I490 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I490a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002179] 4433.#2198 I490 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I490a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4434.#2199 V114 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002130] 4441.#2200 V114 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ DDefs |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4443.#2201 V114 DDef Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4443.#2202 BB187 PredBB112 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002132] 4451.#2203 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4452.#2204 I491 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |I491a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002134] 4453.#2205 I491 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |I491a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4454.#2206 V115 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002136] 4461.#2207 V114 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4462.#2208 I492 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002182] 4473.#2209 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4474.#2210 I493 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I493a|V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002139] 4479.#2211 I492 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I493a|V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4479.#2212 V115 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I493a|V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4479.#2213 I493 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I493a|V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4481.#2214 BB188 PredBB187 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002986] 4491.#2215 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4492.#2216 I494 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|I494a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002155] 4493.#2217 I494 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|I494a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4494.#2218 V116 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002158] 4503.#2219 V116 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4504.#2220 I495 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I495a|V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002159] 4505.#2221 V115 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I495a|V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4505.#2222 I495 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I495a|V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002163] 4509.#2223 V116 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4510.#2224 I496 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|I496a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002162] 4517.#2225 V115 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|I496a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4518.#2226 I497 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I497a|V115a|I496a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002164] 4519.#2227 I496 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I497a|V115a|I496a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4519.#2228 I497 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I497a|V115a|I496a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4520.#2229 I498 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002993] 4527.#2230 V114 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4528.#2231 I499 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I499a|V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002994] 4529.#2232 I499 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a|I499a|V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003003] 4535.#2233 V114 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114i| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4536.#2234 I500 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I500a| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004056] 4537.#2235 I498 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I500a| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4537.#2236 I500 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I500a| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114i| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002175] 4545.#2237 V115 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114i| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4546.#2238 I501 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I501a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004058] 4551.#2239 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I501a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4551.#2240 I501 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I501a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4553.#2241 BB190 PredBB187 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004274] 4559.#2242 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4559.#2243 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4560.#2244 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4560.#2245 I502 Def Alloc x0 |I502a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004275] 4563.#2246 x1 Fixd Keep x1 |I502a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4563.#2247 V114 Use * Spill x1 |I502a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I502a|V114a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4564.#2248 x1 Fixd Keep x1 |I502a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4564.#2249 I503 Def Alloc x1 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003006] 4566.#2250 C504 Def Alloc x11 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C504a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004276] 4567.#2251 x11 Fixd Keep x11 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C504a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4567.#2252 C504 Use * Keep x11 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C504a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4568.#2253 x11 Fixd Keep x11 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4568.#2254 I505 Def Alloc x11 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002142] 4569.#2255 I506 Def ORDER(A) x13 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2256 x0 Fixd Keep x0 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2257 I502 Use * Keep x0 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2258 x1 Fixd Keep x1 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2259 I503 Use * Keep x1 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2260 x11 Fixd Keep x11 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2261 I505 Use * Keep x11 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2262 I506 Use * Keep x13 |I502a|I503a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2263 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2264 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2265 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2266 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2267 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2268 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2269 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2270 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2271 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2272 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2273 x10 Kill Spill x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2274 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2275 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2276 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2277 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2278 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2279 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2280 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2281 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4571.#2282 BB194 PredBB257 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000756] 4579.#2283 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4579.#2284 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4583.#2285 BB195 PredBB194 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000788] 4599.#2286 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4599.#2287 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4600.#2288 I507 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|I507a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003631] 4601.#2289 I507 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|I507a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4602.#2290 V172 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000790] 4607.#2291 V172 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4609.#2292 BB196 PredBB195 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000801] 4617.#2293 V172 Use Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4617.#2294 V18 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4621.#2295 BB191 PredBB196 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000812] 4627.#2296 V16 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4628.#2297 V59 Def BSFIT(A) x4 |V36 a|V7 a|V8 a|V14 a|V59 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000808] 4635.#2298 V59 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V59 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4636.#2299 I508 Def RELPR(A) x4 |V36 a|V7 a|V8 a|V14 a|I508a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000810] 4637.#2300 I508 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|I508a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4638.#2301 V16 Def ORDER(A) x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002225] 4641.#2302 V172 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V172i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4642.#2303 V119 Def COVRS(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002186] 4649.#2304 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4650.#2305 I509 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I509a| |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002188] 4651.#2306 I509 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I509a| |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4652.#2307 V118 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a| |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002228] 4661.#2308 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a| |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4662.#2309 I510 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I510a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002194] 4663.#2310 V118 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I510a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4663.#2311 I510 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I510a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4667.#2312 BB192 PredBB191 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a| |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003018] 4675.#2313 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a| |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4676.#2314 I511 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I511a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002204] 4677.#2315 I511 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I511a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4678.#2316 V120 Def COVRS(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|V120a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002207] 4685.#2317 V120 Use Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|V120a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4686.#2318 I512 Def ORDER(A) x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|V120a|V18 a|V119a|I512a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002208] 4687.#2319 V118 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|V120a|V18 a|V119a|I512a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4687.#2320 I512 Use * Keep x15 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|V120a|V18 a|V119a|I512a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002212] 4691.#2321 V120 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|V120a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4692.#2322 I513 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I513a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004065] 4705.#2323 I513 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I513a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4705.#2324 V118 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I513a|V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4705.#2325 V119 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a|I513a|V18 a|V119i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002221] 4713.#2326 V118 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|V118a| |V18 a|V119i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4714.#2327 I514 Def BSFIT(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|I514a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004067] 4719.#2328 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|I514a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4719.#2329 I514 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|I514a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4721.#2330 BB193 PredBB191 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004277] 4727.#2331 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4727.#2332 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4728.#2333 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4728.#2334 I515 Def Alloc x0 |I515a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004278] 4731.#2335 x1 Fixd Keep x1 |I515a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4731.#2336 V119 Use * Spill x1 |I515a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I515a|V119a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a|V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4732.#2337 x1 Fixd Keep x1 |I515a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4732.#2338 I516 Def Alloc x1 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003025] 4734.#2339 C517 Def Alloc x11 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C517a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004279] 4735.#2340 x11 Fixd Keep x11 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C517a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4735.#2341 C517 Use * Keep x11 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|C517a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4736.#2342 x11 Fixd Keep x11 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4736.#2343 I518 Def Alloc x11 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002198] 4737.#2344 I519 Def ORDER(A) x14 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a|I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2345 x0 Fixd Keep x0 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a|I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2346 I515 Use * Keep x0 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a|I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2347 x1 Fixd Keep x1 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a|I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2348 I516 Use * Keep x1 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a|I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2349 x11 Fixd Keep x11 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a|I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2350 I518 Use * Keep x11 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a|I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2351 I519 Use * Keep x14 |I515a|I516a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I518a| |V18 a|I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2352 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2353 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2354 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2355 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2356 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2357 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2358 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2359 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2360 x8 Kill Spill x8 | | | | | | | | | |V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2361 x9 Kill Spill x9 | | | | | | | | | | |V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | |V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2362 x10 Kill Spill x10 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2363 x11 Kill Keep x11 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2364 x12 Kill Keep x12 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2365 x13 Kill Spill x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2366 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2367 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2368 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2369 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2370 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4739.#2371 V18 ExpU Keep NA | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4739.#2372 BB197 PredBB194 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000763] 4747.#2373 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4747.#2374 V179 Use Keep x25 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4751.#2375 BB198 PredBB195 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000772] 4767.#2376 V34 Use Keep x24 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4767.#2377 V16 Use Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4768.#2378 I520 Def COREL(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | |I520a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003636] 4769.#2379 I520 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | |I520a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4770.#2380 V172 Def THISA(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000774] 4775.#2381 V172 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4777.#2382 BB199 PredBB112 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000778] 4785.#2383 V16 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4786.#2384 I521 Def RELPR(A) x4 |V36 a|V7 a|V8 a|V14 a|I521a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000780] 4787.#2385 I521 Use * Keep x4 |V36 a|V7 a|V8 a|V14 a|I521a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x4 |V36 a|V7 a|V8 a|V14 a|V16 i|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4788.#2386 V16 Def THISA(A) x4 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4789.#2387 BB258 PredBB138 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185a|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004259] 4793.#2388 V185 Use * Keep x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| |V185a|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4794.#2389 I522 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I522a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004260] 4796.#2390 I523 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I522a| |V18 a|I523a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004261] 4797.#2391 I524 Def ORDER(A) x12 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I522a|I524a|V18 a|I523a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4797.#2392 I522 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I522a|I524a|V18 a|I523a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4797.#2393 I523 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I522a|I524a|V18 a|I523a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4799.#2394 V18 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4799.#2395 BB171 PredBB258 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000607] 4807.#2396 V8 Use Keep x2 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4808.#2397 I525 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I525a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000609] 4811.#2398 I525 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I525a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4811.#2399 V21 Use Keep x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I525a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4812.#2400 I526 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I526a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000611] 4815.#2401 I526 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I526a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4817.#2402 BB172 PredBB112 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000615] 4825.#2403 V7 Use Keep x1 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4829.#2404 BB173 PredBB172 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000630] 4841.#2405 V36 Use Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4842.#2406 I527 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I527a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000628] 4849.#2407 V5 Use Keep x28 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I527a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4849.#2408 V4 Use Keep x27 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I527a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4849.#2409 I527 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a|I527a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4851.#2410 V21 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4851.#2411 BB174 PredBB172 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002006] 4861.#2412 V3 Use Keep x20 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4862.#2413 I528 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i|I528a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002059] 4863.#2414 I528 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i|I528a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4864.#2415 V106 Def COVRS(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002010] 4871.#2416 V106 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4873.#2417 BB176 PredBB174 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002012] 4881.#2418 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4882.#2419 I529 Def ORDER(A) x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I529a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002014] 4883.#2420 I529 Use * Keep x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I529a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V21 i|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4884.#2421 V107 Def COVRS(A) x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002016] 4891.#2422 V106 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4892.#2423 I530 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I530a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002062] 4903.#2424 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I530a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4904.#2425 I531 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I530a|I531a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002019] 4909.#2426 I530 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I530a|I531a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4909.#2427 V107 Use Keep x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I530a|I531a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4909.#2428 I531 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I530a|I531a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4911.#2429 BB177 PredBB176 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002919] 4921.#2430 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4922.#2431 I532 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I532a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002035] 4923.#2432 I532 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I532a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4924.#2433 V108 Def COVRS(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |V108a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002038] 4933.#2434 V108 Use Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |V108a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4934.#2435 I533 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |V108a|I533a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002039] 4935.#2436 V107 Use Keep x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |V108a|I533a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4935.#2437 I533 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |V108a|I533a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002043] 4939.#2438 V108 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |V108a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4940.#2439 I534 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I534a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002042] 4947.#2440 V107 Use Keep x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I534a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4948.#2441 I535 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I534a|I535a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002044] 4949.#2442 I534 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I534a|I535a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4949.#2443 I535 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I534a|I535a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4950.#2444 I536 Def ORDER(A) x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002926] 4957.#2445 V106 Use Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4958.#2446 I537 Def ORDER(A) x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I536a|I537a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002927] 4959.#2447 I537 Use * Keep x14 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106a| |I536a|I537a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002936] 4965.#2448 V106 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106i| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4966.#2449 I538 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|I538a| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004034] 4967.#2450 I536 Use * Keep x13 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|I538a| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4967.#2451 I538 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|I538a| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Restr x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106i| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002055] 4975.#2452 V107 Use * Keep x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|V107a|V106i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4976.#2453 I539 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |I539a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004036] 4981.#2454 V0 Use Keep x19 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |I539a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4981.#2455 I539 Use * Keep x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |I539a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4983.#2456 BB179 PredBB176 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004268] 4989.#2457 x0 Fixd Keep x0 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4989.#2458 V0 Use Spill x0 | |V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106a| | | | | |V0 i|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4990.#2459 x0 Fixd Keep x0 |V0 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4990.#2460 I540 Def Alloc x0 |I540a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004269] 4993.#2461 x1 Fixd Keep x1 |I540a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4993.#2462 V106 Use * Spill x1 |I540a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Copy x1 |I540a|V106a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4994.#2463 x1 Fixd Keep x1 |I540a| |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4994.#2464 I541 Def Alloc x1 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002939] 4996.#2465 C542 Def Alloc x11 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |C542a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004270] 4997.#2466 x11 Fixd Keep x11 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |C542a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4997.#2467 C542 Use * Keep x11 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |C542a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4998.#2468 x11 Fixd Keep x11 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4998.#2469 I543 Def Alloc x11 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| |I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002022] 4999.#2470 I544 Def ORDER(A) x10 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2471 x0 Fixd Keep x0 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2472 I540 Use * Keep x0 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2473 x1 Fixd Keep x1 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2474 I541 Use * Keep x1 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2475 x11 Fixd Keep x11 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2476 I543 Use * Keep x11 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2477 I544 Use * Keep x10 |I540a|I541a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2478 x0 Kill Keep x0 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2479 x1 Kill Keep x1 | | |V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2480 x2 Kill Spill x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 | | | |V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2481 x3 Kill Spill x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | | |V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2482 x4 Kill Spill x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | | |V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2483 x5 Kill Spill x5 | | | | | | |V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | | |V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2484 x6 Kill Spill x6 | | | | | | | |V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | | | | | |V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2485 x7 Kill Spill x7 | | | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 | | | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2486 x8 Kill Spill x8 | | | | | | | | | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x8 | | | | | | | | | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2487 x9 Kill Spill x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2488 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2489 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2490 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2491 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2492 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2493 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2494 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2495 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2496 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 5001.#2497 BB180 PredBB174 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002940] 5006.#2498 C545 Def COREL(A) x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000624] 5007.#2499 C545 Use * Keep x10 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5008.#2500 V21 Def BSFIT(A) x11 |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2501 V16 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2502 V0 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2503 V179 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2504 V4 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2505 V20 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2506 V34 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2507 V5 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2508 V8 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2509 V14 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2510 V36 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2511 V6 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2512 V12 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2513 V144 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2514 V9 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2515 V3 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2516 V1 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2517 V7 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2518 V143 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2519 V15 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2520 V17 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2521 V21 ExpU Keep NA |V36 a|V7 a|V8 a|V14 a|V16 a|V9 a|V143a|V12 a|V144a|V20 a|C545i|V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 5009.#2522 BB110 PredBB91 | | | | | | | | | | | | | | | | | | | | | | | | | | | | [002701] 5014.#2523 C546 Def Alloc x11 | | | | | | | | | | | |C546a| | | | | | | | | | | | | | | | [004302] 5015.#2524 x11 Fixd Keep x11 | | | | | | | | | | | |C546a| | | | | | | | | | | | | | | | 5015.#2525 C546 Use * Keep x11 | | | | | | | | | | | |C546a| | | | | | | | | | | | | | | | 5016.#2526 x11 Fixd Keep x11 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5016.#2527 I547 Def Alloc x11 | | | | | | | | | | | |I547a| | | | | | | | | | | | | | | | [001630] 5017.#2528 I548 Def ORDER(A) x0 |I548a| | | | | | | | | | |I547a| | | | | | | | | | | | | | | | 5017.#2529 x11 Fixd Keep x11 |I548a| | | | | | | | | | |I547a| | | | | | | | | | | | | | | | 5017.#2530 I547 Use * Keep x11 |I548a| | | | | | | | | | |I547a| | | | | | | | | | | | | | | | 5017.#2531 I548 Use * Keep x0 |I548a| | | | | | | | | | |I547a| | | | | | | | | | | | | | | | 5018.#2532 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2533 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2534 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2535 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2536 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2537 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2538 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2539 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2540 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2541 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2542 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2543 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2544 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2545 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2546 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2547 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2548 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2549 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2550 lr Kill Keep lr | | | | | | | | | | | | | | | | | | | | | | | | | | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 5019.#2551 BB254 PredBB0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | [004303] 5022.#2552 C549 Def ORDER(A) x0 |C549a| | | | | | | | | | | | | | | | | | | | | | | | | | | [004304] 5023.#2553 C549 Use * Keep x0 |C549a| | | | | | | | | | | | | | | | | | | | | | | | | | | 5024.#2554 I550 Def ORDER(A) x0 |I550a| | | | | | | | | | | | | | | | | | | | | | | | | | | [004154] 5025.#2555 I550 Use * Keep x0 |I550a| | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2556 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2557 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2558 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2559 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2560 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2561 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2562 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2563 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2564 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2565 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2566 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2567 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2568 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2569 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2570 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2571 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2572 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2573 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2574 lr Kill Keep lr | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[x19] minReg=1 regOptional wt=100.00> BB00 regmask=[x20] minReg=1 regOptional wt=100.00> BB00 regmask=[x21] minReg=1 regOptional wt=100.00> BB01 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 copy fixed wt=2150.00> BB01 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00> CNS_INT BB01 regmask=[x11] minReg=1 wt=400.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 last fixed wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x11] minReg=1 fixed wt=400.00> CALL BB01 regmask=[x1] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 last fixed wt=100.00> CALL BB01 regmask=[x1] minReg=1 last wt=400.00> BB01 regmask=[x0] minReg=1 last wt=100.00> BB01 regmask=[x1] minReg=1 last wt=100.00> BB01 regmask=[x2] minReg=1 last wt=100.00> BB01 regmask=[x3] minReg=1 last wt=100.00> BB01 regmask=[x4] minReg=1 last wt=100.00> BB01 regmask=[x5] minReg=1 last wt=100.00> BB01 regmask=[x6] minReg=1 last wt=100.00> BB01 regmask=[x7] minReg=1 last wt=100.00> BB01 regmask=[x8] minReg=1 last wt=100.00> BB01 regmask=[x9] minReg=1 last wt=100.00> BB01 regmask=[x10] minReg=1 last wt=100.00> BB01 regmask=[x11] minReg=1 last wt=100.00> BB01 regmask=[x12] minReg=1 last wt=100.00> BB01 regmask=[x13] minReg=1 last wt=100.00> BB01 regmask=[x14] minReg=1 last wt=100.00> BB01 regmask=[x15] minReg=1 last wt=100.00> BB01 regmask=[xip0] minReg=1 last wt=100.00> BB01 regmask=[xip1] minReg=1 last wt=100.00> BB01 regmask=[lr] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x22] minReg=1 wt=2700.00> LCL_VAR BB01 regmask=[x21] minReg=1 wt=2150.00> ADD BB01 regmask=[x0] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0] minReg=1 wt=600.00> IND BB01 regmask=[x1] minReg=1 wt=400.00> BB01 regmask=[x1] minReg=1 last wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 last wt=600.00> IND BB01 regmask=[x23] minReg=1 wt=400.00> BB01 regmask=[x23] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x23] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x23] minReg=1 last wt=400.00> STORE_LCL_VAR BB01 regmask=[x23] minReg=1 wt=1700.00> LCL_FLD BB01 regmask=[x24] minReg=1 wt=400.00> BB01 regmask=[x24] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x24] minReg=1 wt=1500.00> LCL_VAR BB01 regmask=[x24] minReg=1 wt=1500.00> STORE_LCL_VAR BB01 regmask=[x0] minReg=1 wt=200.00> LCL_FLD BB01 regmask=[x25] minReg=1 wt=400.00> BB01 regmask=[x25] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB01 regmask=[x25] minReg=1 wt=28400.00> STORE_LCL_VAR BB01 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB01 regmask=[x23] minReg=1 wt=1700.00> IND BB01 regmask=[x2] minReg=1 wt=400.00> BB01 regmask=[x2] minReg=1 last wt=100.00> LCL_VAR BB02 regmask=[x0] minReg=1 last wt=200.00> STORE_LCL_VAR BB02 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB02 regmask=[x1] minReg=1 last wt=200.00> STORE_LCL_VAR BB02 regmask=[x1] minReg=1 wt=150.00> LCL_VAR BB02 regmask=[x21] minReg=1 wt=2150.00> IND BB02 regmask=[x2] minReg=1 wt=200.00> BB02 regmask=[x2] minReg=1 last wt=50.00> LCL_VAR BB03 regmask=[x0] minReg=1 last wt=150.00> STORE_LCL_VAR BB03 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB03 regmask=[x1] minReg=1 last wt=150.00> STORE_LCL_VAR BB03 regmask=[x1] minReg=1 wt=250.00> STORE_LCL_VAR BB03 regmask=[x2] minReg=1 wt=250.00> LCL_VAR BB04 regmask=[x0] minReg=1 last wt=150.00> STORE_LCL_VAR BB04 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB04 regmask=[x1] minReg=1 last wt=150.00> STORE_LCL_VAR BB04 regmask=[x1] minReg=1 wt=250.00> CNS_INT BB04 regmask=[x2] minReg=1 wt=200.00> BB04 regmask=[x2] minReg=1 last wt=50.00> STORE_LCL_VAR BB04 regmask=[x2] minReg=1 wt=250.00> LCL_VAR BB05 regmask=[x0] minReg=1 last wt=200.00> STORE_LCL_VAR BB05 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB05 regmask=[x1] minReg=1 last wt=200.00> STORE_LCL_VAR BB05 regmask=[x1] minReg=1 wt=250.00> CNS_INT BB05 regmask=[x2] minReg=1 wt=200.00> BB05 regmask=[x2] minReg=1 last wt=50.00> STORE_LCL_VAR BB05 regmask=[x2] minReg=1 wt=250.00> BB06 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x0] minReg=1 last fixed wt=250.00> BB06 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x0] minReg=1 fixed wt=400.00> BB06 regmask=[x1] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x1] minReg=1 last fixed wt=250.00> BB06 regmask=[x1] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x1] minReg=1 fixed wt=400.00> BB06 regmask=[x2] minReg=1 wt=100.00> LCL_VAR BB06 regmask=[x2] minReg=1 last fixed wt=250.00> BB06 regmask=[x2] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x2] minReg=1 fixed wt=400.00> CNS_INT BB06 regmask=[x11] minReg=1 wt=400.00> BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 last fixed wt=100.00> BB06 regmask=[x11] minReg=1 wt=100.00> PUTARG_REG BB06 regmask=[x11] minReg=1 fixed wt=400.00> CALL BB06 regmask=[x3] minReg=1 wt=400.00> BB06 regmask=[x0] minReg=1 wt=100.00> BB06 regmask=[x0] minReg=1 last fixed wt=100.00> BB06 regmask=[x1] minReg=1 wt=100.00> BB06 regmask=[x1] minReg=1 last fixed wt=100.00> BB06 regmask=[x2] minReg=1 wt=100.00> BB06 regmask=[x2] minReg=1 last fixed wt=100.00> BB06 regmask=[x11] minReg=1 wt=100.00> BB06 regmask=[x11] minReg=1 last fixed wt=100.00> CALL BB06 regmask=[x3] minReg=1 last wt=400.00> BB06 regmask=[x0] minReg=1 last wt=100.00> BB06 regmask=[x1] minReg=1 last wt=100.00> BB06 regmask=[x2] minReg=1 last wt=100.00> BB06 regmask=[x3] minReg=1 last wt=100.00> BB06 regmask=[x4] minReg=1 last wt=100.00> BB06 regmask=[x5] minReg=1 last wt=100.00> BB06 regmask=[x6] minReg=1 last wt=100.00> BB06 regmask=[x7] minReg=1 last wt=100.00> BB06 regmask=[x8] minReg=1 last wt=100.00> BB06 regmask=[x9] minReg=1 last wt=100.00> BB06 regmask=[x10] minReg=1 last wt=100.00> BB06 regmask=[x11] minReg=1 last wt=100.00> BB06 regmask=[x12] minReg=1 last wt=100.00> BB06 regmask=[x13] minReg=1 last wt=100.00> BB06 regmask=[x14] minReg=1 last wt=100.00> BB06 regmask=[x15] minReg=1 last wt=100.00> BB06 regmask=[xip0] minReg=1 last wt=100.00> BB06 regmask=[xip1] minReg=1 last wt=100.00> BB06 regmask=[lr] minReg=1 last wt=100.00> BB06 regmask=[x0] minReg=1 wt=100.00> CALL BB06 regmask=[x0] minReg=1 fixed wt=400.00> BB06 regmask=[x0] minReg=1 last wt=100.00> STORE_LCL_VAR BB06 regmask=[x26] minReg=1 wt=1900.00> STORE_LCL_VAR BB07 regmask=[x27] minReg=1 wt=9600.00> CNS_INT BB07 regmask=[x28] minReg=1 wt=3200.00> BB07 regmask=[x28] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x28] minReg=1 wt=5600.00> CNS_INT BB07 regmask=[x3] minReg=1 wt=3200.00> BB07 regmask=[x3] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x3] minReg=1 spillAfter wt=2900.00> STORE_LCL_VAR BB07 regmask=[x4] minReg=1 spillAfter wt=2200.00> STORE_LCL_VAR BB07 regmask=[x5] minReg=1 wt=2400.00> CNS_INT BB07 regmask=[x6] minReg=1 wt=3200.00> BB07 regmask=[x6] minReg=1 last wt=800.00> STORE_LCL_VAR BB07 regmask=[x6] minReg=1 wt=4200.00> STORE_LCL_VAR BB07 regmask=[x7] minReg=1 wt=2800.00> STORE_LCL_VAR BB07 regmask=[x8] minReg=1 wt=4800.00> LCL_VAR BB07 regmask=[x26] minReg=1 wt=1900.00> STORE_LCL_VAR BB07 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB07 regmask=[x24] minReg=1 wt=1500.00> STORE_LCL_VAR BB07 regmask=[x9] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x9] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x9] minReg=1 last wt=2400.00> STORE_LCL_VAR BB07 regmask=[x9] minReg=1 wt=3200.00> LCL_VAR BB07 regmask=[x9] minReg=1 last wt=3200.00> STORE_LCL_VAR BB07 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB47 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB47 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB48 regmask=[x1] minReg=1 last wt=91300.00> STORE_LCL_VAR BB48 regmask=[x1] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x1] minReg=1 wt=9600.00> ADD BB48 regmask=[x0] minReg=1 wt=6400.00> BB48 regmask=[x0] minReg=1 last wt=1600.00> STORE_LCL_VAR BB48 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB48 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB48 regmask=[x1] minReg=1 last wt=9600.00> IND BB48 regmask=[x13] minReg=1 wt=6400.00> BB48 regmask=[x13] minReg=1 last wt=1600.00> STORE_LCL_VAR BB48 regmask=[x13] minReg=1 wt=6400.00> LCL_VAR BB48 regmask=[x13] minReg=1 last wt=6400.00> STORE_LCL_VAR BB48 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB48 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB49 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB08 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB09 regmask=[x13] minReg=1 wt=23700.00> ADD BB09 regmask=[x14] minReg=1 wt=3200.00> BB09 regmask=[x14] minReg=1 last wt=800.00> STORE_LCL_VAR BB09 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB09 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x13] minReg=1 wt=23700.00> ADD BB10 regmask=[x12] minReg=1 wt=3200.00> BB10 regmask=[x12] minReg=1 last wt=800.00> STORE_LCL_VAR BB10 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB11 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB13 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB14 regmask=[x13] minReg=1 wt=23700.00> CNS_INT BB15 regmask=[x1] minReg=1 wt=3200.00> LCL_VAR BB15 regmask=[x13] minReg=1 last wt=23700.00> BB15 regmask=[x1] minReg=1 last wt=800.00> LCL_VAR BB16 regmask=[x8] minReg=1 last wt=4800.00> ADD BB16 regmask=[x8] minReg=1 wt=3200.00> BB16 regmask=[x8] minReg=1 last wt=800.00> STORE_LCL_VAR BB16 regmask=[x8] minReg=1 wt=4800.00> LCL_VAR BB35 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB35 regmask=[x10] minReg=1 outOfOrder wt=91300.00> IND BB35 regmask=[x1] minReg=1 wt=3200.00> BB35 regmask=[x1] minReg=1 last wt=800.00> STORE_LCL_VAR BB35 regmask=[x1] minReg=1 wt=5600.00> LCL_VAR BB35 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB35 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB35 regmask=[x1] minReg=1 last wt=5600.00> LCL_VAR BB36 regmask=[x1] minReg=1 last outOfOrder wt=91300.00> ADD BB36 regmask=[x1] minReg=1 wt=3200.00> BB36 regmask=[x1] minReg=1 last wt=800.00> STORE_LCL_VAR BB36 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB38 regmask=[x10] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB38 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB39 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB39 regmask=[x10] minReg=1 wt=91300.00> IND BB39 regmask=[x1] minReg=1 wt=3200.00> BB39 regmask=[x1] minReg=1 last wt=800.00> STORE_LCL_VAR BB39 regmask=[x1] minReg=1 wt=5600.00> LCL_VAR BB39 regmask=[x1] minReg=1 last wt=5600.00> LCL_VAR BB40 regmask=[x10] minReg=1 wt=91300.00> ADD BB40 regmask=[x1] minReg=1 wt=3200.00> BB40 regmask=[x1] minReg=1 last wt=800.00> LCL_VAR BB40 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB41 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB41 regmask=[x1] minReg=1 outOfOrder wt=91300.00> IND BB41 regmask=[x0] minReg=1 wt=3200.00> BB41 regmask=[x0] minReg=1 last wt=800.00> STORE_LCL_VAR BB41 regmask=[x0] minReg=1 wt=5600.00> LCL_VAR BB41 regmask=[x0] minReg=1 wt=5600.00> LCL_VAR BB42 regmask=[x0] minReg=1 last wt=5600.00> LCL_VAR BB43 regmask=[x1] minReg=1 wt=91300.00> ADD BB43 regmask=[x0] minReg=1 wt=3200.00> LCL_VAR BB43 regmask=[x9] minReg=1 wt=18400.00> BB43 regmask=[x0] minReg=1 last wt=800.00> IND BB43 regmask=[x0] minReg=1 wt=3200.00> BB43 regmask=[x0] minReg=1 last wt=800.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB44 regmask=[x10] minReg=1 last outOfOrder wt=91300.00> ADD BB44 regmask=[x10] minReg=1 wt=25600.00> BB44 regmask=[x10] minReg=1 last wt=6400.00> STORE_LCL_VAR BB44 regmask=[x10] minReg=1 wt=25600.00> LCL_VAR BB44 regmask=[x10] minReg=1 last wt=25600.00> STORE_LCL_VAR BB44 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB44 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB44 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB45 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB45 regmask=[x10] minReg=1 wt=91300.00> IND BB45 regmask=[x5] minReg=1 wt=25600.00> BB45 regmask=[x5] minReg=1 last wt=6400.00> CNS_INT BB46 regmask=[x5] minReg=1 wt=3200.00> BB46 regmask=[x5] minReg=1 last wt=800.00> STORE_LCL_VAR BB46 regmask=[x5] minReg=1 wt=2400.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB50 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB51 regmask=[x27] minReg=1 wt=9600.00> STORE_LCL_VAR BB51 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB52 regmask=[x6] minReg=1 wt=4200.00> LCL_VAR BB53 regmask=[x6] minReg=1 last wt=4200.00> LCL_VAR BB53 regmask=[x28] minReg=1 wt=5600.00> CNS_INT BB54 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB54 regmask=[x8] minReg=1 last wt=4800.00> LCL_VAR BB54 regmask=[x22] minReg=1 wt=2700.00> BB54 regmask=[x1] minReg=1 last wt=200.00> SUB BB54 regmask=[x8] minReg=1 wt=800.00> BB54 regmask=[x8] minReg=1 last wt=200.00> STORE_LCL_VAR BB54 regmask=[x8] minReg=1 wt=4800.00> CNS_INT BB55 regmask=[x7] minReg=1 wt=800.00> BB55 regmask=[x7] minReg=1 last wt=200.00> STORE_LCL_VAR BB55 regmask=[x7] minReg=1 spillAfter wt=2800.00> LCL_VAR BB56 regmask=[x23] minReg=1 wt=1700.00> IND BB56 regmask=[x1] minReg=1 wt=3200.00> BB56 regmask=[x1] minReg=1 last wt=800.00> LCL_VAR BB57 regmask=[x21] minReg=1 wt=2150.00> ADD BB57 regmask=[x1] minReg=1 wt=1600.00> BB57 regmask=[x1] minReg=1 last wt=400.00> STORE_LCL_VAR BB57 regmask=[x1] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x1] minReg=1 wt=2400.00> IND BB57 regmask=[x0] minReg=1 wt=1600.00> BB57 regmask=[x0] minReg=1 last wt=400.00> LCL_VAR BB57 regmask=[x8] minReg=1 last wt=4800.00> ADD BB57 regmask=[x0] minReg=1 wt=1600.00> LCL_VAR BB57 regmask=[x1] minReg=1 last wt=2400.00> BB57 regmask=[x0] minReg=1 last wt=400.00> LCL_VAR BB57 regmask=[x5] minReg=1 spillAfter wt=2400.00> LCL_VAR BB58 regmask=[x21] minReg=1 wt=2150.00> IND BB58 regmask=[x1] minReg=1 wt=800.00> BB58 regmask=[x1] minReg=1 last wt=200.00> LCL_VAR BB58 regmask=[x27] minReg=1 wt=9600.00> ADD BB58 regmask=[x1] minReg=1 wt=800.00> BB58 regmask=[x1] minReg=1 last wt=200.00> LCL_VAR BB58 regmask=[x28] minReg=1 wt=5600.00> SUB BB58 regmask=[x1] minReg=1 wt=800.00> BB58 regmask=[x1] minReg=1 last wt=200.00> STORE_LCL_VAR BB58 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB59 regmask=[x27] minReg=1 wt=9600.00> STORE_LCL_VAR BB59 regmask=[x1] minReg=1 wt=800.00> BB60 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB60 regmask=[x1] minReg=1 last fixed wt=800.00> BB60 regmask=[x1] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x1] minReg=1 fixed wt=1600.00> BB60 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB60 regmask=[x0] minReg=1 copy fixed wt=2150.00> BB60 regmask=[x0] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x0] minReg=1 fixed wt=1600.00> CNS_INT BB60 regmask=[x11] minReg=1 wt=1600.00> BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 last fixed wt=400.00> BB60 regmask=[x11] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x11] minReg=1 fixed wt=1600.00> CNS_INT BB60 regmask=[x2] minReg=1 wt=1600.00> BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 last fixed wt=400.00> BB60 regmask=[x2] minReg=1 wt=400.00> PUTARG_REG BB60 regmask=[x2] minReg=1 fixed wt=1600.00> CALL BB60 regmask=[x6] minReg=1 wt=1600.00> BB60 regmask=[x1] minReg=1 wt=400.00> BB60 regmask=[x1] minReg=1 last fixed wt=400.00> BB60 regmask=[x0] minReg=1 wt=400.00> BB60 regmask=[x0] minReg=1 last fixed wt=400.00> BB60 regmask=[x11] minReg=1 wt=400.00> BB60 regmask=[x11] minReg=1 last fixed wt=400.00> BB60 regmask=[x2] minReg=1 wt=400.00> BB60 regmask=[x2] minReg=1 last fixed wt=400.00> CALL BB60 regmask=[x6] minReg=1 last wt=1600.00> BB60 regmask=[x0] minReg=1 last wt=400.00> BB60 regmask=[x1] minReg=1 last wt=400.00> BB60 regmask=[x2] minReg=1 last wt=400.00> BB60 regmask=[x3] minReg=1 last wt=400.00> BB60 regmask=[x4] minReg=1 last wt=400.00> BB60 regmask=[x5] minReg=1 last wt=400.00> BB60 regmask=[x6] minReg=1 last wt=400.00> BB60 regmask=[x7] minReg=1 last wt=400.00> BB60 regmask=[x8] minReg=1 last wt=400.00> BB60 regmask=[x9] minReg=1 last wt=400.00> BB60 regmask=[x10] minReg=1 last wt=400.00> BB60 regmask=[x11] minReg=1 last wt=400.00> BB60 regmask=[x12] minReg=1 last wt=400.00> BB60 regmask=[x13] minReg=1 last wt=400.00> BB60 regmask=[x14] minReg=1 last wt=400.00> BB60 regmask=[x15] minReg=1 last wt=400.00> BB60 regmask=[xip0] minReg=1 last wt=400.00> BB60 regmask=[xip1] minReg=1 last wt=400.00> BB60 regmask=[lr] minReg=1 last wt=400.00> LCL_VAR BB60 regmask=[x23] minReg=1 wt=1700.00> IND BB60 regmask=[x0] minReg=1 wt=1600.00> BB60 regmask=[x0] minReg=1 last wt=400.00> BB61 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB61 regmask=[x0] minReg=1 copy fixed wt=1500.00> BB61 regmask=[x0] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x0] minReg=1 fixed wt=1600.00> LCL_FLD BB61 regmask=[x1] minReg=1 wt=1600.00> BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 last fixed wt=400.00> BB61 regmask=[x1] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x1] minReg=1 fixed wt=1600.00> CNS_INT BB61 regmask=[x11] minReg=1 wt=1600.00> BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 last fixed wt=400.00> BB61 regmask=[x11] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x11] minReg=1 fixed wt=1600.00> CNS_INT BB61 regmask=[x2] minReg=1 wt=1600.00> BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 last fixed wt=400.00> BB61 regmask=[x2] minReg=1 wt=400.00> PUTARG_REG BB61 regmask=[x2] minReg=1 fixed wt=1600.00> CALL BB61 regmask=[x3] minReg=1 wt=1600.00> BB61 regmask=[x0] minReg=1 wt=400.00> BB61 regmask=[x0] minReg=1 last fixed wt=400.00> BB61 regmask=[x1] minReg=1 wt=400.00> BB61 regmask=[x1] minReg=1 last fixed wt=400.00> BB61 regmask=[x11] minReg=1 wt=400.00> BB61 regmask=[x11] minReg=1 last fixed wt=400.00> BB61 regmask=[x2] minReg=1 wt=400.00> BB61 regmask=[x2] minReg=1 last fixed wt=400.00> CALL BB61 regmask=[x3] minReg=1 last wt=1600.00> BB61 regmask=[x0] minReg=1 last wt=400.00> BB61 regmask=[x1] minReg=1 last wt=400.00> BB61 regmask=[x2] minReg=1 last wt=400.00> BB61 regmask=[x3] minReg=1 last wt=400.00> BB61 regmask=[x4] minReg=1 last wt=400.00> BB61 regmask=[x5] minReg=1 last wt=400.00> BB61 regmask=[x6] minReg=1 last wt=400.00> BB61 regmask=[x7] minReg=1 last wt=400.00> BB61 regmask=[x8] minReg=1 last wt=400.00> BB61 regmask=[x9] minReg=1 last wt=400.00> BB61 regmask=[x10] minReg=1 last wt=400.00> BB61 regmask=[x11] minReg=1 last wt=400.00> BB61 regmask=[x12] minReg=1 last wt=400.00> BB61 regmask=[x13] minReg=1 last wt=400.00> BB61 regmask=[x14] minReg=1 last wt=400.00> BB61 regmask=[x15] minReg=1 last wt=400.00> BB61 regmask=[xip0] minReg=1 last wt=400.00> BB61 regmask=[xip1] minReg=1 last wt=400.00> BB61 regmask=[lr] minReg=1 last wt=400.00> BB61 regmask=[x0] minReg=1 wt=400.00> CALL BB61 regmask=[x0] minReg=1 fixed wt=1600.00> BB61 regmask=[x0] minReg=1 last wt=400.00> STORE_LCL_VAR BB61 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB61 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB61 regmask=[x26] minReg=1 wt=1900.00> LCL_VAR BB62 regmask=[x1] minReg=1 last wt=91300.00> STORE_LCL_VAR BB62 regmask=[x26] minReg=1 wt=1900.00> BB62 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB63 regmask=[x21] minReg=1 wt=2150.00> IND BB63 regmask=[x1] minReg=1 wt=200.00> BB63 regmask=[x1] minReg=1 last wt=50.00> LCL_VAR BB64 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB65 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB66 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x3] minReg=1 wt=2900.00> SUB BB66 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB66 regmask=[x3] minReg=1 last wt=2900.00> LCL_VAR BB66 regmask=[x28] minReg=1 wt=5600.00> BB66 regmask=[x0] minReg=1 last wt=100.00> SELECT BB66 regmask=[x3] minReg=1 wt=400.00> BB66 regmask=[x3] minReg=1 last wt=100.00> STORE_LCL_VAR BB66 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x3] minReg=1 last wt=200.00> STORE_LCL_VAR BB66 regmask=[x22] minReg=1 wt=2900.00> LCL_VAR BB66 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x4] minReg=1 wt=2200.00> SUB BB66 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB66 regmask=[x4] minReg=1 last wt=2200.00> LCL_VAR BB66 regmask=[x28] minReg=1 wt=5600.00> BB66 regmask=[x0] minReg=1 last wt=100.00> SELECT BB66 regmask=[x4] minReg=1 wt=400.00> BB66 regmask=[x4] minReg=1 last wt=100.00> STORE_LCL_VAR BB66 regmask=[x4] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x4] minReg=1 last wt=200.00> STORE_LCL_VAR BB66 regmask=[x1] minReg=1 spillAfter wt=2200.00> LCL_VAR BB66 regmask=[x5] minReg=1 spillAfter wt=2400.00> LCL_VAR BB73 regmask=[x28] minReg=1 wt=5600.00> STORE_LCL_VAR BB73 regmask=[x2] minReg=1 wt=4650.00> STORE_LCL_VAR BB73 regmask=[x3] minReg=1 wt=4100.00> LCL_VAR BB74 regmask=[x21] minReg=1 wt=2150.00> IND BB74 regmask=[x3] minReg=1 wt=200.00> BB74 regmask=[x3] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x28] minReg=1 wt=5600.00> SELECT BB74 regmask=[x2] minReg=1 wt=200.00> BB74 regmask=[x2] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x2] minReg=1 wt=100.00> LCL_VAR BB74 regmask=[x2] minReg=1 last wt=100.00> STORE_LCL_VAR BB74 regmask=[x2] minReg=1 wt=4650.00> LCL_VAR BB74 regmask=[x3] minReg=1 last wt=200.00> LCL_VAR BB74 regmask=[x28] minReg=1 wt=5600.00> SUB BB74 regmask=[x3] minReg=1 wt=200.00> BB74 regmask=[x3] minReg=1 last wt=50.00> STORE_LCL_VAR BB74 regmask=[x3] minReg=1 wt=4100.00> LCL_VAR BB78 regmask=[x26] minReg=1 wt=1900.00> STORE_LCL_VAR BB78 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR_ADDR BB78 regmask=[x6] minReg=1 wt=400.00> BB78 regmask=[x6] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x6] minReg=1 wt=200.00> LCL_VAR BB78 regmask=[x6] minReg=1 last wt=200.00> STORE_LCL_VAR BB78 regmask=[x6] minReg=1 spillAfter wt=1800.00> CNS_INT BB78 regmask=[x8] minReg=1 wt=400.00> BB78 regmask=[x8] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x8] minReg=1 wt=2600.00> CNS_INT BB78 regmask=[x9] minReg=1 wt=400.00> BB78 regmask=[x9] minReg=1 last wt=100.00> STORE_LCL_VAR BB78 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB78 regmask=[x20] minReg=1 wt=2250.00> IND BB78 regmask=[x0] minReg=1 wt=400.00> BB78 regmask=[x0] minReg=1 last wt=100.00> IND BB78 regmask=[x0] minReg=1 wt=400.00> BB78 regmask=[x0] minReg=1 last wt=100.00> LCL_VAR BB78 regmask=[x7] minReg=1 spillAfter wt=2800.00> LCL_VAR BB79 regmask=[x20] minReg=1 wt=2250.00> IND BB79 regmask=[x10] minReg=1 wt=200.00> BB79 regmask=[x10] minReg=1 last wt=50.00> STORE_LCL_VAR BB79 regmask=[x10] minReg=1 singleDefSpill wt=275.00> STORE_LCL_VAR BB79 regmask=[x13] minReg=1 spillAfter wt=1150.00> STORE_LCL_VAR BB79 regmask=[x14] minReg=1 wt=1650.00> LCL_VAR BB79 regmask=[x10] minReg=1 wt=275.00> IND BB79 regmask=[x12] minReg=1 wt=200.00> BB79 regmask=[x12] minReg=1 last wt=50.00> STORE_LCL_VAR BB79 regmask=[x12] minReg=1 singleDefSpill wt=250.00> LCL_VAR BB79 regmask=[x12] minReg=1 spillAfter wt=250.00> LCL_VAR BB81 regmask=[x10] minReg=1 spillAfter wt=275.00> IND BB81 regmask=[x14] minReg=1 wt=200.00> BB81 regmask=[x14] minReg=1 last wt=50.00> STORE_LCL_VAR BB81 regmask=[x14] minReg=1 wt=1650.00> LCL_VAR BB82 regmask=[x14] minReg=1 spillAfter wt=1650.00> STORE_LCL_VAR BB82 regmask=[x15] minReg=1 wt=1000.00> LCL_VAR BB82 regmask=[x2] minReg=1 spillAfter wt=4650.00> STORE_LCL_VAR BB82 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB82 regmask=[x3] minReg=1 wt=4100.00> LCL_VAR BB83 regmask=[x0] minReg=1 last wt=150.00> STORE_LCL_VAR BB83 regmask=[x0] minReg=1 wt=150.00> STORE_LCL_VAR BB83 regmask=[x11] minReg=1 wt=150.00> LCL_VAR BB84 regmask=[x0] minReg=1 last wt=150.00> STORE_LCL_VAR BB84 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB84 regmask=[x3] minReg=1 spillAfter wt=4100.00> STORE_LCL_VAR BB84 regmask=[x11] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0] minReg=1 last wt=150.00> LCL_VAR BB85 regmask=[x11] minReg=1 last wt=150.00> ADD BB85 regmask=[x0] minReg=1 wt=200.00> BB85 regmask=[x0] minReg=1 last wt=50.00> STORE_LCL_VAR BB85 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x22] minReg=1 wt=2900.00> LCL_VAR BB85 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x22] minReg=1 wt=2900.00> LCL_VAR BB85 regmask=[x0] minReg=1 last wt=150.00> SELECT BB85 regmask=[xip0] minReg=1 wt=200.00> BB85 regmask=[xip0] minReg=1 last wt=50.00> STORE_LCL_VAR BB85 regmask=[xip0] minReg=1 wt=100.00> LCL_VAR BB85 regmask=[xip0] minReg=1 last wt=100.00> STORE_LCL_VAR BB85 regmask=[xip0] minReg=1 singleDefSpill wt=250.00> LCL_VAR BB85 regmask=[xip0] minReg=1 spillAfter wt=250.00> LCL_VAR BB85 regmask=[x15] minReg=1 wt=1000.00> LCL_VAR BB89 regmask=[x15] minReg=1 spillAfter wt=1000.00> LCL_VAR BB90 regmask=[x9] minReg=1 last wt=7000.00> ADD BB90 regmask=[x9] minReg=1 wt=1600.00> BB90 regmask=[x9] minReg=1 last wt=400.00> STORE_LCL_VAR BB90 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB90 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB90 regmask=[x8] minReg=1 wt=2600.00> LCL_VAR BB91 regmask=[x8] minReg=1 spillAfter wt=2600.00> LSH BB91 regmask=[x0] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 last regOptional wt=200.00> CAST BB91 regmask=[x0] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x0] minReg=1 last fixed wt=200.00> BB91 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB91 regmask=[x0] minReg=1 fixed wt=800.00> CNS_INT BB91 regmask=[x11] minReg=1 wt=800.00> BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 last fixed wt=200.00> BB91 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB91 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB91 regmask=[x12] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 wt=200.00> BB91 regmask=[x0] minReg=1 last fixed wt=200.00> BB91 regmask=[x11] minReg=1 wt=200.00> BB91 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB91 regmask=[x12] minReg=1 last wt=800.00> BB91 regmask=[x0] minReg=1 last wt=200.00> BB91 regmask=[x1] minReg=1 last wt=200.00> BB91 regmask=[x2] minReg=1 last wt=200.00> BB91 regmask=[x3] minReg=1 last wt=200.00> BB91 regmask=[x4] minReg=1 last wt=200.00> BB91 regmask=[x5] minReg=1 last wt=200.00> BB91 regmask=[x6] minReg=1 last wt=200.00> BB91 regmask=[x7] minReg=1 last wt=200.00> BB91 regmask=[x8] minReg=1 last wt=200.00> BB91 regmask=[x9] minReg=1 last wt=200.00> BB91 regmask=[x10] minReg=1 last wt=200.00> BB91 regmask=[x11] minReg=1 last wt=200.00> BB91 regmask=[x12] minReg=1 last wt=200.00> BB91 regmask=[x13] minReg=1 last wt=200.00> BB91 regmask=[x14] minReg=1 last wt=200.00> BB91 regmask=[x15] minReg=1 last wt=200.00> BB91 regmask=[xip0] minReg=1 last wt=200.00> BB91 regmask=[xip1] minReg=1 last wt=200.00> BB91 regmask=[lr] minReg=1 last wt=200.00> BB91 regmask=[x0] minReg=1 wt=200.00> CALL BB91 regmask=[x0] minReg=1 fixed wt=800.00> BB91 regmask=[x0] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x3] minReg=1 singleDefSpill wt=500.00> LCL_VAR BB91 regmask=[x3] minReg=1 wt=500.00> ADD BB91 regmask=[x0] minReg=1 wt=800.00> BB91 regmask=[x0] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x3] minReg=1 spillAfter wt=500.00> IND BB91 regmask=[x2] minReg=1 wt=800.00> BB91 regmask=[x2] minReg=1 last wt=200.00> STORE_LCL_VAR BB91 regmask=[x2] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0] minReg=1 last wt=400.00> STORE_LCL_VAR BB91 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x4] minReg=1 reload wt=2600.00> LCL_VAR BB91 regmask=[x2] minReg=1 last wt=400.00> LCL_VAR BB95 regmask=[x4] minReg=1 last regOptional wt=2600.00> CAST BB95 regmask=[x2] minReg=1 wt=800.00> BB95 regmask=[x2] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x2] minReg=1 wt=800.00> LCL_VAR BB95 regmask=[x2] minReg=1 last wt=800.00> LSH BB95 regmask=[x2] minReg=1 wt=800.00> BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 last fixed wt=200.00> BB95 regmask=[x2] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x2] minReg=1 fixed wt=800.00> BB95 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB95 regmask=[x0] minReg=1 last fixed wt=400.00> BB95 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x0] minReg=1 fixed wt=800.00> BB95 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB95 regmask=[x1] minReg=1 last reload fixed wt=1800.00> BB95 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB95 regmask=[x11] minReg=1 wt=800.00> BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 last fixed wt=200.00> BB95 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB95 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB95 regmask=[x4] minReg=1 wt=800.00> BB95 regmask=[x2] minReg=1 wt=200.00> BB95 regmask=[x2] minReg=1 last fixed wt=200.00> BB95 regmask=[x0] minReg=1 wt=200.00> BB95 regmask=[x0] minReg=1 last fixed wt=200.00> BB95 regmask=[x1] minReg=1 wt=200.00> BB95 regmask=[x1] minReg=1 last fixed wt=200.00> BB95 regmask=[x11] minReg=1 wt=200.00> BB95 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB95 regmask=[x4] minReg=1 last wt=800.00> BB95 regmask=[x0] minReg=1 last wt=200.00> BB95 regmask=[x1] minReg=1 last wt=200.00> BB95 regmask=[x2] minReg=1 last wt=200.00> BB95 regmask=[x3] minReg=1 last wt=200.00> BB95 regmask=[x4] minReg=1 last wt=200.00> BB95 regmask=[x5] minReg=1 last wt=200.00> BB95 regmask=[x6] minReg=1 last wt=200.00> BB95 regmask=[x7] minReg=1 last wt=200.00> BB95 regmask=[x8] minReg=1 last wt=200.00> BB95 regmask=[x9] minReg=1 last wt=200.00> BB95 regmask=[x10] minReg=1 last wt=200.00> BB95 regmask=[x11] minReg=1 last wt=200.00> BB95 regmask=[x12] minReg=1 last wt=200.00> BB95 regmask=[x13] minReg=1 last wt=200.00> BB95 regmask=[x14] minReg=1 last wt=200.00> BB95 regmask=[x15] minReg=1 last wt=200.00> BB95 regmask=[xip0] minReg=1 last wt=200.00> BB95 regmask=[xip1] minReg=1 last wt=200.00> BB95 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB95 regmask=[x0] minReg=1 reload wt=500.00> ADD BB95 regmask=[x1] minReg=1 wt=800.00> BB95 regmask=[x1] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0] minReg=1 last wt=500.00> IND BB95 regmask=[x4] minReg=1 wt=800.00> BB95 regmask=[x4] minReg=1 last wt=200.00> STORE_LCL_VAR BB95 regmask=[x4] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x1] minReg=1 last wt=400.00> STORE_LCL_VAR BB95 regmask=[x2] minReg=1 wt=1800.00> LCL_VAR BB95 regmask=[x4] minReg=1 last wt=400.00> STORE_LCL_VAR BB95 regmask=[x3] minReg=1 wt=2600.00> LCL_VAR BB100 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB100 regmask=[x8] minReg=1 spillAfter outOfOrder wt=2600.00> LCL_VAR BB100 regmask=[x6] minReg=1 spillAfter outOfOrder wt=1800.00> LCL_VAR BB100 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB100 regmask=[x14] minReg=1 wt=1650.00> LCL_VAR BB100 regmask=[x12] minReg=1 wt=250.00> ADD BB100 regmask=[x0] minReg=1 wt=1600.00> LCL_VAR BB100 regmask=[x13] minReg=1 wt=1150.00> BB100 regmask=[x0] minReg=1 last wt=400.00> LCL_VAR BB101 regmask=[x13] minReg=1 last wt=1150.00> ADD BB101 regmask=[x13] minReg=1 wt=800.00> BB101 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB101 regmask=[x13] minReg=1 wt=1150.00> LCL_VAR BB101 regmask=[x10] minReg=1 wt=275.00> IND BB101 regmask=[x15] minReg=1 wt=800.00> LCL_VAR BB101 regmask=[x13] minReg=1 wt=1150.00> BB101 regmask=[x15] minReg=1 last wt=200.00> LCL_VAR BB101 regmask=[x10] minReg=1 wt=275.00> ADD BB101 regmask=[x0] minReg=1 wt=800.00> BB101 regmask=[x0] minReg=1 last wt=200.00> LCL_VAR BB101 regmask=[x13] minReg=1 wt=1150.00> IND BB101 regmask=[x15] minReg=1 wt=800.00> BB101 regmask=[x15] minReg=1 last wt=200.00> STORE_LCL_VAR BB101 regmask=[x0] minReg=1 wt=1000.00> LCL_VAR BB102 regmask=[x14] minReg=1 last wt=1650.00> LCL_VAR BB102 regmask=[x15] minReg=1 outOfOrder wt=1000.00> ADD BB102 regmask=[x14] minReg=1 wt=1600.00> BB102 regmask=[x14] minReg=1 last wt=400.00> STORE_LCL_VAR BB102 regmask=[x14] minReg=1 wt=1650.00> LCL_VAR BB102 regmask=[xip0] minReg=1 wt=250.00> LCL_VAR BB102 regmask=[x14] minReg=1 wt=1650.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB103 regmask=[x21] minReg=1 wt=2150.00> IND BB103 regmask=[x0] minReg=1 wt=400.00> BB103 regmask=[x0] minReg=1 last wt=100.00> LCL_VAR BB103 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB104 regmask=[x21] minReg=1 wt=2150.00> IND BB104 regmask=[x0] minReg=1 wt=200.00> BB104 regmask=[x0] minReg=1 last wt=50.00> LCL_VAR BB106 regmask=[x20] minReg=1 wt=2250.00> IND BB106 regmask=[x11] minReg=1 wt=200.00> BB106 regmask=[x11] minReg=1 last wt=50.00> STORE_LCL_VAR BB106 regmask=[x11] minReg=1 wt=500.00> LCL_VAR BB106 regmask=[x11] minReg=1 wt=500.00> LCL_VAR BB107 regmask=[x19] minReg=1 wt=26550.00> IND BB107 regmask=[x0] minReg=1 wt=200.00> BB107 regmask=[x0] minReg=1 last wt=50.00> STORE_LCL_VAR BB107 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB107 regmask=[x11] minReg=1 wt=500.00> IND BB107 regmask=[x10] minReg=1 wt=200.00> LCL_VAR BB107 regmask=[x19] minReg=1 wt=26550.00> IND BB107 regmask=[x13] minReg=1 wt=200.00> BB107 regmask=[x10] minReg=1 last wt=50.00> LCL_VAR BB107 regmask=[x0] minReg=1 wt=250.00> BB107 regmask=[x13] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x19] minReg=1 wt=26550.00> ADD BB108 regmask=[x10] minReg=1 wt=200.00> BB108 regmask=[x10] minReg=1 last wt=50.00> STORE_LCL_VAR BB108 regmask=[x10] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x10] minReg=1 wt=300.00> IND BB108 regmask=[x13] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0] minReg=1 wt=250.00> BB108 regmask=[x13] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x10] minReg=1 last wt=300.00> IND BB108 regmask=[x10] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x0] minReg=1 wt=250.00> BFIZ BB108 regmask=[x13] minReg=1 wt=200.00> BB108 regmask=[x10] minReg=1 last wt=50.00> BB108 regmask=[x13] minReg=1 last wt=50.00> ADD BB108 regmask=[x10] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x11] minReg=1 last wt=500.00> IND BB108 regmask=[x11] minReg=1 wt=200.00> BB108 regmask=[x10] minReg=1 last wt=50.00> BB108 regmask=[x11] minReg=1 last wt=50.00> LCL_VAR BB108 regmask=[x0] minReg=1 last wt=250.00> ADD BB108 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB108 regmask=[x19] minReg=1 wt=26550.00> BB108 regmask=[x0] minReg=1 last wt=50.00> BB111 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB111 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB111 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x0] minReg=1 fixed wt=200.00> BB111 regmask=[x1] minReg=1 wt=50.00> LCL_VAR BB111 regmask=[x1] minReg=1 last copy fixed wt=500.00> BB111 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x1] minReg=1 fixed wt=200.00> CNS_INT BB111 regmask=[x11] minReg=1 wt=200.00> BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 last fixed wt=50.00> BB111 regmask=[x11] minReg=1 wt=50.00> PUTARG_REG BB111 regmask=[x11] minReg=1 fixed wt=200.00> CALL BB111 regmask=[x10] minReg=1 wt=200.00> BB111 regmask=[x0] minReg=1 wt=50.00> BB111 regmask=[x0] minReg=1 last fixed wt=50.00> BB111 regmask=[x1] minReg=1 wt=50.00> BB111 regmask=[x1] minReg=1 last fixed wt=50.00> BB111 regmask=[x11] minReg=1 wt=50.00> BB111 regmask=[x11] minReg=1 last fixed wt=50.00> CALL BB111 regmask=[x10] minReg=1 last wt=200.00> BB111 regmask=[x0] minReg=1 last wt=50.00> BB111 regmask=[x1] minReg=1 last wt=50.00> BB111 regmask=[x2] minReg=1 last wt=50.00> BB111 regmask=[x3] minReg=1 last wt=50.00> BB111 regmask=[x4] minReg=1 last wt=50.00> BB111 regmask=[x5] minReg=1 last wt=50.00> BB111 regmask=[x6] minReg=1 last wt=50.00> BB111 regmask=[x7] minReg=1 last wt=50.00> BB111 regmask=[x8] minReg=1 last wt=50.00> BB111 regmask=[x9] minReg=1 last wt=50.00> BB111 regmask=[x10] minReg=1 last wt=50.00> BB111 regmask=[x11] minReg=1 last wt=50.00> BB111 regmask=[x12] minReg=1 last wt=50.00> BB111 regmask=[x13] minReg=1 last wt=50.00> BB111 regmask=[x14] minReg=1 last wt=50.00> BB111 regmask=[x15] minReg=1 last wt=50.00> BB111 regmask=[xip0] minReg=1 last wt=50.00> BB111 regmask=[xip1] minReg=1 last wt=50.00> BB111 regmask=[lr] minReg=1 last wt=50.00> STORE_LCL_VAR BB112 regmask=[x10] minReg=1 spillAfter wt=400.00> LCL_VAR BB112 regmask=[x24] minReg=1 last wt=1500.00> STORE_LCL_VAR BB112 regmask=[x24] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x24] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x24] minReg=1 last wt=300.00> STORE_LCL_VAR BB112 regmask=[x24] minReg=1 wt=400.00> LCL_VAR BB112 regmask=[x24] minReg=1 last wt=400.00> STORE_LCL_VAR BB112 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB112 regmask=[x23] minReg=1 wt=1700.00> STORE_LCL_VAR BB112 regmask=[x0] minReg=1 wt=3200.00> LCL_VAR BB245 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB245 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB246 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB246 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x11] minReg=1 wt=2400.00> ADD BB246 regmask=[x4] minReg=1 wt=1600.00> BB246 regmask=[x4] minReg=1 last wt=400.00> STORE_LCL_VAR BB246 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB246 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB246 regmask=[x11] minReg=1 last wt=2400.00> IND BB246 regmask=[x13] minReg=1 wt=1600.00> BB246 regmask=[x13] minReg=1 last wt=400.00> STORE_LCL_VAR BB246 regmask=[x13] minReg=1 wt=1600.00> LCL_VAR BB246 regmask=[x13] minReg=1 last wt=1600.00> STORE_LCL_VAR BB246 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB246 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB247 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB113 regmask=[x3] minReg=1 wt=4100.00> CNS_INT BB114 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB114 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB114 regmask=[x13] minReg=1 wt=23700.00> BB114 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB115 regmask=[x13] minReg=1 spillAfter wt=23700.00> LCL_VAR BB135 regmask=[x3] minReg=1 spillAfter wt=4100.00> LCL_VAR BB118 regmask=[x0] minReg=1 wt=3200.00> IND BB118 regmask=[x11] minReg=1 wt=3200.00> BB118 regmask=[x11] minReg=1 last wt=800.00> STORE_LCL_VAR BB118 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB118 regmask=[x11] minReg=1 wt=2400.00> CNS_INT BB119 regmask=[x14] minReg=1 wt=3200.00> BB119 regmask=[x14] minReg=1 last wt=800.00> STORE_LCL_VAR BB119 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB120 regmask=[x0] minReg=1 last wt=3200.00> STORE_LCL_VAR BB120 regmask=[x0] minReg=1 wt=3200.00> LCL_VAR BB120 regmask=[x0] minReg=1 last wt=3200.00> ADD BB120 regmask=[x0] minReg=1 wt=3200.00> BB120 regmask=[x0] minReg=1 last wt=800.00> STORE_LCL_VAR BB120 regmask=[x12] minReg=1 spillAfter wt=3200.00> LCL_VAR BB120 regmask=[x11] minReg=1 last wt=2400.00> STORE_LCL_VAR BB120 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB121 regmask=[x14] minReg=1 last regOptional wt=2400.00> CAST BB121 regmask=[x11] minReg=1 wt=3200.00> BB121 regmask=[x11] minReg=1 last wt=800.00> STORE_LCL_VAR BB121 regmask=[x11] minReg=1 wt=4800.00> LCL_VAR BB121 regmask=[x19] minReg=1 wt=26550.00> IND BB121 regmask=[x14] minReg=1 wt=3200.00> BB121 regmask=[x14] minReg=1 last wt=800.00> STORE_LCL_VAR BB121 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB121 regmask=[x19] minReg=1 wt=26550.00> IND BB121 regmask=[x12] minReg=1 wt=3200.00> LCL_VAR BB121 regmask=[x14] minReg=1 wt=4000.00> BB121 regmask=[x12] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x19] minReg=1 wt=26550.00> ADD BB122 regmask=[x12] minReg=1 wt=3200.00> BB122 regmask=[x12] minReg=1 last wt=800.00> STORE_LCL_VAR BB122 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x12] minReg=1 wt=4800.00> IND BB122 regmask=[x15] minReg=1 wt=3200.00> LCL_VAR BB122 regmask=[x14] minReg=1 wt=4000.00> BB122 regmask=[x15] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x12] minReg=1 last wt=4800.00> IND BB122 regmask=[x12] minReg=1 wt=3200.00> BB122 regmask=[x12] minReg=1 last wt=800.00> LCL_VAR BB122 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x11] minReg=1 last wt=4800.00> LCL_VAR BB122 regmask=[x14] minReg=1 last wt=4000.00> ADD BB122 regmask=[x11] minReg=1 wt=3200.00> LCL_VAR BB122 regmask=[x19] minReg=1 wt=26550.00> BB122 regmask=[x11] minReg=1 last wt=800.00> BB123 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB123 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB123 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x0] minReg=1 fixed wt=3200.00> BB123 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB123 regmask=[x1] minReg=1 last copy fixed wt=4800.00> BB123 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB123 regmask=[x11] minReg=1 wt=3200.00> BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 last fixed wt=800.00> BB123 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB123 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB123 regmask=[x14] minReg=1 wt=3200.00> BB123 regmask=[x0] minReg=1 wt=800.00> BB123 regmask=[x0] minReg=1 last fixed wt=800.00> BB123 regmask=[x1] minReg=1 wt=800.00> BB123 regmask=[x1] minReg=1 last fixed wt=800.00> BB123 regmask=[x11] minReg=1 wt=800.00> BB123 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB123 regmask=[x14] minReg=1 last wt=3200.00> BB123 regmask=[x0] minReg=1 last wt=800.00> BB123 regmask=[x1] minReg=1 last wt=800.00> BB123 regmask=[x2] minReg=1 last wt=800.00> BB123 regmask=[x3] minReg=1 last wt=800.00> BB123 regmask=[x4] minReg=1 last wt=800.00> BB123 regmask=[x5] minReg=1 last wt=800.00> BB123 regmask=[x6] minReg=1 last wt=800.00> BB123 regmask=[x7] minReg=1 last wt=800.00> BB123 regmask=[x8] minReg=1 last wt=800.00> BB123 regmask=[x9] minReg=1 last wt=800.00> BB123 regmask=[x10] minReg=1 last wt=800.00> BB123 regmask=[x11] minReg=1 last wt=800.00> BB123 regmask=[x12] minReg=1 last wt=800.00> BB123 regmask=[x13] minReg=1 last wt=800.00> BB123 regmask=[x14] minReg=1 last wt=800.00> BB123 regmask=[x15] minReg=1 last wt=800.00> BB123 regmask=[xip0] minReg=1 last wt=800.00> BB123 regmask=[xip1] minReg=1 last wt=800.00> BB123 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB124 regmask=[x7] minReg=1 spillAfter wt=2800.00> LCL_VAR BB124 regmask=[x2] minReg=1 wt=4650.00> LCL_VAR BB125 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB125 regmask=[x8] minReg=1 spillAfter wt=2600.00> LCL_VAR BB125 regmask=[x6] minReg=1 spillAfter wt=1800.00> LCL_VAR BB125 regmask=[x9] minReg=1 wt=7000.00> IND BB125 regmask=[x11] minReg=1 wt=3200.00> BB125 regmask=[x11] minReg=1 last wt=800.00> ADD BB125 regmask=[x11] minReg=1 wt=3200.00> BB125 regmask=[x11] minReg=1 last wt=800.00> LCL_VAR BB125 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB125 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB127 regmask=[x20] minReg=1 wt=2250.00> IND BB127 regmask=[x11] minReg=1 wt=3200.00> BB127 regmask=[x11] minReg=1 last wt=800.00> STORE_LCL_VAR BB127 regmask=[x11] minReg=1 wt=8000.00> LCL_VAR BB127 regmask=[x11] minReg=1 wt=8000.00> LCL_VAR BB129 regmask=[x19] minReg=1 wt=26550.00> IND BB129 regmask=[x14] minReg=1 wt=3200.00> BB129 regmask=[x14] minReg=1 last wt=800.00> STORE_LCL_VAR BB129 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB129 regmask=[x11] minReg=1 wt=8000.00> IND BB129 regmask=[x12] minReg=1 wt=3200.00> BB129 regmask=[x12] minReg=1 last wt=800.00> STORE_LCL_VAR BB129 regmask=[x12] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x19] minReg=1 wt=26550.00> IND BB129 regmask=[x15] minReg=1 wt=3200.00> LCL_VAR BB129 regmask=[x12] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x14] minReg=1 wt=4000.00> BB129 regmask=[x15] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x19] minReg=1 wt=26550.00> ADD BB130 regmask=[x15] minReg=1 wt=3200.00> BB130 regmask=[x15] minReg=1 last wt=800.00> STORE_LCL_VAR BB130 regmask=[x15] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x15] minReg=1 wt=4800.00> IND BB130 regmask=[xip0] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x14] minReg=1 wt=4000.00> BB130 regmask=[xip0] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x15] minReg=1 last wt=4800.00> IND BB130 regmask=[x15] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x14] minReg=1 wt=4000.00> BFIZ BB130 regmask=[xip0] minReg=1 wt=3200.00> BB130 regmask=[x15] minReg=1 last wt=800.00> BB130 regmask=[xip0] minReg=1 last wt=800.00> ADD BB130 regmask=[x15] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x12] minReg=1 last wt=2400.00> LCL_VAR BB130 regmask=[x11] minReg=1 last wt=8000.00> IND BB130 regmask=[x11] minReg=1 wt=3200.00> BB130 regmask=[x15] minReg=1 last wt=800.00> BB130 regmask=[x11] minReg=1 last wt=800.00> LCL_VAR BB130 regmask=[x14] minReg=1 last wt=4000.00> ADD BB130 regmask=[x11] minReg=1 wt=3200.00> LCL_VAR BB130 regmask=[x19] minReg=1 wt=26550.00> BB130 regmask=[x11] minReg=1 last wt=800.00> BB132 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB132 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB132 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x0] minReg=1 fixed wt=3200.00> BB132 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB132 regmask=[x1] minReg=1 last copy fixed wt=8000.00> BB132 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB132 regmask=[x11] minReg=1 wt=3200.00> BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 last fixed wt=800.00> BB132 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB132 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB132 regmask=[x14] minReg=1 wt=3200.00> BB132 regmask=[x0] minReg=1 wt=800.00> BB132 regmask=[x0] minReg=1 last fixed wt=800.00> BB132 regmask=[x1] minReg=1 wt=800.00> BB132 regmask=[x1] minReg=1 last fixed wt=800.00> BB132 regmask=[x11] minReg=1 wt=800.00> BB132 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB132 regmask=[x14] minReg=1 last wt=3200.00> BB132 regmask=[x0] minReg=1 last wt=800.00> BB132 regmask=[x1] minReg=1 last wt=800.00> BB132 regmask=[x2] minReg=1 last wt=800.00> BB132 regmask=[x3] minReg=1 last wt=800.00> BB132 regmask=[x4] minReg=1 last wt=800.00> BB132 regmask=[x5] minReg=1 last wt=800.00> BB132 regmask=[x6] minReg=1 last wt=800.00> BB132 regmask=[x7] minReg=1 last wt=800.00> BB132 regmask=[x8] minReg=1 last wt=800.00> BB132 regmask=[x9] minReg=1 last wt=800.00> BB132 regmask=[x10] minReg=1 last wt=800.00> BB132 regmask=[x11] minReg=1 last wt=800.00> BB132 regmask=[x12] minReg=1 last wt=800.00> BB132 regmask=[x13] minReg=1 last wt=800.00> BB132 regmask=[x14] minReg=1 last wt=800.00> BB132 regmask=[x15] minReg=1 last wt=800.00> BB132 regmask=[xip0] minReg=1 last wt=800.00> BB132 regmask=[xip1] minReg=1 last wt=800.00> BB132 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB133 regmask=[x9] minReg=1 last wt=7000.00> ADD BB133 regmask=[x9] minReg=1 wt=3200.00> BB133 regmask=[x9] minReg=1 last wt=800.00> STORE_LCL_VAR BB133 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB134 regmask=[x2] minReg=1 last wt=4650.00> ADD BB134 regmask=[x2] minReg=1 wt=3200.00> BB134 regmask=[x2] minReg=1 last wt=800.00> STORE_LCL_VAR BB134 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB134 regmask=[x3] minReg=1 last wt=4100.00> ADD BB134 regmask=[x3] minReg=1 wt=3200.00> BB134 regmask=[x3] minReg=1 last wt=800.00> STORE_LCL_VAR BB134 regmask=[x3] minReg=1 spillAfter wt=4100.00> LCL_VAR BB136 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB137 regmask=[x13] minReg=1 wt=23700.00> ADD BB137 regmask=[x14] minReg=1 wt=800.00> BB137 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB137 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB137 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x13] minReg=1 wt=23700.00> ADD BB138 regmask=[x12] minReg=1 wt=800.00> BB138 regmask=[x12] minReg=1 last wt=200.00> STORE_LCL_VAR BB138 regmask=[x12] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x12] minReg=1 wt=1200.00> LCL_VAR BB139 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB141 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB142 regmask=[x13] minReg=1 wt=23700.00> CNS_INT BB143 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB143 regmask=[x13] minReg=1 wt=23700.00> BB143 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB144 regmask=[x20] minReg=1 wt=2250.00> IND BB144 regmask=[x11] minReg=1 wt=800.00> BB144 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB144 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB181 regmask=[x11] minReg=1 wt=2400.00> BB182 regmask=[x11] minReg=1 regOptional wt=200.00> LCL_VAR BB182 regmask=[x19] minReg=1 wt=26550.00> IND BB182 regmask=[x13] minReg=1 wt=800.00> BB182 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB182 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB182 regmask=[x11] minReg=1 outOfOrder wt=2400.00> IND BB182 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB182 regmask=[x19] minReg=1 wt=26550.00> IND BB182 regmask=[x12] minReg=1 wt=800.00> BB182 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB182 regmask=[x13] minReg=1 wt=1000.00> BB182 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x19] minReg=1 wt=26550.00> ADD BB183 regmask=[x14] minReg=1 wt=800.00> BB183 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB183 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x14] minReg=1 wt=1200.00> IND BB183 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x13] minReg=1 wt=1000.00> BB183 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x14] minReg=1 last wt=1200.00> IND BB183 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x13] minReg=1 wt=1000.00> BFIZ BB183 regmask=[x12] minReg=1 wt=800.00> BB183 regmask=[x14] minReg=1 last wt=200.00> BB183 regmask=[x12] minReg=1 last wt=200.00> ADD BB183 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x11] minReg=1 wt=2400.00> IND BB183 regmask=[x12] minReg=1 wt=800.00> BB183 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x11] minReg=1 last wt=2400.00> IND BB183 regmask=[x11] minReg=1 wt=800.00> BB183 regmask=[x14] minReg=1 last wt=200.00> BB183 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB183 regmask=[x13] minReg=1 last wt=1000.00> ADD BB183 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB183 regmask=[x19] minReg=1 wt=26550.00> BB183 regmask=[x11] minReg=1 last wt=200.00> BB185 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB185 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB185 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x0] minReg=1 fixed wt=800.00> BB185 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB185 regmask=[x1] minReg=1 last copy fixed wt=2400.00> BB185 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB185 regmask=[x11] minReg=1 wt=800.00> BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 last fixed wt=200.00> BB185 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB185 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB185 regmask=[x13] minReg=1 wt=800.00> BB185 regmask=[x0] minReg=1 wt=200.00> BB185 regmask=[x0] minReg=1 last fixed wt=200.00> BB185 regmask=[x1] minReg=1 wt=200.00> BB185 regmask=[x1] minReg=1 last fixed wt=200.00> BB185 regmask=[x11] minReg=1 wt=200.00> BB185 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB185 regmask=[x13] minReg=1 last wt=800.00> BB185 regmask=[x0] minReg=1 last wt=200.00> BB185 regmask=[x1] minReg=1 last wt=200.00> BB185 regmask=[x2] minReg=1 last wt=200.00> BB185 regmask=[x3] minReg=1 last wt=200.00> BB185 regmask=[x4] minReg=1 last wt=200.00> BB185 regmask=[x5] minReg=1 last wt=200.00> BB185 regmask=[x6] minReg=1 last wt=200.00> BB185 regmask=[x7] minReg=1 last wt=200.00> BB185 regmask=[x8] minReg=1 last wt=200.00> BB185 regmask=[x9] minReg=1 last wt=200.00> BB185 regmask=[x10] minReg=1 last wt=200.00> BB185 regmask=[x11] minReg=1 last wt=200.00> BB185 regmask=[x12] minReg=1 last wt=200.00> BB185 regmask=[x13] minReg=1 last wt=200.00> BB185 regmask=[x14] minReg=1 last wt=200.00> BB185 regmask=[x15] minReg=1 last wt=200.00> BB185 regmask=[xip0] minReg=1 last wt=200.00> BB185 regmask=[xip1] minReg=1 last wt=200.00> BB185 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB200 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB200 regmask=[x4] minReg=1 wt=91300.00> IND BB200 regmask=[x13] minReg=1 wt=800.00> BB200 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB200 regmask=[x13] minReg=1 wt=1600.00> LCL_VAR BB200 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB200 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB200 regmask=[x13] minReg=1 wt=1600.00> BB201 regmask=[x13] minReg=1 regOptional wt=200.00> LCL_VAR BB201 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB201 regmask=[x4] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x4] minReg=1 last wt=800.00> ADD BB201 regmask=[x4] minReg=1 wt=800.00> BB201 regmask=[x4] minReg=1 last wt=200.00> STORE_LCL_VAR BB201 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB201 regmask=[x13] minReg=1 last outOfOrder wt=1600.00> STORE_LCL_VAR BB201 regmask=[x13] minReg=1 wt=1200.00> LCL_VAR BB201 regmask=[x19] minReg=1 wt=26550.00> IND BB201 regmask=[x11] minReg=1 wt=800.00> BB201 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB201 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB201 regmask=[x19] minReg=1 wt=26550.00> IND BB201 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x11] minReg=1 wt=1000.00> BB201 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x19] minReg=1 wt=26550.00> ADD BB203 regmask=[x14] minReg=1 wt=800.00> BB203 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB203 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x14] minReg=1 wt=1200.00> IND BB203 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB203 regmask=[x11] minReg=1 wt=1000.00> BB203 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x14] minReg=1 last wt=1200.00> IND BB203 regmask=[x14] minReg=1 wt=800.00> BB203 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB203 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x13] minReg=1 last wt=1200.00> LCL_VAR BB203 regmask=[x11] minReg=1 last wt=1000.00> ADD BB203 regmask=[x13] minReg=1 wt=800.00> LCL_VAR BB203 regmask=[x19] minReg=1 wt=26550.00> BB203 regmask=[x13] minReg=1 last wt=200.00> BB204 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB204 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB204 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x0] minReg=1 fixed wt=800.00> BB204 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB204 regmask=[x1] minReg=1 last copy fixed wt=1200.00> BB204 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB204 regmask=[x11] minReg=1 wt=800.00> BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 last fixed wt=200.00> BB204 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB204 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB204 regmask=[x13] minReg=1 wt=800.00> BB204 regmask=[x0] minReg=1 wt=200.00> BB204 regmask=[x0] minReg=1 last fixed wt=200.00> BB204 regmask=[x1] minReg=1 wt=200.00> BB204 regmask=[x1] minReg=1 last fixed wt=200.00> BB204 regmask=[x11] minReg=1 wt=200.00> BB204 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB204 regmask=[x13] minReg=1 last wt=800.00> BB204 regmask=[x0] minReg=1 last wt=200.00> BB204 regmask=[x1] minReg=1 last wt=200.00> BB204 regmask=[x2] minReg=1 last wt=200.00> BB204 regmask=[x3] minReg=1 last wt=200.00> BB204 regmask=[x4] minReg=1 last wt=200.00> BB204 regmask=[x5] minReg=1 last wt=200.00> BB204 regmask=[x6] minReg=1 last wt=200.00> BB204 regmask=[x7] minReg=1 last wt=200.00> BB204 regmask=[x8] minReg=1 last wt=200.00> BB204 regmask=[x9] minReg=1 last wt=200.00> BB204 regmask=[x10] minReg=1 last wt=200.00> BB204 regmask=[x11] minReg=1 last wt=200.00> BB204 regmask=[x12] minReg=1 last wt=200.00> BB204 regmask=[x13] minReg=1 last wt=200.00> BB204 regmask=[x14] minReg=1 last wt=200.00> BB204 regmask=[x15] minReg=1 last wt=200.00> BB204 regmask=[xip0] minReg=1 last wt=200.00> BB204 regmask=[xip1] minReg=1 last wt=200.00> BB204 regmask=[lr] minReg=1 last wt=200.00> STORE_LCL_VAR BB205 regmask=[x11] minReg=1 wt=600.00> STORE_LCL_VAR BB205 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB205 regmask=[x5] minReg=1 wt=2400.00> LCL_VAR BB206 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB206 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB207 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB207 regmask=[x4] minReg=1 wt=91300.00> IND BB207 regmask=[x12] minReg=1 wt=800.00> BB207 regmask=[x12] minReg=1 last wt=200.00> STORE_LCL_VAR BB207 regmask=[x12] minReg=1 wt=1600.00> LCL_VAR BB207 regmask=[x12] minReg=1 last wt=1600.00> LCL_VAR BB208 regmask=[x4] minReg=1 wt=91300.00> ADD BB208 regmask=[x12] minReg=1 wt=800.00> BB208 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB208 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB209 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x4] minReg=1 wt=91300.00> IND BB209 regmask=[x12] minReg=1 wt=800.00> BB209 regmask=[x12] minReg=1 last wt=200.00> STORE_LCL_VAR BB209 regmask=[x12] minReg=1 wt=1600.00> LCL_VAR BB209 regmask=[x12] minReg=1 wt=1600.00> NE BB209 regmask=[x15] minReg=1 wt=800.00> LCL_VAR BB209 regmask=[x4] minReg=1 wt=91300.00> ADD BB209 regmask=[xip0] minReg=1 wt=800.00> LCL_VAR BB209 regmask=[x24] minReg=1 wt=6700.00> BB209 regmask=[xip0] minReg=1 last wt=200.00> IND BB209 regmask=[xip0] minReg=1 wt=800.00> BB209 regmask=[xip0] minReg=1 last wt=200.00> NE BB209 regmask=[xip0] minReg=1 wt=800.00> BB209 regmask=[x15] minReg=1 last wt=200.00> BB209 regmask=[xip0] minReg=1 last wt=200.00> AND BB209 regmask=[x15] minReg=1 wt=800.00> BB209 regmask=[x15] minReg=1 last wt=200.00> CNS_INT BB210 regmask=[x11] minReg=1 wt=800.00> BB210 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB210 regmask=[x11] minReg=1 wt=600.00> LCL_VAR BB213 regmask=[x12] minReg=1 last wt=1600.00> LCL_VAR BB214 regmask=[x4] minReg=1 wt=91300.00> ADD BB214 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB214 regmask=[x24] minReg=1 wt=6700.00> BB214 regmask=[x12] minReg=1 last wt=200.00> IND BB214 regmask=[x12] minReg=1 wt=800.00> BB214 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB215 regmask=[x19] minReg=1 wt=26550.00> IND BB215 regmask=[x14] minReg=1 wt=800.00> BB215 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB215 regmask=[x14] minReg=1 wt=1000.00> LCL_VAR BB215 regmask=[x19] minReg=1 wt=26550.00> IND BB215 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB215 regmask=[x14] minReg=1 wt=1000.00> BB215 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x19] minReg=1 wt=26550.00> ADD BB216 regmask=[x11] minReg=1 wt=800.00> BB216 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB216 regmask=[x11] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x11] minReg=1 wt=1200.00> IND BB216 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB216 regmask=[x14] minReg=1 wt=1000.00> BB216 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x11] minReg=1 last wt=1200.00> IND BB216 regmask=[x11] minReg=1 wt=800.00> BB216 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB216 regmask=[x14] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB216 regmask=[x14] minReg=1 last wt=1000.00> ADD BB216 regmask=[x13] minReg=1 wt=800.00> LCL_VAR BB216 regmask=[x19] minReg=1 wt=26550.00> BB216 regmask=[x13] minReg=1 last wt=200.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB218 regmask=[x14] minReg=1 last wt=2400.00> ADD BB218 regmask=[x14] minReg=1 wt=3200.00> BB218 regmask=[x14] minReg=1 last wt=800.00> STORE_LCL_VAR BB218 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB219 regmask=[x4] minReg=1 last wt=91300.00> ADD BB219 regmask=[x4] minReg=1 wt=6400.00> BB219 regmask=[x4] minReg=1 last wt=1600.00> STORE_LCL_VAR BB219 regmask=[x4] minReg=1 wt=6400.00> LCL_VAR BB219 regmask=[x4] minReg=1 last wt=6400.00> STORE_LCL_VAR BB219 regmask=[x12] minReg=1 wt=91300.00> LCL_VAR BB219 regmask=[x12] minReg=1 wt=91300.00> LCL_VAR BB219 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB220 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB220 regmask=[x12] minReg=1 spillAfter wt=91300.00> IND BB220 regmask=[x5] minReg=1 wt=6400.00> BB220 regmask=[x5] minReg=1 last wt=1600.00> LCL_VAR BB221 regmask=[x14] minReg=1 wt=2400.00> CNS_INT BB222 regmask=[x14] minReg=1 wt=800.00> BB222 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB222 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB223 regmask=[x23] minReg=1 wt=1700.00> IND BB223 regmask=[x5] minReg=1 wt=800.00> BB223 regmask=[x5] minReg=1 last wt=200.00> LCL_VAR BB224 regmask=[x21] minReg=1 wt=2150.00> IND BB224 regmask=[x5] minReg=1 wt=800.00> BB224 regmask=[x5] minReg=1 last wt=200.00> LCL_VAR BB224 regmask=[x28] minReg=1 wt=5600.00> SUB BB224 regmask=[x4] minReg=1 wt=800.00> BB224 regmask=[x4] minReg=1 last wt=200.00> STORE_LCL_VAR BB224 regmask=[x4] minReg=1 wt=600.00> STORE_LCL_VAR BB225 regmask=[x4] minReg=1 wt=600.00> BB226 regmask=[x5] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x5] minReg=1 last copy fixed wt=600.00> BB226 regmask=[x5] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x5] minReg=1 fixed wt=800.00> BB226 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB226 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x0] minReg=1 fixed wt=800.00> BB226 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x1] minReg=1 copy fixed wt=2250.00> BB226 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x1] minReg=1 fixed wt=800.00> BB226 regmask=[x2] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x2] minReg=1 last copy fixed wt=600.00> BB226 regmask=[x2] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x2] minReg=1 fixed wt=800.00> BB226 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x3] minReg=1 last copy fixed wt=23700.00> BB226 regmask=[x3] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x3] minReg=1 fixed wt=800.00> BB226 regmask=[x4] minReg=1 wt=200.00> LCL_VAR BB226 regmask=[x4] minReg=1 last copy fixed wt=2400.00> BB226 regmask=[x4] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x4] minReg=1 fixed wt=800.00> CNS_INT BB226 regmask=[x11] minReg=1 wt=800.00> BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 last fixed wt=200.00> BB226 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB226 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB226 regmask=[x13] minReg=1 wt=800.00> BB226 regmask=[x5] minReg=1 wt=200.00> BB226 regmask=[x5] minReg=1 last fixed wt=200.00> BB226 regmask=[x0] minReg=1 wt=200.00> BB226 regmask=[x0] minReg=1 last fixed wt=200.00> BB226 regmask=[x1] minReg=1 wt=200.00> BB226 regmask=[x1] minReg=1 last fixed wt=200.00> BB226 regmask=[x2] minReg=1 wt=200.00> BB226 regmask=[x2] minReg=1 last fixed wt=200.00> BB226 regmask=[x3] minReg=1 wt=200.00> BB226 regmask=[x3] minReg=1 last fixed wt=200.00> BB226 regmask=[x4] minReg=1 wt=200.00> BB226 regmask=[x4] minReg=1 last fixed wt=200.00> BB226 regmask=[x11] minReg=1 wt=200.00> BB226 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB226 regmask=[x13] minReg=1 last wt=800.00> BB226 regmask=[x0] minReg=1 last wt=200.00> BB226 regmask=[x1] minReg=1 last wt=200.00> BB226 regmask=[x2] minReg=1 last wt=200.00> BB226 regmask=[x3] minReg=1 last wt=200.00> BB226 regmask=[x4] minReg=1 last wt=200.00> BB226 regmask=[x5] minReg=1 last wt=200.00> BB226 regmask=[x6] minReg=1 last wt=200.00> BB226 regmask=[x7] minReg=1 last wt=200.00> BB226 regmask=[x8] minReg=1 last wt=200.00> BB226 regmask=[x9] minReg=1 last wt=200.00> BB226 regmask=[x10] minReg=1 last wt=200.00> BB226 regmask=[x11] minReg=1 last wt=200.00> BB226 regmask=[x12] minReg=1 last wt=200.00> BB226 regmask=[x13] minReg=1 last wt=200.00> BB226 regmask=[x14] minReg=1 last wt=200.00> BB226 regmask=[x15] minReg=1 last wt=200.00> BB226 regmask=[xip0] minReg=1 last wt=200.00> BB226 regmask=[xip1] minReg=1 last wt=200.00> BB226 regmask=[lr] minReg=1 last wt=200.00> STORE_LCL_VAR BB226 regmask=[x2] minReg=1 spillAfter wt=2400.00> LCL_VAR BB227 regmask=[x19] minReg=1 wt=26550.00> IND BB227 regmask=[x11] minReg=1 wt=800.00> BB227 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB227 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB227 regmask=[x19] minReg=1 wt=26550.00> IND BB227 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB227 regmask=[x11] minReg=1 wt=1000.00> BB227 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x19] minReg=1 wt=26550.00> ADD BB228 regmask=[x14] minReg=1 wt=800.00> BB228 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB228 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x14] minReg=1 wt=1200.00> IND BB228 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB228 regmask=[x11] minReg=1 wt=1000.00> BB228 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x14] minReg=1 last wt=1200.00> IND BB228 regmask=[x14] minReg=1 wt=800.00> BB228 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB228 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB228 regmask=[x11] minReg=1 last wt=1000.00> ADD BB228 regmask=[x13] minReg=1 wt=800.00> LCL_VAR BB228 regmask=[x19] minReg=1 wt=26550.00> BB228 regmask=[x13] minReg=1 last wt=200.00> BB229 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB229 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB229 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x0] minReg=1 fixed wt=800.00> BB229 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB229 regmask=[x1] minReg=1 last copy fixed wt=23700.00> BB229 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB229 regmask=[x11] minReg=1 wt=800.00> BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 last fixed wt=200.00> BB229 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB229 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB229 regmask=[x13] minReg=1 wt=800.00> BB229 regmask=[x0] minReg=1 wt=200.00> BB229 regmask=[x0] minReg=1 last fixed wt=200.00> BB229 regmask=[x1] minReg=1 wt=200.00> BB229 regmask=[x1] minReg=1 last fixed wt=200.00> BB229 regmask=[x11] minReg=1 wt=200.00> BB229 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB229 regmask=[x13] minReg=1 last wt=800.00> BB229 regmask=[x0] minReg=1 last wt=200.00> BB229 regmask=[x1] minReg=1 last wt=200.00> BB229 regmask=[x2] minReg=1 last wt=200.00> BB229 regmask=[x3] minReg=1 last wt=200.00> BB229 regmask=[x4] minReg=1 last wt=200.00> BB229 regmask=[x5] minReg=1 last wt=200.00> BB229 regmask=[x6] minReg=1 last wt=200.00> BB229 regmask=[x7] minReg=1 last wt=200.00> BB229 regmask=[x8] minReg=1 last wt=200.00> BB229 regmask=[x9] minReg=1 last wt=200.00> BB229 regmask=[x10] minReg=1 last wt=200.00> BB229 regmask=[x11] minReg=1 last wt=200.00> BB229 regmask=[x12] minReg=1 last wt=200.00> BB229 regmask=[x13] minReg=1 last wt=200.00> BB229 regmask=[x14] minReg=1 last wt=200.00> BB229 regmask=[x15] minReg=1 last wt=200.00> BB229 regmask=[xip0] minReg=1 last wt=200.00> BB229 regmask=[xip1] minReg=1 last wt=200.00> BB229 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB230 regmask=[x4] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB230 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB231 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB231 regmask=[x4] minReg=1 wt=91300.00> IND BB231 regmask=[x11] minReg=1 wt=800.00> BB231 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB231 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB231 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB232 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB233 regmask=[x4] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x4] minReg=1 last wt=800.00> ADD BB233 regmask=[x4] minReg=1 wt=800.00> BB233 regmask=[x4] minReg=1 last wt=200.00> STORE_LCL_VAR BB233 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB233 regmask=[x11] minReg=1 last wt=800.00> STORE_LCL_VAR BB233 regmask=[x11] minReg=1 wt=1200.00> LCL_VAR BB233 regmask=[x19] minReg=1 wt=26550.00> IND BB233 regmask=[x13] minReg=1 wt=800.00> BB233 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB233 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB233 regmask=[x19] minReg=1 wt=26550.00> IND BB233 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x13] minReg=1 wt=1000.00> BB233 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x19] minReg=1 wt=26550.00> ADD BB234 regmask=[x14] minReg=1 wt=800.00> BB234 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB234 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x14] minReg=1 wt=1200.00> IND BB234 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB234 regmask=[x13] minReg=1 wt=1000.00> BB234 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x14] minReg=1 last wt=1200.00> IND BB234 regmask=[x14] minReg=1 wt=800.00> BB234 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB234 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x11] minReg=1 last wt=1200.00> LCL_VAR BB234 regmask=[x13] minReg=1 last wt=1000.00> ADD BB234 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB234 regmask=[x19] minReg=1 wt=26550.00> BB234 regmask=[x11] minReg=1 last wt=200.00> BB235 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB235 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB235 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x0] minReg=1 fixed wt=800.00> BB235 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB235 regmask=[x1] minReg=1 last copy fixed wt=1200.00> BB235 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB235 regmask=[x11] minReg=1 wt=800.00> BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 last fixed wt=200.00> BB235 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB235 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB235 regmask=[x13] minReg=1 wt=800.00> BB235 regmask=[x0] minReg=1 wt=200.00> BB235 regmask=[x0] minReg=1 last fixed wt=200.00> BB235 regmask=[x1] minReg=1 wt=200.00> BB235 regmask=[x1] minReg=1 last fixed wt=200.00> BB235 regmask=[x11] minReg=1 wt=200.00> BB235 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB235 regmask=[x13] minReg=1 last wt=800.00> BB235 regmask=[x0] minReg=1 last wt=200.00> BB235 regmask=[x1] minReg=1 last wt=200.00> BB235 regmask=[x2] minReg=1 last wt=200.00> BB235 regmask=[x3] minReg=1 last wt=200.00> BB235 regmask=[x4] minReg=1 last wt=200.00> BB235 regmask=[x5] minReg=1 last wt=200.00> BB235 regmask=[x6] minReg=1 last wt=200.00> BB235 regmask=[x7] minReg=1 last wt=200.00> BB235 regmask=[x8] minReg=1 last wt=200.00> BB235 regmask=[x9] minReg=1 last wt=200.00> BB235 regmask=[x10] minReg=1 last wt=200.00> BB235 regmask=[x11] minReg=1 last wt=200.00> BB235 regmask=[x12] minReg=1 last wt=200.00> BB235 regmask=[x13] minReg=1 last wt=200.00> BB235 regmask=[x14] minReg=1 last wt=200.00> BB235 regmask=[x15] minReg=1 last wt=200.00> BB235 regmask=[xip0] minReg=1 last wt=200.00> BB235 regmask=[xip1] minReg=1 last wt=200.00> BB235 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB239 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB239 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB240 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB240 regmask=[x4] minReg=1 wt=91300.00> IND BB240 regmask=[x11] minReg=1 wt=6400.00> BB240 regmask=[x11] minReg=1 last wt=1600.00> STORE_LCL_VAR BB240 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB240 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB236 regmask=[x4] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x4] minReg=1 last wt=3200.00> ADD BB236 regmask=[x4] minReg=1 wt=3200.00> BB236 regmask=[x4] minReg=1 last wt=800.00> STORE_LCL_VAR BB236 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB236 regmask=[x11] minReg=1 last wt=4000.00> STORE_LCL_VAR BB236 regmask=[x11] minReg=1 wt=4800.00> LCL_VAR BB236 regmask=[x19] minReg=1 wt=26550.00> IND BB236 regmask=[x13] minReg=1 wt=3200.00> BB236 regmask=[x13] minReg=1 last wt=800.00> STORE_LCL_VAR BB236 regmask=[x13] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x19] minReg=1 wt=26550.00> IND BB236 regmask=[x14] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x13] minReg=1 wt=4000.00> BB236 regmask=[x14] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x19] minReg=1 wt=26550.00> ADD BB237 regmask=[x14] minReg=1 wt=3200.00> BB237 regmask=[x14] minReg=1 last wt=800.00> STORE_LCL_VAR BB237 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x14] minReg=1 wt=4800.00> IND BB237 regmask=[x12] minReg=1 wt=3200.00> LCL_VAR BB237 regmask=[x13] minReg=1 wt=4000.00> BB237 regmask=[x12] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x14] minReg=1 last wt=4800.00> IND BB237 regmask=[x14] minReg=1 wt=3200.00> BB237 regmask=[x14] minReg=1 last wt=800.00> LCL_VAR BB237 regmask=[x13] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x11] minReg=1 last wt=4800.00> LCL_VAR BB237 regmask=[x13] minReg=1 last wt=4000.00> ADD BB237 regmask=[x11] minReg=1 wt=3200.00> LCL_VAR BB237 regmask=[x19] minReg=1 wt=26550.00> BB237 regmask=[x11] minReg=1 last wt=800.00> BB238 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB238 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB238 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x0] minReg=1 fixed wt=3200.00> BB238 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB238 regmask=[x1] minReg=1 last copy fixed wt=4800.00> BB238 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB238 regmask=[x11] minReg=1 wt=3200.00> BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 last fixed wt=800.00> BB238 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB238 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB238 regmask=[x13] minReg=1 wt=3200.00> BB238 regmask=[x0] minReg=1 wt=800.00> BB238 regmask=[x0] minReg=1 last fixed wt=800.00> BB238 regmask=[x1] minReg=1 wt=800.00> BB238 regmask=[x1] minReg=1 last fixed wt=800.00> BB238 regmask=[x11] minReg=1 wt=800.00> BB238 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB238 regmask=[x13] minReg=1 last wt=3200.00> BB238 regmask=[x0] minReg=1 last wt=800.00> BB238 regmask=[x1] minReg=1 last wt=800.00> BB238 regmask=[x2] minReg=1 last wt=800.00> BB238 regmask=[x3] minReg=1 last wt=800.00> BB238 regmask=[x4] minReg=1 last wt=800.00> BB238 regmask=[x5] minReg=1 last wt=800.00> BB238 regmask=[x6] minReg=1 last wt=800.00> BB238 regmask=[x7] minReg=1 last wt=800.00> BB238 regmask=[x8] minReg=1 last wt=800.00> BB238 regmask=[x9] minReg=1 last wt=800.00> BB238 regmask=[x10] minReg=1 last wt=800.00> BB238 regmask=[x11] minReg=1 last wt=800.00> BB238 regmask=[x12] minReg=1 last wt=800.00> BB238 regmask=[x13] minReg=1 last wt=800.00> BB238 regmask=[x14] minReg=1 last wt=800.00> BB238 regmask=[x15] minReg=1 last wt=800.00> BB238 regmask=[xip0] minReg=1 last wt=800.00> BB238 regmask=[xip1] minReg=1 last wt=800.00> BB238 regmask=[lr] minReg=1 last wt=800.00> LCL_VAR BB242 regmask=[x19] minReg=1 wt=26550.00> IND BB242 regmask=[x11] minReg=1 wt=800.00> BB242 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB242 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB242 regmask=[x19] minReg=1 wt=26550.00> IND BB242 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB242 regmask=[x11] minReg=1 wt=1000.00> BB242 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x19] minReg=1 wt=26550.00> ADD BB243 regmask=[x14] minReg=1 wt=800.00> BB243 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB243 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x14] minReg=1 wt=1200.00> IND BB243 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB243 regmask=[x11] minReg=1 wt=1000.00> BB243 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x14] minReg=1 last wt=1200.00> IND BB243 regmask=[x14] minReg=1 wt=800.00> BB243 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB243 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB243 regmask=[x11] minReg=1 last wt=1000.00> ADD BB243 regmask=[x13] minReg=1 wt=800.00> LCL_VAR BB243 regmask=[x19] minReg=1 wt=26550.00> BB243 regmask=[x13] minReg=1 last wt=200.00> BB244 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB244 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB244 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x0] minReg=1 fixed wt=800.00> BB244 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB244 regmask=[x1] minReg=1 last copy fixed wt=23700.00> BB244 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB244 regmask=[x11] minReg=1 wt=800.00> BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 last fixed wt=200.00> BB244 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB244 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB244 regmask=[x13] minReg=1 wt=800.00> BB244 regmask=[x0] minReg=1 wt=200.00> BB244 regmask=[x0] minReg=1 last fixed wt=200.00> BB244 regmask=[x1] minReg=1 wt=200.00> BB244 regmask=[x1] minReg=1 last fixed wt=200.00> BB244 regmask=[x11] minReg=1 wt=200.00> BB244 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB244 regmask=[x13] minReg=1 last wt=800.00> BB244 regmask=[x0] minReg=1 last wt=200.00> BB244 regmask=[x1] minReg=1 last wt=200.00> BB244 regmask=[x2] minReg=1 last wt=200.00> BB244 regmask=[x3] minReg=1 last wt=200.00> BB244 regmask=[x4] minReg=1 last wt=200.00> BB244 regmask=[x5] minReg=1 last wt=200.00> BB244 regmask=[x6] minReg=1 last wt=200.00> BB244 regmask=[x7] minReg=1 last wt=200.00> BB244 regmask=[x8] minReg=1 last wt=200.00> BB244 regmask=[x9] minReg=1 last wt=200.00> BB244 regmask=[x10] minReg=1 last wt=200.00> BB244 regmask=[x11] minReg=1 last wt=200.00> BB244 regmask=[x12] minReg=1 last wt=200.00> BB244 regmask=[x13] minReg=1 last wt=200.00> BB244 regmask=[x14] minReg=1 last wt=200.00> BB244 regmask=[x15] minReg=1 last wt=200.00> BB244 regmask=[xip0] minReg=1 last wt=200.00> BB244 regmask=[xip1] minReg=1 last wt=200.00> BB244 regmask=[lr] minReg=1 last wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[] minReg=1 regOptional wt=200.00> BB244 regmask=[] minReg=1 outOfOrder regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[] minReg=1 regOptional wt=200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB244 regmask=[] minReg=1 regOptional wt=200.00> LCL_VAR BB248 regmask=[x21] minReg=1 wt=2150.00> IND BB248 regmask=[x2] minReg=1 wt=400.00> BB248 regmask=[x2] minReg=1 last wt=100.00> LCL_VAR BB248 regmask=[x26] minReg=1 last wt=1900.00> LCL_VAR BB249 regmask=[x21] minReg=1 last wt=2150.00> IND BB249 regmask=[x2] minReg=1 wt=200.00> BB249 regmask=[x2] minReg=1 last wt=50.00> NE BB249 regmask=[x2] minReg=1 wt=200.00> LCL_VAR BB249 regmask=[x19] minReg=1 wt=26550.00> IND BB249 regmask=[x0] minReg=1 wt=200.00> BB249 regmask=[x0] minReg=1 last wt=50.00> LE BB249 regmask=[x0] minReg=1 wt=200.00> BB249 regmask=[x2] minReg=1 last wt=50.00> BB249 regmask=[x0] minReg=1 last wt=50.00> AND BB249 regmask=[x2] minReg=1 wt=200.00> BB249 regmask=[x2] minReg=1 last wt=50.00> LCL_VAR BB251 regmask=[x20] minReg=1 last wt=2250.00> IND BB251 regmask=[x2] minReg=1 wt=200.00> BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 last fixed wt=50.00> BB251 regmask=[x2] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x2] minReg=1 fixed wt=200.00> BB251 regmask=[x0] minReg=1 wt=50.00> LCL_VAR BB251 regmask=[x0] minReg=1 last copy fixed wt=26550.00> BB251 regmask=[x0] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x0] minReg=1 fixed wt=200.00> CNS_INT BB251 regmask=[x11] minReg=1 wt=200.00> BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 last fixed wt=50.00> BB251 regmask=[x11] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x11] minReg=1 fixed wt=200.00> CNS_INT BB251 regmask=[x1] minReg=1 wt=200.00> BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 last fixed wt=50.00> BB251 regmask=[x1] minReg=1 wt=50.00> PUTARG_REG BB251 regmask=[x1] minReg=1 fixed wt=200.00> CALL BB251 regmask=[x3] minReg=1 wt=200.00> BB251 regmask=[x2] minReg=1 wt=50.00> BB251 regmask=[x2] minReg=1 last fixed wt=50.00> BB251 regmask=[x0] minReg=1 wt=50.00> BB251 regmask=[x0] minReg=1 last fixed wt=50.00> BB251 regmask=[x11] minReg=1 wt=50.00> BB251 regmask=[x11] minReg=1 last fixed wt=50.00> BB251 regmask=[x1] minReg=1 wt=50.00> BB251 regmask=[x1] minReg=1 last fixed wt=50.00> CALL BB251 regmask=[x3] minReg=1 last wt=200.00> BB251 regmask=[x0] minReg=1 last wt=50.00> BB251 regmask=[x1] minReg=1 last wt=50.00> BB251 regmask=[x2] minReg=1 last wt=50.00> BB251 regmask=[x3] minReg=1 last wt=50.00> BB251 regmask=[x4] minReg=1 last wt=50.00> BB251 regmask=[x5] minReg=1 last wt=50.00> BB251 regmask=[x6] minReg=1 last wt=50.00> BB251 regmask=[x7] minReg=1 last wt=50.00> BB251 regmask=[x8] minReg=1 last wt=50.00> BB251 regmask=[x9] minReg=1 last wt=50.00> BB251 regmask=[x10] minReg=1 last wt=50.00> BB251 regmask=[x11] minReg=1 last wt=50.00> BB251 regmask=[x12] minReg=1 last wt=50.00> BB251 regmask=[x13] minReg=1 last wt=50.00> BB251 regmask=[x14] minReg=1 last wt=50.00> BB251 regmask=[x15] minReg=1 last wt=50.00> BB251 regmask=[xip0] minReg=1 last wt=50.00> BB251 regmask=[xip1] minReg=1 last wt=50.00> BB251 regmask=[lr] minReg=1 last wt=50.00> LCL_VAR BB255 regmask=[x14] minReg=1 last regOptional wt=4800.00> CAST BB255 regmask=[x0] minReg=1 wt=3200.00> JMPTABLE BB255 regmask=[x1] minReg=1 wt=3200.00> SWITCH_TABLE BB255 regmask=[x11] minReg=1 wt=3200.00> BB255 regmask=[x0] minReg=1 last wt=800.00> BB255 regmask=[x1] minReg=1 last wt=800.00> LCL_VAR BB17 regmask=[x27] minReg=1 last outOfOrder wt=9600.00> ADD BB17 regmask=[x27] minReg=1 wt=3200.00> BB17 regmask=[x27] minReg=1 last wt=800.00> STORE_LCL_VAR BB17 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB30 regmask=[x8] minReg=1 last wt=4800.00> ADD BB30 regmask=[x8] minReg=1 wt=3200.00> BB30 regmask=[x8] minReg=1 last wt=800.00> STORE_LCL_VAR BB30 regmask=[x8] minReg=1 wt=4800.00> LCL_VAR BB31 regmask=[x9] minReg=1 outOfOrder wt=18400.00> LCL_VAR BB31 regmask=[x10] minReg=1 outOfOrder wt=91300.00> IND BB31 regmask=[x0] minReg=1 wt=25600.00> BB31 regmask=[x0] minReg=1 last wt=6400.00> STORE_LCL_VAR BB31 regmask=[x0] minReg=1 wt=19200.00> LCL_VAR BB31 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB31 regmask=[x25] minReg=1 outOfOrder wt=28400.00> LCL_VAR BB31 regmask=[x0] minReg=1 wt=19200.00> BB32 regmask=[x13] minReg=1 regOptional wt=6400.00> BB32 regmask=[x0] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x1] minReg=1 last outOfOrder wt=91300.00> STORE_LCL_VAR BB32 regmask=[x1] minReg=1 wt=25600.00> LCL_VAR BB32 regmask=[x1] minReg=1 last wt=25600.00> ADD BB32 regmask=[x1] minReg=1 wt=25600.00> BB32 regmask=[x1] minReg=1 last wt=6400.00> STORE_LCL_VAR BB32 regmask=[x2] minReg=1 spillAfter wt=91300.00> LCL_VAR BB32 regmask=[x0] minReg=1 last wt=19200.00> LCL_VAR BB32 regmask=[x13] minReg=1 outOfOrder wt=23700.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> LCL_VAR BB256 regmask=[x12] minReg=1 last regOptional wt=4800.00> CAST BB256 regmask=[x13] minReg=1 wt=3200.00> JMPTABLE BB256 regmask=[x0] minReg=1 wt=3200.00> SWITCH_TABLE BB256 regmask=[x1] minReg=1 wt=3200.00> BB256 regmask=[x13] minReg=1 last wt=800.00> BB256 regmask=[x0] minReg=1 last wt=800.00> CNS_INT BB18 regmask=[x4] minReg=1 wt=3200.00> LCL_VAR BB18 regmask=[x3] minReg=1 outOfOrder wt=2900.00> BB18 regmask=[x4] minReg=1 last wt=800.00> LCL_VAR BB19 regmask=[x27] minReg=1 wt=9600.00> STORE_LCL_VAR BB19 regmask=[x3] minReg=1 wt=2900.00> LCL_VAR BB20 regmask=[x27] minReg=1 last wt=9600.00> ADD BB20 regmask=[x27] minReg=1 wt=3200.00> BB20 regmask=[x27] minReg=1 last wt=800.00> STORE_LCL_VAR BB20 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x27] minReg=1 wt=9600.00> STORE_LCL_VAR BB20 regmask=[x2] minReg=1 outOfOrder wt=2200.00> LCL_VAR BB21 regmask=[x28] minReg=1 outOfOrder wt=5600.00> BB21 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB22 regmask=[x27] minReg=1 wt=9600.00> STORE_LCL_VAR BB22 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB23 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB23 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB24 regmask=[x6] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x6] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB27 regmask=[x22] minReg=1 last outOfOrder wt=2700.00> ADD BB27 regmask=[x22] minReg=1 wt=3200.00> BB27 regmask=[x22] minReg=1 last wt=800.00> STORE_LCL_VAR BB27 regmask=[x22] minReg=1 wt=2700.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=800.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> CNS_INT BB28 regmask=[x7] minReg=1 wt=3200.00> BB28 regmask=[x7] minReg=1 last wt=800.00> STORE_LCL_VAR BB28 regmask=[x22] minReg=1 spillAfter wt=2800.00> LCL_VAR BB29 regmask=[x27] minReg=1 wt=9600.00> STORE_LCL_VAR BB29 regmask=[x6] minReg=1 wt=4200.00> CNS_INT BB29 regmask=[x22] minReg=1 wt=3200.00> BB29 regmask=[x22] minReg=1 last wt=800.00> STORE_LCL_VAR BB29 regmask=[x22] minReg=1 wt=2700.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB257 regmask=[x14] minReg=1 last regOptional wt=1200.00> CAST BB257 regmask=[x11] minReg=1 wt=800.00> JMPTABLE BB257 regmask=[x14] minReg=1 wt=800.00> SWITCH_TABLE BB257 regmask=[x12] minReg=1 wt=800.00> BB257 regmask=[x11] minReg=1 last wt=200.00> BB257 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB145 regmask=[x3] minReg=1 outOfOrder wt=4100.00> LCL_VAR BB146 regmask=[x3] minReg=1 last wt=4100.00> ADD BB146 regmask=[x3] minReg=1 wt=800.00> BB146 regmask=[x3] minReg=1 last wt=200.00> STORE_LCL_VAR BB146 regmask=[x3] minReg=1 spillAfter wt=4100.00> LCL_VAR BB146 regmask=[x2] minReg=1 outOfOrder wt=4650.00> LCL_VAR BB146 regmask=[x22] minReg=1 outOfOrder wt=2900.00> STORE_LCL_VAR BB147 regmask=[x13] minReg=1 wt=600.00> CNS_INT BB148 regmask=[x13] minReg=1 wt=800.00> BB148 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB148 regmask=[x13] minReg=1 wt=600.00> LCL_VAR BB149 regmask=[x13] minReg=1 last regOptional wt=600.00> CAST BB149 regmask=[x13] minReg=1 wt=800.00> BB149 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB149 regmask=[x13] minReg=1 outOfOrder wt=23700.00> LCL_VAR BB150 regmask=[x0] minReg=1 outOfOrder wt=3200.00> IND BB150 regmask=[x13] minReg=1 wt=800.00> BB150 regmask=[x13] minReg=1 last wt=200.00> LCL_VAR BB151 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB151 regmask=[x1] minReg=1 spillAfter outOfOrder wt=2200.00> STORE_LCL_VAR BB152 regmask=[x11] minReg=1 wt=800.00> CNS_INT BB153 regmask=[x11] minReg=1 wt=800.00> BB153 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB153 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB154 regmask=[x0] minReg=1 last wt=3200.00> STORE_LCL_VAR BB154 regmask=[x11] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x11] minReg=1 wt=1200.00> ADD BB154 regmask=[x0] minReg=1 wt=800.00> BB154 regmask=[x0] minReg=1 last wt=200.00> STORE_LCL_VAR BB154 regmask=[x0] minReg=1 spillAfter wt=3200.00> LCL_VAR BB154 regmask=[x11] minReg=1 last wt=1200.00> IND BB154 regmask=[x11] minReg=1 wt=800.00> BB154 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB154 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB155 regmask=[x11] minReg=1 last regOptional wt=800.00> CAST BB155 regmask=[x13] minReg=1 wt=800.00> BB155 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB155 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB156 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB157 regmask=[x19] minReg=1 wt=26550.00> IND BB157 regmask=[x11] minReg=1 wt=800.00> BB157 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB157 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB157 regmask=[x19] minReg=1 wt=26550.00> IND BB157 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB157 regmask=[x11] minReg=1 wt=1000.00> BB157 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x19] minReg=1 wt=26550.00> ADD BB158 regmask=[x14] minReg=1 wt=800.00> BB158 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB158 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x14] minReg=1 wt=1200.00> IND BB158 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB158 regmask=[x11] minReg=1 wt=1000.00> BB158 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x14] minReg=1 last wt=1200.00> IND BB158 regmask=[x14] minReg=1 wt=800.00> BB158 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB158 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB158 regmask=[x11] minReg=1 last wt=1000.00> ADD BB158 regmask=[x13] minReg=1 wt=800.00> LCL_VAR BB158 regmask=[x19] minReg=1 wt=26550.00> BB158 regmask=[x13] minReg=1 last wt=200.00> BB159 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB159 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB159 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x0] minReg=1 fixed wt=800.00> BB159 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB159 regmask=[x1] minReg=1 last copy fixed wt=23700.00> BB159 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB159 regmask=[x11] minReg=1 wt=800.00> BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 last fixed wt=200.00> BB159 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB159 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB159 regmask=[x13] minReg=1 wt=800.00> BB159 regmask=[x0] minReg=1 wt=200.00> BB159 regmask=[x0] minReg=1 last fixed wt=200.00> BB159 regmask=[x1] minReg=1 wt=200.00> BB159 regmask=[x1] minReg=1 last fixed wt=200.00> BB159 regmask=[x11] minReg=1 wt=200.00> BB159 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB159 regmask=[x13] minReg=1 last wt=800.00> BB159 regmask=[x0] minReg=1 last wt=200.00> BB159 regmask=[x1] minReg=1 last wt=200.00> BB159 regmask=[x2] minReg=1 last wt=200.00> BB159 regmask=[x3] minReg=1 last wt=200.00> BB159 regmask=[x4] minReg=1 last wt=200.00> BB159 regmask=[x5] minReg=1 last wt=200.00> BB159 regmask=[x6] minReg=1 last wt=200.00> BB159 regmask=[x7] minReg=1 last wt=200.00> BB159 regmask=[x8] minReg=1 last wt=200.00> BB159 regmask=[x9] minReg=1 last wt=200.00> BB159 regmask=[x10] minReg=1 last wt=200.00> BB159 regmask=[x11] minReg=1 last wt=200.00> BB159 regmask=[x12] minReg=1 last wt=200.00> BB159 regmask=[x13] minReg=1 last wt=200.00> BB159 regmask=[x14] minReg=1 last wt=200.00> BB159 regmask=[x15] minReg=1 last wt=200.00> BB159 regmask=[xip0] minReg=1 last wt=200.00> BB159 regmask=[xip1] minReg=1 last wt=200.00> BB159 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB160 regmask=[x7] minReg=1 spillAfter outOfOrder wt=2800.00> LCL_VAR BB160 regmask=[x2] minReg=1 wt=4650.00> LCL_VAR BB161 regmask=[x9] minReg=1 outOfOrder wt=7000.00> LCL_VAR BB161 regmask=[x8] minReg=1 spillAfter outOfOrder wt=2600.00> LCL_VAR BB161 regmask=[x6] minReg=1 spillAfter outOfOrder wt=1800.00> LCL_VAR BB161 regmask=[x9] minReg=1 wt=7000.00> IND BB161 regmask=[x11] minReg=1 wt=800.00> BB161 regmask=[x11] minReg=1 last wt=200.00> ADD BB161 regmask=[x11] minReg=1 wt=800.00> BB161 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB161 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB161 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB163 regmask=[x20] minReg=1 wt=2250.00> IND BB163 regmask=[x11] minReg=1 wt=800.00> BB163 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB163 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB163 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB165 regmask=[x19] minReg=1 wt=26550.00> IND BB165 regmask=[x13] minReg=1 wt=800.00> BB165 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB165 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB165 regmask=[x11] minReg=1 wt=2400.00> IND BB165 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB165 regmask=[x19] minReg=1 wt=26550.00> IND BB165 regmask=[x12] minReg=1 wt=800.00> BB165 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB165 regmask=[x13] minReg=1 wt=1000.00> BB165 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x19] minReg=1 wt=26550.00> ADD BB166 regmask=[x14] minReg=1 wt=800.00> BB166 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB166 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x14] minReg=1 wt=1200.00> IND BB166 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x13] minReg=1 wt=1000.00> BB166 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x14] minReg=1 last wt=1200.00> IND BB166 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x13] minReg=1 wt=1000.00> BFIZ BB166 regmask=[x12] minReg=1 wt=800.00> BB166 regmask=[x14] minReg=1 last wt=200.00> BB166 regmask=[x12] minReg=1 last wt=200.00> ADD BB166 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x11] minReg=1 wt=2400.00> IND BB166 regmask=[x12] minReg=1 wt=800.00> BB166 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x11] minReg=1 last wt=2400.00> IND BB166 regmask=[x11] minReg=1 wt=800.00> BB166 regmask=[x14] minReg=1 last wt=200.00> BB166 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB166 regmask=[x13] minReg=1 last wt=1000.00> ADD BB166 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB166 regmask=[x19] minReg=1 wt=26550.00> BB166 regmask=[x11] minReg=1 last wt=200.00> BB168 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB168 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB168 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x0] minReg=1 fixed wt=800.00> BB168 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB168 regmask=[x1] minReg=1 last copy fixed wt=2400.00> BB168 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB168 regmask=[x11] minReg=1 wt=800.00> BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 last fixed wt=200.00> BB168 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB168 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB168 regmask=[x13] minReg=1 wt=800.00> BB168 regmask=[x0] minReg=1 wt=200.00> BB168 regmask=[x0] minReg=1 last fixed wt=200.00> BB168 regmask=[x1] minReg=1 wt=200.00> BB168 regmask=[x1] minReg=1 last fixed wt=200.00> BB168 regmask=[x11] minReg=1 wt=200.00> BB168 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB168 regmask=[x13] minReg=1 last wt=800.00> BB168 regmask=[x0] minReg=1 last wt=200.00> BB168 regmask=[x1] minReg=1 last wt=200.00> BB168 regmask=[x2] minReg=1 last wt=200.00> BB168 regmask=[x3] minReg=1 last wt=200.00> BB168 regmask=[x4] minReg=1 last wt=200.00> BB168 regmask=[x5] minReg=1 last wt=200.00> BB168 regmask=[x6] minReg=1 last wt=200.00> BB168 regmask=[x7] minReg=1 last wt=200.00> BB168 regmask=[x8] minReg=1 last wt=200.00> BB168 regmask=[x9] minReg=1 last wt=200.00> BB168 regmask=[x10] minReg=1 last wt=200.00> BB168 regmask=[x11] minReg=1 last wt=200.00> BB168 regmask=[x12] minReg=1 last wt=200.00> BB168 regmask=[x13] minReg=1 last wt=200.00> BB168 regmask=[x14] minReg=1 last wt=200.00> BB168 regmask=[x15] minReg=1 last wt=200.00> BB168 regmask=[xip0] minReg=1 last wt=200.00> BB168 regmask=[xip1] minReg=1 last wt=200.00> BB168 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB169 regmask=[x9] minReg=1 last wt=7000.00> ADD BB169 regmask=[x9] minReg=1 wt=800.00> BB169 regmask=[x9] minReg=1 last wt=200.00> STORE_LCL_VAR BB169 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB170 regmask=[x2] minReg=1 last wt=4650.00> ADD BB170 regmask=[x2] minReg=1 wt=800.00> BB170 regmask=[x2] minReg=1 last wt=200.00> STORE_LCL_VAR BB170 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB186 regmask=[x20] minReg=1 wt=2250.00> IND BB186 regmask=[x11] minReg=1 wt=800.00> BB186 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB186 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB186 regmask=[x11] minReg=1 wt=2400.00> BB187 regmask=[x11] minReg=1 regOptional wt=200.00> LCL_VAR BB187 regmask=[x19] minReg=1 wt=26550.00> IND BB187 regmask=[x13] minReg=1 wt=800.00> BB187 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB187 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB187 regmask=[x11] minReg=1 outOfOrder wt=2400.00> IND BB187 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB187 regmask=[x19] minReg=1 wt=26550.00> IND BB187 regmask=[x12] minReg=1 wt=800.00> BB187 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB187 regmask=[x13] minReg=1 wt=1000.00> BB187 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x19] minReg=1 wt=26550.00> ADD BB188 regmask=[x14] minReg=1 wt=800.00> BB188 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB188 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x14] minReg=1 wt=1200.00> IND BB188 regmask=[x12] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x13] minReg=1 wt=1000.00> BB188 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x14] minReg=1 last wt=1200.00> IND BB188 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x13] minReg=1 wt=1000.00> BFIZ BB188 regmask=[x12] minReg=1 wt=800.00> BB188 regmask=[x14] minReg=1 last wt=200.00> BB188 regmask=[x12] minReg=1 last wt=200.00> ADD BB188 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x11] minReg=1 wt=2400.00> IND BB188 regmask=[x12] minReg=1 wt=800.00> BB188 regmask=[x12] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x11] minReg=1 last wt=2400.00> IND BB188 regmask=[x11] minReg=1 wt=800.00> BB188 regmask=[x14] minReg=1 last wt=200.00> BB188 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB188 regmask=[x13] minReg=1 last wt=1000.00> ADD BB188 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB188 regmask=[x19] minReg=1 wt=26550.00> BB188 regmask=[x11] minReg=1 last wt=200.00> BB190 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB190 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB190 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x0] minReg=1 fixed wt=800.00> BB190 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB190 regmask=[x1] minReg=1 last copy fixed wt=2400.00> BB190 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB190 regmask=[x11] minReg=1 wt=800.00> BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 last fixed wt=200.00> BB190 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB190 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB190 regmask=[x13] minReg=1 wt=800.00> BB190 regmask=[x0] minReg=1 wt=200.00> BB190 regmask=[x0] minReg=1 last fixed wt=200.00> BB190 regmask=[x1] minReg=1 wt=200.00> BB190 regmask=[x1] minReg=1 last fixed wt=200.00> BB190 regmask=[x11] minReg=1 wt=200.00> BB190 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB190 regmask=[x13] minReg=1 last wt=800.00> BB190 regmask=[x0] minReg=1 last wt=200.00> BB190 regmask=[x1] minReg=1 last wt=200.00> BB190 regmask=[x2] minReg=1 last wt=200.00> BB190 regmask=[x3] minReg=1 last wt=200.00> BB190 regmask=[x4] minReg=1 last wt=200.00> BB190 regmask=[x5] minReg=1 last wt=200.00> BB190 regmask=[x6] minReg=1 last wt=200.00> BB190 regmask=[x7] minReg=1 last wt=200.00> BB190 regmask=[x8] minReg=1 last wt=200.00> BB190 regmask=[x9] minReg=1 last wt=200.00> BB190 regmask=[x10] minReg=1 last wt=200.00> BB190 regmask=[x11] minReg=1 last wt=200.00> BB190 regmask=[x12] minReg=1 last wt=200.00> BB190 regmask=[x13] minReg=1 last wt=200.00> BB190 regmask=[x14] minReg=1 last wt=200.00> BB190 regmask=[x15] minReg=1 last wt=200.00> BB190 regmask=[xip0] minReg=1 last wt=200.00> BB190 regmask=[xip1] minReg=1 last wt=200.00> BB190 regmask=[lr] minReg=1 last wt=200.00> LCL_VAR BB194 regmask=[x4] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB194 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB195 regmask=[x24] minReg=1 outOfOrder wt=6700.00> LCL_VAR BB195 regmask=[x4] minReg=1 wt=91300.00> IND BB195 regmask=[x14] minReg=1 wt=6400.00> BB195 regmask=[x14] minReg=1 last wt=1600.00> STORE_LCL_VAR BB195 regmask=[x14] minReg=1 wt=6000.00> LCL_VAR BB195 regmask=[x14] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x14] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x13] minReg=1 spillAfter wt=23700.00> LCL_VAR BB191 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB191 regmask=[x4] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x4] minReg=1 last wt=3200.00> ADD BB191 regmask=[x4] minReg=1 wt=3200.00> BB191 regmask=[x4] minReg=1 last wt=800.00> STORE_LCL_VAR BB191 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB191 regmask=[x14] minReg=1 last wt=6000.00> STORE_LCL_VAR BB191 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB191 regmask=[x19] minReg=1 wt=26550.00> IND BB191 regmask=[x11] minReg=1 wt=3200.00> BB191 regmask=[x11] minReg=1 last wt=800.00> STORE_LCL_VAR BB191 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB191 regmask=[x19] minReg=1 wt=26550.00> IND BB191 regmask=[x12] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x11] minReg=1 wt=4000.00> BB191 regmask=[x12] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x19] minReg=1 wt=26550.00> ADD BB192 regmask=[x12] minReg=1 wt=3200.00> BB192 regmask=[x12] minReg=1 last wt=800.00> STORE_LCL_VAR BB192 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x12] minReg=1 wt=4800.00> IND BB192 regmask=[x15] minReg=1 wt=3200.00> LCL_VAR BB192 regmask=[x11] minReg=1 wt=4000.00> BB192 regmask=[x15] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x12] minReg=1 last wt=4800.00> IND BB192 regmask=[x12] minReg=1 wt=3200.00> BB192 regmask=[x12] minReg=1 last wt=800.00> LCL_VAR BB192 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x14] minReg=1 last wt=4800.00> LCL_VAR BB192 regmask=[x11] minReg=1 last wt=4000.00> ADD BB192 regmask=[x14] minReg=1 wt=3200.00> LCL_VAR BB192 regmask=[x19] minReg=1 wt=26550.00> BB192 regmask=[x14] minReg=1 last wt=800.00> BB193 regmask=[x0] minReg=1 wt=800.00> LCL_VAR BB193 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB193 regmask=[x0] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x0] minReg=1 fixed wt=3200.00> BB193 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB193 regmask=[x1] minReg=1 last copy fixed wt=4800.00> BB193 regmask=[x1] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x1] minReg=1 fixed wt=3200.00> CNS_INT BB193 regmask=[x11] minReg=1 wt=3200.00> BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 last fixed wt=800.00> BB193 regmask=[x11] minReg=1 wt=800.00> PUTARG_REG BB193 regmask=[x11] minReg=1 fixed wt=3200.00> CALL BB193 regmask=[x14] minReg=1 wt=3200.00> BB193 regmask=[x0] minReg=1 wt=800.00> BB193 regmask=[x0] minReg=1 last fixed wt=800.00> BB193 regmask=[x1] minReg=1 wt=800.00> BB193 regmask=[x1] minReg=1 last fixed wt=800.00> BB193 regmask=[x11] minReg=1 wt=800.00> BB193 regmask=[x11] minReg=1 last fixed wt=800.00> CALL BB193 regmask=[x14] minReg=1 last wt=3200.00> BB193 regmask=[x0] minReg=1 last wt=800.00> BB193 regmask=[x1] minReg=1 last wt=800.00> BB193 regmask=[x2] minReg=1 last wt=800.00> BB193 regmask=[x3] minReg=1 last wt=800.00> BB193 regmask=[x4] minReg=1 last wt=800.00> BB193 regmask=[x5] minReg=1 last wt=800.00> BB193 regmask=[x6] minReg=1 last wt=800.00> BB193 regmask=[x7] minReg=1 last wt=800.00> BB193 regmask=[x8] minReg=1 last wt=800.00> BB193 regmask=[x9] minReg=1 last wt=800.00> BB193 regmask=[x10] minReg=1 last wt=800.00> BB193 regmask=[x11] minReg=1 last wt=800.00> BB193 regmask=[x12] minReg=1 last wt=800.00> BB193 regmask=[x13] minReg=1 last wt=800.00> BB193 regmask=[x14] minReg=1 last wt=800.00> BB193 regmask=[x15] minReg=1 last wt=800.00> BB193 regmask=[xip0] minReg=1 last wt=800.00> BB193 regmask=[xip1] minReg=1 last wt=800.00> BB193 regmask=[lr] minReg=1 last wt=800.00> BB193 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB197 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB197 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB198 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB198 regmask=[x4] minReg=1 wt=91300.00> IND BB198 regmask=[x14] minReg=1 wt=800.00> BB198 regmask=[x14] minReg=1 last wt=200.00> STORE_LCL_VAR BB198 regmask=[x14] minReg=1 wt=6000.00> LCL_VAR BB198 regmask=[x14] minReg=1 last wt=6000.00> LCL_VAR BB199 regmask=[x4] minReg=1 last wt=91300.00> ADD BB199 regmask=[x4] minReg=1 wt=800.00> BB199 regmask=[x4] minReg=1 last wt=200.00> STORE_LCL_VAR BB199 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB258 regmask=[x12] minReg=1 last regOptional wt=1200.00> CAST BB258 regmask=[x11] minReg=1 wt=800.00> JMPTABLE BB258 regmask=[x14] minReg=1 wt=800.00> SWITCH_TABLE BB258 regmask=[x12] minReg=1 wt=800.00> BB258 regmask=[x11] minReg=1 last wt=200.00> BB258 regmask=[x14] minReg=1 last wt=200.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=200.00> LCL_VAR BB171 regmask=[x2] minReg=1 spillAfter wt=4650.00> NE BB171 regmask=[x11] minReg=1 wt=800.00> BB171 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB171 regmask=[x10] minReg=1 outOfOrder wt=400.00> OR BB171 regmask=[x11] minReg=1 wt=800.00> BB171 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB172 regmask=[x1] minReg=1 spillAfter wt=2200.00> LCL_VAR BB173 regmask=[x0] minReg=1 spillAfter wt=3200.00> IND BB173 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB173 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB173 regmask=[x27] minReg=1 wt=9600.00> BB173 regmask=[x11] minReg=1 last wt=200.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB174 regmask=[x20] minReg=1 wt=2250.00> IND BB174 regmask=[x11] minReg=1 wt=800.00> BB174 regmask=[x11] minReg=1 last wt=200.00> STORE_LCL_VAR BB174 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB174 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB176 regmask=[x19] minReg=1 wt=26550.00> IND BB176 regmask=[x10] minReg=1 wt=800.00> BB176 regmask=[x10] minReg=1 last wt=200.00> STORE_LCL_VAR BB176 regmask=[x10] minReg=1 wt=1000.00> LCL_VAR BB176 regmask=[x11] minReg=1 wt=2400.00> IND BB176 regmask=[x13] minReg=1 wt=800.00> LCL_VAR BB176 regmask=[x19] minReg=1 wt=26550.00> IND BB176 regmask=[x14] minReg=1 wt=800.00> BB176 regmask=[x13] minReg=1 last wt=200.00> LCL_VAR BB176 regmask=[x10] minReg=1 wt=1000.00> BB176 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x19] minReg=1 wt=26550.00> ADD BB177 regmask=[x13] minReg=1 wt=800.00> BB177 regmask=[x13] minReg=1 last wt=200.00> STORE_LCL_VAR BB177 regmask=[x13] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x13] minReg=1 wt=1200.00> IND BB177 regmask=[x14] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x10] minReg=1 wt=1000.00> BB177 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x13] minReg=1 last wt=1200.00> IND BB177 regmask=[x13] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x10] minReg=1 wt=1000.00> BFIZ BB177 regmask=[x14] minReg=1 wt=800.00> BB177 regmask=[x13] minReg=1 last wt=200.00> BB177 regmask=[x14] minReg=1 last wt=200.00> ADD BB177 regmask=[x13] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x11] minReg=1 wt=2400.00> IND BB177 regmask=[x14] minReg=1 wt=800.00> BB177 regmask=[x14] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x11] minReg=1 last wt=2400.00> IND BB177 regmask=[x11] minReg=1 wt=800.00> BB177 regmask=[x13] minReg=1 last wt=200.00> BB177 regmask=[x11] minReg=1 last wt=200.00> LCL_VAR BB177 regmask=[x10] minReg=1 last wt=1000.00> ADD BB177 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB177 regmask=[x19] minReg=1 wt=26550.00> BB177 regmask=[x11] minReg=1 last wt=200.00> BB179 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB179 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB179 regmask=[x0] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x0] minReg=1 fixed wt=800.00> BB179 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB179 regmask=[x1] minReg=1 last copy fixed wt=2400.00> BB179 regmask=[x1] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x1] minReg=1 fixed wt=800.00> CNS_INT BB179 regmask=[x11] minReg=1 wt=800.00> BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 last fixed wt=200.00> BB179 regmask=[x11] minReg=1 wt=200.00> PUTARG_REG BB179 regmask=[x11] minReg=1 fixed wt=800.00> CALL BB179 regmask=[x10] minReg=1 wt=800.00> BB179 regmask=[x0] minReg=1 wt=200.00> BB179 regmask=[x0] minReg=1 last fixed wt=200.00> BB179 regmask=[x1] minReg=1 wt=200.00> BB179 regmask=[x1] minReg=1 last fixed wt=200.00> BB179 regmask=[x11] minReg=1 wt=200.00> BB179 regmask=[x11] minReg=1 last fixed wt=200.00> CALL BB179 regmask=[x10] minReg=1 last wt=800.00> BB179 regmask=[x0] minReg=1 last wt=200.00> BB179 regmask=[x1] minReg=1 last wt=200.00> BB179 regmask=[x2] minReg=1 last wt=200.00> BB179 regmask=[x3] minReg=1 last wt=200.00> BB179 regmask=[x4] minReg=1 last wt=200.00> BB179 regmask=[x5] minReg=1 last wt=200.00> BB179 regmask=[x6] minReg=1 last wt=200.00> BB179 regmask=[x7] minReg=1 last wt=200.00> BB179 regmask=[x8] minReg=1 last wt=200.00> BB179 regmask=[x9] minReg=1 last wt=200.00> BB179 regmask=[x10] minReg=1 last wt=200.00> BB179 regmask=[x11] minReg=1 last wt=200.00> BB179 regmask=[x12] minReg=1 last wt=200.00> BB179 regmask=[x13] minReg=1 last wt=200.00> BB179 regmask=[x14] minReg=1 last wt=200.00> BB179 regmask=[x15] minReg=1 last wt=200.00> BB179 regmask=[xip0] minReg=1 last wt=200.00> BB179 regmask=[xip1] minReg=1 last wt=200.00> BB179 regmask=[lr] minReg=1 last wt=200.00> CNS_INT BB180 regmask=[x10] minReg=1 wt=800.00> BB180 regmask=[x10] minReg=1 last wt=200.00> STORE_LCL_VAR BB180 regmask=[x11] minReg=1 wt=400.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> CNS_INT BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 last fixed wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> PUTARG_REG BB110 regmask=[x11] minReg=1 fixed wt=0.00> CALL BB110 regmask=[x0] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 wt=0.00> BB110 regmask=[x11] minReg=1 last fixed wt=0.00> CALL BB110 regmask=[x0] minReg=1 last wt=0.00> BB110 regmask=[x0] minReg=1 last wt=0.00> BB110 regmask=[x1] minReg=1 last wt=0.00> BB110 regmask=[x2] minReg=1 last wt=0.00> BB110 regmask=[x3] minReg=1 last wt=0.00> BB110 regmask=[x4] minReg=1 last wt=0.00> BB110 regmask=[x5] minReg=1 last wt=0.00> BB110 regmask=[x6] minReg=1 last wt=0.00> BB110 regmask=[x7] minReg=1 last wt=0.00> BB110 regmask=[x8] minReg=1 last wt=0.00> BB110 regmask=[x9] minReg=1 last wt=0.00> BB110 regmask=[x10] minReg=1 last wt=0.00> BB110 regmask=[x11] minReg=1 last wt=0.00> BB110 regmask=[x12] minReg=1 last wt=0.00> BB110 regmask=[x13] minReg=1 last wt=0.00> BB110 regmask=[x14] minReg=1 last wt=0.00> BB110 regmask=[x15] minReg=1 last wt=0.00> BB110 regmask=[xip0] minReg=1 last wt=0.00> BB110 regmask=[xip1] minReg=1 last wt=0.00> BB110 regmask=[lr] minReg=1 last wt=0.00> CNS_INT BB254 regmask=[x0] minReg=1 wt=0.00> BB254 regmask=[x0] minReg=1 last wt=0.00> IND BB254 regmask=[x0] minReg=1 wt=0.00> BB254 regmask=[x0] minReg=1 last wt=0.00> BB254 regmask=[x0] minReg=1 last wt=0.00> BB254 regmask=[x1] minReg=1 last wt=0.00> BB254 regmask=[x2] minReg=1 last wt=0.00> BB254 regmask=[x3] minReg=1 last wt=0.00> BB254 regmask=[x4] minReg=1 last wt=0.00> BB254 regmask=[x5] minReg=1 last wt=0.00> BB254 regmask=[x6] minReg=1 last wt=0.00> BB254 regmask=[x7] minReg=1 last wt=0.00> BB254 regmask=[x8] minReg=1 last wt=0.00> BB254 regmask=[x9] minReg=1 last wt=0.00> BB254 regmask=[x10] minReg=1 last wt=0.00> BB254 regmask=[x11] minReg=1 last wt=0.00> BB254 regmask=[x12] minReg=1 last wt=0.00> BB254 regmask=[x13] minReg=1 last wt=0.00> BB254 regmask=[x14] minReg=1 last wt=0.00> BB254 regmask=[x15] minReg=1 last wt=0.00> BB254 regmask=[xip0] minReg=1 last wt=0.00> BB254 regmask=[xip1] minReg=1 last wt=0.00> BB254 regmask=[lr] minReg=1 last wt=0.00> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[x19] minReg=1 regOptional wt=100.00> LCL_VAR BB107 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB107 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB108 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB108 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB111 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB121 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB121 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB122 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB122 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB123 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB129 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB129 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB130 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB130 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB132 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB182 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB182 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB183 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB183 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB185 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB201 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB201 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB203 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB203 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB204 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB215 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB215 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB216 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB216 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB226 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB227 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB227 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB228 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB228 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB229 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB233 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB233 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB234 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB234 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB235 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB236 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB236 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB237 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB237 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB238 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB242 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB242 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB243 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB243 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB244 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB249 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB251 regmask=[x0] minReg=1 last copy fixed wt=26550.00> LCL_VAR BB157 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB157 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB158 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB158 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB159 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB165 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB165 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB166 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB166 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB168 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB187 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB187 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB188 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB188 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB190 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB191 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB191 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB192 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB192 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB193 regmask=[x0] minReg=1 copy fixed wt=26550.00> LCL_VAR BB176 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB176 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB177 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB177 regmask=[x19] minReg=1 wt=26550.00> LCL_VAR BB179 regmask=[x0] minReg=1 copy fixed wt=26550.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V01 (Interval 1) BB00 regmask=[x21] minReg=1 regOptional wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 copy fixed wt=2150.00> LCL_VAR BB01 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB02 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB57 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB58 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB60 regmask=[x0] minReg=1 copy fixed wt=2150.00> LCL_VAR BB63 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB64 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB65 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB74 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB103 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB104 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB224 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB248 regmask=[x21] minReg=1 wt=2150.00> LCL_VAR BB249 regmask=[x21] minReg=1 last wt=2150.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V02 --- V03 (Interval 2) BB00 regmask=[x20] minReg=1 regOptional wt=100.00> LCL_VAR BB78 regmask=[x20] minReg=1 wt=2250.00> LCL_VAR BB79 regmask=[x20] minReg=1 wt=2250.00> LCL_VAR BB106 regmask=[x20] minReg=1 wt=2250.00> LCL_VAR BB127 regmask=[x20] minReg=1 wt=2250.00> LCL_VAR BB144 regmask=[x20] minReg=1 wt=2250.00> LCL_VAR BB226 regmask=[x1] minReg=1 copy fixed wt=2250.00> LCL_VAR BB251 regmask=[x20] minReg=1 last wt=2250.00> LCL_VAR BB163 regmask=[x20] minReg=1 wt=2250.00> LCL_VAR BB186 regmask=[x20] minReg=1 wt=2250.00> LCL_VAR BB174 regmask=[x20] minReg=1 wt=2250.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V04 (Interval 3) STORE_LCL_VAR BB07 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB51 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB58 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB59 regmask=[x27] minReg=1 wt=9600.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB17 regmask=[x27] minReg=1 last outOfOrder wt=9600.00> STORE_LCL_VAR BB17 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB19 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x27] minReg=1 last wt=9600.00> STORE_LCL_VAR BB20 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB20 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB22 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB23 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB26 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB29 regmask=[x27] minReg=1 wt=9600.00> LCL_VAR BB173 regmask=[x27] minReg=1 wt=9600.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V05 (Interval 4) STORE_LCL_VAR BB07 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB50 regmask=[x28] minReg=1 wt=5600.00> STORE_LCL_VAR BB51 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB53 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB58 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB66 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB73 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB74 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB224 regmask=[x28] minReg=1 wt=5600.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB21 regmask=[x28] minReg=1 outOfOrder wt=5600.00> BB21 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB22 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB23 regmask=[x28] minReg=1 wt=5600.00> LCL_VAR BB173 regmask=[x28] minReg=1 wt=5600.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V06 (Interval 5) STORE_LCL_VAR BB07 regmask=[x3] minReg=1 spillAfter wt=2900.00> LCL_VAR BB66 regmask=[x3] minReg=1 wt=2900.00> LCL_VAR BB66 regmask=[x3] minReg=1 last wt=2900.00> STORE_LCL_VAR BB66 regmask=[x22] minReg=1 wt=2900.00> LCL_VAR BB85 regmask=[x22] minReg=1 wt=2900.00> LCL_VAR BB85 regmask=[x22] minReg=1 wt=2900.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB18 regmask=[x3] minReg=1 outOfOrder wt=2900.00> STORE_LCL_VAR BB19 regmask=[x3] minReg=1 wt=2900.00> LCL_VAR BB146 regmask=[x22] minReg=1 outOfOrder wt=2900.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V07 (Interval 6) STORE_LCL_VAR BB07 regmask=[x4] minReg=1 spillAfter wt=2200.00> LCL_VAR BB66 regmask=[x4] minReg=1 wt=2200.00> LCL_VAR BB66 regmask=[x4] minReg=1 last wt=2200.00> STORE_LCL_VAR BB66 regmask=[x1] minReg=1 spillAfter wt=2200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB20 regmask=[x2] minReg=1 outOfOrder wt=2200.00> LCL_VAR BB151 regmask=[x1] minReg=1 spillAfter outOfOrder wt=2200.00> LCL_VAR BB172 regmask=[x1] minReg=1 spillAfter wt=2200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V08 (Interval 7) STORE_LCL_VAR BB73 regmask=[x2] minReg=1 wt=4650.00> STORE_LCL_VAR BB74 regmask=[x2] minReg=1 wt=4650.00> LCL_VAR BB82 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB124 regmask=[x2] minReg=1 wt=4650.00> LCL_VAR BB125 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB134 regmask=[x2] minReg=1 last wt=4650.00> STORE_LCL_VAR BB134 regmask=[x2] minReg=1 spillAfter wt=4650.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB146 regmask=[x2] minReg=1 outOfOrder wt=4650.00> LCL_VAR BB151 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB160 regmask=[x2] minReg=1 wt=4650.00> LCL_VAR BB161 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB170 regmask=[x2] minReg=1 last wt=4650.00> STORE_LCL_VAR BB170 regmask=[x2] minReg=1 spillAfter wt=4650.00> LCL_VAR BB171 regmask=[x2] minReg=1 spillAfter wt=4650.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V09 (Interval 8) STORE_LCL_VAR BB07 regmask=[x5] minReg=1 wt=2400.00> BB43 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB46 regmask=[x5] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x5] minReg=1 spillAfter wt=2400.00> LCL_VAR BB66 regmask=[x5] minReg=1 spillAfter wt=2400.00> LCL_VAR BB205 regmask=[x5] minReg=1 wt=2400.00> BB216 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB226 regmask=[x2] minReg=1 spillAfter wt=2400.00> BB244 regmask=[] minReg=1 outOfOrder regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=200.00> --- V10 (Interval 9) STORE_LCL_VAR BB07 regmask=[x6] minReg=1 wt=4200.00> LCL_VAR BB52 regmask=[x6] minReg=1 wt=4200.00> LCL_VAR BB53 regmask=[x6] minReg=1 last wt=4200.00> LCL_VAR BB24 regmask=[x6] minReg=1 wt=4200.00> LCL_VAR BB26 regmask=[x6] minReg=1 wt=4200.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB29 regmask=[x6] minReg=1 wt=4200.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V11 (Interval 10) STORE_LCL_VAR BB01 regmask=[x22] minReg=1 wt=2700.00> LCL_VAR BB54 regmask=[x22] minReg=1 wt=2700.00> BB62 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> LCL_VAR BB27 regmask=[x22] minReg=1 last outOfOrder wt=2700.00> STORE_LCL_VAR BB27 regmask=[x22] minReg=1 wt=2700.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB29 regmask=[x22] minReg=1 wt=2700.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V12 (Interval 11) STORE_LCL_VAR BB07 regmask=[x7] minReg=1 wt=2800.00> STORE_LCL_VAR BB55 regmask=[x7] minReg=1 spillAfter wt=2800.00> LCL_VAR BB78 regmask=[x7] minReg=1 spillAfter wt=2800.00> LCL_VAR BB124 regmask=[x7] minReg=1 spillAfter wt=2800.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB27 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=800.00> STORE_LCL_VAR BB28 regmask=[x22] minReg=1 spillAfter wt=2800.00> LCL_VAR BB160 regmask=[x7] minReg=1 spillAfter outOfOrder wt=2800.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V13 (Interval 12) STORE_LCL_VAR BB07 regmask=[x8] minReg=1 wt=4800.00> LCL_VAR BB16 regmask=[x8] minReg=1 last wt=4800.00> STORE_LCL_VAR BB16 regmask=[x8] minReg=1 wt=4800.00> LCL_VAR BB54 regmask=[x8] minReg=1 last wt=4800.00> STORE_LCL_VAR BB54 regmask=[x8] minReg=1 wt=4800.00> LCL_VAR BB57 regmask=[x8] minReg=1 last wt=4800.00> LCL_VAR BB30 regmask=[x8] minReg=1 last wt=4800.00> STORE_LCL_VAR BB30 regmask=[x8] minReg=1 wt=4800.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V14 (Interval 13) STORE_LCL_VAR BB73 regmask=[x3] minReg=1 wt=4100.00> STORE_LCL_VAR BB74 regmask=[x3] minReg=1 wt=4100.00> LCL_VAR BB82 regmask=[x3] minReg=1 wt=4100.00> LCL_VAR BB84 regmask=[x3] minReg=1 spillAfter wt=4100.00> LCL_VAR BB113 regmask=[x3] minReg=1 wt=4100.00> LCL_VAR BB135 regmask=[x3] minReg=1 spillAfter wt=4100.00> LCL_VAR BB134 regmask=[x3] minReg=1 last wt=4100.00> STORE_LCL_VAR BB134 regmask=[x3] minReg=1 spillAfter wt=4100.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB145 regmask=[x3] minReg=1 outOfOrder wt=4100.00> LCL_VAR BB146 regmask=[x3] minReg=1 last wt=4100.00> STORE_LCL_VAR BB146 regmask=[x3] minReg=1 spillAfter wt=4100.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V15 (Interval 14) STORE_LCL_VAR BB06 regmask=[x26] minReg=1 wt=1900.00> LCL_VAR BB07 regmask=[x26] minReg=1 wt=1900.00> LCL_VAR BB61 regmask=[x26] minReg=1 wt=1900.00> STORE_LCL_VAR BB62 regmask=[x26] minReg=1 wt=1900.00> LCL_VAR BB78 regmask=[x26] minReg=1 wt=1900.00> LCL_VAR BB248 regmask=[x26] minReg=1 last wt=1900.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V16 (Interval 15) STORE_LCL_VAR BB07 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB47 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB48 regmask=[x1] minReg=1 last wt=91300.00> STORE_LCL_VAR BB48 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB35 regmask=[x10] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB35 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB36 regmask=[x1] minReg=1 last outOfOrder wt=91300.00> STORE_LCL_VAR BB36 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB38 regmask=[x10] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB39 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB40 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB41 regmask=[x1] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB43 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB44 regmask=[x10] minReg=1 last outOfOrder wt=91300.00> STORE_LCL_VAR BB44 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB44 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB45 regmask=[x10] minReg=1 wt=91300.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> STORE_LCL_VAR BB61 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB61 regmask=[x1] minReg=1 wt=91300.00> LCL_VAR BB62 regmask=[x1] minReg=1 last wt=91300.00> STORE_LCL_VAR BB78 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB103 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB245 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB246 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB246 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB200 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB200 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB201 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB201 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB206 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB207 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB208 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB209 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB209 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB214 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB219 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB219 regmask=[x12] minReg=1 wt=91300.00> LCL_VAR BB219 regmask=[x12] minReg=1 wt=91300.00> LCL_VAR BB220 regmask=[x12] minReg=1 spillAfter wt=91300.00> LCL_VAR BB230 regmask=[x4] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB231 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB233 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB233 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB239 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB240 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB236 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB236 regmask=[x4] minReg=1 spillAfter wt=91300.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB31 regmask=[x10] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB31 regmask=[x10] minReg=1 wt=91300.00> LCL_VAR BB32 regmask=[x1] minReg=1 last outOfOrder wt=91300.00> STORE_LCL_VAR BB32 regmask=[x2] minReg=1 spillAfter wt=91300.00> LCL_VAR BB194 regmask=[x4] minReg=1 outOfOrder wt=91300.00> LCL_VAR BB195 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB191 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB191 regmask=[x4] minReg=1 spillAfter wt=91300.00> LCL_VAR BB197 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB198 regmask=[x4] minReg=1 wt=91300.00> LCL_VAR BB199 regmask=[x4] minReg=1 last wt=91300.00> STORE_LCL_VAR BB199 regmask=[x4] minReg=1 spillAfter wt=91300.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V17 (Interval 16) STORE_LCL_VAR BB01 regmask=[x23] minReg=1 wt=1700.00> LCL_VAR BB01 regmask=[x23] minReg=1 wt=1700.00> LCL_VAR BB56 regmask=[x23] minReg=1 wt=1700.00> LCL_VAR BB60 regmask=[x23] minReg=1 wt=1700.00> LCL_VAR BB112 regmask=[x23] minReg=1 wt=1700.00> LCL_VAR BB223 regmask=[x23] minReg=1 wt=1700.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=200.00> --- V18 (Interval 17) STORE_LCL_VAR BB48 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB48 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB49 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB08 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB09 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB10 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB11 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB13 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB14 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB15 regmask=[x13] minReg=1 last wt=23700.00> STORE_LCL_VAR BB246 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB246 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB247 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB114 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB114 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB115 regmask=[x13] minReg=1 spillAfter wt=23700.00> LCL_VAR BB136 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB137 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB138 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB139 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB141 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB142 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB143 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB216 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB226 regmask=[x3] minReg=1 last copy fixed wt=23700.00> LCL_VAR BB228 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB229 regmask=[x1] minReg=1 last copy fixed wt=23700.00> LCL_VAR BB243 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB244 regmask=[x1] minReg=1 last copy fixed wt=23700.00> BB32 regmask=[x13] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x13] minReg=1 outOfOrder wt=23700.00> BB32 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=6400.00> STORE_LCL_VAR BB149 regmask=[x13] minReg=1 outOfOrder wt=23700.00> STORE_LCL_VAR BB155 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB156 regmask=[x13] minReg=1 wt=23700.00> LCL_VAR BB158 regmask=[x13] minReg=1 last wt=23700.00> LCL_VAR BB159 regmask=[x1] minReg=1 last copy fixed wt=23700.00> LCL_VAR BB196 regmask=[x13] minReg=1 spillAfter wt=23700.00> BB193 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> BB258 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=200.00> --- V19 --- V20 (Interval 18) STORE_LCL_VAR BB78 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB90 regmask=[x9] minReg=1 last wt=7000.00> STORE_LCL_VAR BB90 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB90 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB100 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB100 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB125 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB125 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB125 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB133 regmask=[x9] minReg=1 last wt=7000.00> STORE_LCL_VAR BB133 regmask=[x9] minReg=1 spillAfter wt=7000.00> BB244 regmask=[] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x9] minReg=1 outOfOrder wt=7000.00> LCL_VAR BB161 regmask=[x9] minReg=1 wt=7000.00> LCL_VAR BB161 regmask=[x9] minReg=1 spillAfter wt=7000.00> LCL_VAR BB169 regmask=[x9] minReg=1 last wt=7000.00> STORE_LCL_VAR BB169 regmask=[x9] minReg=1 spillAfter wt=7000.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V21 (Interval 19) STORE_LCL_VAR BB112 regmask=[x10] minReg=1 spillAfter wt=400.00> BB244 regmask=[] minReg=1 regOptional wt=200.00> LCL_VAR BB171 regmask=[x10] minReg=1 outOfOrder wt=400.00> BB173 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> STORE_LCL_VAR BB180 regmask=[x11] minReg=1 wt=400.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V22 (Interval 20) STORE_LCL_VAR BB07 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB48 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB35 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB39 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB41 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB43 regmask=[x9] minReg=1 wt=18400.00> LCL_VAR BB45 regmask=[x9] minReg=1 wt=18400.00> BB46 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> LCL_VAR BB31 regmask=[x9] minReg=1 outOfOrder wt=18400.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V23 --- V24 --- V25 --- V26 (Interval 21) STORE_LCL_VAR BB79 regmask=[x10] minReg=1 singleDefSpill wt=275.00> LCL_VAR BB79 regmask=[x10] minReg=1 wt=275.00> LCL_VAR BB81 regmask=[x10] minReg=1 spillAfter wt=275.00> LCL_VAR BB101 regmask=[x10] minReg=1 wt=275.00> LCL_VAR BB101 regmask=[x10] minReg=1 wt=275.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V27 (Interval 22) STORE_LCL_VAR BB79 regmask=[x13] minReg=1 spillAfter wt=1150.00> LCL_VAR BB100 regmask=[x13] minReg=1 wt=1150.00> LCL_VAR BB101 regmask=[x13] minReg=1 last wt=1150.00> STORE_LCL_VAR BB101 regmask=[x13] minReg=1 wt=1150.00> LCL_VAR BB101 regmask=[x13] minReg=1 wt=1150.00> LCL_VAR BB101 regmask=[x13] minReg=1 wt=1150.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V28 (Interval 23) STORE_LCL_VAR BB79 regmask=[x14] minReg=1 wt=1650.00> STORE_LCL_VAR BB81 regmask=[x14] minReg=1 wt=1650.00> LCL_VAR BB82 regmask=[x14] minReg=1 spillAfter wt=1650.00> LCL_VAR BB100 regmask=[x14] minReg=1 wt=1650.00> LCL_VAR BB102 regmask=[x14] minReg=1 last wt=1650.00> STORE_LCL_VAR BB102 regmask=[x14] minReg=1 wt=1650.00> LCL_VAR BB102 regmask=[x14] minReg=1 wt=1650.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V29 (Interval 24) STORE_LCL_VAR BB79 regmask=[x12] minReg=1 singleDefSpill wt=250.00> LCL_VAR BB79 regmask=[x12] minReg=1 spillAfter wt=250.00> LCL_VAR BB100 regmask=[x12] minReg=1 wt=250.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V30 (Interval 25) STORE_LCL_VAR BB82 regmask=[x15] minReg=1 wt=1000.00> LCL_VAR BB85 regmask=[x15] minReg=1 wt=1000.00> LCL_VAR BB89 regmask=[x15] minReg=1 spillAfter wt=1000.00> STORE_LCL_VAR BB101 regmask=[x0] minReg=1 wt=1000.00> LCL_VAR BB102 regmask=[x15] minReg=1 outOfOrder wt=1000.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V31 (Interval 26) STORE_LCL_VAR BB85 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0] minReg=1 last wt=150.00> --- V32 (Interval 27) STORE_LCL_VAR BB85 regmask=[xip0] minReg=1 singleDefSpill wt=250.00> LCL_VAR BB85 regmask=[xip0] minReg=1 spillAfter wt=250.00> LCL_VAR BB102 regmask=[xip0] minReg=1 wt=250.00> BB102 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=400.00> --- V33 (Interval 28) STORE_LCL_VAR BB91 regmask=[x3] minReg=1 singleDefSpill wt=500.00> LCL_VAR BB91 regmask=[x3] minReg=1 wt=500.00> LCL_VAR BB91 regmask=[x3] minReg=1 spillAfter wt=500.00> LCL_VAR BB95 regmask=[x0] minReg=1 reload wt=500.00> LCL_VAR BB95 regmask=[x0] minReg=1 last wt=500.00> --- V34 (Interval 29) STORE_LCL_VAR BB112 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB246 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB200 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB207 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB209 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB214 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB220 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB231 regmask=[x24] minReg=1 wt=6700.00> LCL_VAR BB240 regmask=[x24] minReg=1 wt=6700.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB195 regmask=[x24] minReg=1 outOfOrder wt=6700.00> LCL_VAR BB198 regmask=[x24] minReg=1 wt=6700.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V35 --- V36 (Interval 30) STORE_LCL_VAR BB112 regmask=[x0] minReg=1 wt=3200.00> LCL_VAR BB118 regmask=[x0] minReg=1 wt=3200.00> LCL_VAR BB120 regmask=[x0] minReg=1 last wt=3200.00> STORE_LCL_VAR BB120 regmask=[x12] minReg=1 spillAfter wt=3200.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 outOfOrder regOptional wt=200.00> LCL_VAR BB150 regmask=[x0] minReg=1 outOfOrder wt=3200.00> LCL_VAR BB154 regmask=[x0] minReg=1 last wt=3200.00> STORE_LCL_VAR BB154 regmask=[x0] minReg=1 spillAfter wt=3200.00> LCL_VAR BB173 regmask=[x0] minReg=1 spillAfter wt=3200.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V37 (Interval 31) STORE_LCL_VAR BB205 regmask=[x11] minReg=1 wt=600.00> STORE_LCL_VAR BB210 regmask=[x11] minReg=1 wt=600.00> LCL_VAR BB226 regmask=[x5] minReg=1 last copy fixed wt=600.00> --- V38 (Interval 32) STORE_LCL_VAR BB205 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB218 regmask=[x14] minReg=1 last wt=2400.00> STORE_LCL_VAR BB218 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB221 regmask=[x14] minReg=1 wt=2400.00> STORE_LCL_VAR BB222 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB226 regmask=[x4] minReg=1 last copy fixed wt=2400.00> --- V39 --- V40 --- V41 --- V42 --- V43 (Interval 33) STORE_LCL_VAR BB03 regmask=[x2] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x2] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x2] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x2] minReg=1 last fixed wt=250.00> --- V44 (Interval 34) STORE_LCL_VAR BB66 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x3] minReg=1 last wt=200.00> --- V45 (Interval 35) STORE_LCL_VAR BB66 regmask=[x4] minReg=1 wt=200.00> LCL_VAR BB66 regmask=[x4] minReg=1 last wt=200.00> --- V46 (Interval 36) STORE_LCL_VAR BB74 regmask=[x2] minReg=1 wt=100.00> LCL_VAR BB74 regmask=[x2] minReg=1 last wt=100.00> --- V47 --- V48 --- V49 (Interval 37) STORE_LCL_VAR BB246 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB246 regmask=[x11] minReg=1 last wt=2400.00> --- V50 (Interval 38) STORE_LCL_VAR BB246 regmask=[x13] minReg=1 wt=1600.00> LCL_VAR BB246 regmask=[x13] minReg=1 last wt=1600.00> --- V51 (Interval 39) STORE_LCL_VAR BB201 regmask=[x4] minReg=1 wt=800.00> LCL_VAR BB201 regmask=[x4] minReg=1 last wt=800.00> --- V52 (Interval 40) STORE_LCL_VAR BB233 regmask=[x4] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x4] minReg=1 last wt=800.00> --- V53 (Interval 41) STORE_LCL_VAR BB236 regmask=[x4] minReg=1 wt=3200.00> LCL_VAR BB236 regmask=[x4] minReg=1 last wt=3200.00> --- V54 (Interval 42) STORE_LCL_VAR BB219 regmask=[x4] minReg=1 wt=6400.00> LCL_VAR BB219 regmask=[x4] minReg=1 last wt=6400.00> --- V55 (Interval 43) STORE_LCL_VAR BB224 regmask=[x4] minReg=1 wt=600.00> STORE_LCL_VAR BB225 regmask=[x4] minReg=1 wt=600.00> LCL_VAR BB226 regmask=[x2] minReg=1 last copy fixed wt=600.00> --- V56 (Interval 44) STORE_LCL_VAR BB154 regmask=[x11] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x11] minReg=1 wt=1200.00> LCL_VAR BB154 regmask=[x11] minReg=1 last wt=1200.00> --- V57 (Interval 45) STORE_LCL_VAR BB152 regmask=[x11] minReg=1 wt=800.00> STORE_LCL_VAR BB153 regmask=[x11] minReg=1 wt=800.00> STORE_LCL_VAR BB154 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB155 regmask=[x11] minReg=1 last regOptional wt=800.00> --- V58 (Interval 46) STORE_LCL_VAR BB147 regmask=[x13] minReg=1 wt=600.00> STORE_LCL_VAR BB148 regmask=[x13] minReg=1 wt=600.00> LCL_VAR BB149 regmask=[x13] minReg=1 last regOptional wt=600.00> --- V59 (Interval 47) STORE_LCL_VAR BB191 regmask=[x4] minReg=1 wt=3200.00> LCL_VAR BB191 regmask=[x4] minReg=1 last wt=3200.00> --- V60 --- V61 (Interval 48) STORE_LCL_VAR BB120 regmask=[x0] minReg=1 wt=3200.00> LCL_VAR BB120 regmask=[x0] minReg=1 last wt=3200.00> --- V62 --- V63 (Interval 49) STORE_LCL_VAR BB119 regmask=[x14] minReg=1 wt=2400.00> STORE_LCL_VAR BB120 regmask=[x14] minReg=1 wt=2400.00> LCL_VAR BB121 regmask=[x14] minReg=1 last regOptional wt=2400.00> --- V64 (Interval 50) STORE_LCL_VAR BB82 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB83 regmask=[x0] minReg=1 last wt=150.00> LCL_VAR BB84 regmask=[x0] minReg=1 last wt=150.00> --- V65 (Interval 51) STORE_LCL_VAR BB83 regmask=[x0] minReg=1 wt=150.00> STORE_LCL_VAR BB84 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x0] minReg=1 last wt=150.00> --- V66 (Interval 52) STORE_LCL_VAR BB83 regmask=[x11] minReg=1 wt=150.00> STORE_LCL_VAR BB84 regmask=[x11] minReg=1 wt=150.00> LCL_VAR BB85 regmask=[x11] minReg=1 last wt=150.00> --- V67 (Interval 53) STORE_LCL_VAR BB85 regmask=[xip0] minReg=1 wt=100.00> LCL_VAR BB85 regmask=[xip0] minReg=1 last wt=100.00> --- V68 --- V69 (Interval 54) STORE_LCL_VAR BB57 regmask=[x1] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x1] minReg=1 wt=2400.00> LCL_VAR BB57 regmask=[x1] minReg=1 last wt=2400.00> --- V70 (Interval 55) STORE_LCL_VAR BB58 regmask=[x1] minReg=1 wt=800.00> STORE_LCL_VAR BB59 regmask=[x1] minReg=1 wt=800.00> LCL_VAR BB60 regmask=[x1] minReg=1 last fixed wt=800.00> --- V71 (Interval 56) STORE_LCL_VAR BB48 regmask=[x1] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x1] minReg=1 wt=9600.00> LCL_VAR BB48 regmask=[x1] minReg=1 last wt=9600.00> --- V72 (Interval 57) STORE_LCL_VAR BB48 regmask=[x13] minReg=1 wt=6400.00> LCL_VAR BB48 regmask=[x13] minReg=1 last wt=6400.00> --- V73 (Interval 58) STORE_LCL_VAR BB44 regmask=[x10] minReg=1 wt=25600.00> LCL_VAR BB44 regmask=[x10] minReg=1 last wt=25600.00> --- V74 (Interval 59) STORE_LCL_VAR BB32 regmask=[x1] minReg=1 wt=25600.00> LCL_VAR BB32 regmask=[x1] minReg=1 last wt=25600.00> --- V75 --- V76 (Interval 60) STORE_LCL_VAR BB01 regmask=[x0] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0] minReg=1 wt=600.00> LCL_VAR BB01 regmask=[x0] minReg=1 last wt=600.00> --- V77 --- V78 --- V79 --- V80 --- V81 --- V82 --- V83 (Interval 61) STORE_LCL_VAR BB95 regmask=[x2] minReg=1 wt=800.00> LCL_VAR BB95 regmask=[x2] minReg=1 last wt=800.00> --- V84 --- V85 --- V86 (Interval 62) STORE_LCL_VAR BB106 regmask=[x11] minReg=1 wt=500.00> LCL_VAR BB106 regmask=[x11] minReg=1 wt=500.00> LCL_VAR BB107 regmask=[x11] minReg=1 wt=500.00> LCL_VAR BB108 regmask=[x11] minReg=1 last wt=500.00> LCL_VAR BB111 regmask=[x1] minReg=1 last copy fixed wt=500.00> --- V87 (Interval 63) STORE_LCL_VAR BB107 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB107 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB108 regmask=[x0] minReg=1 last wt=250.00> --- V88 (Interval 64) STORE_LCL_VAR BB108 regmask=[x10] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x10] minReg=1 wt=300.00> LCL_VAR BB108 regmask=[x10] minReg=1 last wt=300.00> --- V89 --- V90 --- V91 (Interval 65) STORE_LCL_VAR BB121 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB121 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB122 regmask=[x14] minReg=1 last wt=4000.00> --- V92 (Interval 66) STORE_LCL_VAR BB121 regmask=[x11] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x11] minReg=1 last wt=4800.00> LCL_VAR BB123 regmask=[x1] minReg=1 last copy fixed wt=4800.00> --- V93 (Interval 67) STORE_LCL_VAR BB122 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB122 regmask=[x12] minReg=1 last wt=4800.00> --- V94 --- V95 (Interval 68) STORE_LCL_VAR BB127 regmask=[x11] minReg=1 wt=8000.00> LCL_VAR BB127 regmask=[x11] minReg=1 wt=8000.00> LCL_VAR BB129 regmask=[x11] minReg=1 wt=8000.00> LCL_VAR BB130 regmask=[x11] minReg=1 last wt=8000.00> LCL_VAR BB132 regmask=[x1] minReg=1 last copy fixed wt=8000.00> --- V96 (Interval 69) STORE_LCL_VAR BB129 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB129 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x14] minReg=1 wt=4000.00> LCL_VAR BB130 regmask=[x14] minReg=1 last wt=4000.00> --- V97 (Interval 70) STORE_LCL_VAR BB130 regmask=[x15] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x15] minReg=1 wt=4800.00> LCL_VAR BB130 regmask=[x15] minReg=1 last wt=4800.00> --- V98 --- V99 (Interval 71) STORE_LCL_VAR BB157 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB157 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB158 regmask=[x11] minReg=1 last wt=1000.00> --- V100 (Interval 72) STORE_LCL_VAR BB158 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB158 regmask=[x14] minReg=1 last wt=1200.00> --- V101 --- V102 (Interval 73) STORE_LCL_VAR BB163 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB163 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB165 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB166 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB166 regmask=[x11] minReg=1 last wt=2400.00> LCL_VAR BB168 regmask=[x1] minReg=1 last copy fixed wt=2400.00> --- V103 (Interval 74) STORE_LCL_VAR BB165 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB165 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB166 regmask=[x13] minReg=1 last wt=1000.00> --- V104 (Interval 75) STORE_LCL_VAR BB166 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB166 regmask=[x14] minReg=1 last wt=1200.00> --- V105 --- V106 (Interval 76) STORE_LCL_VAR BB174 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB174 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB176 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB177 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB177 regmask=[x11] minReg=1 last wt=2400.00> LCL_VAR BB179 regmask=[x1] minReg=1 last copy fixed wt=2400.00> --- V107 (Interval 77) STORE_LCL_VAR BB176 regmask=[x10] minReg=1 wt=1000.00> LCL_VAR BB176 regmask=[x10] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x10] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x10] minReg=1 wt=1000.00> LCL_VAR BB177 regmask=[x10] minReg=1 last wt=1000.00> --- V108 (Interval 78) STORE_LCL_VAR BB177 regmask=[x13] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x13] minReg=1 wt=1200.00> LCL_VAR BB177 regmask=[x13] minReg=1 last wt=1200.00> --- V109 --- V110 (Interval 79) STORE_LCL_VAR BB144 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB181 regmask=[x11] minReg=1 wt=2400.00> BB182 regmask=[x11] minReg=1 regOptional wt=200.00> LCL_VAR BB182 regmask=[x11] minReg=1 outOfOrder wt=2400.00> LCL_VAR BB183 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB183 regmask=[x11] minReg=1 last wt=2400.00> LCL_VAR BB185 regmask=[x1] minReg=1 last copy fixed wt=2400.00> --- V111 (Interval 80) STORE_LCL_VAR BB182 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB182 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB183 regmask=[x13] minReg=1 last wt=1000.00> --- V112 (Interval 81) STORE_LCL_VAR BB183 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB183 regmask=[x14] minReg=1 last wt=1200.00> --- V113 --- V114 (Interval 82) STORE_LCL_VAR BB186 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB186 regmask=[x11] minReg=1 wt=2400.00> BB187 regmask=[x11] minReg=1 regOptional wt=200.00> LCL_VAR BB187 regmask=[x11] minReg=1 outOfOrder wt=2400.00> LCL_VAR BB188 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB188 regmask=[x11] minReg=1 last wt=2400.00> LCL_VAR BB190 regmask=[x1] minReg=1 last copy fixed wt=2400.00> --- V115 (Interval 83) STORE_LCL_VAR BB187 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB187 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB188 regmask=[x13] minReg=1 last wt=1000.00> --- V116 (Interval 84) STORE_LCL_VAR BB188 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB188 regmask=[x14] minReg=1 last wt=1200.00> --- V117 --- V118 (Interval 85) STORE_LCL_VAR BB191 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB191 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB192 regmask=[x11] minReg=1 last wt=4000.00> --- V119 (Interval 86) STORE_LCL_VAR BB191 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x14] minReg=1 last wt=4800.00> LCL_VAR BB193 regmask=[x1] minReg=1 last copy fixed wt=4800.00> --- V120 (Interval 87) STORE_LCL_VAR BB192 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB192 regmask=[x12] minReg=1 last wt=4800.00> --- V121 --- V122 (Interval 88) STORE_LCL_VAR BB201 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB201 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB203 regmask=[x11] minReg=1 last wt=1000.00> --- V123 (Interval 89) STORE_LCL_VAR BB201 regmask=[x13] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x13] minReg=1 last wt=1200.00> LCL_VAR BB204 regmask=[x1] minReg=1 last copy fixed wt=1200.00> --- V124 (Interval 90) STORE_LCL_VAR BB203 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB203 regmask=[x14] minReg=1 last wt=1200.00> --- V125 --- V126 (Interval 91) STORE_LCL_VAR BB215 regmask=[x14] minReg=1 wt=1000.00> LCL_VAR BB215 regmask=[x14] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x14] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x14] minReg=1 wt=1000.00> LCL_VAR BB216 regmask=[x14] minReg=1 last wt=1000.00> --- V127 (Interval 92) STORE_LCL_VAR BB216 regmask=[x11] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x11] minReg=1 wt=1200.00> LCL_VAR BB216 regmask=[x11] minReg=1 last wt=1200.00> --- V128 --- V129 (Interval 93) STORE_LCL_VAR BB227 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB227 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB228 regmask=[x11] minReg=1 last wt=1000.00> --- V130 (Interval 94) STORE_LCL_VAR BB228 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB228 regmask=[x14] minReg=1 last wt=1200.00> --- V131 --- V132 (Interval 95) STORE_LCL_VAR BB233 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB233 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x13] minReg=1 wt=1000.00> LCL_VAR BB234 regmask=[x13] minReg=1 last wt=1000.00> --- V133 (Interval 96) STORE_LCL_VAR BB233 regmask=[x11] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x11] minReg=1 last wt=1200.00> LCL_VAR BB235 regmask=[x1] minReg=1 last copy fixed wt=1200.00> --- V134 (Interval 97) STORE_LCL_VAR BB234 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB234 regmask=[x14] minReg=1 last wt=1200.00> --- V135 --- V136 (Interval 98) STORE_LCL_VAR BB236 regmask=[x13] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x13] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x13] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x13] minReg=1 wt=4000.00> LCL_VAR BB237 regmask=[x13] minReg=1 last wt=4000.00> --- V137 (Interval 99) STORE_LCL_VAR BB236 regmask=[x11] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x11] minReg=1 last wt=4800.00> LCL_VAR BB238 regmask=[x1] minReg=1 last copy fixed wt=4800.00> --- V138 (Interval 100) STORE_LCL_VAR BB237 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB237 regmask=[x14] minReg=1 last wt=4800.00> --- V139 --- V140 (Interval 101) STORE_LCL_VAR BB242 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB242 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x11] minReg=1 wt=1000.00> LCL_VAR BB243 regmask=[x11] minReg=1 last wt=1000.00> --- V141 (Interval 102) STORE_LCL_VAR BB243 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB243 regmask=[x14] minReg=1 last wt=1200.00> --- V142 --- V143 (Interval 103) STORE_LCL_VAR BB78 regmask=[x6] minReg=1 spillAfter wt=1800.00> LCL_VAR BB95 regmask=[x1] minReg=1 last reload fixed wt=1800.00> STORE_LCL_VAR BB95 regmask=[x2] minReg=1 wt=1800.00> LCL_VAR BB100 regmask=[x6] minReg=1 spillAfter outOfOrder wt=1800.00> LCL_VAR BB125 regmask=[x6] minReg=1 spillAfter wt=1800.00> BB244 regmask=[] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x6] minReg=1 spillAfter outOfOrder wt=1800.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V144 (Interval 104) STORE_LCL_VAR BB78 regmask=[x8] minReg=1 wt=2600.00> LCL_VAR BB90 regmask=[x8] minReg=1 wt=2600.00> LCL_VAR BB91 regmask=[x8] minReg=1 spillAfter wt=2600.00> LCL_VAR BB91 regmask=[x4] minReg=1 reload wt=2600.00> LCL_VAR BB95 regmask=[x4] minReg=1 last regOptional wt=2600.00> STORE_LCL_VAR BB95 regmask=[x3] minReg=1 wt=2600.00> LCL_VAR BB100 regmask=[x8] minReg=1 spillAfter outOfOrder wt=2600.00> LCL_VAR BB125 regmask=[x8] minReg=1 spillAfter wt=2600.00> BB244 regmask=[] minReg=1 regOptional wt=200.00> LCL_VAR BB161 regmask=[x8] minReg=1 spillAfter outOfOrder wt=2600.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V145 --- V146 --- V147 (Interval 105) STORE_LCL_VAR BB01 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB02 regmask=[x0] minReg=1 last wt=200.00> LCL_VAR BB05 regmask=[x0] minReg=1 last wt=200.00> --- V148 (Interval 106) STORE_LCL_VAR BB01 regmask=[x1] minReg=1 wt=200.00> LCL_VAR BB02 regmask=[x1] minReg=1 last wt=200.00> LCL_VAR BB05 regmask=[x1] minReg=1 last wt=200.00> --- V149 (Interval 107) STORE_LCL_VAR BB03 regmask=[x0] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x0] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x0] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x0] minReg=1 last fixed wt=250.00> --- V150 (Interval 108) STORE_LCL_VAR BB03 regmask=[x1] minReg=1 wt=250.00> STORE_LCL_VAR BB04 regmask=[x1] minReg=1 wt=250.00> STORE_LCL_VAR BB05 regmask=[x1] minReg=1 wt=250.00> LCL_VAR BB06 regmask=[x1] minReg=1 last fixed wt=250.00> --- V151 (Interval 109) STORE_LCL_VAR BB78 regmask=[x6] minReg=1 wt=200.00> LCL_VAR BB78 regmask=[x6] minReg=1 last wt=200.00> --- V152 --- V153 --- V154 --- V155 (Interval 110) STORE_LCL_VAR BB02 regmask=[x0] minReg=1 wt=150.00> LCL_VAR BB03 regmask=[x0] minReg=1 last wt=150.00> LCL_VAR BB04 regmask=[x0] minReg=1 last wt=150.00> --- V156 (Interval 111) STORE_LCL_VAR BB02 regmask=[x1] minReg=1 wt=150.00> LCL_VAR BB03 regmask=[x1] minReg=1 last wt=150.00> LCL_VAR BB04 regmask=[x1] minReg=1 last wt=150.00> --- V157 (Interval 112) STORE_LCL_VAR BB07 regmask=[x9] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x9] minReg=1 wt=2400.00> LCL_VAR BB07 regmask=[x9] minReg=1 last wt=2400.00> --- V158 --- V159 (Interval 113) STORE_LCL_VAR BB91 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x0] minReg=1 last wt=400.00> --- V160 (Interval 114) STORE_LCL_VAR BB91 regmask=[x2] minReg=1 wt=400.00> LCL_VAR BB91 regmask=[x2] minReg=1 last wt=400.00> --- V161 (Interval 115) STORE_LCL_VAR BB91 regmask=[x0] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x0] minReg=1 last fixed wt=400.00> --- V162 --- V163 (Interval 116) STORE_LCL_VAR BB95 regmask=[x1] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x1] minReg=1 last wt=400.00> --- V164 (Interval 117) STORE_LCL_VAR BB95 regmask=[x4] minReg=1 wt=400.00> LCL_VAR BB95 regmask=[x4] minReg=1 last wt=400.00> --- V165 (Interval 118) STORE_LCL_VAR BB112 regmask=[x24] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x24] minReg=1 wt=300.00> LCL_VAR BB112 regmask=[x24] minReg=1 last wt=300.00> --- V166 --- V167 (Interval 119) STORE_LCL_VAR BB01 regmask=[x23] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x23] minReg=1 last wt=400.00> --- V168 (Interval 120) STORE_LCL_VAR BB07 regmask=[x9] minReg=1 wt=3200.00> LCL_VAR BB07 regmask=[x9] minReg=1 last wt=3200.00> --- V169 (Interval 121) STORE_LCL_VAR BB112 regmask=[x24] minReg=1 wt=400.00> LCL_VAR BB112 regmask=[x24] minReg=1 last wt=400.00> --- V170 --- V171 (Interval 122) STORE_LCL_VAR BB31 regmask=[x0] minReg=1 wt=19200.00> LCL_VAR BB31 regmask=[x0] minReg=1 wt=19200.00> BB32 regmask=[x0] minReg=1 regOptional wt=6400.00> LCL_VAR BB32 regmask=[x0] minReg=1 last wt=19200.00> --- V172 (Interval 123) STORE_LCL_VAR BB195 regmask=[x14] minReg=1 wt=6000.00> LCL_VAR BB195 regmask=[x14] minReg=1 wt=6000.00> LCL_VAR BB196 regmask=[x14] minReg=1 wt=6000.00> LCL_VAR BB191 regmask=[x14] minReg=1 last wt=6000.00> STORE_LCL_VAR BB198 regmask=[x14] minReg=1 wt=6000.00> LCL_VAR BB198 regmask=[x14] minReg=1 last wt=6000.00> --- V173 (Interval 124) STORE_LCL_VAR BB240 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB240 regmask=[x11] minReg=1 wt=4000.00> LCL_VAR BB236 regmask=[x11] minReg=1 last wt=4000.00> --- V174 (Interval 125) STORE_LCL_VAR BB35 regmask=[x1] minReg=1 wt=5600.00> LCL_VAR BB35 regmask=[x1] minReg=1 last wt=5600.00> STORE_LCL_VAR BB39 regmask=[x1] minReg=1 wt=5600.00> LCL_VAR BB39 regmask=[x1] minReg=1 last wt=5600.00> STORE_LCL_VAR BB41 regmask=[x0] minReg=1 wt=5600.00> LCL_VAR BB41 regmask=[x0] minReg=1 wt=5600.00> LCL_VAR BB42 regmask=[x0] minReg=1 last wt=5600.00> --- V175 (Interval 126) STORE_LCL_VAR BB231 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB231 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB232 regmask=[x11] minReg=1 wt=800.00> LCL_VAR BB233 regmask=[x11] minReg=1 last wt=800.00> --- V176 (Interval 127) STORE_LCL_VAR BB200 regmask=[x13] minReg=1 wt=1600.00> LCL_VAR BB200 regmask=[x13] minReg=1 wt=1600.00> BB201 regmask=[x13] minReg=1 regOptional wt=200.00> LCL_VAR BB201 regmask=[x13] minReg=1 last outOfOrder wt=1600.00> STORE_LCL_VAR BB207 regmask=[x12] minReg=1 wt=1600.00> LCL_VAR BB207 regmask=[x12] minReg=1 last wt=1600.00> STORE_LCL_VAR BB209 regmask=[x12] minReg=1 wt=1600.00> LCL_VAR BB209 regmask=[x12] minReg=1 wt=1600.00> LCL_VAR BB213 regmask=[x12] minReg=1 last wt=1600.00> --- V177 (Interval 128) STORE_LCL_VAR BB118 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB118 regmask=[x11] minReg=1 wt=2400.00> LCL_VAR BB120 regmask=[x11] minReg=1 last wt=2400.00> --- V178 (Interval 129) STORE_LCL_VAR BB74 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x3] minReg=1 wt=200.00> LCL_VAR BB74 regmask=[x3] minReg=1 last wt=200.00> --- V179 (Interval 130) STORE_LCL_VAR BB01 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB01 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB47 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB35 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB38 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB40 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB44 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB245 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB200 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB206 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB208 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB219 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB230 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB239 regmask=[x25] minReg=1 wt=28400.00> BB244 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> LCL_VAR BB31 regmask=[x25] minReg=1 outOfOrder wt=28400.00> LCL_VAR BB194 regmask=[x25] minReg=1 wt=28400.00> LCL_VAR BB197 regmask=[x25] minReg=1 wt=28400.00> BB180 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=200.00> --- V180 (Interval 131) STORE_LCL_VAR BB01 regmask=[x24] minReg=1 wt=1500.00> LCL_VAR BB01 regmask=[x24] minReg=1 wt=1500.00> LCL_VAR BB07 regmask=[x24] minReg=1 wt=1500.00> LCL_VAR BB61 regmask=[x0] minReg=1 copy fixed wt=1500.00> LCL_VAR BB112 regmask=[x24] minReg=1 last wt=1500.00> BB29 regmask=[x0-xip0 x19-x28] minReg=1 regOptional wt=800.00> --- V181 (Interval 132) STORE_LCL_VAR BB129 regmask=[x12] minReg=1 wt=2400.00> LCL_VAR BB129 regmask=[x12] minReg=1 wt=2400.00> LCL_VAR BB130 regmask=[x12] minReg=1 last wt=2400.00> --- V182 (Interval 133) STORE_LCL_VAR BB09 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB09 regmask=[x14] minReg=1 wt=4800.00> LCL_VAR BB255 regmask=[x14] minReg=1 last regOptional wt=4800.00> --- V183 (Interval 134) STORE_LCL_VAR BB10 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB10 regmask=[x12] minReg=1 wt=4800.00> LCL_VAR BB256 regmask=[x12] minReg=1 last regOptional wt=4800.00> --- V184 (Interval 135) STORE_LCL_VAR BB137 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB137 regmask=[x14] minReg=1 wt=1200.00> LCL_VAR BB257 regmask=[x14] minReg=1 last regOptional wt=1200.00> --- V185 (Interval 136) STORE_LCL_VAR BB138 regmask=[x12] minReg=1 wt=1200.00> LCL_VAR BB138 regmask=[x12] minReg=1 wt=1200.00> LCL_VAR BB258 regmask=[x12] minReg=1 last regOptional wt=1200.00> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V20 V21 V22 V26 V27 V28 V29 V30 V32 V33 V34 V36 V37 V38 V43 V55 V57 V58 V63 V64 V65 V66 V70 V86 V87 V91 V92 V95 V96 V99 V102 V103 V106 V107 V110 V111 V114 V115 V118 V119 V122 V123 V126 V129 V132 V133 V136 V137 V140 V143 V144 V147 V148 V149 V150 V155 V156 V161 V171 V172 V173 V174 V175 V176 V177 V179 V180 V181 V182 V183 V184 V185} Has Critical Edges Prior to Resolution BB01 use: {V01 V02} def: {V11 V17 V76 V147 V148 V167 V179 V180} in: {V00 V01 V02 V03} out: {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} Var=Reg beg of BB01: V00=x19 V03=x20 V01=x21 Var=Reg end of BB01: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V147=x0 V148=x1 BB02 use: {V01 V147 V148} def: {V155 V156} in: {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} out: {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} Var=Reg beg of BB02: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V147=x0 V148=x1 Var=Reg end of BB02: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V155=x0 V156=x1 BB03 use: {V155 V156} def: {V43 V149 V150} in: {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} out: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} Var=Reg beg of BB03: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V155=x0 V156=x1 Var=Reg end of BB03: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V149=x0 V43=x2 V150=x1 BB04 use: {V155 V156} def: {V43 V149 V150} in: {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} out: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} Var=Reg beg of BB04: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V155=x0 V156=x1 Var=Reg end of BB04: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V149=x0 V43=x2 V150=x1 BB05 use: {V147 V148} def: {V43 V149 V150} in: {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} out: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} Var=Reg beg of BB05: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V147=x0 V148=x1 Var=Reg end of BB05: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V149=x0 V43=x2 V150=x1 BB06 use: {V43 V149 V150} def: {V15} in: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} out: {V00 V01 V02 V03 V11 V15 V17 V179 V180} Var=Reg beg of BB06: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V149=x0 V43=x2 V150=x1 Var=Reg end of BB06: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB07 use: {V15 V180} def: {V04 V05 V06 V07 V09 V10 V12 V13 V16 V22 V157 V168} in: {V00 V01 V02 V03 V11 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB07: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB07: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB08 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Var=Reg beg of BB08: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB08: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB09 use: {V18} def: {V182} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V182} Var=Reg beg of BB09: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB09: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V182=x14 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB255 use: {V182} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V182} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Var=Reg beg of BB255: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V182=x14 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB255: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB10 use: {V18} def: {V183} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V183} Var=Reg beg of BB10: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB10: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V183=x12 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB256 use: {V183} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180 V183} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB256: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V183=x12 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB256: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB11 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB11: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB11: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB12 use: {} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB12: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB12: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB13 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Var=Reg beg of BB13: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB13: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB14 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Var=Reg beg of BB14: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB14: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB15 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB15: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB15: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB16 use: {V13} def: {V13} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB16: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB16: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB17 use: {V04} def: {V04} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB17: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB17: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB18 use: {V06} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB18: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB18: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V06=x3 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB19 use: {V04} def: {V06} in: {V00 V01 V02 V03 V04 V05 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB19: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB19: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V06=x3 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB20 use: {V04} def: {V04 V07} in: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB20: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V06=x3 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB20: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V06=x3 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V07=x2 V15=x26 V17=x23 V180=x24 BB21 use: {V05} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB21: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB21: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB22 use: {V04} def: {V05} in: {V00 V01 V02 V03 V04 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB22: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB22: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB23 use: {V04 V05} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB23: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB23: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB24 use: {V10} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB24: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB24: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB26 use: {V04 V10} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB26: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB26: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB27 use: {V11} def: {V11} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB27: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB27: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB28 use: {} def: {V12} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB28: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB28: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB29 use: {V04} def: {V10 V11} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB29: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB29: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB30 use: {V13} def: {V13} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB30: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB30: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB31 use: {V16 V22 V179} def: {V171} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} Var=Reg beg of BB31: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB31: V16=x10 V00=x19 V179=x25 V18=x13 V171=x0 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB32 use: {V16 V18 V171} def: {V16 V74} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Var=Reg beg of BB32: V16=x1 V00=x19 V179=x25 V18=x13 V171=x0 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB32: V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB34 use: {} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB34: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB34: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB35 use: {V16 V22 V179} def: {V174} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB35: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB35: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB36 use: {V16} def: {V16} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB36: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB36: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB38 use: {V16 V179} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB38: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB38: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB39 use: {V16 V22} def: {V174} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB39: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB39: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB40 use: {V16 V179} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB40: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB40: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB41 use: {V16 V22} def: {V174} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V174 V179 V180} Var=Reg beg of BB41: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB41: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V174=x0 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB42 use: {V174} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V174 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB42: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V174=x0 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB42: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB43 use: {V16 V22} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB43: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB43: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB44 use: {V16 V179} def: {V16 V73} in: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB44: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB44: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB45 use: {V16 V22} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB45: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB45: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB46 use: {} def: {V09} in: {V00 V01 V02 V03 V04 V05 V06 V07 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB46: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB46: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB47 use: {V16 V179} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Var=Reg beg of BB47: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB47: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB48 use: {V16 V22} def: {V16 V18 V71 V72} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Var=Reg beg of BB48: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB48: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB49 use: {V18} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Var=Reg beg of BB49: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB49: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB50 use: {V05} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} Var=Reg beg of BB50: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB50: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB51 use: {V04} def: {V05} in: {V00 V01 V02 V03 V04 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} Var=Reg beg of BB51: V00=x19 V179=x25 V04=x27 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB51: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB52 use: {V10} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} Var=Reg beg of BB52: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB52: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB53 use: {V05 V10} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} Var=Reg beg of BB53: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB53: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB54 use: {V11 V13} def: {V13} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} Var=Reg beg of BB54: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB54: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB55 use: {} def: {V12} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} Var=Reg beg of BB55: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB55: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB56 use: {V17} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} Var=Reg beg of BB56: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB56: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB57 use: {V01 V09 V13} def: {V69} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V13 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} Var=Reg beg of BB57: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB57: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB58 use: {V01 V04 V05} def: {V70} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70 V179 V180} Var=Reg beg of BB58: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB58: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V70=x1 BB59 use: {V04} def: {V70} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70 V179 V180} Var=Reg beg of BB59: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB59: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V70=x1 BB60 use: {V01 V17 V70} def: {} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V70 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} Var=Reg beg of BB60: V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V70=x1 Var=Reg end of BB60: V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB61 use: {V02 V15 V180} def: {V16} in: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V17 V179 V180} out: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V12 V15 V16 V17 V179 V180} Var=Reg beg of BB61: V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB61: V16=x1 V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB62 use: {V16} def: {V15} in: {V00 V01 V02 V03 V11 V16 V17 V179 V180} out: {V00 V01 V02 V03 V11 V15 V17 V179 V180} Var=Reg beg of BB62: V16=x1 V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 Var=Reg end of BB62: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB63 use: {V01} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} Var=Reg beg of BB63: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB63: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB64 use: {V01} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} Var=Reg beg of BB64: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB64: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB65 use: {V01} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} Var=Reg beg of BB65: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB65: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB66 use: {V05 V06 V07 V09} def: {V06 V07 V44 V45} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} Var=Reg beg of BB66: V00=x19 V179=x25 V04=x27 V05=x28 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB66: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB73 use: {V05} def: {V08 V14} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V179 V180} Var=Reg beg of BB73: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB73: V00=x19 V179=x25 V04=x27 V05=x28 V08=x2 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB74 use: {V01 V05} def: {V08 V14 V46 V178} in: {V00 V01 V03 V04 V05 V06 V07 V09 V12 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V179 V180} Var=Reg beg of BB74: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB74: V00=x19 V179=x25 V04=x27 V05=x28 V08=x2 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB78 use: {V03 V12 V15} def: {V16 V20 V143 V144 V151 V152} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V17 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} Var=Reg beg of BB78: V00=x19 V179=x25 V04=x27 V05=x28 V08=x2 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB78: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB79 use: {V03} def: {V26 V27 V28 V29} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144 V179 V180} Var=Reg beg of BB79: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB79: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V26=x10 BB81 use: {V26} def: {V28} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V29 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144 V179 V180} Var=Reg beg of BB81: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 Var=Reg end of BB81: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 BB82 use: {V08 V14 V28} def: {V30 V64} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144 V179 V180} Var=Reg beg of BB82: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V26=x10 Var=Reg end of BB82: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V64=x0 BB83 use: {V64} def: {V65 V66} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144 V179 V180} Var=Reg beg of BB83: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V64=x0 Var=Reg end of BB83: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V65=x0 V66=x11 BB84 use: {V14 V64} def: {V65 V66} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V64 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144 V179 V180} Var=Reg beg of BB84: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V64=x0 Var=Reg end of BB84: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V65=x0 V66=x11 BB85 use: {V06 V30 V65 V66} def: {V31 V32 V67} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V65 V66 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} Var=Reg beg of BB85: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V65=x0 V66=x11 Var=Reg end of BB85: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 BB89 use: {V30} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} Var=Reg beg of BB89: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 Var=Reg end of BB89: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 BB90 use: {V20 V144} def: {V20} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} Var=Reg beg of BB90: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 Var=Reg end of BB90: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 BB91 use: {V144} def: {V33 V159 V160 V161} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V161 V179 V180} Var=Reg beg of BB91: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB91: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V144=x4 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V161=x0 BB95 use: {V33 V143 V144 V161} def: {V83 V143 V144 V163 V164} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V33 V143 V144 V161 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} Var=Reg beg of BB95: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V144=x4 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V161=x0 Var=Reg end of BB95: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V144=x3 V03=x20 V01=x21 V143=x2 V15=x26 V17=x23 V180=x24 BB100 use: {V20 V27 V28 V29 V143 V144} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} Var=Reg beg of BB100: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 Var=Reg end of BB100: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V26=x10 V29=x12 BB101 use: {V26 V27} def: {V27 V30} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} Var=Reg beg of BB101: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V26=x10 V29=x12 Var=Reg end of BB101: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V30=x0 V26=x10 V29=x12 BB102 use: {V28 V30 V32} def: {V28} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V26 V27 V28 V29 V30 V32 V143 V144 V179 V180} Var=Reg beg of BB102: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V26=x10 V29=x12 Var=Reg end of BB102: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V30=x15 V26=x10 V29=x12 V32=xip0 BB103 use: {V01 V16} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} Var=Reg beg of BB103: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB103: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB104 use: {V01} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} Var=Reg beg of BB104: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB104: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB106 use: {V03} def: {V86} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144 V179 V180} Var=Reg beg of BB106: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB106: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 BB107 use: {V00 V86} def: {V87} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144 V179 V180} Var=Reg beg of BB107: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 Var=Reg end of BB107: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 V87=x0 BB108 use: {V00 V86 V87} def: {V88} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V87 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} Var=Reg beg of BB108: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 V87=x0 Var=Reg end of BB108: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB112 use: {V17 V180} def: {V21 V34 V36 V165 V169} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB112: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 Var=Reg end of BB112: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB245 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB245: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB245: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB246 use: {V16 V34} def: {V16 V18 V49 V50} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB246: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB246: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB247 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB247: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB247: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB248 use: {V01 V15} def: {} in: {V00 V01 V03 V15} out: {V00 V01 V03} Var=Reg beg of BB248: V00=x19 V03=x20 V01=x21 V15=x26 Var=Reg end of BB248: V00=x19 V03=x20 V01=x21 BB249 use: {V00 V01} def: {} in: {V00 V01 V03} out: {V00 V03} Var=Reg beg of BB249: V00=x19 V03=x20 V01=x21 Var=Reg end of BB249: V00=x19 V03=x20 BB251 use: {V00 V03} def: {} in: {V00 V03} out: {} Var=Reg beg of BB251: V00=x19 V03=x20 Var=Reg end of BB251: none BB253 use: {} def: {} in: {} out: {} Var=Reg beg of BB253: none Var=Reg end of BB253: none BB111 use: {V00 V86} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V86 V143 V144 V179 V180} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V143 V144 V179 V180} Var=Reg beg of BB111: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 Var=Reg end of BB111: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB113 use: {V14} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB113: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB113: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB114 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB114: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB114: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB115 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB115: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB115: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB117 use: {} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB117: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB117: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB118 use: {V00 V36} def: {V60 V177} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V177 V179} Var=Reg beg of BB118: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB118: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V177=x11 V01=x21 V15=x26 V17=x23 BB119 use: {V00} def: {V62 V63} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V63 V143 V144 V179} Var=Reg beg of BB119: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB119: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V63=x14 V01=x21 V15=x26 V17=x23 BB120 use: {V00 V36 V177} def: {V36 V61 V62 V63} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V177 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V63 V143 V144 V179} Var=Reg beg of BB120: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V177=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB120: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V06=x22 V144=x8 V03=x20 V63=x14 V01=x21 V15=x26 V17=x23 BB121 use: {V00 V63} def: {V91 V92} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V63 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V91 V92 V143 V144 V179} Var=Reg beg of BB121: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V63=x14 V01=x21 V15=x26 V17=x23 Var=Reg end of BB121: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V92=x11 V91=x14 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB122 use: {V00 V91 V92} def: {V93} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V91 V92 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB122: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V92=x11 V91=x14 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB122: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB123 use: {V00 V92} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V92 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB123: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V92=x11 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB123: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB124 use: {V08 V12} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB124: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB124: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB125 use: {V08 V20 V143 V144} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB125: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB125: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB127 use: {V03} def: {V95} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144 V179} Var=Reg beg of BB127: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB127: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB129 use: {V00 V95} def: {V96 V181} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144 V179 V181} Var=Reg beg of BB129: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB129: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V96=x14 V36=x0 V06=x22 V03=x20 V181=x12 V01=x21 V15=x26 V17=x23 BB130 use: {V00 V95 V96 V181} def: {V97} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V96 V143 V144 V179 V181} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB130: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V96=x14 V36=x0 V06=x22 V03=x20 V181=x12 V01=x21 V15=x26 V17=x23 Var=Reg end of BB130: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB132 use: {V00 V95} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V95 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB132: V00=x19 V179=x25 V04=x27 V95=x11 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB132: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB133 use: {V20} def: {V20} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB133: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB133: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB134 use: {V08 V14} def: {V08 V14} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB134: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB134: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB135 use: {V14} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB135: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB135: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB136 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB136: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB136: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB137 use: {V18} def: {V184} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V184} Var=Reg beg of BB137: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB137: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V184=x14 BB257 use: {V184} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V184} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB257: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V184=x14 Var=Reg end of BB257: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB138 use: {V18} def: {V185} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V185} Var=Reg beg of BB138: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB138: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V185=x12 BB258 use: {V185} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179 V185} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB258: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V185=x12 Var=Reg end of BB258: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB139 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB139: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB139: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB140 use: {} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB140: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB140: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB141 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB141: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB141: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB142 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB142: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB142: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB143 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB143: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB143: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB144 use: {V03} def: {V110} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} Var=Reg beg of BB144: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB144: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 BB145 use: {V14} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB145: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB145: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB146 use: {V06 V08 V14} def: {V14} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB146: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB146: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB147 use: {} def: {V58} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144 V179} Var=Reg beg of BB147: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB147: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V58=x13 BB148 use: {} def: {V58} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144 V179} Var=Reg beg of BB148: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB148: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V58=x13 BB149 use: {V58} def: {V18} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V58 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB149: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V58=x13 Var=Reg end of BB149: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB150 use: {V36} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB150: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB150: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB151 use: {V07 V08} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB151: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB151: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB152 use: {} def: {V57} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} Var=Reg beg of BB152: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB152: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V57=x11 BB153 use: {} def: {V57} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} Var=Reg beg of BB153: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB153: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V57=x11 BB154 use: {V36} def: {V36 V56 V57} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} Var=Reg beg of BB154: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB154: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V57=x11 BB155 use: {V57} def: {V18} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V57 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB155: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V57=x11 Var=Reg end of BB155: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB156 use: {V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB156: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB156: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB157 use: {V00} def: {V99} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144 V179} Var=Reg beg of BB157: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB157: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V99=x11 BB158 use: {V00 V18 V99} def: {V100} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V99 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB158: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V99=x11 Var=Reg end of BB158: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB159 use: {V00 V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB159: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB159: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB160 use: {V08 V12} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB160: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB160: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB161 use: {V08 V20 V143 V144} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB161: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB161: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB163 use: {V03} def: {V102} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144 V179} Var=Reg beg of BB163: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB163: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 BB165 use: {V00 V102} def: {V103} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144 V179} Var=Reg beg of BB165: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB165: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 V103=x13 BB166 use: {V00 V102 V103} def: {V104} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V103 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB166: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 V103=x13 Var=Reg end of BB166: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB168 use: {V00 V102} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V102 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB168: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB168: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB169 use: {V20} def: {V20} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB169: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB169: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB170 use: {V08} def: {V08} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB170: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB170: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB171 use: {V08 V21} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB171: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB171: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V21=x10 BB172 use: {V07} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB172: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB172: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB173 use: {V04 V05 V36} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB173: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB173: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB174 use: {V03} def: {V106} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144 V179} Var=Reg beg of BB174: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB174: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 BB176 use: {V00 V106} def: {V107} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144 V179} Var=Reg beg of BB176: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB176: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 V107=x10 BB177 use: {V00 V106 V107} def: {V108} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V107 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} Var=Reg beg of BB177: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 V107=x10 Var=Reg end of BB177: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB179 use: {V00 V106} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V106 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} Var=Reg beg of BB179: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB179: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB180 use: {} def: {V21} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB180: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB180: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V21=x11 BB181 use: {V110} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} Var=Reg beg of BB181: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB181: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 BB182 use: {V00 V110} def: {V111} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144 V179} Var=Reg beg of BB182: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB182: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 V111=x13 BB183 use: {V00 V110 V111} def: {V112} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V111 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB183: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 V111=x13 Var=Reg end of BB183: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB185 use: {V00 V110} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V110 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB185: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB185: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB186 use: {V03} def: {V114} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144 V179} Var=Reg beg of BB186: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB186: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 BB187 use: {V00 V114} def: {V115} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144 V179} Var=Reg beg of BB187: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB187: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 V115=x13 BB188 use: {V00 V114 V115} def: {V116} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V115 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB188: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 V115=x13 Var=Reg end of BB188: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB190 use: {V00 V114} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V114 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB190: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 Var=Reg end of BB190: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB191 use: {V00 V16 V172} def: {V16 V59 V118 V119} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144 V179} Var=Reg beg of BB191: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V172=x14 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB191: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V119=x14 V118=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB192 use: {V00 V118 V119} def: {V120} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V118 V119 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB192: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V119=x14 V118=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB192: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB193 use: {V00 V119} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V119 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB193: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V119=x14 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB193: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB194 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB194: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB194: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB195 use: {V16 V34} def: {V172} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} Var=Reg beg of BB195: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB195: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V172=x14 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB196 use: {V18 V172} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V172 V179} Var=Reg beg of BB196: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V172=x14 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB196: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V172=x14 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB197 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB197: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB197: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB198 use: {V16 V34} def: {V172} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB198: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB198: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB199 use: {V16} def: {V16} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB199: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB199: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB200 use: {V16 V34 V179} def: {V176} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V176 V179} Var=Reg beg of BB200: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB200: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V176=x13 BB201 use: {V00 V16 V176} def: {V16 V51 V122 V123} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V176 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144 V179} Var=Reg beg of BB201: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V176=x13 Var=Reg end of BB201: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V123=x13 V122=x11 BB203 use: {V00 V122 V123} def: {V124} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V122 V123 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB203: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V123=x13 V122=x11 Var=Reg end of BB203: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB204 use: {V00 V123} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V123 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB204: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V123=x13 Var=Reg end of BB204: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB205 use: {V09} def: {V37 V38} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB205: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB205: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB206 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB206: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB206: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB207 use: {V16 V34} def: {V176} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB207: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB207: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB208 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB208: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB208: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB209 use: {V16 V34} def: {V176} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V176 V179} Var=Reg beg of BB209: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB209: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V176=x12 V37=x11 BB210 use: {} def: {V37} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB210: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 Var=Reg end of BB210: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB213 use: {V176} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V176 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB213: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V176=x12 V37=x11 Var=Reg end of BB213: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB214 use: {V16 V34} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB214: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB214: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB215 use: {V00} def: {V126} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144 V179} Var=Reg beg of BB215: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB215: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V126=x14 BB216 use: {V00 V18 V126} def: {V127} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V126 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB216: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V126=x14 Var=Reg end of BB216: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 BB218 use: {V38} def: {V38} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB218: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB218: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB219 use: {V16 V179} def: {V16 V54} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB219: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB219: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB220 use: {V16 V34} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB220: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB220: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB221 use: {V38} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB221: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB221: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB222 use: {} def: {V38} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB222: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB222: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB223 use: {V17} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} Var=Reg beg of BB223: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB223: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB224 use: {V01 V05} def: {V55} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144 V179} Var=Reg beg of BB224: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB224: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 V55=x4 BB225 use: {} def: {V55} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144 V179} Var=Reg beg of BB225: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 Var=Reg end of BB225: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 V55=x4 BB226 use: {V00 V03 V18 V37 V38 V55} def: {V09} in: {V00 V01 V03 V04 V05 V06 V07 V08 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V37 V38 V55 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB226: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 V55=x4 Var=Reg end of BB226: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB227 use: {V00} def: {V129} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144 V179} Var=Reg beg of BB227: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB227: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V129=x11 BB228 use: {V00 V18 V129} def: {V130} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V129 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB228: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V129=x11 Var=Reg end of BB228: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 BB229 use: {V00 V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB229: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB229: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB230 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB230: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB230: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 BB231 use: {V16 V34} def: {V175} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} Var=Reg beg of BB231: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB231: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V175=x11 BB232 use: {V175} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} Var=Reg beg of BB232: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V175=x11 Var=Reg end of BB232: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V175=x11 BB233 use: {V00 V16 V175} def: {V16 V52 V132 V133} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V175 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144 V179} Var=Reg beg of BB233: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V175=x11 Var=Reg end of BB233: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V133=x11 V132=x13 BB234 use: {V00 V132 V133} def: {V134} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V132 V133 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB234: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V133=x11 V132=x13 Var=Reg end of BB234: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB235 use: {V00 V133} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V133 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB235: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V133=x11 Var=Reg end of BB235: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB236 use: {V00 V16 V173} def: {V16 V53 V136 V137} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V173 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144 V179} Var=Reg beg of BB236: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V173=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB236: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V137=x11 V14=x3 V136=x13 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB237 use: {V00 V136 V137} def: {V138} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V136 V137 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB237: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V137=x11 V14=x3 V136=x13 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB237: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB238 use: {V00 V137} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V137 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB238: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V137=x11 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB238: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB239 use: {V16 V179} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB239: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB239: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB240 use: {V16 V34} def: {V173} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V173 V179} Var=Reg beg of BB240: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB240: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V173=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB241 use: {} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB241: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB241: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB242 use: {V00} def: {V140} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144 V179} Var=Reg beg of BB242: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB242: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V140=x11 BB243 use: {V00 V18 V140} def: {V141} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V140 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB243: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V140=x11 Var=Reg end of BB243: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB244 use: {V00 V18} def: {} in: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V18 V20 V21 V34 V36 V143 V144 V179} out: {V00 V01 V03 V04 V05 V06 V07 V08 V09 V12 V14 V15 V16 V17 V20 V21 V34 V36 V143 V144 V179} Var=Reg beg of BB244: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB244: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB110 use: {} def: {} in: {} out: {} Var=Reg beg of BB110: none Var=Reg end of BB110: none BB254 use: {} def: {} in: {} out: {} Var=Reg beg of BB254: none Var=Reg end of BB254: none RESOLVING EDGES fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB255, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB255 New Basic Block BB259 [0368] created. Splitting edge from BB255 to BB47; adding BB259 Setting edge weights for BB255 -> BB259 to [0 .. 3.402823e+38] Setting edge weights for BB259 -> BB47 to [0 .. 3.402823e+38] BB259 bottom (BB255->BB47): move V16 from x10 to x1 (Critical) N001 ( 1, 1) [004305] ----------- t4305 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4305 int N002 ( 2, 2) [004306] ----------- t4306 = * COPY int REG x1 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB256, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB256 New Basic Block BB260 [0369] created. Splitting edge from BB256 to BB47; adding BB260 Setting edge weights for BB256 -> BB260 to [0 .. 3.402823e+38] Setting edge weights for BB260 -> BB47 to [0 .. 3.402823e+38] BB260 bottom (BB256->BB47): move V16 from x10 to x1 (Critical) N001 ( 1, 1) [004307] ----------- t4307 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4307 int N002 ( 2, 2) [004308] ----------- t4308 = * COPY int REG x1 BB15 bottom: move V16 from x10 to x1 (SharedCritical) N001 ( 1, 1) [004309] ----------- t4309 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4309 int N002 ( 2, 2) [004310] ----------- t4310 = * COPY int REG x1 BB21 bottom: move V16 from x10 to x1 (SharedCritical) N001 ( 1, 1) [004311] ----------- t4311 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4311 int N002 ( 2, 2) [004312] ----------- t4312 = * COPY int REG x1 BB23 bottom: move V16 from x10 to x1 (SharedCritical) N001 ( 1, 1) [004313] ----------- t4313 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4313 int N002 ( 2, 2) [004314] ----------- t4314 = * COPY int REG x1 BB31 bottom: move V16 from x10 to x1 (SharedCritical) N001 ( 1, 1) [004315] ----------- t4315 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4315 int N002 ( 2, 2) [004316] ----------- t4316 = * COPY int REG x1 BB32 bottom: move V16 from STK to x10 (SharedCritical) N001 ( 1, 1) [004317] ----------z t4317 = LCL_VAR int V16 loc12 x10 REG x10 BB35 bottom: move V16 from x10 to x1 (SharedCritical) N001 ( 1, 1) [004318] ----------- t4318 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4318 int N002 ( 2, 2) [004319] ----------- t4319 = * COPY int REG x1 BB40 bottom: move V16 from x10 to x1 (SharedCritical) N001 ( 1, 1) [004320] ----------- t4320 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4320 int N002 ( 2, 2) [004321] ----------- t4321 = * COPY int REG x1 New Basic Block BB261 [0370] created. Splitting edge from BB43 to BB44; adding BB261 Setting edge weights for BB43 -> BB261 to [0 .. 3.402823e+38] BB261 bottom (BB43->BB44): move V16 from x1 to x10 (Critical) N001 ( 1, 1) [004322] ----------- t4322 = LCL_VAR int V16 loc12 x1 REG x1 /--* t4322 int N002 ( 2, 2) [004323] ----------- t4323 = * COPY int REG x10 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB78, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB83 New Basic Block BB262 [0371] created. Splitting edge from BB78 to BB103; adding BB262 Setting edge weights for BB78 -> BB262 to [0 .. 3.402823e+38] BB262 bottom (BB78->BB103): move V08 from x2 to STK (Critical) N001 ( 1, 1) [004324] ----------Z t4324 = LCL_VAR int V08 loc4 x2 REG x2 BB102 bottom: move V28 from x14 to STK (SharedCritical) N001 ( 1, 1) [004325] ----------Z t4325 = LCL_VAR int V28 loc24 x14 REG x14 BB102 bottom: move V27 from x13 to STK (SharedCritical) N001 ( 1, 1) [004326] ----------Z t4326 = LCL_VAR int V27 loc23 x13 REG x13 BB102 bottom: move V29 from x12 to STK (SharedCritical) N001 ( 1, 1) [004327] ----------Z t4327 = LCL_VAR int V29 loc25 x12 REG x12 BB102 bottom: move V32 from xip0 to STK (SharedCritical) N001 ( 1, 1) [004328] ----------Z t4328 = LCL_VAR int V32 loc28 xip0 REG xip0 BB102 bottom: move V144 from STK to x8 (SharedCritical) N001 ( 1, 1) [004329] ----------z t4329 = LCL_VAR int V144 tmp104 x8 REG x8 BB102 bottom: move V20 from STK to x9 (SharedCritical) N001 ( 1, 1) [004330] ----------z t4330 = LCL_VAR int V20 loc16 x9 REG x9 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB113, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB117 New Basic Block BB263 [0372] created. Splitting edge from BB113 to BB136; adding BB263 Setting edge weights for BB113 -> BB263 to [0 .. 3.402823e+38] BB263 bottom (BB113->BB136): move V14 from x3 to STK (Critical) N001 ( 1, 1) [004331] ----------Z t4331 = LCL_VAR int V14 loc10 x3 REG x3 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB115, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB117 New Basic Block BB264 [0373] created. Splitting edge from BB115 to BB135; adding BB264 Setting edge weights for BB115 -> BB264 to [0 .. 3.402823e+38] BB264 bottom (BB115->BB135): move V18 from STK to x13 (Critical) N001 ( 1, 1) [004332] ----------z t4332 = LCL_VAR ushort V18 loc14 x13 REG x13 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB125, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB130 New Basic Block BB265 [0374] created. Splitting edge from BB125 to BB134; adding BB265 Setting edge weights for BB125 -> BB265 to [0 .. 3.402823e+38] BB265 bottom (BB125->BB134): move V08 from STK to x2 (Critical) N001 ( 1, 1) [004333] ----------z t4333 = LCL_VAR int V08 loc4 x2 REG x2 BB265 bottom (BB125->BB134): move V144 from STK to x8 (Critical) N001 ( 1, 1) [004334] ----------z t4334 = LCL_VAR int V144 tmp104 x8 REG x8 BB265 bottom (BB125->BB134): move V20 from STK to x9 (Critical) N001 ( 1, 1) [004335] ----------z t4335 = LCL_VAR int V20 loc16 x9 REG x9 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB258, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB258 New Basic Block BB266 [0375] created. Splitting edge from BB258 to BB245; adding BB266 Setting edge weights for BB258 -> BB266 to [0 .. 3.402823e+38] Setting edge weights for BB266 -> BB245 to [0 .. 3.402823e+38] BB266 bottom (BB258->BB245): move V14 from STK to x3 (Critical) N001 ( 1, 1) [004336] ----------z t4336 = LCL_VAR int V14 loc10 x3 REG x3 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB161, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB166 New Basic Block BB267 [0376] created. Splitting edge from BB161 to BB170; adding BB267 Setting edge weights for BB161 -> BB267 to [0 .. 3.402823e+38] BB267 bottom (BB161->BB170): move V08 from STK to x2 (Critical) N001 ( 1, 1) [004337] ----------z t4337 = LCL_VAR int V08 loc4 x2 REG x2 BB267 bottom (BB161->BB170): move V144 from STK to x8 (Critical) N001 ( 1, 1) [004338] ----------z t4338 = LCL_VAR int V144 tmp104 x8 REG x8 BB267 bottom (BB161->BB170): move V20 from STK to x9 (Critical) N001 ( 1, 1) [004339] ----------z t4339 = LCL_VAR int V20 loc16 x9 REG x9 BB171 bottom: move V21 from x10 to STK (SharedCritical) N001 ( 1, 1) [004340] ----------Z t4340 = LCL_VAR bool V21 loc17 x10 REG x10 BB171 bottom: move V14 from STK to x3 (SharedCritical) N001 ( 1, 1) [004341] ----------z t4341 = LCL_VAR int V14 loc10 x3 REG x3 BB173 bottom: move V36 from STK to x0 (SharedCritical) N001 ( 1, 1) [004342] ----------z t4342 = LCL_VAR long V36 loc32 x0 REG x0 BB181 bottom: move V14 from STK to x3 (SharedCritical) N001 ( 1, 1) [004343] ----------z t4343 = LCL_VAR int V14 loc10 x3 REG x3 BB186 bottom: move V14 from STK to x3 (SharedCritical) N001 ( 1, 1) [004344] ----------z t4344 = LCL_VAR int V14 loc10 x3 REG x3 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB197, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB199 New Basic Block BB268 [0377] created. Splitting edge from BB197 to BB245; adding BB268 Setting edge weights for BB197 -> BB268 to [0 .. 3.402823e+38] BB268 bottom (BB197->BB245): move V16 from x4 to STK (Critical) N001 ( 1, 1) [004345] ----------Z t4345 = LCL_VAR int V16 loc12 x4 REG x4 BB268 bottom (BB197->BB245): move V14 from STK to x3 (Critical) N001 ( 1, 1) [004346] ----------z t4346 = LCL_VAR int V14 loc10 x3 REG x3 BB198 bottom: move V16 from x4 to STK (SharedCritical) N001 ( 1, 1) [004347] ----------Z t4347 = LCL_VAR int V16 loc12 x4 REG x4 BB198 bottom: move V14 from STK to x3 (SharedCritical) N001 ( 1, 1) [004348] ----------z t4348 = LCL_VAR int V14 loc10 x3 REG x3 BB200 bottom: move V16 from x4 to STK (SharedCritical) N001 ( 1, 1) [004349] ----------Z t4349 = LCL_VAR int V16 loc12 x4 REG x4 BB200 bottom: move V14 from STK to x3 (SharedCritical) N001 ( 1, 1) [004350] ----------z t4350 = LCL_VAR int V14 loc10 x3 REG x3 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB215, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB216 New Basic Block BB269 [0378] created. Splitting edge from BB215 to BB244; adding BB269 Setting edge weights for BB215 -> BB269 to [0 .. 3.402823e+38] BB269 bottom (BB215->BB244): move V16 from x4 to STK (Critical) N001 ( 1, 1) [004351] ----------Z t4351 = LCL_VAR int V16 loc12 x4 REG x4 BB269 bottom (BB215->BB244): move V20 from x9 to STK (Critical) N001 ( 1, 1) [004352] ----------Z t4352 = LCL_VAR int V20 loc16 x9 REG x9 BB269 bottom (BB215->BB244): move V36 from x0 to STK (Critical) N001 ( 1, 1) [004353] ----------Z t4353 = LCL_VAR long V36 loc32 x0 REG x0 BB269 bottom (BB215->BB244): move V144 from x8 to STK (Critical) N001 ( 1, 1) [004354] ----------Z t4354 = LCL_VAR int V144 tmp104 x8 REG x8 BB269 bottom (BB215->BB244): move V09 from x5 to STK (Critical) N001 ( 1, 1) [004355] ----------Z t4355 = LCL_VAR bool V09 loc5 x5 REG x5 New Basic Block BB270 [0379] created. Splitting edge from BB220 to BB221; adding BB270 Setting edge weights for BB220 -> BB270 to [0 .. 3.402823e+38] BB270 bottom (BB220->BB221): move V16 from STK to x12 (Critical) N001 ( 1, 1) [004356] ----------z t4356 = LCL_VAR int V16 loc12 x12 REG x12 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB220, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB224 New Basic Block BB271 [0380] created. Splitting edge from BB220 to BB218; adding BB271 Setting edge weights for BB220 -> BB271 to [0 .. 3.402823e+38] BB271 bottom (BB220->BB218): move V16 from STK to x4 (Critical) N001 ( 1, 1) [004357] ----------z t4357 = LCL_VAR int V16 loc12 x4 REG x4 BB230 bottom: move V16 from x4 to STK (SharedCritical) N001 ( 1, 1) [004358] ----------Z t4358 = LCL_VAR int V16 loc12 x4 REG x4 BB230 bottom: move V09 from x5 to STK (SharedCritical) N001 ( 1, 1) [004359] ----------Z t4359 = LCL_VAR bool V09 loc5 x5 REG x5 BB230 bottom: move V14 from STK to x3 (SharedCritical) N001 ( 1, 1) [004360] ----------z t4360 = LCL_VAR int V14 loc10 x3 REG x3 BB239 bottom: move V16 from x4 to STK (SharedCritical) N001 ( 1, 1) [004361] ----------Z t4361 = LCL_VAR int V16 loc12 x4 REG x4 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB242, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB243 New Basic Block BB272 [0381] created. Splitting edge from BB242 to BB244; adding BB272 Setting edge weights for BB242 -> BB272 to [0 .. 3.402823e+38] BB272 bottom (BB242->BB244): move V20 from x9 to STK (Critical) N001 ( 1, 1) [004362] ----------Z t4362 = LCL_VAR int V20 loc16 x9 REG x9 BB272 bottom (BB242->BB244): move V36 from x0 to STK (Critical) N001 ( 1, 1) [004363] ----------Z t4363 = LCL_VAR long V36 loc32 x0 REG x0 BB272 bottom (BB242->BB244): move V144 from x8 to STK (Critical) N001 ( 1, 1) [004364] ----------Z t4364 = LCL_VAR int V144 tmp104 x8 REG x8 BB12 bottom (BB12->BB47): move V16 from x10 to x1 (Join) N001 ( 1, 1) [004365] ----------- t4365 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4365 int N002 ( 2, 2) [004366] ----------- t4366 = * COPY int REG x1 BB17 bottom (BB17->BB47): move V16 from x10 to x1 (Join) N001 ( 1, 1) [004367] ----------- t4367 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4367 int N002 ( 2, 2) [004368] ----------- t4368 = * COPY int REG x1 BB20 bottom (BB20->BB47): move V06 from x3 to STK (Join) N001 ( 1, 1) [004369] ----------Z t4369 = LCL_VAR int V06 loc2 x3 REG x3 BB20 bottom (BB20->BB47): move V07 from x2 to STK (Join) N001 ( 1, 1) [004370] ----------Z t4370 = LCL_VAR int V07 loc3 x2 REG x2 BB20 bottom (BB20->BB47): move V16 from x10 to x1 (Join) N001 ( 1, 1) [004371] ----------- t4371 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4371 int N002 ( 2, 2) [004372] ----------- t4372 = * COPY int REG x1 BB28 bottom (BB28->BB29): move V12 from STK to x7 (Join) N001 ( 1, 1) [004373] ----------z t4373 = LCL_VAR bool V12 loc8 x7 REG x7 BB30 bottom (BB30->BB47): move V16 from x10 to x1 (Join) N001 ( 1, 1) [004374] ----------- t4374 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4374 int N002 ( 2, 2) [004375] ----------- t4375 = * COPY int REG x1 BB34 bottom (BB34->BB47): move V16 from x10 to x1 (Join) N001 ( 1, 1) [004376] ----------- t4376 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4376 int N002 ( 2, 2) [004377] ----------- t4377 = * COPY int REG x1 BB46 bottom (BB46->BB47): move V16 from x10 to x1 (Join) N001 ( 1, 1) [004378] ----------- t4378 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4378 int N002 ( 2, 2) [004379] ----------- t4379 = * COPY int REG x1 BB55 bottom (BB55->BB56): move V12 from STK to x7 (Join) N001 ( 1, 1) [004380] ----------z t4380 = LCL_VAR bool V12 loc8 x7 REG x7 BB58 bottom (BB58->BB60): move V12 from x7 to STK (Join) N001 ( 1, 1) [004381] ----------Z t4381 = LCL_VAR bool V12 loc8 x7 REG x7 BB59 bottom (BB59->BB60): move V12 from x7 to STK (Join) N001 ( 1, 1) [004382] ----------Z t4382 = LCL_VAR bool V12 loc8 x7 REG x7 BB65 bottom (BB65->BB66): move V12 from x7 to STK (Join) N001 ( 1, 1) [004383] ----------Z t4383 = LCL_VAR bool V12 loc8 x7 REG x7 BB65 bottom (BB65->BB66): move V09 from x5 to STK (Join) N001 ( 1, 1) [004384] ----------Z t4384 = LCL_VAR bool V09 loc5 x5 REG x5 BB81 bottom (BB81->BB82): move V26 from STK to x10 (Join) N001 ( 1, 1) [004385] ----------z t4385 = LCL_VAR ref V26 loc22 x10 REG x10 BB84 bottom (BB84->BB85): move V14 from STK to x3 (Join) N001 ( 1, 1) [004386] ----------z t4386 = LCL_VAR int V14 loc10 x3 REG x3 BB91 top (BB90->BB91): move V14 from x3 to STK (Split) N001 ( 1, 1) [004387] ----------Z t4387 = LCL_VAR int V14 loc10 x3 REG x3 BB91 top (BB90->BB91): move V26 from x10 to STK (Split) N001 ( 1, 1) [004388] ----------Z t4388 = LCL_VAR ref V26 loc22 x10 REG x10 BB95 bottom (BB95->BB100): move V143 from x2 to STK (Join) N001 ( 1, 1) [004389] ----------Z t4389 = LCL_VAR byref V143 tmp103 x2 REG x2 BB95 bottom (BB95->BB100): move V144 from x3 to x8 (Join) N001 ( 1, 1) [004390] ----------- t4390 = LCL_VAR int V144 tmp104 x3 REG x3 /--* t4390 int N002 ( 2, 2) [004391] ----------- t4391 = * COPY int REG x8 BB95 bottom (BB95->BB100): move V14 from STK to x3 (Join) N001 ( 1, 1) [004392] ----------z t4392 = LCL_VAR int V14 loc10 x3 REG x3 BB95 bottom (BB95->BB100): move V26 from STK to x10 (Join) N001 ( 1, 1) [004393] ----------z t4393 = LCL_VAR ref V26 loc22 x10 REG x10 BB101 bottom (BB101->BB102): move V30 from x0 to STK (Join) N001 ( 1, 1) [004394] ----------Z t4394 = LCL_VAR int V30 loc26 x0 REG x0 BB111 top (BB107->BB111): move V20 from x9 to STK (Split) N001 ( 1, 1) [004395] ----------Z t4395 = LCL_VAR int V20 loc16 x9 REG x9 BB111 top (BB107->BB111): move V14 from x3 to STK (Split) N001 ( 1, 1) [004396] ----------Z t4396 = LCL_VAR int V14 loc10 x3 REG x3 BB111 top (BB107->BB111): move V144 from x8 to STK (Split) N001 ( 1, 1) [004397] ----------Z t4397 = LCL_VAR int V144 tmp104 x8 REG x8 BB111 bottom (BB111->BB112): move V14 from STK to x3 (Join) N001 ( 1, 1) [004398] ----------z t4398 = LCL_VAR int V14 loc10 x3 REG x3 BB111 bottom (BB111->BB112): move V144 from STK to x8 (Join) N001 ( 1, 1) [004399] ----------z t4399 = LCL_VAR int V144 tmp104 x8 REG x8 BB111 bottom (BB111->BB112): move V20 from STK to x9 (Join) N001 ( 1, 1) [004400] ----------z t4400 = LCL_VAR int V20 loc16 x9 REG x9 BB117 bottom (BB117->BB136): move V14 from x3 to STK (Join) N001 ( 1, 1) [004401] ----------Z t4401 = LCL_VAR int V14 loc10 x3 REG x3 BB117 bottom (BB117->BB136): move V18 from STK to x13 (Join) N001 ( 1, 1) [004402] ----------z t4402 = LCL_VAR ushort V18 loc14 x13 REG x13 BB120 bottom (BB120->BB121): move V36 from STK to x0 (Join) N001 ( 1, 1) [004403] ----------z t4403 = LCL_VAR long V36 loc32 x0 REG x0 BB123 top (BB121->BB123): move V18 from x13 to STK (Split) N001 ( 1, 1) [004404] ----------Z t4404 = LCL_VAR ushort V18 loc14 x13 REG x13 BB123 top (BB121->BB123): move V20 from x9 to STK (Split) N001 ( 1, 1) [004405] ----------Z t4405 = LCL_VAR int V20 loc16 x9 REG x9 BB123 top (BB121->BB123): move V36 from x0 to STK (Split) N001 ( 1, 1) [004406] ----------Z t4406 = LCL_VAR long V36 loc32 x0 REG x0 BB123 top (BB121->BB123): move V144 from x8 to STK (Split) N001 ( 1, 1) [004407] ----------Z t4407 = LCL_VAR int V144 tmp104 x8 REG x8 BB123 bottom (BB123->BB124): move V36 from STK to x0 (Join) N001 ( 1, 1) [004408] ----------z t4408 = LCL_VAR long V36 loc32 x0 REG x0 BB123 bottom (BB123->BB124): move V144 from STK to x8 (Join) N001 ( 1, 1) [004409] ----------z t4409 = LCL_VAR int V144 tmp104 x8 REG x8 BB123 bottom (BB123->BB124): move V20 from STK to x9 (Join) N001 ( 1, 1) [004410] ----------z t4410 = LCL_VAR int V20 loc16 x9 REG x9 BB123 bottom (BB123->BB124): move V18 from STK to x13 (Join) N001 ( 1, 1) [004411] ----------z t4411 = LCL_VAR ushort V18 loc14 x13 REG x13 BB132 top (BB129->BB132): move V18 from x13 to STK (Split) N001 ( 1, 1) [004412] ----------Z t4412 = LCL_VAR ushort V18 loc14 x13 REG x13 BB132 top (BB129->BB132): move V36 from x0 to STK (Split) N001 ( 1, 1) [004413] ----------Z t4413 = LCL_VAR long V36 loc32 x0 REG x0 BB132 bottom (BB132->BB133): move V36 from STK to x0 (Join) N001 ( 1, 1) [004414] ----------z t4414 = LCL_VAR long V36 loc32 x0 REG x0 BB132 bottom (BB132->BB133): move V18 from STK to x13 (Join) N001 ( 1, 1) [004415] ----------z t4415 = LCL_VAR ushort V18 loc14 x13 REG x13 BB133 bottom (BB133->BB134): move V08 from STK to x2 (Join) N001 ( 1, 1) [004416] ----------z t4416 = LCL_VAR int V08 loc4 x2 REG x2 BB133 bottom (BB133->BB134): move V144 from STK to x8 (Join) N001 ( 1, 1) [004417] ----------z t4417 = LCL_VAR int V144 tmp104 x8 REG x8 BB133 bottom (BB133->BB134): move V20 from STK to x9 (Join) N001 ( 1, 1) [004418] ----------z t4418 = LCL_VAR int V20 loc16 x9 REG x9 BB134 bottom (BB134->BB135): move V14 from STK to x3 (Join) N001 ( 1, 1) [004419] ----------z t4419 = LCL_VAR int V14 loc10 x3 REG x3 BB154 bottom (BB154->BB155): move V36 from STK to x0 (Join) N001 ( 1, 1) [004420] ----------z t4420 = LCL_VAR long V36 loc32 x0 REG x0 BB155 bottom (BB155->BB156): move V14 from x3 to STK (Join) N001 ( 1, 1) [004421] ----------Z t4421 = LCL_VAR int V14 loc10 x3 REG x3 BB155 bottom (BB155->BB156): move V08 from STK to x2 (Join) N001 ( 1, 1) [004422] ----------z t4422 = LCL_VAR int V08 loc4 x2 REG x2 BB159 top (BB157->BB159): move V20 from x9 to STK (Split) N001 ( 1, 1) [004423] ----------Z t4423 = LCL_VAR int V20 loc16 x9 REG x9 BB159 top (BB157->BB159): move V08 from x2 to STK (Split) N001 ( 1, 1) [004424] ----------Z t4424 = LCL_VAR int V08 loc4 x2 REG x2 BB159 top (BB157->BB159): move V36 from x0 to STK (Split) N001 ( 1, 1) [004425] ----------Z t4425 = LCL_VAR long V36 loc32 x0 REG x0 BB159 top (BB157->BB159): move V144 from x8 to STK (Split) N001 ( 1, 1) [004426] ----------Z t4426 = LCL_VAR int V144 tmp104 x8 REG x8 BB159 bottom (BB159->BB160): move V36 from STK to x0 (Join) N001 ( 1, 1) [004427] ----------z t4427 = LCL_VAR long V36 loc32 x0 REG x0 BB159 bottom (BB159->BB160): move V08 from STK to x2 (Join) N001 ( 1, 1) [004428] ----------z t4428 = LCL_VAR int V08 loc4 x2 REG x2 BB159 bottom (BB159->BB160): move V144 from STK to x8 (Join) N001 ( 1, 1) [004429] ----------z t4429 = LCL_VAR int V144 tmp104 x8 REG x8 BB159 bottom (BB159->BB160): move V20 from STK to x9 (Join) N001 ( 1, 1) [004430] ----------z t4430 = LCL_VAR int V20 loc16 x9 REG x9 BB168 top (BB165->BB168): move V36 from x0 to STK (Split) N001 ( 1, 1) [004431] ----------Z t4431 = LCL_VAR long V36 loc32 x0 REG x0 BB168 bottom (BB168->BB169): move V36 from STK to x0 (Join) N001 ( 1, 1) [004432] ----------z t4432 = LCL_VAR long V36 loc32 x0 REG x0 BB169 bottom (BB169->BB170): move V08 from STK to x2 (Join) N001 ( 1, 1) [004433] ----------z t4433 = LCL_VAR int V08 loc4 x2 REG x2 BB169 bottom (BB169->BB170): move V144 from STK to x8 (Join) N001 ( 1, 1) [004434] ----------z t4434 = LCL_VAR int V144 tmp104 x8 REG x8 BB169 bottom (BB169->BB170): move V20 from STK to x9 (Join) N001 ( 1, 1) [004435] ----------z t4435 = LCL_VAR int V20 loc16 x9 REG x9 BB170 bottom (BB170->BB245): move V14 from STK to x3 (Join) N001 ( 1, 1) [004436] ----------z t4436 = LCL_VAR int V14 loc10 x3 REG x3 BB179 top (BB176->BB179): move V20 from x9 to STK (Split) N001 ( 1, 1) [004437] ----------Z t4437 = LCL_VAR int V20 loc16 x9 REG x9 BB179 top (BB176->BB179): move V14 from x3 to STK (Split) N001 ( 1, 1) [004438] ----------Z t4438 = LCL_VAR int V14 loc10 x3 REG x3 BB179 top (BB176->BB179): move V36 from x0 to STK (Split) N001 ( 1, 1) [004439] ----------Z t4439 = LCL_VAR long V36 loc32 x0 REG x0 BB179 top (BB176->BB179): move V144 from x8 to STK (Split) N001 ( 1, 1) [004440] ----------Z t4440 = LCL_VAR int V144 tmp104 x8 REG x8 BB179 bottom (BB179->BB180): move V36 from STK to x0 (Join) N001 ( 1, 1) [004441] ----------z t4441 = LCL_VAR long V36 loc32 x0 REG x0 BB179 bottom (BB179->BB180): move V14 from STK to x3 (Join) N001 ( 1, 1) [004442] ----------z t4442 = LCL_VAR int V14 loc10 x3 REG x3 BB179 bottom (BB179->BB180): move V144 from STK to x8 (Join) N001 ( 1, 1) [004443] ----------z t4443 = LCL_VAR int V144 tmp104 x8 REG x8 BB179 bottom (BB179->BB180): move V20 from STK to x9 (Join) N001 ( 1, 1) [004444] ----------z t4444 = LCL_VAR int V20 loc16 x9 REG x9 BB180 bottom (BB180->BB245): move V21 from x11 to STK (Join) N001 ( 1, 1) [004445] ----------Z t4445 = LCL_VAR bool V21 loc17 x11 REG x11 BB185 top (BB182->BB185): move V20 from x9 to STK (Split) N001 ( 1, 1) [004446] ----------Z t4446 = LCL_VAR int V20 loc16 x9 REG x9 BB185 top (BB182->BB185): move V14 from x3 to STK (Split) N001 ( 1, 1) [004447] ----------Z t4447 = LCL_VAR int V14 loc10 x3 REG x3 BB185 top (BB182->BB185): move V36 from x0 to STK (Split) N001 ( 1, 1) [004448] ----------Z t4448 = LCL_VAR long V36 loc32 x0 REG x0 BB185 top (BB182->BB185): move V144 from x8 to STK (Split) N001 ( 1, 1) [004449] ----------Z t4449 = LCL_VAR int V144 tmp104 x8 REG x8 BB185 bottom (BB185->BB245): move V36 from STK to x0 (Join) N001 ( 1, 1) [004450] ----------z t4450 = LCL_VAR long V36 loc32 x0 REG x0 BB185 bottom (BB185->BB245): move V14 from STK to x3 (Join) N001 ( 1, 1) [004451] ----------z t4451 = LCL_VAR int V14 loc10 x3 REG x3 BB185 bottom (BB185->BB245): move V144 from STK to x8 (Join) N001 ( 1, 1) [004452] ----------z t4452 = LCL_VAR int V144 tmp104 x8 REG x8 BB185 bottom (BB185->BB245): move V20 from STK to x9 (Join) N001 ( 1, 1) [004453] ----------z t4453 = LCL_VAR int V20 loc16 x9 REG x9 BB190 top (BB187->BB190): move V20 from x9 to STK (Split) N001 ( 1, 1) [004454] ----------Z t4454 = LCL_VAR int V20 loc16 x9 REG x9 BB190 top (BB187->BB190): move V14 from x3 to STK (Split) N001 ( 1, 1) [004455] ----------Z t4455 = LCL_VAR int V14 loc10 x3 REG x3 BB190 top (BB187->BB190): move V36 from x0 to STK (Split) N001 ( 1, 1) [004456] ----------Z t4456 = LCL_VAR long V36 loc32 x0 REG x0 BB190 top (BB187->BB190): move V144 from x8 to STK (Split) N001 ( 1, 1) [004457] ----------Z t4457 = LCL_VAR int V144 tmp104 x8 REG x8 BB190 bottom (BB190->BB245): move V36 from STK to x0 (Join) N001 ( 1, 1) [004458] ----------z t4458 = LCL_VAR long V36 loc32 x0 REG x0 BB190 bottom (BB190->BB245): move V14 from STK to x3 (Join) N001 ( 1, 1) [004459] ----------z t4459 = LCL_VAR int V14 loc10 x3 REG x3 BB190 bottom (BB190->BB245): move V144 from STK to x8 (Join) N001 ( 1, 1) [004460] ----------z t4460 = LCL_VAR int V144 tmp104 x8 REG x8 BB190 bottom (BB190->BB245): move V20 from STK to x9 (Join) N001 ( 1, 1) [004461] ----------z t4461 = LCL_VAR int V20 loc16 x9 REG x9 BB192 bottom (BB192->BB194): move V18 from STK to x13 (Join) N001 ( 1, 1) [004462] ----------z t4462 = LCL_VAR ushort V18 loc14 x13 REG x13 BB193 top (BB191->BB193): move V20 from x9 to STK (Split) N001 ( 1, 1) [004463] ----------Z t4463 = LCL_VAR int V20 loc16 x9 REG x9 BB193 top (BB191->BB193): move V36 from x0 to STK (Split) N001 ( 1, 1) [004464] ----------Z t4464 = LCL_VAR long V36 loc32 x0 REG x0 BB193 top (BB191->BB193): move V144 from x8 to STK (Split) N001 ( 1, 1) [004465] ----------Z t4465 = LCL_VAR int V144 tmp104 x8 REG x8 BB193 bottom (BB193->BB194): move V36 from STK to x0 (Join) N001 ( 1, 1) [004466] ----------z t4466 = LCL_VAR long V36 loc32 x0 REG x0 BB193 bottom (BB193->BB194): move V144 from STK to x8 (Join) N001 ( 1, 1) [004467] ----------z t4467 = LCL_VAR int V144 tmp104 x8 REG x8 BB193 bottom (BB193->BB194): move V20 from STK to x9 (Join) N001 ( 1, 1) [004468] ----------z t4468 = LCL_VAR int V20 loc16 x9 REG x9 BB193 bottom (BB193->BB194): move V18 from STK to x13 (Join) N001 ( 1, 1) [004469] ----------z t4469 = LCL_VAR ushort V18 loc14 x13 REG x13 BB204 top (BB201->BB204): move V20 from x9 to STK (Split) N001 ( 1, 1) [004470] ----------Z t4470 = LCL_VAR int V20 loc16 x9 REG x9 BB204 top (BB201->BB204): move V14 from x3 to STK (Split) N001 ( 1, 1) [004471] ----------Z t4471 = LCL_VAR int V14 loc10 x3 REG x3 BB204 top (BB201->BB204): move V36 from x0 to STK (Split) N001 ( 1, 1) [004472] ----------Z t4472 = LCL_VAR long V36 loc32 x0 REG x0 BB204 top (BB201->BB204): move V144 from x8 to STK (Split) N001 ( 1, 1) [004473] ----------Z t4473 = LCL_VAR int V144 tmp104 x8 REG x8 BB204 bottom (BB204->BB245): move V36 from STK to x0 (Join) N001 ( 1, 1) [004474] ----------z t4474 = LCL_VAR long V36 loc32 x0 REG x0 BB204 bottom (BB204->BB245): move V14 from STK to x3 (Join) N001 ( 1, 1) [004475] ----------z t4475 = LCL_VAR int V14 loc10 x3 REG x3 BB204 bottom (BB204->BB245): move V144 from STK to x8 (Join) N001 ( 1, 1) [004476] ----------z t4476 = LCL_VAR int V144 tmp104 x8 REG x8 BB204 bottom (BB204->BB245): move V20 from STK to x9 (Join) N001 ( 1, 1) [004477] ----------z t4477 = LCL_VAR int V20 loc16 x9 REG x9 BB216 bottom (BB216->BB245): move V16 from x4 to STK (Join) N001 ( 1, 1) [004478] ----------Z t4478 = LCL_VAR int V16 loc12 x4 REG x4 BB216 bottom (BB216->BB245): move V09 from x5 to STK (Join) N001 ( 1, 1) [004479] ----------Z t4479 = LCL_VAR bool V09 loc5 x5 REG x5 BB216 bottom (BB216->BB245): move V14 from STK to x3 (Join) N001 ( 1, 1) [004480] ----------z t4480 = LCL_VAR int V14 loc10 x3 REG x3 BB224 bottom (BB224->BB226): move V16 from x12 to STK (Join) N001 ( 1, 1) [004481] ----------Z t4481 = LCL_VAR int V16 loc12 x12 REG x12 BB224 bottom (BB224->BB226): move V20 from x9 to STK (Join) N001 ( 1, 1) [004482] ----------Z t4482 = LCL_VAR int V20 loc16 x9 REG x9 BB224 bottom (BB224->BB226): move V36 from x0 to STK (Join) N001 ( 1, 1) [004483] ----------Z t4483 = LCL_VAR long V36 loc32 x0 REG x0 BB224 bottom (BB224->BB226): move V144 from x8 to STK (Join) N001 ( 1, 1) [004484] ----------Z t4484 = LCL_VAR int V144 tmp104 x8 REG x8 BB225 bottom (BB225->BB226): move V16 from x12 to STK (Join) N001 ( 1, 1) [004485] ----------Z t4485 = LCL_VAR int V16 loc12 x12 REG x12 BB225 bottom (BB225->BB226): move V20 from x9 to STK (Join) N001 ( 1, 1) [004486] ----------Z t4486 = LCL_VAR int V20 loc16 x9 REG x9 BB225 bottom (BB225->BB226): move V36 from x0 to STK (Join) N001 ( 1, 1) [004487] ----------Z t4487 = LCL_VAR long V36 loc32 x0 REG x0 BB225 bottom (BB225->BB226): move V144 from x8 to STK (Join) N001 ( 1, 1) [004488] ----------Z t4488 = LCL_VAR int V144 tmp104 x8 REG x8 BB226 bottom (BB226->BB245): move V36 from STK to x0 (Join) N001 ( 1, 1) [004489] ----------z t4489 = LCL_VAR long V36 loc32 x0 REG x0 BB226 bottom (BB226->BB245): move V14 from STK to x3 (Join) N001 ( 1, 1) [004490] ----------z t4490 = LCL_VAR int V14 loc10 x3 REG x3 BB226 bottom (BB226->BB245): move V144 from STK to x8 (Join) N001 ( 1, 1) [004491] ----------z t4491 = LCL_VAR int V144 tmp104 x8 REG x8 BB226 bottom (BB226->BB245): move V20 from STK to x9 (Join) N001 ( 1, 1) [004492] ----------z t4492 = LCL_VAR int V20 loc16 x9 REG x9 BB229 top (BB227->BB229): move V20 from x9 to STK (Split) N001 ( 1, 1) [004493] ----------Z t4493 = LCL_VAR int V20 loc16 x9 REG x9 BB229 top (BB227->BB229): move V36 from x0 to STK (Split) N001 ( 1, 1) [004494] ----------Z t4494 = LCL_VAR long V36 loc32 x0 REG x0 BB229 top (BB227->BB229): move V144 from x8 to STK (Split) N001 ( 1, 1) [004495] ----------Z t4495 = LCL_VAR int V144 tmp104 x8 REG x8 BB229 top (BB227->BB229): move V09 from x5 to STK (Split) N001 ( 1, 1) [004496] ----------Z t4496 = LCL_VAR bool V09 loc5 x5 REG x5 BB229 bottom (BB229->BB230): move V36 from STK to x0 (Join) N001 ( 1, 1) [004497] ----------z t4497 = LCL_VAR long V36 loc32 x0 REG x0 BB229 bottom (BB229->BB230): move V09 from STK to x5 (Join) N001 ( 1, 1) [004498] ----------z t4498 = LCL_VAR bool V09 loc5 x5 REG x5 BB229 bottom (BB229->BB230): move V144 from STK to x8 (Join) N001 ( 1, 1) [004499] ----------z t4499 = LCL_VAR int V144 tmp104 x8 REG x8 BB229 bottom (BB229->BB230): move V20 from STK to x9 (Join) N001 ( 1, 1) [004500] ----------z t4500 = LCL_VAR int V20 loc16 x9 REG x9 BB234 bottom (BB234->BB239): move V16 from STK to x4 (Join) N001 ( 1, 1) [004501] ----------z t4501 = LCL_VAR int V16 loc12 x4 REG x4 BB235 top (BB233->BB235): move V20 from x9 to STK (Split) N001 ( 1, 1) [004502] ----------Z t4502 = LCL_VAR int V20 loc16 x9 REG x9 BB235 top (BB233->BB235): move V14 from x3 to STK (Split) N001 ( 1, 1) [004503] ----------Z t4503 = LCL_VAR int V14 loc10 x3 REG x3 BB235 top (BB233->BB235): move V36 from x0 to STK (Split) N001 ( 1, 1) [004504] ----------Z t4504 = LCL_VAR long V36 loc32 x0 REG x0 BB235 top (BB233->BB235): move V144 from x8 to STK (Split) N001 ( 1, 1) [004505] ----------Z t4505 = LCL_VAR int V144 tmp104 x8 REG x8 BB235 bottom (BB235->BB239): move V36 from STK to x0 (Join) N001 ( 1, 1) [004506] ----------z t4506 = LCL_VAR long V36 loc32 x0 REG x0 BB235 bottom (BB235->BB239): move V14 from STK to x3 (Join) N001 ( 1, 1) [004507] ----------z t4507 = LCL_VAR int V14 loc10 x3 REG x3 BB235 bottom (BB235->BB239): move V16 from STK to x4 (Join) N001 ( 1, 1) [004508] ----------z t4508 = LCL_VAR int V16 loc12 x4 REG x4 BB235 bottom (BB235->BB239): move V144 from STK to x8 (Join) N001 ( 1, 1) [004509] ----------z t4509 = LCL_VAR int V144 tmp104 x8 REG x8 BB235 bottom (BB235->BB239): move V20 from STK to x9 (Join) N001 ( 1, 1) [004510] ----------z t4510 = LCL_VAR int V20 loc16 x9 REG x9 BB237 bottom (BB237->BB239): move V16 from STK to x4 (Join) N001 ( 1, 1) [004511] ----------z t4511 = LCL_VAR int V16 loc12 x4 REG x4 BB238 top (BB236->BB238): move V20 from x9 to STK (Split) N001 ( 1, 1) [004512] ----------Z t4512 = LCL_VAR int V20 loc16 x9 REG x9 BB238 top (BB236->BB238): move V14 from x3 to STK (Split) N001 ( 1, 1) [004513] ----------Z t4513 = LCL_VAR int V14 loc10 x3 REG x3 BB238 top (BB236->BB238): move V36 from x0 to STK (Split) N001 ( 1, 1) [004514] ----------Z t4514 = LCL_VAR long V36 loc32 x0 REG x0 BB238 top (BB236->BB238): move V144 from x8 to STK (Split) N001 ( 1, 1) [004515] ----------Z t4515 = LCL_VAR int V144 tmp104 x8 REG x8 BB238 bottom (BB238->BB239): move V36 from STK to x0 (Join) N001 ( 1, 1) [004516] ----------z t4516 = LCL_VAR long V36 loc32 x0 REG x0 BB238 bottom (BB238->BB239): move V14 from STK to x3 (Join) N001 ( 1, 1) [004517] ----------z t4517 = LCL_VAR int V14 loc10 x3 REG x3 BB238 bottom (BB238->BB239): move V16 from STK to x4 (Join) N001 ( 1, 1) [004518] ----------z t4518 = LCL_VAR int V16 loc12 x4 REG x4 BB238 bottom (BB238->BB239): move V144 from STK to x8 (Join) N001 ( 1, 1) [004519] ----------z t4519 = LCL_VAR int V144 tmp104 x8 REG x8 BB238 bottom (BB238->BB239): move V20 from STK to x9 (Join) N001 ( 1, 1) [004520] ----------z t4520 = LCL_VAR int V20 loc16 x9 REG x9 BB241 bottom (BB241->BB245): move V16 from x4 to STK (Join) N001 ( 1, 1) [004521] ----------Z t4521 = LCL_VAR int V16 loc12 x4 REG x4 BB243 bottom (BB243->BB245): move V14 from STK to x3 (Join) N001 ( 1, 1) [004522] ----------z t4522 = LCL_VAR int V14 loc10 x3 REG x3 BB244 bottom (BB244->BB245): move V36 from STK to x0 (Join) N001 ( 1, 1) [004523] ----------z t4523 = LCL_VAR long V36 loc32 x0 REG x0 BB244 bottom (BB244->BB245): move V14 from STK to x3 (Join) N001 ( 1, 1) [004524] ----------z t4524 = LCL_VAR int V14 loc10 x3 REG x3 BB244 bottom (BB244->BB245): move V144 from STK to x8 (Join) N001 ( 1, 1) [004525] ----------z t4525 = LCL_VAR int V144 tmp104 x8 REG x8 BB244 bottom (BB244->BB245): move V20 from STK to x9 (Join) N001 ( 1, 1) [004526] ----------z t4526 = LCL_VAR int V20 loc16 x9 REG x9 Set V00 argument initial register to x19 Set V01 argument initial register to x21 Set V03 argument initial register to x20 Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..061)-> BB10 ( cond ) i bwd LIR BB255 [0364] 1 BB09 8 [061..083)-> BB31,BB17,BB259,BB30,BB259,BB31 (switch) i bwd LIR BB259 [0368] 2 BB255(2) 4 [???..???)-> BB47 (always) internal bwd LIR BB10 [0009] 1 BB09 8 1 [083..083)-> BB11 ( cond ) i bwd LIR BB256 [0365] 1 BB10 8 [083..0A1)-> BB23,BB260,BB21,BB260,BB18 (switch) i bwd LIR BB260 [0369] 2 BB256(2) 4 [???..???)-> BB47 (always) internal bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB255 8 1 [0CF..0D8)-> BB47 (always) i bwd LIR BB18 [0017] 1 BB256 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd LIR BB21 [0020] 1 BB256 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB256 8 1 [0FB..102)-> BB47 ( cond ) i bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd LIR BB30 [0029] 1 BB255 8 1 [12C..137)-> BB47 (always) i bwd LIR BB31 [0031] 3 BB32,BB255(2) 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd LIR BB261 [0370] 1 BB43 4 [???..???) internal bwd LIR BB44 [0044] 3 BB39,BB45,BB261 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd LIR BB47 [0047] 22 BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB259,BB260 64 1 [204..20F)-> BB50 ( cond ) i bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB262 ( cond ) i idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB262 [0371] 1 BB78 0.50 [???..???)-> BB103 (always) internal LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd LIR BB103 [0096] 4 BB85,BB89,BB102,BB262 1 [3C8..3D0)-> BB112 ( cond ) i LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i LIR BB245 [0190] 25 BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB266,BB268 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB263 ( cond ) i Loop Loop0 bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB264 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB264 [0373] 1 BB115 1 [???..???)-> BB135 (always) internal bwd LIR BB263 [0372] 1 BB113 1 [???..???)-> BB136 (always) internal bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB265 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB265 [0374] 1 BB125 4 [???..???)-> BB134 (always) internal bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd LIR BB134 [0114] 3 BB124,BB133,BB265 8 3 [461..46D) i bwd LIR BB135 [0115] 3 BB114,BB134,BB264 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src LIR BB136 [0116] 3 BB117,BB135,BB263 2 3 [472..478)-> BB141 ( cond ) i bwd LIR BB137 [0117] 1 BB136 2 3 [478..478)-> BB138 ( cond ) i bwd LIR BB257 [0366] 1 BB137 2 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194 (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..49A)-> BB139 ( cond ) i bwd LIR BB258 [0367] 1 BB138 2 [49A..4B8)-> BB266,BB242,BB171,BB242,BB145 (switch) i bwd LIR BB266 [0375] 1 BB258 1 [???..???)-> BB245 (always) internal bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB257,BB258 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB267 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB267 [0376] 1 BB161 1 [???..???)-> BB170 (always) internal bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd LIR BB170 [0142] 4 BB156,BB160,BB169,BB267 2 3 [559..564)-> BB245 (always) i bwd LIR BB171 [0143] 1 BB258 2 3 [564..571)-> BB245 ( cond ) i bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd LIR BB186 [0149] 1 BB257 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd LIR BB194 [0151] 4 BB192,BB193,BB257(2) 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB268 ( cond ) i bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB268 [0377] 1 BB197 1 [???..???)-> BB245 (always) internal bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB269 ( cond ) i bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB269 [0378] 1 BB215 1 [???..???)-> BB244 (always) internal bwd LIR BB218 [0172] 2 BB207,BB271 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB271 ( cond ) i bwd bwd-src LIR BB270 [0379] 1 BB220 8 [???..???) internal bwd LIR BB221 [0175] 2 BB219,BB270 2 3 [701..707)-> BB223 ( cond ) i bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB271 [0380] 1 BB220 8 [???..???)-> BB218 (always) internal bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB140,BB143,BB257(2),BB258(2) 2 3 [7A2..7AA)-> BB272 ( cond ) i bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB272 [0381] 1 BB242 1 [???..???)-> BB244 (always) internal bwd LIR BB244 [0355] 2 BB269,BB272 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd LIR BB254 [0363] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} N003 (???,???) [003780] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t0 byref N007 (???,???) [004185] ----------- t4185 = * PUTARG_REG byref REG x0 N009 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn REG x11 $42 /--* t2543 long N011 (???,???) [004186] ----------- t4186 = * PUTARG_REG long REG x11 /--* t4185 byref this in x0 +--* t4186 long r2r cell in x11 N013 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void REG NA $VN.Void N015 (???,???) [003781] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N017 ( 1, 2) [000002] -c--------- t2 = CNS_INT int 0 REG NA $c0 /--* t2 int N019 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 x22 REG x22 N021 (???,???) [003782] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] REG NA N023 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 N025 ( 1, 2) [002547] -c--------- t2547 = CNS_INT long 16 REG NA $200 /--* t2546 byref +--* t2547 long N027 ( 3, 4) [002548] -----O----- t2548 = * ADD byref REG x0 $240 /--* t2548 byref N029 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 x0 REG x0 N031 (???,???) [003783] ----------- IL_OFFSET void INLRT @ 0x009[E-] REG NA N033 ( 1, 2) [001497] -c--------- t1497 = CNS_INT int 0 REG NA $c0 N035 ( 1, 1) [001502] ----------- t1502 = LCL_VAR byref V76 tmp36 u:1 x0 REG x0 $240 /--* t1502 byref N037 ( 3, 4) [002556] -c--------- t2556 = * LEA(b+8) byref REG NA /--* t2556 byref N039 ( 4, 3) [001503] ---XG------ t1503 = * IND int REG x1 /--* t1497 int +--* t1503 int N041 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N043 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 x0 (last use) REG x0 $240 /--* t1501 byref N045 ( 3, 2) [001505] n---GO----- t1505 = * IND byref REG x23 /--* t1505 byref N047 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 x23 REG x23 N049 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 x23 (last use) REG x23 /--* t2552 long N051 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 x23 REG x23 N053 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] x24 REG x24 $246 /--* t2558 byref N055 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 x24 REG x24 N057 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 x24 REG x24 $246 /--* t3710 byref N059 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 x0 REG x0 N061 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] x25 REG x25 $342 /--* t2561 int N063 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 x25 REG x25 N065 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t3690 int N067 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 x1 REG x1 N069 (???,???) [003784] ----------- IL_OFFSET void INLRT @ 0x011[E-] REG NA N071 ( 1, 1) [000011] ----------- t11 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t11 long N073 ( 4, 3) [000012] ---XG------ t12 = * IND ubyte REG x2 N075 ( 1, 2) [000013] -c--------- t13 = CNS_INT int 0 REG NA $c0 /--* t12 ubyte +--* t13 int N077 ( 6, 6) [000014] CEQ---XG--N--- * JCMP void REG NA ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N081 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 x0 (last use) REG x0 $246 /--* t2565 byref N083 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 x0 REG x0 N085 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 x1 (last use) REG x1 $342 /--* t2568 int N087 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 x1 REG x1 N089 ( 1, 1) [001472] ----------- t1472 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1472 byref N091 ( 3, 4) [002572] -c--------- t2572 = * LEA(b+8) byref REG NA /--* t2572 byref N093 ( 5, 4) [001473] n---GO----- t1473 = * IND bool REG x2 N095 ( 1, 2) [001474] -c--------- t1474 = CNS_INT int 0 REG NA $c0 /--* t1473 bool +--* t1474 int N097 ( 7, 7) [001475] CNE----GO-N--- * JCMP void REG NA ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} N101 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 x0 (last use) REG x0 $246 /--* t2574 byref N103 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 x0 REG x0 N105 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 x1 (last use) REG x1 $342 /--* t2577 int N107 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 x1 REG x1 N109 ( 1, 2) [001489] -c--------- t1489 = CNS_INT int 0 REG NA $c0 /--* t1489 int N111 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 x2 REG x2 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} N115 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 x0 (last use) REG x0 $246 /--* t2581 byref N117 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 x0 REG x0 N119 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 x1 (last use) REG x1 $342 /--* t2584 int N121 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 x1 REG x1 N123 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 REG x2 $c1 /--* t1482 int N125 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 x2 REG x2 ------------ BB05 [025..026), preds={BB01} succs={BB06} N129 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 x0 (last use) REG x0 $246 /--* t2588 byref N131 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 x0 REG x0 N133 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 x1 (last use) REG x1 $342 /--* t2591 int N135 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 x1 REG x1 N137 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 REG x2 $c2 /--* t21 int N139 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 x2 REG x2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} N143 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 x0 (last use) REG x0 $246 /--* t2596 byref N145 (???,???) [004187] ----------- t4187 = * PUTARG_REG byref REG x0 N147 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 x1 (last use) REG x1 $342 /--* t2597 int N149 (???,???) [004188] ----------- t4188 = * PUTARG_REG int REG x1 /--* t4187 byref +--* t4188 int N151 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct REG NA $141 N153 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 x2 (last use) REG x2 $281 /--* t29 int N155 (???,???) [004189] ----------- t4189 = * PUTARG_REG int REG x2 N157 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn REG x11 $43 /--* t2594 long N159 (???,???) [004190] ----------- t4190 = * PUTARG_REG long REG x11 /--* t2595 struct arg1 x0,x1 +--* t4189 int arg2 in x2 +--* t4190 long r2r cell in x11 N161 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int REG x0 $2c1 /--* t30 int N163 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 x26 REG x26 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} N167 (???,???) [003785] ----------- IL_OFFSET void INLRT @ 0x02D[E-] REG NA N169 ( 1, 2) [000035] -c--------- t35 = CNS_INT int 0 REG NA $c0 /--* t35 int N171 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 x27 REG x27 N173 (???,???) [003786] ----------- IL_OFFSET void INLRT @ 0x02F[E-] REG NA N175 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 REG x28 $c4 /--* t38 int N177 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 x28 REG x28 N179 (???,???) [003787] ----------- IL_OFFSET void INLRT @ 0x031[E-] REG NA N181 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF REG x3 $c9 /--* t41 int N183 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 NA REG NA N185 (???,???) [003788] ----------- IL_OFFSET void INLRT @ 0x037[E-] REG NA N187 ( 1, 2) [000044] -c--------- t44 = CNS_INT int 0 REG NA $c0 /--* t44 int N189 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 NA REG NA N191 (???,???) [003789] ----------- IL_OFFSET void INLRT @ 0x039[E-] REG NA N193 ( 1, 2) [002598] -c--------- t2598 = CNS_INT int 0 REG NA $c0 /--* t2598 int N195 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 x5 REG x5 N197 (???,???) [003790] ----------- IL_OFFSET void INLRT @ 0x03C[E-] REG NA N199 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 REG x6 $c4 /--* t50 int N201 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 x6 REG x6 N203 (???,???) [003791] ----------- IL_OFFSET void INLRT @ 0x03F[E-] REG NA N205 ( 1, 2) [002599] -c--------- t2599 = CNS_INT int 0 REG NA $c0 /--* t2599 int N207 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 x7 REG x7 N209 (???,???) [003792] ----------- IL_OFFSET void INLRT @ 0x042[E-] REG NA N211 ( 1, 2) [000056] -c--------- t56 = CNS_INT int 0 REG NA $c0 /--* t56 int N213 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 x8 REG x8 N215 (???,???) [003793] ----------- IL_OFFSET void INLRT @ 0x045[E-] REG NA N217 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 x26 REG x26 $283 /--* t59 int N219 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 x1 REG x1 N221 (???,???) [003794] ----------- IL_OFFSET void INLRT @ 0x049[E-] REG NA N223 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 x24 REG x24 $246 /--* t3712 byref N225 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 x9 REG x9 N227 (???,???) [003795] ----------- IL_OFFSET void INLRT @ 0x049[E-] REG NA N229 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 x9 REG x9 $246 /--* t1512 byref N231 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 NA REG NA N233 (???,???) [003796] ----------- IL_OFFSET void INLRT @ 0x051[E-] REG NA N235 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 x9 (last use) REG x9 $246 /--* t69 byref N237 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 x9 REG x9 N239 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 x9 (last use) REG x9 $3c4 /--* t2609 long N241 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 x9 REG x9 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} N313 (???,???) [003797] ----------- IL_OFFSET void INLRT @ 0x05B[E-] REG NA N315 ( 1, 1) [001226] ----------- t1226 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N317 ( 1, 2) [001227] -c--------- t1227 = CNS_INT int 69 REG NA $d2 /--* t1226 int +--* t1227 int N319 ( 3, 4) [001228] N------N-U- * GT void REG NA N321 ( 5, 6) [001229] ----------- * JTRUE void REG NA $VN.Void ------------ BB09 [061..061) -> BB10 (cond), preds={BB08} succs={BB255,BB10} N325 (???,???) [003798] ----------- IL_OFFSET void INLRT @ 0x061[E-] REG NA N327 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N329 ( 1, 2) [001362] -c--------- t1362 = CNS_INT int -34 REG NA $d6 /--* t1361 int +--* t1362 int N331 ( 3, 4) [001363] ----------- t1363 = * ADD int REG x14 /--* t1363 int N333 (???,???) [004192] DA--------- * STORE_LCL_VAR int V182 rat0 x14 REG x14 N335 ( 3, 2) [004194] ----------- t4194 = LCL_VAR int V182 rat0 x14 REG x14 N337 ( 1, 2) [004195] -c--------- t4195 = CNS_INT int 5 REG NA /--* t4194 int +--* t4195 int N339 ( 8, 5) [004196] ---------U- * GT void REG NA N341 ( 10, 7) [004197] ----------- * JTRUE void REG NA ------------ BB255 [061..083) -> BB31,BB17,BB259,BB30,BB259,BB31 (switch), preds={BB09} succs={BB17,BB30,BB31,BB259} N3689 (???,???) [004198] ----------- t4198 = LCL_VAR int V182 rat0 x14 (last use) REG x14 /--* t4198 int N3691 (???,???) [004199] ---------U- t4199 = * CAST long <- ulong <- uint REG x0 N3693 (???,???) [004200] ----------- t4200 = JMPTABLE long REG x1 /--* t4199 long +--* t4200 long N3695 (???,???) [004201] ----------- * SWITCH_TABLE void REG NA ------------ BB259 [???..???) -> BB47 (always), preds={BB255(2)} succs={BB47} N001 ( 1, 1) [004305] ----------- t4305 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4305 int N002 ( 2, 2) [004306] ----------- t4306 = * COPY int REG x1 ------------ BB10 [083..083) -> BB11 (cond), preds={BB09} succs={BB256,BB11} N345 (???,???) [003799] ----------- IL_OFFSET void INLRT @ 0x083[E-] REG NA N347 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N349 ( 1, 2) [001366] -c--------- t1366 = CNS_INT int -44 REG NA $d7 /--* t1365 int +--* t1366 int N351 ( 3, 4) [001367] ----------- t1367 = * ADD int REG x12 /--* t1367 int N353 (???,???) [004203] DA--------- * STORE_LCL_VAR int V183 rat1 x12 REG x12 N355 ( 3, 2) [004205] ----------- t4205 = LCL_VAR int V183 rat1 x12 REG x12 N357 ( 1, 2) [004206] -c--------- t4206 = CNS_INT int 4 REG NA /--* t4205 int +--* t4206 int N359 ( 8, 5) [004207] ---------U- * GT void REG NA N361 ( 10, 7) [004208] ----------- * JTRUE void REG NA ------------ BB256 [083..0A1) -> BB23,BB260,BB21,BB260,BB18 (switch), preds={BB10} succs={BB18,BB21,BB23,BB260} N3789 (???,???) [004209] ----------- t4209 = LCL_VAR int V183 rat1 x12 (last use) REG x12 /--* t4209 int N3791 (???,???) [004210] ---------U- t4210 = * CAST long <- ulong <- uint REG x13 N3793 (???,???) [004211] ----------- t4211 = JMPTABLE long REG x0 /--* t4210 long +--* t4211 long N3795 (???,???) [004212] ----------- * SWITCH_TABLE void REG NA ------------ BB260 [???..???) -> BB47 (always), preds={BB256(2)} succs={BB47} N001 ( 1, 1) [004307] ----------- t4307 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4307 int N002 ( 2, 2) [004308] ----------- t4308 = * COPY int REG x1 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} N365 (???,???) [003800] ----------- IL_OFFSET void INLRT @ 0x0A1[E-] REG NA N367 ( 1, 1) [001369] ----------- t1369 = LCL_VAR int V18 loc14 u:5 x13 (last use) REG x13 N369 ( 1, 2) [001370] -c--------- t1370 = CNS_INT int 69 REG NA $d2 /--* t1369 int +--* t1370 int N371 ( 3, 4) [001371] J------N--- * EQ void REG NA N373 ( 5, 6) [001372] ----------- * JTRUE void REG NA $VN.Void ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} N001 ( 1, 1) [004365] ----------- t4365 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4365 int N002 ( 2, 2) [004366] ----------- t4366 = * COPY int REG x1 ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} N379 (???,???) [003801] ----------- IL_OFFSET void INLRT @ 0x0AF[E-] REG NA N381 ( 1, 1) [001230] ----------- t1230 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N383 ( 1, 2) [001231] -c--------- t1231 = CNS_INT int 92 REG NA $d3 /--* t1230 int +--* t1231 int N385 ( 3, 4) [001232] J------N--- * EQ void REG NA N387 ( 5, 6) [001233] ----------- * JTRUE void REG NA $VN.Void ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} N391 (???,???) [003802] ----------- IL_OFFSET void INLRT @ 0x0B8[E-] REG NA N393 ( 1, 1) [001257] ----------- t1257 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N395 ( 1, 2) [001258] -c--------- t1258 = CNS_INT int 101 REG NA $d4 /--* t1257 int +--* t1258 int N397 ( 3, 4) [001259] J------N--- * EQ void REG NA N399 ( 5, 6) [001260] ----------- * JTRUE void REG NA $VN.Void ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} N403 (???,???) [003803] ----------- IL_OFFSET void INLRT @ 0x0C1[E-] REG NA N405 ( 1, 1) [001352] ----------- t1352 = LCL_VAR int V18 loc14 u:5 x13 (last use) REG x13 N407 ( 1, 4) [001353] ----------- t1353 = CNS_INT int 0x2030 REG x1 $d5 /--* t1352 int +--* t1353 int N409 ( 3, 6) [001354] J------N--- * NE void REG NA N001 ( 1, 1) [004309] ----------- t4309 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4309 int N002 ( 2, 2) [004310] ----------- t4310 = * COPY int REG x1 N411 ( 5, 8) [001355] ----------- * JTRUE void REG NA $VN.Void ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} N415 (???,???) [003804] ----------- IL_OFFSET void INLRT @ 0x137[E-] REG NA N417 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 x8 (last use) REG x8 $289 N419 ( 1, 2) [001357] -c--------- t1357 = CNS_INT int 3 REG NA $c3 /--* t1356 int +--* t1357 int N421 ( 3, 4) [001358] ----------- t1358 = * ADD int REG x8 $376 /--* t1358 int N423 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 x8 REG x8 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB255} succs={BB47} N3699 (???,???) [003805] ----------- IL_OFFSET void INLRT @ 0x0CF[E-] REG NA N3701 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 x27 (last use) REG x27 $28a N3703 ( 1, 2) [001431] -c--------- t1431 = CNS_INT int 1 REG NA $c1 /--* t1430 int +--* t1431 int N3705 ( 3, 4) [001432] ----------- t1432 = * ADD int REG x27 $68f /--* t1432 int N3707 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 x27 REG x27 N001 ( 1, 1) [004367] ----------- t4367 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4367 int N002 ( 2, 2) [004368] ----------- t4368 = * COPY int REG x1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB256} succs={BB19,BB20} N3799 (???,???) [003806] ----------- IL_OFFSET void INLRT @ 0x0D8[E-] REG NA N3801 ( 1, 1) [001373] ----------z t1373 = LCL_VAR int V06 loc2 u:2 x3 REG x3 $284 N3803 ( 1, 4) [001374] ----------- t1374 = CNS_INT int 0x7FFFFFFF REG x4 $c9 /--* t1373 int +--* t1374 int N3805 ( 3, 6) [001375] N------N-U- * NE void REG NA $68e N3807 ( 5, 8) [001376] ----------- * JTRUE void REG NA $VN.Void ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} N3811 (???,???) [003807] ----------- IL_OFFSET void INLRT @ 0x0E0[E-] REG NA N3813 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1385 int N3815 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 x3 REG x3 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} N3819 (???,???) [003808] ----------- IL_OFFSET void INLRT @ 0x0E2[E-] REG NA N3821 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 x27 (last use) REG x27 $28a N3823 ( 1, 2) [001378] -c--------- t1378 = CNS_INT int 1 REG NA $c1 /--* t1377 int +--* t1378 int N3825 ( 3, 4) [001379] ----------- t1379 = * ADD int REG x27 $68f /--* t1379 int N3827 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 x27 REG x27 N3829 (???,???) [003809] ----------- IL_OFFSET void INLRT @ 0x0E6[E-] REG NA N3831 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 x27 REG x27 $68f /--* t1382 int N3833 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 x2 REG x2 N001 ( 1, 1) [004369] ----------Z t4369 = LCL_VAR int V06 loc2 x3 REG x3 N001 ( 1, 1) [004370] ----------Z t4370 = LCL_VAR int V07 loc3 x2 REG x2 N001 ( 1, 1) [004371] ----------- t4371 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4371 int N002 ( 2, 2) [004372] ----------- t4372 = * COPY int REG x1 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB256} succs={BB22,BB47} N3837 (???,???) [003810] ----------- IL_OFFSET void INLRT @ 0x0ED[E-] REG NA N3839 ( 1, 1) [001388] ----------- t1388 = LCL_VAR int V05 loc1 u:2 x28 REG x28 $286 N3841 ( 1, 2) [001389] -c--------- t1389 = CNS_INT int 0 REG NA $c0 /--* t1388 int +--* t1389 int N3843 ( 3, 4) [001390] J------N--- * GE void REG NA $690 N001 ( 1, 1) [004311] ----------- t4311 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4311 int N002 ( 2, 2) [004312] ----------- t4312 = * COPY int REG x1 N3845 ( 5, 6) [001391] ----------- * JTRUE void REG NA $VN.Void ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} N3849 (???,???) [003811] ----------- IL_OFFSET void INLRT @ 0x0F4[E-] REG NA N3851 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1392 int N3853 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 x28 REG x28 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB256} succs={BB24,BB47} N3857 (???,???) [003812] ----------- IL_OFFSET void INLRT @ 0x0FB[E-] REG NA N3859 ( 1, 1) [001395] ----------- t1395 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a N3861 ( 1, 2) [001396] -c--------- t1396 = CNS_INT int 0 REG NA $c0 /--* t1395 int +--* t1396 int N3863 ( 6, 4) [001397] -c-----N--- t1397 = * LE int REG NA $691 N3865 ( 1, 1) [001399] ----------- t1399 = LCL_VAR int V05 loc1 u:2 x28 REG x28 $286 N3867 ( 1, 2) [001400] -c--------- t1400 = CNS_INT int 0 REG NA $c0 /--* t1399 int +--* t1400 int N3869 ( 6, 4) [001401] -c-----N--- t1401 = * GE int REG NA $690 /--* t1397 int +--* t1401 int N3871 ( 13, 9) [003726] Jc-----N--- * AND void REG NA N001 ( 1, 1) [004313] ----------- t4313 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4313 int N002 ( 2, 2) [004314] ----------- t4314 = * COPY int REG x1 N3873 ( 15, 11) [001398] ----------- * JTRUE void REG NA $VN.Void ------------ BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} N3877 (???,???) [003813] ----------- IL_OFFSET void INLRT @ 0x102[E-] REG NA N3879 (???,???) [003814] ----------- IL_OFFSET void INLRT @ 0x109[E-] REG NA N3881 ( 1, 1) [001403] ----------- t1403 = LCL_VAR int V10 loc6 u:2 x6 REG x6 $287 N3883 ( 1, 2) [001404] -c--------- t1404 = CNS_INT int 0 REG NA $c0 /--* t1403 int +--* t1404 int N3885 ( 3, 4) [001405] J------N--- * LT void REG NA $692 N3887 ( 5, 6) [001406] ----------- * JTRUE void REG NA $VN.Void ------------ BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} N3891 (???,???) [003815] ----------- IL_OFFSET void INLRT @ 0x10E[E-] REG NA N3893 ( 1, 1) [001413] ----------- t1413 = LCL_VAR int V10 loc6 u:2 x6 REG x6 $287 N3895 ( 1, 1) [001414] ----------- t1414 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1413 int +--* t1414 int N3897 ( 3, 3) [001415] N------N-U- * NE void REG NA $693 N3899 ( 5, 5) [001416] ----------- * JTRUE void REG NA $VN.Void ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} N3903 (???,???) [003816] ----------- IL_OFFSET void INLRT @ 0x113[E-] REG NA N3905 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 x22 (last use) REG x22 $288 N3907 ( 1, 2) [001421] -c--------- t1421 = CNS_INT int 1 REG NA $c1 /--* t1420 int +--* t1421 int N3909 ( 3, 4) [001422] ----------- t1422 = * ADD int REG x22 $694 /--* t1422 int N3911 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 x22 REG x22 ------------ BB28 [11E..121), preds={BB26} succs={BB29} N3915 (???,???) [003817] ----------- IL_OFFSET void INLRT @ 0x11E[E-] REG NA N3917 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 REG x7 $c1 /--* t2612 int N3919 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 NA REG NA N001 ( 1, 1) [004373] ----------z t4373 = LCL_VAR bool V12 loc8 x7 REG x7 ------------ BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} N3923 (???,???) [003818] ----------- IL_OFFSET void INLRT @ 0x121[E-] REG NA N3925 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1407 int N3927 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 x6 REG x6 N3929 (???,???) [003819] ----------- IL_OFFSET void INLRT @ 0x124[E-] REG NA N3931 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 REG x22 $c1 /--* t1410 int N3933 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 x22 REG x22 ------------ BB30 [12C..137) -> BB47 (always), preds={BB255} succs={BB47} N3711 (???,???) [003820] ----------- IL_OFFSET void INLRT @ 0x12C[E-] REG NA N3713 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 x8 (last use) REG x8 $289 N3715 ( 1, 2) [001426] -c--------- t1426 = CNS_INT int 2 REG NA $c2 /--* t1425 int +--* t1426 int N3717 ( 3, 4) [001427] ----------- t1427 = * ADD int REG x8 $695 /--* t1427 int N3719 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 x8 REG x8 N001 ( 1, 1) [004374] ----------- t4374 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4374 int N002 ( 2, 2) [004375] ----------- t4375 = * COPY int REG x1 ------------ BB31 [142..150) -> BB47 (cond), preds={BB32,BB255(2)} succs={BB32,BB47} N3723 (???,???) [003821] ----------- IL_OFFSET void INLRT @ 0x142[E-] REG NA N3725 ( 1, 1) [001435] ----------- t1435 = LCL_VAR int V16 loc12 u:21 x10 REG x10 $2b1 N3727 ( 1, 1) [003693] ----------- t3693 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1435 int +--* t3693 int N3729 ( 6, 3) [001440] -c-----N--- t1440 = * GE int REG NA $8b7 N3731 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N3733 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 x10 REG x10 $2b1 /--* t1443 int N3735 ( 2, 3) [001444] -c--------- t1444 = * CAST long <- int REG NA $3de N3737 ( 1, 2) [001446] -c--------- t1446 = CNS_INT long 1 REG NA $204 /--* t1444 long +--* t1446 long N3739 ( 4, 6) [001447] -c--------- t1447 = * BFIZ long REG NA /--* t1442 long +--* t1447 long N3741 ( 6, 8) [001448] -c--------- t1448 = * LEA(b+(i*1)+0) long REG NA /--* t1448 long N3743 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort REG x0 /--* t1449 ushort N3745 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 x0 REG x0 N3747 ( 1, 1) [003626] ----------- t3626 = LCL_VAR int V171 cse0 u:1 x0 REG x0 N3749 ( 1, 2) [001450] -c--------- t1450 = CNS_INT int 0 REG NA $c0 /--* t3626 int +--* t1450 int N3751 ( 15, 14) [001451] -c-XG--N--- t1451 = * EQ int REG NA /--* t1440 int +--* t1451 int N3753 ( 22, 18) [003728] Jc-XG--N--- * AND void REG NA N001 ( 1, 1) [004315] ----------- t4315 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4315 int N002 ( 2, 2) [004316] ----------- t4316 = * COPY int REG x1 N3755 ( 24, 20) [001441] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} N3759 (???,???) [003822] ----------- IL_OFFSET void INLRT @ 0x150[E-] REG NA N3761 (???,???) [003823] ----------- IL_OFFSET void INLRT @ 0x15E[E-] REG NA N3763 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 x1 (last use) REG x1 $2b1 /--* t1454 int N3765 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 x1 REG x1 N3767 (???,???) [003824] ----------- IL_OFFSET void INLRT @ 0x15E[E-] REG NA N3769 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 x1 (last use) REG x1 $2b1 N3771 ( 1, 2) [001456] -c--------- t1456 = CNS_INT int 1 REG NA $c1 /--* t1455 int +--* t1456 int N3773 ( 3, 4) [001457] ----------- t1457 = * ADD int REG x1 $8bc /--* t1457 int N3775 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 NA REG NA N3777 ( 1, 1) [003628] ----------- t3628 = LCL_VAR int V171 cse0 u:1 x0 (last use) REG x0 N3779 ( 1, 1) [001469] ----------- t1469 = LCL_VAR int V18 loc14 u:5 x13 REG x13 /--* t3628 int +--* t1469 int N3781 ( 3, 3) [001470] N---G--N-U- * NE void REG NA N001 ( 1, 1) [004317] ----------z t4317 = LCL_VAR int V16 loc12 x10 REG x10 N3783 ( 5, 5) [001471] ----G------ * JTRUE void REG NA $876 ------------ BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} N001 ( 1, 1) [004376] ----------- t4376 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4376 int N002 ( 2, 2) [004377] ----------- t4377 = * COPY int REG x1 ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} N427 (???,???) [003825] ----------- IL_OFFSET void INLRT @ 0x175[E-] REG NA N429 ( 1, 1) [001234] ----------- t1234 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 N431 ( 1, 1) [003694] ----------- t3694 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1234 int +--* t3694 int N433 ( 6, 3) [001239] -c-----N--- t1239 = * GE int REG NA $36c N435 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N437 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 /--* t1242 int N439 ( 2, 3) [001243] -c--------- t1243 = * CAST long <- int REG NA $3c8 N441 ( 1, 2) [001245] -c--------- t1245 = CNS_INT long 1 REG NA $204 /--* t1243 long +--* t1245 long N443 ( 4, 6) [001246] -c--------- t1246 = * BFIZ long REG NA /--* t1241 long +--* t1246 long N445 ( 6, 8) [001247] -c--------- t1247 = * LEA(b+(i*1)+0) long REG NA /--* t1247 long N447 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort REG x1 /--* t1248 ushort N449 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 x1 REG x1 N451 ( 1, 1) [003646] ----------- t3646 = LCL_VAR int V174 cse3 x1 (last use) REG x1 N453 ( 1, 2) [001249] -c--------- t1249 = CNS_INT int 0 REG NA $c0 /--* t3646 int +--* t1249 int N455 ( 15, 14) [001250] -c-XG--N--- t1250 = * EQ int REG NA /--* t1239 int +--* t1250 int N457 ( 22, 18) [003730] Jc-XG--N--- * AND void REG NA N001 ( 1, 1) [004318] ----------- t4318 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4318 int N002 ( 2, 2) [004319] ----------- t4319 = * COPY int REG x1 N459 ( 24, 20) [001240] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} N463 (???,???) [003826] ----------- IL_OFFSET void INLRT @ 0x183[E-] REG NA N465 (???,???) [003827] ----------- IL_OFFSET void INLRT @ 0x18E[E-] REG NA N467 ( 1, 1) [001252] ----------- t1252 = LCL_VAR int V16 loc12 u:17 x1 (last use) REG x1 $361 N469 ( 1, 2) [001253] -c--------- t1253 = CNS_INT int 1 REG NA $c1 /--* t1252 int +--* t1253 int N471 ( 3, 4) [001254] ----------- t1254 = * ADD int REG x1 $371 /--* t1254 int N473 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 x1 REG x1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} N477 (???,???) [003828] ----------- IL_OFFSET void INLRT @ 0x196[E-] REG NA N479 ( 1, 1) [001261] ----------- t1261 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 N481 ( 1, 1) [003695] ----------- t3695 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1261 int +--* t3695 int N483 ( 3, 3) [001266] J------N--- * GE void REG NA $36c N485 ( 5, 5) [001267] ----------- * JTRUE void REG NA $VN.Void ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} N489 (???,???) [003829] ----------- IL_OFFSET void INLRT @ 0x1A1[E-] REG NA N491 ( 1, 1) [001341] ----------- t1341 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N493 ( 1, 1) [001342] ----------- t1342 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 /--* t1342 int N495 ( 2, 3) [001343] -c--------- t1343 = * CAST long <- int REG NA $3c8 N497 ( 1, 2) [001345] -c--------- t1345 = CNS_INT long 1 REG NA $204 /--* t1343 long +--* t1345 long N499 ( 4, 6) [001346] -c--------- t1346 = * BFIZ long REG NA /--* t1341 long +--* t1346 long N501 ( 6, 8) [001347] -c--------- t1347 = * LEA(b+(i*1)+0) long REG NA /--* t1347 long N503 ( 9, 10) [001348] ---XG------ t1348 = * IND ushort REG x1 /--* t1348 ushort N505 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 x1 REG x1 N507 ( 1, 1) [003650] ----------- t3650 = LCL_VAR int V174 cse3 x1 (last use) REG x1 N509 ( 1, 2) [001349] -c--------- t1349 = CNS_INT int 48 REG NA $d8 /--* t3650 int +--* t1349 int N511 ( 12, 14) [001350] J--XG--N--- * EQ void REG NA N513 ( 14, 16) [001351] ---XG------ * JTRUE void REG NA $311 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} N517 (???,???) [003830] ----------- IL_OFFSET void INLRT @ 0x1AE[E-] REG NA N519 ( 1, 1) [001268] ----------- t1268 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 N521 ( 1, 2) [001269] -c--------- t1269 = CNS_INT int 1 REG NA $c1 /--* t1268 int +--* t1269 int N523 ( 3, 4) [001270] ----------- t1270 = * ADD int REG x1 $371 N525 ( 1, 1) [003696] ----------- t3696 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1270 int +--* t3696 int N527 ( 5, 6) [001275] J------N--- * GE void REG NA $681 N001 ( 1, 1) [004320] ----------- t4320 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4320 int N002 ( 2, 2) [004321] ----------- t4321 = * COPY int REG x1 N529 ( 7, 8) [001276] ----------- * JTRUE void REG NA $VN.Void ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} N533 (???,???) [003831] ----------- IL_OFFSET void INLRT @ 0x1BB[E-] REG NA N535 ( 1, 1) [001277] ----------- t1277 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N537 ( 1, 1) [001278] ----------- t1278 = LCL_VAR int V16 loc12 u:17 x1 REG x1 $361 /--* t1278 int N539 ( 2, 3) [001279] -c--------- t1279 = * CAST long <- int REG NA $3c8 N541 ( 1, 2) [001281] -c--------- t1281 = CNS_INT long 1 REG NA $204 /--* t1279 long +--* t1281 long N543 ( 4, 6) [001282] -c--------- t1282 = * BFIZ long REG NA /--* t1277 long +--* t1282 long N545 ( 6, 8) [001283] -c--------- t1283 = * LEA(b+(i*1)+0) long REG NA /--* t1283 long N547 ( 9, 10) [001284] ---XG------ t1284 = * IND ushort REG x0 /--* t1284 ushort N549 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 x0 REG x0 N551 ( 1, 1) [003654] ----------- t3654 = LCL_VAR int V174 cse3 x0 REG x0 N553 ( 1, 2) [001285] -c--------- t1285 = CNS_INT int 43 REG NA $d9 /--* t3654 int +--* t1285 int N555 ( 12, 14) [001286] J--XG--N--- * EQ void REG NA N557 ( 14, 16) [001287] ---XG------ * JTRUE void REG NA $311 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} N561 (???,???) [003832] ----------- IL_OFFSET void INLRT @ 0x1C8[E-] REG NA N563 ( 1, 1) [003656] ----------- t3656 = LCL_VAR int V174 cse3 x0 (last use) REG x0 N565 ( 1, 2) [001338] -c--------- t1338 = CNS_INT int 45 REG NA $da /--* t3656 int +--* t1338 int N567 ( 3, 4) [001339] N---G--N-U- * NE void REG NA N569 ( 5, 6) [001340] ----G------ * JTRUE void REG NA $311 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB261,BB47} N573 (???,???) [003833] ----------- IL_OFFSET void INLRT @ 0x1D5[E-] REG NA N575 ( 1, 1) [001288] ----------- t1288 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N577 ( 1, 1) [001289] ----------- t1289 = LCL_VAR int V16 loc12 u:17 x1 REG x1 $361 N579 ( 1, 2) [001290] -c--------- t1290 = CNS_INT int 1 REG NA $c1 /--* t1289 int +--* t1290 int N581 ( 3, 4) [001291] ----------- t1291 = * ADD int REG x0 $371 /--* t1291 int N583 ( 4, 6) [001292] -c--------- t1292 = * CAST long <- int REG NA $3cb N585 ( 1, 2) [001294] -c--------- t1294 = CNS_INT long 1 REG NA $204 /--* t1292 long +--* t1294 long N587 ( 6, 9) [001295] -c--------- t1295 = * BFIZ long REG NA /--* t1288 long +--* t1295 long N589 ( 8, 11) [001296] -c--------- t1296 = * LEA(b+(i*1)+0) long REG NA /--* t1296 long N591 ( 11, 13) [001297] ---XG------ t1297 = * IND ushort REG x0 N593 ( 1, 2) [001298] -c--------- t1298 = CNS_INT int 48 REG NA $d8 /--* t1297 ushort +--* t1298 int N595 ( 13, 16) [001299] N--XG--N-U- * NE void REG NA N597 ( 15, 18) [001300] ---XG------ * JTRUE void REG NA $313 ------------ BB261 [???..???), preds={BB43} succs={BB44} N001 ( 1, 1) [004322] ----------- t4322 = LCL_VAR int V16 loc12 x1 REG x1 /--* t4322 int N002 ( 2, 2) [004323] ----------- t4323 = * COPY int REG x10 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB45,BB261} succs={BB45,BB46} N601 (???,???) [003834] ----------- IL_OFFSET void INLRT @ 0x1E4[E-] REG NA N603 ( 1, 1) [001301] ----------- t1301 = LCL_VAR int V16 loc12 u:18 x10 (last use) REG x10 $2b2 N605 ( 1, 2) [001302] -c--------- t1302 = CNS_INT int 1 REG NA $c1 /--* t1301 int +--* t1302 int N607 ( 3, 4) [001303] ----------- t1303 = * ADD int REG x10 $942 /--* t1303 int N609 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 x10 REG x10 N611 ( 1, 1) [001307] ----------- t1307 = LCL_VAR int V73 tmp33 u:1 x10 (last use) REG x10 $942 /--* t1307 int N613 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 x10 REG x10 N615 ( 1, 1) [001306] ----------- t1306 = LCL_VAR int V16 loc12 u:19 x10 REG x10 $942 N617 ( 1, 1) [003697] ----------- t3697 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1306 int +--* t3697 int N619 ( 3, 3) [001314] J------N--- * GE void REG NA $943 N621 ( 5, 5) [001315] ----------- * JTRUE void REG NA $VN.Void ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} N625 (???,???) [003835] ----------- IL_OFFSET void INLRT @ 0x1F4[E-] REG NA N627 ( 1, 1) [001319] ----------- t1319 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N629 ( 1, 1) [001320] ----------- t1320 = LCL_VAR int V16 loc12 u:19 x10 REG x10 $942 /--* t1320 int N631 ( 2, 3) [001321] -c--------- t1321 = * CAST long <- int REG NA $3e1 N633 ( 1, 2) [001323] -c--------- t1323 = CNS_INT long 1 REG NA $204 /--* t1321 long +--* t1323 long N635 ( 4, 6) [001324] -c--------- t1324 = * BFIZ long REG NA /--* t1319 long +--* t1324 long N637 ( 6, 8) [001325] -c--------- t1325 = * LEA(b+(i*1)+0) long REG NA /--* t1325 long N639 ( 9, 10) [001326] ---XG------ t1326 = * IND ushort REG x5 N641 ( 1, 2) [001327] -c--------- t1327 = CNS_INT int 48 REG NA $d8 /--* t1326 ushort +--* t1327 int N643 ( 11, 13) [001328] J--XG--N--- * EQ void REG NA N645 ( 13, 15) [001329] ---XG------ * JTRUE void REG NA $878 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} N649 (???,???) [003836] ----------- IL_OFFSET void INLRT @ 0x201[E-] REG NA N651 ( 1, 2) [002613] ----------- t2613 = CNS_INT int 1 REG x5 $c1 /--* t2613 int N653 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 x5 REG x5 N001 ( 1, 1) [004378] ----------- t4378 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4378 int N002 ( 2, 2) [004379] ----------- t4379 = * COPY int REG x1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB259,BB260} succs={BB48,BB50} N245 (???,???) [003837] ----------- IL_OFFSET void INLRT @ 0x204[E-] REG NA N247 ( 1, 1) [000073] ----------- t73 = LCL_VAR int V16 loc12 u:2 x1 REG x1 $28b N249 ( 1, 1) [003698] ----------- t3698 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t73 int +--* t3698 int N251 ( 3, 3) [000078] J------N--- * GE void REG NA $360 N253 ( 5, 5) [000079] ----------- * JTRUE void REG NA $VN.Void ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} N257 (???,???) [003838] ----------- IL_OFFSET void INLRT @ 0x20F[E-] REG NA N259 ( 1, 1) [001198] ----------- t1198 = LCL_VAR int V16 loc12 u:2 x1 (last use) REG x1 $28b /--* t1198 int N261 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 x1 REG x1 N263 (???,???) [003839] ----------- IL_OFFSET void INLRT @ 0x20F[E-] REG NA N265 ( 1, 1) [001199] ----------- t1199 = LCL_VAR int V71 tmp31 u:1 x1 REG x1 $28b N267 ( 1, 2) [001200] -c--------- t1200 = CNS_INT int 1 REG NA $c1 /--* t1199 int +--* t1200 int N269 ( 3, 4) [001201] ----------- t1201 = * ADD int REG x0 $361 /--* t1201 int N271 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 x10 REG x10 N273 ( 1, 1) [001197] ----------- t1197 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N275 ( 1, 1) [001206] ----------- t1206 = LCL_VAR int V71 tmp31 u:1 x1 (last use) REG x1 $28b /--* t1206 int N277 ( 2, 3) [001207] -c--------- t1207 = * CAST long <- int REG NA $3c5 N279 ( 1, 2) [001209] -c--------- t1209 = CNS_INT long 1 REG NA $204 /--* t1207 long +--* t1209 long N281 ( 4, 6) [001210] -c--------- t1210 = * BFIZ long REG NA /--* t1197 long +--* t1210 long N283 ( 6, 8) [001211] -c--------- t1211 = * LEA(b+(i*1)+0) long REG NA /--* t1211 long N285 ( 9, 10) [001212] ---XG------ t1212 = * IND ushort REG x13 /--* t1212 ushort N287 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 x13 REG x13 N289 ( 1, 1) [001216] ----------- t1216 = LCL_VAR int V72 tmp32 u:1 x13 (last use) REG x13 /--* t1216 int N291 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 x13 REG x13 N293 ( 1, 1) [001215] ----------- t1215 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N295 ( 1, 2) [001219] -c--------- t1219 = CNS_INT int 0 REG NA $c0 /--* t1215 int +--* t1219 int N297 ( 3, 4) [001220] CEQ-------N--- * JCMP void REG NA ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} N301 (???,???) [003840] ----------- IL_OFFSET void INLRT @ 0x222[E-] REG NA N303 ( 1, 1) [001222] ----------- t1222 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N305 ( 1, 2) [001223] -c--------- t1223 = CNS_INT int 59 REG NA $d1 /--* t1222 int +--* t1223 int N307 ( 3, 4) [001224] N------N-U- * NE void REG NA N309 ( 5, 6) [001225] ----------- * JTRUE void REG NA $VN.Void ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} N657 (???,???) [003841] ----------- IL_OFFSET void INLRT @ 0x22B[E-] REG NA N659 ( 1, 2) [000081] -c--------- t81 = CNS_INT long 0 REG NA $205 /--* t81 long N661 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 NA REG NA N663 (???,???) [003842] ----------- IL_OFFSET void INLRT @ 0x22F[E-] REG NA N665 ( 1, 1) [000084] ----------- t84 = LCL_VAR int V05 loc1 u:2 x28 REG x28 $286 N667 ( 1, 2) [000085] -c--------- t85 = CNS_INT int 0 REG NA $c0 /--* t84 int +--* t85 int N669 ( 3, 4) [000086] J------N--- * GE void REG NA $690 N671 ( 5, 6) [000087] ----------- * JTRUE void REG NA $VN.Void ------------ BB51 [233..235), preds={BB50} succs={BB52} N675 (???,???) [003843] ----------- IL_OFFSET void INLRT @ 0x233[E-] REG NA N677 ( 1, 1) [001194] ----------- t1194 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1194 int N679 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 x28 REG x28 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} N683 (???,???) [003844] ----------- IL_OFFSET void INLRT @ 0x235[E-] REG NA N685 ( 1, 1) [000088] ----------- t88 = LCL_VAR int V10 loc6 u:2 x6 REG x6 $287 N687 ( 1, 2) [000089] -c--------- t89 = CNS_INT int 0 REG NA $c0 /--* t88 int +--* t89 int N689 ( 3, 4) [000090] J------N--- * LT void REG NA $692 N691 ( 5, 6) [000091] ----------- * JTRUE void REG NA $VN.Void ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} N695 (???,???) [003845] ----------- IL_OFFSET void INLRT @ 0x23A[E-] REG NA N697 ( 1, 1) [001180] ----------- t1180 = LCL_VAR int V10 loc6 u:2 x6 (last use) REG x6 $287 N699 ( 1, 1) [001181] ----------- t1181 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t1180 int +--* t1181 int N701 ( 3, 3) [001182] N------N-U- * NE void REG NA $696 N703 ( 5, 5) [001183] ----------- * JTRUE void REG NA $VN.Void ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} N707 (???,???) [003846] ----------- IL_OFFSET void INLRT @ 0x23F[E-] REG NA N709 ( 1, 1) [001187] ----------- t1187 = LCL_VAR int V13 loc9 u:2 x8 (last use) REG x8 $289 N711 ( 1, 1) [001188] ----------- t1188 = LCL_VAR int V11 loc7 u:3 x22 REG x22 $288 N713 ( 1, 2) [001189] ----------- t1189 = CNS_INT int 3 REG x1 $c3 /--* t1188 int +--* t1189 int N715 ( 6, 6) [001190] -c--------- t1190 = * MUL int REG NA $697 /--* t1187 int +--* t1190 int N717 ( 8, 8) [001191] ----------- t1191 = * SUB int REG x8 $698 /--* t1191 int N719 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 x8 REG x8 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} N723 (???,???) [003847] ----------- IL_OFFSET void INLRT @ 0x24A[E-] REG NA N725 ( 1, 2) [002615] ----------- t2615 = CNS_INT int 1 REG x7 $c1 /--* t2615 int N727 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 NA REG NA N001 ( 1, 1) [004380] ----------z t4380 = LCL_VAR bool V12 loc8 x7 REG x7 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} N731 (???,???) [003848] ----------- IL_OFFSET void INLRT @ 0x24D[E-] REG NA N733 ( 1, 1) [000092] ----------- t92 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t92 long N735 ( 4, 3) [000093] ---XG------ t93 = * IND ubyte REG x1 N737 ( 1, 2) [000094] -c--------- t94 = CNS_INT int 0 REG NA $c0 /--* t93 ubyte +--* t94 int N739 ( 6, 6) [000095] CEQ---XG--N--- * JCMP void REG NA ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} N743 (???,???) [003849] ----------- IL_OFFSET void INLRT @ 0x252[E-] REG NA N745 ( 1, 1) [002618] ----------- t2618 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 N747 ( 1, 2) [002619] -c--------- t2619 = CNS_INT long 4 REG NA $207 /--* t2618 byref +--* t2619 long N749 ( 3, 4) [002620] -----O----- t2620 = * ADD byref REG x1 $24a /--* t2620 byref N751 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 x1 REG x1 N753 ( 1, 1) [001131] ----------- t1131 = LCL_VAR byref V69 tmp29 u:1 x1 REG x1 $24a /--* t1131 byref N755 ( 3, 2) [001132] n---GO----- t1132 = * IND int REG x0 N757 ( 1, 1) [001133] ----------- t1133 = LCL_VAR int V13 loc9 u:3 x8 (last use) REG x8 $28e /--* t1132 int +--* t1133 int N759 ( 5, 4) [001134] ----GO----- t1134 = * ADD int REG x0 N761 ( 1, 1) [001130] ----------- t1130 = LCL_VAR byref V69 tmp29 u:1 x1 (last use) REG x1 $24a /--* t1130 byref +--* t1134 int N763 (???,???) [003850] -A--GO----- * STOREIND int REG NA N765 (???,???) [003851] ----------- IL_OFFSET void INLRT @ 0x25E[E-] REG NA N767 ( 1, 1) [001137] ----------Z t1137 = LCL_VAR int V09 loc5 u:2 x5 REG x5 $4c1 N769 ( 1, 2) [001138] -c--------- t1138 = CNS_INT int 0 REG NA $c0 /--* t1137 int +--* t1138 int N771 ( 3, 4) [001139] CNE-------N--- * JCMP void REG NA ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} N775 (???,???) [003852] ----------- IL_OFFSET void INLRT @ 0x262[E-] REG NA N777 ( 1, 1) [001171] ----------- t1171 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1171 byref N779 ( 3, 4) [002623] -c--------- t2623 = * LEA(b+4) byref REG NA /--* t2623 byref N781 ( 4, 3) [001172] n---GO----- t1172 = * IND int REG x1 N783 ( 1, 1) [001173] ----------- t1173 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1172 int +--* t1173 int N785 ( 6, 5) [001174] ----GO----- t1174 = * ADD int REG x1 N787 ( 1, 1) [001175] ----------- t1175 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t1174 int +--* t1175 int N789 ( 8, 7) [001176] ----GO----- t1176 = * SUB int REG x1 /--* t1176 int N791 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 x1 REG x1 N001 ( 1, 1) [004381] ----------Z t4381 = LCL_VAR bool V12 loc8 x7 REG x7 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} N795 (???,???) [003853] ----------- IL_OFFSET void INLRT @ 0x26E[E-] REG NA N797 ( 1, 1) [001141] ----------- t1141 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1141 int N799 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 x1 REG x1 N001 ( 1, 1) [004382] ----------Z t4382 = LCL_VAR bool V12 loc8 x7 REG x7 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} N803 (???,???) [003854] ----------- IL_OFFSET void INLRT @ 0x271[E-] REG NA N805 ( 1, 1) [001145] ----------- t1145 = LCL_VAR int V70 tmp30 u:1 x1 (last use) REG x1 $291 /--* t1145 int N807 (???,???) [004213] ----------- t4213 = * PUTARG_REG int REG x1 N809 ( 1, 1) [001148] ----------- t1148 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1148 byref N811 (???,???) [004214] ----------- t4214 = * PUTARG_REG byref REG x0 N813 ( 2, 8) [002624] H---------- t2624 = CNS_INT(h) long 0x400000000046acb8 ftn REG x11 $45 /--* t2624 long N815 (???,???) [004215] ----------- t4215 = * PUTARG_REG long REG x11 N817 ( 1, 2) [001150] ----------- t1150 = CNS_INT int 0 REG x2 $c0 /--* t1150 int N819 (???,???) [004216] ----------- t4216 = * PUTARG_REG int REG x2 /--* t4213 int arg2 in x1 +--* t4214 byref arg1 in x0 +--* t4215 long r2r cell in x11 +--* t4216 int arg3 in x2 N821 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void REG NA $VN.Void N823 (???,???) [003855] ----------- IL_OFFSET void INLRT @ 0x27A[E-] REG NA N825 ( 1, 1) [001152] ----------- t1152 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t1152 long N827 ( 4, 3) [001153] ---XG------ t1153 = * IND ubyte REG x0 N829 ( 1, 2) [001154] -c--------- t1154 = CNS_INT int 0 REG NA $c0 /--* t1153 ubyte +--* t1154 int N831 ( 6, 6) [001155] CNE---XG--N--- * JCMP void REG NA ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} N835 (???,???) [003856] ----------- IL_OFFSET void INLRT @ 0x27F[E-] REG NA N837 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 x24 REG x24 $246 /--* t3713 byref N839 (???,???) [004217] ----------- t4217 = * PUTARG_REG byref REG x0 N841 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] x1 REG x1 $3ce /--* t2628 long N843 (???,???) [004218] ----------- t4218 = * PUTARG_REG long REG x1 /--* t4217 byref +--* t4218 long N845 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct REG NA $142 N847 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn REG x11 $43 /--* t2625 long N849 (???,???) [004219] ----------- t4219 = * PUTARG_REG long REG x11 N851 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 REG x2 $c2 /--* t1158 int N853 (???,???) [004220] ----------- t4220 = * PUTARG_REG int REG x2 /--* t2626 struct arg1 x0,x1 +--* t4219 long r2r cell in x11 +--* t4220 int arg2 in x2 N855 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int REG x0 $2c4 /--* t1159 int N857 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 x1 REG x1 N859 (???,???) [003857] ----------- IL_OFFSET void INLRT @ 0x288[E-] REG NA N861 ( 1, 1) [001164] ----------- t1164 = LCL_VAR int V16 loc12 u:16 x1 REG x1 $2c4 N863 ( 1, 1) [001165] ----------- t1165 = LCL_VAR int V15 loc11 u:2 x26 REG x26 $283 /--* t1164 int +--* t1165 int N865 ( 3, 3) [001166] J------N--- * EQ void REG NA $6b6 N867 ( 5, 5) [001167] ----------- * JTRUE void REG NA $VN.Void ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} N871 (???,???) [003858] ----------- IL_OFFSET void INLRT @ 0x28E[E-] REG NA N873 ( 1, 1) [001168] ----------- t1168 = LCL_VAR int V16 loc12 u:16 x1 (last use) REG x1 $2c4 /--* t1168 int N875 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 x26 REG x26 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} N879 (???,???) [003859] ----------- IL_OFFSET void INLRT @ 0x297[E-] REG NA N881 ( 1, 1) [000097] ----------- t97 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t97 byref N883 ( 3, 4) [002630] -c--------- t2630 = * LEA(b+10) byref REG NA /--* t2630 byref N885 ( 5, 4) [000098] n---GO----- t98 = * IND ubyte REG x1 N887 ( 1, 2) [000099] -c--------- t99 = CNS_INT int 3 REG NA $c3 /--* t98 ubyte +--* t99 int N889 ( 7, 7) [000100] J---GO-N--- * EQ void REG NA N891 ( 9, 9) [000101] ----GO----- * JTRUE void REG NA $301 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} N895 (???,???) [003860] ----------- IL_OFFSET void INLRT @ 0x2A0[E-] REG NA N897 ( 1, 1) [001122] ----------- t1122 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1122 byref N899 ( 3, 4) [002632] -c--------- t2632 = * LEA(b+8) byref REG NA N901 ( 1, 2) [001123] -c--------- t1123 = CNS_INT int 0 REG NA $c0 /--* t2632 byref +--* t1123 int N903 (???,???) [003861] -A--GO----- * STOREIND bool REG NA ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} N907 (???,???) [003862] ----------- IL_OFFSET void INLRT @ 0x2A7[E-] REG NA N909 ( 1, 1) [000102] ----------- t102 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t102 byref N911 ( 3, 4) [002634] -c--------- t2634 = * LEA(b+4) byref REG NA N913 ( 1, 2) [000103] -c--------- t103 = CNS_INT int 0 REG NA $c0 /--* t2634 byref +--* t103 int N915 (???,???) [003863] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004383] ----------Z t4383 = LCL_VAR bool V12 loc8 x7 REG x7 N001 ( 1, 1) [004384] ----------Z t4384 = LCL_VAR bool V09 loc5 x5 REG x5 ------------ BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} N919 (???,???) [003864] ----------- IL_OFFSET void INLRT @ 0x2AE[E-] REG NA N921 (???,???) [003865] ----------- IL_OFFSET void INLRT @ 0x2B2[E-] REG NA N923 ( 1, 1) [000106] ----------- t106 = LCL_VAR int V06 loc2 u:2 x3 (last use) REG x3 $284 N925 ( 1, 1) [000107] ----------- t107 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t106 int +--* t107 int N927 ( 3, 3) [000108] Jc-----N--- t108 = * LT int REG NA $6b7 N929 ( 1, 1) [000110] ----------- t110 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d N931 ( 1, 1) [000111] ----------z t111 = LCL_VAR int V06 loc2 u:2 x3 REG x3 $284 /--* t110 int +--* t111 int N933 ( 3, 3) [000112] ----------- t112 = * SUB int REG x0 $6b8 N935 ( 1, 2) [001118] -c--------- t1118 = CNS_INT int 0 REG NA $c0 /--* t108 int +--* t112 int +--* t1118 int N937 ( 8, 9) [003777] ----------- t3777 = * SELECT int REG x3 /--* t3777 int N939 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 x3 REG x3 N941 (???,???) [003866] ----------- IL_OFFSET void INLRT @ 0x2B5[E-] REG NA N943 ( 3, 2) [000116] ----------- t116 = LCL_VAR int V44 tmp4 u:1 x3 (last use) REG x3 $292 /--* t116 int N945 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 x22 REG x22 N947 (???,???) [003867] ----------- IL_OFFSET void INLRT @ 0x2B9[E-] REG NA N949 (???,???) [003868] ----------- IL_OFFSET void INLRT @ 0x2BD[E-] REG NA N951 ( 1, 1) [000119] ----------- t119 = LCL_VAR int V07 loc3 u:2 x4 (last use) REG x4 $285 N953 ( 1, 1) [000120] ----------- t120 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t119 int +--* t120 int N955 ( 3, 3) [000121] Jc-----N--- t121 = * GT int REG NA $6b9 N957 ( 1, 1) [000123] ----------- t123 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d N959 ( 1, 1) [000124] ----------z t124 = LCL_VAR int V07 loc3 u:2 x4 REG x4 $285 /--* t123 int +--* t124 int N961 ( 3, 3) [000125] ----------- t125 = * SUB int REG x0 $6ba N963 ( 1, 2) [001114] -c--------- t1114 = CNS_INT int 0 REG NA $c0 /--* t121 int +--* t125 int +--* t1114 int N965 ( 8, 9) [003774] ----------- t3774 = * SELECT int REG x4 /--* t3774 int N967 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 x4 REG x4 N969 (???,???) [003869] ----------- IL_OFFSET void INLRT @ 0x2C0[E-] REG NA N971 ( 3, 2) [000129] ----------- t129 = LCL_VAR int V45 tmp5 u:1 x4 (last use) REG x4 $293 /--* t129 int N973 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 NA REG NA N975 (???,???) [003870] ----------- IL_OFFSET void INLRT @ 0x2C4[E-] REG NA N977 ( 1, 1) [000132] ----------z t132 = LCL_VAR int V09 loc5 u:2 x5 REG x5 $4c1 N979 ( 1, 2) [000133] -c--------- t133 = CNS_INT int 0 REG NA $c0 /--* t132 int +--* t133 int N981 ( 3, 4) [000134] CEQ-------N--- * JCMP void REG NA ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} N985 (???,???) [003871] ----------- IL_OFFSET void INLRT @ 0x2C8[E-] REG NA N987 ( 1, 1) [001108] ----------- t1108 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t1108 int N989 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 x2 REG x2 N991 (???,???) [003872] ----------- IL_OFFSET void INLRT @ 0x2CB[E-] REG NA N993 ( 1, 2) [001111] -c--------- t1111 = CNS_INT int 0 REG NA $c0 /--* t1111 int N995 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 x3 REG x3 ------------ BB74 [2D0..2EE), preds={BB66} succs={BB78} N999 (???,???) [003873] ----------- IL_OFFSET void INLRT @ 0x2D0[E-] REG NA N1001 (???,???) [003874] ----------- IL_OFFSET void INLRT @ 0x2D9[E-] REG NA N1003 ( 1, 1) [000136] ----------- t136 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t136 byref N1005 ( 3, 4) [002636] -c--------- t2636 = * LEA(b+4) byref REG NA /--* t2636 byref N1007 ( 4, 3) [000137] n---GO----- t137 = * IND int REG x3 /--* t137 int N1009 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 x3 REG x3 N1011 ( 3, 2) [003684] ----------- t3684 = LCL_VAR int V178 cse7 u:1 x3 REG x3 N1013 ( 1, 1) [000138] ----------- t138 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t3684 int +--* t138 int N1015 ( 13, 10) [000139] Jc--GO-N--- t139 = * GT int REG NA N1017 ( 3, 2) [003686] ----------- t3686 = LCL_VAR int V178 cse7 u:1 x3 REG x3 N1019 ( 1, 1) [001104] ----------- t1104 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t139 int +--* t3686 int +--* t1104 int N1021 ( 18, 14) [003771] ----GO----- t3771 = * SELECT int REG x2 /--* t3771 int N1023 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 x2 REG x2 N1025 (???,???) [003875] ----------- IL_OFFSET void INLRT @ 0x2DC[E-] REG NA N1027 ( 3, 2) [000146] ----------- t146 = LCL_VAR int V46 tmp6 u:1 x2 (last use) REG x2 $295 /--* t146 int N1029 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 x2 REG x2 N1031 (???,???) [003876] ----------- IL_OFFSET void INLRT @ 0x2E4[E-] REG NA N1033 ( 3, 2) [003687] ----------- t3687 = LCL_VAR int V178 cse7 u:1 x3 (last use) REG x3 N1035 ( 1, 1) [000151] ----------- t151 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t3687 int +--* t151 int N1037 ( 5, 4) [000152] ----G------ t152 = * SUB int REG x3 /--* t152 int N1039 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 x3 REG x3 ------------ BB78 [000..30D) -> BB262 (cond), preds={BB73,BB74} succs={BB79,BB262} N1043 (???,???) [003877] ----------- IL_OFFSET void INLRT @ 0x2EE[E-] REG NA N1045 ( 1, 1) [000155] ----------- t155 = LCL_VAR int V15 loc11 u:2 x26 REG x26 $283 /--* t155 int N1047 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 NA REG NA N1049 (???,???) [003878] ----------- IL_OFFSET void INLRT @ 0x2F2[E-] REG NA N1051 (???,???) [003879] ----------- IL_OFFSET void INL09 @ 0x01F[E-] <- INLRT @ ??? REG NA N1053 ( 3, 3) [001550] ----------- t1550 = LCL_VAR_ADDR long V47 tmp7 x6 REG x6 $740 /--* t1550 long N1055 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 x6 REG x6 N1057 (???,???) [003880] ----------- IL_OFFSET void INL09 @ 0x026[E-] <- INLRT @ ??? REG NA N1059 (???,???) [003881] ----------- IL_OFFSET void INLRT @ 0x2FF[E-] REG NA N1061 ( 1, 1) [002649] ----------- t2649 = LCL_VAR byref V151 tmp111 u:1 x6 (last use) REG x6 $24b /--* t2649 byref N1063 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 NA REG NA N1065 ( 1, 2) [003720] ----------- t3720 = CNS_INT int 4 REG x8 $c8 /--* t3720 int N1067 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 x8 REG x8 N1069 (???,???) [003882] ----------- IL_OFFSET void INLRT @ 0x303[E-] REG NA N1071 ( 1, 2) [000175] ----------- t175 = CNS_INT int -1 REG x9 $c4 /--* t175 int N1073 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 x9 REG x9 N1075 (???,???) [003883] ----------- IL_OFFSET void INLRT @ 0x306[E-] REG NA N1077 ( 1, 1) [000941] ----------- t941 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t941 ref N1079 ( 3, 4) [002656] -c--------- t2656 = * LEA(b+56) byref REG NA /--* t2656 byref N1081 ( 4, 3) [001570] ---XG------ t1570 = * IND ref REG x0 /--* t1570 ref N1083 (???,???) [004156] -c--------- t4156 = * LEA(b+8) byref REG NA /--* t4156 byref N1085 ( 6, 5) [000944] ---XG------ t944 = * IND int REG x0 N1087 ( 1, 2) [000945] -c--------- t945 = CNS_INT int 0 REG NA $c0 /--* t944 int +--* t945 int N1089 ( 11, 8) [000946] -c-XG--N--- t946 = * LE int REG NA N1091 ( 1, 1) [000178] ----------z t178 = LCL_VAR int V12 loc8 u:3 x7 REG x7 $4c4 N1093 ( 1, 2) [000179] -c--------- t179 = CNS_INT int 0 REG NA $c0 /--* t178 int +--* t179 int N1095 ( 6, 4) [000180] -c-----N--- t180 = * EQ int REG NA $70a /--* t946 int +--* t180 int N1097 ( 18, 13) [003732] Jc-XG--N--- * AND void REG NA N1099 ( 20, 15) [000181] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} N1103 (???,???) [003884] ----------- IL_OFFSET void INLRT @ 0x30D[E-] REG NA N1105 (???,???) [003885] ----------- IL_OFFSET void INLRT @ 0x31E[E-] REG NA N1107 ( 1, 1) [000948] ----------- t948 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t948 ref N1109 ( 3, 4) [002658] -c--------- t2658 = * LEA(b+8) byref REG NA /--* t2658 byref N1111 ( 4, 3) [000949] n---GO----- t949 = * IND ref REG x10 /--* t949 ref N1113 ( 4, 3) [000951] DA--GO----z * STORE_LCL_VAR ref V26 loc22 d:1 x10 REG x10 N1115 (???,???) [003886] ----------- IL_OFFSET void INLRT @ 0x326[E-] REG NA N1117 ( 1, 2) [000952] -c--------- t952 = CNS_INT int 0 REG NA $c0 /--* t952 int N1119 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 NA REG NA N1121 (???,???) [003887] ----------- IL_OFFSET void INLRT @ 0x329[E-] REG NA N1123 ( 1, 2) [000955] -c--------- t955 = CNS_INT int 0 REG NA $c0 /--* t955 int N1125 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 x14 REG x14 N1127 (???,???) [003888] ----------- IL_OFFSET void INLRT @ 0x32C[E-] REG NA N1129 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 x10 REG x10 /--* t958 ref N1131 (???,???) [004158] -c--------- t4158 = * LEA(b+8) byref REG NA /--* t4158 byref N1133 ( 3, 3) [000959] ---X------- t959 = * IND int REG x12 /--* t959 int N1135 ( 3, 3) [000961] DA-X------z * STORE_LCL_VAR int V29 loc25 d:1 x12 REG x12 N1137 (???,???) [003889] ----------- IL_OFFSET void INLRT @ 0x332[E-] REG NA N1139 ( 1, 1) [000962] ----------Z t962 = LCL_VAR int V29 loc25 u:1 x12 REG x12 N1141 ( 1, 2) [000963] -c--------- t963 = CNS_INT int 0 REG NA $c0 /--* t962 int +--* t963 int N1143 ( 3, 4) [000964] CEQ-------N--- * JCMP void REG NA ------------ BB81 [336..33D), preds={BB79} succs={BB82} N1147 (???,???) [003890] ----------- IL_OFFSET void INLRT @ 0x336[E-] REG NA N1149 ( 1, 1) [002659] ----------Z t2659 = LCL_VAR ref V26 loc22 u:1 x10 REG x10 /--* t2659 ref N1151 ( 1, 1) [002667] -c--------- t2667 = * LEA(b+16) byref REG NA /--* t2667 byref N1153 ( 4, 3) [002671] n---GO----- t2671 = * IND int REG x14 /--* t2671 int N1155 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 x14 REG x14 N001 ( 1, 1) [004385] ----------z t4385 = LCL_VAR ref V26 loc22 x10 REG x10 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} N1159 (???,???) [003891] ----------- IL_OFFSET void INLRT @ 0x33D[E-] REG NA N1161 ( 1, 1) [000966] ----------Z t966 = LCL_VAR int V28 loc24 u:2 x14 REG x14 $298 /--* t966 int N1163 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 x15 REG x15 N1165 ( 1, 1) [000969] ----------Z t969 = LCL_VAR int V08 loc4 u:1 x2 REG x2 $297 /--* t969 int N1167 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 x0 REG x0 N1169 (???,???) [003892] ----------- IL_OFFSET void INLRT @ 0x341[E-] REG NA N1171 ( 1, 1) [000970] ----------- t970 = LCL_VAR int V14 loc10 u:1 x3 REG x3 $296 N1173 ( 1, 2) [000971] -c--------- t971 = CNS_INT int 0 REG NA $c0 /--* t970 int +--* t971 int N1175 ( 3, 4) [000972] J------N--- * LT void REG NA $719 N1177 ( 5, 6) [000973] ----------- * JTRUE void REG NA $VN.Void ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} N1181 ( 3, 2) [000977] ----------- t977 = LCL_VAR int V64 tmp24 u:1 x0 (last use) REG x0 $297 /--* t977 int N1183 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 x0 REG x0 N1185 ( 1, 2) [001091] -c--------- t1091 = CNS_INT int 0 REG NA $c0 /--* t1091 int N1187 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 x11 REG x11 ------------ BB262 [???..???) -> BB103 (always), preds={BB78} succs={BB103} N001 ( 1, 1) [004324] ----------Z t4324 = LCL_VAR int V08 loc4 x2 REG x2 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} N1191 ( 3, 2) [000978] ----------- t978 = LCL_VAR int V64 tmp24 u:1 x0 (last use) REG x0 $297 /--* t978 int N1193 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 x0 REG x0 N1195 ( 1, 1) [000979] ----------Z t979 = LCL_VAR int V14 loc10 u:1 x3 REG x3 $296 /--* t979 int N1197 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 x11 REG x11 N001 ( 1, 1) [004386] ----------z t4386 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} N1201 ( 3, 2) [000986] ----------- t986 = LCL_VAR int V65 tmp25 u:1 x0 (last use) REG x0 $297 N1203 ( 3, 2) [000987] ----------- t987 = LCL_VAR int V66 tmp26 u:1 x11 (last use) REG x11 $299 /--* t986 int +--* t987 int N1205 ( 7, 5) [000988] ----------- t988 = * ADD int REG x0 $71a /--* t988 int N1207 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 x0 REG x0 N1209 (???,???) [003893] ----------- IL_OFFSET void INLRT @ 0x350[E-] REG NA N1211 (???,???) [003894] ----------- IL_OFFSET void INLRT @ 0x355[E-] REG NA N1213 ( 1, 1) [000991] ----------- t991 = LCL_VAR int V06 loc2 u:3 x22 REG x22 $292 N1215 ( 3, 2) [000992] ----------- t992 = LCL_VAR int V31 loc27 u:1 x0 REG x0 $71a /--* t991 int +--* t992 int N1217 ( 5, 4) [000993] Jc-----N--- t993 = * GT int REG NA $71b N1219 ( 1, 1) [000995] ----------- t995 = LCL_VAR int V06 loc2 u:3 x22 REG x22 $292 N1221 ( 3, 2) [001087] ----------- t1087 = LCL_VAR int V31 loc27 u:1 x0 (last use) REG x0 $71a /--* t993 int +--* t995 int +--* t1087 int N1223 ( 10, 8) [003768] ----------- t3768 = * SELECT int REG xip0 /--* t3768 int N1225 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 xip0 REG xip0 N1227 (???,???) [003895] ----------- IL_OFFSET void INLRT @ 0x359[E-] REG NA N1229 ( 3, 2) [000999] ----------- t999 = LCL_VAR int V67 tmp27 u:1 xip0 (last use) REG xip0 $29a /--* t999 int N1231 ( 3, 3) [001001] DA--------z * STORE_LCL_VAR int V32 loc28 d:1 xip0 REG xip0 N1233 (???,???) [003896] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] REG NA N1235 ( 1, 1) [003158] ----------Z t3158 = LCL_VAR int V32 loc28 u:1 xip0 REG xip0 $29a N1237 ( 1, 1) [003159] ----------- t3159 = LCL_VAR int V30 loc26 u:1 x15 REG x15 $298 /--* t3158 int +--* t3159 int N1239 ( 3, 3) [003157] J------N--- * LE void REG NA $71c N1241 ( 5, 5) [003156] ----------- * JTRUE void REG NA $VN.Void ------------ BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} N1245 (???,???) [003897] ----------- IL_OFFSET void INLRT @ 0x35E[E-] REG NA N1247 ( 1, 1) [001006] ----------Z t1006 = LCL_VAR int V30 loc26 u:2 x15 REG x15 $29d N1249 ( 1, 2) [001007] -c--------- t1007 = CNS_INT int 0 REG NA $c0 /--* t1006 int +--* t1007 int N1251 ( 3, 4) [001008] CEQ-------N--- * JCMP void REG NA ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} N1255 (???,???) [003898] ----------- IL_OFFSET void INLRT @ 0x362[E-] REG NA N1257 ( 1, 1) [001010] ----------- t1010 = LCL_VAR int V20 loc16 u:10 x9 (last use) REG x9 $29b N1259 ( 1, 2) [001011] -c--------- t1011 = CNS_INT int 1 REG NA $c1 /--* t1010 int +--* t1011 int N1261 ( 3, 4) [001012] ----------- t1012 = * ADD int REG x9 $71f /--* t1012 int N1263 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 x9 REG x9 N1265 (???,???) [003899] ----------- IL_OFFSET void INLRT @ 0x368[E-] REG NA N1267 ( 1, 1) [001015] ----------Z t1015 = LCL_VAR int V20 loc16 u:11 x9 REG x9 $71f N1269 ( 1, 1) [001574] ----------- t1574 = LCL_VAR int V144 tmp104 u:3 x8 REG x8 $29c /--* t1015 int +--* t1574 int N1271 ( 3, 3) [001020] J------N--- * LT void REG NA $720 N1273 ( 5, 5) [001021] ----------- * JTRUE void REG NA $VN.Void ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} N001 ( 1, 1) [004387] ----------Z t4387 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004388] ----------Z t4388 = LCL_VAR ref V26 loc22 x10 REG x10 N1277 (???,???) [003900] ----------- IL_OFFSET void INLRT @ 0x373[E-] REG NA N1279 ( 1, 1) [001578] ----------Z t1578 = LCL_VAR int V144 tmp104 u:3 x8 REG x8 $29c N1281 ( 1, 2) [001065] -c--------- t1065 = CNS_INT int 1 REG NA $c1 /--* t1578 int +--* t1065 int N1283 ( 3, 4) [001066] ----------- t1066 = * LSH int REG x0 $721 /--* t1066 int N1285 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int REG x0 $3cf /--* t1067 long N1287 (???,???) [004221] ----------- t4221 = * PUTARG_REG long REG x0 N1289 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn REG x11 $49 /--* t2672 long N1291 (???,???) [004222] ----------- t4222 = * PUTARG_REG long REG x11 /--* t4221 long arg1 in x0 +--* t4222 long r2r cell in x11 N1293 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 REG x0 $330 /--* t1068 ref N1295 ( 20, 18) [001070] DA-XG-----z * STORE_LCL_VAR ref V33 loc29 d:1 x3 REG x3 N1297 (???,???) [003901] ----------- IL_OFFSET void INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] REG NA N1299 (???,???) [003902] ----------- IL_OFFSET void INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] REG NA N1301 ( 1, 1) [002689] ----------- t2689 = LCL_VAR ref V33 loc29 u:1 x3 REG x3 $800 N1303 ( 1, 2) [002690] -c--------- t2690 = CNS_INT long 16 Fseq[] REG NA $200 /--* t2689 ref +--* t2690 long N1305 ( 3, 4) [002691] -----O----- t2691 = * ADD byref REG x0 $253 /--* t2691 byref N1307 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 x0 REG x0 N1309 (???,???) [003903] ----------- IL_OFFSET void INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] REG NA N1311 ( 1, 1) [001607] ----------Z t1607 = LCL_VAR ref V33 loc29 u:1 x3 REG x3 $800 /--* t1607 ref N1313 (???,???) [004160] -c--------- t4160 = * LEA(b+8) byref REG NA /--* t4160 byref N1315 ( 3, 3) [001608] ---X------- t1608 = * IND int REG x2 $2cc /--* t1608 int N1317 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 x2 REG x2 N1319 ( 1, 1) [002694] ----------- t2694 = LCL_VAR byref V159 tmp119 u:1 x0 (last use) REG x0 $382 /--* t2694 byref N1321 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 x0 REG x0 N1323 ( 1, 1) [001620] ----------z t1620 = LCL_VAR int V144 tmp104 u:3 x4 REG x4 $29c N1325 ( 1, 1) [001647] ----------- t1647 = LCL_VAR int V160 tmp120 u:1 x2 (last use) REG x2 $2a0 /--* t1620 int +--* t1647 int N1327 ( 3, 3) [001628] N------N-U- * GT void REG NA $722 N1329 ( 5, 5) [001629] ----------- * JTRUE void REG NA $VN.Void ------------ BB95 [000..392), preds={BB91} succs={BB100} N1333 (???,???) [003904] ----------- IL_OFFSET void INL17 @ 0x00F[E-] <- INLRT @ ??? REG NA N1335 ( 1, 1) [001639] ----------- t1639 = LCL_VAR int V144 tmp104 u:3 x4 (last use) REG x4 $29c /--* t1639 int N1337 ( 2, 3) [001640] ---------U- t1640 = * CAST long <- ulong <- uint REG x2 $3d0 /--* t1640 long N1339 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 x2 REG x2 N1341 (???,???) [003905] ----------- IL_OFFSET void INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? REG NA N1343 ( 1, 1) [001663] ----------- t1663 = LCL_VAR long V83 tmp43 u:1 x2 (last use) REG x2 $3d0 N1345 ( 1, 2) [001665] -c--------- t1665 = CNS_INT long 2 REG NA $20a /--* t1663 long +--* t1665 long N1347 ( 3, 4) [001666] ----------- t1666 = * LSH long REG x2 $3d1 /--* t1666 long N1349 (???,???) [004223] ----------- t4223 = * PUTARG_REG long REG x2 N1351 ( 1, 1) [001661] ----------- t1661 = LCL_VAR byref V161 tmp121 u:1 x0 (last use) REG x0 $382 /--* t1661 byref N1353 (???,???) [004224] ----------- t4224 = * PUTARG_REG byref REG x0 N1355 ( 1, 1) [001662] ----------z t1662 = LCL_VAR byref V143 tmp103 u:3 x1 (last use) REG x1 $381 /--* t1662 byref N1357 (???,???) [004225] ----------- t4225 = * PUTARG_REG byref REG x1 N1359 ( 2, 8) [002700] H---------- t2700 = CNS_INT(h) long 0x4000000000420490 ftn REG x11 $4b /--* t2700 long N1361 (???,???) [004226] ----------- t4226 = * PUTARG_REG long REG x11 /--* t4223 long arg3 in x2 +--* t4224 byref arg1 in x0 +--* t4225 byref arg2 in x1 +--* t4226 long r2r cell in x11 N1363 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void REG NA $VN.Void N1365 (???,???) [003906] ----------- IL_OFFSET void INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] REG NA N1367 (???,???) [003907] ----------- IL_OFFSET void INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] REG NA N1369 ( 1, 1) [002718] ----------z t2718 = LCL_VAR ref V33 loc29 u:1 x0 REG x0 $800 N1371 ( 1, 2) [002719] -c--------- t2719 = CNS_INT long 16 Fseq[] REG NA $200 /--* t2718 ref +--* t2719 long N1373 ( 3, 4) [002720] -----O----- t2720 = * ADD byref REG x1 $253 /--* t2720 byref N1375 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 x1 REG x1 N1377 (???,???) [003908] ----------- IL_OFFSET void INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] REG NA N1379 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 x0 (last use) REG x0 $800 /--* t1719 ref N1381 (???,???) [004162] -c--------- t4162 = * LEA(b+8) byref REG NA /--* t4162 byref N1383 ( 3, 3) [001720] ---X------- t1720 = * IND int REG x4 $2cc /--* t1720 int N1385 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 x4 REG x4 N1387 (???,???) [003909] ----------- IL_OFFSET void INLRT @ 0x391[E-] REG NA N1389 ( 1, 1) [002723] ----------- t2723 = LCL_VAR byref V163 tmp123 u:1 x1 (last use) REG x1 $383 /--* t2723 byref N1391 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 x2 REG x2 N1393 ( 1, 1) [002726] ----------- t2726 = LCL_VAR int V164 tmp124 u:1 x4 (last use) REG x4 $2a1 /--* t2726 int N1395 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 x3 REG x3 N001 ( 1, 1) [004389] ----------Z t4389 = LCL_VAR byref V143 tmp103 x2 REG x2 N001 ( 1, 1) [004390] ----------- t4390 = LCL_VAR int V144 tmp104 x3 REG x3 /--* t4390 int N002 ( 2, 2) [004391] ----------- t4391 = * COPY int REG x8 N001 ( 1, 1) [004392] ----------z t4392 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004393] ----------z t4393 = LCL_VAR ref V26 loc22 x10 REG x10 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} N1399 (???,???) [003910] ----------- IL_OFFSET void INLRT @ 0x39A[E-] REG NA N1401 ( 1, 1) [001024] ----------z t1024 = LCL_VAR int V20 loc16 u:11 x9 REG x9 $71f N1403 ( 1, 1) [001028] ----------Z t1028 = LCL_VAR int V144 tmp104 u:4 x8 REG x8 $2a2 /--* t1024 int +--* t1028 int N1405 ( 6, 9) [001029] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $334 N1407 ( 1, 1) [001033] ----------z t1033 = LCL_VAR byref V143 tmp103 u:4 x6 REG x6 $384 N1409 ( 1, 1) [001025] ----------Z t1025 = LCL_VAR int V20 loc16 u:11 x9 REG x9 $71f /--* t1025 int N1411 ( 2, 3) [001030] -c-------U- t1030 = * CAST long <- uint REG NA $3d2 N1413 ( 1, 2) [001031] -c--------- t1031 = CNS_INT long 2 REG NA $20a /--* t1030 long +--* t1031 long N1415 ( 4, 6) [001032] -c--------- t1032 = * BFIZ long REG NA /--* t1033 byref +--* t1032 long N1417 ( 6, 8) [001034] -c--------- t1034 = * LEA(b+(i*1)+0) byref REG NA N1419 ( 1, 1) [001036] ----------z t1036 = LCL_VAR int V28 loc24 u:3 x14 REG x14 $29f /--* t1034 byref +--* t1036 int N1421 (???,???) [003911] -A-XGO----- * STOREIND int REG NA N1423 (???,???) [003912] ----------- IL_OFFSET void INLRT @ 0x3A6[E-] REG NA N1425 ( 1, 1) [001039] ----------z t1039 = LCL_VAR int V27 loc23 u:2 x13 REG x13 $29e N1427 ( 1, 1) [001040] ----------z t1040 = LCL_VAR int V29 loc25 u:1 x12 REG x12 N1429 ( 1, 2) [001041] -c--------- t1041 = CNS_INT int -1 REG NA $c4 /--* t1040 int +--* t1041 int N1431 ( 3, 4) [001042] ----------- t1042 = * ADD int REG x0 /--* t1039 int +--* t1042 int N1433 ( 5, 6) [001043] J------N--- * GE void REG NA N1435 ( 7, 8) [001044] ----------- * JTRUE void REG NA $VN.Void ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} N1439 (???,???) [003913] ----------- IL_OFFSET void INLRT @ 0x3AE[E-] REG NA N1441 ( 1, 1) [001050] ----------- t1050 = LCL_VAR int V27 loc23 u:2 x13 (last use) REG x13 $29e N1443 ( 1, 2) [001051] -c--------- t1051 = CNS_INT int 1 REG NA $c1 /--* t1050 int +--* t1051 int N1445 ( 3, 4) [001052] ----------- t1052 = * ADD int REG x13 $727 /--* t1052 int N1447 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 x13 REG x13 N1449 (???,???) [003914] ----------- IL_OFFSET void INLRT @ 0x3B4[E-] REG NA N1451 ( 1, 1) [001056] ----------- t1056 = LCL_VAR int V27 loc23 u:4 x13 REG x13 $727 N1453 ( 1, 1) [001055] ----------- t1055 = LCL_VAR ref V26 loc22 u:1 x10 REG x10 /--* t1055 ref N1455 (???,???) [004164] -c--------- t4164 = * LEA(b+8) byref REG NA /--* t4164 byref N1457 ( 3, 3) [002732] ---X------- t2732 = * IND int REG x15 /--* t1056 int +--* t2732 int N1459 ( 8, 11) [002733] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N1461 ( 1, 1) [002730] ----------- t2730 = LCL_VAR ref V26 loc22 u:1 x10 REG x10 N1463 ( 1, 2) [002737] -c--------- t2737 = CNS_INT long 16 REG NA $200 /--* t2730 ref +--* t2737 long N1465 ( 3, 4) [002738] ----------- t2738 = * ADD byref REG x0 N1467 ( 1, 1) [002731] ----------- t2731 = LCL_VAR int V27 loc23 u:4 x13 REG x13 $727 /--* t2731 int N1469 ( 2, 3) [002734] -c-------U- t2734 = * CAST long <- uint REG NA $3d4 N1471 ( 1, 2) [002735] -c-----N--- t2735 = CNS_INT long 2 REG NA $20a /--* t2734 long +--* t2735 long N1473 ( 4, 6) [002736] -c--------- t2736 = * BFIZ long REG NA /--* t2738 byref +--* t2736 long N1475 ( 7, 10) [002739] -c--------- t2739 = * LEA(b+(i*1)+0) byref REG NA /--* t2739 byref N1477 ( 10, 12) [002742] n---GO----- t2742 = * IND int REG x15 /--* t2742 int N1479 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 x0 REG x0 N001 ( 1, 1) [004394] ----------Z t4394 = LCL_VAR int V30 loc26 x0 REG x0 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} N1483 (???,???) [003915] ----------- IL_OFFSET void INLRT @ 0x3BB[E-] REG NA N1485 ( 1, 1) [001045] ----------- t1045 = LCL_VAR int V28 loc24 u:3 x14 (last use) REG x14 $29f N1487 ( 1, 1) [001046] ----------z t1046 = LCL_VAR int V30 loc26 u:3 x15 REG x15 $2a3 /--* t1045 int +--* t1046 int N1489 ( 3, 3) [001047] ----------- t1047 = * ADD int REG x14 $72b /--* t1047 int N1491 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 x14 REG x14 N1493 (???,???) [003916] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] REG NA N1495 ( 1, 1) [001002] ----------z t1002 = LCL_VAR int V32 loc28 u:1 xip0 REG xip0 $29a N1497 ( 1, 1) [001003] ----------- t1003 = LCL_VAR int V28 loc24 u:4 x14 REG x14 $72b /--* t1002 int +--* t1003 int N1499 ( 3, 3) [001004] J------N--- * GT void REG NA $72c N001 ( 1, 1) [004325] ----------Z t4325 = LCL_VAR int V28 loc24 x14 REG x14 N001 ( 1, 1) [004326] ----------Z t4326 = LCL_VAR int V27 loc23 x13 REG x13 N001 ( 1, 1) [004327] ----------Z t4327 = LCL_VAR int V29 loc25 x12 REG x12 N001 ( 1, 1) [004328] ----------Z t4328 = LCL_VAR int V32 loc28 xip0 REG xip0 N001 ( 1, 1) [004329] ----------z t4329 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004330] ----------z t4330 = LCL_VAR int V20 loc16 x9 REG x9 N1501 ( 5, 5) [001005] ----------- * JTRUE void REG NA $VN.Void ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB85,BB89,BB102,BB262} succs={BB104,BB112} N1505 (???,???) [003917] ----------- IL_OFFSET void INLRT @ 0x3C8[E-] REG NA N1507 ( 1, 1) [000182] ----------- t182 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t182 byref N1509 ( 3, 4) [002744] -c--------- t2744 = * LEA(b+8) byref REG NA /--* t2744 byref N1511 ( 5, 4) [000183] n---GO----- t183 = * IND bool REG x0 N1513 ( 1, 2) [000184] -c--------- t184 = CNS_INT int 0 REG NA $c0 /--* t183 bool +--* t184 int N1515 ( 10, 7) [000185] -c--GO-N--- t185 = * EQ int REG NA N1517 ( 1, 1) [000927] ----------z t927 = LCL_VAR int V16 loc12 u:3 x4 REG x4 $283 N1519 ( 1, 2) [000928] -c--------- t928 = CNS_INT int 0 REG NA $c0 /--* t927 int +--* t928 int N1521 ( 6, 4) [000929] -c-----N--- t929 = * NE int REG NA $733 /--* t185 int +--* t929 int N1523 ( 17, 12) [003734] Jc--GO-N--- * AND void REG NA N1525 ( 19, 14) [000186] ----GO----- * JTRUE void REG NA $301 ------------ BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} N1529 (???,???) [003918] ----------- IL_OFFSET void INLRT @ 0x3D0[E-] REG NA N1531 (???,???) [003919] ----------- IL_OFFSET void INLRT @ 0x3D4[E-] REG NA N1533 ( 1, 1) [000931] ----------- t931 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t931 byref N1535 ( 3, 4) [002746] -c--------- t2746 = * LEA(b+4) byref REG NA /--* t2746 byref N1537 ( 4, 3) [000932] n---GO----- t932 = * IND int REG x0 N1539 ( 1, 2) [000933] -c--------- t933 = CNS_INT int 0 REG NA $c0 /--* t932 int +--* t933 int N1541 ( 6, 6) [000934] CEQ----GO-N--- * JCMP void REG NA ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} N1545 (???,???) [003920] ----------- IL_OFFSET void INLRT @ 0x3DC[E-] REG NA N1547 ( 1, 1) [000937] ----------- t937 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t937 ref N1549 ( 3, 4) [002748] -c--------- t2748 = * LEA(b+40) byref REG NA /--* t2748 byref N1551 ( 4, 3) [001730] ---XG------ t1730 = * IND ref REG x11 /--* t1730 ref N1553 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 x11 REG x11 N1555 (???,???) [003921] ----------- IL_OFFSET void INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] REG NA N1557 ( 1, 1) [001732] ----------- t1732 = LCL_VAR ref V86 tmp46 u:1 x11 REG x11 N1559 ( 1, 2) [001733] -c--------- t1733 = CNS_INT ref null REG NA $VN.Null /--* t1732 ref +--* t1733 ref N1561 ( 3, 4) [001734] CEQ-------N--- * JCMP void REG NA ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} N1565 (???,???) [003922] ----------- IL_OFFSET void INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] REG NA N1567 ( 1, 1) [000936] ----------- t936 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t936 byref N1569 ( 3, 4) [002750] -c--------- t2750 = * LEA(b+8) byref REG NA /--* t2750 byref N1571 ( 4, 3) [001736] ---XG------ t1736 = * IND int REG x0 /--* t1736 int N1573 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 x0 REG x0 N1575 (???,???) [003923] ----------- IL_OFFSET void INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] REG NA N1577 ( 1, 1) [001739] ----------- t1739 = LCL_VAR ref V86 tmp46 u:1 x11 REG x11 /--* t1739 ref N1579 (???,???) [004166] -c--------- t4166 = * LEA(b+8) byref REG NA /--* t4166 byref N1581 ( 3, 3) [001740] ---X------- t1740 = * IND int REG x10 N1583 ( 1, 2) [001741] -c--------- t1741 = CNS_INT int 1 REG NA $c1 /--* t1740 int +--* t1741 int N1585 ( 8, 6) [001742] Nc-X---N-U- t1742 = * NE int REG NA N1587 ( 3, 2) [001747] ----------- t1747 = LCL_VAR int V87 tmp47 u:1 x0 REG x0 N1589 ( 1, 1) [001748] ----------- t1748 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1748 byref N1591 ( 3, 4) [002754] -c--------- t2754 = * LEA(b+24) byref REG NA /--* t2754 byref N1593 ( 4, 3) [001786] n---GO----- t1786 = * IND int REG x13 /--* t1747 int +--* t1786 int N1595 ( 11, 6) [001752] Nc--GO-N-U- t1752 = * GE int REG NA /--* t1742 int +--* t1752 int N1597 ( 20, 13) [003736] Jc-XGO-N--- * AND void REG NA N1599 ( 22, 15) [001743] ---XGO----- * JTRUE void REG NA ------------ BB108 [3DC..3DD), preds={BB107} succs={BB112} N1603 (???,???) [003924] ----------- IL_OFFSET void INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] REG NA N1605 (???,???) [003925] ----------- IL_OFFSET void INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] REG NA N1607 ( 1, 1) [002758] ----------- t2758 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N1609 ( 1, 2) [002759] -c--------- t2759 = CNS_INT long 16 REG NA $200 /--* t2758 byref +--* t2759 long N1611 ( 3, 4) [002760] -----O----- t2760 = * ADD byref REG x10 $25c /--* t2760 byref N1613 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 x10 REG x10 N1615 (???,???) [003926] ----------- IL_OFFSET void INL26 @ ??? <- INLRT @ 0x3DC[E-] REG NA N1617 ( 3, 2) [001756] ----------- t1756 = LCL_VAR int V87 tmp47 u:1 x0 REG x0 N1619 ( 1, 1) [001761] ----------- t1761 = LCL_VAR byref V88 tmp48 u:1 x10 REG x10 $25c /--* t1761 byref N1621 ( 3, 4) [002763] -c--------- t2763 = * LEA(b+8) byref REG NA /--* t2763 byref N1623 ( 4, 3) [001762] n---GO----- t1762 = * IND int REG x13 /--* t1756 int +--* t1762 int N1625 ( 11, 12) [001763] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N1627 ( 1, 1) [001760] ----------- t1760 = LCL_VAR byref V88 tmp48 u:1 x10 (last use) REG x10 $25c /--* t1760 byref N1629 ( 3, 2) [001767] n---GO----- t1767 = * IND byref REG x10 N1631 ( 3, 2) [001757] ----------- t1757 = LCL_VAR int V87 tmp47 u:1 x0 REG x0 /--* t1757 int N1633 ( 4, 4) [001764] -c-------U- t1764 = * CAST long <- uint REG NA N1635 ( 1, 2) [001765] -c--------- t1765 = CNS_INT long 1 REG NA $204 /--* t1764 long +--* t1765 long N1637 ( 6, 7) [001766] ----------- t1766 = * BFIZ long REG x13 /--* t1767 byref +--* t1766 long N1639 ( 10, 10) [001768] ----GO-N--- t1768 = * ADD byref REG x10 N1641 ( 1, 1) [002765] ----------- t2765 = LCL_VAR ref V86 tmp46 u:1 x11 (last use) REG x11 /--* t2765 ref N1643 ( 1, 1) [002772] -c--------- t2772 = * LEA(b+12) byref REG NA /--* t2772 byref N1645 ( 5, 4) [002777] n---GO----- t2777 = * IND ushort REG x11 /--* t1768 byref +--* t2777 ushort N1647 (???,???) [003927] -A-XGO----- * STOREIND short REG NA N1649 (???,???) [003928] ----------- IL_OFFSET void INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] REG NA N1651 ( 3, 2) [001777] ----------- t1777 = LCL_VAR int V87 tmp47 u:1 x0 (last use) REG x0 N1653 ( 1, 2) [001778] -c--------- t1778 = CNS_INT int 1 REG NA $c1 /--* t1777 int +--* t1778 int N1655 ( 5, 5) [001779] ----------- t1779 = * ADD int REG x0 N1657 ( 1, 1) [001776] ----------- t1776 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1776 byref N1659 ( 3, 4) [002779] -c--------- t2779 = * LEA(b+8) byref REG NA /--* t2779 byref +--* t1779 int N1661 (???,???) [003929] -A--GO----- * STOREIND int REG NA ------------ BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} N1683 (???,???) [003930] ----------- IL_OFFSET void INLRT @ 0x3E8[E-] REG NA N1685 ( 1, 2) [002781] -c--------- t2781 = CNS_INT int 0 REG NA $c0 /--* t2781 int N1687 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 NA REG NA N1689 (???,???) [003931] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] REG NA N1691 ( 1, 1) [003714] ----------- t3714 = LCL_VAR byref V180 cse9 u:1 x24 (last use) REG x24 $246 /--* t3714 byref N1693 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 x24 REG x24 N1695 (???,???) [003932] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] REG NA N1697 ( 1, 1) [001792] ----------- t1792 = LCL_VAR byref V165 tmp125 u:1 x24 REG x24 $246 /--* t1792 byref N1699 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 NA REG NA N1701 (???,???) [003933] ----------- IL_OFFSET void INLRT @ 0x3F3[E-] REG NA N1703 ( 1, 1) [000197] ----------- t197 = LCL_VAR byref V165 tmp125 u:1 x24 (last use) REG x24 $246 /--* t197 byref N1705 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 x24 REG x24 N1707 ( 1, 1) [002791] ----------- t2791 = LCL_VAR long V169 tmp129 u:1 x24 (last use) REG x24 $3c4 /--* t2791 long N1709 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 x24 REG x24 N1711 (???,???) [003934] ----------- IL_OFFSET void INLRT @ 0x3F8[E-] REG NA N1713 ( 1, 1) [000201] ----------- t201 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t201 long N1715 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 x0 REG x0 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB266,BB268} succs={BB246,BB248} N1719 (???,???) [003935] ----------- IL_OFFSET void INLRT @ 0x7AA[E-] REG NA N1721 ( 1, 1) [000204] ----------z t204 = LCL_VAR int V16 loc12 u:4 x4 REG x4 $2ae N1723 ( 1, 1) [003707] ----------- t3707 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t204 int +--* t3707 int N1725 ( 3, 3) [000209] J------N--- * GE void REG NA $897 N1727 ( 5, 5) [000210] ----------- * JTRUE void REG NA $VN.Void ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} N1731 (???,???) [003936] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] REG NA N1733 ( 1, 1) [000243] ----------- t243 = LCL_VAR int V16 loc12 u:4 x4 (last use) REG x4 $2ae /--* t243 int N1735 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 x11 REG x11 N1737 (???,???) [003937] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] REG NA N1739 ( 1, 1) [000244] ----------- t244 = LCL_VAR int V49 tmp9 u:1 x11 REG x11 $2ae N1741 ( 1, 2) [000245] -c--------- t245 = CNS_INT int 1 REG NA $c1 /--* t244 int +--* t245 int N1743 ( 3, 4) [000246] ----------- t246 = * ADD int REG x4 $898 /--* t246 int N1745 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 NA REG NA N1747 ( 1, 1) [000242] ----------- t242 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N1749 ( 1, 1) [000251] ----------- t251 = LCL_VAR int V49 tmp9 u:1 x11 (last use) REG x11 $2ae /--* t251 int N1751 ( 2, 3) [000252] -c--------- t252 = * CAST long <- int REG NA $3db N1753 ( 1, 2) [000254] -c--------- t254 = CNS_INT long 1 REG NA $204 /--* t252 long +--* t254 long N1755 ( 4, 6) [000255] -c--------- t255 = * BFIZ long REG NA /--* t242 long +--* t255 long N1757 ( 6, 8) [000256] -c--------- t256 = * LEA(b+(i*1)+0) long REG NA /--* t256 long N1759 ( 9, 10) [000257] ---XG------ t257 = * IND ushort REG x13 /--* t257 ushort N1761 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 x13 REG x13 N1763 ( 1, 1) [000261] ----------- t261 = LCL_VAR int V50 tmp10 u:1 x13 (last use) REG x13 /--* t261 int N1765 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 x13 REG x13 N1767 ( 1, 1) [000260] ----------- t260 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1769 ( 1, 2) [000264] -c--------- t264 = CNS_INT int 0 REG NA $c0 /--* t260 int +--* t264 int N1771 ( 3, 4) [000265] CEQ-------N--- * JCMP void REG NA ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} N1775 (???,???) [003938] ----------- IL_OFFSET void INLRT @ 0x7C8[E-] REG NA N1777 ( 1, 1) [000267] ----------- t267 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1779 ( 1, 2) [000268] -c--------- t268 = CNS_INT int 59 REG NA $d1 /--* t267 int +--* t268 int N1781 ( 3, 4) [000269] N------N-U- * NE void REG NA N1783 ( 5, 6) [000270] ----------- * JTRUE void REG NA $VN.Void ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} N3595 (???,???) [003939] ----------- IL_OFFSET void INLRT @ 0x7D1[E-] REG NA N3597 ( 1, 2) [000212] -c--------- t212 = CNS_INT long 0 REG NA $205 /--* t212 long N3599 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 NA REG NA N3601 (???,???) [003940] ----------- IL_OFFSET void INLRT @ 0x7D5[E-] REG NA N3603 ( 1, 1) [000215] ----------- t215 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t215 byref N3605 ( 3, 4) [003148] -c--------- t3148 = * LEA(b+8) byref REG NA /--* t3148 byref N3607 ( 5, 4) [000216] n---GO----- t216 = * IND bool REG x2 N3609 ( 1, 2) [000217] -c--------- t217 = CNS_INT int 0 REG NA $c0 /--* t216 bool +--* t217 int N3611 ( 10, 7) [000218] -c--GO-N--- t218 = * EQ int REG NA N3613 ( 1, 1) [000221] ----------- t221 = LCL_VAR int V15 loc11 u:2 x26 (last use) REG x26 $283 N3615 ( 1, 2) [000222] -c--------- t222 = CNS_INT int 0 REG NA $c0 /--* t221 int +--* t222 int N3617 ( 6, 4) [000223] -c-----N--- t223 = * NE int REG NA $733 /--* t218 int +--* t223 int N3619 ( 17, 12) [003764] Jc--GO-N--- * AND void REG NA N3621 ( 19, 14) [000219] ----GO----- * JTRUE void REG NA $301 ------------ BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} N3625 (???,???) [003941] ----------- IL_OFFSET void INLRT @ 0x7DD[E-] REG NA N3627 (???,???) [003942] ----------- IL_OFFSET void INLRT @ 0x7E1[E-] REG NA N3629 ( 1, 1) [000225] ----------- t225 = LCL_VAR byref V01 arg1 u:1 x21 (last use) REG x21 $101 /--* t225 byref N3631 ( 3, 4) [003150] -c--------- t3150 = * LEA(b+4) byref REG NA /--* t3150 byref N3633 ( 4, 3) [000226] n---GO----- t226 = * IND int REG x2 N3635 ( 1, 2) [000227] -c--------- t227 = CNS_INT int 0 REG NA $c0 /--* t226 int +--* t227 int N3637 ( 9, 6) [000228] ----GO-N--- t228 = * NE int REG x2 N3639 ( 1, 1) [000230] ----------- t230 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t230 byref N3641 ( 3, 4) [003152] -c--------- t3152 = * LEA(b+8) byref REG NA /--* t3152 byref N3643 ( 4, 3) [002539] ---XG------ t2539 = * IND int REG x0 N3645 ( 1, 2) [000233] -c--------- t233 = CNS_INT int 0 REG NA $c0 /--* t2539 int +--* t233 int N3647 ( 9, 6) [000234] ---XG--N--- t234 = * LE int REG x0 /--* t228 int +--* t234 int N3649 ( 19, 13) [003766] J--XGO-N--- t3766 = * AND int REG x2 /--* t3766 int N3651 ( 21, 15) [000229] ---XGO----- * JTRUE void REG NA $301 ------------ BB251 [7E9..7FF), preds={BB249} succs={BB253} N3655 (???,???) [003943] ----------- IL_OFFSET void INLRT @ 0x7E9[E-] REG NA N3657 (???,???) [003944] ----------- IL_OFFSET void INLRT @ 0x7F2[E-] REG NA N3659 ( 1, 1) [000238] ----------- t238 = LCL_VAR ref V03 arg3 u:1 x20 (last use) REG x20 $180 /--* t238 ref N3661 ( 3, 4) [003155] -c--------- t3155 = * LEA(b+40) byref REG NA /--* t3155 byref N3663 ( 4, 3) [002541] ---XG------ t2541 = * IND ref REG x2 /--* t2541 ref N3665 (???,???) [004227] ---XG------ t4227 = * PUTARG_REG ref REG x2 N3667 ( 1, 1) [000236] ----------- t236 = LCL_VAR byref V00 arg0 u:1 x19 (last use) REG x19 $100 /--* t236 byref N3669 (???,???) [004228] ----------- t4228 = * PUTARG_REG byref REG x0 N3671 ( 2, 8) [003153] H---------- t3153 = CNS_INT(h) long 0x4000000000540210 ftn REG x11 $51 /--* t3153 long N3673 (???,???) [004229] ----------- t4229 = * PUTARG_REG long REG x11 N3675 ( 1, 2) [000237] ----------- t237 = CNS_INT int 0 REG x1 $c0 /--* t237 int N3677 (???,???) [004230] ----------- t4230 = * PUTARG_REG int REG x1 /--* t4227 ref arg3 in x2 +--* t4228 byref this in x0 +--* t4229 long r2r cell in x11 +--* t4230 int arg2 in x1 N3679 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void REG NA $VN.Void ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} N3683 (???,???) [003945] ----------- IL_OFFSET void INLRT @ 0x7FF[E-] REG NA N3685 ( 0, 0) [000220] ----------- RETURN void REG NA $VN.Void ------------ BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} N001 ( 1, 1) [004395] ----------Z t4395 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004396] ----------Z t4396 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004397] ----------Z t4397 = LCL_VAR int V144 tmp104 x8 REG x8 N1665 (???,???) [003946] ----------- IL_OFFSET void INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] REG NA N1667 ( 1, 1) [001744] ----------- t1744 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1744 byref N1669 (???,???) [004231] ----------- t4231 = * PUTARG_REG byref REG x0 N1671 ( 1, 1) [001745] ----------- t1745 = LCL_VAR ref V86 tmp46 u:1 x11 (last use) REG x11 /--* t1745 ref N1673 (???,???) [004232] ----------- t4232 = * PUTARG_REG ref REG x1 N1675 ( 2, 8) [002780] H---------- t2780 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2780 long N1677 (???,???) [004233] ----------- t4233 = * PUTARG_REG long REG x11 /--* t4231 byref this in x0 +--* t4232 ref arg2 in x1 +--* t4233 long r2r cell in x11 N1679 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004398] ----------z t4398 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004399] ----------z t4399 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004400] ----------z t4400 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB113 [401..406) -> BB263 (cond), preds={BB247} succs={BB114,BB263} N1787 (???,???) [003947] ----------- IL_OFFSET void INLRT @ 0x401[E-] REG NA N1789 ( 1, 1) [000271] ----------- t271 = LCL_VAR int V14 loc10 u:2 x3 REG x3 $2ab N1791 ( 1, 2) [000272] -c--------- t272 = CNS_INT int 0 REG NA $c0 /--* t271 int +--* t272 int N1793 ( 3, 4) [000273] J------N--- * LE void REG NA $89f N1795 ( 5, 6) [000274] ----------- * JTRUE void REG NA $VN.Void ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} N1799 (???,???) [003948] ----------- IL_OFFSET void INLRT @ 0x406[E-] REG NA N1801 ( 1, 1) [000821] ----------- t821 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1803 ( 1, 2) [000822] -c--------- t822 = CNS_INT int 35 REG NA $ea /--* t821 int +--* t822 int N1805 ( 6, 4) [000823] -c-----N--- t823 = * EQ int REG NA N1807 ( 1, 1) [000919] ----------- t919 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1809 ( 1, 2) [000920] ----------- t920 = CNS_INT int 46 REG x11 $eb /--* t919 int +--* t920 int N1811 ( 6, 4) [000921] -c-----N--- t921 = * EQ int REG NA /--* t823 int +--* t921 int N1813 ( 13, 9) [003738] Jc-----N--- * AND void REG NA N1815 ( 15, 11) [000824] ----------- * JTRUE void REG NA $VN.Void ------------ BB115 [40C..418) -> BB264 (cond), preds={BB114} succs={BB117,BB264} N1819 (???,???) [003949] ----------- IL_OFFSET void INLRT @ 0x40C[E-] REG NA N1821 (???,???) [003950] ----------- IL_OFFSET void INLRT @ 0x412[E-] REG NA N1823 ( 1, 1) [000923] ----------Z t923 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1825 ( 1, 2) [000924] -c--------- t924 = CNS_INT int 48 REG NA $d8 /--* t923 int +--* t924 int N1827 ( 3, 4) [000925] J------N--- * EQ void REG NA N1829 ( 5, 6) [000926] ----------- * JTRUE void REG NA $VN.Void ------------ BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} N001 ( 1, 1) [004401] ----------Z t4401 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004402] ----------z t4402 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB264 [???..???) -> BB135 (always), preds={BB115} succs={BB135} N001 ( 1, 1) [004332] ----------z t4332 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB263 [???..???) -> BB136 (always), preds={BB113} succs={BB136} N001 ( 1, 1) [004331] ----------Z t4331 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} N1847 (???,???) [003951] ----------- IL_OFFSET void INLRT @ 0x41A[E-] REG NA N1849 ( 1, 1) [000830] ----------- t830 = LCL_VAR long V36 loc32 u:7 x0 REG x0 $904 /--* t830 long N1851 ( 4, 3) [000831] ---XG------ t831 = * IND ubyte REG x11 /--* t831 ubyte N1853 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 x11 REG x11 N1855 ( 1, 1) [003679] ----------- t3679 = LCL_VAR int V177 cse6 u:1 x11 REG x11 N1857 ( 1, 2) [000832] -c--------- t832 = CNS_INT int 0 REG NA $c0 /--* t3679 int +--* t832 int N1859 ( 7, 7) [000833] CNE---XG--N--- * JCMP void REG NA ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} N1863 ( 1, 2) [000912] ----------- t912 = CNS_INT int 48 REG x14 $d8 /--* t912 int N1865 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 x14 REG x14 ------------ BB120 [424..42C), preds={BB118} succs={BB121} N1869 ( 1, 1) [000840] ----------- t840 = LCL_VAR long V36 loc32 u:7 x0 (last use) REG x0 $904 /--* t840 long N1871 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 x0 REG x0 N1873 ( 1, 1) [000841] ----------- t841 = LCL_VAR long V61 tmp21 u:1 x0 (last use) REG x0 $904 N1875 ( 1, 2) [000843] -c--------- t843 = CNS_INT long 1 REG NA $204 /--* t841 long +--* t843 long N1877 ( 3, 4) [000844] ----------- t844 = * ADD long REG x0 $adc /--* t844 long N1879 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 NA REG NA N1881 ( 1, 1) [003681] ----------- t3681 = LCL_VAR int V177 cse6 u:1 x11 (last use) REG x11 /--* t3681 int N1883 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 x14 REG x14 N001 ( 1, 1) [004403] ----------z t4403 = LCL_VAR long V36 loc32 x0 REG x0 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} N1887 ( 1, 1) [000858] ----------- t858 = LCL_VAR int V63 tmp23 u:1 x14 (last use) REG x14 $b16 /--* t858 int N1889 ( 2, 3) [001796] ----------- t1796 = * CAST int <- ushort <- int REG x11 $c75 /--* t1796 int N1891 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 x11 REG x11 N1893 (???,???) [003952] ----------- IL_OFFSET void INL29 @ 0x000[E-] <- INLRT @ ??? REG NA N1895 ( 1, 1) [000857] ----------- t857 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t857 byref N1897 ( 3, 4) [002795] -c--------- t2795 = * LEA(b+8) byref REG NA /--* t2795 byref N1899 ( 4, 3) [001797] ---XG------ t1797 = * IND int REG x14 /--* t1797 int N1901 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 x14 REG x14 N1903 (???,???) [003953] ----------- IL_OFFSET void INL29 @ 0x007[E-] <- INLRT @ ??? REG NA N1905 ( 1, 1) [001800] ----------- t1800 = LCL_VAR int V91 tmp51 u:1 x14 REG x14 N1907 ( 1, 1) [001801] ----------- t1801 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1801 byref N1909 ( 3, 4) [002799] -c--------- t2799 = * LEA(b+24) byref REG NA /--* t2799 byref N1911 ( 4, 3) [001839] n---GO----- t1839 = * IND int REG x12 /--* t1800 int +--* t1839 int N1913 ( 6, 5) [001805] N---GO-N-U- * GE void REG NA N1915 ( 8, 7) [001806] ----GO----- * JTRUE void REG NA $845 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} N1919 (???,???) [003954] ----------- IL_OFFSET void INL29 @ 0x015[E-] <- INLRT @ ??? REG NA N1921 ( 1, 1) [002803] ----------- t2803 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N1923 ( 1, 2) [002804] -c--------- t2804 = CNS_INT long 16 REG NA $200 /--* t2803 byref +--* t2804 long N1925 ( 3, 4) [002805] -----O----- t2805 = * ADD byref REG x12 $25c /--* t2805 byref N1927 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 x12 REG x12 N1929 ( 1, 1) [001812] ----------- t1812 = LCL_VAR int V91 tmp51 u:1 x14 REG x14 N1931 ( 1, 1) [001817] ----------- t1817 = LCL_VAR byref V93 tmp53 u:1 x12 REG x12 $25c /--* t1817 byref N1933 ( 3, 4) [002808] -c--------- t2808 = * LEA(b+8) byref REG NA /--* t2808 byref N1935 ( 4, 3) [001818] n---GO----- t1818 = * IND int REG x15 /--* t1812 int +--* t1818 int N1937 ( 9, 11) [001819] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N1939 ( 1, 1) [001816] ----------- t1816 = LCL_VAR byref V93 tmp53 u:1 x12 (last use) REG x12 $25c /--* t1816 byref N1941 ( 3, 2) [001823] n---GO----- t1823 = * IND byref REG x12 N1943 ( 1, 1) [001813] ----------- t1813 = LCL_VAR int V91 tmp51 u:1 x14 REG x14 /--* t1813 int N1945 ( 2, 3) [001820] -c-------U- t1820 = * CAST long <- uint REG NA N1947 ( 1, 2) [001821] -c--------- t1821 = CNS_INT long 1 REG NA $204 /--* t1820 long +--* t1821 long N1949 ( 4, 6) [001822] -c--------- t1822 = * BFIZ long REG NA /--* t1823 byref +--* t1822 long N1951 ( 8, 9) [001824] -c--------- t1824 = * LEA(b+(i*1)+0) byref REG NA N1953 ( 1, 1) [001826] ----------- t1826 = LCL_VAR int V92 tmp52 u:1 x11 (last use) REG x11 $c75 /--* t1824 byref +--* t1826 int N1955 (???,???) [003955] -A-XGO----- * STOREIND short REG NA N1957 (???,???) [003956] ----------- IL_OFFSET void INL29 @ 0x023[E-] <- INLRT @ ??? REG NA N1959 ( 1, 1) [001830] ----------- t1830 = LCL_VAR int V91 tmp51 u:1 x14 (last use) REG x14 N1961 ( 1, 2) [001831] -c--------- t1831 = CNS_INT int 1 REG NA $c1 /--* t1830 int +--* t1831 int N1963 ( 3, 4) [001832] ----------- t1832 = * ADD int REG x11 N1965 ( 1, 1) [001829] ----------- t1829 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1829 byref N1967 ( 3, 4) [002811] -c--------- t2811 = * LEA(b+8) byref REG NA /--* t2811 byref +--* t1832 int N1969 (???,???) [003957] -A--GO----- * STOREIND int REG NA ------------ BB123 [000..000), preds={BB121} succs={BB124} N001 ( 1, 1) [004404] ----------Z t4404 = LCL_VAR ushort V18 loc14 x13 REG x13 N001 ( 1, 1) [004405] ----------Z t4405 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004406] ----------Z t4406 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004407] ----------Z t4407 = LCL_VAR int V144 tmp104 x8 REG x8 N1973 (???,???) [003958] ----------- IL_OFFSET void INL29 @ 0x02D[E-] <- INLRT @ ??? REG NA N1975 ( 1, 1) [001807] ----------- t1807 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1807 byref N1977 (???,???) [004234] ----------- t4234 = * PUTARG_REG byref REG x0 N1979 ( 1, 1) [001808] ----------- t1808 = LCL_VAR int V92 tmp52 u:1 x11 (last use) REG x11 $c75 /--* t1808 int N1981 (???,???) [004235] ----------- t4235 = * PUTARG_REG int REG x1 N1983 ( 2, 8) [002812] H---------- t2812 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t2812 long N1985 (???,???) [004236] ----------- t4236 = * PUTARG_REG long REG x11 /--* t4234 byref this in x0 +--* t4235 int arg2 in x1 +--* t4236 long r2r cell in x11 N1987 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004408] ----------z t4408 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004409] ----------z t4409 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004410] ----------z t4410 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004411] ----------z t4411 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} N1991 (???,???) [003959] ----------- IL_OFFSET void INLRT @ 0x431[E-] REG NA N1993 ( 1, 1) [000860] ----------z t860 = LCL_VAR int V12 loc8 u:3 x7 REG x7 $4c4 N1995 ( 1, 2) [000861] -c--------- t861 = CNS_INT int 0 REG NA $c0 /--* t860 int +--* t861 int N1997 ( 6, 4) [000862] -c-----N--- t862 = * EQ int REG NA $70a N1999 ( 1, 1) [000874] ----------z t874 = LCL_VAR int V08 loc4 u:5 x2 REG x2 $b15 N2001 ( 1, 2) [000875] -c--------- t875 = CNS_INT int 1 REG NA $c1 /--* t874 int +--* t875 int N2003 ( 6, 4) [000876] -c-----N--- t876 = * LE int REG NA $d03 /--* t862 int +--* t876 int N2005 ( 13, 9) [003740] Jc-----N--- * AND void REG NA N2007 ( 15, 11) [000863] ----------- * JTRUE void REG NA $VN.Void ------------ BB125 [435..43F) -> BB265 (cond), preds={BB124} succs={BB127,BB265} N2011 (???,???) [003960] ----------- IL_OFFSET void INLRT @ 0x435[E-] REG NA N2013 (???,???) [003961] ----------- IL_OFFSET void INLRT @ 0x43A[E-] REG NA N2015 ( 1, 1) [000885] ----------- t885 = LCL_VAR int V20 loc16 u:7 x9 REG x9 $b13 N2017 ( 1, 1) [000889] ----------Z t889 = LCL_VAR int V144 tmp104 u:2 x8 REG x8 $2a6 /--* t885 int +--* t889 int N2019 ( 6, 9) [000890] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $c31 N2021 ( 1, 1) [000894] ----------z t894 = LCL_VAR byref V143 tmp103 u:2 x6 REG x6 $385 N2023 ( 1, 1) [000886] ----------- t886 = LCL_VAR int V20 loc16 u:7 x9 REG x9 $b13 /--* t886 int N2025 ( 2, 3) [000891] -c-------U- t891 = * CAST long <- uint REG NA $ae2 N2027 ( 1, 2) [000892] -c--------- t892 = CNS_INT long 2 REG NA $20a /--* t891 long +--* t892 long N2029 ( 4, 6) [000893] -c--------- t893 = * BFIZ long REG NA /--* t894 byref +--* t893 long N2031 ( 6, 8) [000895] -c--------- t895 = * LEA(b+(i*1)+0) byref REG NA /--* t895 byref N2033 ( 8, 9) [002813] ---XGO----- t2813 = * IND int REG x11 N2035 ( 1, 2) [000898] -c--------- t898 = CNS_INT int 1 REG NA $c1 /--* t2813 int +--* t898 int N2037 ( 16, 21) [000899] ---XGO----- t899 = * ADD int REG x11 N2039 ( 1, 1) [000882] ----------Z t882 = LCL_VAR int V08 loc4 u:5 x2 REG x2 $b15 /--* t899 int +--* t882 int N2041 ( 21, 23) [000900] Nc-XGO-N-U- t900 = * NE int REG NA N2043 ( 1, 1) [000878] ----------Z t878 = LCL_VAR int V20 loc16 u:7 x9 REG x9 $b13 N2045 ( 1, 2) [000879] -c--------- t879 = CNS_INT int 0 REG NA $c0 /--* t878 int +--* t879 int N2047 ( 6, 4) [000880] -c-----N--- t880 = * LT int REG NA $d04 /--* t900 int +--* t880 int N2049 ( 28, 28) [003742] Jc-XGO-N--- * AND void REG NA N2051 ( 30, 30) [000881] ---XGO----- * JTRUE void REG NA $VN.Void ------------ BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} N2055 (???,???) [003962] ----------- IL_OFFSET void INLRT @ 0x43F[E-] REG NA N2057 (???,???) [003963] ----------- IL_OFFSET void INLRT @ 0x44F[E-] REG NA N2059 ( 1, 1) [000903] ----------- t903 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t903 ref N2061 ( 3, 4) [002815] -c--------- t2815 = * LEA(b+56) byref REG NA /--* t2815 byref N2063 ( 4, 3) [001843] ---XG------ t1843 = * IND ref REG x11 /--* t1843 ref N2065 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 x11 REG x11 N2067 (???,???) [003964] ----------- IL_OFFSET void INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] REG NA N2069 ( 1, 1) [001845] ----------- t1845 = LCL_VAR ref V95 tmp55 u:1 x11 REG x11 N2071 ( 1, 2) [001846] -c--------- t1846 = CNS_INT ref null REG NA $VN.Null /--* t1845 ref +--* t1846 ref N2073 ( 3, 4) [001847] CEQ-------N--- * JCMP void REG NA ------------ BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} N2077 (???,???) [003965] ----------- IL_OFFSET void INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] REG NA N2079 ( 1, 1) [000902] ----------- t902 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t902 byref N2081 ( 3, 4) [002817] -c--------- t2817 = * LEA(b+8) byref REG NA /--* t2817 byref N2083 ( 4, 3) [001849] n---GO----- t1849 = * IND int REG x14 /--* t1849 int N2085 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 x14 REG x14 N2087 (???,???) [003966] ----------- IL_OFFSET void INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] REG NA N2089 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 x11 REG x11 /--* t1852 ref N2091 (???,???) [004168] -c--------- t4168 = * LEA(b+8) byref REG NA /--* t4168 byref N2093 ( 3, 3) [001853] ---X------- t1853 = * IND int REG x12 /--* t1853 int N2095 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 x12 REG x12 N2097 ( 1, 1) [003717] ----------- t3717 = LCL_VAR int V181 cse10 u:1 x12 REG x12 N2099 ( 1, 2) [001854] -c--------- t1854 = CNS_INT int 1 REG NA $c1 /--* t3717 int +--* t1854 int N2101 ( 9, 7) [001855] Nc-X---N-U- t1855 = * NE int REG NA N2103 ( 1, 1) [001860] ----------- t1860 = LCL_VAR int V96 tmp56 u:1 x14 REG x14 N2105 ( 1, 1) [001861] ----------- t1861 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1861 byref N2107 ( 3, 4) [002821] -c--------- t2821 = * LEA(b+24) byref REG NA /--* t2821 byref N2109 ( 4, 3) [001899] n---GO----- t1899 = * IND int REG x15 /--* t1860 int +--* t1899 int N2111 ( 9, 5) [001865] Nc--GO-N-U- t1865 = * GE int REG NA /--* t1855 int +--* t1865 int N2113 ( 19, 13) [003744] Jc-XGO-N--- * AND void REG NA N2115 ( 21, 15) [001856] ---XGO----- * JTRUE void REG NA ------------ BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} N2119 (???,???) [003967] ----------- IL_OFFSET void INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] REG NA N2121 (???,???) [003968] ----------- IL_OFFSET void INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] REG NA N2123 ( 1, 1) [002825] ----------- t2825 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N2125 ( 1, 2) [002826] -c--------- t2826 = CNS_INT long 16 REG NA $200 /--* t2825 byref +--* t2826 long N2127 ( 3, 4) [002827] -----O----- t2827 = * ADD byref REG x15 $25c /--* t2827 byref N2129 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 x15 REG x15 N2131 (???,???) [003969] ----------- IL_OFFSET void INL32 @ ??? <- INLRT @ 0x44F[E-] REG NA N2133 ( 1, 1) [001869] ----------- t1869 = LCL_VAR int V96 tmp56 u:1 x14 REG x14 N2135 ( 1, 1) [001874] ----------- t1874 = LCL_VAR byref V97 tmp57 u:1 x15 REG x15 $25c /--* t1874 byref N2137 ( 3, 4) [002830] -c--------- t2830 = * LEA(b+8) byref REG NA /--* t2830 byref N2139 ( 4, 3) [001875] n---GO----- t1875 = * IND int REG xip0 /--* t1869 int +--* t1875 int N2141 ( 9, 11) [001876] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2143 ( 1, 1) [001873] ----------- t1873 = LCL_VAR byref V97 tmp57 u:1 x15 (last use) REG x15 $25c /--* t1873 byref N2145 ( 3, 2) [001880] n---GO----- t1880 = * IND byref REG x15 N2147 ( 1, 1) [001870] ----------- t1870 = LCL_VAR int V96 tmp56 u:1 x14 REG x14 /--* t1870 int N2149 ( 2, 3) [001877] -c-------U- t1877 = * CAST long <- uint REG NA N2151 ( 1, 2) [001878] -c--------- t1878 = CNS_INT long 1 REG NA $204 /--* t1877 long +--* t1878 long N2153 ( 4, 6) [001879] ----------- t1879 = * BFIZ long REG xip0 /--* t1880 byref +--* t1879 long N2155 ( 8, 9) [001881] ----GO-N--- t1881 = * ADD byref REG x15 N2157 ( 1, 2) [001884] -c--------- t1884 = CNS_INT int 0 REG NA $c0 N2159 ( 1, 1) [003719] ----------- t3719 = LCL_VAR int V181 cse10 u:1 x12 (last use) REG x12 /--* t1884 int +--* t3719 int N2161 ( 6, 10) [002835] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2163 ( 1, 1) [002832] ----------- t2832 = LCL_VAR ref V95 tmp55 u:1 x11 (last use) REG x11 /--* t2832 ref N2165 ( 1, 1) [002839] -c--------- t2839 = * LEA(b+12) byref REG NA /--* t2839 byref N2167 ( 5, 4) [002844] n---GO----- t2844 = * IND ushort REG x11 /--* t1881 byref +--* t2844 ushort N2169 (???,???) [003970] -A-XGO----- * STOREIND short REG NA N2171 (???,???) [003971] ----------- IL_OFFSET void INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] REG NA N2173 ( 1, 1) [001890] ----------- t1890 = LCL_VAR int V96 tmp56 u:1 x14 (last use) REG x14 N2175 ( 1, 2) [001891] -c--------- t1891 = CNS_INT int 1 REG NA $c1 /--* t1890 int +--* t1891 int N2177 ( 3, 4) [001892] ----------- t1892 = * ADD int REG x11 N2179 ( 1, 1) [001889] ----------- t1889 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1889 byref N2181 ( 3, 4) [002846] -c--------- t2846 = * LEA(b+8) byref REG NA /--* t2846 byref +--* t1892 int N2183 (???,???) [003972] -A--GO----- * STOREIND int REG NA ------------ BB265 [???..???) -> BB134 (always), preds={BB125} succs={BB134} N001 ( 1, 1) [004333] ----------z t4333 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004334] ----------z t4334 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004335] ----------z t4335 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB132 [44F..450), preds={BB129} succs={BB133} N001 ( 1, 1) [004412] ----------Z t4412 = LCL_VAR ushort V18 loc14 x13 REG x13 N001 ( 1, 1) [004413] ----------Z t4413 = LCL_VAR long V36 loc32 x0 REG x0 N2187 (???,???) [003973] ----------- IL_OFFSET void INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] REG NA N2189 ( 1, 1) [001857] ----------- t1857 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1857 byref N2191 (???,???) [004237] ----------- t4237 = * PUTARG_REG byref REG x0 N2193 ( 1, 1) [001858] ----------- t1858 = LCL_VAR ref V95 tmp55 u:1 x11 (last use) REG x11 /--* t1858 ref N2195 (???,???) [004238] ----------- t4238 = * PUTARG_REG ref REG x1 N2197 ( 2, 8) [002847] H---------- t2847 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2847 long N2199 (???,???) [004239] ----------- t4239 = * PUTARG_REG long REG x11 /--* t4237 byref this in x0 +--* t4238 ref arg2 in x1 +--* t4239 long r2r cell in x11 N2201 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004414] ----------z t4414 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004415] ----------z t4415 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} N2205 (???,???) [003974] ----------- IL_OFFSET void INLRT @ 0x45B[E-] REG NA N2207 ( 1, 1) [000907] ----------z t907 = LCL_VAR int V20 loc16 u:7 x9 (last use) REG x9 $b13 N2209 ( 1, 2) [000908] -c--------- t908 = CNS_INT int -1 REG NA $c4 /--* t907 int +--* t908 int N2211 ( 3, 4) [000909] ----------- t909 = * ADD int REG x9 $d27 /--* t909 int N2213 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 NA REG NA N001 ( 1, 1) [004416] ----------z t4416 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004417] ----------z t4417 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004418] ----------z t4418 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB134 [461..46D), preds={BB124,BB133,BB265} succs={BB135} N2217 (???,???) [003975] ----------- IL_OFFSET void INLRT @ 0x461[E-] REG NA N2219 ( 1, 1) [000864] ----------- t864 = LCL_VAR int V08 loc4 u:5 x2 (last use) REG x2 $b15 N2221 ( 1, 2) [000865] -c--------- t865 = CNS_INT int -1 REG NA $c4 /--* t864 int +--* t865 int N2223 ( 3, 4) [000866] ----------- t866 = * ADD int REG x2 $d29 /--* t866 int N2225 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 NA REG NA N2227 (???,???) [003976] ----------- IL_OFFSET void INLRT @ 0x467[E-] REG NA N2229 ( 1, 1) [000869] ----------z t869 = LCL_VAR int V14 loc10 u:6 x3 (last use) REG x3 $b14 N2231 ( 1, 2) [000870] -c--------- t870 = CNS_INT int -1 REG NA $c4 /--* t869 int +--* t870 int N2233 ( 3, 4) [000871] ----------- t871 = * ADD int REG x3 $d2a /--* t871 int N2235 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 NA REG NA N001 ( 1, 1) [004419] ----------z t4419 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB134,BB264} succs={BB136,BB118} N1835 (???,???) [003977] ----------- IL_OFFSET void INLRT @ 0x46D[E-] REG NA N1837 ( 1, 1) [000825] ----------Z t825 = LCL_VAR int V14 loc10 u:6 x3 REG x3 $b14 N1839 ( 1, 2) [000826] -c--------- t826 = CNS_INT int 0 REG NA $c0 /--* t825 int +--* t826 int N1841 ( 3, 4) [000827] J------N--- * GT void REG NA $c6e N1843 ( 5, 6) [000828] ----------- * JTRUE void REG NA $VN.Void ------------ BB136 [472..478) -> BB141 (cond), preds={BB117,BB135,BB263} succs={BB137,BB141} N2239 (???,???) [003978] ----------- IL_OFFSET void INLRT @ 0x472[E-] REG NA N2241 ( 1, 1) [000275] ----------- t275 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2243 ( 1, 2) [000276] -c--------- t276 = CNS_INT int 69 REG NA $d2 /--* t275 int +--* t276 int N2245 ( 3, 4) [000277] N------N-U- * GT void REG NA N2247 ( 5, 6) [000278] ----------- * JTRUE void REG NA $VN.Void ------------ BB137 [478..478) -> BB138 (cond), preds={BB136} succs={BB257,BB138} N2251 (???,???) [003979] ----------- IL_OFFSET void INLRT @ 0x478[E-] REG NA N2253 ( 1, 1) [000593] ----------- t593 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2255 ( 1, 2) [000594] -c--------- t594 = CNS_INT int -34 REG NA $d6 /--* t593 int +--* t594 int N2257 ( 3, 4) [000595] ----------- t595 = * ADD int REG x14 /--* t595 int N2259 (???,???) [004241] DA--------- * STORE_LCL_VAR int V184 rat2 x14 REG x14 N2261 ( 3, 2) [004243] ----------- t4243 = LCL_VAR int V184 rat2 x14 REG x14 N2263 ( 1, 2) [004244] -c--------- t4244 = CNS_INT int 5 REG NA /--* t4243 int +--* t4244 int N2265 ( 8, 5) [004245] ---------U- * GT void REG NA N2267 ( 10, 7) [004246] ----------- * JTRUE void REG NA ------------ BB257 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194 (switch), preds={BB137} succs={BB145,BB186,BB194,BB242} N3937 (???,???) [004247] ----------- t4247 = LCL_VAR int V184 rat2 x14 (last use) REG x14 /--* t4247 int N3939 (???,???) [004248] ---------U- t4248 = * CAST long <- ulong <- uint REG x11 N3941 (???,???) [004249] ----------- t4249 = JMPTABLE long REG x14 /--* t4248 long +--* t4249 long N3943 (???,???) [004250] ----------- * SWITCH_TABLE void REG NA ------------ BB138 [49A..49A) -> BB139 (cond), preds={BB137} succs={BB258,BB139} N2271 (???,???) [003980] ----------- IL_OFFSET void INLRT @ 0x49A[E-] REG NA N2273 ( 1, 1) [000597] ----------- t597 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2275 ( 1, 2) [000598] -c--------- t598 = CNS_INT int -44 REG NA $d7 /--* t597 int +--* t598 int N2277 ( 3, 4) [000599] ----------- t599 = * ADD int REG x12 /--* t599 int N2279 (???,???) [004252] DA--------- * STORE_LCL_VAR int V185 rat3 x12 REG x12 N2281 ( 3, 2) [004254] ----------- t4254 = LCL_VAR int V185 rat3 x12 REG x12 N2283 ( 1, 2) [004255] -c--------- t4255 = CNS_INT int 4 REG NA /--* t4254 int +--* t4255 int N2285 ( 8, 5) [004256] ---------U- * GT void REG NA N2287 ( 10, 7) [004257] ----------- * JTRUE void REG NA ------------ BB258 [49A..4B8) -> BB266,BB242,BB171,BB242,BB145 (switch), preds={BB138} succs={BB145,BB171,BB242,BB266} N4791 (???,???) [004258] ----------- t4258 = LCL_VAR int V185 rat3 x12 (last use) REG x12 /--* t4258 int N4793 (???,???) [004259] ---------U- t4259 = * CAST long <- ulong <- uint REG x11 N4795 (???,???) [004260] ----------- t4260 = JMPTABLE long REG x14 /--* t4259 long +--* t4260 long N4797 (???,???) [004261] ----------- * SWITCH_TABLE void REG NA ------------ BB266 [???..???) -> BB245 (always), preds={BB258} succs={BB245} N001 ( 1, 1) [004336] ----------z t4336 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} N2291 (???,???) [003981] ----------- IL_OFFSET void INLRT @ 0x4B8[E-] REG NA N2293 ( 1, 1) [000601] ----------- t601 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2295 ( 1, 2) [000602] -c--------- t602 = CNS_INT int 69 REG NA $d2 /--* t601 int +--* t602 int N2297 ( 3, 4) [000603] J------N--- * EQ void REG NA N2299 ( 5, 6) [000604] ----------- * JTRUE void REG NA $VN.Void ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} N2305 (???,???) [003982] ----------- IL_OFFSET void INLRT @ 0x4C6[E-] REG NA N2307 ( 1, 1) [000279] ----------- t279 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2309 ( 1, 2) [000280] -c--------- t280 = CNS_INT int 92 REG NA $d3 /--* t279 int +--* t280 int N2311 ( 3, 4) [000281] J------N--- * EQ void REG NA N2313 ( 5, 6) [000282] ----------- * JTRUE void REG NA $VN.Void ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} N2317 (???,???) [003983] ----------- IL_OFFSET void INLRT @ 0x4CF[E-] REG NA N2319 ( 1, 1) [000319] ----------- t319 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2321 ( 1, 2) [000320] -c--------- t320 = CNS_INT int 101 REG NA $d4 /--* t319 int +--* t320 int N2323 ( 3, 4) [000321] J------N--- * EQ void REG NA N2325 ( 5, 6) [000322] ----------- * JTRUE void REG NA $VN.Void ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} N2329 (???,???) [003984] ----------- IL_OFFSET void INLRT @ 0x4D8[E-] REG NA N2331 ( 1, 1) [000581] ----------- t581 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2333 ( 1, 4) [000582] ----------- t582 = CNS_INT int 0x2030 REG x11 $d5 /--* t581 int +--* t582 int N2335 ( 3, 6) [000583] J------N--- * NE void REG NA N2337 ( 5, 8) [000584] ----------- * JTRUE void REG NA $VN.Void ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} N2341 (???,???) [003985] ----------- IL_OFFSET void INLRT @ 0x598[E-] REG NA N2343 ( 1, 1) [000586] ----------- t586 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t586 ref N2345 ( 3, 4) [002849] -c--------- t2849 = * LEA(b+136) byref REG NA /--* t2849 byref N2347 ( 4, 3) [002066] ---XG------ t2066 = * IND ref REG x11 /--* t2066 ref N2349 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 x11 REG x11 ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB257,BB258} succs={BB146,BB150} N3947 (???,???) [003986] ----------- IL_OFFSET void INLRT @ 0x4E9[E-] REG NA N3949 ( 1, 1) [000639] ----------z t639 = LCL_VAR int V14 loc10 u:3 x3 REG x3 $2b4 N3951 ( 1, 2) [000640] -c--------- t640 = CNS_INT int 0 REG NA $c0 /--* t639 int +--* t640 int N3953 ( 3, 4) [000641] J------N--- * GE void REG NA $9ff N3955 ( 5, 6) [000642] ----------- * JTRUE void REG NA $VN.Void ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} N3959 (???,???) [003987] ----------- IL_OFFSET void INLRT @ 0x4EE[E-] REG NA N3961 ( 1, 1) [000731] ----------- t731 = LCL_VAR int V14 loc10 u:3 x3 (last use) REG x3 $2b4 N3963 ( 1, 2) [000732] -c--------- t732 = CNS_INT int 1 REG NA $c1 /--* t731 int +--* t732 int N3965 ( 3, 4) [000733] ----------- t733 = * ADD int REG x3 $a88 /--* t733 int N3967 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 NA REG NA N3969 (???,???) [003988] ----------- IL_OFFSET void INLRT @ 0x4F4[E-] REG NA N3971 ( 1, 1) [000736] ----------z t736 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 N3973 ( 1, 1) [000737] ----------- t737 = LCL_VAR int V06 loc2 u:3 x22 REG x22 $292 /--* t736 int +--* t737 int N3975 ( 3, 3) [000738] J------N--- * LE void REG NA $a89 N3977 ( 5, 5) [000739] ----------- * JTRUE void REG NA $VN.Void ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} N3981 (???,???) [003989] ----------- IL_OFFSET void INLRT @ 0x4F9[E-] REG NA N3983 ( 1, 2) [000747] -c--------- t747 = CNS_INT int 0 REG NA $c0 /--* t747 int N3985 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 x13 REG x13 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} N3989 (???,???) [003990] ----------- IL_OFFSET void INLRT @ 0x4FC[E-] REG NA N3991 ( 1, 2) [000740] ----------- t740 = CNS_INT int 48 REG x13 $d8 /--* t740 int N3993 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 x13 REG x13 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} N3997 ( 1, 1) [000744] ----------- t744 = LCL_VAR int V58 tmp18 u:1 x13 (last use) REG x13 $2bd /--* t744 int N3999 ( 2, 3) [002850] ----------- t2850 = * CAST int <- ushort <- int REG x13 $a8a /--* t2850 int N4001 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 x13 REG x13 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} N4005 (???,???) [003991] ----------- IL_OFFSET void INLRT @ 0x502[E-] REG NA N4007 ( 1, 1) [000643] ----------- t643 = LCL_VAR long V36 loc32 u:3 x0 REG x0 $901 /--* t643 long N4009 ( 4, 3) [000644] ---XG------ t644 = * IND ubyte REG x13 N4011 ( 1, 2) [000645] -c--------- t645 = CNS_INT int 0 REG NA $c0 /--* t644 ubyte +--* t645 int N4013 ( 6, 6) [000646] CNE---XG--N--- * JCMP void REG NA ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} N4017 (???,???) [003992] ----------- IL_OFFSET void INLRT @ 0x507[E-] REG NA N4019 ( 1, 1) [000719] ----------z t719 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 N4021 ( 1, 1) [000720] ----------z t720 = LCL_VAR int V07 loc3 u:3 x1 REG x1 $293 /--* t719 int +--* t720 int N4023 ( 3, 3) [000721] J------N--- * GT void REG NA $a86 N4025 ( 5, 5) [000722] ----------- * JTRUE void REG NA $VN.Void ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} N4029 (???,???) [003993] ----------- IL_OFFSET void INLRT @ 0x50C[E-] REG NA N4031 ( 1, 2) [000727] -c--------- t727 = CNS_INT int 0 REG NA $c0 /--* t727 int N4033 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 x11 REG x11 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} N4037 (???,???) [003994] ----------- IL_OFFSET void INLRT @ 0x50F[E-] REG NA N4039 ( 1, 2) [000723] ----------- t723 = CNS_INT int 48 REG x11 $d8 /--* t723 int N4041 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 x11 REG x11 ------------ BB154 [513..51B), preds={BB150} succs={BB155} N4045 (???,???) [003995] ----------- IL_OFFSET void INLRT @ 0x513[E-] REG NA N4047 ( 1, 1) [000648] ----------- t648 = LCL_VAR long V36 loc32 u:3 x0 (last use) REG x0 $901 /--* t648 long N4049 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 x11 REG x11 N4051 (???,???) [003996] ----------- IL_OFFSET void INLRT @ 0x513[E-] REG NA N4053 ( 1, 1) [000649] ----------- t649 = LCL_VAR long V56 tmp16 u:1 x11 REG x11 $901 N4055 ( 1, 2) [000651] -c--------- t651 = CNS_INT long 1 REG NA $204 /--* t649 long +--* t651 long N4057 ( 3, 4) [000652] ----------- t652 = * ADD long REG x0 $3fb /--* t652 long N4059 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 NA REG NA N4061 ( 1, 1) [000657] ----------- t657 = LCL_VAR long V56 tmp16 u:1 x11 (last use) REG x11 $901 /--* t657 long N4063 ( 4, 3) [000658] ---XG------ t658 = * IND ubyte REG x11 /--* t658 ubyte N4065 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 x11 REG x11 N001 ( 1, 1) [004420] ----------z t4420 = LCL_VAR long V36 loc32 x0 REG x0 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} N4069 ( 1, 1) [000662] ----------- t662 = LCL_VAR int V57 tmp17 u:1 x11 (last use) REG x11 $2bc /--* t662 int N4071 ( 2, 3) [002851] ----------- t2851 = * CAST int <- ushort <- int REG x13 $a87 /--* t2851 int N4073 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 x13 REG x13 N001 ( 1, 1) [004421] ----------Z t4421 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004422] ----------z t4422 = LCL_VAR int V08 loc4 x2 REG x2 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} N4077 (???,???) [003997] ----------- IL_OFFSET void INLRT @ 0x51D[E-] REG NA N4079 ( 1, 1) [000665] ----------- t665 = LCL_VAR int V18 loc14 u:2 x13 REG x13 $5c9 N4081 ( 1, 2) [000666] -c--------- t666 = CNS_INT int 0 REG NA $c0 /--* t665 int +--* t666 int N4083 ( 3, 4) [000667] CEQ-------N--- * JCMP void REG NA ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} N4087 (???,???) [003998] ----------- IL_OFFSET void INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] REG NA N4089 ( 1, 1) [000674] ----------- t674 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t674 byref N4091 ( 3, 4) [002853] -c--------- t2853 = * LEA(b+8) byref REG NA /--* t2853 byref N4093 ( 4, 3) [001903] ---XG------ t1903 = * IND int REG x11 /--* t1903 int N4095 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 x11 REG x11 N4097 (???,???) [003999] ----------- IL_OFFSET void INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] REG NA N4099 ( 1, 1) [001906] ----------- t1906 = LCL_VAR int V99 tmp59 u:1 x11 REG x11 N4101 ( 1, 1) [001907] ----------- t1907 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1907 byref N4103 ( 3, 4) [002857] -c--------- t2857 = * LEA(b+24) byref REG NA /--* t2857 byref N4105 ( 4, 3) [001942] n---GO----- t1942 = * IND int REG x14 /--* t1906 int +--* t1942 int N4107 ( 6, 5) [001911] N---GO-N-U- * GE void REG NA N4109 ( 8, 7) [001912] ----GO----- * JTRUE void REG NA $845 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} N4113 (???,???) [004000] ----------- IL_OFFSET void INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] REG NA N4115 ( 1, 1) [002861] ----------- t2861 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4117 ( 1, 2) [002862] -c--------- t2862 = CNS_INT long 16 REG NA $200 /--* t2861 byref +--* t2862 long N4119 ( 3, 4) [002863] -----O----- t2863 = * ADD byref REG x14 $25c /--* t2863 byref N4121 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 x14 REG x14 N4123 (???,???) [004001] ----------- IL_OFFSET void INL34 @ ??? <- INLRT @ 0x521[E-] REG NA N4125 ( 1, 1) [001917] ----------- t1917 = LCL_VAR int V99 tmp59 u:1 x11 REG x11 N4127 ( 1, 1) [001922] ----------- t1922 = LCL_VAR byref V100 tmp60 u:1 x14 REG x14 $25c /--* t1922 byref N4129 ( 3, 4) [002866] -c--------- t2866 = * LEA(b+8) byref REG NA /--* t2866 byref N4131 ( 4, 3) [001923] n---GO----- t1923 = * IND int REG x12 /--* t1917 int +--* t1923 int N4133 ( 9, 11) [001924] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4135 ( 1, 1) [001921] ----------- t1921 = LCL_VAR byref V100 tmp60 u:1 x14 (last use) REG x14 $25c /--* t1921 byref N4137 ( 3, 2) [001928] n---GO----- t1928 = * IND byref REG x14 N4139 ( 1, 1) [001918] ----------- t1918 = LCL_VAR int V99 tmp59 u:1 x11 REG x11 /--* t1918 int N4141 ( 2, 3) [001925] -c-------U- t1925 = * CAST long <- uint REG NA N4143 ( 1, 2) [001926] -c--------- t1926 = CNS_INT long 1 REG NA $204 /--* t1925 long +--* t1926 long N4145 ( 4, 6) [001927] -c--------- t1927 = * BFIZ long REG NA /--* t1928 byref +--* t1927 long N4147 ( 8, 9) [001929] -c--------- t1929 = * LEA(b+(i*1)+0) byref REG NA N4149 ( 1, 1) [001931] ----------- t1931 = LCL_VAR int V18 loc14 u:2 x13 (last use) REG x13 $5c9 /--* t1929 byref +--* t1931 int N4151 (???,???) [004002] -A-XGO----- * STOREIND short REG NA N4153 (???,???) [004003] ----------- IL_OFFSET void INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] REG NA N4155 ( 1, 1) [001935] ----------- t1935 = LCL_VAR int V99 tmp59 u:1 x11 (last use) REG x11 N4157 ( 1, 2) [001936] -c--------- t1936 = CNS_INT int 1 REG NA $c1 /--* t1935 int +--* t1936 int N4159 ( 3, 4) [001937] ----------- t1937 = * ADD int REG x13 N4161 ( 1, 1) [001934] ----------- t1934 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1934 byref N4163 ( 3, 4) [002869] -c--------- t2869 = * LEA(b+8) byref REG NA /--* t2869 byref +--* t1937 int N4165 (???,???) [004004] -A--GO----- * STOREIND int REG NA ------------ BB159 [521..522), preds={BB157} succs={BB160} N001 ( 1, 1) [004423] ----------Z t4423 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004424] ----------Z t4424 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004425] ----------Z t4425 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004426] ----------Z t4426 = LCL_VAR int V144 tmp104 x8 REG x8 N4169 (???,???) [004005] ----------- IL_OFFSET void INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] REG NA N4171 ( 1, 1) [001913] ----------- t1913 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1913 byref N4173 (???,???) [004262] ----------- t4262 = * PUTARG_REG byref REG x0 N4175 ( 1, 1) [000675] ----------- t675 = LCL_VAR int V18 loc14 u:2 x13 (last use) REG x13 $5c9 /--* t675 int N4177 (???,???) [004263] ----------- t4263 = * PUTARG_REG int REG x1 N4179 ( 2, 8) [002870] H---------- t2870 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t2870 long N4181 (???,???) [004264] ----------- t4264 = * PUTARG_REG long REG x11 /--* t4262 byref this in x0 +--* t4263 int arg2 in x1 +--* t4264 long r2r cell in x11 N4183 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004427] ----------z t4427 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004428] ----------z t4428 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004429] ----------z t4429 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004430] ----------z t4430 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} N4187 (???,???) [004006] ----------- IL_OFFSET void INLRT @ 0x529[E-] REG NA N4189 ( 1, 1) [000677] ----------z t677 = LCL_VAR int V12 loc8 u:3 x7 REG x7 $4c4 N4191 ( 1, 2) [000678] -c--------- t678 = CNS_INT int 0 REG NA $c0 /--* t677 int +--* t678 int N4193 ( 6, 4) [000679] -c-----N--- t679 = * EQ int REG NA $70a N4195 ( 1, 1) [000681] ----------- t681 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 N4197 ( 1, 2) [000682] -c--------- t682 = CNS_INT int 1 REG NA $c1 /--* t681 int +--* t682 int N4199 ( 6, 4) [000683] -c-----N--- t683 = * LE int REG NA $a93 /--* t679 int +--* t683 int N4201 ( 13, 9) [003746] Jc-----N--- * AND void REG NA N4203 ( 15, 11) [000680] ----------- * JTRUE void REG NA $VN.Void ------------ BB161 [52D..537) -> BB267 (cond), preds={BB160} succs={BB163,BB267} N4207 (???,???) [004007] ----------- IL_OFFSET void INLRT @ 0x52D[E-] REG NA N4209 (???,???) [004008] ----------- IL_OFFSET void INLRT @ 0x532[E-] REG NA N4211 ( 1, 1) [000692] ----------- t692 = LCL_VAR int V20 loc16 u:4 x9 REG x9 $2b3 N4213 ( 1, 1) [000696] ----------Z t696 = LCL_VAR int V144 tmp104 u:2 x8 REG x8 $2a6 /--* t692 int +--* t696 int N4215 ( 6, 9) [000697] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $a34 N4217 ( 1, 1) [000701] ----------z t701 = LCL_VAR byref V143 tmp103 u:2 x6 REG x6 $385 N4219 ( 1, 1) [000693] ----------- t693 = LCL_VAR int V20 loc16 u:4 x9 REG x9 $2b3 /--* t693 int N4221 ( 2, 3) [000698] -c-------U- t698 = * CAST long <- uint REG NA $ac0 N4223 ( 1, 2) [000699] -c--------- t699 = CNS_INT long 2 REG NA $20a /--* t698 long +--* t699 long N4225 ( 4, 6) [000700] -c--------- t700 = * BFIZ long REG NA /--* t701 byref +--* t700 long N4227 ( 6, 8) [000702] -c--------- t702 = * LEA(b+(i*1)+0) byref REG NA /--* t702 byref N4229 ( 8, 9) [002871] ---XGO----- t2871 = * IND int REG x11 N4231 ( 1, 2) [000705] -c--------- t705 = CNS_INT int 1 REG NA $c1 /--* t2871 int +--* t705 int N4233 ( 16, 21) [000706] ---XGO----- t706 = * ADD int REG x11 N4235 ( 1, 1) [000689] ----------Z t689 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 /--* t706 int +--* t689 int N4237 ( 21, 23) [000707] Nc-XGO-N-U- t707 = * NE int REG NA N4239 ( 1, 1) [000685] ----------Z t685 = LCL_VAR int V20 loc16 u:4 x9 REG x9 $2b3 N4241 ( 1, 2) [000686] -c--------- t686 = CNS_INT int 0 REG NA $c0 /--* t685 int +--* t686 int N4243 ( 6, 4) [000687] -c-----N--- t687 = * LT int REG NA $a94 /--* t707 int +--* t687 int N4245 ( 28, 28) [003748] Jc-XGO-N--- * AND void REG NA N4247 ( 30, 30) [000688] ---XGO----- * JTRUE void REG NA $VN.Void ------------ BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} N4251 (???,???) [004009] ----------- IL_OFFSET void INLRT @ 0x537[E-] REG NA N4253 (???,???) [004010] ----------- IL_OFFSET void INLRT @ 0x547[E-] REG NA N4255 ( 1, 1) [000710] ----------- t710 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t710 ref N4257 ( 3, 4) [002873] -c--------- t2873 = * LEA(b+56) byref REG NA /--* t2873 byref N4259 ( 4, 3) [001946] ---XG------ t1946 = * IND ref REG x11 /--* t1946 ref N4261 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 x11 REG x11 N4263 (???,???) [004011] ----------- IL_OFFSET void INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] REG NA N4265 ( 1, 1) [001948] ----------- t1948 = LCL_VAR ref V102 tmp62 u:1 x11 REG x11 N4267 ( 1, 2) [001949] -c--------- t1949 = CNS_INT ref null REG NA $VN.Null /--* t1948 ref +--* t1949 ref N4269 ( 3, 4) [001950] CEQ-------N--- * JCMP void REG NA ------------ BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} N4273 (???,???) [004012] ----------- IL_OFFSET void INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] REG NA N4275 ( 1, 1) [000709] ----------- t709 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t709 byref N4277 ( 3, 4) [002875] -c--------- t2875 = * LEA(b+8) byref REG NA /--* t2875 byref N4279 ( 4, 3) [001952] n---GO----- t1952 = * IND int REG x13 /--* t1952 int N4281 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 x13 REG x13 N4283 (???,???) [004013] ----------- IL_OFFSET void INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] REG NA N4285 ( 1, 1) [001955] ----------- t1955 = LCL_VAR ref V102 tmp62 u:1 x11 REG x11 /--* t1955 ref N4287 (???,???) [004170] -c--------- t4170 = * LEA(b+8) byref REG NA /--* t4170 byref N4289 ( 3, 3) [001956] ---X------- t1956 = * IND int REG x14 N4291 ( 1, 2) [001957] -c--------- t1957 = CNS_INT int 1 REG NA $c1 /--* t1956 int +--* t1957 int N4293 ( 8, 6) [001958] Nc-X---N-U- t1958 = * NE int REG NA N4295 ( 1, 1) [001963] ----------- t1963 = LCL_VAR int V103 tmp63 u:1 x13 REG x13 N4297 ( 1, 1) [001964] ----------- t1964 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1964 byref N4299 ( 3, 4) [002879] -c--------- t2879 = * LEA(b+24) byref REG NA /--* t2879 byref N4301 ( 4, 3) [002002] n---GO----- t2002 = * IND int REG x12 /--* t1963 int +--* t2002 int N4303 ( 9, 5) [001968] Nc--GO-N-U- t1968 = * GE int REG NA /--* t1958 int +--* t1968 int N4305 ( 18, 12) [003750] Jc-XGO-N--- * AND void REG NA N4307 ( 20, 14) [001959] ---XGO----- * JTRUE void REG NA ------------ BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} N4311 (???,???) [004014] ----------- IL_OFFSET void INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] REG NA N4313 (???,???) [004015] ----------- IL_OFFSET void INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] REG NA N4315 ( 1, 1) [002883] ----------- t2883 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4317 ( 1, 2) [002884] -c--------- t2884 = CNS_INT long 16 REG NA $200 /--* t2883 byref +--* t2884 long N4319 ( 3, 4) [002885] -----O----- t2885 = * ADD byref REG x14 $25c /--* t2885 byref N4321 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 x14 REG x14 N4323 (???,???) [004016] ----------- IL_OFFSET void INL37 @ ??? <- INLRT @ 0x547[E-] REG NA N4325 ( 1, 1) [001972] ----------- t1972 = LCL_VAR int V103 tmp63 u:1 x13 REG x13 N4327 ( 1, 1) [001977] ----------- t1977 = LCL_VAR byref V104 tmp64 u:1 x14 REG x14 $25c /--* t1977 byref N4329 ( 3, 4) [002888] -c--------- t2888 = * LEA(b+8) byref REG NA /--* t2888 byref N4331 ( 4, 3) [001978] n---GO----- t1978 = * IND int REG x12 /--* t1972 int +--* t1978 int N4333 ( 9, 11) [001979] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4335 ( 1, 1) [001976] ----------- t1976 = LCL_VAR byref V104 tmp64 u:1 x14 (last use) REG x14 $25c /--* t1976 byref N4337 ( 3, 2) [001983] n---GO----- t1983 = * IND byref REG x14 N4339 ( 1, 1) [001973] ----------- t1973 = LCL_VAR int V103 tmp63 u:1 x13 REG x13 /--* t1973 int N4341 ( 2, 3) [001980] -c-------U- t1980 = * CAST long <- uint REG NA N4343 ( 1, 2) [001981] -c--------- t1981 = CNS_INT long 1 REG NA $204 /--* t1980 long +--* t1981 long N4345 ( 4, 6) [001982] ----------- t1982 = * BFIZ long REG x12 /--* t1983 byref +--* t1982 long N4347 ( 8, 9) [001984] ----GO-N--- t1984 = * ADD byref REG x14 N4349 ( 1, 2) [001987] -c--------- t1987 = CNS_INT int 0 REG NA $c0 N4351 ( 1, 1) [001986] ----------- t1986 = LCL_VAR ref V102 tmp62 u:1 x11 REG x11 /--* t1986 ref N4353 (???,???) [004172] -c--------- t4172 = * LEA(b+8) byref REG NA /--* t4172 byref N4355 ( 3, 3) [002892] ---X------- t2892 = * IND int REG x12 /--* t1987 int +--* t2892 int N4357 ( 8, 12) [002893] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4359 ( 1, 1) [002890] ----------- t2890 = LCL_VAR ref V102 tmp62 u:1 x11 (last use) REG x11 /--* t2890 ref N4361 ( 1, 1) [002897] -c--------- t2897 = * LEA(b+12) byref REG NA /--* t2897 byref N4363 ( 5, 4) [002902] n---GO----- t2902 = * IND ushort REG x11 /--* t1984 byref +--* t2902 ushort N4365 (???,???) [004017] -A-XGO----- * STOREIND short REG NA N4367 (???,???) [004018] ----------- IL_OFFSET void INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] REG NA N4369 ( 1, 1) [001993] ----------- t1993 = LCL_VAR int V103 tmp63 u:1 x13 (last use) REG x13 N4371 ( 1, 2) [001994] -c--------- t1994 = CNS_INT int 1 REG NA $c1 /--* t1993 int +--* t1994 int N4373 ( 3, 4) [001995] ----------- t1995 = * ADD int REG x11 N4375 ( 1, 1) [001992] ----------- t1992 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1992 byref N4377 ( 3, 4) [002904] -c--------- t2904 = * LEA(b+8) byref REG NA /--* t2904 byref +--* t1995 int N4379 (???,???) [004019] -A--GO----- * STOREIND int REG NA ------------ BB267 [???..???) -> BB170 (always), preds={BB161} succs={BB170} N001 ( 1, 1) [004337] ----------z t4337 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004338] ----------z t4338 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004339] ----------z t4339 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB168 [547..548), preds={BB165} succs={BB169} N001 ( 1, 1) [004431] ----------Z t4431 = LCL_VAR long V36 loc32 x0 REG x0 N4383 (???,???) [004020] ----------- IL_OFFSET void INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] REG NA N4385 ( 1, 1) [001960] ----------- t1960 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1960 byref N4387 (???,???) [004265] ----------- t4265 = * PUTARG_REG byref REG x0 N4389 ( 1, 1) [001961] ----------- t1961 = LCL_VAR ref V102 tmp62 u:1 x11 (last use) REG x11 /--* t1961 ref N4391 (???,???) [004266] ----------- t4266 = * PUTARG_REG ref REG x1 N4393 ( 2, 8) [002905] H---------- t2905 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2905 long N4395 (???,???) [004267] ----------- t4267 = * PUTARG_REG long REG x11 /--* t4265 byref this in x0 +--* t4266 ref arg2 in x1 +--* t4267 long r2r cell in x11 N4397 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004432] ----------z t4432 = LCL_VAR long V36 loc32 x0 REG x0 ------------ BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} N4401 (???,???) [004021] ----------- IL_OFFSET void INLRT @ 0x553[E-] REG NA N4403 ( 1, 1) [000714] ----------z t714 = LCL_VAR int V20 loc16 u:4 x9 (last use) REG x9 $2b3 N4405 ( 1, 2) [000715] -c--------- t715 = CNS_INT int -1 REG NA $c4 /--* t714 int +--* t715 int N4407 ( 3, 4) [000716] ----------- t716 = * ADD int REG x9 $ab7 /--* t716 int N4409 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 NA REG NA N001 ( 1, 1) [004433] ----------z t4433 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004434] ----------z t4434 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004435] ----------z t4435 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB169,BB267} succs={BB245} N4413 (???,???) [004022] ----------- IL_OFFSET void INLRT @ 0x559[E-] REG NA N4415 ( 1, 1) [000669] ----------- t669 = LCL_VAR int V08 loc4 u:3 x2 (last use) REG x2 $2b5 N4417 ( 1, 2) [000670] -c--------- t670 = CNS_INT int -1 REG NA $c4 /--* t669 int +--* t670 int N4419 ( 3, 4) [000671] ----------- t671 = * ADD int REG x2 $ab9 /--* t671 int N4421 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 NA REG NA N001 ( 1, 1) [004436] ----------z t4436 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB171 [564..571) -> BB245 (cond), preds={BB258} succs={BB172,BB245} N4801 (???,???) [004023] ----------- IL_OFFSET void INLRT @ 0x564[E-] REG NA N4803 ( 1, 1) [000605] ----------z t605 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 N4805 ( 1, 2) [000606] -c--------- t606 = CNS_INT int 0 REG NA $c0 /--* t605 int +--* t606 int N4807 ( 6, 4) [000607] ----------- t607 = * NE int REG x11 $aba N4809 ( 1, 1) [000608] ----------z t608 = LCL_VAR int V21 loc17 u:2 x10 REG x10 $4c7 /--* t607 int +--* t608 int N4811 ( 8, 6) [000609] ----------- t609 = * OR int REG x11 $abb N4813 ( 1, 2) [000610] -c--------- t610 = CNS_INT int 0 REG NA $c0 N001 ( 1, 1) [004340] ----------Z t4340 = LCL_VAR bool V21 loc17 x10 REG x10 N001 ( 1, 1) [004341] ----------z t4341 = LCL_VAR int V14 loc10 x3 REG x3 /--* t609 int +--* t610 int N4815 ( 10, 9) [000611] CNE-------N--- * JCMP void REG NA ------------ BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} N4819 (???,???) [004024] ----------- IL_OFFSET void INLRT @ 0x571[E-] REG NA N4821 ( 1, 1) [000613] ----------z t613 = LCL_VAR int V07 loc3 u:3 x1 REG x1 $293 N4823 ( 1, 2) [000614] -c--------- t614 = CNS_INT int 0 REG NA $c0 /--* t613 int +--* t614 int N4825 ( 3, 4) [000615] J------N--- * LT void REG NA $abd N4827 ( 5, 6) [000616] ----------- * JTRUE void REG NA $VN.Void ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} N4831 (???,???) [004025] ----------- IL_OFFSET void INLRT @ 0x575[E-] REG NA N4833 ( 1, 1) [000625] ----------- t625 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d N4835 ( 1, 1) [000626] ----------- t626 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t625 int +--* t626 int N4837 ( 6, 3) [000627] -c-----N--- t627 = * GE int REG NA $abe N4839 ( 1, 1) [000629] ----------Z t629 = LCL_VAR long V36 loc32 u:3 x0 REG x0 $901 /--* t629 long N4841 ( 4, 3) [000630] ---XG------ t630 = * IND ubyte REG x11 N4843 ( 1, 2) [000631] -c--------- t631 = CNS_INT int 0 REG NA $c0 /--* t630 ubyte +--* t631 int N4845 ( 9, 6) [000632] -c-XG--N--- t632 = * EQ int REG NA /--* t627 int +--* t632 int N4847 ( 16, 10) [003752] Jc-XG--N--- * AND void REG NA N001 ( 1, 1) [004342] ----------z t4342 = LCL_VAR long V36 loc32 x0 REG x0 N4849 ( 18, 12) [000628] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} N4853 (???,???) [004026] ----------- IL_OFFSET void INLRT @ 0x57C[E-] REG NA N4855 (???,???) [004027] ----------- IL_OFFSET void INLRT @ 0x584[E-] REG NA N4857 ( 1, 1) [000618] ----------- t618 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t618 ref N4859 ( 3, 4) [002907] -c--------- t2907 = * LEA(b+48) byref REG NA /--* t2907 byref N4861 ( 4, 3) [002006] ---XG------ t2006 = * IND ref REG x11 /--* t2006 ref N4863 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 x11 REG x11 N4865 (???,???) [004028] ----------- IL_OFFSET void INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] REG NA N4867 ( 1, 1) [002008] ----------- t2008 = LCL_VAR ref V106 tmp66 u:1 x11 REG x11 N4869 ( 1, 2) [002009] -c--------- t2009 = CNS_INT ref null REG NA $VN.Null /--* t2008 ref +--* t2009 ref N4871 ( 3, 4) [002010] CEQ-------N--- * JCMP void REG NA ------------ BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} N4875 (???,???) [004029] ----------- IL_OFFSET void INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] REG NA N4877 ( 1, 1) [000617] ----------- t617 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t617 byref N4879 ( 3, 4) [002909] -c--------- t2909 = * LEA(b+8) byref REG NA /--* t2909 byref N4881 ( 4, 3) [002012] ---XG------ t2012 = * IND int REG x10 /--* t2012 int N4883 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 x10 REG x10 N4885 (???,???) [004030] ----------- IL_OFFSET void INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] REG NA N4887 ( 1, 1) [002015] ----------- t2015 = LCL_VAR ref V106 tmp66 u:1 x11 REG x11 /--* t2015 ref N4889 (???,???) [004174] -c--------- t4174 = * LEA(b+8) byref REG NA /--* t4174 byref N4891 ( 3, 3) [002016] ---X------- t2016 = * IND int REG x13 N4893 ( 1, 2) [002017] -c--------- t2017 = CNS_INT int 1 REG NA $c1 /--* t2016 int +--* t2017 int N4895 ( 8, 6) [002018] Nc-X---N-U- t2018 = * NE int REG NA N4897 ( 1, 1) [002023] ----------- t2023 = LCL_VAR int V107 tmp67 u:1 x10 REG x10 N4899 ( 1, 1) [002024] ----------- t2024 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2024 byref N4901 ( 3, 4) [002913] -c--------- t2913 = * LEA(b+24) byref REG NA /--* t2913 byref N4903 ( 4, 3) [002062] n---GO----- t2062 = * IND int REG x14 /--* t2023 int +--* t2062 int N4905 ( 9, 5) [002028] Nc--GO-N-U- t2028 = * GE int REG NA /--* t2018 int +--* t2028 int N4907 ( 18, 12) [003754] Jc-XGO-N--- * AND void REG NA N4909 ( 20, 14) [002019] ---XGO----- * JTRUE void REG NA ------------ BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} N4913 (???,???) [004031] ----------- IL_OFFSET void INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] REG NA N4915 (???,???) [004032] ----------- IL_OFFSET void INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] REG NA N4917 ( 1, 1) [002917] ----------- t2917 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4919 ( 1, 2) [002918] -c--------- t2918 = CNS_INT long 16 REG NA $200 /--* t2917 byref +--* t2918 long N4921 ( 3, 4) [002919] -----O----- t2919 = * ADD byref REG x13 $25c /--* t2919 byref N4923 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 x13 REG x13 N4925 (???,???) [004033] ----------- IL_OFFSET void INL40 @ ??? <- INLRT @ 0x584[E-] REG NA N4927 ( 1, 1) [002032] ----------- t2032 = LCL_VAR int V107 tmp67 u:1 x10 REG x10 N4929 ( 1, 1) [002037] ----------- t2037 = LCL_VAR byref V108 tmp68 u:1 x13 REG x13 $25c /--* t2037 byref N4931 ( 3, 4) [002922] -c--------- t2922 = * LEA(b+8) byref REG NA /--* t2922 byref N4933 ( 4, 3) [002038] n---GO----- t2038 = * IND int REG x14 /--* t2032 int +--* t2038 int N4935 ( 9, 11) [002039] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4937 ( 1, 1) [002036] ----------- t2036 = LCL_VAR byref V108 tmp68 u:1 x13 (last use) REG x13 $25c /--* t2036 byref N4939 ( 3, 2) [002043] n---GO----- t2043 = * IND byref REG x13 N4941 ( 1, 1) [002033] ----------- t2033 = LCL_VAR int V107 tmp67 u:1 x10 REG x10 /--* t2033 int N4943 ( 2, 3) [002040] -c-------U- t2040 = * CAST long <- uint REG NA N4945 ( 1, 2) [002041] -c--------- t2041 = CNS_INT long 1 REG NA $204 /--* t2040 long +--* t2041 long N4947 ( 4, 6) [002042] ----------- t2042 = * BFIZ long REG x14 /--* t2043 byref +--* t2042 long N4949 ( 8, 9) [002044] ----GO-N--- t2044 = * ADD byref REG x13 N4951 ( 1, 2) [002047] -c--------- t2047 = CNS_INT int 0 REG NA $c0 N4953 ( 1, 1) [002046] ----------- t2046 = LCL_VAR ref V106 tmp66 u:1 x11 REG x11 /--* t2046 ref N4955 (???,???) [004176] -c--------- t4176 = * LEA(b+8) byref REG NA /--* t4176 byref N4957 ( 3, 3) [002926] ---X------- t2926 = * IND int REG x14 /--* t2047 int +--* t2926 int N4959 ( 8, 12) [002927] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4961 ( 1, 1) [002924] ----------- t2924 = LCL_VAR ref V106 tmp66 u:1 x11 (last use) REG x11 /--* t2924 ref N4963 ( 1, 1) [002931] -c--------- t2931 = * LEA(b+12) byref REG NA /--* t2931 byref N4965 ( 5, 4) [002936] n---GO----- t2936 = * IND ushort REG x11 /--* t2044 byref +--* t2936 ushort N4967 (???,???) [004034] -A-XGO----- * STOREIND short REG NA N4969 (???,???) [004035] ----------- IL_OFFSET void INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] REG NA N4971 ( 1, 1) [002053] ----------- t2053 = LCL_VAR int V107 tmp67 u:1 x10 (last use) REG x10 N4973 ( 1, 2) [002054] -c--------- t2054 = CNS_INT int 1 REG NA $c1 /--* t2053 int +--* t2054 int N4975 ( 3, 4) [002055] ----------- t2055 = * ADD int REG x11 N4977 ( 1, 1) [002052] ----------- t2052 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2052 byref N4979 ( 3, 4) [002938] -c--------- t2938 = * LEA(b+8) byref REG NA /--* t2938 byref +--* t2055 int N4981 (???,???) [004036] -A--GO----- * STOREIND int REG NA ------------ BB179 [584..585), preds={BB176} succs={BB180} N001 ( 1, 1) [004437] ----------Z t4437 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004438] ----------Z t4438 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004439] ----------Z t4439 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004440] ----------Z t4440 = LCL_VAR int V144 tmp104 x8 REG x8 N4985 (???,???) [004037] ----------- IL_OFFSET void INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] REG NA N4987 ( 1, 1) [002020] ----------- t2020 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2020 byref N4989 (???,???) [004268] ----------- t4268 = * PUTARG_REG byref REG x0 N4991 ( 1, 1) [002021] ----------- t2021 = LCL_VAR ref V106 tmp66 u:1 x11 (last use) REG x11 /--* t2021 ref N4993 (???,???) [004269] ----------- t4269 = * PUTARG_REG ref REG x1 N4995 ( 2, 8) [002939] H---------- t2939 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2939 long N4997 (???,???) [004270] ----------- t4270 = * PUTARG_REG long REG x11 /--* t4268 byref this in x0 +--* t4269 ref arg2 in x1 +--* t4270 long r2r cell in x11 N4999 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004441] ----------z t4441 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004442] ----------z t4442 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004443] ----------z t4443 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004444] ----------z t4444 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} N5003 (???,???) [004038] ----------- IL_OFFSET void INLRT @ 0x590[E-] REG NA N5005 ( 1, 2) [002940] ----------- t2940 = CNS_INT int 1 REG x10 $c1 /--* t2940 int N5007 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 x11 REG x11 N001 ( 1, 1) [004445] ----------Z t4445 = LCL_VAR bool V21 loc17 x11 REG x11 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} N2353 (???,???) [004039] ----------- IL_OFFSET void INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] REG NA N2355 ( 1, 1) [002068] ----------- t2068 = LCL_VAR ref V110 tmp70 u:1 x11 REG x11 N2357 ( 1, 2) [002069] -c--------- t2069 = CNS_INT ref null REG NA $VN.Null N001 ( 1, 1) [004343] ----------z t4343 = LCL_VAR int V14 loc10 x3 REG x3 /--* t2068 ref +--* t2069 ref N2359 ( 3, 4) [002070] CEQ-------N--- * JCMP void REG NA ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} N2363 (???,???) [004040] ----------- IL_OFFSET void INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] REG NA N2365 ( 1, 1) [000585] ----------- t585 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t585 byref N2367 ( 3, 4) [002942] -c--------- t2942 = * LEA(b+8) byref REG NA /--* t2942 byref N2369 ( 4, 3) [002072] ---XG------ t2072 = * IND int REG x13 /--* t2072 int N2371 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 x13 REG x13 N2373 (???,???) [004041] ----------- IL_OFFSET void INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] REG NA N2375 ( 1, 1) [002075] ----------- t2075 = LCL_VAR ref V110 tmp70 u:1 x11 REG x11 /--* t2075 ref N2377 (???,???) [004178] -c--------- t4178 = * LEA(b+8) byref REG NA /--* t4178 byref N2379 ( 3, 3) [002076] ---X------- t2076 = * IND int REG x14 N2381 ( 1, 2) [002077] -c--------- t2077 = CNS_INT int 1 REG NA $c1 /--* t2076 int +--* t2077 int N2383 ( 8, 6) [002078] Nc-X---N-U- t2078 = * NE int REG NA N2385 ( 1, 1) [002083] ----------- t2083 = LCL_VAR int V111 tmp71 u:1 x13 REG x13 N2387 ( 1, 1) [002084] ----------- t2084 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2084 byref N2389 ( 3, 4) [002946] -c--------- t2946 = * LEA(b+24) byref REG NA /--* t2946 byref N2391 ( 4, 3) [002122] n---GO----- t2122 = * IND int REG x12 /--* t2083 int +--* t2122 int N2393 ( 9, 5) [002088] Nc--GO-N-U- t2088 = * GE int REG NA /--* t2078 int +--* t2088 int N2395 ( 18, 12) [003756] Jc-XGO-N--- * AND void REG NA N2397 ( 20, 14) [002079] ---XGO----- * JTRUE void REG NA ------------ BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} N2401 (???,???) [004042] ----------- IL_OFFSET void INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] REG NA N2403 (???,???) [004043] ----------- IL_OFFSET void INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] REG NA N2405 ( 1, 1) [002950] ----------- t2950 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N2407 ( 1, 2) [002951] -c--------- t2951 = CNS_INT long 16 REG NA $200 /--* t2950 byref +--* t2951 long N2409 ( 3, 4) [002952] -----O----- t2952 = * ADD byref REG x14 $25c /--* t2952 byref N2411 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 x14 REG x14 N2413 (???,???) [004044] ----------- IL_OFFSET void INL43 @ ??? <- INLRT @ 0x598[E-] REG NA N2415 ( 1, 1) [002092] ----------- t2092 = LCL_VAR int V111 tmp71 u:1 x13 REG x13 N2417 ( 1, 1) [002097] ----------- t2097 = LCL_VAR byref V112 tmp72 u:1 x14 REG x14 $25c /--* t2097 byref N2419 ( 3, 4) [002955] -c--------- t2955 = * LEA(b+8) byref REG NA /--* t2955 byref N2421 ( 4, 3) [002098] n---GO----- t2098 = * IND int REG x12 /--* t2092 int +--* t2098 int N2423 ( 9, 11) [002099] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2425 ( 1, 1) [002096] ----------- t2096 = LCL_VAR byref V112 tmp72 u:1 x14 (last use) REG x14 $25c /--* t2096 byref N2427 ( 3, 2) [002103] n---GO----- t2103 = * IND byref REG x14 N2429 ( 1, 1) [002093] ----------- t2093 = LCL_VAR int V111 tmp71 u:1 x13 REG x13 /--* t2093 int N2431 ( 2, 3) [002100] -c-------U- t2100 = * CAST long <- uint REG NA N2433 ( 1, 2) [002101] -c--------- t2101 = CNS_INT long 1 REG NA $204 /--* t2100 long +--* t2101 long N2435 ( 4, 6) [002102] ----------- t2102 = * BFIZ long REG x12 /--* t2103 byref +--* t2102 long N2437 ( 8, 9) [002104] ----GO-N--- t2104 = * ADD byref REG x14 N2439 ( 1, 2) [002107] -c--------- t2107 = CNS_INT int 0 REG NA $c0 N2441 ( 1, 1) [002106] ----------- t2106 = LCL_VAR ref V110 tmp70 u:1 x11 REG x11 /--* t2106 ref N2443 (???,???) [004180] -c--------- t4180 = * LEA(b+8) byref REG NA /--* t4180 byref N2445 ( 3, 3) [002959] ---X------- t2959 = * IND int REG x12 /--* t2107 int +--* t2959 int N2447 ( 8, 12) [002960] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2449 ( 1, 1) [002957] ----------- t2957 = LCL_VAR ref V110 tmp70 u:1 x11 (last use) REG x11 /--* t2957 ref N2451 ( 1, 1) [002964] -c--------- t2964 = * LEA(b+12) byref REG NA /--* t2964 byref N2453 ( 5, 4) [002969] n---GO----- t2969 = * IND ushort REG x11 /--* t2104 byref +--* t2969 ushort N2455 (???,???) [004045] -A-XGO----- * STOREIND short REG NA N2457 (???,???) [004046] ----------- IL_OFFSET void INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] REG NA N2459 ( 1, 1) [002113] ----------- t2113 = LCL_VAR int V111 tmp71 u:1 x13 (last use) REG x13 N2461 ( 1, 2) [002114] -c--------- t2114 = CNS_INT int 1 REG NA $c1 /--* t2113 int +--* t2114 int N2463 ( 3, 4) [002115] ----------- t2115 = * ADD int REG x11 N2465 ( 1, 1) [002112] ----------- t2112 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2112 byref N2467 ( 3, 4) [002971] -c--------- t2971 = * LEA(b+8) byref REG NA /--* t2971 byref +--* t2115 int N2469 (???,???) [004047] -A--GO----- * STOREIND int REG NA ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} N001 ( 1, 1) [004446] ----------Z t4446 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004447] ----------Z t4447 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004448] ----------Z t4448 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004449] ----------Z t4449 = LCL_VAR int V144 tmp104 x8 REG x8 N2473 (???,???) [004048] ----------- IL_OFFSET void INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] REG NA N2475 ( 1, 1) [002080] ----------- t2080 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2080 byref N2477 (???,???) [004271] ----------- t4271 = * PUTARG_REG byref REG x0 N2479 ( 1, 1) [002081] ----------- t2081 = LCL_VAR ref V110 tmp70 u:1 x11 (last use) REG x11 /--* t2081 ref N2481 (???,???) [004272] ----------- t4272 = * PUTARG_REG ref REG x1 N2483 ( 2, 8) [002972] H---------- t2972 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2972 long N2485 (???,???) [004273] ----------- t4273 = * PUTARG_REG long REG x11 /--* t4271 byref this in x0 +--* t4272 ref arg2 in x1 +--* t4273 long r2r cell in x11 N2487 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004450] ----------z t4450 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004451] ----------z t4451 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004452] ----------z t4452 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004453] ----------z t4453 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB257} succs={BB187,BB245} N4425 (???,???) [004049] ----------- IL_OFFSET void INLRT @ 0x5A9[E-] REG NA N4427 ( 1, 1) [000635] ----------- t635 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t635 ref N4429 ( 3, 4) [002974] -c--------- t2974 = * LEA(b+128) byref REG NA /--* t2974 byref N4431 ( 4, 3) [002126] ---XG------ t2126 = * IND ref REG x11 /--* t2126 ref N4433 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 x11 REG x11 N4435 (???,???) [004050] ----------- IL_OFFSET void INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] REG NA N4437 ( 1, 1) [002128] ----------- t2128 = LCL_VAR ref V114 tmp74 u:1 x11 REG x11 N4439 ( 1, 2) [002129] -c--------- t2129 = CNS_INT ref null REG NA $VN.Null N001 ( 1, 1) [004344] ----------z t4344 = LCL_VAR int V14 loc10 x3 REG x3 /--* t2128 ref +--* t2129 ref N4441 ( 3, 4) [002130] CEQ-------N--- * JCMP void REG NA ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} N4445 (???,???) [004051] ----------- IL_OFFSET void INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] REG NA N4447 ( 1, 1) [000634] ----------- t634 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t634 byref N4449 ( 3, 4) [002976] -c--------- t2976 = * LEA(b+8) byref REG NA /--* t2976 byref N4451 ( 4, 3) [002132] ---XG------ t2132 = * IND int REG x13 /--* t2132 int N4453 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 x13 REG x13 N4455 (???,???) [004052] ----------- IL_OFFSET void INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] REG NA N4457 ( 1, 1) [002135] ----------- t2135 = LCL_VAR ref V114 tmp74 u:1 x11 REG x11 /--* t2135 ref N4459 (???,???) [004182] -c--------- t4182 = * LEA(b+8) byref REG NA /--* t4182 byref N4461 ( 3, 3) [002136] ---X------- t2136 = * IND int REG x14 N4463 ( 1, 2) [002137] -c--------- t2137 = CNS_INT int 1 REG NA $c1 /--* t2136 int +--* t2137 int N4465 ( 8, 6) [002138] Nc-X---N-U- t2138 = * NE int REG NA N4467 ( 1, 1) [002143] ----------- t2143 = LCL_VAR int V115 tmp75 u:1 x13 REG x13 N4469 ( 1, 1) [002144] ----------- t2144 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2144 byref N4471 ( 3, 4) [002980] -c--------- t2980 = * LEA(b+24) byref REG NA /--* t2980 byref N4473 ( 4, 3) [002182] n---GO----- t2182 = * IND int REG x12 /--* t2143 int +--* t2182 int N4475 ( 9, 5) [002148] Nc--GO-N-U- t2148 = * GE int REG NA /--* t2138 int +--* t2148 int N4477 ( 18, 12) [003758] Jc-XGO-N--- * AND void REG NA N4479 ( 20, 14) [002139] ---XGO----- * JTRUE void REG NA ------------ BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} N4483 (???,???) [004053] ----------- IL_OFFSET void INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] REG NA N4485 (???,???) [004054] ----------- IL_OFFSET void INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] REG NA N4487 ( 1, 1) [002984] ----------- t2984 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4489 ( 1, 2) [002985] -c--------- t2985 = CNS_INT long 16 REG NA $200 /--* t2984 byref +--* t2985 long N4491 ( 3, 4) [002986] -----O----- t2986 = * ADD byref REG x14 $25c /--* t2986 byref N4493 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 x14 REG x14 N4495 (???,???) [004055] ----------- IL_OFFSET void INL46 @ ??? <- INLRT @ 0x5A9[E-] REG NA N4497 ( 1, 1) [002152] ----------- t2152 = LCL_VAR int V115 tmp75 u:1 x13 REG x13 N4499 ( 1, 1) [002157] ----------- t2157 = LCL_VAR byref V116 tmp76 u:1 x14 REG x14 $25c /--* t2157 byref N4501 ( 3, 4) [002989] -c--------- t2989 = * LEA(b+8) byref REG NA /--* t2989 byref N4503 ( 4, 3) [002158] n---GO----- t2158 = * IND int REG x12 /--* t2152 int +--* t2158 int N4505 ( 9, 11) [002159] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4507 ( 1, 1) [002156] ----------- t2156 = LCL_VAR byref V116 tmp76 u:1 x14 (last use) REG x14 $25c /--* t2156 byref N4509 ( 3, 2) [002163] n---GO----- t2163 = * IND byref REG x14 N4511 ( 1, 1) [002153] ----------- t2153 = LCL_VAR int V115 tmp75 u:1 x13 REG x13 /--* t2153 int N4513 ( 2, 3) [002160] -c-------U- t2160 = * CAST long <- uint REG NA N4515 ( 1, 2) [002161] -c--------- t2161 = CNS_INT long 1 REG NA $204 /--* t2160 long +--* t2161 long N4517 ( 4, 6) [002162] ----------- t2162 = * BFIZ long REG x12 /--* t2163 byref +--* t2162 long N4519 ( 8, 9) [002164] ----GO-N--- t2164 = * ADD byref REG x14 N4521 ( 1, 2) [002167] -c--------- t2167 = CNS_INT int 0 REG NA $c0 N4523 ( 1, 1) [002166] ----------- t2166 = LCL_VAR ref V114 tmp74 u:1 x11 REG x11 /--* t2166 ref N4525 (???,???) [004184] -c--------- t4184 = * LEA(b+8) byref REG NA /--* t4184 byref N4527 ( 3, 3) [002993] ---X------- t2993 = * IND int REG x12 /--* t2167 int +--* t2993 int N4529 ( 8, 12) [002994] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4531 ( 1, 1) [002991] ----------- t2991 = LCL_VAR ref V114 tmp74 u:1 x11 (last use) REG x11 /--* t2991 ref N4533 ( 1, 1) [002998] -c--------- t2998 = * LEA(b+12) byref REG NA /--* t2998 byref N4535 ( 5, 4) [003003] n---GO----- t3003 = * IND ushort REG x11 /--* t2164 byref +--* t3003 ushort N4537 (???,???) [004056] -A-XGO----- * STOREIND short REG NA N4539 (???,???) [004057] ----------- IL_OFFSET void INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] REG NA N4541 ( 1, 1) [002173] ----------- t2173 = LCL_VAR int V115 tmp75 u:1 x13 (last use) REG x13 N4543 ( 1, 2) [002174] -c--------- t2174 = CNS_INT int 1 REG NA $c1 /--* t2173 int +--* t2174 int N4545 ( 3, 4) [002175] ----------- t2175 = * ADD int REG x11 N4547 ( 1, 1) [002172] ----------- t2172 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2172 byref N4549 ( 3, 4) [003005] -c--------- t3005 = * LEA(b+8) byref REG NA /--* t3005 byref +--* t2175 int N4551 (???,???) [004058] -A--GO----- * STOREIND int REG NA ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} N001 ( 1, 1) [004454] ----------Z t4454 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004455] ----------Z t4455 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004456] ----------Z t4456 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004457] ----------Z t4457 = LCL_VAR int V144 tmp104 x8 REG x8 N4555 (???,???) [004059] ----------- IL_OFFSET void INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] REG NA N4557 ( 1, 1) [002140] ----------- t2140 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2140 byref N4559 (???,???) [004274] ----------- t4274 = * PUTARG_REG byref REG x0 N4561 ( 1, 1) [002141] ----------- t2141 = LCL_VAR ref V114 tmp74 u:1 x11 (last use) REG x11 /--* t2141 ref N4563 (???,???) [004275] ----------- t4275 = * PUTARG_REG ref REG x1 N4565 ( 2, 8) [003006] H---------- t3006 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t3006 long N4567 (???,???) [004276] ----------- t4276 = * PUTARG_REG long REG x11 /--* t4274 byref this in x0 +--* t4275 ref arg2 in x1 +--* t4276 long r2r cell in x11 N4569 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004458] ----------z t4458 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004459] ----------z t4459 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004460] ----------z t4460 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004461] ----------z t4461 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} N4623 (???,???) [004060] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] REG NA N4625 ( 1, 1) [000805] ----------- t805 = LCL_VAR int V16 loc12 u:13 x4 (last use) REG x4 $b04 /--* t805 int N4627 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 x4 REG x4 N4629 (???,???) [004061] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] REG NA N4631 ( 1, 1) [000806] ----------- t806 = LCL_VAR int V59 tmp19 u:1 x4 (last use) REG x4 $b04 N4633 ( 1, 2) [000807] -c--------- t807 = CNS_INT int 1 REG NA $c1 /--* t806 int +--* t807 int N4635 ( 3, 4) [000808] ----------- t808 = * ADD int REG x4 $bad /--* t808 int N4637 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 NA REG NA N4639 ( 1, 1) [003629] ----------- t3629 = LCL_VAR int V172 cse1 x14 (last use) REG x14 /--* t3629 int N4641 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 x14 REG x14 N4643 (???,???) [004062] ----------- IL_OFFSET void INL48 @ 0x000[E-] <- INLRT @ ??? REG NA N4645 ( 1, 1) [000803] ----------- t803 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t803 byref N4647 ( 3, 4) [003008] -c--------- t3008 = * LEA(b+8) byref REG NA /--* t3008 byref N4649 ( 4, 3) [002186] ---XG------ t2186 = * IND int REG x11 /--* t2186 int N4651 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 x11 REG x11 N4653 (???,???) [004063] ----------- IL_OFFSET void INL48 @ 0x007[E-] <- INLRT @ ??? REG NA N4655 ( 1, 1) [002189] ----------- t2189 = LCL_VAR int V118 tmp78 u:1 x11 REG x11 N4657 ( 1, 1) [002190] ----------- t2190 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2190 byref N4659 ( 3, 4) [003012] -c--------- t3012 = * LEA(b+24) byref REG NA /--* t3012 byref N4661 ( 4, 3) [002228] n---GO----- t2228 = * IND int REG x12 /--* t2189 int +--* t2228 int N4663 ( 6, 5) [002194] N---GO-N-U- * GE void REG NA N4665 ( 8, 7) [002195] ----GO----- * JTRUE void REG NA $845 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} N4669 (???,???) [004064] ----------- IL_OFFSET void INL48 @ 0x015[E-] <- INLRT @ ??? REG NA N4671 ( 1, 1) [003016] ----------- t3016 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4673 ( 1, 2) [003017] -c--------- t3017 = CNS_INT long 16 REG NA $200 /--* t3016 byref +--* t3017 long N4675 ( 3, 4) [003018] -----O----- t3018 = * ADD byref REG x12 $25c /--* t3018 byref N4677 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 x12 REG x12 N4679 ( 1, 1) [002201] ----------- t2201 = LCL_VAR int V118 tmp78 u:1 x11 REG x11 N4681 ( 1, 1) [002206] ----------- t2206 = LCL_VAR byref V120 tmp80 u:1 x12 REG x12 $25c /--* t2206 byref N4683 ( 3, 4) [003021] -c--------- t3021 = * LEA(b+8) byref REG NA /--* t3021 byref N4685 ( 4, 3) [002207] n---GO----- t2207 = * IND int REG x15 /--* t2201 int +--* t2207 int N4687 ( 9, 11) [002208] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4689 ( 1, 1) [002205] ----------- t2205 = LCL_VAR byref V120 tmp80 u:1 x12 (last use) REG x12 $25c /--* t2205 byref N4691 ( 3, 2) [002212] n---GO----- t2212 = * IND byref REG x12 N4693 ( 1, 1) [002202] ----------- t2202 = LCL_VAR int V118 tmp78 u:1 x11 REG x11 /--* t2202 int N4695 ( 2, 3) [002209] -c-------U- t2209 = * CAST long <- uint REG NA N4697 ( 1, 2) [002210] -c--------- t2210 = CNS_INT long 1 REG NA $204 /--* t2209 long +--* t2210 long N4699 ( 4, 6) [002211] -c--------- t2211 = * BFIZ long REG NA /--* t2212 byref +--* t2211 long N4701 ( 8, 9) [002213] -c--------- t2213 = * LEA(b+(i*1)+0) byref REG NA N4703 ( 1, 1) [002215] ----------- t2215 = LCL_VAR int V119 tmp79 u:1 x14 (last use) REG x14 /--* t2213 byref +--* t2215 int N4705 (???,???) [004065] -A-XGO----- * STOREIND short REG NA N4707 (???,???) [004066] ----------- IL_OFFSET void INL48 @ 0x023[E-] <- INLRT @ ??? REG NA N4709 ( 1, 1) [002219] ----------- t2219 = LCL_VAR int V118 tmp78 u:1 x11 (last use) REG x11 N4711 ( 1, 2) [002220] -c--------- t2220 = CNS_INT int 1 REG NA $c1 /--* t2219 int +--* t2220 int N4713 ( 3, 4) [002221] ----------- t2221 = * ADD int REG x14 N4715 ( 1, 1) [002218] ----------- t2218 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2218 byref N4717 ( 3, 4) [003024] -c--------- t3024 = * LEA(b+8) byref REG NA /--* t3024 byref +--* t2221 int N4719 (???,???) [004067] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004462] ----------z t4462 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB193 [000..000), preds={BB191} succs={BB194} N001 ( 1, 1) [004463] ----------Z t4463 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004464] ----------Z t4464 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004465] ----------Z t4465 = LCL_VAR int V144 tmp104 x8 REG x8 N4723 (???,???) [004068] ----------- IL_OFFSET void INL48 @ 0x02D[E-] <- INLRT @ ??? REG NA N4725 ( 1, 1) [002196] ----------- t2196 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2196 byref N4727 (???,???) [004277] ----------- t4277 = * PUTARG_REG byref REG x0 N4729 ( 1, 1) [002197] ----------- t2197 = LCL_VAR int V119 tmp79 u:1 x14 (last use) REG x14 /--* t2197 int N4731 (???,???) [004278] ----------- t4278 = * PUTARG_REG int REG x1 N4733 ( 2, 8) [003025] H---------- t3025 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3025 long N4735 (???,???) [004279] ----------- t4279 = * PUTARG_REG long REG x11 /--* t4277 byref this in x0 +--* t4278 int arg2 in x1 +--* t4279 long r2r cell in x11 N4737 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004466] ----------z t4466 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004467] ----------z t4467 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004468] ----------z t4468 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004469] ----------z t4469 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB192,BB193,BB257(2)} succs={BB195,BB197} N4573 (???,???) [004069] ----------- IL_OFFSET void INLRT @ 0x5CE[E-] REG NA N4575 ( 1, 1) [000751] ----------z t751 = LCL_VAR int V16 loc12 u:13 x4 REG x4 $b04 N4577 ( 1, 1) [003699] ----------- t3699 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t751 int +--* t3699 int N4579 ( 3, 3) [000756] J------N--- * GE void REG NA $ba4 N4581 ( 5, 5) [000757] ----------- * JTRUE void REG NA $VN.Void ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} N4585 (???,???) [004070] ----------- IL_OFFSET void INLRT @ 0x5D9[E-] REG NA N4587 ( 1, 1) [000781] ----------- t781 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N4589 ( 1, 1) [000782] ----------- t782 = LCL_VAR int V16 loc12 u:13 x4 REG x4 $b04 /--* t782 int N4591 ( 2, 3) [000783] -c--------- t783 = * CAST long <- int REG NA $aca N4593 ( 1, 2) [000785] -c--------- t785 = CNS_INT long 1 REG NA $204 /--* t783 long +--* t785 long N4595 ( 4, 6) [000786] -c--------- t786 = * BFIZ long REG NA /--* t781 long +--* t786 long N4597 ( 6, 8) [000787] -c--------- t787 = * LEA(b+(i*1)+0) long REG NA /--* t787 long N4599 ( 9, 10) [000788] ---XG------ t788 = * IND ushort REG x14 /--* t788 ushort N4601 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 x14 REG x14 N4603 ( 1, 1) [003632] ----------- t3632 = LCL_VAR int V172 cse1 x14 REG x14 N4605 ( 1, 2) [000789] -c--------- t789 = CNS_INT int 0 REG NA $c0 /--* t3632 int +--* t789 int N4607 ( 12, 14) [000790] CEQ---XG--N--- * JCMP void REG NA ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} N4611 (???,???) [004071] ----------- IL_OFFSET void INLRT @ 0x5E4[E-] REG NA N4613 ( 1, 1) [003634] ----------- t3634 = LCL_VAR int V172 cse1 x14 REG x14 N4615 ( 1, 1) [000800] ----------Z t800 = LCL_VAR int V18 loc14 u:1 x13 REG x13 /--* t3634 int +--* t800 int N4617 ( 3, 3) [000801] N---G--N-U- * NE void REG NA N4619 ( 5, 5) [000802] ----G------ * JTRUE void REG NA $bec ------------ BB197 [5F1..5FF) -> BB268 (cond), preds={BB194,BB196} succs={BB198,BB268} N4741 (???,???) [004072] ----------- IL_OFFSET void INLRT @ 0x5F1[E-] REG NA N4743 ( 1, 1) [000758] ----------- t758 = LCL_VAR int V16 loc12 u:13 x4 REG x4 $b04 N4745 ( 1, 1) [003700] ----------- t3700 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t758 int +--* t3700 int N4747 ( 3, 3) [000763] J------N--- * GE void REG NA $ba4 N4749 ( 5, 5) [000764] ----------- * JTRUE void REG NA $VN.Void ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} N4753 (???,???) [004073] ----------- IL_OFFSET void INLRT @ 0x5FF[E-] REG NA N4755 ( 1, 1) [000765] ----------- t765 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N4757 ( 1, 1) [000766] ----------- t766 = LCL_VAR int V16 loc12 u:13 x4 REG x4 $b04 /--* t766 int N4759 ( 2, 3) [000767] -c--------- t767 = * CAST long <- int REG NA $aca N4761 ( 1, 2) [000769] -c--------- t769 = CNS_INT long 1 REG NA $204 /--* t767 long +--* t769 long N4763 ( 4, 6) [000770] -c--------- t770 = * BFIZ long REG NA /--* t765 long +--* t770 long N4765 ( 6, 8) [000771] -c--------- t771 = * LEA(b+(i*1)+0) long REG NA /--* t771 long N4767 ( 9, 10) [000772] ---XG------ t772 = * IND ushort REG x14 /--* t772 ushort N4769 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 x14 REG x14 N4771 ( 1, 1) [003637] ----------- t3637 = LCL_VAR int V172 cse1 x14 (last use) REG x14 N4773 ( 1, 2) [000773] -c--------- t773 = CNS_INT int 0 REG NA $c0 N001 ( 1, 1) [004347] ----------Z t4347 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004348] ----------z t4348 = LCL_VAR int V14 loc10 x3 REG x3 /--* t3637 int +--* t773 int N4775 ( 12, 14) [000774] CEQ---XG--N--- * JCMP void REG NA ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} N4779 (???,???) [004074] ----------- IL_OFFSET void INLRT @ 0x60D[E-] REG NA N4781 ( 1, 1) [000776] ----------z t776 = LCL_VAR int V16 loc12 u:13 x4 (last use) REG x4 $b04 N4783 ( 1, 2) [000777] -c--------- t777 = CNS_INT int 1 REG NA $c1 /--* t776 int +--* t777 int N4785 ( 3, 4) [000778] ----------- t778 = * ADD int REG x4 $bad /--* t778 int N4787 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 NA REG NA ------------ BB268 [???..???) -> BB245 (always), preds={BB197} succs={BB245} N001 ( 1, 1) [004345] ----------Z t4345 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004346] ----------z t4346 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} N2491 (???,???) [004075] ----------- IL_OFFSET void INLRT @ 0x618[E-] REG NA N2493 ( 1, 1) [000283] ----------- t283 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2495 ( 1, 1) [003701] ----------- t3701 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t283 int +--* t3701 int N2497 ( 6, 3) [000288] -c-----N--- t288 = * GE int REG NA $94d N2499 ( 1, 1) [000290] ----------- t290 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2501 ( 1, 1) [000291] ----------z t291 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 /--* t291 int N2503 ( 2, 3) [000292] -c--------- t292 = * CAST long <- int REG NA $3e5 N2505 ( 1, 2) [000294] -c--------- t294 = CNS_INT long 1 REG NA $204 /--* t292 long +--* t294 long N2507 ( 4, 6) [000295] -c--------- t295 = * BFIZ long REG NA /--* t290 long +--* t295 long N2509 ( 6, 8) [000296] -c--------- t296 = * LEA(b+(i*1)+0) long REG NA /--* t296 long N2511 ( 9, 10) [000297] ---XG------ t297 = * IND ushort REG x13 /--* t297 ushort N2513 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 x13 REG x13 N2515 ( 1, 1) [003665] ----------- t3665 = LCL_VAR int V176 cse5 x13 REG x13 N2517 ( 1, 2) [000298] -c--------- t298 = CNS_INT int 0 REG NA $c0 /--* t3665 int +--* t298 int N2519 ( 15, 14) [000299] -c-XG--N--- t299 = * EQ int REG NA /--* t288 int +--* t299 int N2521 ( 22, 18) [003760] Jc-XG--N--- * AND void REG NA N001 ( 1, 1) [004349] ----------Z t4349 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004350] ----------z t4350 = LCL_VAR int V14 loc10 x3 REG x3 N2523 ( 24, 20) [000289] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} N2527 (???,???) [004076] ----------- IL_OFFSET void INLRT @ 0x626[E-] REG NA N2529 (???,???) [004077] ----------- IL_OFFSET void INLRT @ 0x634[E-] REG NA N2531 ( 1, 1) [000303] ----------z t303 = LCL_VAR int V16 loc12 u:5 x4 (last use) REG x4 $898 /--* t303 int N2533 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 x4 REG x4 N2535 (???,???) [004078] ----------- IL_OFFSET void INLRT @ 0x634[E-] REG NA N2537 ( 1, 1) [000304] ----------- t304 = LCL_VAR int V51 tmp11 u:1 x4 (last use) REG x4 $898 N2539 ( 1, 2) [000305] -c--------- t305 = CNS_INT int 1 REG NA $c1 /--* t304 int +--* t305 int N2541 ( 3, 4) [000306] ----------- t306 = * ADD int REG x4 $952 /--* t306 int N2543 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 NA REG NA N2545 ( 1, 1) [003667] ----------- t3667 = LCL_VAR int V176 cse5 x13 (last use) REG x13 /--* t3667 int N2547 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 x13 REG x13 N2549 (???,???) [004079] ----------- IL_OFFSET void INL53 @ 0x000[E-] <- INLRT @ ??? REG NA N2551 ( 1, 1) [000301] ----------- t301 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t301 byref N2553 ( 3, 4) [003027] -c--------- t3027 = * LEA(b+8) byref REG NA /--* t3027 byref N2555 ( 4, 3) [002244] ---XG------ t2244 = * IND int REG x11 /--* t2244 int N2557 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 x11 REG x11 N2559 (???,???) [004080] ----------- IL_OFFSET void INL53 @ 0x007[E-] <- INLRT @ ??? REG NA N2561 ( 1, 1) [002247] ----------- t2247 = LCL_VAR int V122 tmp82 u:1 x11 REG x11 N2563 ( 1, 1) [002248] ----------- t2248 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2248 byref N2565 ( 3, 4) [003031] -c--------- t3031 = * LEA(b+24) byref REG NA /--* t3031 byref N2567 ( 4, 3) [002286] n---GO----- t2286 = * IND int REG x14 /--* t2247 int +--* t2286 int N2569 ( 6, 5) [002252] N---GO-N-U- * GE void REG NA N2571 ( 8, 7) [002253] ----GO----- * JTRUE void REG NA $845 ------------ BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} N2575 (???,???) [004081] ----------- IL_OFFSET void INL53 @ 0x015[E-] <- INLRT @ ??? REG NA N2577 ( 1, 1) [003035] ----------- t3035 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N2579 ( 1, 2) [003036] -c--------- t3036 = CNS_INT long 16 REG NA $200 /--* t3035 byref +--* t3036 long N2581 ( 3, 4) [003037] -----O----- t3037 = * ADD byref REG x14 $25c /--* t3037 byref N2583 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 x14 REG x14 N2585 ( 1, 1) [002259] ----------- t2259 = LCL_VAR int V122 tmp82 u:1 x11 REG x11 N2587 ( 1, 1) [002264] ----------- t2264 = LCL_VAR byref V124 tmp84 u:1 x14 REG x14 $25c /--* t2264 byref N2589 ( 3, 4) [003040] -c--------- t3040 = * LEA(b+8) byref REG NA /--* t3040 byref N2591 ( 4, 3) [002265] n---GO----- t2265 = * IND int REG x12 /--* t2259 int +--* t2265 int N2593 ( 9, 11) [002266] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2595 ( 1, 1) [002263] ----------- t2263 = LCL_VAR byref V124 tmp84 u:1 x14 (last use) REG x14 $25c /--* t2263 byref N2597 ( 3, 2) [002270] n---GO----- t2270 = * IND byref REG x14 N2599 ( 1, 1) [002260] ----------- t2260 = LCL_VAR int V122 tmp82 u:1 x11 REG x11 /--* t2260 int N2601 ( 2, 3) [002267] -c-------U- t2267 = * CAST long <- uint REG NA N2603 ( 1, 2) [002268] -c--------- t2268 = CNS_INT long 1 REG NA $204 /--* t2267 long +--* t2268 long N2605 ( 4, 6) [002269] -c--------- t2269 = * BFIZ long REG NA /--* t2270 byref +--* t2269 long N2607 ( 8, 9) [002271] -c--------- t2271 = * LEA(b+(i*1)+0) byref REG NA N2609 ( 1, 1) [002273] ----------- t2273 = LCL_VAR int V123 tmp83 u:1 x13 (last use) REG x13 /--* t2271 byref +--* t2273 int N2611 (???,???) [004082] -A-XGO----- * STOREIND short REG NA N2613 (???,???) [004083] ----------- IL_OFFSET void INL53 @ 0x023[E-] <- INLRT @ ??? REG NA N2615 ( 1, 1) [002277] ----------- t2277 = LCL_VAR int V122 tmp82 u:1 x11 (last use) REG x11 N2617 ( 1, 2) [002278] -c--------- t2278 = CNS_INT int 1 REG NA $c1 /--* t2277 int +--* t2278 int N2619 ( 3, 4) [002279] ----------- t2279 = * ADD int REG x13 N2621 ( 1, 1) [002276] ----------- t2276 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2276 byref N2623 ( 3, 4) [003043] -c--------- t3043 = * LEA(b+8) byref REG NA /--* t3043 byref +--* t2279 int N2625 (???,???) [004084] -A--GO----- * STOREIND int REG NA ------------ BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} N001 ( 1, 1) [004470] ----------Z t4470 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004471] ----------Z t4471 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004472] ----------Z t4472 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004473] ----------Z t4473 = LCL_VAR int V144 tmp104 x8 REG x8 N2629 (???,???) [004085] ----------- IL_OFFSET void INL53 @ 0x02D[E-] <- INLRT @ ??? REG NA N2631 ( 1, 1) [002254] ----------- t2254 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2254 byref N2633 (???,???) [004280] ----------- t4280 = * PUTARG_REG byref REG x0 N2635 ( 1, 1) [002255] ----------- t2255 = LCL_VAR int V123 tmp83 u:1 x13 (last use) REG x13 /--* t2255 int N2637 (???,???) [004281] ----------- t4281 = * PUTARG_REG int REG x1 N2639 ( 2, 8) [003044] H---------- t3044 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3044 long N2641 (???,???) [004282] ----------- t4282 = * PUTARG_REG long REG x11 /--* t4280 byref this in x0 +--* t4281 int arg2 in x1 +--* t4282 long r2r cell in x11 N2643 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004474] ----------z t4474 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004475] ----------z t4475 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004476] ----------z t4476 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004477] ----------z t4477 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} N2647 (???,???) [004086] ----------- IL_OFFSET void INLRT @ 0x64D[E-] REG NA N2649 ( 1, 2) [003045] -c--------- t3045 = CNS_INT int 0 REG NA $c0 /--* t3045 int N2651 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 x11 REG x11 N2653 (???,???) [004087] ----------- IL_OFFSET void INLRT @ 0x650[E-] REG NA N2655 ( 1, 2) [000326] -c--------- t326 = CNS_INT int 0 REG NA $c0 /--* t326 int N2657 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 x14 REG x14 N2659 (???,???) [004088] ----------- IL_OFFSET void INLRT @ 0x653[E-] REG NA N2661 ( 1, 1) [000329] ----------z t329 = LCL_VAR int V09 loc5 u:3 x5 REG x5 $4c6 N2663 ( 1, 2) [000330] -c--------- t330 = CNS_INT int 0 REG NA $c0 /--* t329 int +--* t330 int N2665 ( 3, 4) [000331] CEQ-------N--- * JCMP void REG NA ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} N2669 (???,???) [004089] ----------- IL_OFFSET void INLRT @ 0x65A[E-] REG NA N2671 ( 1, 1) [000419] ----------z t419 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2673 ( 1, 1) [003702] ----------- t3702 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t419 int +--* t3702 int N2675 ( 3, 3) [000424] J------N--- * GE void REG NA $94d N2677 ( 5, 5) [000425] ----------- * JTRUE void REG NA $VN.Void ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} N2681 (???,???) [004090] ----------- IL_OFFSET void INLRT @ 0x665[E-] REG NA N2683 ( 1, 1) [000565] ----------- t565 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2685 ( 1, 1) [000566] ----------- t566 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 /--* t566 int N2687 ( 2, 3) [000567] -c--------- t567 = * CAST long <- int REG NA $3e5 N2689 ( 1, 2) [000569] -c--------- t569 = CNS_INT long 1 REG NA $204 /--* t567 long +--* t569 long N2691 ( 4, 6) [000570] -c--------- t570 = * BFIZ long REG NA /--* t565 long +--* t570 long N2693 ( 6, 8) [000571] -c--------- t571 = * LEA(b+(i*1)+0) long REG NA /--* t571 long N2695 ( 9, 10) [000572] ---XG------ t572 = * IND ushort REG x12 /--* t572 ushort N2697 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 x12 REG x12 N2699 ( 1, 1) [003670] ----------- t3670 = LCL_VAR int V176 cse5 x12 (last use) REG x12 N2701 ( 1, 2) [000573] -c--------- t573 = CNS_INT int 48 REG NA $d8 /--* t3670 int +--* t573 int N2703 ( 12, 14) [000574] N--XG--N-U- * EQ void REG NA N2705 ( 14, 16) [000575] ---XG------ * JTRUE void REG NA $87a ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} N2709 (???,???) [004091] ----------- IL_OFFSET void INLRT @ 0x67A[E-] REG NA N2711 ( 1, 1) [000426] ----------- t426 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2713 ( 1, 2) [000427] -c--------- t427 = CNS_INT int 1 REG NA $c1 /--* t426 int +--* t427 int N2715 ( 3, 4) [000428] ----------- t428 = * ADD int REG x12 $952 N2717 ( 1, 1) [003703] ----------- t3703 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t428 int +--* t3703 int N2719 ( 5, 6) [000433] J------N--- * GE void REG NA $9e2 N2721 ( 7, 8) [000434] ----------- * JTRUE void REG NA $VN.Void ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} N2725 (???,???) [004092] ----------- IL_OFFSET void INLRT @ 0x687[E-] REG NA N2727 ( 1, 1) [000538] ----------- t538 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2729 ( 1, 1) [000539] ----------- t539 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 /--* t539 int N2731 ( 2, 3) [000540] -c--------- t540 = * CAST long <- int REG NA $3e5 N2733 ( 1, 2) [000542] -c--------- t542 = CNS_INT long 1 REG NA $204 /--* t540 long +--* t542 long N2735 ( 4, 6) [000543] -c--------- t543 = * BFIZ long REG NA /--* t538 long +--* t543 long N2737 ( 6, 8) [000544] -c--------- t544 = * LEA(b+(i*1)+0) long REG NA /--* t544 long N2739 ( 9, 10) [000545] ---XG------ t545 = * IND ushort REG x12 /--* t545 ushort N2741 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 x12 REG x12 N2743 ( 1, 1) [003674] ----------- t3674 = LCL_VAR int V176 cse5 x12 REG x12 N2745 ( 1, 2) [000546] -c--------- t546 = CNS_INT int 43 REG NA $d9 /--* t3674 int +--* t546 int N2747 ( 15, 14) [000547] N--XG--N-U- t547 = * NE int REG x15 N2749 ( 1, 1) [000549] ----------- t549 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2751 ( 1, 1) [000550] ----------- t550 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2753 ( 1, 2) [000551] -c--------- t551 = CNS_INT int 1 REG NA $c1 /--* t550 int +--* t551 int N2755 ( 3, 4) [000552] ----------- t552 = * ADD int REG xip0 $952 /--* t552 int N2757 ( 4, 6) [000553] -c--------- t553 = * CAST long <- int REG NA $3f4 N2759 ( 1, 2) [000555] -c--------- t555 = CNS_INT long 1 REG NA $204 /--* t553 long +--* t555 long N2761 ( 6, 9) [000556] -c--------- t556 = * BFIZ long REG NA /--* t549 long +--* t556 long N2763 ( 8, 11) [000557] -c--------- t557 = * LEA(b+(i*1)+0) long REG NA /--* t557 long N2765 ( 11, 13) [000558] ---XG------ t558 = * IND ushort REG xip0 N2767 ( 1, 2) [000559] -c--------- t559 = CNS_INT int 48 REG NA $d8 /--* t558 ushort +--* t559 int N2769 ( 16, 16) [000560] N--XG--N-U- t560 = * NE int REG xip0 /--* t547 int +--* t560 int N2771 ( 32, 31) [003762] J--XG--N--- t3762 = * AND int REG x15 /--* t3762 int N2773 ( 34, 33) [000548] ---XG------ * JTRUE void REG NA $87a ------------ BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} N2777 (???,???) [004093] ----------- IL_OFFSET void INLRT @ 0x694[E-] REG NA N2779 (???,???) [004094] ----------- IL_OFFSET void INLRT @ 0x6A3[E-] REG NA N2781 ( 1, 2) [003046] ----------- t3046 = CNS_INT int 1 REG x11 $c1 /--* t3046 int N2783 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 x11 REG x11 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} N2787 (???,???) [004095] ----------- IL_OFFSET void INLRT @ 0x6B5[E-] REG NA N2789 ( 1, 1) [003676] ----------- t3676 = LCL_VAR int V176 cse5 x12 (last use) REG x12 N2791 ( 1, 2) [000455] -c--------- t455 = CNS_INT int 45 REG NA $da /--* t3676 int +--* t455 int N2793 ( 3, 4) [000456] N---G--N-U- * NE void REG NA N2795 ( 5, 6) [000457] ----G------ * JTRUE void REG NA $87a ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} N2799 (???,???) [004096] ----------- IL_OFFSET void INLRT @ 0x6C2[E-] REG NA N2801 ( 1, 1) [000458] ----------- t458 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2803 ( 1, 1) [000459] ----------- t459 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2805 ( 1, 2) [000460] -c--------- t460 = CNS_INT int 1 REG NA $c1 /--* t459 int +--* t460 int N2807 ( 3, 4) [000461] ----------- t461 = * ADD int REG x12 $952 /--* t461 int N2809 ( 4, 6) [000462] -c--------- t462 = * CAST long <- int REG NA $3f4 N2811 ( 1, 2) [000464] -c--------- t464 = CNS_INT long 1 REG NA $204 /--* t462 long +--* t464 long N2813 ( 6, 9) [000465] -c--------- t465 = * BFIZ long REG NA /--* t458 long +--* t465 long N2815 ( 8, 11) [000466] -c--------- t466 = * LEA(b+(i*1)+0) long REG NA /--* t466 long N2817 ( 11, 13) [000467] ---XG------ t467 = * IND ushort REG x12 N2819 ( 1, 2) [000468] -c--------- t468 = CNS_INT int 48 REG NA $d8 /--* t467 ushort +--* t468 int N2821 ( 13, 16) [000469] J--XG--N--- * EQ void REG NA N2823 ( 15, 18) [000470] ---XG------ * JTRUE void REG NA $a11 ------------ BB215 [6D1..6DE) -> BB269 (cond), preds={BB208,BB213,BB214} succs={BB216,BB269} N2827 (???,???) [004097] ----------- IL_OFFSET void INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] REG NA N2829 ( 1, 1) [000444] ----------- t444 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t444 byref N2831 ( 3, 4) [003048] -c--------- t3048 = * LEA(b+8) byref REG NA /--* t3048 byref N2833 ( 4, 3) [002302] ---XG------ t2302 = * IND int REG x14 /--* t2302 int N2835 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 x14 REG x14 N2837 (???,???) [004098] ----------- IL_OFFSET void INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] REG NA N2839 ( 1, 1) [002305] ----------- t2305 = LCL_VAR int V126 tmp86 u:1 x14 REG x14 N2841 ( 1, 1) [002306] ----------- t2306 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2306 byref N2843 ( 3, 4) [003052] -c--------- t3052 = * LEA(b+24) byref REG NA /--* t3052 byref N2845 ( 4, 3) [002341] n---GO----- t2341 = * IND int REG x11 /--* t2305 int +--* t2341 int N2847 ( 6, 5) [002310] N---GO-N-U- * GE void REG NA N2849 ( 8, 7) [002311] ----GO----- * JTRUE void REG NA $845 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} N2853 (???,???) [004099] ----------- IL_OFFSET void INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] REG NA N2855 ( 1, 1) [003056] ----------- t3056 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N2857 ( 1, 2) [003057] -c--------- t3057 = CNS_INT long 16 REG NA $200 /--* t3056 byref +--* t3057 long N2859 ( 3, 4) [003058] -----O----- t3058 = * ADD byref REG x11 $25c /--* t3058 byref N2861 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 x11 REG x11 N2863 (???,???) [004100] ----------- IL_OFFSET void INL58 @ ??? <- INLRT @ 0x6D1[E-] REG NA N2865 ( 1, 1) [002316] ----------- t2316 = LCL_VAR int V126 tmp86 u:1 x14 REG x14 N2867 ( 1, 1) [002321] ----------- t2321 = LCL_VAR byref V127 tmp87 u:1 x11 REG x11 $25c /--* t2321 byref N2869 ( 3, 4) [003061] -c--------- t3061 = * LEA(b+8) byref REG NA /--* t3061 byref N2871 ( 4, 3) [002322] n---GO----- t2322 = * IND int REG x12 /--* t2316 int +--* t2322 int N2873 ( 9, 11) [002323] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2875 ( 1, 1) [002320] ----------- t2320 = LCL_VAR byref V127 tmp87 u:1 x11 (last use) REG x11 $25c /--* t2320 byref N2877 ( 3, 2) [002327] n---GO----- t2327 = * IND byref REG x11 N2879 ( 1, 1) [002317] ----------- t2317 = LCL_VAR int V126 tmp86 u:1 x14 REG x14 /--* t2317 int N2881 ( 2, 3) [002324] -c-------U- t2324 = * CAST long <- uint REG NA N2883 ( 1, 2) [002325] -c--------- t2325 = CNS_INT long 1 REG NA $204 /--* t2324 long +--* t2325 long N2885 ( 4, 6) [002326] -c--------- t2326 = * BFIZ long REG NA /--* t2327 byref +--* t2326 long N2887 ( 8, 9) [002328] -c--------- t2328 = * LEA(b+(i*1)+0) byref REG NA N2889 ( 1, 1) [002330] ----------- t2330 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t2328 byref +--* t2330 int N2891 (???,???) [004101] -A-XGO----- * STOREIND short REG NA N2893 (???,???) [004102] ----------- IL_OFFSET void INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] REG NA N2895 ( 1, 1) [002334] ----------- t2334 = LCL_VAR int V126 tmp86 u:1 x14 (last use) REG x14 N2897 ( 1, 2) [002335] -c--------- t2335 = CNS_INT int 1 REG NA $c1 /--* t2334 int +--* t2335 int N2899 ( 3, 4) [002336] ----------- t2336 = * ADD int REG x13 N2901 ( 1, 1) [002333] ----------- t2333 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2333 byref N2903 ( 3, 4) [003064] -c--------- t3064 = * LEA(b+8) byref REG NA /--* t3064 byref +--* t2336 int N2905 (???,???) [004103] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004478] ----------Z t4478 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004479] ----------Z t4479 = LCL_VAR bool V09 loc5 x5 REG x5 N001 ( 1, 1) [004480] ----------z t4480 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB269 [???..???) -> BB244 (always), preds={BB215} succs={BB244} N001 ( 1, 1) [004351] ----------Z t4351 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004352] ----------Z t4352 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004353] ----------Z t4353 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004354] ----------Z t4354 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004355] ----------Z t4355 = LCL_VAR bool V09 loc5 x5 REG x5 ------------ BB218 [6DE..6E4), preds={BB207,BB271} succs={BB219} N2909 (???,???) [004104] ----------- IL_OFFSET void INLRT @ 0x6DE[E-] REG NA N2911 ( 1, 1) [000533] ----------- t533 = LCL_VAR int V38 loc34 u:5 x14 (last use) REG x14 $b0d N2913 ( 1, 2) [000534] -c--------- t534 = CNS_INT int 1 REG NA $c1 /--* t533 int +--* t534 int N2915 ( 3, 4) [000535] ----------- t535 = * ADD int REG x14 $c59 /--* t535 int N2917 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 x14 REG x14 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} N2921 (???,???) [004105] ----------- IL_OFFSET void INLRT @ 0x6E4[E-] REG NA N2923 ( 1, 1) [000471] ----------- t471 = LCL_VAR int V16 loc12 u:9 x4 (last use) REG x4 $b0e N2925 ( 1, 2) [000472] -c--------- t472 = CNS_INT int 1 REG NA $c1 /--* t471 int +--* t472 int N2927 ( 3, 4) [000473] ----------- t473 = * ADD int REG x4 $c5c /--* t473 int N2929 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 x4 REG x4 N2931 ( 1, 1) [000477] ----------- t477 = LCL_VAR int V54 tmp14 u:1 x4 (last use) REG x4 $c5c /--* t477 int N2933 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 x12 REG x12 N2935 ( 1, 1) [000476] ----------- t476 = LCL_VAR int V16 loc12 u:10 x12 REG x12 $c5c N2937 ( 1, 1) [003704] ----------- t3704 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t476 int +--* t3704 int N2939 ( 3, 3) [000484] J------N--- * GE void REG NA $c5d N2941 ( 5, 5) [000485] ----------- * JTRUE void REG NA $VN.Void ------------ BB220 [6F4..701) -> BB271 (cond), preds={BB219} succs={BB270,BB271} N2945 (???,???) [004106] ----------- IL_OFFSET void INLRT @ 0x6F4[E-] REG NA N2947 ( 1, 1) [000522] ----------- t522 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2949 ( 1, 1) [000523] ----------Z t523 = LCL_VAR int V16 loc12 u:10 x12 REG x12 $c5c /--* t523 int N2951 ( 2, 3) [000524] -c--------- t524 = * CAST long <- int REG NA $ad8 N2953 ( 1, 2) [000526] -c--------- t526 = CNS_INT long 1 REG NA $204 /--* t524 long +--* t526 long N2955 ( 4, 6) [000527] -c--------- t527 = * BFIZ long REG NA /--* t522 long +--* t527 long N2957 ( 6, 8) [000528] -c--------- t528 = * LEA(b+(i*1)+0) long REG NA /--* t528 long N2959 ( 9, 10) [000529] ---XG------ t529 = * IND ushort REG x5 N2961 ( 1, 2) [000530] -c--------- t530 = CNS_INT int 48 REG NA $d8 /--* t529 ushort +--* t530 int N2963 ( 11, 13) [000531] J--XG--N--- * EQ void REG NA N2965 ( 13, 15) [000532] ---XG------ * JTRUE void REG NA $c18 ------------ BB270 [???..???), preds={BB220} succs={BB221} N001 ( 1, 1) [004356] ----------z t4356 = LCL_VAR int V16 loc12 x12 REG x12 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB270} succs={BB222,BB223} N2969 (???,???) [004107] ----------- IL_OFFSET void INLRT @ 0x701[E-] REG NA N2971 ( 1, 1) [000486] ----------- t486 = LCL_VAR int V38 loc34 u:2 x14 REG x14 $b0f N2973 ( 1, 2) [000487] -c--------- t487 = CNS_INT int 10 REG NA $e4 /--* t486 int +--* t487 int N2975 ( 3, 4) [000488] J------N--- * LE void REG NA $c62 N2977 ( 5, 6) [000489] ----------- * JTRUE void REG NA $VN.Void ------------ BB222 [707..70B), preds={BB221} succs={BB223} N2981 (???,???) [004108] ----------- IL_OFFSET void INLRT @ 0x707[E-] REG NA N2983 ( 1, 2) [000519] ----------- t519 = CNS_INT int 10 REG x14 $e4 /--* t519 int N2985 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 x14 REG x14 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} N2989 (???,???) [004109] ----------- IL_OFFSET void INLRT @ 0x70B[E-] REG NA N2991 ( 1, 1) [000490] ----------- t490 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t490 long N2993 ( 4, 3) [000491] ---XG------ t491 = * IND ubyte REG x5 N2995 ( 1, 2) [000492] -c--------- t492 = CNS_INT int 0 REG NA $c0 /--* t491 ubyte +--* t492 int N2997 ( 6, 6) [000493] CEQ---XG--N--- * JCMP void REG NA ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} N3001 (???,???) [004110] ----------- IL_OFFSET void INLRT @ 0x710[E-] REG NA N3003 ( 1, 1) [000512] ----------- t512 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t512 byref N3005 ( 3, 4) [003067] -c--------- t3067 = * LEA(b+4) byref REG NA /--* t3067 byref N3007 ( 4, 3) [000513] n---GO----- t513 = * IND int REG x5 N3009 ( 1, 1) [000514] ----------- t514 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t513 int +--* t514 int N3011 ( 6, 5) [000515] ----GO----- t515 = * SUB int REG x4 /--* t515 int N3013 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 x4 REG x4 N001 ( 1, 1) [004481] ----------Z t4481 = LCL_VAR int V16 loc12 x12 REG x12 N001 ( 1, 1) [004482] ----------Z t4482 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004483] ----------Z t4483 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004484] ----------Z t4484 = LCL_VAR int V144 tmp104 x8 REG x8 ------------ BB271 [???..???) -> BB218 (always), preds={BB220} succs={BB218} N001 ( 1, 1) [004357] ----------z t4357 = LCL_VAR int V16 loc12 x4 REG x4 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} N3017 (???,???) [004111] ----------- IL_OFFSET void INLRT @ 0x71A[E-] REG NA N3019 ( 1, 2) [000495] -c--------- t495 = CNS_INT int 0 REG NA $c0 /--* t495 int N3021 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 x4 REG x4 N001 ( 1, 1) [004485] ----------Z t4485 = LCL_VAR int V16 loc12 x12 REG x12 N001 ( 1, 1) [004486] ----------Z t4486 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004487] ----------Z t4487 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004488] ----------Z t4488 = LCL_VAR int V144 tmp104 x8 REG x8 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} N3025 (???,???) [004112] ----------- IL_OFFSET void INLRT @ 0x71D[E-] REG NA N3027 ( 1, 1) [000507] ----------- t507 = LCL_VAR int V37 loc33 u:2 x11 (last use) REG x11 $4ca /--* t507 int N3029 (???,???) [004283] ----------- t4283 = * PUTARG_REG int REG x5 N3031 ( 1, 1) [000502] ----------- t502 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t502 byref N3033 (???,???) [004284] ----------- t4284 = * PUTARG_REG byref REG x0 N3035 ( 1, 1) [000503] ----------- t503 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t503 ref N3037 (???,???) [004285] ----------- t4285 = * PUTARG_REG ref REG x1 N3039 ( 1, 1) [000499] ----------- t499 = LCL_VAR int V55 tmp15 u:1 x4 (last use) REG x4 $b12 /--* t499 int N3041 (???,???) [004286] ----------- t4286 = * PUTARG_REG int REG x2 N3043 ( 1, 1) [000505] ----------- t505 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t505 int N3045 (???,???) [004287] ----------- t4287 = * PUTARG_REG int REG x3 N3047 ( 1, 1) [000506] ----------- t506 = LCL_VAR int V38 loc34 u:3 x14 (last use) REG x14 $b10 /--* t506 int N3049 (???,???) [004288] ----------- t4288 = * PUTARG_REG int REG x4 N3051 ( 2, 8) [003068] H---------- t3068 = CNS_INT(h) long 0x4000000000540240 ftn REG x11 $5e /--* t3068 long N3053 (???,???) [004289] ----------- t4289 = * PUTARG_REG long REG x11 /--* t4283 int arg6 in x5 +--* t4284 byref arg1 in x0 +--* t4285 ref arg2 in x1 +--* t4286 int arg3 in x2 +--* t4287 int arg4 in x3 +--* t4288 int arg5 in x4 +--* t4289 long r2r cell in x11 N3055 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) REG NA $VN.Void N3057 (???,???) [004113] ----------- IL_OFFSET void INLRT @ 0x72C[E-] REG NA N3059 ( 1, 2) [003069] -c--------- t3069 = CNS_INT int 0 REG NA $c0 /--* t3069 int N3061 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 NA REG NA N001 ( 1, 1) [004489] ----------z t4489 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004490] ----------z t4490 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004491] ----------z t4491 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004492] ----------z t4492 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} N3065 (???,???) [004114] ----------- IL_OFFSET void INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] REG NA N3067 ( 1, 1) [000333] ----------- t333 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t333 byref N3069 ( 3, 4) [003071] -c--------- t3071 = * LEA(b+8) byref REG NA /--* t3071 byref N3071 ( 4, 3) [002349] ---XG------ t2349 = * IND int REG x11 /--* t2349 int N3073 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 x11 REG x11 N3075 (???,???) [004115] ----------- IL_OFFSET void INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] REG NA N3077 ( 1, 1) [002352] ----------- t2352 = LCL_VAR int V129 tmp89 u:1 x11 REG x11 N3079 ( 1, 1) [002353] ----------- t2353 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2353 byref N3081 ( 3, 4) [003075] -c--------- t3075 = * LEA(b+24) byref REG NA /--* t3075 byref N3083 ( 4, 3) [002388] n---GO----- t2388 = * IND int REG x14 /--* t2352 int +--* t2388 int N3085 ( 6, 5) [002357] N---GO-N-U- * GE void REG NA N3087 ( 8, 7) [002358] ----GO----- * JTRUE void REG NA $845 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} N3091 (???,???) [004116] ----------- IL_OFFSET void INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] REG NA N3093 ( 1, 1) [003079] ----------- t3079 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N3095 ( 1, 2) [003080] -c--------- t3080 = CNS_INT long 16 REG NA $200 /--* t3079 byref +--* t3080 long N3097 ( 3, 4) [003081] -----O----- t3081 = * ADD byref REG x14 $25c /--* t3081 byref N3099 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 x14 REG x14 N3101 (???,???) [004117] ----------- IL_OFFSET void INL61 @ ??? <- INLRT @ 0x731[E-] REG NA N3103 ( 1, 1) [002363] ----------- t2363 = LCL_VAR int V129 tmp89 u:1 x11 REG x11 N3105 ( 1, 1) [002368] ----------- t2368 = LCL_VAR byref V130 tmp90 u:1 x14 REG x14 $25c /--* t2368 byref N3107 ( 3, 4) [003084] -c--------- t3084 = * LEA(b+8) byref REG NA /--* t3084 byref N3109 ( 4, 3) [002369] n---GO----- t2369 = * IND int REG x12 /--* t2363 int +--* t2369 int N3111 ( 9, 11) [002370] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N3113 ( 1, 1) [002367] ----------- t2367 = LCL_VAR byref V130 tmp90 u:1 x14 (last use) REG x14 $25c /--* t2367 byref N3115 ( 3, 2) [002374] n---GO----- t2374 = * IND byref REG x14 N3117 ( 1, 1) [002364] ----------- t2364 = LCL_VAR int V129 tmp89 u:1 x11 REG x11 /--* t2364 int N3119 ( 2, 3) [002371] -c-------U- t2371 = * CAST long <- uint REG NA N3121 ( 1, 2) [002372] -c--------- t2372 = CNS_INT long 1 REG NA $204 /--* t2371 long +--* t2372 long N3123 ( 4, 6) [002373] -c--------- t2373 = * BFIZ long REG NA /--* t2374 byref +--* t2373 long N3125 ( 8, 9) [002375] -c--------- t2375 = * LEA(b+(i*1)+0) byref REG NA N3127 ( 1, 1) [002377] ----------- t2377 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t2375 byref +--* t2377 int N3129 (???,???) [004118] -A-XGO----- * STOREIND short REG NA N3131 (???,???) [004119] ----------- IL_OFFSET void INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] REG NA N3133 ( 1, 1) [002381] ----------- t2381 = LCL_VAR int V129 tmp89 u:1 x11 (last use) REG x11 N3135 ( 1, 2) [002382] -c--------- t2382 = CNS_INT int 1 REG NA $c1 /--* t2381 int +--* t2382 int N3137 ( 3, 4) [002383] ----------- t2383 = * ADD int REG x13 N3139 ( 1, 1) [002380] ----------- t2380 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2380 byref N3141 ( 3, 4) [003087] -c--------- t3087 = * LEA(b+8) byref REG NA /--* t3087 byref +--* t2383 int N3143 (???,???) [004120] -A--GO----- * STOREIND int REG NA ------------ BB229 [731..732), preds={BB227} succs={BB230} N001 ( 1, 1) [004493] ----------Z t4493 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004494] ----------Z t4494 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004495] ----------Z t4495 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004496] ----------Z t4496 = LCL_VAR bool V09 loc5 x5 REG x5 N3147 (???,???) [004121] ----------- IL_OFFSET void INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] REG NA N3149 ( 1, 1) [002359] ----------- t2359 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2359 byref N3151 (???,???) [004290] ----------- t4290 = * PUTARG_REG byref REG x0 N3153 ( 1, 1) [000334] ----------- t334 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t334 int N3155 (???,???) [004291] ----------- t4291 = * PUTARG_REG int REG x1 N3157 ( 2, 8) [003088] H---------- t3088 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3088 long N3159 (???,???) [004292] ----------- t4292 = * PUTARG_REG long REG x11 /--* t4290 byref this in x0 +--* t4291 int arg2 in x1 +--* t4292 long r2r cell in x11 N3161 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004497] ----------z t4497 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004498] ----------z t4498 = LCL_VAR bool V09 loc5 x5 REG x5 N001 ( 1, 1) [004499] ----------z t4499 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004500] ----------z t4500 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} N3165 (???,???) [004122] ----------- IL_OFFSET void INLRT @ 0x739[E-] REG NA N3167 ( 1, 1) [000336] ----------z t336 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N3169 ( 1, 1) [003705] ----------- t3705 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t336 int +--* t3705 int N3171 ( 3, 3) [000341] J------N--- * GE void REG NA $94d N001 ( 1, 1) [004358] ----------Z t4358 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004359] ----------Z t4359 = LCL_VAR bool V09 loc5 x5 REG x5 N001 ( 1, 1) [004360] ----------z t4360 = LCL_VAR int V14 loc10 x3 REG x3 N3173 ( 5, 5) [000342] ----------- * JTRUE void REG NA $VN.Void ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} N3177 (???,???) [004123] ----------- IL_OFFSET void INLRT @ 0x744[E-] REG NA N3179 ( 1, 1) [000343] ----------- t343 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N3181 ( 1, 1) [000344] ----------z t344 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 /--* t344 int N3183 ( 2, 3) [000345] -c--------- t345 = * CAST long <- int REG NA $3e5 N3185 ( 1, 2) [000347] -c--------- t347 = CNS_INT long 1 REG NA $204 /--* t345 long +--* t347 long N3187 ( 4, 6) [000348] -c--------- t348 = * BFIZ long REG NA /--* t343 long +--* t348 long N3189 ( 6, 8) [000349] -c--------- t349 = * LEA(b+(i*1)+0) long REG NA /--* t349 long N3191 ( 9, 10) [000350] ---XG------ t350 = * IND ushort REG x11 /--* t350 ushort N3193 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 x11 REG x11 N3195 ( 1, 1) [003659] ----------- t3659 = LCL_VAR int V175 cse4 u:1 x11 REG x11 N3197 ( 1, 2) [000351] -c--------- t351 = CNS_INT int 43 REG NA $d9 /--* t3659 int +--* t351 int N3199 ( 12, 14) [000352] J--XG--N--- * EQ void REG NA N3201 ( 14, 16) [000353] ---XG------ * JTRUE void REG NA $87a ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} N3205 (???,???) [004124] ----------- IL_OFFSET void INLRT @ 0x751[E-] REG NA N3207 ( 1, 1) [003661] ----------- t3661 = LCL_VAR int V175 cse4 u:1 x11 REG x11 N3209 ( 1, 2) [000416] -c--------- t416 = CNS_INT int 45 REG NA $da /--* t3661 int +--* t416 int N3211 ( 3, 4) [000417] N---G--N-U- * NE void REG NA N3213 ( 5, 6) [000418] ----G------ * JTRUE void REG NA $87a ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} N3217 (???,???) [004125] ----------- IL_OFFSET void INLRT @ 0x75E[E-] REG NA N3219 ( 1, 1) [000356] ----------- t356 = LCL_VAR int V16 loc12 u:5 x4 (last use) REG x4 $898 /--* t356 int N3221 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 x4 REG x4 N3223 (???,???) [004126] ----------- IL_OFFSET void INLRT @ 0x75E[E-] REG NA N3225 ( 1, 1) [000357] ----------- t357 = LCL_VAR int V52 tmp12 u:1 x4 (last use) REG x4 $898 N3227 ( 1, 2) [000358] -c--------- t358 = CNS_INT int 1 REG NA $c1 /--* t357 int +--* t358 int N3229 ( 3, 4) [000359] ----------- t359 = * ADD int REG x4 $952 /--* t359 int N3231 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 NA REG NA N3233 ( 1, 1) [003662] ----------- t3662 = LCL_VAR int V175 cse4 u:1 x11 (last use) REG x11 /--* t3662 int N3235 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 x11 REG x11 N3237 (???,???) [004127] ----------- IL_OFFSET void INL64 @ 0x000[E-] <- INLRT @ ??? REG NA N3239 ( 1, 1) [000354] ----------- t354 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t354 byref N3241 ( 3, 4) [003090] -c--------- t3090 = * LEA(b+8) byref REG NA /--* t3090 byref N3243 ( 4, 3) [002396] n---GO----- t2396 = * IND int REG x13 /--* t2396 int N3245 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 x13 REG x13 N3247 (???,???) [004128] ----------- IL_OFFSET void INL64 @ 0x007[E-] <- INLRT @ ??? REG NA N3249 ( 1, 1) [002399] ----------- t2399 = LCL_VAR int V132 tmp92 u:1 x13 REG x13 N3251 ( 1, 1) [002400] ----------- t2400 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2400 byref N3253 ( 3, 4) [003094] -c--------- t3094 = * LEA(b+24) byref REG NA /--* t3094 byref N3255 ( 4, 3) [002438] n---GO----- t2438 = * IND int REG x14 /--* t2399 int +--* t2438 int N3257 ( 6, 5) [002404] N---GO-N-U- * GE void REG NA N3259 ( 8, 7) [002405] ----GO----- * JTRUE void REG NA $845 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} N3263 (???,???) [004129] ----------- IL_OFFSET void INL64 @ 0x015[E-] <- INLRT @ ??? REG NA N3265 ( 1, 1) [003098] ----------- t3098 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N3267 ( 1, 2) [003099] -c--------- t3099 = CNS_INT long 16 REG NA $200 /--* t3098 byref +--* t3099 long N3269 ( 3, 4) [003100] -----O----- t3100 = * ADD byref REG x14 $25c /--* t3100 byref N3271 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 x14 REG x14 N3273 ( 1, 1) [002411] ----------- t2411 = LCL_VAR int V132 tmp92 u:1 x13 REG x13 N3275 ( 1, 1) [002416] ----------- t2416 = LCL_VAR byref V134 tmp94 u:1 x14 REG x14 $25c /--* t2416 byref N3277 ( 3, 4) [003103] -c--------- t3103 = * LEA(b+8) byref REG NA /--* t3103 byref N3279 ( 4, 3) [002417] n---GO----- t2417 = * IND int REG x12 /--* t2411 int +--* t2417 int N3281 ( 9, 11) [002418] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N3283 ( 1, 1) [002415] ----------- t2415 = LCL_VAR byref V134 tmp94 u:1 x14 (last use) REG x14 $25c /--* t2415 byref N3285 ( 3, 2) [002422] n---GO----- t2422 = * IND byref REG x14 N3287 ( 1, 1) [002412] ----------- t2412 = LCL_VAR int V132 tmp92 u:1 x13 REG x13 /--* t2412 int N3289 ( 2, 3) [002419] -c-------U- t2419 = * CAST long <- uint REG NA N3291 ( 1, 2) [002420] -c--------- t2420 = CNS_INT long 1 REG NA $204 /--* t2419 long +--* t2420 long N3293 ( 4, 6) [002421] -c--------- t2421 = * BFIZ long REG NA /--* t2422 byref +--* t2421 long N3295 ( 8, 9) [002423] -c--------- t2423 = * LEA(b+(i*1)+0) byref REG NA N3297 ( 1, 1) [002425] ----------- t2425 = LCL_VAR int V133 tmp93 u:1 x11 (last use) REG x11 /--* t2423 byref +--* t2425 int N3299 (???,???) [004130] -A-XGO----- * STOREIND short REG NA N3301 (???,???) [004131] ----------- IL_OFFSET void INL64 @ 0x023[E-] <- INLRT @ ??? REG NA N3303 ( 1, 1) [002429] ----------- t2429 = LCL_VAR int V132 tmp92 u:1 x13 (last use) REG x13 N3305 ( 1, 2) [002430] -c--------- t2430 = CNS_INT int 1 REG NA $c1 /--* t2429 int +--* t2430 int N3307 ( 3, 4) [002431] ----------- t2431 = * ADD int REG x11 N3309 ( 1, 1) [002428] ----------- t2428 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2428 byref N3311 ( 3, 4) [003106] -c--------- t3106 = * LEA(b+8) byref REG NA /--* t3106 byref +--* t2431 int N3313 (???,???) [004132] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004501] ----------z t4501 = LCL_VAR int V16 loc12 x4 REG x4 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} N001 ( 1, 1) [004502] ----------Z t4502 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004503] ----------Z t4503 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004504] ----------Z t4504 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004505] ----------Z t4505 = LCL_VAR int V144 tmp104 x8 REG x8 N3317 (???,???) [004133] ----------- IL_OFFSET void INL64 @ 0x02D[E-] <- INLRT @ ??? REG NA N3319 ( 1, 1) [002406] ----------- t2406 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2406 byref N3321 (???,???) [004293] ----------- t4293 = * PUTARG_REG byref REG x0 N3323 ( 1, 1) [002407] ----------- t2407 = LCL_VAR int V133 tmp93 u:1 x11 (last use) REG x11 /--* t2407 int N3325 (???,???) [004294] ----------- t4294 = * PUTARG_REG int REG x1 N3327 ( 2, 8) [003107] H---------- t3107 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3107 long N3329 (???,???) [004295] ----------- t4295 = * PUTARG_REG long REG x11 /--* t4293 byref this in x0 +--* t4294 int arg2 in x1 +--* t4295 long r2r cell in x11 N3331 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004506] ----------z t4506 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004507] ----------z t4507 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004508] ----------z t4508 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004509] ----------z t4509 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004510] ----------z t4510 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} N3375 (???,???) [004134] ----------- IL_OFFSET void INLRT @ 0x774[E-] REG NA N3377 ( 1, 1) [000392] ----------- t392 = LCL_VAR int V16 loc12 u:6 x4 (last use) REG x4 $b08 /--* t392 int N3379 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 x4 REG x4 N3381 (???,???) [004135] ----------- IL_OFFSET void INLRT @ 0x774[E-] REG NA N3383 ( 1, 1) [000393] ----------- t393 = LCL_VAR int V53 tmp13 u:1 x4 (last use) REG x4 $b08 N3385 ( 1, 2) [000394] -c--------- t394 = CNS_INT int 1 REG NA $c1 /--* t393 int +--* t394 int N3387 ( 3, 4) [000395] ----------- t395 = * ADD int REG x4 $c47 /--* t395 int N3389 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 NA REG NA N3391 ( 1, 1) [003639] ----------- t3639 = LCL_VAR int V173 cse2 u:1 x11 (last use) REG x11 /--* t3639 int N3393 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 x11 REG x11 N3395 (???,???) [004136] ----------- IL_OFFSET void INL66 @ 0x000[E-] <- INLRT @ ??? REG NA N3397 ( 1, 1) [000390] ----------- t390 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t390 byref N3399 ( 3, 4) [003109] -c--------- t3109 = * LEA(b+8) byref REG NA /--* t3109 byref N3401 ( 4, 3) [002442] n---GO----- t2442 = * IND int REG x13 /--* t2442 int N3403 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 x13 REG x13 N3405 (???,???) [004137] ----------- IL_OFFSET void INL66 @ 0x007[E-] <- INLRT @ ??? REG NA N3407 ( 1, 1) [002445] ----------- t2445 = LCL_VAR int V136 tmp96 u:1 x13 REG x13 N3409 ( 1, 1) [002446] ----------- t2446 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2446 byref N3411 ( 3, 4) [003113] -c--------- t3113 = * LEA(b+24) byref REG NA /--* t3113 byref N3413 ( 4, 3) [002484] n---GO----- t2484 = * IND int REG x14 /--* t2445 int +--* t2484 int N3415 ( 6, 5) [002450] N---GO-N-U- * GE void REG NA N3417 ( 8, 7) [002451] ----GO----- * JTRUE void REG NA $845 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} N3421 (???,???) [004138] ----------- IL_OFFSET void INL66 @ 0x015[E-] <- INLRT @ ??? REG NA N3423 ( 1, 1) [003117] ----------- t3117 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N3425 ( 1, 2) [003118] -c--------- t3118 = CNS_INT long 16 REG NA $200 /--* t3117 byref +--* t3118 long N3427 ( 3, 4) [003119] -----O----- t3119 = * ADD byref REG x14 $25c /--* t3119 byref N3429 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 x14 REG x14 N3431 ( 1, 1) [002457] ----------- t2457 = LCL_VAR int V136 tmp96 u:1 x13 REG x13 N3433 ( 1, 1) [002462] ----------- t2462 = LCL_VAR byref V138 tmp98 u:1 x14 REG x14 $25c /--* t2462 byref N3435 ( 3, 4) [003122] -c--------- t3122 = * LEA(b+8) byref REG NA /--* t3122 byref N3437 ( 4, 3) [002463] n---GO----- t2463 = * IND int REG x12 /--* t2457 int +--* t2463 int N3439 ( 9, 11) [002464] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N3441 ( 1, 1) [002461] ----------- t2461 = LCL_VAR byref V138 tmp98 u:1 x14 (last use) REG x14 $25c /--* t2461 byref N3443 ( 3, 2) [002468] n---GO----- t2468 = * IND byref REG x14 N3445 ( 1, 1) [002458] ----------- t2458 = LCL_VAR int V136 tmp96 u:1 x13 REG x13 /--* t2458 int N3447 ( 2, 3) [002465] -c-------U- t2465 = * CAST long <- uint REG NA N3449 ( 1, 2) [002466] -c--------- t2466 = CNS_INT long 1 REG NA $204 /--* t2465 long +--* t2466 long N3451 ( 4, 6) [002467] -c--------- t2467 = * BFIZ long REG NA /--* t2468 byref +--* t2467 long N3453 ( 8, 9) [002469] -c--------- t2469 = * LEA(b+(i*1)+0) byref REG NA N3455 ( 1, 1) [002471] ----------- t2471 = LCL_VAR int V137 tmp97 u:1 x11 (last use) REG x11 /--* t2469 byref +--* t2471 int N3457 (???,???) [004139] -A-XGO----- * STOREIND short REG NA N3459 (???,???) [004140] ----------- IL_OFFSET void INL66 @ 0x023[E-] <- INLRT @ ??? REG NA N3461 ( 1, 1) [002475] ----------- t2475 = LCL_VAR int V136 tmp96 u:1 x13 (last use) REG x13 N3463 ( 1, 2) [002476] -c--------- t2476 = CNS_INT int 1 REG NA $c1 /--* t2475 int +--* t2476 int N3465 ( 3, 4) [002477] ----------- t2477 = * ADD int REG x11 N3467 ( 1, 1) [002474] ----------- t2474 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2474 byref N3469 ( 3, 4) [003125] -c--------- t3125 = * LEA(b+8) byref REG NA /--* t3125 byref +--* t2477 int N3471 (???,???) [004141] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004511] ----------z t4511 = LCL_VAR int V16 loc12 x4 REG x4 ------------ BB238 [000..000), preds={BB236} succs={BB239} N001 ( 1, 1) [004512] ----------Z t4512 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004513] ----------Z t4513 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004514] ----------Z t4514 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004515] ----------Z t4515 = LCL_VAR int V144 tmp104 x8 REG x8 N3475 (???,???) [004142] ----------- IL_OFFSET void INL66 @ 0x02D[E-] <- INLRT @ ??? REG NA N3477 ( 1, 1) [002452] ----------- t2452 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2452 byref N3479 (???,???) [004296] ----------- t4296 = * PUTARG_REG byref REG x0 N3481 ( 1, 1) [002453] ----------- t2453 = LCL_VAR int V137 tmp97 u:1 x11 (last use) REG x11 /--* t2453 int N3483 (???,???) [004297] ----------- t4297 = * PUTARG_REG int REG x1 N3485 ( 2, 8) [003126] H---------- t3126 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3126 long N3487 (???,???) [004298] ----------- t4298 = * PUTARG_REG long REG x11 /--* t4296 byref this in x0 +--* t4297 int arg2 in x1 +--* t4298 long r2r cell in x11 N3489 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004516] ----------z t4516 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004517] ----------z t4517 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004518] ----------z t4518 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004519] ----------z t4519 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004520] ----------z t4520 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} N3335 (???,???) [004143] ----------- IL_OFFSET void INLRT @ 0x788[E-] REG NA N3337 ( 1, 1) [000372] ----------- t372 = LCL_VAR int V16 loc12 u:6 x4 REG x4 $b08 N3339 ( 1, 1) [003706] ----------- t3706 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t372 int +--* t3706 int N3341 ( 3, 3) [000377] J------N--- * GE void REG NA $c42 N001 ( 1, 1) [004361] ----------Z t4361 = LCL_VAR int V16 loc12 x4 REG x4 N3343 ( 5, 5) [000378] ----------- * JTRUE void REG NA $VN.Void ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} N3347 (???,???) [004144] ----------- IL_OFFSET void INLRT @ 0x793[E-] REG NA N3349 ( 1, 1) [000379] ----------- t379 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N3351 ( 1, 1) [000380] ----------z t380 = LCL_VAR int V16 loc12 u:6 x4 REG x4 $b08 /--* t380 int N3353 ( 2, 3) [000381] -c--------- t381 = * CAST long <- int REG NA $ad1 N3355 ( 1, 2) [000383] -c--------- t383 = CNS_INT long 1 REG NA $204 /--* t381 long +--* t383 long N3357 ( 4, 6) [000384] -c--------- t384 = * BFIZ long REG NA /--* t379 long +--* t384 long N3359 ( 6, 8) [000385] -c--------- t385 = * LEA(b+(i*1)+0) long REG NA /--* t385 long N3361 ( 9, 10) [000386] ---XG------ t386 = * IND ushort REG x11 /--* t386 ushort N3363 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 x11 REG x11 N3365 ( 1, 1) [003642] ----------- t3642 = LCL_VAR int V173 cse2 u:1 x11 REG x11 N3367 ( 1, 2) [000387] -c--------- t387 = CNS_INT int 48 REG NA $d8 /--* t3642 int +--* t387 int N3369 ( 12, 14) [000388] J--XG--N--- * EQ void REG NA N3371 ( 14, 16) [000389] ---XG------ * JTRUE void REG NA $c02 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} N001 ( 1, 1) [004521] ----------Z t4521 = LCL_VAR int V16 loc12 x4 REG x4 ------------ BB242 [7A2..7AA) -> BB272 (cond), preds={BB140,BB143,BB257(2),BB258(2)} succs={BB243,BB272} N3495 (???,???) [004145] ----------- IL_OFFSET void INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] REG NA N3497 ( 1, 1) [000590] ----------- t590 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t590 byref N3499 ( 3, 4) [003128] -c--------- t3128 = * LEA(b+8) byref REG NA /--* t3128 byref N3501 ( 4, 3) [002492] ---XG------ t2492 = * IND int REG x11 /--* t2492 int N3503 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 x11 REG x11 N3505 (???,???) [004146] ----------- IL_OFFSET void INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] REG NA N3507 ( 1, 1) [002495] ----------- t2495 = LCL_VAR int V140 tmp100 u:1 x11 REG x11 N3509 ( 1, 1) [002496] ----------- t2496 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2496 byref N3511 ( 3, 4) [003132] -c--------- t3132 = * LEA(b+24) byref REG NA /--* t3132 byref N3513 ( 4, 3) [002531] n---GO----- t2531 = * IND int REG x14 /--* t2495 int +--* t2531 int N3515 ( 6, 5) [002500] N---GO-N-U- * GE void REG NA N3517 ( 8, 7) [002501] ----GO----- * JTRUE void REG NA $845 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} N3521 (???,???) [004147] ----------- IL_OFFSET void INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] REG NA N3523 ( 1, 1) [003136] ----------- t3136 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N3525 ( 1, 2) [003137] -c--------- t3137 = CNS_INT long 16 REG NA $200 /--* t3136 byref +--* t3137 long N3527 ( 3, 4) [003138] -----O----- t3138 = * ADD byref REG x14 $25c /--* t3138 byref N3529 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 x14 REG x14 N3531 (???,???) [004148] ----------- IL_OFFSET void INL69 @ ??? <- INLRT @ 0x7A2[E-] REG NA N3533 ( 1, 1) [002506] ----------- t2506 = LCL_VAR int V140 tmp100 u:1 x11 REG x11 N3535 ( 1, 1) [002511] ----------- t2511 = LCL_VAR byref V141 tmp101 u:1 x14 REG x14 $25c /--* t2511 byref N3537 ( 3, 4) [003141] -c--------- t3141 = * LEA(b+8) byref REG NA /--* t3141 byref N3539 ( 4, 3) [002512] n---GO----- t2512 = * IND int REG x12 /--* t2506 int +--* t2512 int N3541 ( 9, 11) [002513] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N3543 ( 1, 1) [002510] ----------- t2510 = LCL_VAR byref V141 tmp101 u:1 x14 (last use) REG x14 $25c /--* t2510 byref N3545 ( 3, 2) [002517] n---GO----- t2517 = * IND byref REG x14 N3547 ( 1, 1) [002507] ----------- t2507 = LCL_VAR int V140 tmp100 u:1 x11 REG x11 /--* t2507 int N3549 ( 2, 3) [002514] -c-------U- t2514 = * CAST long <- uint REG NA N3551 ( 1, 2) [002515] -c--------- t2515 = CNS_INT long 1 REG NA $204 /--* t2514 long +--* t2515 long N3553 ( 4, 6) [002516] -c--------- t2516 = * BFIZ long REG NA /--* t2517 byref +--* t2516 long N3555 ( 8, 9) [002518] -c--------- t2518 = * LEA(b+(i*1)+0) byref REG NA N3557 ( 1, 1) [002520] ----------- t2520 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t2518 byref +--* t2520 int N3559 (???,???) [004149] -A-XGO----- * STOREIND short REG NA N3561 (???,???) [004150] ----------- IL_OFFSET void INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] REG NA N3563 ( 1, 1) [002524] ----------- t2524 = LCL_VAR int V140 tmp100 u:1 x11 (last use) REG x11 N3565 ( 1, 2) [002525] -c--------- t2525 = CNS_INT int 1 REG NA $c1 /--* t2524 int +--* t2525 int N3567 ( 3, 4) [002526] ----------- t2526 = * ADD int REG x13 N3569 ( 1, 1) [002523] ----------- t2523 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2523 byref N3571 ( 3, 4) [003144] -c--------- t3144 = * LEA(b+8) byref REG NA /--* t3144 byref +--* t2526 int N3573 (???,???) [004151] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004522] ----------z t4522 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB272 [???..???) -> BB244 (always), preds={BB242} succs={BB244} N001 ( 1, 1) [004362] ----------Z t4362 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004363] ----------Z t4363 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004364] ----------Z t4364 = LCL_VAR int V144 tmp104 x8 REG x8 ------------ BB244 [7A2..7A3) -> BB245 (always), preds={BB269,BB272} succs={BB245} N3577 (???,???) [004152] ----------- IL_OFFSET void INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] REG NA N3579 ( 1, 1) [002502] ----------- t2502 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2502 byref N3581 (???,???) [004299] ----------- t4299 = * PUTARG_REG byref REG x0 N3583 ( 1, 1) [000591] ----------- t591 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t591 int N3585 (???,???) [004300] ----------- t4300 = * PUTARG_REG int REG x1 N3587 ( 2, 8) [003145] H---------- t3145 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3145 long N3589 (???,???) [004301] ----------- t4301 = * PUTARG_REG long REG x11 /--* t4299 byref this in x0 +--* t4300 int arg2 in x1 +--* t4301 long r2r cell in x11 N3591 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004523] ----------z t4523 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004524] ----------z t4524 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004525] ----------z t4525 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004526] ----------z t4526 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB110 [000..000) (throw), preds={BB91} succs={} N5011 (???,???) [004153] ----------- IL_OFFSET void INL17 @ 0x029[E-] <- INLRT @ ??? REG NA N5013 ( 2, 8) [002701] H---------- t2701 = CNS_INT(h) long 0x4000000000424a20 ftn REG x11 $4a /--* t2701 long N5015 (???,???) [004302] ----------- t4302 = * PUTARG_REG long REG x11 /--* t4302 long r2r cell in x11 N5017 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() REG NA $VN.Void ------------ BB254 [???..???) (throw), preds={} succs={} N5021 ( 2, 8) [004303] H---------- t4303 = CNS_INT(h) long 0x4000000000421828 ftn REG x0 /--* t4303 long N5023 ( 5, 10) [004304] ----------- t4304 = * IND long REG x0 /--* t4304 long control expr N5025 ( 14, 2) [004154] --CXG------ * CALL help void CORINFO_HELP_RNGCHKFAIL REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 V0 Parm Alloc x19 | | | | | | | | | | | | | | | | | |V0 a| | | | | | | | | | 0.#1 V3 Parm Alloc x20 | | | | | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | 0.#2 V1 Parm Alloc x21 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 1.#3 BB1 PredBB0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | [004185] 7.#4 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 7.#5 V1 Use Copy x0 |V1 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 8.#6 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 8.#7 I137 Def Alloc x0 |I137a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | [002543] 10.#8 C138 Def Alloc x11 |I137a| | | | | | | | | | |C138a| | | | | |V0 a|V3 a|V1 a| | | | | | | | [004186] 11.#9 x11 Fixd Keep x11 |I137a| | | | | | | | | | |C138a| | | | | |V0 a|V3 a|V1 a| | | | | | | | 11.#10 C138 Use * Keep x11 |I137a| | | | | | | | | | |C138i| | | | | |V0 a|V3 a|V1 a| | | | | | | | 12.#11 x11 Fixd Keep x11 |I137a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 12.#12 I139 Def Alloc x11 |I137a| | | | | | | | | | |I139a| | | | | |V0 a|V3 a|V1 a| | | | | | | | [000001] 13.#13 I140 Def Alloc x1 |I137a|I140a| | | | | | | | | |I139a| | | | | |V0 a|V3 a|V1 a| | | | | | | | 13.#14 x0 Fixd Keep x0 |I137a|I140a| | | | | | | | | |I139a| | | | | |V0 a|V3 a|V1 a| | | | | | | | 13.#15 I137 Use * Keep x0 |I137i|I140a| | | | | | | | | |I139a| | | | | |V0 a|V3 a|V1 a| | | | | | | | 13.#16 x11 Fixd Keep x11 | |I140a| | | | | | | | | |I139a| | | | | |V0 a|V3 a|V1 a| | | | | | | | 13.#17 I139 Use * Keep x11 | |I140a| | | | | | | | | |I139i| | | | | |V0 a|V3 a|V1 a| | | | | | | | 13.#18 I140 Use * Keep x1 | |I140i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#19 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#20 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#21 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#22 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#23 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#24 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#25 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#26 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#27 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#28 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#29 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#30 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#31 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#32 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#33 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#34 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#35 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#36 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | 14.#37 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | [000004] 20.#38 V11 Def Alloc x22 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | [002548] 27.#39 V1 Use Keep x21 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | 28.#40 I141 Def Alloc x0 |I141a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | [001500] 29.#41 I141 Use * Keep x0 |I141i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | 30.#42 V76 Def Alloc x0 |V76 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | [001503] 39.#43 V76 Use Keep x0 |V76 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | 40.#44 I142 Def Alloc x1 |V76 a|I142a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | [001504] 41.#45 I142 Use * Keep x1 |V76 a|I142i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | [001505] 45.#46 V76 Use * Keep x0 |V76 i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a| | | | | | | 46.#47 I143 Def Alloc x23 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|I143a| | | | | | [002551] 47.#48 I143 Use * Keep x23 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|I143i| | | | | | 48.#49 V167 Def Alloc x23 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V167a| | | | | | [000009] 51.#50 V167 Use * Keep x23 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V167i| | | | | | 52.#51 V17 Def Alloc x23 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a| | | | | | [002558] 54.#52 I144 Def Alloc x24 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|I144a| | | | | [003709] 55.#53 I144 Use * Keep x24 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|I144i| | | | | 56.#54 V180 Def Alloc x24 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a| | | | | [002559] 59.#55 V180 Use Keep x24 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a| | | | | 60.#56 V147 Def Alloc x0 |V147a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a| | | | | [002561] 62.#57 I145 Def Alloc x25 |V147a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|I145a| | | | [003689] 63.#58 I145 Use * Keep x25 |V147a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|I145i| | | | 64.#59 V179 Def Alloc x25 |V147a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002562] 67.#60 V179 Use Keep x25 |V147a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 68.#61 V148 Def Alloc x1 |V147a|V148a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [000012] 73.#62 V17 Use Keep x23 |V147a|V148a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 74.#63 I146 Def Alloc x2 |V147a|V148a|I146a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [000014] 77.#64 I146 Use * Keep x2 |V147a|V148a|I146i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 79.#65 BB2 PredBB1 |V147a|V148a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002566] 83.#66 V147 Use * Keep x0 |V147i|V148a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 84.#67 V155 Def Alloc x0 |V155a|V148a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002569] 87.#68 V148 Use * Keep x1 |V155a|V148i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 88.#69 V156 Def Alloc x1 |V155a|V156a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [001473] 93.#70 V1 Use Keep x21 |V155a|V156a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 94.#71 I147 Def Alloc x2 |V155a|V156a|I147a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [001475] 97.#72 I147 Use * Keep x2 |V155a|V156a|I147i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 99.#73 BB3 PredBB2 |V155a|V156a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002575] 103.#74 V155 Use * Keep x0 |V155i|V156a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 104.#75 V149 Def Alloc x0 |V149a|V156a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002578] 107.#76 V156 Use * Keep x1 |V149a|V156i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 108.#77 V150 Def Alloc x1 |V149a|V150a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [001494] 112.#78 V43 Def Alloc x2 |V149a|V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 113.#79 BB4 PredBB2 |V155a|V156a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002582] 117.#80 V155 Use * Keep x0 |V155i|V156a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 118.#81 V149 Def Alloc x0 |V149a|V156a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002585] 121.#82 V156 Use * Keep x1 |V149a|V156i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 122.#83 V150 Def Alloc x1 |V149a|V150a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [001482] 124.#84 C148 Def Alloc x2 |V149a|V150a|C148a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [001487] 125.#85 C148 Use * Keep x2 |V149a|V150a|C148i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 126.#86 V43 Def Alloc x2 |V149a|V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 127.#87 BB5 PredBB1 |V147a|V148a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002589] 131.#88 V147 Use * Keep x0 |V147i|V148a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 132.#89 V149 Def Alloc x0 |V149a|V148a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002592] 135.#90 V148 Use * Keep x1 |V149a|V148i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 136.#91 V150 Def Alloc x1 |V149a|V150a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [000021] 138.#92 C149 Def Alloc x2 |V149a|V150a|C149a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [000026] 139.#93 C149 Use * Keep x2 |V149a|V150a|C149i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 140.#94 V43 Def Alloc x2 |V149a|V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 141.#95 BB6 PredBB3 |V149a|V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [004187] 145.#96 x0 Fixd Keep x0 |V149a|V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 145.#97 V149 Use * Keep x0 |V149i|V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 146.#98 x0 Fixd Keep x0 | |V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 146.#99 I150 Def Alloc x0 |I150a|V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [004188] 149.#100 x1 Fixd Keep x1 |I150a|V150a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 149.#101 V150 Use * Keep x1 |I150a|V150i|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 150.#102 x1 Fixd Keep x1 |I150a| |V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 150.#103 I151 Def Alloc x1 |I150a|I151a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [004189] 155.#104 x2 Fixd Keep x2 |I150a|I151a|V43 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 155.#105 V43 Use * Keep x2 |I150a|I151a|V43 i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 156.#106 x2 Fixd Keep x2 |I150a|I151a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 156.#107 I152 Def Alloc x2 |I150a|I151a|I152a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [002594] 158.#108 C153 Def Alloc x11 |I150a|I151a|I152a| | | | | | | | |C153a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [004190] 159.#109 x11 Fixd Keep x11 |I150a|I151a|I152a| | | | | | | | |C153a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 159.#110 C153 Use * Keep x11 |I150a|I151a|I152a| | | | | | | | |C153i| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 160.#111 x11 Fixd Keep x11 |I150a|I151a|I152a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 160.#112 I154 Def Alloc x11 |I150a|I151a|I152a| | | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [000030] 161.#113 I155 Def Alloc x3 |I150a|I151a|I152a|I155a| | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#114 x0 Fixd Keep x0 |I150a|I151a|I152a|I155a| | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#115 I150 Use * Keep x0 |I150i|I151a|I152a|I155a| | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#116 x1 Fixd Keep x1 | |I151a|I152a|I155a| | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#117 I151 Use * Keep x1 | |I151i|I152a|I155a| | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#118 x2 Fixd Keep x2 | | |I152a|I155a| | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#119 I152 Use * Keep x2 | | |I152i|I155a| | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#120 x11 Fixd Keep x11 | | | |I155a| | | | | | | |I154a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#121 I154 Use * Keep x11 | | | |I155a| | | | | | | |I154i| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 161.#122 I155 Use * Keep x3 | | | |I155i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#123 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#124 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#125 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#126 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#127 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#128 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#129 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#130 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#131 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#132 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#133 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#134 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#135 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#136 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#137 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#138 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#139 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#140 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#141 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#142 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 162.#143 I156 Def Alloc x0 |I156a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [000034] 163.#144 I156 Use * Keep x0 |I156i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 164.#145 V15 Def Alloc x26 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a| | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 165.#146 BB7 PredBB6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a| | | [000037] 172.#147 V4 Def Alloc x27 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a| | [000038] 176.#148 C157 Def Alloc x28 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|C157a| [000040] 177.#149 C157 Use * Keep x28 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|C157i| 178.#150 V5 Def Alloc x28 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000041] 182.#151 C158 Def Alloc x3 | | | |C158a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000043] 183.#152 C158 Use * Keep x3 | | | |C158i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 184.#153 V6 Def Alloc x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000046] 190.#154 V7 Def Alloc x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000049] 196.#155 V9 Def Alloc x5 | | | | | |V9 a| | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000050] 200.#156 C159 Def Alloc x6 | | | | | |V9 a|C159a| | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000052] 201.#157 C159 Use * Keep x6 | | | | | |V9 a|C159i| | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 202.#158 V10 Def Alloc x6 | | | | | |V9 a|V10 a| | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000055] 208.#159 V12 Def Alloc x7 | | | | | |V9 a|V10 a|V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000058] 214.#160 V13 Def Alloc x8 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000061] 219.#161 V15 Use Keep x26 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 220.#162 V16 Def Alloc x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002602] 225.#163 V180 Use Keep x24 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 226.#164 V157 Def Alloc x9 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V157a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000068] 231.#165 V157 Use Keep x9 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V157a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002608] 237.#166 V157 Use * Keep x9 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V157i| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 238.#167 V168 Def Alloc x9 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V168a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000072] 241.#168 V168 Use * Keep x9 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V168i| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 242.#169 V22 Def Alloc x9 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 243.#170 BB47 PredBB7 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000078] 251.#171 V16 Use Keep x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 251.#172 V179 Use Keep x25 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 255.#173 BB48 PredBB47 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001205] 261.#174 V16 Use * Keep x1 | |V16 i| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 262.#175 V71 Def Alloc x1 | |V71 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001201] 269.#176 V71 Use Keep x1 | |V71 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 270.#177 I160 Def Alloc x0 |I160a|V71 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001203] 271.#178 I160 Use * Keep x0 |I160i|V71 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 272.#179 V16 Def Alloc x10 | |V71 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001212] 285.#180 V22 Use Keep x9 | |V71 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 285.#181 V71 Use * Keep x1 | |V71 i| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 286.#182 I161 Def Alloc x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I161a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001214] 287.#183 I161 Use * Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I161i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 288.#184 V72 Def Alloc x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V72 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001218] 291.#185 V72 Use * Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V72 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 292.#186 V18 Def Alloc x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001220] 297.#187 V18 Use Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 299.#188 BB49 PredBB48 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001224] 307.#189 V18 Use Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 311.#190 BB8 PredBB49 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001228] 319.#191 V18 Use Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 323.#192 BB9 PredBB8 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001363] 331.#193 V18 Use Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 332.#194 I162 Def Alloc x14 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a|I162a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004192] 333.#195 I162 Use * Keep x14 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a|I162i| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 334.#196 V182 Def Alloc x14 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a|V182a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004196] 339.#197 V182 Use Keep x14 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a|V182a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 343.#198 BB10 PredBB9 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001367] 351.#199 V18 Use Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 352.#200 I163 Def Alloc x12 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |I163a|V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004203] 353.#201 I163 Use * Keep x12 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |I163i|V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 354.#202 V183 Def Alloc x12 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183a|V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004207] 359.#203 V183 Use Keep x12 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183a|V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 363.#204 BB11 PredBB10 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001371] 371.#205 V18 Use * Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 375.#206 BB12 PredBB11 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004366] 375.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 377.#207 BB13 PredBB8 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001232] 385.#208 V18 Use Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 389.#209 BB14 PredBB13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001259] 397.#210 V18 Use Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 401.#211 BB15 PredBB14 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001353] 408.#212 C164 Def Alloc x1 | |C164a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001354] 409.#213 V18 Use * Keep x13 | |C164a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 409.#214 C164 Use * Keep x1 | |C164i| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004310] 413.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 413.#215 BB16 PredBB7 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001358] 421.#216 V13 Use * Keep x8 | |V16 a| | | |V9 a|V10 a|V12 a|V13 i|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 422.#217 I165 Def Alloc x8 | |V16 a| | | |V9 a|V10 a|V12 a|I165a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001360] 423.#218 I165 Use * Keep x8 | |V16 a| | | |V9 a|V10 a|V12 a|I165i|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 424.#219 V13 Def Alloc x8 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 425.#220 BB35 PredBB13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001248] 447.#221 V22 Use Keep x9 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 447.#222 V16 Use Keep x10 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 448.#223 I166 Def Alloc x1 | |I166a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003645] 449.#224 I166 Use * Keep x1 | |I166i| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 450.#225 V174 Def Alloc x1 | |V174a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001240] 459.#226 V16 Use Keep x10 | |V174a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 459.#227 V179 Use Keep x25 | |V174a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 459.#228 V174 Use * Keep x1 | |V174i| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004319] 461.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 461.#229 BB36 PredBB7 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001254] 471.#230 V16 Use * Keep x1 | |V16 i| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 472.#231 I167 Def Alloc x1 | |I167a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001256] 473.#232 I167 Use * Keep x1 | |I167i| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 474.#233 V16 Def Alloc x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 475.#234 BB38 PredBB11 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001266] 483.#235 V16 Use Keep x10 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 483.#236 V179 Use Keep x25 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 487.#237 BB39 PredBB38 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001348] 503.#238 V22 Use Keep x9 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 503.#239 V16 Use Keep x10 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 504.#240 I168 Def Alloc x1 | |I168a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003649] 505.#241 I168 Use * Keep x1 | |I168i| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 506.#242 V174 Def Alloc x1 | |V174a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001350] 511.#243 V174 Use * Keep x1 | |V174i| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 515.#244 BB40 PredBB38 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001270] 523.#245 V16 Use Keep x10 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 524.#246 I169 Def Alloc x1 | |I169a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001275] 527.#247 I169 Use * Keep x1 | |I169i| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 527.#248 V179 Use Keep x25 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004321] 531.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 531.#249 BB41 PredBB7 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001284] 547.#250 V22 Use Keep x9 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 547.#251 V16 Use Keep x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 548.#252 I170 Def Alloc x0 |I170a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003653] 549.#253 I170 Use * Keep x0 |I170i|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 550.#254 V174 Def Alloc x0 |V174a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001286] 555.#255 V174 Use Keep x0 |V174a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 559.#256 BB42 PredBB41 |V174a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001339] 567.#257 V174 Use * Keep x0 |V174i|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 571.#258 BB43 PredBB41 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001291] 581.#259 V16 Use Keep x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 582.#260 I171 Def Alloc x0 |I171a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001297] 591.#261 V22 Use Keep x9 |I171a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 591.#262 I171 Use * Keep x0 |I171i|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 592.#263 I172 Def Alloc x0 |I172a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001299] 595.#264 I172 Use * Keep x0 |I172i|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001300] 599.#265 V9 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 599.#266 BB44 PredBB39 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001303] 607.#267 V16 Use * Keep x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 608.#268 I173 Def Alloc x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|I173a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001305] 609.#269 I173 Use * Keep x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|I173i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 610.#270 V73 Def Alloc x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|V73 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001309] 613.#271 V73 Use * Keep x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|V73 i| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 614.#272 V16 Def Alloc x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001314] 619.#273 V16 Use Keep x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 619.#274 V179 Use Keep x25 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 623.#275 BB45 PredBB44 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001326] 639.#276 V22 Use Keep x9 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 639.#277 V16 Use Keep x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 640.#278 I174 Def Alloc x5 | | | | | |I174a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001328] 643.#279 I174 Use * Keep x5 | | | | | |I174i|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 647.#280 BB46 PredBB44 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002613] 652.#281 C175 Def Alloc x5 | | | | | |C175a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001318] 653.#282 C175 Use * Keep x5 | | | | | |C175i|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 654.#283 V9 Def Alloc x5 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 655.#284 V16 ExpU | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 655.#285 V22 ExpU | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004379] 655.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 655.#286 BB50 PredBB47 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000086] 669.#287 V5 Use Keep x28 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 673.#288 BB51 PredBB50 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a| | [001196] 679.#289 V4 Use Keep x27 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a| | 680.#290 V5 Def Alloc x28 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 681.#291 BB52 PredBB50 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000090] 689.#292 V10 Use Keep x6 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 693.#293 BB53 PredBB52 | | | | | |V9 a|V10 a|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001182] 701.#294 V10 Use * Keep x6 | | | | | |V9 a|V10 i|V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 701.#295 V5 Use Keep x28 | | | | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 705.#296 BB54 PredBB53 | | | | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001189] 714.#297 C176 Def Alloc x1 | |C176a| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001191] 717.#298 V13 Use * Keep x8 | |C176a| | | |V9 a| |V12 a|V13 i| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 717.#299 V11 Use Keep x22 | |C176a| | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 717.#300 C176 Use * Keep x1 | |C176i| | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 718.#301 I177 Def Alloc x8 | | | | | |V9 a| |V12 a|I177a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001193] 719.#302 I177 Use * Keep x8 | | | | | |V9 a| |V12 a|I177i| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 720.#303 V13 Def Alloc x8 | | | | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 721.#304 BB55 PredBB53 | | | | | |V9 a| | |V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002615] 726.#305 C178 Def Alloc x7 | | | | | |V9 a| |C178a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001186] 727.#306 C178 Use * Keep x7 | | | | | |V9 a| |C178i|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 728.#307 V12 Def Alloc x7 | | | | | |V9 a| | |V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x7 | | | | | |V9 a| | |V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004380] 729.#0 V12 Move x7 | | | | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 729.#308 BB56 PredBB52 | | | | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000093] 735.#309 V17 Use Keep x23 | | | | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 736.#310 I179 Def Alloc x1 | |I179a| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000095] 739.#311 I179 Use * Keep x1 | |I179i| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 741.#312 BB57 PredBB56 | | | | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002620] 749.#313 V1 Use Keep x21 | | | | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 750.#314 I180 Def Alloc x1 | |I180a| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001129] 751.#315 I180 Use * Keep x1 | |I180i| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 752.#316 V69 Def Alloc x1 | |V69 a| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001132] 755.#317 V69 Use Keep x1 | |V69 a| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 756.#318 I181 Def Alloc x0 |I181a|V69 a| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001134] 759.#319 I181 Use * Keep x0 |I181i|V69 a| | | |V9 a| |V12 a|V13 a| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 759.#320 V13 Use * Keep x8 | |V69 a| | | |V9 a| |V12 a|V13 i| | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 760.#321 I182 Def Alloc x0 |I182a|V69 a| | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003850] 763.#322 V69 Use * Keep x1 |I182a|V69 i| | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 763.#323 I182 Use * Keep x0 |I182i| | | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001139] 771.#324 V9 Use Keep x5 | | | | | |V9 i| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x5 | | | | | |V9 i| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 773.#325 BB58 PredBB57 | | | | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001172] 781.#326 V1 Use Keep x21 | | | | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 782.#327 I183 Def Alloc x1 | |I183a| | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001174] 785.#328 I183 Use * Keep x1 | |I183i| | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 785.#329 V4 Use Keep x27 | | | | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 786.#330 I184 Def Alloc x1 | |I184a| | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001176] 789.#331 I184 Use * Keep x1 | |I184i| | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 789.#332 V5 Use Keep x28 | | | | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 790.#333 I185 Def Alloc x1 | |I185a| | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001178] 791.#334 I185 Use * Keep x1 | |I185i| | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 792.#335 V70 Def Alloc x1 | |V70 a| | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004381] 793.#0 V12 Move STK | |V70 a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 793.#336 BB59 PredBB57 | | | | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001143] 799.#337 V4 Use Keep x27 | | | | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 800.#338 V70 Def Alloc x1 | |V70 a| | | | | |V12 a| | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004382] 801.#0 V12 Move STK | |V70 a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 801.#339 BB60 PredBB58 | |V70 a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004213] 807.#340 x1 Fixd Keep x1 | |V70 a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 807.#341 V70 Use * Keep x1 | |V70 i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 808.#342 x1 Fixd Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 808.#343 I186 Def Alloc x1 | |I186a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004214] 811.#344 x0 Fixd Keep x0 | |I186a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 811.#345 V1 Use Copy x0 |V1 a|I186a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 812.#346 x0 Fixd Keep x0 | |I186a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 812.#347 I187 Def Alloc x0 |I187a|I186a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002624] 814.#348 C188 Def Alloc x11 |I187a|I186a| | | | | | | | | |C188a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004215] 815.#349 x11 Fixd Keep x11 |I187a|I186a| | | | | | | | | |C188a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 815.#350 C188 Use * Keep x11 |I187a|I186a| | | | | | | | | |C188i| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 816.#351 x11 Fixd Keep x11 |I187a|I186a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 816.#352 I189 Def Alloc x11 |I187a|I186a| | | | | | | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001150] 818.#353 C190 Def Alloc x2 |I187a|I186a|C190a| | | | | | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004216] 819.#354 x2 Fixd Keep x2 |I187a|I186a|C190a| | | | | | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 819.#355 C190 Use * Keep x2 |I187a|I186a|C190i| | | | | | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 820.#356 x2 Fixd Keep x2 |I187a|I186a| | | | | | | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 820.#357 I191 Def Alloc x2 |I187a|I186a|I191a| | | | | | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001151] 821.#358 I192 Def Alloc x6 |I187a|I186a|I191a| | | |I192a| | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#359 x1 Fixd Keep x1 |I187a|I186a|I191a| | | |I192a| | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#360 I186 Use * Keep x1 |I187a|I186i|I191a| | | |I192a| | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#361 x0 Fixd Keep x0 |I187a| |I191a| | | |I192a| | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#362 I187 Use * Keep x0 |I187i| |I191a| | | |I192a| | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#363 x11 Fixd Keep x11 | | |I191a| | | |I192a| | | | |I189a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#364 I189 Use * Keep x11 | | |I191a| | | |I192a| | | | |I189i| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#365 x2 Fixd Keep x2 | | |I191a| | | |I192a| | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#366 I191 Use * Keep x2 | | |I191i| | | |I192a| | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 821.#367 I192 Use * Keep x6 | | | | | | |I192i| | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#368 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#369 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#370 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#371 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#372 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#373 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#374 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#375 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#376 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#377 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#378 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#379 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#380 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#381 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#382 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#383 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#384 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#385 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 822.#386 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001153] 827.#387 V17 Use Keep x23 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 828.#388 I193 Def Alloc x0 |I193a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001155] 831.#389 I193 Use * Keep x0 |I193i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 833.#390 BB61 PredBB60 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004217] 839.#391 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 839.#392 V180 Use Copy x0 |V180a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 840.#393 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 840.#394 I194 Def Alloc x0 |I194a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002628] 842.#395 I195 Def Alloc x1 |I194a|I195a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004218] 843.#396 x1 Fixd Keep x1 |I194a|I195a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 843.#397 I195 Use * Keep x1 |I194a|I195i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 844.#398 x1 Fixd Keep x1 |I194a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 844.#399 I196 Def Alloc x1 |I194a|I196a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002625] 848.#400 C197 Def Alloc x11 |I194a|I196a| | | | | | | | | |C197a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004219] 849.#401 x11 Fixd Keep x11 |I194a|I196a| | | | | | | | | |C197a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 849.#402 C197 Use * Keep x11 |I194a|I196a| | | | | | | | | |C197i| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 850.#403 x11 Fixd Keep x11 |I194a|I196a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 850.#404 I198 Def Alloc x11 |I194a|I196a| | | | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001158] 852.#405 C199 Def Alloc x2 |I194a|I196a|C199a| | | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004220] 853.#406 x2 Fixd Keep x2 |I194a|I196a|C199a| | | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 853.#407 C199 Use * Keep x2 |I194a|I196a|C199i| | | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 854.#408 x2 Fixd Keep x2 |I194a|I196a| | | | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 854.#409 I200 Def Alloc x2 |I194a|I196a|I200a| | | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001159] 855.#410 I201 Def Alloc x3 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#411 x0 Fixd Keep x0 |I194a|I196a|I200a|I201a| | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#412 I194 Use * Keep x0 |I194i|I196a|I200a|I201a| | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#413 x1 Fixd Keep x1 | |I196a|I200a|I201a| | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#414 I196 Use * Keep x1 | |I196i|I200a|I201a| | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#415 x11 Fixd Keep x11 | | |I200a|I201a| | | | | | | |I198a| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#416 I198 Use * Keep x11 | | |I200a|I201a| | | | | | | |I198i| | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#417 x2 Fixd Keep x2 | | |I200a|I201a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#418 I200 Use * Keep x2 | | |I200i|I201a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 855.#419 I201 Use * Keep x3 | | | |I201i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#420 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#421 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#422 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#423 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#424 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#425 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#426 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#427 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#428 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#429 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#430 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#431 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#432 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#433 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#434 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#435 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#436 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#437 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#438 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#439 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 856.#440 I202 Def Alloc x0 |I202a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001163] 857.#441 I202 Use * Keep x0 |I202i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 858.#442 V16 Def Alloc x1 | |V16 a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001166] 865.#443 V16 Use Keep x1 | |V16 a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 865.#444 V15 Use Keep x26 | |V16 a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 869.#445 BB62 PredBB61 | |V16 a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | [001170] 875.#446 V16 Use * Keep x1 | |V16 i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a| | | | 876.#447 V15 Def Alloc x26 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a| | | 877.#448 V11 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a| | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 877.#449 BB63 PredBB56 | | | | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000098] 885.#450 V1 Use Keep x21 | | | | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 886.#451 I203 Def Alloc x1 | |I203a| | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000100] 889.#452 I203 Use * Keep x1 | |I203i| | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 893.#453 BB64 PredBB63 | | | | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003861] 903.#454 V1 Use Keep x21 | | | | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 905.#455 BB65 PredBB63 | | | | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003863] 915.#456 V1 Use Keep x21 | | | | | |V9 a| |V12 a| | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004383] 917.#0 V12 Move STK | | | | | |V9 a| | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004384] 917.#0 V9 Move STK | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 917.#457 BB66 PredBB60 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000112] 933.#458 V5 Use Keep x28 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 933.#459 V6 Use ReLod x3 | | | |V6 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | |V6 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 934.#460 I204 Def Alloc x0 |I204a| | |V6 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003777] 937.#461 V6 Use * Keep x3 |I204a| | |V6 i| | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 937.#462 V5 Use Keep x28 |I204a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 937.#463 I204 Use * Keep x0 |I204i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 938.#464 I205 Def Alloc x3 | | | |I205a| | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001120] 939.#465 I205 Use * Keep x3 | | | |I205i| | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 940.#466 V44 Def Alloc x3 | | | |V44 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000118] 945.#467 V44 Use * Keep x3 | | | |V44 i| | | | | | | | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 946.#468 V6 Def Alloc x22 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000125] 961.#469 V5 Use Keep x28 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 961.#470 V7 Use ReLod x4 | | | | |V7 a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | | |V7 a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 962.#471 I206 Def Alloc x0 |I206a| | | |V7 a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003774] 965.#472 V7 Use * Keep x4 |I206a| | | |V7 i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 965.#473 V5 Use Keep x28 |I206a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 965.#474 I206 Use * Keep x0 |I206i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 966.#475 I207 Def Alloc x4 | | | | |I207a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001116] 967.#476 I207 Use * Keep x4 | | | | |I207i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 968.#477 V45 Def Alloc x4 | | | | |V45 a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000131] 973.#478 V45 Use * Keep x4 | | | | |V45 i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 974.#479 V7 Def Alloc x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000134] 981.#480 V9 Use ReLod x5 | | | | | |V9 a| | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x5 | | | | | |V9 i| | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x5 | | | | | |V9 i| | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 983.#481 BB73 PredBB66 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001110] 989.#482 V5 Use Keep x28 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 990.#483 V8 Def Alloc x2 | | |V8 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001113] 996.#484 V14 Def Alloc x3 | | |V8 a|V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 997.#485 BB74 PredBB66 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000137] 1007.#486 V1 Use Keep x21 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1008.#487 I208 Def Alloc x3 | | | |I208a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003683] 1009.#488 I208 Use * Keep x3 | | | |I208i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1010.#489 V178 Def Alloc x3 | | | |V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003771] 1021.#490 V178 Use Keep x3 | | | |V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1021.#491 V5 Use Keep x28 | | | |V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1021.#492 V178 Use Keep x3 | | | |V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1021.#493 V5 Use Keep x28 | | | |V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1022.#494 I209 Def Alloc x2 | | |I209a|V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001106] 1023.#495 I209 Use * Keep x2 | | |I209i|V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1024.#496 V46 Def Alloc x2 | | |V46 a|V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000148] 1029.#497 V46 Use * Keep x2 | | |V46 i|V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1030.#498 V8 Def Alloc x2 | | |V8 a|V178a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000152] 1037.#499 V178 Use * Keep x3 | | |V8 a|V178i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1037.#500 V5 Use Keep x28 | | |V8 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1038.#501 I210 Def Alloc x3 | | |V8 a|I210a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000154] 1039.#502 I210 Use * Keep x3 | | |V8 a|I210i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1040.#503 V14 Def Alloc x3 | | |V8 a|V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1041.#504 BB78 PredBB73 | | |V8 a|V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000157] 1047.#505 V15 Use Keep x26 | | |V8 a|V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1048.#506 V16 Def Alloc x4 | | |V8 a|V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x4 | | |V8 a|V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001550] 1054.#507 I211 Def Alloc x6 | | |V8 a|V14 a| | |I211a| | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001553] 1055.#508 I211 Use * Keep x6 | | |V8 a|V14 a| | |I211i| | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1056.#509 V151 Def Alloc x6 | | |V8 a|V14 a| | |V151a| | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002650] 1063.#510 V151 Use * Keep x6 | | |V8 a|V14 a| | |V151i| | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1064.#511 V143 Def Alloc x6 | | |V8 a|V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x6 | | |V8 a|V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003720] 1066.#512 C212 Def Alloc x8 | | |V8 a|V14 a| | | | |C212a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002653] 1067.#513 C212 Use * Keep x8 | | |V8 a|V14 a| | | | |C212i| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1068.#514 V144 Def Alloc x8 | | |V8 a|V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000175] 1072.#515 C213 Def Alloc x9 | | |V8 a|V14 a| | | | |V144a|C213a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000177] 1073.#516 C213 Use * Keep x9 | | |V8 a|V14 a| | | | |V144a|C213i| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1074.#517 V20 Def Alloc x9 | | |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001570] 1081.#518 V3 Use Keep x20 | | |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1082.#519 I214 Def Alloc x0 |I214a| |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000944] 1085.#520 I214 Use * Keep x0 |I214i| |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1086.#521 I215 Def Alloc x0 |I215a| |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000181] 1099.#522 I215 Use * Keep x0 |I215i| |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1099.#523 V12 Use ReLod x7 | | |V8 a|V14 a| | | |V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x7 | | |V8 a|V14 a| | | |V12 i|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x7 | | |V8 a|V14 a| | | |V12 i|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1101.#524 BB79 PredBB78 | | |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000949] 1111.#525 V3 Use Keep x20 | | |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1112.#526 I216 Def Alloc x10 | | |V8 a|V14 a| | | | |V144a|V20 a|I216a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000951] 1113.#527 I216 Use * Keep x10 | | |V8 a|V14 a| | | | |V144a|V20 a|I216i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1114.#528 V26 Def Alloc x10 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000954] 1120.#529 V27 Def Alloc x13 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x13 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000957] 1126.#530 V28 Def Alloc x14 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000959] 1133.#531 V26 Use Keep x10 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1134.#532 I217 Def Alloc x12 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| |I217a| |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000961] 1135.#533 I217 Use * Keep x12 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| |I217i| |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1136.#534 V29 Def Alloc x12 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| |V29 a| |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000964] 1143.#535 V29 Use Keep x12 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| |V29 i| |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x12 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| |V29 i| |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1145.#536 BB81 PredBB79 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002671] 1153.#537 V26 Use Keep x10 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x10 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1154.#538 I218 Def Alloc x14 | | |V8 a|V14 a| | | | |V144a|V20 a| | | | |I218a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001103] 1155.#539 I218 Use * Keep x14 | | |V8 a|V14 a| | | | |V144a|V20 a| | | | |I218i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1156.#540 V28 Def Alloc x14 | | |V8 a|V14 a| | | | |V144a|V20 a| | | | |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004385] 1157.#0 V26 Move x10 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1157.#541 BB82 PredBB79 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000968] 1163.#542 V28 Use Keep x14 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | |V28 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x14 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | |V28 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1164.#543 V30 Def Alloc x15 | | |V8 a|V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000975] 1167.#544 V8 Use Keep x2 | | |V8 i|V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x2 | | |V8 i|V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1168.#545 V64 Def Alloc x0 |V64 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000972] 1175.#546 V14 Use Keep x3 |V64 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1179.#547 BB83 PredBB82 |V64 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001093] 1183.#548 V64 Use * Keep x0 |V64 i| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1184.#549 V65 Def Alloc x0 |V65 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001096] 1188.#550 V66 Def Alloc x11 |V65 a| | |V14 a| | | | |V144a|V20 a|V26 a|V66 a| | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1189.#551 BB84 PredBB82 |V64 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000981] 1193.#552 V64 Use * Keep x0 |V64 i| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1194.#553 V65 Def Alloc x0 |V65 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000984] 1197.#554 V14 Use Keep x3 |V65 a| | |V14 i| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x3 |V65 a| | |V14 i| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1198.#555 V66 Def Alloc x11 |V65 a| | | | | | | |V144a|V20 a|V26 a|V66 a| | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004386] 1199.#0 V14 Move x3 |V65 a| | |V14 a| | | | |V144a|V20 a|V26 a|V66 a| | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1199.#556 BB85 PredBB83 |V65 a| | |V14 a| | | | |V144a|V20 a|V26 a|V66 a| | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000988] 1205.#557 V65 Use * Keep x0 |V65 i| | |V14 a| | | | |V144a|V20 a|V26 a|V66 a| | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1205.#558 V66 Use * Keep x11 | | | |V14 a| | | | |V144a|V20 a|V26 a|V66 i| | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1206.#559 I219 Def Alloc x0 |I219a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000990] 1207.#560 I219 Use * Keep x0 |I219i| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1208.#561 V31 Def Alloc x0 |V31 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003768] 1223.#562 V6 Use Keep x22 |V31 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1223.#563 V31 Use Keep x0 |V31 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1223.#564 V6 Use Keep x22 |V31 a| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1223.#565 V31 Use * Keep x0 |V31 i| | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1224.#566 I220 Def Alloc xip0 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a|I220a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001089] 1225.#567 I220 Use * Keep xip0 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a|I220i|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1226.#568 V67 Def Alloc xip0 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a|V67 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001001] 1231.#569 V67 Use * Keep xip0 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a|V67 i|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1232.#570 V32 Def Alloc xip0 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003157] 1239.#571 V32 Use Keep xip0 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a|V32 i|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill xip0 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a|V32 i|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1239.#572 V30 Use Keep x15 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1243.#573 BB89 PredBB85 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001008] 1251.#574 V30 Use Keep x15 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 i| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x15 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 i| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1253.#575 BB90 PredBB89 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001012] 1261.#576 V20 Use * Keep x9 | | | |V14 a| | | | |V144a|V20 i|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1262.#577 I221 Def Alloc x9 | | | |V14 a| | | | |V144a|I221a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001014] 1263.#578 I221 Use * Keep x9 | | | |V14 a| | | | |V144a|I221i|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1264.#579 V20 Def Alloc x9 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001020] 1271.#580 V20 Use Keep x9 | | | |V14 a| | | | |V144a|V20 i|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x9 | | | |V14 a| | | | |V144a|V20 i|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1271.#581 V144 Use Keep x8 | | | |V14 a| | | | |V144a| |V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1275.#582 BB91 PredBB90 | | | |V14 a| | | | |V144a| |V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004387] 1275.#0 V14 Move STK | | | | | | | | |V144a| |V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004388] 1275.#0 V26 Move STK | | | | | | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001066] 1283.#583 V144 Use Keep x8 | | | | | | | | |V144i| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x8 | | | | | | | | |V144i| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1284.#584 I222 Def Alloc x0 |I222a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001067] 1285.#585 I222 Use * Keep x0 |I222i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1286.#586 I223 Def Alloc x0 |I223a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004221] 1287.#587 x0 Fixd Keep x0 |I223a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1287.#588 I223 Use * Keep x0 |I223i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1288.#589 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1288.#590 I224 Def Alloc x0 |I224a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002672] 1290.#591 C225 Def Alloc x11 |I224a| | | | | | | | | | |C225a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004222] 1291.#592 x11 Fixd Keep x11 |I224a| | | | | | | | | | |C225a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1291.#593 C225 Use * Keep x11 |I224a| | | | | | | | | | |C225i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1292.#594 x11 Fixd Keep x11 |I224a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1292.#595 I226 Def Alloc x11 |I224a| | | | | | | | | | |I226a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001068] 1293.#596 I227 Def Alloc x12 |I224a| | | | | | | | | | |I226a|I227a| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#597 x0 Fixd Keep x0 |I224a| | | | | | | | | | |I226a|I227a| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#598 I224 Use * Keep x0 |I224i| | | | | | | | | | |I226a|I227a| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#599 x11 Fixd Keep x11 | | | | | | | | | | | |I226a|I227a| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#600 I226 Use * Keep x11 | | | | | | | | | | | |I226i|I227a| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1293.#601 I227 Use * Keep x12 | | | | | | | | | | | | |I227i| | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#602 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#603 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#604 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#605 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#606 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#607 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#608 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#609 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#610 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#611 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#612 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#613 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#614 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#615 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#616 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#617 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#618 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#619 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#620 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#621 x0 Fixd Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1294.#622 I228 Def Alloc x0 |I228a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001070] 1295.#623 I228 Use * Keep x0 |I228i| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1296.#624 V33 Def Alloc x3 | | | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002691] 1305.#625 V33 Use Keep x3 | | | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1306.#626 I229 Def Alloc x0 |I229a| | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001604] 1307.#627 I229 Use * Keep x0 |I229i| | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1308.#628 V159 Def Alloc x0 |V159a| | |V33 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001608] 1315.#629 V33 Use Keep x3 |V159a| | |V33 i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x3 |V159a| | |V33 i| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1316.#630 I230 Def Alloc x2 |V159a| |I230a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001610] 1317.#631 I230 Use * Keep x2 |V159a| |I230i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1318.#632 V160 Def Alloc x2 |V159a| |V160a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002695] 1321.#633 V159 Use * Keep x0 |V159i| |V160a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1322.#634 V161 Def Alloc x0 |V161a| |V160a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001628] 1327.#635 V144 Use ReLod x4 |V161a| |V160a| |V144a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x4 |V161a| |V160a| |V144a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1327.#636 V160 Use * Keep x2 |V161a| |V160i| |V144a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1331.#637 BB95 PredBB91 |V161a| | | |V144a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001640] 1337.#638 V144 Use * Keep x4 |V161a| | | |V144i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1338.#639 I231 Def Alloc x2 |V161a| |I231a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001673] 1339.#640 I231 Use * Keep x2 |V161a| |I231i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1340.#641 V83 Def Alloc x2 |V161a| |V83 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001666] 1347.#642 V83 Use * Keep x2 |V161a| |V83 i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1348.#643 I232 Def Alloc x2 |V161a| |I232a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004223] 1349.#644 x2 Fixd Keep x2 |V161a| |I232a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1349.#645 I232 Use * Keep x2 |V161a| |I232i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1350.#646 x2 Fixd Keep x2 |V161a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1350.#647 I233 Def Alloc x2 |V161a| |I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004224] 1353.#648 x0 Fixd Keep x0 |V161a| |I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1353.#649 V161 Use * Keep x0 |V161i| |I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1354.#650 x0 Fixd Keep x0 | | |I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1354.#651 I234 Def Alloc x0 |I234a| |I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004225] 1357.#652 x1 Fixd Keep x1 |I234a| |I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1357.#653 V143 Use * ReLod x1 |I234a|V143a|I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x1 |I234a|V143i|I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1358.#654 x1 Fixd Keep x1 |I234a| |I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1358.#655 I235 Def Alloc x1 |I234a|I235a|I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002700] 1360.#656 C236 Def Alloc x11 |I234a|I235a|I233a| | | | | | | | |C236a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004226] 1361.#657 x11 Fixd Keep x11 |I234a|I235a|I233a| | | | | | | | |C236a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1361.#658 C236 Use * Keep x11 |I234a|I235a|I233a| | | | | | | | |C236i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1362.#659 x11 Fixd Keep x11 |I234a|I235a|I233a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1362.#660 I237 Def Alloc x11 |I234a|I235a|I233a| | | | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001667] 1363.#661 I238 Def Alloc x4 |I234a|I235a|I233a| |I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#662 x2 Fixd Keep x2 |I234a|I235a|I233a| |I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#663 I233 Use * Keep x2 |I234a|I235a|I233i| |I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#664 x0 Fixd Keep x0 |I234a|I235a| | |I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#665 I234 Use * Keep x0 |I234i|I235a| | |I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#666 x1 Fixd Keep x1 | |I235a| | |I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#667 I235 Use * Keep x1 | |I235i| | |I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#668 x11 Fixd Keep x11 | | | | |I238a| | | | | | |I237a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#669 I237 Use * Keep x11 | | | | |I238a| | | | | | |I237i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1363.#670 I238 Use * Keep x4 | | | | |I238i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#671 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#672 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#673 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#674 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#675 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#676 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#677 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#678 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#679 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#680 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#681 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#682 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#683 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#684 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#685 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#686 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#687 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#688 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1364.#689 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002720] 1373.#690 V33 Use ReLod x0 |V33 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x0 |V33 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1374.#691 I239 Def Alloc x1 |V33 a|I239a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001716] 1375.#692 I239 Use * Keep x1 |V33 a|I239i| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1376.#693 V163 Def Alloc x1 |V33 a|V163a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001720] 1383.#694 V33 Use * Keep x0 |V33 i|V163a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1384.#695 I240 Def Alloc x4 | |V163a| | |I240a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001722] 1385.#696 I240 Use * Keep x4 | |V163a| | |I240i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1386.#697 V164 Def Alloc x4 | |V163a| | |V164a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002724] 1391.#698 V163 Use * Keep x1 | |V163i| | |V164a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1392.#699 V143 Def Alloc x2 | | |V143a| |V164a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002727] 1395.#700 V164 Use * Keep x4 | | |V143a| |V164i| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1396.#701 V144 Def Alloc x3 | | |V143a|V144a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004389] 1397.#0 V143 Move STK | | | |V144a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004391] 1397.#0 V144 Move x8 | | | | | | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004392] 1397.#0 V14 Move x3 | | | |V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004393] 1397.#0 V26 Move x10 | | | |V14 a| | | | |V144a| |V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1397.#702 BB100 PredBB90 | | | |V14 a| | | | |V144a| |V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001029] 1405.#703 V20 Use ReLod x9 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x9 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1405.#704 V144 Use Keep x8 | | | |V14 a| | | | |V144i|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x8 | | | |V14 a| | | | |V144i|V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003911] 1421.#705 V143 Use ReLod x6 | | | |V14 a| | |V143a| | |V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x6 | | | |V14 a| | |V143i| | |V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x6 | | | |V14 a| | |V143i| | |V20 a|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1421.#706 V20 Use Keep x9 | | | |V14 a| | | | | |V20 i|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x9 | | | |V14 a| | | | | |V20 i|V26 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1421.#707 V28 Use ReLod x14 | | | |V14 a| | | | | | |V26 a| | | |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x14 | | | |V14 a| | | | | | |V26 a| | | |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001042] 1431.#708 V29 Use ReLod x12 | | | |V14 a| | | | | | |V26 a| |V29 a| |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x12 | | | |V14 a| | | | | | |V26 a| |V29 a| |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1432.#709 I241 Def Alloc x0 |I241a| | |V14 a| | | | | | |V26 a| |V29 a| |V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001043] 1433.#710 V27 Use ReLod x13 |I241a| | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x13 |I241a| | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1433.#711 I241 Use * Keep x0 |I241i| | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1437.#712 BB101 PredBB100 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001052] 1445.#713 V27 Use * Keep x13 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 i|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1446.#714 I242 Def Alloc x13 | | | |V14 a| | | | | | |V26 a| |V29 a|I242a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001054] 1447.#715 I242 Use * Keep x13 | | | |V14 a| | | | | | |V26 a| |V29 a|I242i|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1448.#716 V27 Def Alloc x13 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002732] 1457.#717 V26 Use Keep x10 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1458.#718 I243 Def Alloc x15 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|I243a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002733] 1459.#719 V27 Use Keep x13 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|I243a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1459.#720 I243 Use * Keep x15 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|I243i| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002738] 1465.#721 V26 Use Keep x10 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1466.#722 I244 Def Alloc x0 |I244a| | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002742] 1477.#723 I244 Use * Keep x0 |I244i| | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1477.#724 V27 Use Keep x13 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1478.#725 I245 Def Alloc x15 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|I245a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001060] 1479.#726 I245 Use * Keep x15 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|I245i| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1480.#727 V30 Def Alloc x0 |V30 a| | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004394] 1481.#0 V30 Move STK | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1481.#728 BB102 PredBB100 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001047] 1489.#729 V28 Use * Keep x14 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1489.#730 V30 Use ReLod x15 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a| |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x15 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a| |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1490.#731 I246 Def Alloc x14 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|I246a|V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001049] 1491.#732 I246 Use * Keep x14 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|I246i|V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1492.#733 V28 Def Alloc x14 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001004] 1499.#734 V32 Use ReLod xip0 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep xip0 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1499.#735 V28 Use Keep x14 | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001005] 1503.#736 V28 ExpU | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#737 V27 ExpU | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#738 V30 ExpU | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#739 V26 ExpU | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#740 V29 ExpU | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1503.#741 V32 ExpU | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a|V28 a|V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004325] 1503.#0 V28 Move STK | | | |V14 a| | | | | | |V26 a| |V29 a|V27 a| |V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004326] 1503.#0 V27 Move STK | | | |V14 a| | | | | | |V26 a| |V29 a| | |V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004327] 1503.#0 V29 Move STK | | | |V14 a| | | | | | |V26 a| | | | |V30 a|V32 a|V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004328] 1503.#0 V32 Move STK | | | |V14 a| | | | | | |V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004329] 1503.#0 V144 Move x8 | | | |V14 a| | | | |V144a| |V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004330] 1503.#0 V20 Move x9 | | | |V14 a| | | | |V144a|V20 a|V26 a| | | | |V30 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1503.#742 BB103 PredBB89 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000183] 1511.#743 V1 Use Keep x21 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1512.#744 I247 Def Alloc x0 |I247a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000186] 1525.#745 I247 Use * Keep x0 |I247i| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1525.#746 V16 Use ReLod x4 | | | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x4 | | | |V14 a|V16 i| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x4 | | | |V14 a|V16 i| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1527.#747 BB104 PredBB103 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000932] 1537.#748 V1 Use Keep x21 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1538.#749 I248 Def Alloc x0 |I248a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000934] 1541.#750 I248 Use * Keep x0 |I248i| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1543.#751 BB106 PredBB104 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001730] 1551.#752 V3 Use Keep x20 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1552.#753 I249 Def Alloc x11 | | | |V14 a| | | | |V144a|V20 a| |I249a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001783] 1553.#754 I249 Use * Keep x11 | | | |V14 a| | | | |V144a|V20 a| |I249i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1554.#755 V86 Def Alloc x11 | | | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001734] 1561.#756 V86 Use Keep x11 | | | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1563.#757 BB107 PredBB106 | | | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001736] 1571.#758 V0 Use Keep x19 | | | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1572.#759 I250 Def Alloc x0 |I250a| | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001738] 1573.#760 I250 Use * Keep x0 |I250i| | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1574.#761 V87 Def Alloc x0 |V87 a| | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001740] 1581.#762 V86 Use Keep x11 |V87 a| | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1582.#763 I251 Def Alloc x10 |V87 a| | |V14 a| | | | |V144a|V20 a|I251a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001786] 1593.#764 V0 Use Keep x19 |V87 a| | |V14 a| | | | |V144a|V20 a|I251a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1594.#765 I252 Def Alloc x13 |V87 a| | |V14 a| | | | |V144a|V20 a|I251a|V86 a| |I252a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001743] 1599.#766 I251 Use * Keep x10 |V87 a| | |V14 a| | | | |V144a|V20 a|I251i|V86 a| |I252a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1599.#767 V87 Use Keep x0 |V87 a| | |V14 a| | | | |V144a|V20 a| |V86 a| |I252a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1599.#768 I252 Use * Keep x13 |V87 a| | |V14 a| | | | |V144a|V20 a| |V86 a| |I252i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1601.#769 BB108 PredBB107 |V87 a| | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002760] 1611.#770 V0 Use Keep x19 |V87 a| | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1612.#771 I253 Def Alloc x10 |V87 a| | |V14 a| | | | |V144a|V20 a|I253a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001759] 1613.#772 I253 Use * Keep x10 |V87 a| | |V14 a| | | | |V144a|V20 a|I253i|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1614.#773 V88 Def Alloc x10 |V87 a| | |V14 a| | | | |V144a|V20 a|V88 a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001762] 1623.#774 V88 Use Keep x10 |V87 a| | |V14 a| | | | |V144a|V20 a|V88 a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1624.#775 I254 Def Alloc x13 |V87 a| | |V14 a| | | | |V144a|V20 a|V88 a|V86 a| |I254a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001763] 1625.#776 V87 Use Keep x0 |V87 a| | |V14 a| | | | |V144a|V20 a|V88 a|V86 a| |I254a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1625.#777 I254 Use * Keep x13 |V87 a| | |V14 a| | | | |V144a|V20 a|V88 a|V86 a| |I254i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001767] 1629.#778 V88 Use * Keep x10 |V87 a| | |V14 a| | | | |V144a|V20 a|V88 i|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1630.#779 I255 Def Alloc x10 |V87 a| | |V14 a| | | | |V144a|V20 a|I255a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001766] 1637.#780 V87 Use Keep x0 |V87 a| | |V14 a| | | | |V144a|V20 a|I255a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1638.#781 I256 Def Alloc x13 |V87 a| | |V14 a| | | | |V144a|V20 a|I255a|V86 a| |I256a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001768] 1639.#782 I255 Use * Keep x10 |V87 a| | |V14 a| | | | |V144a|V20 a|I255i|V86 a| |I256a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1639.#783 I256 Use * Keep x13 |V87 a| | |V14 a| | | | |V144a|V20 a| |V86 a| |I256i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1640.#784 I257 Def Alloc x10 |V87 a| | |V14 a| | | | |V144a|V20 a|I257a|V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002777] 1645.#785 V86 Use * Keep x11 |V87 a| | |V14 a| | | | |V144a|V20 a|I257a|V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1646.#786 I258 Def Alloc x11 |V87 a| | |V14 a| | | | |V144a|V20 a|I257a|I258a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003927] 1647.#787 I257 Use * Keep x10 |V87 a| | |V14 a| | | | |V144a|V20 a|I257i|I258a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1647.#788 I258 Use * Keep x11 |V87 a| | |V14 a| | | | |V144a|V20 a| |I258i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001779] 1655.#789 V87 Use * Keep x0 |V87 i| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1656.#790 I259 Def Alloc x0 |I259a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003929] 1661.#791 V0 Use Keep x19 |I259a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1661.#792 I259 Use * Keep x0 |I259i| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1663.#793 BB111 PredBB107 | | | |V14 a| | | | |V144a|V20 a| |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004395] 1663.#0 V20 Move STK | | | |V14 a| | | | |V144a| | |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004396] 1663.#0 V14 Move STK | | | | | | | | |V144a| | |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004397] 1663.#0 V144 Move STK | | | | | | | | | | | |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004231] 1669.#794 x0 Fixd Keep x0 | | | | | | | | | | | |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1669.#795 V0 Use Copy x0 |V0 a| | | | | | | | | | |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1670.#796 x0 Fixd Keep x0 | | | | | | | | | | | |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1670.#797 I260 Def Alloc x0 |I260a| | | | | | | | | | |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004232] 1673.#798 x1 Fixd Keep x1 |I260a| | | | | | | | | | |V86 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1673.#799 V86 Use * Copy x1 |I260a|V86 i| | | | | | | | | |V86 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1674.#800 x1 Fixd Keep x1 |I260a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1674.#801 I261 Def Alloc x1 |I260a|I261a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002780] 1676.#802 C262 Def Alloc x11 |I260a|I261a| | | | | | | | | |C262a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004233] 1677.#803 x11 Fixd Keep x11 |I260a|I261a| | | | | | | | | |C262a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1677.#804 C262 Use * Keep x11 |I260a|I261a| | | | | | | | | |C262i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1678.#805 x11 Fixd Keep x11 |I260a|I261a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1678.#806 I263 Def Alloc x11 |I260a|I261a| | | | | | | | | |I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001746] 1679.#807 I264 Def Alloc x10 |I260a|I261a| | | | | | | | |I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#808 x0 Fixd Keep x0 |I260a|I261a| | | | | | | | |I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#809 I260 Use * Keep x0 |I260i|I261a| | | | | | | | |I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#810 x1 Fixd Keep x1 | |I261a| | | | | | | | |I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#811 I261 Use * Keep x1 | |I261i| | | | | | | | |I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#812 x11 Fixd Keep x11 | | | | | | | | | | |I264a|I263a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#813 I263 Use * Keep x11 | | | | | | | | | | |I264a|I263i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1679.#814 I264 Use * Keep x10 | | | | | | | | | | |I264i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#815 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#816 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#817 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#818 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#819 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#820 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#821 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#822 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#823 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#824 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#825 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#826 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#827 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#828 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#829 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#830 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#831 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#832 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 1680.#833 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004398] 1681.#0 V14 Move x3 | | | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004399] 1681.#0 V144 Move x8 | | | |V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004400] 1681.#0 V20 Move x9 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1681.#834 BB112 PredBB103 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [000189] 1688.#835 V21 Def Alloc x10 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x10 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002784] 1693.#836 V180 Use * Keep x24 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180i|V179a|V15 a|V4 a|V5 a| 1694.#837 V165 Def Alloc x24 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V165a|V179a|V15 a|V4 a|V5 a| [000196] 1699.#838 V165 Use Keep x24 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V165a|V179a|V15 a|V4 a|V5 a| [002790] 1705.#839 V165 Use * Keep x24 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V165i|V179a|V15 a|V4 a|V5 a| 1706.#840 V169 Def Alloc x24 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V169a|V179a|V15 a|V4 a|V5 a| [000200] 1709.#841 V169 Use * Keep x24 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V169i|V179a|V15 a|V4 a|V5 a| 1710.#842 V34 Def Alloc x24 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000203] 1715.#843 V17 Use Keep x23 | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1716.#844 V36 Def Alloc x0 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1717.#845 BB245 PredBB112 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000209] 1725.#846 V16 Use ReLod x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1725.#847 V179 Use Keep x25 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1729.#848 BB246 PredBB245 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000250] 1735.#849 V16 Use * Keep x4 |V36 a| | |V14 a|V16 i| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1736.#850 V49 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000246] 1743.#851 V49 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1744.#852 I265 Def Alloc x4 |V36 a| | |V14 a|I265a| | | |V144a|V20 a| |V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000248] 1745.#853 I265 Use * Keep x4 |V36 a| | |V14 a|I265i| | | |V144a|V20 a| |V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1746.#854 V16 Def Alloc x4 |V36 a| | |V14 a| | | | |V144a|V20 a| |V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x4 |V36 a| | |V14 a| | | | |V144a|V20 a| |V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000257] 1759.#855 V34 Use Keep x24 |V36 a| | |V14 a| | | | |V144a|V20 a| |V49 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1759.#856 V49 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V49 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1760.#857 I266 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I266a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000259] 1761.#858 I266 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I266i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1762.#859 V50 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V50 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000263] 1765.#860 V50 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V50 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1766.#861 V18 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000265] 1771.#862 V18 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1773.#863 BB247 PredBB246 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000269] 1781.#864 V18 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1785.#865 BB113 PredBB247 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000273] 1793.#866 V14 Use Keep x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1797.#867 BB114 PredBB113 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000920] 1810.#868 C267 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |C267a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000824] 1815.#869 V18 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |C267a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1815.#870 V18 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |C267a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1815.#871 C267 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |C267i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1817.#872 BB115 PredBB114 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000925] 1827.#873 V18 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1831.#874 BB117 PredBB115 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004401] 1831.#0 V14 Move STK |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004402] 1831.#0 V18 Move x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1833.#875 BB135 PredBB114 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000827] 1841.#876 V14 Use Keep x3 |V36 a| | |V14 i| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x3 |V36 a| | |V14 i| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1845.#877 BB118 PredBB135 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000831] 1851.#878 V36 Use Keep x0 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1852.#879 I268 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I268a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003678] 1853.#880 I268 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I268i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1854.#881 V177 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000833] 1859.#882 V177 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1861.#883 BB119 PredBB118 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000912] 1864.#884 C269 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|C269a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000917] 1865.#885 C269 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|C269i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1866.#886 V63 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V63 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1867.#887 BB120 PredBB118 |V36 a| | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000848] 1871.#888 V36 Use * Keep x0 |V36 i| | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1872.#889 V61 Def Alloc x0 |V61 a| | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000844] 1877.#890 V61 Use * Keep x0 |V61 i| | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1878.#891 I270 Def Alloc x0 |I270a| | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000846] 1879.#892 I270 Use * Keep x0 |I270i| | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1880.#893 V36 Def Alloc x12 | | | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x12 | | | | | | | | |V144a|V20 a| |V177a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000855] 1883.#894 V177 Use * Keep x11 | | | | | | | | |V144a|V20 a| |V177i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1884.#895 V63 Def Alloc x14 | | | | | | | | |V144a|V20 a| | | |V18 a|V63 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004403] 1885.#0 V36 Move x0 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V63 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1885.#896 BB121 PredBB119 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V63 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001796] 1889.#897 V63 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V63 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1890.#898 I271 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I271a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001836] 1891.#899 I271 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I271i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1892.#900 V92 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001797] 1899.#901 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1900.#902 I272 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a|I272a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001799] 1901.#903 I272 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a|I272i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1902.#904 V91 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001839] 1911.#905 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1912.#906 I273 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|I273a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001805] 1913.#907 V91 Use Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V92 a|I273a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1913.#908 I273 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|I273i|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1917.#909 BB122 PredBB121 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002805] 1925.#910 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1926.#911 I274 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|I274a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001815] 1927.#912 I274 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|I274i|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1928.#913 V93 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|V93 a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001818] 1935.#914 V93 Use Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|V93 a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1936.#915 I275 Def Alloc x15 |V36 a| | | | | | | |V144a|V20 a| |V92 a|V93 a|V18 a|V91 a|I275a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001819] 1937.#916 V91 Use Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V92 a|V93 a|V18 a|V91 a|I275a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1937.#917 I275 Use * Keep x15 |V36 a| | | | | | | |V144a|V20 a| |V92 a|V93 a|V18 a|V91 a|I275i| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001823] 1941.#918 V93 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|V93 i|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1942.#919 I276 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|I276a|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003955] 1955.#920 I276 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V92 a|I276i|V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1955.#921 V91 Use Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1955.#922 V92 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V92 i| |V18 a|V91 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001832] 1963.#923 V91 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V91 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1964.#924 I277 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I277a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003957] 1969.#925 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| |I277a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1969.#926 I277 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I277i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1971.#927 BB123 PredBB121 |V36 a| | | | | | | |V144a|V20 a| |V92 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004404] 1971.#0 V18 Move STK |V36 a| | | | | | | |V144a|V20 a| |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004405] 1971.#0 V20 Move STK |V36 a| | | | | | | |V144a| | |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004406] 1971.#0 V36 Move STK | | | | | | | | |V144a| | |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004407] 1971.#0 V144 Move STK | | | | | | | | | | | |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004234] 1977.#928 x0 Fixd Keep x0 | | | | | | | | | | | |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1977.#929 V0 Use Copy x0 |V0 a| | | | | | | | | | |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1978.#930 x0 Fixd Keep x0 | | | | | | | | | | | |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1978.#931 I278 Def Alloc x0 |I278a| | | | | | | | | | |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004235] 1981.#932 x1 Fixd Keep x1 |I278a| | | | | | | | | | |V92 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1981.#933 V92 Use * Copy x1 |I278a|V92 i| | | | | | | | | |V92 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1982.#934 x1 Fixd Keep x1 |I278a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1982.#935 I279 Def Alloc x1 |I278a|I279a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002812] 1984.#936 C280 Def Alloc x11 |I278a|I279a| | | | | | | | | |C280a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004236] 1985.#937 x11 Fixd Keep x11 |I278a|I279a| | | | | | | | | |C280a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1985.#938 C280 Use * Keep x11 |I278a|I279a| | | | | | | | | |C280i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1986.#939 x11 Fixd Keep x11 |I278a|I279a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1986.#940 I281 Def Alloc x11 |I278a|I279a| | | | | | | | | |I281a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001809] 1987.#941 I282 Def Alloc x14 |I278a|I279a| | | | | | | | | |I281a| | |I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#942 x0 Fixd Keep x0 |I278a|I279a| | | | | | | | | |I281a| | |I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#943 I278 Use * Keep x0 |I278i|I279a| | | | | | | | | |I281a| | |I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#944 x1 Fixd Keep x1 | |I279a| | | | | | | | | |I281a| | |I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#945 I279 Use * Keep x1 | |I279i| | | | | | | | | |I281a| | |I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#946 x11 Fixd Keep x11 | | | | | | | | | | | |I281a| | |I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#947 I281 Use * Keep x11 | | | | | | | | | | | |I281i| | |I282a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1987.#948 I282 Use * Keep x14 | | | | | | | | | | | | | | |I282i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#949 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#950 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#951 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#952 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#953 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#954 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#955 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#956 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#957 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#958 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#959 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#960 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#961 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#962 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#963 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#964 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#965 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#966 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 1988.#967 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004408] 1989.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004409] 1989.#0 V144 Move x8 |V36 a| | | | | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004410] 1989.#0 V20 Move x9 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004411] 1989.#0 V18 Move x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1989.#968 BB124 PredBB122 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000863] 2007.#969 V12 Use ReLod x7 |V36 a| | | | | | |V12 a|V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 |V36 a| | | | | | |V12 i|V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x7 |V36 a| | | | | | |V12 i|V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2007.#970 V8 Use ReLod x2 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2009.#971 BB125 PredBB124 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000890] 2019.#972 V20 Use Keep x9 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2019.#973 V144 Use Keep x8 |V36 a| |V8 a| | | | | |V144i|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x8 |V36 a| |V8 a| | | | | |V144i|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002813] 2033.#974 V143 Use ReLod x6 |V36 a| |V8 a| | | |V143a| | |V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 |V36 a| |V8 a| | | |V143i| | |V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x6 |V36 a| |V8 a| | | |V143i| | |V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2033.#975 V20 Use Keep x9 |V36 a| |V8 a| | | | | | |V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2034.#976 I283 Def Alloc x11 |V36 a| |V8 a| | | | | | |V20 a| |I283a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000899] 2037.#977 I283 Use * Keep x11 |V36 a| |V8 a| | | | | | |V20 a| |I283i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2038.#978 I284 Def Alloc x11 |V36 a| |V8 a| | | | | | |V20 a| |I284a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000881] 2051.#979 I284 Use * Keep x11 |V36 a| |V8 a| | | | | | |V20 a| |I284i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2051.#980 V8 Use Keep x2 |V36 a| |V8 i| | | | | | |V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x2 |V36 a| |V8 i| | | | | | |V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2051.#981 V20 Use Keep x9 |V36 a| | | | | | | | |V20 i| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x9 |V36 a| | | | | | | | |V20 i| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2053.#982 BB127 PredBB125 |V36 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001843] 2063.#983 V3 Use Keep x20 |V36 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2064.#984 I285 Def Alloc x11 |V36 a| | | | | | | | | | |I285a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001896] 2065.#985 I285 Use * Keep x11 |V36 a| | | | | | | | | | |I285i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2066.#986 V95 Def Alloc x11 |V36 a| | | | | | | | | | |V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001847] 2073.#987 V95 Use Keep x11 |V36 a| | | | | | | | | | |V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2075.#988 BB129 PredBB127 |V36 a| | | | | | | | | | |V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001849] 2083.#989 V0 Use Keep x19 |V36 a| | | | | | | | | | |V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2084.#990 I286 Def Alloc x14 |V36 a| | | | | | | | | | |V95 a| |V18 a|I286a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001851] 2085.#991 I286 Use * Keep x14 |V36 a| | | | | | | | | | |V95 a| |V18 a|I286i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2086.#992 V96 Def Alloc x14 |V36 a| | | | | | | | | | |V95 a| |V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001853] 2093.#993 V95 Use Keep x11 |V36 a| | | | | | | | | | |V95 a| |V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2094.#994 I287 Def Alloc x12 |V36 a| | | | | | | | | | |V95 a|I287a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003716] 2095.#995 I287 Use * Keep x12 |V36 a| | | | | | | | | | |V95 a|I287i|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2096.#996 V181 Def Alloc x12 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001899] 2109.#997 V0 Use Keep x19 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2110.#998 I288 Def Alloc x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I288a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001856] 2115.#999 V181 Use Keep x12 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I288a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2115.#1000 V96 Use Keep x14 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I288a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2115.#1001 I288 Use * Keep x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I288i| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2117.#1002 BB130 PredBB129 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002827] 2127.#1003 V0 Use Keep x19 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2128.#1004 I289 Def Alloc x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I289a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001872] 2129.#1005 I289 Use * Keep x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I289i| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2130.#1006 V97 Def Alloc x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|V97 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001875] 2139.#1007 V97 Use Keep x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|V97 a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2140.#1008 I290 Def Alloc xip0 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|V97 a|I290a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001876] 2141.#1009 V96 Use Keep x14 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|V97 a|I290a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2141.#1010 I290 Use * Keep xip0 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|V97 a|I290i|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001880] 2145.#1011 V97 Use * Keep x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|V97 i| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2146.#1012 I291 Def Alloc x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I291a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001879] 2153.#1013 V96 Use Keep x14 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I291a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2154.#1014 I292 Def Alloc xip0 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I291a|I292a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001881] 2155.#1015 I291 Use * Keep x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I291i|I292a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2155.#1016 I292 Use * Keep xip0 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a| |I292i|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2156.#1017 I293 Def Alloc x15 |V36 a| | | | | | | | | | |V95 a|V181a|V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002835] 2161.#1018 V181 Use * Keep x12 |V36 a| | | | | | | | | | |V95 a|V181i|V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002844] 2167.#1019 V95 Use * Keep x11 |V36 a| | | | | | | | | | |V95 i| |V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2168.#1020 I294 Def Alloc x11 |V36 a| | | | | | | | | | |I294a| |V18 a|V96 a|I293a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003970] 2169.#1021 I293 Use * Keep x15 |V36 a| | | | | | | | | | |I294a| |V18 a|V96 a|I293i| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2169.#1022 I294 Use * Keep x11 |V36 a| | | | | | | | | | |I294i| |V18 a|V96 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001892] 2177.#1023 V96 Use * Keep x14 |V36 a| | | | | | | | | | | | |V18 a|V96 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2178.#1024 I295 Def Alloc x11 |V36 a| | | | | | | | | | |I295a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003972] 2183.#1025 V0 Use Keep x19 |V36 a| | | | | | | | | | |I295a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2183.#1026 I295 Use * Keep x11 |V36 a| | | | | | | | | | |I295i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2185.#1027 BB132 PredBB129 |V36 a| | | | | | | | | | |V95 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004412] 2185.#0 V18 Move STK |V36 a| | | | | | | | | | |V95 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004413] 2185.#0 V36 Move STK | | | | | | | | | | | |V95 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004237] 2191.#1028 x0 Fixd Keep x0 | | | | | | | | | | | |V95 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2191.#1029 V0 Use Copy x0 |V0 a| | | | | | | | | | |V95 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2192.#1030 x0 Fixd Keep x0 | | | | | | | | | | | |V95 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2192.#1031 I296 Def Alloc x0 |I296a| | | | | | | | | | |V95 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004238] 2195.#1032 x1 Fixd Keep x1 |I296a| | | | | | | | | | |V95 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2195.#1033 V95 Use * Copy x1 |I296a|V95 i| | | | | | | | | |V95 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2196.#1034 x1 Fixd Keep x1 |I296a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2196.#1035 I297 Def Alloc x1 |I296a|I297a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002847] 2198.#1036 C298 Def Alloc x11 |I296a|I297a| | | | | | | | | |C298a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004239] 2199.#1037 x11 Fixd Keep x11 |I296a|I297a| | | | | | | | | |C298a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2199.#1038 C298 Use * Keep x11 |I296a|I297a| | | | | | | | | |C298i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2200.#1039 x11 Fixd Keep x11 |I296a|I297a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2200.#1040 I299 Def Alloc x11 |I296a|I297a| | | | | | | | | |I299a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001859] 2201.#1041 I300 Def Alloc x14 |I296a|I297a| | | | | | | | | |I299a| | |I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1042 x0 Fixd Keep x0 |I296a|I297a| | | | | | | | | |I299a| | |I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1043 I296 Use * Keep x0 |I296i|I297a| | | | | | | | | |I299a| | |I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1044 x1 Fixd Keep x1 | |I297a| | | | | | | | | |I299a| | |I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1045 I297 Use * Keep x1 | |I297i| | | | | | | | | |I299a| | |I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1046 x11 Fixd Keep x11 | | | | | | | | | | | |I299a| | |I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1047 I299 Use * Keep x11 | | | | | | | | | | | |I299i| | |I300a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2201.#1048 I300 Use * Keep x14 | | | | | | | | | | | | | | |I300i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1049 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1050 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1051 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1052 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1053 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1054 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1055 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1056 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1057 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1058 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1059 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1060 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1061 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1062 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1063 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1064 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1065 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1066 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2202.#1067 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004414] 2203.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004415] 2203.#0 V18 Move x13 |V36 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2203.#1068 BB133 PredBB127 |V36 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000909] 2211.#1069 V20 Use * ReLod x9 |V36 a| | | | | | | | |V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 |V36 a| | | | | | | | |V20 i| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2212.#1070 I301 Def Alloc x9 |V36 a| | | | | | | | |I301a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000911] 2213.#1071 I301 Use * Keep x9 |V36 a| | | | | | | | |I301i| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2214.#1072 V20 Def Alloc x9 |V36 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x9 |V36 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004416] 2215.#0 V8 Move x2 |V36 a| |V8 a| | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004417] 2215.#0 V144 Move x8 |V36 a| |V8 a| | | | | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004418] 2215.#0 V20 Move x9 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2215.#1073 BB134 PredBB124 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000866] 2223.#1074 V8 Use * Keep x2 |V36 a| |V8 i| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2224.#1075 I302 Def Alloc x2 |V36 a| |I302a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000868] 2225.#1076 I302 Use * Keep x2 |V36 a| |I302i| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2226.#1077 V8 Def Alloc x2 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x2 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000871] 2233.#1078 V14 Use * ReLod x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 |V36 a| | |V14 i| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2234.#1079 I303 Def Alloc x3 |V36 a| | |I303a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000873] 2235.#1080 I303 Use * Keep x3 |V36 a| | |I303i| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2236.#1081 V14 Def Alloc x3 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x3 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004419] 2237.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2237.#1082 BB136 PredBB135 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000277] 2245.#1083 V18 Use Keep x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2249.#1084 BB137 PredBB136 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000595] 2257.#1085 V18 Use Keep x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2258.#1086 I304 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|I304a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004241] 2259.#1087 I304 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|I304i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2260.#1088 V184 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V184a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004245] 2265.#1089 V184 Use Keep x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V184a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2269.#1090 BB138 PredBB137 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000599] 2277.#1091 V18 Use Keep x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2278.#1092 I305 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| | |I305a|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004252] 2279.#1093 I305 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| | |I305i|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2280.#1094 V185 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| | |V185a|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004256] 2285.#1095 V185 Use Keep x12 |V36 a| | | | | | | |V144a|V20 a| | |V185a|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2289.#1096 BB139 PredBB138 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000603] 2297.#1097 V18 Use Keep x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2301.#1098 BB140 PredBB139 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2303.#1099 BB141 PredBB136 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000281] 2311.#1100 V18 Use Keep x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2315.#1101 BB142 PredBB141 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000321] 2323.#1102 V18 Use Keep x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2327.#1103 BB143 PredBB142 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000582] 2334.#1104 C306 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |C306a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000583] 2335.#1105 V18 Use Keep x13 |V36 a| | | | | | | |V144a|V20 a| |C306a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2335.#1106 C306 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |C306i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2339.#1107 BB144 PredBB143 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002066] 2347.#1108 V3 Use Keep x20 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2348.#1109 I307 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I307a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002119] 2349.#1110 I307 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I307i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2350.#1111 V110 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2351.#1112 BB181 PredBB144 |V36 a| | | | | | | |V144a|V20 a| |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002070] 2359.#1113 V110 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2361.#1114 V110 DDef |V36 a| | | | | | | |V144a|V20 a| |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004343] 2361.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2361.#1115 BB182 PredBB112 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002072] 2369.#1116 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2370.#1117 I308 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |I308a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002074] 2371.#1118 I308 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |I308i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2372.#1119 V111 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002076] 2379.#1120 V110 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2380.#1121 I309 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002122] 2391.#1122 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2392.#1123 I310 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I310a|V111a|I309a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002079] 2397.#1124 I309 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I310a|V111a|I309i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2397.#1125 V111 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I310a|V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2397.#1126 I310 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I310i|V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2399.#1127 BB183 PredBB182 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002952] 2409.#1128 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2410.#1129 I311 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|I311a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002095] 2411.#1130 I311 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|I311i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2412.#1131 V112 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002098] 2421.#1132 V112 Use Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2422.#1133 I312 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I312a|V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002099] 2423.#1134 V111 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I312a|V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2423.#1135 I312 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I312i|V111a|V112a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002103] 2427.#1136 V112 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|V112i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2428.#1137 I313 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|I313a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002102] 2435.#1138 V111 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|I313a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2436.#1139 I314 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I314a|V111a|I313a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002104] 2437.#1140 I313 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I314a|V111a|I313i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2437.#1141 I314 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I314i|V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2438.#1142 I315 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002959] 2445.#1143 V110 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2446.#1144 I316 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I316a|V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002960] 2447.#1145 I316 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a|I316i|V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002969] 2453.#1146 V110 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110i| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2454.#1147 I317 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I317a| |V111a|I315a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004045] 2455.#1148 I315 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |I317a| |V111a|I315i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2455.#1149 I317 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I317i| |V111a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002115] 2463.#1150 V111 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V111i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2464.#1151 I318 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I318a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004047] 2469.#1152 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |I318a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2469.#1153 I318 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I318i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2471.#1154 BB185 PredBB182 |V36 a| | |V14 a| | | | |V144a|V20 a| |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004446] 2471.#0 V20 Move STK |V36 a| | |V14 a| | | | |V144a| | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004447] 2471.#0 V14 Move STK |V36 a| | | | | | | |V144a| | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004448] 2471.#0 V36 Move STK | | | | | | | | |V144a| | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004449] 2471.#0 V144 Move STK | | | | | | | | | | | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004271] 2477.#1155 x0 Fixd Keep x0 | | | | | | | | | | | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2477.#1156 V0 Use Copy x0 |V0 a| | | | | | | | | | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2478.#1157 x0 Fixd Keep x0 | | | | | | | | | | | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2478.#1158 I319 Def Alloc x0 |I319a| | | | | | | | | | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004272] 2481.#1159 x1 Fixd Keep x1 |I319a| | | | | | | | | | |V110a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2481.#1160 V110 Use * Copy x1 |I319a|V110i| | | | | | | | | |V110i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2482.#1161 x1 Fixd Keep x1 |I319a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2482.#1162 I320 Def Alloc x1 |I319a|I320a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002972] 2484.#1163 C321 Def Alloc x11 |I319a|I320a| | | | | | | | | |C321a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004273] 2485.#1164 x11 Fixd Keep x11 |I319a|I320a| | | | | | | | | |C321a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2485.#1165 C321 Use * Keep x11 |I319a|I320a| | | | | | | | | |C321i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2486.#1166 x11 Fixd Keep x11 |I319a|I320a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2486.#1167 I322 Def Alloc x11 |I319a|I320a| | | | | | | | | |I322a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002082] 2487.#1168 I323 Def Alloc x13 |I319a|I320a| | | | | | | | | |I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1169 x0 Fixd Keep x0 |I319a|I320a| | | | | | | | | |I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1170 I319 Use * Keep x0 |I319i|I320a| | | | | | | | | |I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1171 x1 Fixd Keep x1 | |I320a| | | | | | | | | |I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1172 I320 Use * Keep x1 | |I320i| | | | | | | | | |I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1173 x11 Fixd Keep x11 | | | | | | | | | | | |I322a| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1174 I322 Use * Keep x11 | | | | | | | | | | | |I322i| |I323a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2487.#1175 I323 Use * Keep x13 | | | | | | | | | | | | | |I323i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1176 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1177 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1178 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1179 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1180 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1181 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1182 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1183 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1184 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1185 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1186 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1187 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1188 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1189 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1190 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1191 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1192 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1193 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2488.#1194 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004450] 2489.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004451] 2489.#0 V14 Move x3 |V36 a| | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004452] 2489.#0 V144 Move x8 |V36 a| | |V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004453] 2489.#0 V20 Move x9 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2489.#1195 BB200 PredBB141 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000297] 2511.#1196 V34 Use Keep x24 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2511.#1197 V16 Use ReLod x4 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2512.#1198 I324 Def Alloc x13 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |I324a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003664] 2513.#1199 I324 Use * Keep x13 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |I324i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2514.#1200 V176 Def Alloc x13 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000289] 2523.#1201 V16 Use Keep x4 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2523.#1202 V179 Use Keep x25 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2523.#1203 V176 Use Keep x13 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2525.#1204 V176 DDef |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004349] 2525.#0 V16 Move STK |V36 a| | | | | | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004350] 2525.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2525.#1205 BB201 PredBB112 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000310] 2533.#1206 V16 Use * ReLod x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | |V14 a|V16 i| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2534.#1207 V51 Def Alloc x4 |V36 a| | |V14 a|V51 a| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000306] 2541.#1208 V51 Use * Keep x4 |V36 a| | |V14 a|V51 i| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2542.#1209 I325 Def Alloc x4 |V36 a| | |V14 a|I325a| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000308] 2543.#1210 I325 Use * Keep x4 |V36 a| | |V14 a|I325i| | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2544.#1211 V16 Def Alloc x4 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x4 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V176a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002283] 2547.#1212 V176 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V176i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2548.#1213 V123 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002244] 2555.#1214 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2556.#1215 I326 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I326a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002246] 2557.#1216 I326 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I326i| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2558.#1217 V122 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002286] 2567.#1218 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2568.#1219 I327 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|I327a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002252] 2569.#1220 V122 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|I327a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2569.#1221 I327 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|I327i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2573.#1222 BB203 PredBB201 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003037] 2581.#1223 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2582.#1224 I328 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|I328a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002262] 2583.#1225 I328 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|I328i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2584.#1226 V124 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002265] 2591.#1227 V124 Use Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2592.#1228 I329 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a|I329a|V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002266] 2593.#1229 V122 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a|I329a|V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2593.#1230 I329 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a|I329i|V123a|V124a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002270] 2597.#1231 V124 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|V124i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2598.#1232 I330 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|I330a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004082] 2611.#1233 I330 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a|I330i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2611.#1234 V122 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2611.#1235 V123 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122a| |V123i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002279] 2619.#1236 V122 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V122i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2620.#1237 I331 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I331a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004084] 2625.#1238 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I331a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2625.#1239 I331 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I331i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2627.#1240 BB204 PredBB201 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004470] 2627.#0 V20 Move STK |V36 a| | |V14 a| | | | |V144a| | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004471] 2627.#0 V14 Move STK |V36 a| | | | | | | |V144a| | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004472] 2627.#0 V36 Move STK | | | | | | | | |V144a| | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004473] 2627.#0 V144 Move STK | | | | | | | | | | | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004280] 2633.#1241 x0 Fixd Keep x0 | | | | | | | | | | | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2633.#1242 V0 Use Copy x0 |V0 a| | | | | | | | | | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2634.#1243 x0 Fixd Keep x0 | | | | | | | | | | | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2634.#1244 I332 Def Alloc x0 |I332a| | | | | | | | | | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004281] 2637.#1245 x1 Fixd Keep x1 |I332a| | | | | | | | | | | | |V123a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2637.#1246 V123 Use * Copy x1 |I332a|V123i| | | | | | | | | | | |V123i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2638.#1247 x1 Fixd Keep x1 |I332a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2638.#1248 I333 Def Alloc x1 |I332a|I333a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003044] 2640.#1249 C334 Def Alloc x11 |I332a|I333a| | | | | | | | | |C334a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004282] 2641.#1250 x11 Fixd Keep x11 |I332a|I333a| | | | | | | | | |C334a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2641.#1251 C334 Use * Keep x11 |I332a|I333a| | | | | | | | | |C334i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2642.#1252 x11 Fixd Keep x11 |I332a|I333a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2642.#1253 I335 Def Alloc x11 |I332a|I333a| | | | | | | | | |I335a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002256] 2643.#1254 I336 Def Alloc x13 |I332a|I333a| | | | | | | | | |I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1255 x0 Fixd Keep x0 |I332a|I333a| | | | | | | | | |I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1256 I332 Use * Keep x0 |I332i|I333a| | | | | | | | | |I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1257 x1 Fixd Keep x1 | |I333a| | | | | | | | | |I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1258 I333 Use * Keep x1 | |I333i| | | | | | | | | |I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1259 x11 Fixd Keep x11 | | | | | | | | | | | |I335a| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1260 I335 Use * Keep x11 | | | | | | | | | | | |I335i| |I336a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2643.#1261 I336 Use * Keep x13 | | | | | | | | | | | | | |I336i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1262 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1263 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1264 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1265 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1266 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1267 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1268 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1269 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1270 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1271 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1272 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1273 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1274 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1275 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1276 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1277 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1278 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1279 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2644.#1280 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004474] 2645.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004475] 2645.#0 V14 Move x3 |V36 a| | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004476] 2645.#0 V144 Move x8 |V36 a| | |V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004477] 2645.#0 V20 Move x9 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2645.#1281 BB205 PredBB139 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000325] 2652.#1282 V37 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |V37 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000328] 2658.#1283 V38 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000331] 2665.#1284 V9 Use ReLod x5 |V36 a| | | | |V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x5 |V36 a| | | | |V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2667.#1285 BB206 PredBB205 |V36 a| | | | |V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000424] 2675.#1286 V16 Use ReLod x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2675.#1287 V179 Use Keep x25 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2679.#1288 BB207 PredBB206 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000572] 2695.#1289 V34 Use Keep x24 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2695.#1290 V16 Use Keep x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2696.#1291 I337 Def Alloc x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I337a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003669] 2697.#1292 I337 Use * Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I337i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2698.#1293 V176 Def Alloc x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000574] 2703.#1294 V176 Use * Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2707.#1295 BB208 PredBB206 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000428] 2715.#1296 V16 Use Keep x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2716.#1297 I338 Def Alloc x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I338a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000433] 2719.#1298 I338 Use * Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I338i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2719.#1299 V179 Use Keep x25 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2723.#1300 BB209 PredBB208 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000545] 2739.#1301 V34 Use Keep x24 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2739.#1302 V16 Use Keep x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2740.#1303 I339 Def Alloc x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I339a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003673] 2741.#1304 I339 Use * Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I339i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2742.#1305 V176 Def Alloc x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000547] 2747.#1306 V176 Use Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2748.#1307 I340 Def Alloc x15 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000552] 2755.#1308 V16 Use Keep x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2756.#1309 I341 Def Alloc xip0 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340a|I341a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000558] 2765.#1310 V34 Use Keep x24 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340a|I341a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2765.#1311 I341 Use * Keep xip0 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340a|I341i|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2766.#1312 I342 Def Alloc xip0 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340a|I342a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000560] 2769.#1313 I342 Use * Keep xip0 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340a|I342i|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2770.#1314 I343 Def Alloc xip0 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340a|I343a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003762] 2771.#1315 I340 Use * Keep x15 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I340i|I343a|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2771.#1316 I343 Use * Keep xip0 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a| |I343i|V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2772.#1317 I344 Def Alloc x15 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I344a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000548] 2773.#1318 I344 Use * Keep x15 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a|I344i| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2775.#1319 BB210 PredBB209 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003046] 2782.#1320 C345 Def Alloc x11 |V36 a| | | |V16 a| | | |V144a|V20 a| |C345a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000564] 2783.#1321 C345 Use * Keep x11 |V36 a| | | |V16 a| | | |V144a|V20 a| |C345i| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2784.#1322 V37 Def Alloc x11 |V36 a| | | |V16 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2785.#1323 BB213 PredBB209 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000456] 2793.#1324 V176 Use * Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|V176i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2797.#1325 BB214 PredBB213 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000461] 2807.#1326 V16 Use Keep x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2808.#1327 I346 Def Alloc x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I346a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000467] 2817.#1328 V34 Use Keep x24 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I346a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2817.#1329 I346 Use * Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I346i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2818.#1330 I347 Def Alloc x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I347a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000469] 2821.#1331 I347 Use * Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V37 a|I347i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2825.#1332 BB215 PredBB208 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002302] 2833.#1333 V0 Use Keep x19 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2834.#1334 I348 Def Alloc x14 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a|I348a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002304] 2835.#1335 I348 Use * Keep x14 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a|I348i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2836.#1336 V126 Def Alloc x14 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002341] 2845.#1337 V0 Use Keep x19 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2846.#1338 I349 Def Alloc x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |I349a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002310] 2847.#1339 V126 Use Keep x14 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |I349a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2847.#1340 I349 Use * Keep x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |I349i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2851.#1341 BB216 PredBB215 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003058] 2859.#1342 V0 Use Keep x19 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2860.#1343 I350 Def Alloc x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |I350a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002319] 2861.#1344 I350 Use * Keep x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |I350i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2862.#1345 V127 Def Alloc x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V127a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002322] 2871.#1346 V127 Use Keep x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V127a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2872.#1347 I351 Def Alloc x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V127a|I351a|V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002323] 2873.#1348 V126 Use Keep x14 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V127a|I351a|V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2873.#1349 I351 Use * Keep x12 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V127a|I351i|V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002327] 2877.#1350 V127 Use * Keep x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |V127i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2878.#1351 I352 Def Alloc x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |I352a| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004101] 2891.#1352 I352 Use * Keep x11 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| |I352i| |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2891.#1353 V126 Use Keep x14 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 a|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2891.#1354 V18 Use * Keep x13 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |V18 i|V126a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002336] 2899.#1355 V126 Use * Keep x14 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | | |V126i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2900.#1356 I353 Def Alloc x13 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |I353a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004103] 2905.#1357 V0 Use Keep x19 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |I353a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2905.#1358 I353 Use * Keep x13 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | |I353i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2907.#1359 V9 ExpU |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004478] 2907.#0 V16 Move STK |V36 a| | | | |V9 a| | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004479] 2907.#0 V9 Move STK |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004480] 2907.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2907.#1360 BB218 PredBB207 |V36 a| | | |V16 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000535] 2915.#1361 V38 Use * Keep x14 |V36 a| | | |V16 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2916.#1362 I354 Def Alloc x14 |V36 a| | | |V16 a| | | |V144a|V20 a| |V37 a| |V18 a|I354a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000537] 2917.#1363 I354 Use * Keep x14 |V36 a| | | |V16 a| | | |V144a|V20 a| |V37 a| |V18 a|I354i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2918.#1364 V38 Def Alloc x14 |V36 a| | | |V16 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2919.#1365 BB219 PredBB218 |V36 a| | | |V16 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000473] 2927.#1366 V16 Use * Keep x4 |V36 a| | | |V16 i| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2928.#1367 I355 Def Alloc x4 |V36 a| | | |I355a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000475] 2929.#1368 I355 Use * Keep x4 |V36 a| | | |I355i| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2930.#1369 V54 Def Alloc x4 |V36 a| | | |V54 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000479] 2933.#1370 V54 Use * Keep x4 |V36 a| | | |V54 i| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2934.#1371 V16 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000484] 2939.#1372 V16 Use Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2939.#1373 V179 Use Keep x25 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2943.#1374 BB220 PredBB219 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000529] 2959.#1375 V34 Use Keep x24 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2959.#1376 V16 Use Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x12 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 i|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2960.#1377 I356 Def Alloc x5 |V36 a| | | | |I356a| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000531] 2963.#1378 I356 Use * Keep x5 |V36 a| | | | |I356i| | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2967.#1379 BB221 PredBB219 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000488] 2975.#1380 V38 Use Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2979.#1381 BB222 PredBB221 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000519] 2984.#1382 C357 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|C357a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000521] 2985.#1383 C357 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|C357i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2986.#1384 V38 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2987.#1385 BB223 PredBB221 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000491] 2993.#1386 V17 Use Keep x23 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 2994.#1387 I358 Def Alloc x5 |V36 a| | | | |I358a| | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000493] 2997.#1388 I358 Use * Keep x5 |V36 a| | | | |I358i| | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 2999.#1389 BB224 PredBB223 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000513] 3007.#1390 V1 Use Keep x21 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3008.#1391 I359 Def Alloc x5 |V36 a| | | | |I359a| | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000515] 3011.#1392 I359 Use * Keep x5 |V36 a| | | | |I359i| | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3011.#1393 V5 Use Keep x28 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3012.#1394 I360 Def Alloc x4 |V36 a| | | |I360a| | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000517] 3013.#1395 I360 Use * Keep x4 |V36 a| | | |I360i| | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3014.#1396 V55 Def Alloc x4 |V36 a| | | |V55 a| | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004481] 3015.#0 V16 Move STK |V36 a| | | |V55 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004482] 3015.#0 V20 Move STK |V36 a| | | |V55 a| | | |V144a| | |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004483] 3015.#0 V36 Move STK | | | | |V55 a| | | |V144a| | |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004484] 3015.#0 V144 Move STK | | | | |V55 a| | | | | | |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3015.#1397 BB225 PredBB223 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000497] 3022.#1398 V55 Def Alloc x4 |V36 a| | | |V55 a| | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004485] 3023.#0 V16 Move STK |V36 a| | | |V55 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004486] 3023.#0 V20 Move STK |V36 a| | | |V55 a| | | |V144a| | |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004487] 3023.#0 V36 Move STK | | | | |V55 a| | | |V144a| | |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004488] 3023.#0 V144 Move STK | | | | |V55 a| | | | | | |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3023.#1399 BB226 PredBB224 | | | | |V55 a| | | | | | |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004283] 3029.#1400 x5 Fixd Keep x5 | | | | |V55 a| | | | | | |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3029.#1401 V37 Use * Copy x5 | | | | |V55 a|V37 i| | | | | |V37 i| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3030.#1402 x5 Fixd Keep x5 | | | | |V55 a| | | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3030.#1403 I361 Def Alloc x5 | | | | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004284] 3033.#1404 x0 Fixd Keep x0 | | | | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3033.#1405 V0 Use Copy x0 |V0 a| | | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3034.#1406 x0 Fixd Keep x0 | | | | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3034.#1407 I362 Def Alloc x0 |I362a| | | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004285] 3037.#1408 x1 Fixd Keep x1 |I362a| | | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3037.#1409 V3 Use Copy x1 |I362a|V3 a| | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3038.#1410 x1 Fixd Keep x1 |I362a| | | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3038.#1411 I363 Def Alloc x1 |I362a|I363a| | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004286] 3041.#1412 x2 Fixd Keep x2 |I362a|I363a| | |V55 a|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3041.#1413 V55 Use * Copy x2 |I362a|I363a|V55 i| |V55 i|I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3042.#1414 x2 Fixd Keep x2 |I362a|I363a| | | |I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3042.#1415 I364 Def Alloc x2 |I362a|I363a|I364a| | |I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004287] 3045.#1416 x3 Fixd Keep x3 |I362a|I363a|I364a| | |I361a| | | | | | | |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3045.#1417 V18 Use * Copy x3 |I362a|I363a|I364a|V18 i| |I361a| | | | | | | |V18 i|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3046.#1418 x3 Fixd Keep x3 |I362a|I363a|I364a| | |I361a| | | | | | | | |V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3046.#1419 I365 Def Alloc x3 |I362a|I363a|I364a|I365a| |I361a| | | | | | | | |V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004288] 3049.#1420 x4 Fixd Keep x4 |I362a|I363a|I364a|I365a| |I361a| | | | | | | | |V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3049.#1421 V38 Use * Copy x4 |I362a|I363a|I364a|I365a|V38 i|I361a| | | | | | | | |V38 i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3050.#1422 x4 Fixd Keep x4 |I362a|I363a|I364a|I365a| |I361a| | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3050.#1423 I366 Def Alloc x4 |I362a|I363a|I364a|I365a|I366a|I361a| | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003068] 3052.#1424 C367 Def Alloc x11 |I362a|I363a|I364a|I365a|I366a|I361a| | | | | |C367a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004289] 3053.#1425 x11 Fixd Keep x11 |I362a|I363a|I364a|I365a|I366a|I361a| | | | | |C367a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3053.#1426 C367 Use * Keep x11 |I362a|I363a|I364a|I365a|I366a|I361a| | | | | |C367i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3054.#1427 x11 Fixd Keep x11 |I362a|I363a|I364a|I365a|I366a|I361a| | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3054.#1428 I368 Def Alloc x11 |I362a|I363a|I364a|I365a|I366a|I361a| | | | | |I368a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000508] 3055.#1429 I369 Def Alloc x13 |I362a|I363a|I364a|I365a|I366a|I361a| | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1430 x5 Fixd Keep x5 |I362a|I363a|I364a|I365a|I366a|I361a| | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1431 I361 Use * Keep x5 |I362a|I363a|I364a|I365a|I366a|I361i| | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1432 x0 Fixd Keep x0 |I362a|I363a|I364a|I365a|I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1433 I362 Use * Keep x0 |I362i|I363a|I364a|I365a|I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1434 x1 Fixd Keep x1 | |I363a|I364a|I365a|I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1435 I363 Use * Keep x1 | |I363i|I364a|I365a|I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1436 x2 Fixd Keep x2 | | |I364a|I365a|I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1437 I364 Use * Keep x2 | | |I364i|I365a|I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1438 x3 Fixd Keep x3 | | | |I365a|I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1439 I365 Use * Keep x3 | | | |I365i|I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1440 x4 Fixd Keep x4 | | | | |I366a| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1441 I366 Use * Keep x4 | | | | |I366i| | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1442 x11 Fixd Keep x11 | | | | | | | | | | | |I368a| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1443 I368 Use * Keep x11 | | | | | | | | | | | |I368i| |I369a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3055.#1444 I369 Use * Keep x13 | | | | | | | | | | | | | |I369i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1445 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1446 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1447 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1448 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1449 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1450 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1451 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1452 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1453 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1454 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1455 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1456 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1457 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1458 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1459 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1460 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1461 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1462 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3056.#1463 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000511] 3062.#1464 V9 Def Alloc x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004489] 3063.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004490] 3063.#0 V14 Move x3 |V36 a| | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004491] 3063.#0 V144 Move x8 |V36 a| | |V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004492] 3063.#0 V20 Move x9 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3063.#1465 BB227 PredBB205 |V36 a| | | | |V9 a| | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002349] 3071.#1466 V0 Use Keep x19 |V36 a| | | | |V9 a| | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3072.#1467 I370 Def Alloc x11 |V36 a| | | | |V9 a| | |V144a|V20 a| |I370a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002351] 3073.#1468 I370 Use * Keep x11 |V36 a| | | | |V9 a| | |V144a|V20 a| |I370i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3074.#1469 V129 Def Alloc x11 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002388] 3083.#1470 V0 Use Keep x19 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3084.#1471 I371 Def Alloc x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|I371a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002357] 3085.#1472 V129 Use Keep x11 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|I371a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3085.#1473 I371 Use * Keep x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|I371i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3089.#1474 BB228 PredBB227 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003081] 3097.#1475 V0 Use Keep x19 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3098.#1476 I372 Def Alloc x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|I372a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002366] 3099.#1477 I372 Use * Keep x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|I372i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3100.#1478 V130 Def Alloc x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002369] 3109.#1479 V130 Use Keep x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3110.#1480 I373 Def Alloc x12 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a|I373a|V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002370] 3111.#1481 V129 Use Keep x11 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a|I373a|V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3111.#1482 I373 Use * Keep x12 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a|I373i|V18 a|V130a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002374] 3115.#1483 V130 Use * Keep x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|V130i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3116.#1484 I374 Def Alloc x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|I374a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004118] 3129.#1485 I374 Use * Keep x14 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a|I374i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3129.#1486 V129 Use Keep x11 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3129.#1487 V18 Use * Keep x13 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002383] 3137.#1488 V129 Use * Keep x11 |V36 a| | | | |V9 a| | |V144a|V20 a| |V129i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3138.#1489 I375 Def Alloc x13 |V36 a| | | | |V9 a| | |V144a|V20 a| | | |I375a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004120] 3143.#1490 V0 Use Keep x19 |V36 a| | | | |V9 a| | |V144a|V20 a| | | |I375a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3143.#1491 I375 Use * Keep x13 |V36 a| | | | |V9 a| | |V144a|V20 a| | | |I375i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3145.#1492 BB229 PredBB227 |V36 a| | | | |V9 a| | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004493] 3145.#0 V20 Move STK |V36 a| | | | |V9 a| | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004494] 3145.#0 V36 Move STK | | | | | |V9 a| | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004495] 3145.#0 V144 Move STK | | | | | |V9 a| | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004496] 3145.#0 V9 Move STK | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004290] 3151.#1493 x0 Fixd Keep x0 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3151.#1494 V0 Use Copy x0 |V0 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3152.#1495 x0 Fixd Keep x0 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3152.#1496 I376 Def Alloc x0 |I376a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004291] 3155.#1497 x1 Fixd Keep x1 |I376a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3155.#1498 V18 Use * Copy x1 |I376a|V18 i| | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3156.#1499 x1 Fixd Keep x1 |I376a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3156.#1500 I377 Def Alloc x1 |I376a|I377a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003088] 3158.#1501 C378 Def Alloc x11 |I376a|I377a| | | | | | | | | |C378a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004292] 3159.#1502 x11 Fixd Keep x11 |I376a|I377a| | | | | | | | | |C378a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3159.#1503 C378 Use * Keep x11 |I376a|I377a| | | | | | | | | |C378i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3160.#1504 x11 Fixd Keep x11 |I376a|I377a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3160.#1505 I379 Def Alloc x11 |I376a|I377a| | | | | | | | | |I379a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002360] 3161.#1506 I380 Def Alloc x13 |I376a|I377a| | | | | | | | | |I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1507 x0 Fixd Keep x0 |I376a|I377a| | | | | | | | | |I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1508 I376 Use * Keep x0 |I376i|I377a| | | | | | | | | |I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1509 x1 Fixd Keep x1 | |I377a| | | | | | | | | |I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1510 I377 Use * Keep x1 | |I377i| | | | | | | | | |I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1511 x11 Fixd Keep x11 | | | | | | | | | | | |I379a| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1512 I379 Use * Keep x11 | | | | | | | | | | | |I379i| |I380a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3161.#1513 I380 Use * Keep x13 | | | | | | | | | | | | | |I380i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1514 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1515 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1516 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1517 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1518 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1519 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1520 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1521 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1522 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1523 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1524 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1525 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1526 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1527 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1528 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1529 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1530 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1531 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3162.#1532 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004497] 3163.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004498] 3163.#0 V9 Move x5 |V36 a| | | | |V9 a| | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004499] 3163.#0 V144 Move x8 |V36 a| | | | |V9 a| | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004500] 3163.#0 V20 Move x9 |V36 a| | | | |V9 a| | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3163.#1533 BB230 PredBB228 |V36 a| | | | |V9 a| | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000341] 3171.#1534 V16 Use ReLod x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3171.#1535 V179 Use Keep x25 |V36 a| | | |V16 a|V9 a| | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004358] 3175.#0 V16 Move STK |V36 a| | | | |V9 a| | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004359] 3175.#0 V9 Move STK |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004360] 3175.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3175.#1536 BB231 PredBB112 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000350] 3191.#1537 V34 Use Keep x24 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3191.#1538 V16 Use ReLod x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3192.#1539 I381 Def Alloc x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |I381a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003658] 3193.#1540 I381 Use * Keep x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |I381i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3194.#1541 V175 Def Alloc x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000352] 3199.#1542 V175 Use Keep x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3203.#1543 BB232 PredBB231 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000417] 3211.#1544 V175 Use Keep x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3215.#1545 BB233 PredBB231 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000363] 3221.#1546 V16 Use * Keep x4 |V36 a| | |V14 a|V16 i| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3222.#1547 V52 Def Alloc x4 |V36 a| | |V14 a|V52 a| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000359] 3229.#1548 V52 Use * Keep x4 |V36 a| | |V14 a|V52 i| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3230.#1549 I382 Def Alloc x4 |V36 a| | |V14 a|I382a| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000361] 3231.#1550 I382 Use * Keep x4 |V36 a| | |V14 a|I382i| | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3232.#1551 V16 Def Alloc x4 |V36 a| | |V14 a| | | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x4 |V36 a| | |V14 a| | | | |V144a|V20 a| |V175a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002435] 3235.#1552 V175 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V175i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3236.#1553 V133 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002396] 3243.#1554 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3244.#1555 I383 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |I383a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002398] 3245.#1556 I383 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |I383i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3246.#1557 V132 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002438] 3255.#1558 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3256.#1559 I384 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|I384a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002404] 3257.#1560 V132 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|I384a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3257.#1561 I384 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|I384i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3261.#1562 BB234 PredBB233 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003100] 3269.#1563 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3270.#1564 I385 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|I385a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002414] 3271.#1565 I385 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|I385i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3272.#1566 V134 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002417] 3279.#1567 V134 Use Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3280.#1568 I386 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a|I386a|V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002418] 3281.#1569 V132 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a|I386a|V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3281.#1570 I386 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a|I386i|V132a|V134a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002422] 3285.#1571 V134 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|V134i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3286.#1572 I387 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|I387a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004130] 3299.#1573 I387 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a|I387i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3299.#1574 V132 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3299.#1575 V133 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133i| |V132a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002431] 3307.#1576 V132 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V132i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3308.#1577 I388 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I388a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004132] 3313.#1578 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |I388a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3313.#1579 I388 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I388i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004501] 3315.#0 V16 Move x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3315.#1580 BB235 PredBB233 |V36 a| | |V14 a| | | | |V144a|V20 a| |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004502] 3315.#0 V20 Move STK |V36 a| | |V14 a| | | | |V144a| | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004503] 3315.#0 V14 Move STK |V36 a| | | | | | | |V144a| | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004504] 3315.#0 V36 Move STK | | | | | | | | |V144a| | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004505] 3315.#0 V144 Move STK | | | | | | | | | | | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004293] 3321.#1581 x0 Fixd Keep x0 | | | | | | | | | | | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3321.#1582 V0 Use Copy x0 |V0 a| | | | | | | | | | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3322.#1583 x0 Fixd Keep x0 | | | | | | | | | | | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3322.#1584 I389 Def Alloc x0 |I389a| | | | | | | | | | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004294] 3325.#1585 x1 Fixd Keep x1 |I389a| | | | | | | | | | |V133a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3325.#1586 V133 Use * Copy x1 |I389a|V133i| | | | | | | | | |V133i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3326.#1587 x1 Fixd Keep x1 |I389a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3326.#1588 I390 Def Alloc x1 |I389a|I390a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003107] 3328.#1589 C391 Def Alloc x11 |I389a|I390a| | | | | | | | | |C391a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004295] 3329.#1590 x11 Fixd Keep x11 |I389a|I390a| | | | | | | | | |C391a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3329.#1591 C391 Use * Keep x11 |I389a|I390a| | | | | | | | | |C391i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3330.#1592 x11 Fixd Keep x11 |I389a|I390a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3330.#1593 I392 Def Alloc x11 |I389a|I390a| | | | | | | | | |I392a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002408] 3331.#1594 I393 Def Alloc x13 |I389a|I390a| | | | | | | | | |I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1595 x0 Fixd Keep x0 |I389a|I390a| | | | | | | | | |I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1596 I389 Use * Keep x0 |I389i|I390a| | | | | | | | | |I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1597 x1 Fixd Keep x1 | |I390a| | | | | | | | | |I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1598 I390 Use * Keep x1 | |I390i| | | | | | | | | |I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1599 x11 Fixd Keep x11 | | | | | | | | | | | |I392a| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1600 I392 Use * Keep x11 | | | | | | | | | | | |I392i| |I393a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3331.#1601 I393 Use * Keep x13 | | | | | | | | | | | | | |I393i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1602 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1603 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1604 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1605 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1606 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1607 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1608 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1609 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1610 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1611 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1612 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1613 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1614 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1615 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1616 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1617 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1618 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1619 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3332.#1620 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004506] 3333.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004507] 3333.#0 V14 Move x3 |V36 a| | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004508] 3333.#0 V16 Move x4 |V36 a| | |V14 a|V16 a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004509] 3333.#0 V144 Move x8 |V36 a| | |V14 a|V16 a| | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004510] 3333.#0 V20 Move x9 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3333.#1621 BB239 PredBB232 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000377] 3341.#1622 V16 Use Keep x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3341.#1623 V179 Use Keep x25 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004361] 3345.#0 V16 Move STK |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3345.#1624 BB240 PredBB112 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000386] 3361.#1625 V34 Use Keep x24 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3361.#1626 V16 Use ReLod x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3362.#1627 I394 Def Alloc x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |I394a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003641] 3363.#1628 I394 Use * Keep x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |I394i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3364.#1629 V173 Def Alloc x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000388] 3369.#1630 V173 Use Keep x11 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3373.#1631 BB236 PredBB240 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000399] 3379.#1632 V16 Use * Keep x4 |V36 a| | |V14 a|V16 i| | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3380.#1633 V53 Def Alloc x4 |V36 a| | |V14 a|V53 a| | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000395] 3387.#1634 V53 Use * Keep x4 |V36 a| | |V14 a|V53 i| | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3388.#1635 I395 Def Alloc x4 |V36 a| | |V14 a|I395a| | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000397] 3389.#1636 I395 Use * Keep x4 |V36 a| | |V14 a|I395i| | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3390.#1637 V16 Def Alloc x4 |V36 a| | |V14 a| | | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x4 |V36 a| | |V14 a| | | | |V144a|V20 a| |V173a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002481] 3393.#1638 V173 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V173i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3394.#1639 V137 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002442] 3401.#1640 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3402.#1641 I396 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |I396a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002444] 3403.#1642 I396 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |I396i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3404.#1643 V136 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002484] 3413.#1644 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3414.#1645 I397 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|I397a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002450] 3415.#1646 V136 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|I397a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3415.#1647 I397 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|I397i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3419.#1648 BB237 PredBB236 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003119] 3427.#1649 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3428.#1650 I398 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|I398a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002460] 3429.#1651 I398 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|I398i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3430.#1652 V138 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002463] 3437.#1653 V138 Use Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3438.#1654 I399 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a|I399a|V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002464] 3439.#1655 V136 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a|I399a|V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3439.#1656 I399 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a|I399i|V136a|V138a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002468] 3443.#1657 V138 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|V138i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3444.#1658 I400 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|I400a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004139] 3457.#1659 I400 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a|I400i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3457.#1660 V136 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3457.#1661 V137 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137i| |V136a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002477] 3465.#1662 V136 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V136i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3466.#1663 I401 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I401a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004141] 3471.#1664 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |I401a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3471.#1665 I401 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I401i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004511] 3473.#0 V16 Move x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3473.#1666 BB238 PredBB236 |V36 a| | |V14 a| | | | |V144a|V20 a| |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004512] 3473.#0 V20 Move STK |V36 a| | |V14 a| | | | |V144a| | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004513] 3473.#0 V14 Move STK |V36 a| | | | | | | |V144a| | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004514] 3473.#0 V36 Move STK | | | | | | | | |V144a| | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004515] 3473.#0 V144 Move STK | | | | | | | | | | | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004296] 3479.#1667 x0 Fixd Keep x0 | | | | | | | | | | | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3479.#1668 V0 Use Copy x0 |V0 a| | | | | | | | | | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3480.#1669 x0 Fixd Keep x0 | | | | | | | | | | | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3480.#1670 I402 Def Alloc x0 |I402a| | | | | | | | | | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004297] 3483.#1671 x1 Fixd Keep x1 |I402a| | | | | | | | | | |V137a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3483.#1672 V137 Use * Copy x1 |I402a|V137i| | | | | | | | | |V137i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3484.#1673 x1 Fixd Keep x1 |I402a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3484.#1674 I403 Def Alloc x1 |I402a|I403a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003126] 3486.#1675 C404 Def Alloc x11 |I402a|I403a| | | | | | | | | |C404a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004298] 3487.#1676 x11 Fixd Keep x11 |I402a|I403a| | | | | | | | | |C404a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3487.#1677 C404 Use * Keep x11 |I402a|I403a| | | | | | | | | |C404i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3488.#1678 x11 Fixd Keep x11 |I402a|I403a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3488.#1679 I405 Def Alloc x11 |I402a|I403a| | | | | | | | | |I405a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002454] 3489.#1680 I406 Def Alloc x13 |I402a|I403a| | | | | | | | | |I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1681 x0 Fixd Keep x0 |I402a|I403a| | | | | | | | | |I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1682 I402 Use * Keep x0 |I402i|I403a| | | | | | | | | |I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1683 x1 Fixd Keep x1 | |I403a| | | | | | | | | |I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1684 I403 Use * Keep x1 | |I403i| | | | | | | | | |I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1685 x11 Fixd Keep x11 | | | | | | | | | | | |I405a| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1686 I405 Use * Keep x11 | | | | | | | | | | | |I405i| |I406a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3489.#1687 I406 Use * Keep x13 | | | | | | | | | | | | | |I406i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1688 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1689 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1690 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1691 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1692 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1693 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1694 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1695 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1696 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1697 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1698 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1699 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1700 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1701 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1702 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1703 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1704 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1705 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3490.#1706 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004516] 3491.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004517] 3491.#0 V14 Move x3 |V36 a| | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004518] 3491.#0 V16 Move x4 |V36 a| | |V14 a|V16 a| | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004519] 3491.#0 V144 Move x8 |V36 a| | |V14 a|V16 a| | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004520] 3491.#0 V20 Move x9 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3491.#1707 BB241 PredBB240 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004521] 3491.#0 V16 Move STK |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3493.#1708 BB242 PredBB140 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002492] 3501.#1709 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3502.#1710 I407 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I407a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002494] 3503.#1711 I407 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I407i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3504.#1712 V140 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002531] 3513.#1713 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3514.#1714 I408 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|I408a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002500] 3515.#1715 V140 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|I408a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3515.#1716 I408 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|I408i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3519.#1717 BB243 PredBB242 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003138] 3527.#1718 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3528.#1719 I409 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|I409a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002509] 3529.#1720 I409 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|I409i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3530.#1721 V141 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002512] 3539.#1722 V141 Use Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3540.#1723 I410 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V140a|I410a|V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002513] 3541.#1724 V140 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V140a|I410a|V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3541.#1725 I410 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V140a|I410i|V18 a|V141a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002517] 3545.#1726 V141 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|V141i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3546.#1727 I411 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|I411a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004149] 3559.#1728 I411 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a|I411i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3559.#1729 V140 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3559.#1730 V18 Use * Keep x13 |V36 a| | | | | | | |V144a|V20 a| |V140a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002526] 3567.#1731 V140 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V140i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3568.#1732 I412 Def Alloc x13 |V36 a| | | | | | | |V144a|V20 a| | | |I412a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004151] 3573.#1733 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| | | |I412a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3573.#1734 I412 Use * Keep x13 |V36 a| | | | | | | |V144a|V20 a| | | |I412i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004522] 3575.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3575.#1735 BB244 PredBB215 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004299] 3581.#1736 x0 Fixd Keep x0 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3581.#1737 V0 Use Copy x0 |V0 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3582.#1738 x0 Fixd Keep x0 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3582.#1739 I413 Def Alloc x0 |I413a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004300] 3585.#1740 x1 Fixd Keep x1 |I413a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3585.#1741 V18 Use * Copy x1 |I413a|V18 i| | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3586.#1742 x1 Fixd Keep x1 |I413a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3586.#1743 I414 Def Alloc x1 |I413a|I414a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003145] 3588.#1744 C415 Def Alloc x11 |I413a|I414a| | | | | | | | | |C415a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004301] 3589.#1745 x11 Fixd Keep x11 |I413a|I414a| | | | | | | | | |C415a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3589.#1746 C415 Use * Keep x11 |I413a|I414a| | | | | | | | | |C415i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3590.#1747 x11 Fixd Keep x11 |I413a|I414a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3590.#1748 I416 Def Alloc x11 |I413a|I414a| | | | | | | | | |I416a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002503] 3591.#1749 I417 Def Alloc x13 |I413a|I414a| | | | | | | | | |I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1750 x0 Fixd Keep x0 |I413a|I414a| | | | | | | | | |I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1751 I413 Use * Keep x0 |I413i|I414a| | | | | | | | | |I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1752 x1 Fixd Keep x1 | |I414a| | | | | | | | | |I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1753 I414 Use * Keep x1 | |I414i| | | | | | | | | |I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1754 x11 Fixd Keep x11 | | | | | | | | | | | |I416a| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1755 I416 Use * Keep x11 | | | | | | | | | | | |I416i| |I417a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3591.#1756 I417 Use * Keep x13 | | | | | | | | | | | | | |I417i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1757 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1758 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1759 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1760 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1761 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1762 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1763 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1764 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1765 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1766 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1767 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1768 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1769 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1770 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1771 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1772 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1773 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1774 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3592.#1775 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1776 V16 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1777 V179 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1778 V4 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1779 V20 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1780 V34 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1781 V5 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1782 V8 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1783 V14 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1784 V36 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1785 V6 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1786 V12 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1787 V144 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1788 V9 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1789 V7 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1790 V143 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1791 V17 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3593.#1792 V21 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004523] 3593.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004524] 3593.#0 V14 Move x3 |V36 a| | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004525] 3593.#0 V144 Move x8 |V36 a| | |V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004526] 3593.#0 V20 Move x9 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3593.#1793 BB248 PredBB245 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | |V15 a| | | [000216] 3607.#1794 V1 Use Keep x21 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | |V15 a| | | 3608.#1795 I418 Def Alloc x2 | | |I418a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | |V15 a| | | [000219] 3621.#1796 I418 Use * Keep x2 | | |I418i| | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | |V15 a| | | 3621.#1797 V15 Use * Keep x26 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | |V15 i| | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3623.#1798 BB249 PredBB248 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a| | | | | | | | [000226] 3633.#1799 V1 Use * Keep x21 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 i| | | | | | | | 3634.#1800 I419 Def Alloc x2 | | |I419a| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | [000228] 3637.#1801 I419 Use * Keep x2 | | |I419i| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | 3638.#1802 I420 Def Alloc x2 | | |I420a| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | [002539] 3643.#1803 V0 Use Keep x19 | | |I420a| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | 3644.#1804 I421 Def Alloc x0 |I421a| |I420a| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | [000234] 3647.#1805 I421 Use * Keep x0 |I421i| |I420a| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | 3648.#1806 I422 Def Alloc x0 |I422a| |I420a| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | [003766] 3649.#1807 I420 Use * Keep x2 |I422a| |I420i| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | 3649.#1808 I422 Use * Keep x0 |I422i| | | | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | 3650.#1809 I423 Def Alloc x2 | | |I423a| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | [000229] 3651.#1810 I423 Use * Keep x2 | | |I423i| | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3653.#1811 BB251 PredBB249 | | | | | | | | | | | | | | | | | |V0 a|V3 a| | | | | | | | | [002541] 3663.#1812 V3 Use * Keep x20 | | | | | | | | | | | | | | | | | |V0 a|V3 i| | | | | | | | | 3664.#1813 I424 Def Alloc x2 | | |I424a| | | | | | | | | | | | | | |V0 a| | | | | | | | | | [004227] 3665.#1814 x2 Fixd Keep x2 | | |I424a| | | | | | | | | | | | | | |V0 a| | | | | | | | | | 3665.#1815 I424 Use * Keep x2 | | |I424i| | | | | | | | | | | | | | |V0 a| | | | | | | | | | 3666.#1816 x2 Fixd Keep x2 | | | | | | | | | | | | | | | | | |V0 a| | | | | | | | | | 3666.#1817 I425 Def Alloc x2 | | |I425a| | | | | | | | | | | | | | |V0 a| | | | | | | | | | [004228] 3669.#1818 x0 Fixd Keep x0 | | |I425a| | | | | | | | | | | | | | |V0 a| | | | | | | | | | 3669.#1819 V0 Use * Copy x0 |V0 i| |I425a| | | | | | | | | | | | | | |V0 i| | | | | | | | | | 3670.#1820 x0 Fixd Keep x0 | | |I425a| | | | | | | | | | | | | | | | | | | | | | | | | 3670.#1821 I426 Def Alloc x0 |I426a| |I425a| | | | | | | | | | | | | | | | | | | | | | | | | [003153] 3672.#1822 C427 Def Alloc x11 |I426a| |I425a| | | | | | | | |C427a| | | | | | | | | | | | | | | | [004229] 3673.#1823 x11 Fixd Keep x11 |I426a| |I425a| | | | | | | | |C427a| | | | | | | | | | | | | | | | 3673.#1824 C427 Use * Keep x11 |I426a| |I425a| | | | | | | | |C427i| | | | | | | | | | | | | | | | 3674.#1825 x11 Fixd Keep x11 |I426a| |I425a| | | | | | | | | | | | | | | | | | | | | | | | | 3674.#1826 I428 Def Alloc x11 |I426a| |I425a| | | | | | | | |I428a| | | | | | | | | | | | | | | | [000237] 3676.#1827 C429 Def Alloc x1 |I426a|C429a|I425a| | | | | | | | |I428a| | | | | | | | | | | | | | | | [004230] 3677.#1828 x1 Fixd Keep x1 |I426a|C429a|I425a| | | | | | | | |I428a| | | | | | | | | | | | | | | | 3677.#1829 C429 Use * Keep x1 |I426a|C429i|I425a| | | | | | | | |I428a| | | | | | | | | | | | | | | | 3678.#1830 x1 Fixd Keep x1 |I426a| |I425a| | | | | | | | |I428a| | | | | | | | | | | | | | | | 3678.#1831 I430 Def Alloc x1 |I426a|I430a|I425a| | | | | | | | |I428a| | | | | | | | | | | | | | | | [000241] 3679.#1832 I431 Def Alloc x3 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | | | | | | | | | | | | 3679.#1833 x2 Fixd Keep x2 |I426a|I430a|I425a|I431a| | | | | | | |I428a| | | | | | | | | | | | | | | | 3679.#1834 I425 Use * Keep x2 |I426a|I430a|I425i|I431a| | | | | | | |I428a| | | | | | | | | | | | | | | | 3679.#1835 x0 Fixd Keep x0 |I426a|I430a| |I431a| | | | | | | |I428a| | | | | | | | | | | | | | | | 3679.#1836 I426 Use * Keep x0 |I426i|I430a| |I431a| | | | | | | |I428a| | | | | | | | | | | | | | | | 3679.#1837 x11 Fixd Keep x11 | |I430a| |I431a| | | | | | | |I428a| | | | | | | | | | | | | | | | 3679.#1838 I428 Use * Keep x11 | |I430a| |I431a| | | | | | | |I428i| | | | | | | | | | | | | | | | 3679.#1839 x1 Fixd Keep x1 | |I430a| |I431a| | | | | | | | | | | | | | | | | | | | | | | | 3679.#1840 I430 Use * Keep x1 | |I430i| |I431a| | | | | | | | | | | | | | | | | | | | | | | | 3679.#1841 I431 Use * Keep x3 | | | |I431i| | | | | | | | | | | | | | | | | | | | | | | | 3680.#1842 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1843 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1844 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1845 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1846 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1847 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1848 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1849 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1850 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1851 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1852 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1853 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1854 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1855 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1856 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1857 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1858 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1859 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 3680.#1860 lr Kill Keep lr | | | | | | | | | | | | | | | | | | | | | | | | | | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3681.#1861 BB253 PredBB248 | | | | | | | | | | | | | | | | | | | | | | | | | | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3687.#1862 BB255 PredBB9 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a|V182a| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004199] 3691.#1863 V182 Use * Keep x14 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a|V182i| | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3692.#1864 I432 Def Alloc x0 |I432a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004200] 3694.#1865 I433 Def Alloc x1 |I432a|I433a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004201] 3695.#1866 I434 Def Alloc x11 |I432a|I433a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a|I434a| |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3695.#1867 I432 Use * Keep x0 |I432i|I433a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a|I434a| |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3695.#1868 I433 Use * Keep x1 | |I433i| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a|I434a| |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3697.#1869 BB17 PredBB255 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001432] 3705.#1870 V4 Use * Keep x27 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 i|V5 a| 3706.#1871 I435 Def Alloc x27 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|I435a|V5 a| [001434] 3707.#1872 I435 Use * Keep x27 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|I435i|V5 a| 3708.#1873 V4 Def Alloc x27 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004368] 3709.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3709.#1874 BB30 PredBB255 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001427] 3717.#1875 V13 Use * Keep x8 | | | | | |V9 a|V10 a|V12 a|V13 i|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3718.#1876 I436 Def Alloc x8 | | | | | |V9 a|V10 a|V12 a|I436a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001429] 3719.#1877 I436 Use * Keep x8 | | | | | |V9 a|V10 a|V12 a|I436i|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3720.#1878 V13 Def Alloc x8 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004375] 3721.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3721.#1879 BB31 PredBB255 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001449] 3743.#1880 V22 Use Keep x9 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3743.#1881 V16 Use Keep x10 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3744.#1882 I437 Def Alloc x0 |I437a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [003625] 3745.#1883 I437 Use * Keep x0 |I437i| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3746.#1884 V171 Def Alloc x0 |V171a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001441] 3755.#1885 V16 Use Keep x10 |V171a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3755.#1886 V179 Use Keep x25 |V171a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3755.#1887 V171 Use Keep x0 |V171a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3757.#1888 V18 DDef |V171a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3757.#1889 V171 DDef |V171a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004316] 3757.#0 V16 Move x1 |V171a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3757.#1890 BB32 PredBB7 |V171a|V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001461] 3765.#1891 V16 Use * Keep x1 |V171a|V16 i| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3766.#1892 V74 Def Alloc x1 |V171a|V74 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001457] 3773.#1893 V74 Use * Keep x1 |V171a|V74 i| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3774.#1894 I438 Def Alloc x1 |V171a|I438a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001459] 3775.#1895 I438 Use * Keep x1 |V171a|I438i| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3776.#1896 V16 Def Alloc x2 |V171a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x2 |V171a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001470] 3781.#1897 V171 Use * Keep x0 |V171i| | | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3781.#1898 V18 Use Keep x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001471] 3785.#1899 V18 ExpU | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004317] 3785.#0 V16 Move x10 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |V18 a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3785.#1900 BB34 PredBB255 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004377] 3785.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3787.#1901 BB256 PredBB10 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183a| | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004210] 3791.#1902 V183 Use * Keep x12 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| |V183i| | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3792.#1903 I439 Def Alloc x13 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004211] 3794.#1904 I440 Def Alloc x0 |I440a| | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004212] 3795.#1905 I441 Def Alloc x1 |I440a|I441a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439a| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3795.#1906 I439 Use * Keep x13 |I440a|I441a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | |I439i| | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3795.#1907 I440 Use * Keep x0 |I440i|I441a| | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3797.#1908 BB18 PredBB256 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001374] 3804.#1909 C442 Def Alloc x4 | | | | |C442a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001375] 3805.#1910 V6 Use ReLod x3 | | | |V6 a|C442a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| Keep x3 | | | |V6 a|C442a|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3805.#1911 C442 Use * Keep x4 | | | |V6 a|C442i|V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3809.#1912 BB19 PredBB18 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001387] 3815.#1913 V4 Use Keep x27 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3816.#1914 V6 Def Alloc x3 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3817.#1915 BB20 PredBB18 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001379] 3825.#1916 V4 Use * Keep x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 i|V5 a| 3826.#1917 I443 Def Alloc x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|I443a|V5 a| [001381] 3827.#1918 I443 Use * Keep x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|I443i|V5 a| 3828.#1919 V4 Def Alloc x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001384] 3833.#1920 V4 Use Keep x27 | | | |V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3834.#1921 V7 Def Alloc x2 | | |V7 a|V6 a| |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004369] 3835.#0 V6 Move STK | | |V7 a| | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004370] 3835.#0 V7 Move STK | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004372] 3835.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3835.#1922 BB21 PredBB256 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001390] 3843.#1923 V5 Use Keep x28 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001391] 3847.#1924 V5 ExpU | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004312] 3847.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3847.#1925 BB22 PredBB7 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a| | [001394] 3853.#1926 V4 Use Keep x27 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a| | 3854.#1927 V5 Def Alloc x28 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3855.#1928 BB23 PredBB256 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001398] 3873.#1929 V4 Use Keep x27 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3873.#1930 V5 Use Keep x28 | | | | | |V9 a|V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004314] 3875.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3875.#1931 BB24 PredBB7 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001405] 3885.#1932 V10 Use Keep x6 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3889.#1933 BB26 PredBB24 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001415] 3897.#1934 V10 Use Keep x6 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3897.#1935 V4 Use Keep x27 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3901.#1936 BB27 PredBB26 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001422] 3909.#1937 V11 Use * Keep x22 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3910.#1938 I444 Def Alloc x22 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|I444a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001424] 3911.#1939 I444 Use * Keep x22 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|I444i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3912.#1940 V11 Def Alloc x22 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3913.#1941 V10 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3913.#1942 V12 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3913.#1943 V11 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3913.#1944 BB28 PredBB26 | |V16 a| | | |V9 a| | |V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [002612] 3918.#1945 C445 Def Alloc x7 | |V16 a| | | |V9 a| |C445a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001419] 3919.#1946 C445 Use * Keep x7 | |V16 a| | | |V9 a| |C445i|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3920.#1947 V12 Def Alloc x22 | |V16 a| | | |V9 a| | |V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| Spill x22 | |V16 a| | | |V9 a| | |V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [004373] 3921.#0 V12 Move x7 | |V16 a| | | |V9 a| |V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3921.#1948 BB29 PredBB24 | |V16 a| | | |V9 a| |V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001409] 3927.#1949 V4 Use Keep x27 | |V16 a| | | |V9 a| |V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3928.#1950 V10 Def Alloc x6 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a| |V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001410] 3932.#1951 C446 Def Alloc x22 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|C446a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| [001412] 3933.#1952 C446 Use * Keep x22 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|C446i|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3934.#1953 V11 Def Alloc x22 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1954 V22 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1955 V13 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1956 V10 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1957 V11 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| 3935.#1958 V180 ExpU | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3935.#1959 BB257 PredBB137 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V184a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004248] 3939.#1960 V184 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a|V184i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3940.#1961 I447 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I447a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004249] 3942.#1962 I448 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |I447a| |V18 a|I448a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004250] 3943.#1963 I449 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |I447a|I449a|V18 a|I448a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3943.#1964 I447 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I447i|I449a|V18 a|I448a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3943.#1965 I448 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | |I449a|V18 a|I448i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3945.#1966 BB145 PredBB257 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000641] 3953.#1967 V14 Use ReLod x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3957.#1968 BB146 PredBB145 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000733] 3965.#1969 V14 Use * Keep x3 |V36 a| | |V14 i| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3966.#1970 I450 Def Alloc x3 |V36 a| | |I450a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000735] 3967.#1971 I450 Use * Keep x3 |V36 a| | |I450i| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3968.#1972 V14 Def Alloc x3 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x3 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000738] 3975.#1973 V8 Use ReLod x2 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3975.#1974 V6 Use Keep x22 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3979.#1975 BB147 PredBB146 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000749] 3986.#1976 V58 Def Alloc x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V58 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3987.#1977 BB148 PredBB146 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000740] 3992.#1978 C451 Def Alloc x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |C451a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000742] 3993.#1979 C451 Use * Keep x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |C451i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 3994.#1980 V58 Def Alloc x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V58 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 3995.#1981 BB149 PredBB147 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V58 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002850] 3999.#1982 V58 Use * Keep x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V58 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4000.#1983 I452 Def Alloc x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |I452a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000746] 4001.#1984 I452 Use * Keep x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |I452i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4002.#1985 V18 Def Alloc x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4003.#1986 BB150 PredBB145 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000644] 4009.#1987 V36 Use Keep x0 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4010.#1988 I453 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I453a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000646] 4013.#1989 I453 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I453i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4015.#1990 BB151 PredBB150 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000721] 4023.#1991 V8 Use ReLod x2 |V36 a| |V8 a|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 |V36 a| |V8 i|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x2 |V36 a| |V8 i|V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4023.#1992 V7 Use ReLod x1 |V36 a|V7 a| |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x1 |V36 a|V7 i| |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x1 |V36 a|V7 i| |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4027.#1993 BB152 PredBB151 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000729] 4034.#1994 V57 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V57 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4035.#1995 BB153 PredBB151 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000723] 4040.#1996 C454 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |C454a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000725] 4041.#1997 C454 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |C454i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4042.#1998 V57 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V57 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4043.#1999 BB154 PredBB150 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000656] 4049.#2000 V36 Use * Keep x0 |V36 i| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4050.#2001 V56 Def Alloc x11 | | | |V14 a| | | | |V144a|V20 a| |V56 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000652] 4057.#2002 V56 Use Keep x11 | | | |V14 a| | | | |V144a|V20 a| |V56 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4058.#2003 I455 Def Alloc x0 |I455a| | |V14 a| | | | |V144a|V20 a| |V56 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000654] 4059.#2004 I455 Use * Keep x0 |I455i| | |V14 a| | | | |V144a|V20 a| |V56 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4060.#2005 V36 Def Alloc x0 | | | |V14 a| | | | |V144a|V20 a| |V56 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x0 | | | |V14 a| | | | |V144a|V20 a| |V56 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000658] 4063.#2006 V56 Use * Keep x11 | | | |V14 a| | | | |V144a|V20 a| |V56 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4064.#2007 I456 Def Alloc x11 | | | |V14 a| | | | |V144a|V20 a| |I456a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000660] 4065.#2008 I456 Use * Keep x11 | | | |V14 a| | | | |V144a|V20 a| |I456i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4066.#2009 V57 Def Alloc x11 | | | |V14 a| | | | |V144a|V20 a| |V57 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004420] 4067.#0 V36 Move x0 |V36 a| | |V14 a| | | | |V144a|V20 a| |V57 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4067.#2010 BB155 PredBB152 |V36 a| | |V14 a| | | | |V144a|V20 a| |V57 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002851] 4071.#2011 V57 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V57 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4072.#2012 I457 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I457a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000664] 4073.#2013 I457 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |I457i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4074.#2014 V18 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004421] 4075.#0 V14 Move STK |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004422] 4075.#0 V8 Move x2 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4075.#2015 BB156 PredBB149 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000667] 4083.#2016 V18 Use Keep x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4085.#2017 BB157 PredBB156 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001903] 4093.#2018 V0 Use Keep x19 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4094.#2019 I458 Def Alloc x11 |V36 a| |V8 a| | | | | |V144a|V20 a| |I458a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001905] 4095.#2020 I458 Use * Keep x11 |V36 a| |V8 a| | | | | |V144a|V20 a| |I458i| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4096.#2021 V99 Def Alloc x11 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001942] 4105.#2022 V0 Use Keep x19 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4106.#2023 I459 Def Alloc x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|I459a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001911] 4107.#2024 V99 Use Keep x11 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|I459a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4107.#2025 I459 Use * Keep x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|I459i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4111.#2026 BB158 PredBB157 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002863] 4119.#2027 V0 Use Keep x19 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4120.#2028 I460 Def Alloc x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|I460a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001920] 4121.#2029 I460 Use * Keep x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|I460i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4122.#2030 V100 Def Alloc x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001923] 4131.#2031 V100 Use Keep x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4132.#2032 I461 Def Alloc x12 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a|I461a|V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001924] 4133.#2033 V99 Use Keep x11 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a|I461a|V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4133.#2034 I461 Use * Keep x12 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a|I461i|V18 a|V100a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001928] 4137.#2035 V100 Use * Keep x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|V100i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4138.#2036 I462 Def Alloc x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|I462a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004002] 4151.#2037 I462 Use * Keep x14 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a|I462i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4151.#2038 V99 Use Keep x11 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4151.#2039 V18 Use * Keep x13 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 a| |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001937] 4159.#2040 V99 Use * Keep x11 |V36 a| |V8 a| | | | | |V144a|V20 a| |V99 i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4160.#2041 I463 Def Alloc x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |I463a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004004] 4165.#2042 V0 Use Keep x19 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |I463a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4165.#2043 I463 Use * Keep x13 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |I463i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4167.#2044 BB159 PredBB157 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004423] 4167.#0 V20 Move STK |V36 a| |V8 a| | | | | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004424] 4167.#0 V8 Move STK |V36 a| | | | | | | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004425] 4167.#0 V36 Move STK | | | | | | | | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004426] 4167.#0 V144 Move STK | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004262] 4173.#2045 x0 Fixd Keep x0 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4173.#2046 V0 Use Copy x0 |V0 a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4174.#2047 x0 Fixd Keep x0 | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4174.#2048 I464 Def Alloc x0 |I464a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004263] 4177.#2049 x1 Fixd Keep x1 |I464a| | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4177.#2050 V18 Use * Copy x1 |I464a|V18 i| | | | | | | | | | | |V18 i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4178.#2051 x1 Fixd Keep x1 |I464a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4178.#2052 I465 Def Alloc x1 |I464a|I465a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002870] 4180.#2053 C466 Def Alloc x11 |I464a|I465a| | | | | | | | | |C466a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004264] 4181.#2054 x11 Fixd Keep x11 |I464a|I465a| | | | | | | | | |C466a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4181.#2055 C466 Use * Keep x11 |I464a|I465a| | | | | | | | | |C466i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4182.#2056 x11 Fixd Keep x11 |I464a|I465a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4182.#2057 I467 Def Alloc x11 |I464a|I465a| | | | | | | | | |I467a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001914] 4183.#2058 I468 Def Alloc x13 |I464a|I465a| | | | | | | | | |I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2059 x0 Fixd Keep x0 |I464a|I465a| | | | | | | | | |I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2060 I464 Use * Keep x0 |I464i|I465a| | | | | | | | | |I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2061 x1 Fixd Keep x1 | |I465a| | | | | | | | | |I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2062 I465 Use * Keep x1 | |I465i| | | | | | | | | |I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2063 x11 Fixd Keep x11 | | | | | | | | | | | |I467a| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2064 I467 Use * Keep x11 | | | | | | | | | | | |I467i| |I468a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4183.#2065 I468 Use * Keep x13 | | | | | | | | | | | | | |I468i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2066 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2067 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2068 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2069 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2070 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2071 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2072 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2073 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2074 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2075 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2076 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2077 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2078 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2079 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2080 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2081 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2082 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2083 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4184.#2084 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004427] 4185.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004428] 4185.#0 V8 Move x2 |V36 a| |V8 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004429] 4185.#0 V144 Move x8 |V36 a| |V8 a| | | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004430] 4185.#0 V20 Move x9 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4185.#2085 BB160 PredBB158 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000680] 4203.#2086 V12 Use ReLod x7 |V36 a| |V8 a| | | | |V12 a|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x7 |V36 a| |V8 a| | | | |V12 i|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x7 |V36 a| |V8 a| | | | |V12 i|V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4203.#2087 V8 Use Keep x2 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4205.#2088 BB161 PredBB160 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000697] 4215.#2089 V20 Use Keep x9 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4215.#2090 V144 Use Keep x8 |V36 a| |V8 a| | | | | |V144i|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x8 |V36 a| |V8 a| | | | | |V144i|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002871] 4229.#2091 V143 Use ReLod x6 |V36 a| |V8 a| | | |V143a| | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x6 |V36 a| |V8 a| | | |V143i| | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x6 |V36 a| |V8 a| | | |V143i| | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4229.#2092 V20 Use Keep x9 |V36 a| |V8 a| | | | | | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4230.#2093 I469 Def Alloc x11 |V36 a| |V8 a| | | | | | |V20 a| |I469a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000706] 4233.#2094 I469 Use * Keep x11 |V36 a| |V8 a| | | | | | |V20 a| |I469i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4234.#2095 I470 Def Alloc x11 |V36 a| |V8 a| | | | | | |V20 a| |I470a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000688] 4247.#2096 I470 Use * Keep x11 |V36 a| |V8 a| | | | | | |V20 a| |I470i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4247.#2097 V8 Use Keep x2 |V36 a| |V8 i| | | | | | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x2 |V36 a| |V8 i| | | | | | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4247.#2098 V20 Use Keep x9 |V36 a| | | | | | | | |V20 i| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x9 |V36 a| | | | | | | | |V20 i| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4249.#2099 BB163 PredBB161 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001946] 4259.#2100 V3 Use Keep x20 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4260.#2101 I471 Def Alloc x11 |V36 a| | | | | | | | | | |I471a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001999] 4261.#2102 I471 Use * Keep x11 |V36 a| | | | | | | | | | |I471i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4262.#2103 V102 Def Alloc x11 |V36 a| | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001950] 4269.#2104 V102 Use Keep x11 |V36 a| | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4271.#2105 BB165 PredBB163 |V36 a| | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001952] 4279.#2106 V0 Use Keep x19 |V36 a| | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4280.#2107 I472 Def Alloc x13 |V36 a| | | | | | | | | | |V102a| |I472a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001954] 4281.#2108 I472 Use * Keep x13 |V36 a| | | | | | | | | | |V102a| |I472i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4282.#2109 V103 Def Alloc x13 |V36 a| | | | | | | | | | |V102a| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001956] 4289.#2110 V102 Use Keep x11 |V36 a| | | | | | | | | | |V102a| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4290.#2111 I473 Def Alloc x14 |V36 a| | | | | | | | | | |V102a| |V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002002] 4301.#2112 V0 Use Keep x19 |V36 a| | | | | | | | | | |V102a| |V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4302.#2113 I474 Def Alloc x12 |V36 a| | | | | | | | | | |V102a|I474a|V103a|I473a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001959] 4307.#2114 I473 Use * Keep x14 |V36 a| | | | | | | | | | |V102a|I474a|V103a|I473i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4307.#2115 V103 Use Keep x13 |V36 a| | | | | | | | | | |V102a|I474a|V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4307.#2116 I474 Use * Keep x12 |V36 a| | | | | | | | | | |V102a|I474i|V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4309.#2117 BB166 PredBB165 |V36 a| | | | | | | | | | |V102a| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002885] 4319.#2118 V0 Use Keep x19 |V36 a| | | | | | | | | | |V102a| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4320.#2119 I475 Def Alloc x14 |V36 a| | | | | | | | | | |V102a| |V103a|I475a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001975] 4321.#2120 I475 Use * Keep x14 |V36 a| | | | | | | | | | |V102a| |V103a|I475i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4322.#2121 V104 Def Alloc x14 |V36 a| | | | | | | | | | |V102a| |V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001978] 4331.#2122 V104 Use Keep x14 |V36 a| | | | | | | | | | |V102a| |V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4332.#2123 I476 Def Alloc x12 |V36 a| | | | | | | | | | |V102a|I476a|V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001979] 4333.#2124 V103 Use Keep x13 |V36 a| | | | | | | | | | |V102a|I476a|V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4333.#2125 I476 Use * Keep x12 |V36 a| | | | | | | | | | |V102a|I476i|V103a|V104a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001983] 4337.#2126 V104 Use * Keep x14 |V36 a| | | | | | | | | | |V102a| |V103a|V104i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4338.#2127 I477 Def Alloc x14 |V36 a| | | | | | | | | | |V102a| |V103a|I477a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001982] 4345.#2128 V103 Use Keep x13 |V36 a| | | | | | | | | | |V102a| |V103a|I477a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4346.#2129 I478 Def Alloc x12 |V36 a| | | | | | | | | | |V102a|I478a|V103a|I477a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001984] 4347.#2130 I477 Use * Keep x14 |V36 a| | | | | | | | | | |V102a|I478a|V103a|I477i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4347.#2131 I478 Use * Keep x12 |V36 a| | | | | | | | | | |V102a|I478i|V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4348.#2132 I479 Def Alloc x14 |V36 a| | | | | | | | | | |V102a| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002892] 4355.#2133 V102 Use Keep x11 |V36 a| | | | | | | | | | |V102a| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4356.#2134 I480 Def Alloc x12 |V36 a| | | | | | | | | | |V102a|I480a|V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002893] 4357.#2135 I480 Use * Keep x12 |V36 a| | | | | | | | | | |V102a|I480i|V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002902] 4363.#2136 V102 Use * Keep x11 |V36 a| | | | | | | | | | |V102i| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4364.#2137 I481 Def Alloc x11 |V36 a| | | | | | | | | | |I481a| |V103a|I479a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004017] 4365.#2138 I479 Use * Keep x14 |V36 a| | | | | | | | | | |I481a| |V103a|I479i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4365.#2139 I481 Use * Keep x11 |V36 a| | | | | | | | | | |I481i| |V103a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001995] 4373.#2140 V103 Use * Keep x13 |V36 a| | | | | | | | | | | | |V103i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4374.#2141 I482 Def Alloc x11 |V36 a| | | | | | | | | | |I482a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004019] 4379.#2142 V0 Use Keep x19 |V36 a| | | | | | | | | | |I482a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4379.#2143 I482 Use * Keep x11 |V36 a| | | | | | | | | | |I482i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4381.#2144 BB168 PredBB165 |V36 a| | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004431] 4381.#0 V36 Move STK | | | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004265] 4387.#2145 x0 Fixd Keep x0 | | | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4387.#2146 V0 Use Copy x0 |V0 a| | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4388.#2147 x0 Fixd Keep x0 | | | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4388.#2148 I483 Def Alloc x0 |I483a| | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004266] 4391.#2149 x1 Fixd Keep x1 |I483a| | | | | | | | | | |V102a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4391.#2150 V102 Use * Copy x1 |I483a|V102i| | | | | | | | | |V102i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4392.#2151 x1 Fixd Keep x1 |I483a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4392.#2152 I484 Def Alloc x1 |I483a|I484a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002905] 4394.#2153 C485 Def Alloc x11 |I483a|I484a| | | | | | | | | |C485a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004267] 4395.#2154 x11 Fixd Keep x11 |I483a|I484a| | | | | | | | | |C485a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4395.#2155 C485 Use * Keep x11 |I483a|I484a| | | | | | | | | |C485i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4396.#2156 x11 Fixd Keep x11 |I483a|I484a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4396.#2157 I486 Def Alloc x11 |I483a|I484a| | | | | | | | | |I486a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [001962] 4397.#2158 I487 Def Alloc x13 |I483a|I484a| | | | | | | | | |I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2159 x0 Fixd Keep x0 |I483a|I484a| | | | | | | | | |I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2160 I483 Use * Keep x0 |I483i|I484a| | | | | | | | | |I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2161 x1 Fixd Keep x1 | |I484a| | | | | | | | | |I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2162 I484 Use * Keep x1 | |I484i| | | | | | | | | |I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2163 x11 Fixd Keep x11 | | | | | | | | | | | |I486a| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2164 I486 Use * Keep x11 | | | | | | | | | | | |I486i| |I487a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4397.#2165 I487 Use * Keep x13 | | | | | | | | | | | | | |I487i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2166 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2167 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2168 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2169 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2170 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2171 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2172 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2173 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2174 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2175 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2176 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2177 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2178 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2179 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2180 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2181 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2182 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2183 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4398.#2184 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004432] 4399.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4399.#2185 BB169 PredBB163 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000716] 4407.#2186 V20 Use * ReLod x9 |V36 a| | | | | | | | |V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x9 |V36 a| | | | | | | | |V20 i| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4408.#2187 I488 Def Alloc x9 |V36 a| | | | | | | | |I488a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000718] 4409.#2188 I488 Use * Keep x9 |V36 a| | | | | | | | |I488i| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4410.#2189 V20 Def Alloc x9 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x9 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004433] 4411.#0 V8 Move x2 |V36 a| |V8 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004434] 4411.#0 V144 Move x8 |V36 a| |V8 a| | | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004435] 4411.#0 V20 Move x9 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4411.#2190 BB170 PredBB156 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000671] 4419.#2191 V8 Use * Keep x2 |V36 a| |V8 i| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4420.#2192 I489 Def Alloc x2 |V36 a| |I489a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000673] 4421.#2193 I489 Use * Keep x2 |V36 a| |I489i| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4422.#2194 V8 Def Alloc x2 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x2 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004436] 4423.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4423.#2195 BB186 PredBB257 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002126] 4431.#2196 V3 Use Keep x20 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4432.#2197 I490 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I490a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002179] 4433.#2198 I490 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I490i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4434.#2199 V114 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002130] 4441.#2200 V114 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4443.#2201 V114 DDef |V36 a| | | | | | | |V144a|V20 a| |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004344] 4443.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4443.#2202 BB187 PredBB112 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002132] 4451.#2203 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4452.#2204 I491 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |I491a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002134] 4453.#2205 I491 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |I491i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4454.#2206 V115 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002136] 4461.#2207 V114 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4462.#2208 I492 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002182] 4473.#2209 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4474.#2210 I493 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I493a|V115a|I492a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002139] 4479.#2211 I492 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I493a|V115a|I492i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4479.#2212 V115 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I493a|V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4479.#2213 I493 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I493i|V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4481.#2214 BB188 PredBB187 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002986] 4491.#2215 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4492.#2216 I494 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|I494a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002155] 4493.#2217 I494 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|I494i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4494.#2218 V116 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002158] 4503.#2219 V116 Use Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4504.#2220 I495 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I495a|V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002159] 4505.#2221 V115 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I495a|V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4505.#2222 I495 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I495i|V115a|V116a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002163] 4509.#2223 V116 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|V116i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4510.#2224 I496 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|I496a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002162] 4517.#2225 V115 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|I496a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4518.#2226 I497 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I497a|V115a|I496a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002164] 4519.#2227 I496 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I497a|V115a|I496i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4519.#2228 I497 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I497i|V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4520.#2229 I498 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002993] 4527.#2230 V114 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4528.#2231 I499 Def Alloc x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I499a|V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002994] 4529.#2232 I499 Use * Keep x12 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a|I499i|V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003003] 4535.#2233 V114 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114i| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4536.#2234 I500 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I500a| |V115a|I498a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004056] 4537.#2235 I498 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a| |I500a| |V115a|I498i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4537.#2236 I500 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I500i| |V115a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002175] 4545.#2237 V115 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V115i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4546.#2238 I501 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I501a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004058] 4551.#2239 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |I501a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4551.#2240 I501 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I501i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4553.#2241 BB190 PredBB187 |V36 a| | |V14 a| | | | |V144a|V20 a| |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004454] 4553.#0 V20 Move STK |V36 a| | |V14 a| | | | |V144a| | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004455] 4553.#0 V14 Move STK |V36 a| | | | | | | |V144a| | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004456] 4553.#0 V36 Move STK | | | | | | | | |V144a| | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004457] 4553.#0 V144 Move STK | | | | | | | | | | | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004274] 4559.#2242 x0 Fixd Keep x0 | | | | | | | | | | | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4559.#2243 V0 Use Copy x0 |V0 a| | | | | | | | | | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4560.#2244 x0 Fixd Keep x0 | | | | | | | | | | | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4560.#2245 I502 Def Alloc x0 |I502a| | | | | | | | | | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004275] 4563.#2246 x1 Fixd Keep x1 |I502a| | | | | | | | | | |V114a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4563.#2247 V114 Use * Copy x1 |I502a|V114i| | | | | | | | | |V114i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4564.#2248 x1 Fixd Keep x1 |I502a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4564.#2249 I503 Def Alloc x1 |I502a|I503a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003006] 4566.#2250 C504 Def Alloc x11 |I502a|I503a| | | | | | | | | |C504a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004276] 4567.#2251 x11 Fixd Keep x11 |I502a|I503a| | | | | | | | | |C504a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4567.#2252 C504 Use * Keep x11 |I502a|I503a| | | | | | | | | |C504i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4568.#2253 x11 Fixd Keep x11 |I502a|I503a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4568.#2254 I505 Def Alloc x11 |I502a|I503a| | | | | | | | | |I505a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002142] 4569.#2255 I506 Def Alloc x13 |I502a|I503a| | | | | | | | | |I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2256 x0 Fixd Keep x0 |I502a|I503a| | | | | | | | | |I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2257 I502 Use * Keep x0 |I502i|I503a| | | | | | | | | |I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2258 x1 Fixd Keep x1 | |I503a| | | | | | | | | |I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2259 I503 Use * Keep x1 | |I503i| | | | | | | | | |I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2260 x11 Fixd Keep x11 | | | | | | | | | | | |I505a| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2261 I505 Use * Keep x11 | | | | | | | | | | | |I505i| |I506a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4569.#2262 I506 Use * Keep x13 | | | | | | | | | | | | | |I506i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2263 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2264 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2265 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2266 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2267 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2268 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2269 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2270 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2271 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2272 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2273 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2274 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2275 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2276 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2277 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2278 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2279 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2280 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4570.#2281 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004458] 4571.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004459] 4571.#0 V14 Move x3 |V36 a| | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004460] 4571.#0 V144 Move x8 |V36 a| | |V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004461] 4571.#0 V20 Move x9 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4571.#2282 BB194 PredBB257 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000756] 4579.#2283 V16 Use ReLod x4 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4579.#2284 V179 Use Keep x25 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4583.#2285 BB195 PredBB194 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000788] 4599.#2286 V34 Use Keep x24 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4599.#2287 V16 Use Keep x4 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4600.#2288 I507 Def Alloc x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a|I507a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003631] 4601.#2289 I507 Use * Keep x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a|I507i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4602.#2290 V172 Def Alloc x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000790] 4607.#2291 V172 Use Keep x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4609.#2292 BB196 PredBB195 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000801] 4617.#2293 V172 Use Keep x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 a|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4617.#2294 V18 Use Keep x13 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 i|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x13 |V36 a| | | |V16 a| | | |V144a|V20 a| | | |V18 i|V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4621.#2295 BB191 PredBB196 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000812] 4627.#2296 V16 Use * Keep x4 |V36 a| | | |V16 i| | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4628.#2297 V59 Def Alloc x4 |V36 a| | | |V59 a| | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000808] 4635.#2298 V59 Use * Keep x4 |V36 a| | | |V59 i| | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4636.#2299 I508 Def Alloc x4 |V36 a| | | |I508a| | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000810] 4637.#2300 I508 Use * Keep x4 |V36 a| | | |I508i| | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4638.#2301 V16 Def Alloc x4 |V36 a| | | | | | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x4 |V36 a| | | | | | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002225] 4641.#2302 V172 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | | | |V172i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4642.#2303 V119 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002186] 4649.#2304 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4650.#2305 I509 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I509a| | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002188] 4651.#2306 I509 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I509i| | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4652.#2307 V118 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |V118a| | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002228] 4661.#2308 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| |V118a| | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4662.#2309 I510 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|I510a| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002194] 4663.#2310 V118 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V118a|I510a| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4663.#2311 I510 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|I510i| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4667.#2312 BB192 PredBB191 |V36 a| | | | | | | |V144a|V20 a| |V118a| | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003018] 4675.#2313 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| |V118a| | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4676.#2314 I511 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|I511a| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002204] 4677.#2315 I511 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|I511i| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4678.#2316 V120 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|V120a| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002207] 4685.#2317 V120 Use Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|V120a| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4686.#2318 I512 Def Alloc x15 |V36 a| | | | | | | |V144a|V20 a| |V118a|V120a| |V119a|I512a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002208] 4687.#2319 V118 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V118a|V120a| |V119a|I512a| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4687.#2320 I512 Use * Keep x15 |V36 a| | | | | | | |V144a|V20 a| |V118a|V120a| |V119a|I512i| |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002212] 4691.#2321 V120 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|V120i| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4692.#2322 I513 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|I513a| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004065] 4705.#2323 I513 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| |V118a|I513i| |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4705.#2324 V118 Use Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V118a| | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4705.#2325 V119 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| |V118a| | |V119i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002221] 4713.#2326 V118 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |V118i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4714.#2327 I514 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| | | | |I514a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004067] 4719.#2328 V0 Use Keep x19 |V36 a| | | | | | | |V144a|V20 a| | | | |I514a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4719.#2329 I514 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | | | |I514i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004462] 4721.#0 V18 Move x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4721.#2330 BB193 PredBB191 |V36 a| | | | | | | |V144a|V20 a| | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004463] 4721.#0 V20 Move STK |V36 a| | | | | | | |V144a| | | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004464] 4721.#0 V36 Move STK | | | | | | | | |V144a| | | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004465] 4721.#0 V144 Move STK | | | | | | | | | | | | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004277] 4727.#2331 x0 Fixd Keep x0 | | | | | | | | | | | | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4727.#2332 V0 Use Copy x0 |V0 a| | | | | | | | | | | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4728.#2333 x0 Fixd Keep x0 | | | | | | | | | | | | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4728.#2334 I515 Def Alloc x0 |I515a| | | | | | | | | | | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004278] 4731.#2335 x1 Fixd Keep x1 |I515a| | | | | | | | | | | | | |V119a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4731.#2336 V119 Use * Copy x1 |I515a|V119i| | | | | | | | | | | | |V119i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4732.#2337 x1 Fixd Keep x1 |I515a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4732.#2338 I516 Def Alloc x1 |I515a|I516a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003025] 4734.#2339 C517 Def Alloc x11 |I515a|I516a| | | | | | | | | |C517a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004279] 4735.#2340 x11 Fixd Keep x11 |I515a|I516a| | | | | | | | | |C517a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4735.#2341 C517 Use * Keep x11 |I515a|I516a| | | | | | | | | |C517i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4736.#2342 x11 Fixd Keep x11 |I515a|I516a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4736.#2343 I518 Def Alloc x11 |I515a|I516a| | | | | | | | | |I518a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002198] 4737.#2344 I519 Def Alloc x14 |I515a|I516a| | | | | | | | | |I518a| | |I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2345 x0 Fixd Keep x0 |I515a|I516a| | | | | | | | | |I518a| | |I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2346 I515 Use * Keep x0 |I515i|I516a| | | | | | | | | |I518a| | |I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2347 x1 Fixd Keep x1 | |I516a| | | | | | | | | |I518a| | |I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2348 I516 Use * Keep x1 | |I516i| | | | | | | | | |I518a| | |I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2349 x11 Fixd Keep x11 | | | | | | | | | | | |I518a| | |I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2350 I518 Use * Keep x11 | | | | | | | | | | | |I518i| | |I519a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4737.#2351 I519 Use * Keep x14 | | | | | | | | | | | | | | |I519i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2352 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2353 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2354 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2355 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2356 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2357 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2358 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2359 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2360 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2361 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2362 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2363 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2364 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2365 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2366 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2367 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2368 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2369 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4738.#2370 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4739.#2371 V18 ExpU | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004466] 4739.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004467] 4739.#0 V144 Move x8 |V36 a| | | | | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004468] 4739.#0 V20 Move x9 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004469] 4739.#0 V18 Move x13 |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4739.#2372 BB197 PredBB194 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000763] 4747.#2373 V16 Use Keep x4 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4747.#2374 V179 Use Keep x25 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4751.#2375 BB198 PredBB195 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000772] 4767.#2376 V34 Use Keep x24 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4767.#2377 V16 Use Keep x4 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4768.#2378 I520 Def Alloc x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | |I520a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [003636] 4769.#2379 I520 Use * Keep x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | |I520i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4770.#2380 V172 Def Alloc x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | |V172a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000774] 4775.#2381 V172 Use * Keep x14 |V36 a| | | |V16 a| | | |V144a|V20 a| | | | |V172i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004347] 4777.#0 V16 Move STK |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004348] 4777.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4777.#2382 BB199 PredBB112 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000778] 4785.#2383 V16 Use * ReLod x4 |V36 a| | |V14 a|V16 a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x4 |V36 a| | |V14 a|V16 i| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4786.#2384 I521 Def Alloc x4 |V36 a| | |V14 a|I521a| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000780] 4787.#2385 I521 Use * Keep x4 |V36 a| | |V14 a|I521i| | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4788.#2386 V16 Def Alloc x4 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x4 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4789.#2387 BB258 PredBB138 |V36 a| | | | | | | |V144a|V20 a| | |V185a|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004259] 4793.#2388 V185 Use * Keep x12 |V36 a| | | | | | | |V144a|V20 a| | |V185i|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4794.#2389 I522 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I522a| |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004260] 4796.#2390 I523 Def Alloc x14 |V36 a| | | | | | | |V144a|V20 a| |I522a| |V18 a|I523a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004261] 4797.#2391 I524 Def Alloc x12 |V36 a| | | | | | | |V144a|V20 a| |I522a|I524a|V18 a|I523a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4797.#2392 I522 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I522i|I524a|V18 a|I523a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4797.#2393 I523 Use * Keep x14 |V36 a| | | | | | | |V144a|V20 a| | |I524a|V18 a|I523i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4799.#2394 V18 ExpU |V36 a| | | | | | | |V144a|V20 a| | |I524a|V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4799.#2395 BB171 PredBB258 |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000607] 4807.#2396 V8 Use ReLod x2 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x2 |V36 a| |V8 i| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x2 |V36 a| |V8 i| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4808.#2397 I525 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a| |I525a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000609] 4811.#2398 I525 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a| |I525i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4811.#2399 V21 Use ReLod x10 |V36 a| | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x10 |V36 a| | | | | | | |V144a|V20 a|V21 a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4812.#2400 I526 Def Alloc x11 |V36 a| | | | | | | |V144a|V20 a|V21 a|I526a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000611] 4815.#2401 I526 Use * Keep x11 |V36 a| | | | | | | |V144a|V20 a|V21 a|I526i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004340] 4817.#0 V21 Move STK |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004341] 4817.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4817.#2402 BB172 PredBB112 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000615] 4825.#2403 V7 Use ReLod x1 |V36 a|V7 a| |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Keep x1 |V36 a|V7 i| |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x1 |V36 a|V7 i| |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4829.#2404 BB173 PredBB172 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000630] 4841.#2405 V36 Use Keep x0 |V36 i| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Spill x0 |V36 i| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4842.#2406 I527 Def Alloc x11 | | | |V14 a| | | | |V144a|V20 a| |I527a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000628] 4849.#2407 V5 Use Keep x28 | | | |V14 a| | | | |V144a|V20 a| |I527a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4849.#2408 V4 Use Keep x27 | | | |V14 a| | | | |V144a|V20 a| |I527a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4849.#2409 I527 Use * Keep x11 | | | |V14 a| | | | |V144a|V20 a| |I527i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4851.#2410 V21 ExpU | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004342] 4851.#0 V36 Move x0 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4851.#2411 BB174 PredBB172 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002006] 4861.#2412 V3 Use Keep x20 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4862.#2413 I528 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I528a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002059] 4863.#2414 I528 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I528i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4864.#2415 V106 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002010] 4871.#2416 V106 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4873.#2417 BB176 PredBB174 |V36 a| | |V14 a| | | | |V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002012] 4881.#2418 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4882.#2419 I529 Def Alloc x10 |V36 a| | |V14 a| | | | |V144a|V20 a|I529a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002014] 4883.#2420 I529 Use * Keep x10 |V36 a| | |V14 a| | | | |V144a|V20 a|I529i|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4884.#2421 V107 Def Alloc x10 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002016] 4891.#2422 V106 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4892.#2423 I530 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I530a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002062] 4903.#2424 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I530a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4904.#2425 I531 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I530a|I531a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002019] 4909.#2426 I530 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I530i|I531a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4909.#2427 V107 Use Keep x10 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| | |I531a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4909.#2428 I531 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| | |I531i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4911.#2429 BB177 PredBB176 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002919] 4921.#2430 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4922.#2431 I532 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I532a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002035] 4923.#2432 I532 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I532i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4924.#2433 V108 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |V108a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002038] 4933.#2434 V108 Use Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |V108a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4934.#2435 I533 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |V108a|I533a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002039] 4935.#2436 V107 Use Keep x10 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |V108a|I533a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4935.#2437 I533 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |V108a|I533i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002043] 4939.#2438 V108 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |V108i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4940.#2439 I534 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I534a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002042] 4947.#2440 V107 Use Keep x10 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I534a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4948.#2441 I535 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I534a|I535a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002044] 4949.#2442 I534 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I534i|I535a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4949.#2443 I535 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| | |I535i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4950.#2444 I536 Def Alloc x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002926] 4957.#2445 V106 Use Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4958.#2446 I537 Def Alloc x14 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I536a|I537a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002927] 4959.#2447 I537 Use * Keep x14 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106a| |I536a|I537i| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002936] 4965.#2448 V106 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|V106i| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4966.#2449 I538 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|I538a| |I536a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004034] 4967.#2450 I536 Use * Keep x13 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|I538a| |I536i| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4967.#2451 I538 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a|V107a|I538i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002055] 4975.#2452 V107 Use * Keep x10 |V36 a| | |V14 a| | | | |V144a|V20 a|V107i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4976.#2453 I539 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I539a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004036] 4981.#2454 V0 Use Keep x19 |V36 a| | |V14 a| | | | |V144a|V20 a| |I539a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4981.#2455 I539 Use * Keep x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |I539i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 4983.#2456 BB179 PredBB176 |V36 a| | |V14 a| | | | |V144a|V20 a| |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004437] 4983.#0 V20 Move STK |V36 a| | |V14 a| | | | |V144a| | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004438] 4983.#0 V14 Move STK |V36 a| | | | | | | |V144a| | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004439] 4983.#0 V36 Move STK | | | | | | | | |V144a| | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004440] 4983.#0 V144 Move STK | | | | | | | | | | | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004268] 4989.#2457 x0 Fixd Keep x0 | | | | | | | | | | | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4989.#2458 V0 Use Copy x0 |V0 a| | | | | | | | | | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4990.#2459 x0 Fixd Keep x0 | | | | | | | | | | | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4990.#2460 I540 Def Alloc x0 |I540a| | | | | | | | | | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004269] 4993.#2461 x1 Fixd Keep x1 |I540a| | | | | | | | | | |V106a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4993.#2462 V106 Use * Copy x1 |I540a|V106i| | | | | | | | | |V106i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4994.#2463 x1 Fixd Keep x1 |I540a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4994.#2464 I541 Def Alloc x1 |I540a|I541a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002939] 4996.#2465 C542 Def Alloc x11 |I540a|I541a| | | | | | | | | |C542a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004270] 4997.#2466 x11 Fixd Keep x11 |I540a|I541a| | | | | | | | | |C542a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4997.#2467 C542 Use * Keep x11 |I540a|I541a| | | | | | | | | |C542i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4998.#2468 x11 Fixd Keep x11 |I540a|I541a| | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4998.#2469 I543 Def Alloc x11 |I540a|I541a| | | | | | | | | |I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002022] 4999.#2470 I544 Def Alloc x10 |I540a|I541a| | | | | | | | |I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2471 x0 Fixd Keep x0 |I540a|I541a| | | | | | | | |I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2472 I540 Use * Keep x0 |I540i|I541a| | | | | | | | |I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2473 x1 Fixd Keep x1 | |I541a| | | | | | | | |I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2474 I541 Use * Keep x1 | |I541i| | | | | | | | |I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2475 x11 Fixd Keep x11 | | | | | | | | | | |I544a|I543a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2476 I543 Use * Keep x11 | | | | | | | | | | |I544a|I543i| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 4999.#2477 I544 Use * Keep x10 | | | | | | | | | | |I544i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2478 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2479 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2480 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2481 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2482 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2483 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2484 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2485 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2486 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2487 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2488 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2489 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2490 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2491 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2492 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2493 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2494 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2495 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5000.#2496 lr Kill Keep lr | | | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004441] 5001.#0 V36 Move x0 |V36 a| | | | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004442] 5001.#0 V14 Move x3 |V36 a| | |V14 a| | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004443] 5001.#0 V144 Move x8 |V36 a| | |V14 a| | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004444] 5001.#0 V20 Move x9 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 5001.#2497 BB180 PredBB174 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [002940] 5006.#2498 C545 Def Alloc x10 |V36 a| | |V14 a| | | | |V144a|V20 a|C545a| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [000624] 5007.#2499 C545 Use * Keep x10 |V36 a| | |V14 a| | | | |V144a|V20 a|C545i| | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5008.#2500 V21 Def Alloc x11 |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2501 V16 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2502 V0 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2503 V179 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2504 V4 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2505 V20 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2506 V34 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2507 V5 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2508 V8 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2509 V14 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2510 V36 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2511 V6 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2512 V12 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2513 V144 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2514 V9 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2515 V3 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2516 V1 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2517 V7 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2518 V143 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2519 V15 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2520 V17 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| 5009.#2521 V21 ExpU |V36 a| | |V14 a| | | | |V144a|V20 a| |V21 a| | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004445] 5009.#0 V21 Move STK |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 5009.#2522 BB110 PredBB91 | | | | | | | | | | | | | | | | | | | | | | | | | | | | [002701] 5014.#2523 C546 Def Alloc x11 | | | | | | | | | | | |C546a| | | | | | | | | | | | | | | | [004302] 5015.#2524 x11 Fixd Keep x11 | | | | | | | | | | | |C546a| | | | | | | | | | | | | | | | 5015.#2525 C546 Use * Keep x11 | | | | | | | | | | | |C546i| | | | | | | | | | | | | | | | 5016.#2526 x11 Fixd Keep x11 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5016.#2527 I547 Def Alloc x11 | | | | | | | | | | | |I547a| | | | | | | | | | | | | | | | [001630] 5017.#2528 I548 Def Alloc x0 |I548a| | | | | | | | | | |I547a| | | | | | | | | | | | | | | | 5017.#2529 x11 Fixd Keep x11 |I548a| | | | | | | | | | |I547a| | | | | | | | | | | | | | | | 5017.#2530 I547 Use * Keep x11 |I548a| | | | | | | | | | |I547i| | | | | | | | | | | | | | | | 5017.#2531 I548 Use * Keep x0 |I548i| | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2532 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2533 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2534 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2535 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2536 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2537 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2538 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2539 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2540 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2541 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2542 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2543 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2544 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2545 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2546 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2547 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2548 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2549 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5018.#2550 lr Kill Keep lr | | | | | | | | | | | | | | | | | | | | | | | | | | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 5019.#2551 BB254 PredBB0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | [004303] 5022.#2552 C549 Def Alloc x0 |C549a| | | | | | | | | | | | | | | | | | | | | | | | | | | [004304] 5023.#2553 C549 Use * Keep x0 |C549i| | | | | | | | | | | | | | | | | | | | | | | | | | | 5024.#2554 I550 Def Alloc x0 |I550a| | | | | | | | | | | | | | | | | | | | | | | | | | | [004154] 5025.#2555 I550 Use * Keep x0 |I550i| | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2556 x0 Kill Keep x0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2557 x1 Kill Keep x1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2558 x2 Kill Keep x2 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2559 x3 Kill Keep x3 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2560 x4 Kill Keep x4 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2561 x5 Kill Keep x5 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2562 x6 Kill Keep x6 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2563 x7 Kill Keep x7 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2564 x8 Kill Keep x8 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2565 x9 Kill Keep x9 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2566 x10 Kill Keep x10 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2567 x11 Kill Keep x11 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2568 x12 Kill Keep x12 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2569 x13 Kill Keep x13 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2570 x14 Kill Keep x14 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2571 x15 Kill Keep x15 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2572 xip0 Kill Keep xip0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2573 xip1 Kill Keep xip1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5026.#2574 lr Kill Keep lr | | | | | | | | | | | | | | | | | | | | | | | | | | | | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB259 PredBB255 | | | | | | | | | | | | | | | | | | | | | | | | | | | | [004306] 5026.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB260 PredBB256 | |V16 i| | | |V9 i|V10 i|V12 i|V13 i|V22 i| | | | | | | |V0 i|V3 i|V1 i|V11 i|V17 i|V180i|V179i|V15 i|V4 i|V5 i| [004308] 5026.#0 V16 Move x1 | |V16 a| | | |V9 a|V10 a|V12 a|V13 a|V22 a| | | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB261 PredBB43 | |V16 i| | | |V9 i|V10 i|V12 i|V13 i|V22 i| | | | | | | |V0 i|V3 i|V1 i|V11 i|V17 i|V180i|V179i|V15 i|V4 i|V5 i| [004323] 5026.#0 V16 Move x10 | | | | | | |V10 a|V12 a|V13 a|V22 a|V16 a| | | | | | |V0 a|V3 a|V1 a|V11 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB262 PredBB78 | | | | | | |V10 i|V12 i|V13 i|V22 i|V16 i| | | | | | |V0 i|V3 i|V1 i|V11 i|V17 i|V180i|V179i|V15 i|V4 i|V5 i| [004324] 5026.#0 V8 Move STK | | | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V180a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB264 PredBB115 | | | |V14 i| | | | |V144i|V20 i| | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V180i|V179i|V15 i|V4 i|V5 i| [004332] 5026.#0 V18 Move x13 |V36 a| | |V14 a| | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB263 PredBB113 |V36 i| | |V14 i| | | | |V144i|V20 i| | | |V18 i| | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004331] 5026.#0 V14 Move STK |V36 a| | | | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB265 PredBB125 |V36 i| | | | | | | |V144i|V20 i| | | |V18 i| | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004333] 5026.#0 V8 Move x2 |V36 a| |V8 a| | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004334] 5026.#0 V144 Move x8 |V36 a| |V8 a| | | | | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004335] 5026.#0 V20 Move x9 |V36 a| |V8 a| | | | | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB266 PredBB258 |V36 i| |V8 i| | | | | |V144i|V20 i| | | |V18 i| | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004336] 5026.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB267 PredBB161 |V36 i| | |V14 i| | | | |V144i|V20 i| | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004337] 5026.#0 V8 Move x2 |V36 a| |V8 a| | | | | | | | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004338] 5026.#0 V144 Move x8 |V36 a| |V8 a| | | | | |V144a| | | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004339] 5026.#0 V20 Move x9 |V36 a| |V8 a| | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB268 PredBB197 |V36 i| |V8 i| | | | | |V144i|V20 i| | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004345] 5026.#0 V16 Move STK |V36 a| | | | | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004346] 5026.#0 V14 Move x3 |V36 a| | |V14 a| | | | |V144a|V20 a| | | | | | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB269 PredBB215 |V36 i| | |V14 i| | | | |V144i|V20 i| | | | | | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004351] 5026.#0 V16 Move STK |V36 a| | | | |V9 a| | |V144a|V20 a| | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004352] 5026.#0 V20 Move STK |V36 a| | | | |V9 a| | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004353] 5026.#0 V36 Move STK | | | | | |V9 a| | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004354] 5026.#0 V144 Move STK | | | | | |V9 a| | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004355] 5026.#0 V9 Move STK | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB270 PredBB220 | | | | | | | | | | | | | |V18 i| | | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004356] 5026.#0 V16 Move x12 |V36 a| | | | | | | |V144a|V20 a| |V37 a|V16 a|V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB271 PredBB220 |V36 i| | | | | | | |V144i|V20 i| |V37 i|V16 i|V18 i|V38 i| | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004357] 5026.#0 V16 Move x4 |V36 a| | | |V16 a| | | |V144a|V20 a| |V37 a| |V18 a|V38 a| | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ TreeID Loc RP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x8 |x9 |x10 |x11 |x12 |x13 |x14 |x15 |xip0 |x19 |x20 |x21 |x22 |x23 |x24 |x25 |x26 |x27 |x28 | -----------------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 BB272 PredBB242 |V36 i| | | |V16 i| | | |V144i|V20 i| |V37 i| |V18 i|V38 i| | |V0 i|V3 i|V1 i|V6 i|V17 i|V34 i|V179i|V15 i|V4 i|V5 i| [004362] 5026.#0 V20 Move STK |V36 a| | | | | | | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004363] 5026.#0 V36 Move STK | | | | | | | | |V144a| | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| [004364] 5026.#0 V144 Move STK | | | | | | | | | | | | | |V18 a| | | |V0 a|V3 a|V1 a|V6 a|V17 a|V34 a|V179a|V15 a|V4 a|V5 a| Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Register selection order: ABCDEFGHIJKLMNOPQ Total Tracked Vars: 141 Total Reg Cand Vars: 137 Total number of Intervals: 550 Total number of RefPositions: 2574 Total Number of spill temps created: 0 .......... BB00 [ 100.00]: REG_ORDER = 3 BB01 [ 100.00]: COVERS = 5, COVERS_RELATED = 2, BEST_FIT = 3, REG_ORDER = 5 BB02 [ 50.00]: COVERS = 2, BEST_FIT = 1 BB03 [ 50.00]: COVERS = 1, OWN_PREFERENCE = 2 BB04 [ 50.00]: THIS_ASSIGNED = 3, RELATED_PREFERENCE = 1 BB05 [ 50.00]: THIS_ASSIGNED = 3, RELATED_PREFERENCE = 1 BB06 [ 100.00]: REG_ORDER = 2 BB07 [ 800.00]: SpillCount = 2, COVERS = 4, COVERS_RELATED = 1, BEST_FIT = 1, REG_ORDER = 9 BB09 [ 800.00]: COVERS = 1, REG_ORDER = 1 BB255 [ 800.00]: SplitEdges = 1, BEST_FIT = 3 BB10 [ 800.00]: COVERS = 1, REG_ORDER = 1 BB256 [ 800.00]: SplitEdges = 1, BEST_FIT = 3 BB12 [ 800.00]: ResolutionMovs = 1 BB15 [ 800.00]: ResolutionMovs = 1, BEST_FIT = 1 BB16 [ 800.00]: RELATED_PREFERENCE = 1 BB17 [ 800.00]: ResolutionMovs = 1, RELATED_PREFERENCE = 1 BB18 [ 800.00]: BEST_FIT = 1 BB20 [ 800.00]: ResolutionMovs = 3, RELATED_PREFERENCE = 1, REG_ORDER = 1 BB21 [ 800.00]: ResolutionMovs = 1 BB23 [ 800.00]: ResolutionMovs = 1 BB27 [ 800.00]: RELATED_PREFERENCE = 1 BB28 [ 800.00]: SpillCount = 1, ResolutionMovs = 1, OWN_PREFERENCE = 1, RELATED_PREFERENCE = 1 BB29 [ 800.00]: THIS_ASSIGNED = 1, COVERS_RELATED = 1 BB30 [ 800.00]: ResolutionMovs = 1, RELATED_PREFERENCE = 1 BB31 [ 6400.00]: ResolutionMovs = 1, COVERS = 1, BEST_FIT = 1 BB32 [ 6400.00]: SpillCount = 3, ResolutionMovs = 1, RELATED_PREFERENCE = 1, BEST_FIT = 1, REG_ORDER = 1 BB34 [ 800.00]: ResolutionMovs = 1 BB35 [ 800.00]: ResolutionMovs = 1, COVERS = 1, BEST_FIT = 1 BB36 [ 800.00]: RELATED_PREFERENCE = 1 BB39 [ 800.00]: THIS_ASSIGNED = 1, COVERS_RELATED = 1 BB40 [ 800.00]: ResolutionMovs = 1, BEST_FIT = 1 BB41 [ 800.00]: COVERS = 1, BEST_FIT = 1 BB43 [ 800.00]: SplitEdges = 1, BEST_FIT = 2 BB44 [ 6400.00]: COVERS = 1, COVERS_RELATED = 1, REG_ORDER = 1 BB45 [ 6400.00]: BEST_FIT = 1 BB46 [ 800.00]: ResolutionMovs = 1, RELATED_PREFERENCE = 1, REG_ORDER = 1 BB48 [ 1600.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 4 BB54 [ 200.00]: RELATED_PREFERENCE = 1, BEST_FIT = 1 BB55 [ 200.00]: SpillCount = 1, ResolutionMovs = 1, RELATED_PREFERENCE = 1, REG_ORDER = 1 BB56 [ 800.00]: BEST_FIT = 1 BB57 [ 400.00]: SpillCount = 1, COVERS = 1, BEST_FIT = 3 BB58 [ 200.00]: ResolutionMovs = 1, COVERS = 1, RELATED_PREFERENCE = 1, BEST_FIT = 2 BB59 [ 200.00]: ResolutionMovs = 1 BB60 [ 400.00]: BEST_FIT = 1, REG_ORDER = 1 BB61 [ 400.00]: REG_ORDER = 2 BB63 [ 50.00]: BEST_FIT = 1 BB65 [ 50.00]: ResolutionMovs = 2 BB66 [ 100.00]: SpillCount = 17, COVERS = 3, COVERS_RELATED = 2, BEST_FIT = 2, REG_ORDER = 1 BB73 [ 50.00]: REG_ORDER = 2 BB74 [ 50.00]: COVERS = 2, COVERS_RELATED = 1, RELATED_PREFERENCE = 1, BEST_FIT = 1, REG_ORDER = 2 BB78 [ 100.00]: SpillCount = 5, SplitEdges = 1, BEST_FIT = 2, REG_ORDER = 8 BB79 [ 50.00]: SpillCount = 2, REG_ORDER = 6 BB81 [ 50.00]: SpillCount = 1, ResolutionMovs = 1, RELATED_PREFERENCE = 1 BB82 [ 50.00]: SpillCount = 4, BEST_FIT = 1, REG_ORDER = 1 BB83 [ 50.00]: OWN_PREFERENCE = 1, BEST_FIT = 1 BB84 [ 50.00]: SpillCount = 2, ResolutionMovs = 1, THIS_ASSIGNED = 1 BB85 [ 50.00]: SpillCount = 1, COVERS = 1, BEST_FIT = 4 BB89 [ 400.00]: SpillCount = 1 BB90 [ 400.00]: SpillCount = 1, RELATED_PREFERENCE = 1 BB91 [ 200.00]: SpillCount = 2, ResolutionMovs = 2, COVERS = 3, COVERS_RELATED = 1, BEST_FIT = 2, REG_ORDER = 2, REG_NUM = 1 BB95 [ 200.00]: ResolutionMovs = 4, COVERS = 3, COVERS_RELATED = 2, BEST_FIT = 2, REG_ORDER = 3 BB100 [ 400.00]: SpillCount = 6, BEST_FIT = 1 BB101 [ 200.00]: ResolutionMovs = 1, COVERS_RELATED = 1, RELATED_PREFERENCE = 1, BEST_FIT = 3 BB102 [ 400.00]: ResolutionMovs = 6, RELATED_PREFERENCE = 1 BB103 [ 100.00]: SpillCount = 1, BEST_FIT = 1 BB104 [ 50.00]: BEST_FIT = 1 BB106 [ 50.00]: COVERS = 1, BEST_FIT = 1 BB107 [ 50.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 2 BB108 [ 50.00]: COVERS = 1, BEST_FIT = 2, REG_ORDER = 5 BB112 [ 100.00]: SpillCount = 9, COVERS = 3, BEST_FIT = 1, REG_ORDER = 1 BB246 [ 400.00]: SpillCount = 3, COVERS = 1, COVERS_RELATED = 1, RELATED_PREFERENCE = 1, BEST_FIT = 1, REG_ORDER = 1 BB248 [ 100.00]: BEST_FIT = 1 BB249 [ 50.00]: BEST_FIT = 5 BB251 [ 50.00]: REG_ORDER = 1 BB111 [ 50.00]: ResolutionMovs = 6, REG_ORDER = 1 BB113 [ 200.00]: SplitEdges = 1 BB114 [ 200.00]: BEST_FIT = 1 BB115 [ 200.00]: SpillCount = 2, SplitEdges = 1 BB117 [ 200.00]: ResolutionMovs = 2 BB118 [ 800.00]: COVERS = 1, BEST_FIT = 1 BB119 [ 800.00]: COVERS = 1, REG_ORDER = 1 BB120 [ 800.00]: SpillCount = 9, ResolutionMovs = 1, COVERS = 1, RELATED_PREFERENCE = 1, REG_ORDER = 1 BB121 [ 800.00]: COVERS = 2, BEST_FIT = 1, REG_ORDER = 2 BB122 [ 800.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 3 BB123 [ 800.00]: ResolutionMovs = 8, REG_ORDER = 1 BB124 [ 800.00]: SpillCount = 8 BB125 [ 800.00]: SpillCount = 18, SplitEdges = 1, BEST_FIT = 2 BB127 [ 800.00]: COVERS = 1, BEST_FIT = 1 BB129 [ 800.00]: COVERS = 2, REG_ORDER = 3 BB130 [ 800.00]: FREE = 2, COVERS = 1, BEST_FIT = 2, REG_ORDER = 3 BB132 [ 800.00]: ResolutionMovs = 4, REG_ORDER = 1 BB133 [ 800.00]: SpillCount = 7, ResolutionMovs = 3, RELATED_PREFERENCE = 1 BB134 [ 800.00]: SpillCount = 14, ResolutionMovs = 1, RELATED_PREFERENCE = 2 BB135 [ 1600.00]: SpillCount = 2 BB137 [ 200.00]: COVERS = 1, REG_ORDER = 1 BB257 [ 200.00]: BEST_FIT = 1, REG_ORDER = 2 BB138 [ 200.00]: COVERS = 1, REG_ORDER = 1 BB258 [ 200.00]: SplitEdges = 1, BEST_FIT = 1, REG_ORDER = 2 BB143 [ 200.00]: BEST_FIT = 1 BB144 [ 200.00]: COVERS = 1, BEST_FIT = 1 BB146 [ 200.00]: SpillCount = 5, RELATED_PREFERENCE = 1 BB147 [ 200.00]: BEST_FIT = 1 BB148 [ 200.00]: THIS_ASSIGNED = 1, RELATED_PREFERENCE = 1 BB149 [ 200.00]: RELATED_PREFERENCE = 1, REG_ORDER = 1 BB150 [ 200.00]: BEST_FIT = 1 BB151 [ 200.00]: SpillCount = 5 BB152 [ 200.00]: BEST_FIT = 1 BB153 [ 200.00]: THIS_ASSIGNED = 1, RELATED_PREFERENCE = 1 BB154 [ 200.00]: SpillCount = 4, ResolutionMovs = 1, THIS_ASSIGNED = 1, COVERS_RELATED = 1, RELATED_PREFERENCE = 1, BEST_FIT = 1 BB155 [ 200.00]: ResolutionMovs = 2, RELATED_PREFERENCE = 1, REG_ORDER = 1 BB157 [ 200.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 1 BB158 [ 200.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 3 BB159 [ 200.00]: ResolutionMovs = 8, REG_ORDER = 1 BB160 [ 200.00]: SpillCount = 4 BB161 [ 200.00]: SpillCount = 10, SplitEdges = 1, BEST_FIT = 2 BB163 [ 200.00]: COVERS = 1, BEST_FIT = 1 BB165 [ 200.00]: COVERS = 1, REG_ORDER = 3 BB166 [ 200.00]: COVERS = 1, BEST_FIT = 2, REG_ORDER = 6 BB168 [ 200.00]: ResolutionMovs = 2, REG_ORDER = 1 BB169 [ 200.00]: SpillCount = 3, ResolutionMovs = 3, RELATED_PREFERENCE = 1 BB170 [ 200.00]: SpillCount = 2, ResolutionMovs = 1, RELATED_PREFERENCE = 1 BB171 [ 200.00]: SpillCount = 1, ResolutionMovs = 2, BEST_FIT = 2 BB172 [ 200.00]: SpillCount = 1 BB173 [ 200.00]: SpillCount = 1, ResolutionMovs = 1, BEST_FIT = 1 BB174 [ 200.00]: COVERS = 1, BEST_FIT = 1 BB176 [ 200.00]: COVERS = 1, REG_ORDER = 3 BB177 [ 200.00]: COVERS = 1, BEST_FIT = 2, REG_ORDER = 6 BB179 [ 200.00]: ResolutionMovs = 8, REG_ORDER = 1 BB180 [ 200.00]: ResolutionMovs = 1, COVERS_RELATED = 1, BEST_FIT = 1 BB181 [ 200.00]: ResolutionMovs = 1 BB182 [ 200.00]: COVERS = 1, REG_ORDER = 3 BB183 [ 200.00]: COVERS = 1, BEST_FIT = 2, REG_ORDER = 6 BB185 [ 200.00]: ResolutionMovs = 8, REG_ORDER = 1 BB186 [ 200.00]: ResolutionMovs = 1, COVERS = 1, BEST_FIT = 1 BB187 [ 200.00]: COVERS = 1, REG_ORDER = 3 BB188 [ 200.00]: COVERS = 1, BEST_FIT = 2, REG_ORDER = 6 BB190 [ 200.00]: ResolutionMovs = 8, REG_ORDER = 1 BB191 [ 800.00]: SpillCount = 1, COVERS = 2, RELATED_PREFERENCE = 1, BEST_FIT = 2, REG_ORDER = 2 BB192 [ 800.00]: ResolutionMovs = 1, COVERS = 1, BEST_FIT = 1, REG_ORDER = 3 BB193 [ 800.00]: ResolutionMovs = 7, REG_ORDER = 1 BB195 [ 1600.00]: COVERS = 1, REG_ORDER = 1 BB196 [ 1600.00]: SpillCount = 1 BB197 [ 200.00]: SplitEdges = 1 BB198 [ 200.00]: ResolutionMovs = 2, THIS_ASSIGNED = 1, COVERS_RELATED = 1 BB199 [ 200.00]: SpillCount = 1, RELATED_PREFERENCE = 1 BB200 [ 200.00]: ResolutionMovs = 2, COVERS = 1, REG_ORDER = 1 BB201 [ 200.00]: SpillCount = 1, COVERS = 2, RELATED_PREFERENCE = 1, BEST_FIT = 2, REG_ORDER = 2 BB203 [ 200.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 3 BB204 [ 200.00]: ResolutionMovs = 8, REG_ORDER = 1 BB205 [ 200.00]: BEST_FIT = 1, REG_ORDER = 1 BB207 [ 200.00]: COVERS = 1, REG_ORDER = 1 BB208 [ 200.00]: BEST_FIT = 1 BB209 [ 200.00]: FREE = 3, THIS_ASSIGNED = 1, COVERS_RELATED = 1, REG_ORDER = 2 BB210 [ 200.00]: THIS_ASSIGNED = 1, RELATED_PREFERENCE = 1 BB214 [ 200.00]: REG_ORDER = 2 BB215 [ 200.00]: SplitEdges = 1, COVERS = 1, BEST_FIT = 2 BB216 [ 200.00]: ResolutionMovs = 3, COVERS = 1, BEST_FIT = 3, REG_ORDER = 1 BB218 [ 800.00]: RELATED_PREFERENCE = 1 BB219 [ 1600.00]: COVERS = 1, COVERS_RELATED = 1, REG_ORDER = 1 BB220 [ 1600.00]: SpillCount = 2, SplitEdges = 2, BEST_FIT = 1 BB222 [ 200.00]: THIS_ASSIGNED = 1, RELATED_PREFERENCE = 1 BB223 [ 200.00]: BEST_FIT = 1 BB224 [ 200.00]: ResolutionMovs = 4, COVERS = 1, BEST_FIT = 2 BB225 [ 200.00]: ResolutionMovs = 4 BB226 [ 200.00]: SpillCount = 4, ResolutionMovs = 4, REG_ORDER = 2 BB227 [ 200.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 1 BB228 [ 200.00]: COVERS = 1, BEST_FIT = 1, REG_ORDER = 3 BB229 [ 200.00]: ResolutionMovs = 8, REG_ORDER = 1 BB230 [ 200.00]: ResolutionMovs = 3 BB231 [ 200.00]: COVERS = 1, BEST_FIT = 1 BB233 [ 200.00]: SpillCount = 1, COVERS = 2, RELATED_PREFERENCE = 1, BEST_FIT = 1, REG_ORDER = 3 BB234 [ 200.00]: ResolutionMovs = 1, COVERS = 1, BEST_FIT = 1, REG_ORDER = 3 BB235 [ 200.00]: ResolutionMovs = 9, REG_ORDER = 1 BB236 [ 800.00]: SpillCount = 2, COVERS = 2, RELATED_PREFERENCE = 1, BEST_FIT = 1, REG_ORDER = 3 BB237 [ 800.00]: ResolutionMovs = 1, COVERS = 1, BEST_FIT = 1, REG_ORDER = 3 BB238 [ 800.00]: ResolutionMovs = 9, REG_ORDER = 1 BB239 [ 1600.00]: ResolutionMovs = 1 BB240 [ 1600.00]: COVERS = 1, BEST_FIT = 1 BB241 [ 200.00]: ResolutionMovs = 1 BB242 [ 200.00]: SplitEdges = 1, COVERS = 1, BEST_FIT = 1, REG_ORDER = 1 BB243 [ 200.00]: ResolutionMovs = 1, COVERS = 1, BEST_FIT = 1, REG_ORDER = 3 BB244 [ 200.00]: SpillCount = 12, ResolutionMovs = 4, REG_ORDER = 1 BB110 [ 0.00]: REG_ORDER = 1 BB254 [ 0.00]: REG_ORDER = 2 .......... Total SpillCount : 184 Weighted: 97300.000000 Total CopyReg : 0 Weighted: 0.000000 Total ResolutionMovs : 181 Weighted: 79100.000000 Total SplitEdges : 14 Weighted: 7900.000000 .......... Total FREE [# 1] : 5 Weighted: 2200.000000 Total THIS_ASSIGNED [# 3] : 16 Weighted: 3350.000000 Total COVERS [# 4] : 91 Weighted: 48550.000000 Total OWN_PREFERENCE [# 5] : 4 Weighted: 950.000000 Total COVERS_RELATED [# 6] : 19 Weighted: 12850.000000 Total RELATED_PREFERENCE [# 7] : 40 Weighted: 23200.000000 Total BEST_FIT [#11] : 127 Weighted: 62350.000000 Total REG_ORDER [#13] : 188 Weighted: 78200.000000 Total REG_NUM [#17] : 1 Weighted: 200.000000 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(x0=>x19) V03(x4=>x20) V01(x1=>x21) BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} ===== N003. IL_OFFSET INLRT @ 0x000[E-] N005. V01(x21) N007. x0 = PUTARG_REG; x21 N009. x11 = CNS_INT(h) 0x400000000046ac80 ftn N011. x11 = PUTARG_REG; x11 N013. CALL r2r_ind; x0,x11 N015. IL_OFFSET INLRT @ 0x006[E-] N017. CNS_INT 0 * N019. V11(x22) N021. IL_OFFSET INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] N023. V01(x21) N025. CNS_INT 16 N027. x0 = ADD ; x21 * N029. V76(x0); x0 N031. IL_OFFSET INLRT @ 0x009[E-] N033. CNS_INT 0 N035. V76(x0) N037. STK = LEA(b+8) ; x0 N039. x1 = IND ; STK N041. BOUNDS_CHECK_Rng -> BB254; x1 N043. V76(x0*) N045. x23 = IND ; x0* * N047. V167(x23); x23 N049. V167(x23*) * N051. V17(x23); x23* N053. x24 = V02 MEM * N055. V180(x24); x24 N057. V180(x24) * N059. V147(x0); x24 N061. x25 = V02 MEM * N063. V179(x25); x25 N065. V179(x25) * N067. V148(x1); x25 N069. IL_OFFSET INLRT @ 0x011[E-] N071. V17(x23) N073. x2 = IND ; x23 N075. CNS_INT 0 N077. JCMP ; x2 Var=Reg end of BB01: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V147=x0 V148=x1 BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V147=x0 V148=x1 N081. V147(x0*) * N083. V155(x0); x0* N085. V148(x1*) * N087. V156(x1); x1* N089. V01(x21) N091. STK = LEA(b+8) ; x21 N093. x2 = IND ; STK N095. CNS_INT 0 N097. JCMP ; x2 Var=Reg end of BB02: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V155=x0 V156=x1 BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB03: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V155=x0 V156=x1 N101. V155(x0*) * N103. V149(x0); x0* N105. V156(x1*) * N107. V150(x1); x1* N109. CNS_INT 0 * N111. V43(x2) Var=Reg end of BB03: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V149=x0 V43=x2 V150=x1 BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB04: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V155=x0 V156=x1 N115. V155(x0*) * N117. V149(x0); x0* N119. V156(x1*) * N121. V150(x1); x1* N123. x2 = CNS_INT 1 * N125. V43(x2); x2 Var=Reg end of BB04: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V149=x0 V43=x2 V150=x1 BB05 [025..026), preds={BB01} succs={BB06} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB05: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V147=x0 V148=x1 N129. V147(x0*) * N131. V149(x0); x0* N133. V148(x1*) * N135. V150(x1); x1* N137. x2 = CNS_INT 2 * N139. V43(x2); x2 Var=Reg end of BB05: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V149=x0 V43=x2 V150=x1 BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB06: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 V149=x0 V43=x2 V150=x1 N143. V149(x0*) N145. x0 = PUTARG_REG; x0* N147. V150(x1*) N149. x1 = PUTARG_REG; x1* N151. STK = FIELD_LIST; x0,x1 N153. V43(x2*) N155. x2 = PUTARG_REG; x2* N157. x11 = CNS_INT(h) 0x40000000005401e8 ftn N159. x11 = PUTARG_REG; x11 N161. x0 = CALL r2r_ind; STK,x2,x11 * N163. V15(x26); x0 Var=Reg end of BB06: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB07: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N167. IL_OFFSET INLRT @ 0x02D[E-] N169. CNS_INT 0 * N171. V04(x27) N173. IL_OFFSET INLRT @ 0x02F[E-] N175. x28 = CNS_INT -1 * N177. V05(x28); x28 N179. IL_OFFSET INLRT @ 0x031[E-] N181. x3 = CNS_INT 0x7FFFFFFF N183. V06(STK); x3 N185. IL_OFFSET INLRT @ 0x037[E-] N187. CNS_INT 0 N189. V07(STK) N191. IL_OFFSET INLRT @ 0x039[E-] N193. CNS_INT 0 * N195. V09(x5) N197. IL_OFFSET INLRT @ 0x03C[E-] N199. x6 = CNS_INT -1 * N201. V10(x6); x6 N203. IL_OFFSET INLRT @ 0x03F[E-] N205. CNS_INT 0 * N207. V12(x7) N209. IL_OFFSET INLRT @ 0x042[E-] N211. CNS_INT 0 * N213. V13(x8) N215. IL_OFFSET INLRT @ 0x045[E-] N217. V15(x26) * N219. V16(x1); x26 N221. IL_OFFSET INLRT @ 0x049[E-] N223. V180(x24) * N225. V157(x9); x24 N227. IL_OFFSET INLRT @ 0x049[E-] N229. V157(x9) N231. V23 MEM; x9 N233. IL_OFFSET INLRT @ 0x051[E-] N235. V157(x9*) * N237. V168(x9); x9* N239. V168(x9*) * N241. V22(x9); x9* Var=Reg end of BB07: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB47 [204..20F) -> BB50 (cond), preds={BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB259,BB260} succs={BB48,BB50} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB47: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N245. IL_OFFSET INLRT @ 0x204[E-] N247. V16(x1) N249. V179(x25) N251. GE ; x1,x25 N253. JTRUE Var=Reg end of BB47: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} ===== Predecessor for variable locations: BB47 Var=Reg beg of BB48: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N257. IL_OFFSET INLRT @ 0x20F[E-] N259. V16(x1*) * N261. V71(x1); x1* N263. IL_OFFSET INLRT @ 0x20F[E-] N265. V71(x1) N267. CNS_INT 1 N269. x0 = ADD ; x1 * N271. V16(x10); x0 N273. V22(x9) N275. V71(x1*) N277. STK = CAST ; x1* N279. CNS_INT 1 N281. STK = BFIZ ; STK N283. STK = LEA(b+(i*1)+0); x9,STK N285. x13 = IND ; STK * N287. V72(x13); x13 N289. V72(x13*) * N291. V18(x13); x13* N293. V18(x13) N295. CNS_INT 0 N297. JCMP ; x13 Var=Reg end of BB48: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} ===== Predecessor for variable locations: BB48 Var=Reg beg of BB49: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N301. IL_OFFSET INLRT @ 0x222[E-] N303. V18(x13) N305. CNS_INT 59 N307. NE ; x13 N309. JTRUE Var=Reg end of BB49: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} ===== Predecessor for variable locations: BB49 Var=Reg beg of BB08: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N313. IL_OFFSET INLRT @ 0x05B[E-] N315. V18(x13) N317. CNS_INT 69 N319. GT ; x13 N321. JTRUE Var=Reg end of BB08: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB09 [061..061) -> BB10 (cond), preds={BB08} succs={BB255,BB10} ===== Predecessor for variable locations: BB08 Var=Reg beg of BB09: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N325. IL_OFFSET INLRT @ 0x061[E-] N327. V18(x13) N329. CNS_INT -34 N331. x14 = ADD ; x13 * N333. V182(x14); x14 N335. V182(x14) N337. CNS_INT 5 N339. GT ; x14 N341. JTRUE Var=Reg end of BB09: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V182=x14 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB10 [083..083) -> BB11 (cond), preds={BB09} succs={BB256,BB11} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB10: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N345. IL_OFFSET INLRT @ 0x083[E-] N347. V18(x13) N349. CNS_INT -44 N351. x12 = ADD ; x13 * N353. V183(x12); x12 N355. V183(x12) N357. CNS_INT 4 N359. GT ; x12 N361. JTRUE Var=Reg end of BB10: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V183=x12 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB11: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N365. IL_OFFSET INLRT @ 0x0A1[E-] N367. V18(x13*) N369. CNS_INT 69 N371. EQ ; x13* N373. JTRUE Var=Reg end of BB11: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} ===== Predecessor for variable locations: BB11 Var=Reg beg of BB12: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N001. V16(x10) * N002. x1 = COPY ; x10 Var=Reg end of BB12: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} ===== Predecessor for variable locations: BB08 Var=Reg beg of BB13: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N379. IL_OFFSET INLRT @ 0x0AF[E-] N381. V18(x13) N383. CNS_INT 92 N385. EQ ; x13 N387. JTRUE Var=Reg end of BB13: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} ===== Predecessor for variable locations: BB13 Var=Reg beg of BB14: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N391. IL_OFFSET INLRT @ 0x0B8[E-] N393. V18(x13) N395. CNS_INT 101 N397. EQ ; x13 N399. JTRUE Var=Reg end of BB14: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB15: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N403. IL_OFFSET INLRT @ 0x0C1[E-] N405. V18(x13*) N407. x1 = CNS_INT 0x2030 N409. NE ; x13*,x1 N001. V16(x10) * N002. x1 = COPY ; x10 N411. JTRUE Var=Reg end of BB15: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB16: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N415. IL_OFFSET INLRT @ 0x137[E-] N417. V13(x8*) N419. CNS_INT 3 N421. x8 = ADD ; x8* * N423. V13(x8); x8 Var=Reg end of BB16: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} ===== Predecessor for variable locations: BB13 Var=Reg beg of BB35: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N427. IL_OFFSET INLRT @ 0x175[E-] N429. V16(x10) N431. V179(x25) N433. STK = GE ; x10,x25 N435. V22(x9) N437. V16(x10) N439. STK = CAST ; x10 N441. CNS_INT 1 N443. STK = BFIZ ; STK N445. STK = LEA(b+(i*1)+0); x9,STK N447. x1 = IND ; STK * N449. V174(x1); x1 N451. V174(x1*) N453. CNS_INT 0 N455. STK = EQ ; x1* N457. AND ; STK,STK N001. V16(x10) * N002. x1 = COPY ; x10 N459. JTRUE ; STK Var=Reg end of BB35: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB36: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N463. IL_OFFSET INLRT @ 0x183[E-] N465. IL_OFFSET INLRT @ 0x18E[E-] N467. V16(x1*) N469. CNS_INT 1 N471. x1 = ADD ; x1* * N473. V16(x1); x1 Var=Reg end of BB36: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} ===== Predecessor for variable locations: BB11 Var=Reg beg of BB38: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N477. IL_OFFSET INLRT @ 0x196[E-] N479. V16(x10) N481. V179(x25) N483. GE ; x10,x25 N485. JTRUE Var=Reg end of BB38: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} ===== Predecessor for variable locations: BB38 Var=Reg beg of BB39: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N489. IL_OFFSET INLRT @ 0x1A1[E-] N491. V22(x9) N493. V16(x10) N495. STK = CAST ; x10 N497. CNS_INT 1 N499. STK = BFIZ ; STK N501. STK = LEA(b+(i*1)+0); x9,STK N503. x1 = IND ; STK * N505. V174(x1); x1 N507. V174(x1*) N509. CNS_INT 48 N511. EQ ; x1* N513. JTRUE Var=Reg end of BB39: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} ===== Predecessor for variable locations: BB38 Var=Reg beg of BB40: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N517. IL_OFFSET INLRT @ 0x1AE[E-] N519. V16(x10) N521. CNS_INT 1 N523. x1 = ADD ; x10 N525. V179(x25) N527. GE ; x1,x25 N001. V16(x10) * N002. x1 = COPY ; x10 N529. JTRUE Var=Reg end of BB40: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB41: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N533. IL_OFFSET INLRT @ 0x1BB[E-] N535. V22(x9) N537. V16(x1) N539. STK = CAST ; x1 N541. CNS_INT 1 N543. STK = BFIZ ; STK N545. STK = LEA(b+(i*1)+0); x9,STK N547. x0 = IND ; STK * N549. V174(x0); x0 N551. V174(x0) N553. CNS_INT 43 N555. EQ ; x0 N557. JTRUE Var=Reg end of BB41: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V174=x0 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} ===== Predecessor for variable locations: BB41 Var=Reg beg of BB42: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V174=x0 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N561. IL_OFFSET INLRT @ 0x1C8[E-] N563. V174(x0*) N565. CNS_INT 45 N567. NE ; x0* N569. JTRUE Var=Reg end of BB42: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB261,BB47} ===== Predecessor for variable locations: BB41 Var=Reg beg of BB43: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N573. IL_OFFSET INLRT @ 0x1D5[E-] N575. V22(x9) N577. V16(x1) N579. CNS_INT 1 N581. x0 = ADD ; x1 N583. STK = CAST ; x0 N585. CNS_INT 1 N587. STK = BFIZ ; STK N589. STK = LEA(b+(i*1)+0); x9,STK N591. x0 = IND ; STK N593. CNS_INT 48 N595. NE ; x0 N597. JTRUE Var=Reg end of BB43: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB45,BB261} succs={BB45,BB46} ===== Predecessor for variable locations: BB39 Var=Reg beg of BB44: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N601. IL_OFFSET INLRT @ 0x1E4[E-] N603. V16(x10*) N605. CNS_INT 1 N607. x10 = ADD ; x10* * N609. V73(x10); x10 N611. V73(x10*) * N613. V16(x10); x10* N615. V16(x10) N617. V179(x25) N619. GE ; x10,x25 N621. JTRUE Var=Reg end of BB44: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} ===== Predecessor for variable locations: BB44 Var=Reg beg of BB45: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N625. IL_OFFSET INLRT @ 0x1F4[E-] N627. V22(x9) N629. V16(x10) N631. STK = CAST ; x10 N633. CNS_INT 1 N635. STK = BFIZ ; STK N637. STK = LEA(b+(i*1)+0); x9,STK N639. x5 = IND ; STK N641. CNS_INT 48 N643. EQ ; x5 N645. JTRUE Var=Reg end of BB45: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB46 [201..204), preds={BB44,BB45} succs={BB47} ===== Predecessor for variable locations: BB44 Var=Reg beg of BB46: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N649. IL_OFFSET INLRT @ 0x201[E-] N651. x5 = CNS_INT 1 * N653. V09(x5); x5 N001. V16(x10) * N002. x1 = COPY ; x10 Var=Reg end of BB46: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} ===== Predecessor for variable locations: BB47 Var=Reg beg of BB50: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N657. IL_OFFSET INLRT @ 0x22B[E-] N659. CNS_INT 0 N661. V23 MEM N663. IL_OFFSET INLRT @ 0x22F[E-] N665. V05(x28) N667. CNS_INT 0 N669. GE ; x28 N671. JTRUE Var=Reg end of BB50: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB51 [233..235), preds={BB50} succs={BB52} ===== Predecessor for variable locations: BB50 Var=Reg beg of BB51: V00=x19 V179=x25 V04=x27 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N675. IL_OFFSET INLRT @ 0x233[E-] N677. V04(x27) * N679. V05(x28); x27 Var=Reg end of BB51: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} ===== Predecessor for variable locations: BB50 Var=Reg beg of BB52: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N683. IL_OFFSET INLRT @ 0x235[E-] N685. V10(x6) N687. CNS_INT 0 N689. LT ; x6 N691. JTRUE Var=Reg end of BB52: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} ===== Predecessor for variable locations: BB52 Var=Reg beg of BB53: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N695. IL_OFFSET INLRT @ 0x23A[E-] N697. V10(x6*) N699. V05(x28) N701. NE ; x6*,x28 N703. JTRUE Var=Reg end of BB53: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} ===== Predecessor for variable locations: BB53 Var=Reg beg of BB54: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N707. IL_OFFSET INLRT @ 0x23F[E-] N709. V13(x8*) N711. V11(x22) N713. x1 = CNS_INT 3 N715. STK = MUL ; x22,x1 N717. x8 = SUB ; x8*,STK * N719. V13(x8); x8 Var=Reg end of BB54: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB55 [24A..24D), preds={BB53} succs={BB56} ===== Predecessor for variable locations: BB53 Var=Reg beg of BB55: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N723. IL_OFFSET INLRT @ 0x24A[E-] N725. x7 = CNS_INT 1 N727. V12(STK); x7 * N001. V12(x7)R Var=Reg end of BB55: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} ===== Predecessor for variable locations: BB52 Var=Reg beg of BB56: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N731. IL_OFFSET INLRT @ 0x24D[E-] N733. V17(x23) N735. x1 = IND ; x23 N737. CNS_INT 0 N739. JCMP ; x1 Var=Reg end of BB56: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} ===== Predecessor for variable locations: BB56 Var=Reg beg of BB57: V00=x19 V179=x25 V04=x27 V05=x28 V13=x8 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N743. IL_OFFSET INLRT @ 0x252[E-] N745. V01(x21) N747. CNS_INT 4 N749. x1 = ADD ; x21 * N751. V69(x1); x1 N753. V69(x1) N755. x0 = IND ; x1 N757. V13(x8*) N759. x0 = ADD ; x0,x8* N761. V69(x1*) N763. STOREIND ; x1*,x0 N765. IL_OFFSET INLRT @ 0x25E[E-] S N767. V09(x5) N769. CNS_INT 0 N771. JCMP ; x5 Var=Reg end of BB57: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} ===== Predecessor for variable locations: BB57 Var=Reg beg of BB58: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N775. IL_OFFSET INLRT @ 0x262[E-] N777. V01(x21) N779. STK = LEA(b+4) ; x21 N781. x1 = IND ; STK N783. V04(x27) N785. x1 = ADD ; x1,x27 N787. V05(x28) N789. x1 = SUB ; x1,x28 * N791. V70(x1); x1 $ N001. V12(x7) Var=Reg end of BB58: V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V70=x1 BB59 [26E..26F), preds={BB57} succs={BB60} ===== Predecessor for variable locations: BB57 Var=Reg beg of BB59: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N795. IL_OFFSET INLRT @ 0x26E[E-] N797. V04(x27) * N799. V70(x1); x27 $ N001. V12(x7) Var=Reg end of BB59: V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V70=x1 BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} ===== Predecessor for variable locations: BB58 Var=Reg beg of BB60: V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V70=x1 N803. IL_OFFSET INLRT @ 0x271[E-] N805. V70(x1*) N807. x1 = PUTARG_REG; x1* N809. V01(x21) N811. x0 = PUTARG_REG; x21 N813. x11 = CNS_INT(h) 0x400000000046acb8 ftn N815. x11 = PUTARG_REG; x11 N817. x2 = CNS_INT 0 N819. x2 = PUTARG_REG; x2 N821. CALL r2r_ind; x1,x0,x11,x2 N823. IL_OFFSET INLRT @ 0x27A[E-] N825. V17(x23) N827. x0 = IND ; x23 N829. CNS_INT 0 N831. JCMP ; x0 Var=Reg end of BB60: V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} ===== Predecessor for variable locations: BB60 Var=Reg beg of BB61: V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N835. IL_OFFSET INLRT @ 0x27F[E-] N837. V180(x24) N839. x0 = PUTARG_REG; x24 N841. x1 = V02 MEM N843. x1 = PUTARG_REG; x1 N845. STK = FIELD_LIST; x0,x1 N847. x11 = CNS_INT(h) 0x40000000005401e8 ftn N849. x11 = PUTARG_REG; x11 N851. x2 = CNS_INT 2 N853. x2 = PUTARG_REG; x2 N855. x0 = CALL r2r_ind; STK,x11,x2 * N857. V16(x1); x0 N859. IL_OFFSET INLRT @ 0x288[E-] N861. V16(x1) N863. V15(x26) N865. EQ ; x1,x26 N867. JTRUE Var=Reg end of BB61: V16=x1 V00=x19 V179=x25 V04=x27 V05=x28 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} ===== Predecessor for variable locations: BB61 Var=Reg beg of BB62: V16=x1 V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V17=x23 V180=x24 N871. IL_OFFSET INLRT @ 0x28E[E-] N873. V16(x1*) * N875. V15(x26); x1* Var=Reg end of BB62: V00=x19 V179=x25 V11=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} ===== Predecessor for variable locations: BB56 Var=Reg beg of BB63: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N879. IL_OFFSET INLRT @ 0x297[E-] N881. V01(x21) N883. STK = LEA(b+10); x21 N885. x1 = IND ; STK N887. CNS_INT 3 N889. EQ ; x1 N891. JTRUE Var=Reg end of BB63: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB64 [2A0..2A7), preds={BB63} succs={BB65} ===== Predecessor for variable locations: BB63 Var=Reg beg of BB64: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N895. IL_OFFSET INLRT @ 0x2A0[E-] N897. V01(x21) N899. STK = LEA(b+8) ; x21 N901. CNS_INT 0 N903. STOREIND ; STK Var=Reg end of BB64: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} ===== Predecessor for variable locations: BB63 Var=Reg beg of BB65: V00=x19 V179=x25 V04=x27 V05=x28 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N907. IL_OFFSET INLRT @ 0x2A7[E-] N909. V01(x21) N911. STK = LEA(b+4) ; x21 N913. CNS_INT 0 N915. STOREIND ; STK $ N001. V12(x7) $ N001. V09(x5) Var=Reg end of BB65: V00=x19 V179=x25 V04=x27 V05=x28 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} ===== Predecessor for variable locations: BB60 Var=Reg beg of BB66: V00=x19 V179=x25 V04=x27 V05=x28 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N919. IL_OFFSET INLRT @ 0x2AE[E-] N921. IL_OFFSET INLRT @ 0x2B2[E-] N923. V06(x3*) N925. V05(x28) N927. STK = LT ; x3*,x28 N929. V05(x28) N931. V06(x3)R N933. x0 = SUB ; x28,x3 N935. CNS_INT 0 N937. x3 = SELECT ; STK,x0 * N939. V44(x3); x3 N941. IL_OFFSET INLRT @ 0x2B5[E-] N943. V44(x3*) * N945. V06(x22); x3* N947. IL_OFFSET INLRT @ 0x2B9[E-] N949. IL_OFFSET INLRT @ 0x2BD[E-] N951. V07(x4*) N953. V05(x28) N955. STK = GT ; x4*,x28 N957. V05(x28) N959. V07(x4)R N961. x0 = SUB ; x28,x4 N963. CNS_INT 0 N965. x4 = SELECT ; STK,x0 * N967. V45(x4); x4 N969. IL_OFFSET INLRT @ 0x2C0[E-] N971. V45(x4*) N973. V07(STK); x4* N975. IL_OFFSET INLRT @ 0x2C4[E-] S N977. V09(x5)R N979. CNS_INT 0 N981. JCMP ; x5 Var=Reg end of BB66: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} ===== Predecessor for variable locations: BB66 Var=Reg beg of BB73: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N985. IL_OFFSET INLRT @ 0x2C8[E-] N987. V05(x28) * N989. V08(x2); x28 N991. IL_OFFSET INLRT @ 0x2CB[E-] N993. CNS_INT 0 * N995. V14(x3) Var=Reg end of BB73: V00=x19 V179=x25 V04=x27 V05=x28 V08=x2 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB74 [2D0..2EE), preds={BB66} succs={BB78} ===== Predecessor for variable locations: BB66 Var=Reg beg of BB74: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N999. IL_OFFSET INLRT @ 0x2D0[E-] N1001. IL_OFFSET INLRT @ 0x2D9[E-] N1003. V01(x21) N1005. STK = LEA(b+4) ; x21 N1007. x3 = IND ; STK * N1009. V178(x3); x3 N1011. V178(x3) N1013. V05(x28) N1015. STK = GT ; x3,x28 N1017. V178(x3) N1019. V05(x28) N1021. x2 = SELECT ; STK,x3,x28 * N1023. V46(x2); x2 N1025. IL_OFFSET INLRT @ 0x2DC[E-] N1027. V46(x2*) * N1029. V08(x2); x2* N1031. IL_OFFSET INLRT @ 0x2E4[E-] N1033. V178(x3*) N1035. V05(x28) N1037. x3 = SUB ; x3*,x28 * N1039. V14(x3); x3 Var=Reg end of BB74: V00=x19 V179=x25 V04=x27 V05=x28 V08=x2 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB78 [000..30D) -> BB262 (cond), preds={BB73,BB74} succs={BB79,BB262} ===== Predecessor for variable locations: BB73 Var=Reg beg of BB78: V00=x19 V179=x25 V04=x27 V05=x28 V08=x2 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N1043. IL_OFFSET INLRT @ 0x2EE[E-] N1045. V15(x26) N1047. V16(STK); x26 N1049. IL_OFFSET INLRT @ 0x2F2[E-] N1051. IL_OFFSET INL09 @ 0x01F[E-] <- INLRT @ ??? N1053. x6 = LCL_VAR_ADDR V47 tmp7 x6 * N1055. V151(x6); x6 N1057. IL_OFFSET INL09 @ 0x026[E-] <- INLRT @ ??? N1059. IL_OFFSET INLRT @ 0x2FF[E-] N1061. V151(x6*) N1063. V143(STK); x6* N1065. x8 = CNS_INT 4 * N1067. V144(x8); x8 N1069. IL_OFFSET INLRT @ 0x303[E-] N1071. x9 = CNS_INT -1 * N1073. V20(x9); x9 N1075. IL_OFFSET INLRT @ 0x306[E-] N1077. V03(x20) N1079. STK = LEA(b+56); x20 N1081. x0 = IND ; STK N1083. STK = LEA(b+8) ; x0 N1085. x0 = IND ; STK N1087. CNS_INT 0 N1089. STK = LE ; x0 S N1091. V12(x7)R N1093. CNS_INT 0 N1095. STK = EQ ; x7 N1097. AND ; STK,STK N1099. JTRUE ; STK Var=Reg end of BB78: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} ===== Predecessor for variable locations: BB78 Var=Reg beg of BB79: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N1103. IL_OFFSET INLRT @ 0x30D[E-] N1105. IL_OFFSET INLRT @ 0x31E[E-] N1107. V03(x20) N1109. STK = LEA(b+8) ; x20 N1111. x10 = IND ; STK $ N1113. V26(x10)R; x10 N1115. IL_OFFSET INLRT @ 0x326[E-] N1117. CNS_INT 0 N1119. V27(STK) N1121. IL_OFFSET INLRT @ 0x329[E-] N1123. CNS_INT 0 * N1125. V28(x14) N1127. IL_OFFSET INLRT @ 0x32C[E-] N1129. V26(x10) N1131. STK = LEA(b+8) ; x10 N1133. x12 = IND ; STK $ N1135. V29(x12)R; x12 N1137. IL_OFFSET INLRT @ 0x332[E-] S N1139. V29(x12) N1141. CNS_INT 0 N1143. JCMP ; x12 Var=Reg end of BB79: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V26=x10 BB81 [336..33D), preds={BB79} succs={BB82} ===== Predecessor for variable locations: BB79 Var=Reg beg of BB81: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 N1147. IL_OFFSET INLRT @ 0x336[E-] S N1149. V26(x10) N1151. STK = LEA(b+16); x10 N1153. x14 = IND ; STK * N1155. V28(x14); x14 * N001. V26(x10)R Var=Reg end of BB81: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V26=x10 BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} ===== Predecessor for variable locations: BB79 Var=Reg beg of BB82: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V08=x2 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V26=x10 N1159. IL_OFFSET INLRT @ 0x33D[E-] S N1161. V28(x14) * N1163. V30(x15); x14 S N1165. V08(x2) * N1167. V64(x0); x2 N1169. IL_OFFSET INLRT @ 0x341[E-] N1171. V14(x3) N1173. CNS_INT 0 N1175. LT ; x3 N1177. JTRUE Var=Reg end of BB82: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V64=x0 BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} ===== Predecessor for variable locations: BB82 Var=Reg beg of BB83: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V64=x0 N1181. V64(x0*) * N1183. V65(x0); x0* N1185. CNS_INT 0 * N1187. V66(x11) Var=Reg end of BB83: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V65=x0 V66=x11 BB84 [34B..34D), preds={BB82} succs={BB85} ===== Predecessor for variable locations: BB82 Var=Reg beg of BB84: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V64=x0 N1191. V64(x0*) * N1193. V65(x0); x0* S N1195. V14(x3) * N1197. V66(x11); x3 * N001. V14(x3)R Var=Reg end of BB84: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V65=x0 V66=x11 BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} ===== Predecessor for variable locations: BB83 Var=Reg beg of BB85: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 V65=x0 V66=x11 N1201. V65(x0*) N1203. V66(x11*) N1205. x0 = ADD ; x0*,x11* * N1207. V31(x0); x0 N1209. IL_OFFSET INLRT @ 0x350[E-] N1211. IL_OFFSET INLRT @ 0x355[E-] N1213. V06(x22) N1215. V31(x0) N1217. STK = GT ; x22,x0 N1219. V06(x22) N1221. V31(x0*) N1223. xip0 = SELECT ; STK,x22,x0* * N1225. V67(xip0); xip0 N1227. IL_OFFSET INLRT @ 0x359[E-] N1229. V67(xip0*) $ N1231. V32(xip0)R; xip0* N1233. IL_OFFSET INLRT @ 0x3C2[E-] S N1235. V32(xip0) N1237. V30(x15) N1239. LE ; xip0,x15 N1241. JTRUE Var=Reg end of BB85: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} ===== Predecessor for variable locations: BB85 Var=Reg beg of BB89: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 N1245. IL_OFFSET INLRT @ 0x35E[E-] S N1247. V30(x15) N1249. CNS_INT 0 N1251. JCMP ; x15 Var=Reg end of BB89: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} ===== Predecessor for variable locations: BB89 Var=Reg beg of BB90: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 N1255. IL_OFFSET INLRT @ 0x362[E-] N1257. V20(x9*) N1259. CNS_INT 1 N1261. x9 = ADD ; x9* * N1263. V20(x9); x9 N1265. IL_OFFSET INLRT @ 0x368[E-] S N1267. V20(x9) N1269. V144(x8) N1271. LT ; x9,x8 N1273. JTRUE Var=Reg end of BB90: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} ===== Predecessor for variable locations: BB90 Var=Reg beg of BB91: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 $ N001. V14(x3) $ N001. V26(x10) N1277. IL_OFFSET INLRT @ 0x373[E-] S N1279. V144(x8) N1281. CNS_INT 1 N1283. x0 = LSH ; x8 N1285. x0 = CAST ; x0 N1287. x0 = PUTARG_REG; x0 N1289. x11 = CNS_INT(h) 0x4000000000421858 ftn N1291. x11 = PUTARG_REG; x11 N1293. x0 = CALL help r2r_ind; x0,x11 $ N1295. V33(x3)R; x0 N1297. IL_OFFSET INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] N1299. IL_OFFSET INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] N1301. V33(x3) N1303. CNS_INT 16 Fseq[] N1305. x0 = ADD ; x3 * N1307. V159(x0); x0 N1309. IL_OFFSET INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] S N1311. V33(x3) N1313. STK = LEA(b+8) ; x3 N1315. x2 = IND ; STK * N1317. V160(x2); x2 N1319. V159(x0*) * N1321. V161(x0); x0* N1323. V144(x4)R N1325. V160(x2*) N1327. GT ; x4,x2* N1329. JTRUE Var=Reg end of BB91: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V144=x4 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V161=x0 BB95 [000..392), preds={BB91} succs={BB100} ===== Predecessor for variable locations: BB91 Var=Reg beg of BB95: V00=x19 V179=x25 V04=x27 V05=x28 V06=x22 V144=x4 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V161=x0 N1333. IL_OFFSET INL17 @ 0x00F[E-] <- INLRT @ ??? N1335. V144(x4*) N1337. x2 = CAST ; x4* * N1339. V83(x2); x2 N1341. IL_OFFSET INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? N1343. V83(x2*) N1345. CNS_INT 2 N1347. x2 = LSH ; x2* N1349. x2 = PUTARG_REG; x2 N1351. V161(x0*) N1353. x0 = PUTARG_REG; x0* N1355. V143(x1*)R N1357. x1 = PUTARG_REG; x1* N1359. x11 = CNS_INT(h) 0x4000000000420490 ftn N1361. x11 = PUTARG_REG; x11 N1363. CALL r2r_ind; x2,x0,x1,x11 N1365. IL_OFFSET INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] N1367. IL_OFFSET INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N1369. V33(x0)R N1371. CNS_INT 16 Fseq[] N1373. x1 = ADD ; x0 * N1375. V163(x1); x1 N1377. IL_OFFSET INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] N1379. V33(x0*) N1381. STK = LEA(b+8) ; x0* N1383. x4 = IND ; STK * N1385. V164(x4); x4 N1387. IL_OFFSET INLRT @ 0x391[E-] N1389. V163(x1*) * N1391. V143(x2); x1* N1393. V164(x4*) * N1395. V144(x3); x4* $ N001. V143(x2) N001. V144(x3) * N002. x8 = COPY ; x3 * N001. V14(x3)R * N001. V26(x10)R Var=Reg end of BB95: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} ===== Predecessor for variable locations: BB90 Var=Reg beg of BB100: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V26=x10 N1399. IL_OFFSET INLRT @ 0x39A[E-] N1401. V20(x9)R S N1403. V144(x8) N1405. BOUNDS_CHECK_Rng -> BB254; x9,x8 S N1407. V143(x6)R S N1409. V20(x9) N1411. STK = CAST ; x9 N1413. CNS_INT 2 N1415. STK = BFIZ ; STK N1417. STK = LEA(b+(i*1)+0); x6,STK N1419. V28(x14)R N1421. STOREIND ; STK,x14 N1423. IL_OFFSET INLRT @ 0x3A6[E-] N1425. V27(x13)R N1427. V29(x12)R N1429. CNS_INT -1 N1431. x0 = ADD ; x12 N1433. GE ; x13,x0 N1435. JTRUE Var=Reg end of BB100: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V26=x10 V29=x12 BB101 [3AE..3BB), preds={BB100} succs={BB102} ===== Predecessor for variable locations: BB100 Var=Reg beg of BB101: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V26=x10 V29=x12 N1439. IL_OFFSET INLRT @ 0x3AE[E-] N1441. V27(x13*) N1443. CNS_INT 1 N1445. x13 = ADD ; x13* * N1447. V27(x13); x13 N1449. IL_OFFSET INLRT @ 0x3B4[E-] N1451. V27(x13) N1453. V26(x10) N1455. STK = LEA(b+8) ; x10 N1457. x15 = IND ; STK N1459. BOUNDS_CHECK_Rng -> BB254; x13,x15 N1461. V26(x10) N1463. CNS_INT 16 N1465. x0 = ADD ; x10 N1467. V27(x13) N1469. STK = CAST ; x13 N1471. CNS_INT 2 N1473. STK = BFIZ ; STK N1475. STK = LEA(b+(i*1)+0); x0,STK N1477. x15 = IND ; STK * N1479. V30(x0); x15 $ N001. V30(x0) Var=Reg end of BB101: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V26=x10 V29=x12 BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} ===== Predecessor for variable locations: BB100 Var=Reg beg of BB102: V00=x19 V179=x25 V04=x27 V05=x28 V14=x3 V06=x22 V03=x20 V01=x21 V15=x26 V28=x14 V17=x23 V180=x24 V27=x13 V26=x10 V29=x12 N1483. IL_OFFSET INLRT @ 0x3BB[E-] N1485. V28(x14*) N1487. V30(x15)R N1489. x14 = ADD ; x14*,x15 * N1491. V28(x14); x14 N1493. IL_OFFSET INLRT @ 0x3C2[E-] N1495. V32(xip0)R N1497. V28(x14) N1499. GT ; xip0,x14 $ N001. V28(x14) $ N001. V27(x13) $ N001. V29(x12) $ N001. V32(xip0) * N001. V144(x8)R * N001. V20(x9)R N1501. JTRUE Var=Reg end of BB102: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V30=x15 V26=x10 BB103 [3C8..3D0) -> BB112 (cond), preds={BB85,BB89,BB102,BB262} succs={BB104,BB112} ===== Predecessor for variable locations: BB89 Var=Reg beg of BB103: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N1505. IL_OFFSET INLRT @ 0x3C8[E-] N1507. V01(x21) N1509. STK = LEA(b+8) ; x21 N1511. x0 = IND ; STK N1513. CNS_INT 0 N1515. STK = EQ ; x0 S N1517. V16(x4)R N1519. CNS_INT 0 N1521. STK = NE ; x4 N1523. AND ; STK,STK N1525. JTRUE ; STK Var=Reg end of BB103: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} ===== Predecessor for variable locations: BB103 Var=Reg beg of BB104: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N1529. IL_OFFSET INLRT @ 0x3D0[E-] N1531. IL_OFFSET INLRT @ 0x3D4[E-] N1533. V01(x21) N1535. STK = LEA(b+4) ; x21 N1537. x0 = IND ; STK N1539. CNS_INT 0 N1541. JCMP ; x0 Var=Reg end of BB104: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} ===== Predecessor for variable locations: BB104 Var=Reg beg of BB106: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N1545. IL_OFFSET INLRT @ 0x3DC[E-] N1547. V03(x20) N1549. STK = LEA(b+40); x20 N1551. x11 = IND ; STK * N1553. V86(x11); x11 N1555. IL_OFFSET INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] N1557. V86(x11) N1559. CNS_INT null N1561. JCMP ; x11 Var=Reg end of BB106: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} ===== Predecessor for variable locations: BB106 Var=Reg beg of BB107: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 N1565. IL_OFFSET INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] N1567. V00(x19) N1569. STK = LEA(b+8) ; x19 N1571. x0 = IND ; STK * N1573. V87(x0); x0 N1575. IL_OFFSET INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] N1577. V86(x11) N1579. STK = LEA(b+8) ; x11 N1581. x10 = IND ; STK N1583. CNS_INT 1 N1585. STK = NE ; x10 N1587. V87(x0) N1589. V00(x19) N1591. STK = LEA(b+24); x19 N1593. x13 = IND ; STK N1595. STK = GE ; x0,x13 N1597. AND ; STK,STK N1599. JTRUE ; STK Var=Reg end of BB107: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 V87=x0 BB108 [3DC..3DD), preds={BB107} succs={BB112} ===== Predecessor for variable locations: BB107 Var=Reg beg of BB108: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 V87=x0 N1603. IL_OFFSET INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] N1605. IL_OFFSET INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] N1607. V00(x19) N1609. CNS_INT 16 N1611. x10 = ADD ; x19 * N1613. V88(x10); x10 N1615. IL_OFFSET INL26 @ ??? <- INLRT @ 0x3DC[E-] N1617. V87(x0) N1619. V88(x10) N1621. STK = LEA(b+8) ; x10 N1623. x13 = IND ; STK N1625. BOUNDS_CHECK_Rng -> BB254; x0,x13 N1627. V88(x10*) N1629. x10 = IND ; x10* N1631. V87(x0) N1633. STK = CAST ; x0 N1635. CNS_INT 1 N1637. x13 = BFIZ ; STK N1639. x10 = ADD ; x10,x13 N1641. V86(x11*) N1643. STK = LEA(b+12); x11* N1645. x11 = IND ; STK N1647. STOREIND ; x10,x11 N1649. IL_OFFSET INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] N1651. V87(x0*) N1653. CNS_INT 1 N1655. x0 = ADD ; x0* N1657. V00(x19) N1659. STK = LEA(b+8) ; x19 N1661. STOREIND ; STK,x0 Var=Reg end of BB108: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} ===== Predecessor for variable locations: BB107 Var=Reg beg of BB111: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 V86=x11 $ N001. V20(x9) $ N001. V14(x3) $ N001. V144(x8) N1665. IL_OFFSET INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] N1667. V00(x19) N1669. x0 = PUTARG_REG; x19 N1671. V86(x11*) N1673. x1 = PUTARG_REG; x11* N1675. x11 = CNS_INT(h) 0x4000000000431d58 ftn N1677. x11 = PUTARG_REG; x11 N1679. CALL r2r_ind; x0,x1,x11 * N001. V14(x3)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB111: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} ===== Predecessor for variable locations: BB103 Var=Reg beg of BB112: V00=x19 V179=x25 V04=x27 V20=x9 V05=x28 V14=x3 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N1683. IL_OFFSET INLRT @ 0x3E8[E-] N1685. CNS_INT 0 N1687. V21(STK) N1689. IL_OFFSET INLRT @ 0x3EB[E-] N1691. V180(x24*) * N1693. V165(x24); x24* N1695. IL_OFFSET INLRT @ 0x3EB[E-] N1697. V165(x24) N1699. V35 MEM; x24 N1701. IL_OFFSET INLRT @ 0x3F3[E-] N1703. V165(x24*) * N1705. V169(x24); x24* N1707. V169(x24*) * N1709. V34(x24); x24* N1711. IL_OFFSET INLRT @ 0x3F8[E-] N1713. V17(x23) * N1715. V36(x0); x23 Var=Reg end of BB112: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB266,BB268} succs={BB246,BB248} ===== Predecessor for variable locations: BB112 Var=Reg beg of BB245: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1719. IL_OFFSET INLRT @ 0x7AA[E-] N1721. V16(x4)R N1723. V179(x25) N1725. GE ; x4,x25 N1727. JTRUE Var=Reg end of BB245: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} ===== Predecessor for variable locations: BB245 Var=Reg beg of BB246: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1731. IL_OFFSET INLRT @ 0x7B5[E-] N1733. V16(x4*) * N1735. V49(x11); x4* N1737. IL_OFFSET INLRT @ 0x7B5[E-] N1739. V49(x11) N1741. CNS_INT 1 N1743. x4 = ADD ; x11 N1745. V16(STK); x4 N1747. V34(x24) N1749. V49(x11*) N1751. STK = CAST ; x11* N1753. CNS_INT 1 N1755. STK = BFIZ ; STK N1757. STK = LEA(b+(i*1)+0); x24,STK N1759. x13 = IND ; STK * N1761. V50(x13); x13 N1763. V50(x13*) * N1765. V18(x13); x13* N1767. V18(x13) N1769. CNS_INT 0 N1771. JCMP ; x13 Var=Reg end of BB246: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} ===== Predecessor for variable locations: BB246 Var=Reg beg of BB247: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1775. IL_OFFSET INLRT @ 0x7C8[E-] N1777. V18(x13) N1779. CNS_INT 59 N1781. NE ; x13 N1783. JTRUE Var=Reg end of BB247: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB113 [401..406) -> BB263 (cond), preds={BB247} succs={BB114,BB263} ===== Predecessor for variable locations: BB247 Var=Reg beg of BB113: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1787. IL_OFFSET INLRT @ 0x401[E-] N1789. V14(x3) N1791. CNS_INT 0 N1793. LE ; x3 N1795. JTRUE Var=Reg end of BB113: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} ===== Predecessor for variable locations: BB113 Var=Reg beg of BB114: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1799. IL_OFFSET INLRT @ 0x406[E-] N1801. V18(x13) N1803. CNS_INT 35 N1805. STK = EQ ; x13 N1807. V18(x13) N1809. x11 = CNS_INT 46 N1811. STK = EQ ; x13,x11 N1813. AND ; STK,STK N1815. JTRUE ; STK Var=Reg end of BB114: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB115 [40C..418) -> BB264 (cond), preds={BB114} succs={BB117,BB264} ===== Predecessor for variable locations: BB114 Var=Reg beg of BB115: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1819. IL_OFFSET INLRT @ 0x40C[E-] N1821. IL_OFFSET INLRT @ 0x412[E-] S N1823. V18(x13) N1825. CNS_INT 48 N1827. EQ ; x13 N1829. JTRUE Var=Reg end of BB115: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} ===== Predecessor for variable locations: BB115 Var=Reg beg of BB117: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 $ N001. V14(x3) * N001. V18(x13)R Var=Reg end of BB117: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB135 [46D..472) -> BB118 (cond), preds={BB114,BB134,BB264} succs={BB136,BB118} ===== Predecessor for variable locations: BB114 Var=Reg beg of BB135: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1835. IL_OFFSET INLRT @ 0x46D[E-] S N1837. V14(x3) N1839. CNS_INT 0 N1841. GT ; x3 N1843. JTRUE Var=Reg end of BB135: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} ===== Predecessor for variable locations: BB135 Var=Reg beg of BB118: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1847. IL_OFFSET INLRT @ 0x41A[E-] N1849. V36(x0) N1851. x11 = IND ; x0 * N1853. V177(x11); x11 N1855. V177(x11) N1857. CNS_INT 0 N1859. JCMP ; x11 Var=Reg end of BB118: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V177=x11 V01=x21 V15=x26 V17=x23 BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} ===== Predecessor for variable locations: BB118 Var=Reg beg of BB119: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1863. x14 = CNS_INT 48 * N1865. V63(x14); x14 Var=Reg end of BB119: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V63=x14 V01=x21 V15=x26 V17=x23 BB120 [424..42C), preds={BB118} succs={BB121} ===== Predecessor for variable locations: BB118 Var=Reg beg of BB120: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V177=x11 V01=x21 V15=x26 V17=x23 N1869. V36(x0*) * N1871. V61(x0); x0* N1873. V61(x0*) N1875. CNS_INT 1 N1877. x0 = ADD ; x0* N1879. V36(STK); x0 N1881. V177(x11*) * N1883. V63(x14); x11* * N001. V36(x0)R Var=Reg end of BB120: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V63=x14 V01=x21 V15=x26 V17=x23 BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} ===== Predecessor for variable locations: BB119 Var=Reg beg of BB121: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V63=x14 V01=x21 V15=x26 V17=x23 N1887. V63(x14*) N1889. x11 = CAST ; x14* * N1891. V92(x11); x11 N1893. IL_OFFSET INL29 @ 0x000[E-] <- INLRT @ ??? N1895. V00(x19) N1897. STK = LEA(b+8) ; x19 N1899. x14 = IND ; STK * N1901. V91(x14); x14 N1903. IL_OFFSET INL29 @ 0x007[E-] <- INLRT @ ??? N1905. V91(x14) N1907. V00(x19) N1909. STK = LEA(b+24); x19 N1911. x12 = IND ; STK N1913. GE ; x14,x12 N1915. JTRUE Var=Reg end of BB121: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V92=x11 V91=x14 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} ===== Predecessor for variable locations: BB121 Var=Reg beg of BB122: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V92=x11 V91=x14 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1919. IL_OFFSET INL29 @ 0x015[E-] <- INLRT @ ??? N1921. V00(x19) N1923. CNS_INT 16 N1925. x12 = ADD ; x19 * N1927. V93(x12); x12 N1929. V91(x14) N1931. V93(x12) N1933. STK = LEA(b+8) ; x12 N1935. x15 = IND ; STK N1937. BOUNDS_CHECK_Rng -> BB254; x14,x15 N1939. V93(x12*) N1941. x12 = IND ; x12* N1943. V91(x14) N1945. STK = CAST ; x14 N1947. CNS_INT 1 N1949. STK = BFIZ ; STK N1951. STK = LEA(b+(i*1)+0); x12,STK N1953. V92(x11*) N1955. STOREIND ; STK,x11* N1957. IL_OFFSET INL29 @ 0x023[E-] <- INLRT @ ??? N1959. V91(x14*) N1961. CNS_INT 1 N1963. x11 = ADD ; x14* N1965. V00(x19) N1967. STK = LEA(b+8) ; x19 N1969. STOREIND ; STK,x11 Var=Reg end of BB122: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB123 [000..000), preds={BB121} succs={BB124} ===== Predecessor for variable locations: BB121 Var=Reg beg of BB123: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V92=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 $ N001. V18(x13) $ N001. V20(x9) $ N001. V36(x0) $ N001. V144(x8) N1973. IL_OFFSET INL29 @ 0x02D[E-] <- INLRT @ ??? N1975. V00(x19) N1977. x0 = PUTARG_REG; x19 N1979. V92(x11*) N1981. x1 = PUTARG_REG; x11* N1983. x11 = CNS_INT(h) 0x4000000000435c58 ftn N1985. x11 = PUTARG_REG; x11 N1987. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V144(x8)R * N001. V20(x9)R * N001. V18(x13)R Var=Reg end of BB123: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} ===== Predecessor for variable locations: BB122 Var=Reg beg of BB124: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N1991. IL_OFFSET INLRT @ 0x431[E-] S N1993. V12(x7)R N1995. CNS_INT 0 N1997. STK = EQ ; x7 N1999. V08(x2)R N2001. CNS_INT 1 N2003. STK = LE ; x2 N2005. AND ; STK,STK N2007. JTRUE ; STK Var=Reg end of BB124: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB125 [435..43F) -> BB265 (cond), preds={BB124} succs={BB127,BB265} ===== Predecessor for variable locations: BB124 Var=Reg beg of BB125: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2011. IL_OFFSET INLRT @ 0x435[E-] N2013. IL_OFFSET INLRT @ 0x43A[E-] N2015. V20(x9) S N2017. V144(x8) N2019. BOUNDS_CHECK_Rng -> BB254; x9,x8 S N2021. V143(x6)R N2023. V20(x9) N2025. STK = CAST ; x9 N2027. CNS_INT 2 N2029. STK = BFIZ ; STK N2031. STK = LEA(b+(i*1)+0); x6,STK N2033. x11 = IND ; STK N2035. CNS_INT 1 N2037. x11 = ADD ; x11 S N2039. V08(x2) N2041. STK = NE ; x11,x2 S N2043. V20(x9) N2045. CNS_INT 0 N2047. STK = LT ; x9 N2049. AND ; STK,STK N2051. JTRUE ; STK Var=Reg end of BB125: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} ===== Predecessor for variable locations: BB125 Var=Reg beg of BB127: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 N2055. IL_OFFSET INLRT @ 0x43F[E-] N2057. IL_OFFSET INLRT @ 0x44F[E-] N2059. V03(x20) N2061. STK = LEA(b+56); x20 N2063. x11 = IND ; STK * N2065. V95(x11); x11 N2067. IL_OFFSET INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] N2069. V95(x11) N2071. CNS_INT null N2073. JCMP ; x11 Var=Reg end of BB127: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} ===== Predecessor for variable locations: BB127 Var=Reg beg of BB129: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 N2077. IL_OFFSET INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] N2079. V00(x19) N2081. STK = LEA(b+8) ; x19 N2083. x14 = IND ; STK * N2085. V96(x14); x14 N2087. IL_OFFSET INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] N2089. V95(x11) N2091. STK = LEA(b+8) ; x11 N2093. x12 = IND ; STK * N2095. V181(x12); x12 N2097. V181(x12) N2099. CNS_INT 1 N2101. STK = NE ; x12 N2103. V96(x14) N2105. V00(x19) N2107. STK = LEA(b+24); x19 N2109. x15 = IND ; STK N2111. STK = GE ; x14,x15 N2113. AND ; STK,STK N2115. JTRUE ; STK Var=Reg end of BB129: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V96=x14 V36=x0 V06=x22 V03=x20 V181=x12 V01=x21 V15=x26 V17=x23 BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} ===== Predecessor for variable locations: BB129 Var=Reg beg of BB130: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V96=x14 V36=x0 V06=x22 V03=x20 V181=x12 V01=x21 V15=x26 V17=x23 N2119. IL_OFFSET INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] N2121. IL_OFFSET INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] N2123. V00(x19) N2125. CNS_INT 16 N2127. x15 = ADD ; x19 * N2129. V97(x15); x15 N2131. IL_OFFSET INL32 @ ??? <- INLRT @ 0x44F[E-] N2133. V96(x14) N2135. V97(x15) N2137. STK = LEA(b+8) ; x15 N2139. xip0 = IND ; STK N2141. BOUNDS_CHECK_Rng -> BB254; x14,xip0 N2143. V97(x15*) N2145. x15 = IND ; x15* N2147. V96(x14) N2149. STK = CAST ; x14 N2151. CNS_INT 1 N2153. xip0 = BFIZ ; STK N2155. x15 = ADD ; x15,xip0 N2157. CNS_INT 0 N2159. V181(x12*) N2161. BOUNDS_CHECK_Rng -> BB254; x12* N2163. V95(x11*) N2165. STK = LEA(b+12); x11* N2167. x11 = IND ; STK N2169. STOREIND ; x15,x11 N2171. IL_OFFSET INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] N2173. V96(x14*) N2175. CNS_INT 1 N2177. x11 = ADD ; x14* N2179. V00(x19) N2181. STK = LEA(b+8) ; x19 N2183. STOREIND ; STK,x11 Var=Reg end of BB130: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB132 [44F..450), preds={BB129} succs={BB133} ===== Predecessor for variable locations: BB129 Var=Reg beg of BB132: V00=x19 V179=x25 V18=x13 V04=x27 V95=x11 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 $ N001. V18(x13) $ N001. V36(x0) N2187. IL_OFFSET INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] N2189. V00(x19) N2191. x0 = PUTARG_REG; x19 N2193. V95(x11*) N2195. x1 = PUTARG_REG; x11* N2197. x11 = CNS_INT(h) 0x4000000000431d58 ftn N2199. x11 = PUTARG_REG; x11 N2201. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V18(x13)R Var=Reg end of BB132: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} ===== Predecessor for variable locations: BB127 Var=Reg beg of BB133: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 N2205. IL_OFFSET INLRT @ 0x45B[E-] N2207. V20(x9*)R N2209. CNS_INT -1 N2211. x9 = ADD ; x9* N2213. V20(STK); x9 * N001. V08(x2)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB133: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB134 [461..46D), preds={BB124,BB133,BB265} succs={BB135} ===== Predecessor for variable locations: BB124 Var=Reg beg of BB134: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2217. IL_OFFSET INLRT @ 0x461[E-] N2219. V08(x2*) N2221. CNS_INT -1 N2223. x2 = ADD ; x2* N2225. V08(STK); x2 N2227. IL_OFFSET INLRT @ 0x467[E-] N2229. V14(x3*)R N2231. CNS_INT -1 N2233. x3 = ADD ; x3* N2235. V14(STK); x3 * N001. V14(x3)R Var=Reg end of BB134: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB136 [472..478) -> BB141 (cond), preds={BB117,BB135,BB263} succs={BB137,BB141} ===== Predecessor for variable locations: BB135 Var=Reg beg of BB136: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2239. IL_OFFSET INLRT @ 0x472[E-] N2241. V18(x13) N2243. CNS_INT 69 N2245. GT ; x13 N2247. JTRUE Var=Reg end of BB136: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB137 [478..478) -> BB138 (cond), preds={BB136} succs={BB257,BB138} ===== Predecessor for variable locations: BB136 Var=Reg beg of BB137: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2251. IL_OFFSET INLRT @ 0x478[E-] N2253. V18(x13) N2255. CNS_INT -34 N2257. x14 = ADD ; x13 * N2259. V184(x14); x14 N2261. V184(x14) N2263. CNS_INT 5 N2265. GT ; x14 N2267. JTRUE Var=Reg end of BB137: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V184=x14 BB138 [49A..49A) -> BB139 (cond), preds={BB137} succs={BB258,BB139} ===== Predecessor for variable locations: BB137 Var=Reg beg of BB138: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2271. IL_OFFSET INLRT @ 0x49A[E-] N2273. V18(x13) N2275. CNS_INT -44 N2277. x12 = ADD ; x13 * N2279. V185(x12); x12 N2281. V185(x12) N2283. CNS_INT 4 N2285. GT ; x12 N2287. JTRUE Var=Reg end of BB138: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V185=x12 BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} ===== Predecessor for variable locations: BB138 Var=Reg beg of BB139: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2291. IL_OFFSET INLRT @ 0x4B8[E-] N2293. V18(x13) N2295. CNS_INT 69 N2297. EQ ; x13 N2299. JTRUE Var=Reg end of BB139: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ===== Predecessor for variable locations: BB139 Var=Reg beg of BB140: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 Var=Reg end of BB140: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} ===== Predecessor for variable locations: BB136 Var=Reg beg of BB141: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2305. IL_OFFSET INLRT @ 0x4C6[E-] N2307. V18(x13) N2309. CNS_INT 92 N2311. EQ ; x13 N2313. JTRUE Var=Reg end of BB141: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} ===== Predecessor for variable locations: BB141 Var=Reg beg of BB142: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2317. IL_OFFSET INLRT @ 0x4CF[E-] N2319. V18(x13) N2321. CNS_INT 101 N2323. EQ ; x13 N2325. JTRUE Var=Reg end of BB142: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} ===== Predecessor for variable locations: BB142 Var=Reg beg of BB143: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2329. IL_OFFSET INLRT @ 0x4D8[E-] N2331. V18(x13) N2333. x11 = CNS_INT 0x2030 N2335. NE ; x13,x11 N2337. JTRUE Var=Reg end of BB143: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} ===== Predecessor for variable locations: BB143 Var=Reg beg of BB144: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2341. IL_OFFSET INLRT @ 0x598[E-] N2343. V03(x20) N2345. STK = LEA(b+136); x20 N2347. x11 = IND ; STK * N2349. V110(x11); x11 Var=Reg end of BB144: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} ===== Predecessor for variable locations: BB144 Var=Reg beg of BB181: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 N2353. IL_OFFSET INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] N2355. V110(x11) N2357. CNS_INT null * N001. V14(x3)R N2359. JCMP ; x11 Var=Reg end of BB181: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} ===== Predecessor for variable locations: BB112 Var=Reg beg of BB182: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 N2363. IL_OFFSET INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] N2365. V00(x19) N2367. STK = LEA(b+8) ; x19 N2369. x13 = IND ; STK * N2371. V111(x13); x13 N2373. IL_OFFSET INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] N2375. V110(x11) N2377. STK = LEA(b+8) ; x11 N2379. x14 = IND ; STK N2381. CNS_INT 1 N2383. STK = NE ; x14 N2385. V111(x13) N2387. V00(x19) N2389. STK = LEA(b+24); x19 N2391. x12 = IND ; STK N2393. STK = GE ; x13,x12 N2395. AND ; STK,STK N2397. JTRUE ; STK Var=Reg end of BB182: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 V111=x13 BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ===== Predecessor for variable locations: BB182 Var=Reg beg of BB183: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 V111=x13 N2401. IL_OFFSET INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] N2403. IL_OFFSET INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] N2405. V00(x19) N2407. CNS_INT 16 N2409. x14 = ADD ; x19 * N2411. V112(x14); x14 N2413. IL_OFFSET INL43 @ ??? <- INLRT @ 0x598[E-] N2415. V111(x13) N2417. V112(x14) N2419. STK = LEA(b+8) ; x14 N2421. x12 = IND ; STK N2423. BOUNDS_CHECK_Rng -> BB254; x13,x12 N2425. V112(x14*) N2427. x14 = IND ; x14* N2429. V111(x13) N2431. STK = CAST ; x13 N2433. CNS_INT 1 N2435. x12 = BFIZ ; STK N2437. x14 = ADD ; x14,x12 N2439. CNS_INT 0 N2441. V110(x11) N2443. STK = LEA(b+8) ; x11 N2445. x12 = IND ; STK N2447. BOUNDS_CHECK_Rng -> BB254; x12 N2449. V110(x11*) N2451. STK = LEA(b+12); x11* N2453. x11 = IND ; STK N2455. STOREIND ; x14,x11 N2457. IL_OFFSET INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] N2459. V111(x13*) N2461. CNS_INT 1 N2463. x11 = ADD ; x13* N2465. V00(x19) N2467. STK = LEA(b+8) ; x19 N2469. STOREIND ; STK,x11 Var=Reg end of BB183: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} ===== Predecessor for variable locations: BB182 Var=Reg beg of BB185: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V110=x11 V01=x21 V15=x26 V17=x23 $ N001. V20(x9) $ N001. V14(x3) $ N001. V36(x0) $ N001. V144(x8) N2473. IL_OFFSET INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] N2475. V00(x19) N2477. x0 = PUTARG_REG; x19 N2479. V110(x11*) N2481. x1 = PUTARG_REG; x11* N2483. x11 = CNS_INT(h) 0x4000000000431d58 ftn N2485. x11 = PUTARG_REG; x11 N2487. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V14(x3)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB185: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} ===== Predecessor for variable locations: BB141 Var=Reg beg of BB200: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2491. IL_OFFSET INLRT @ 0x618[E-] N2493. V16(x4) N2495. V179(x25) N2497. STK = GE ; x4,x25 N2499. V34(x24) N2501. V16(x4)R N2503. STK = CAST ; x4 N2505. CNS_INT 1 N2507. STK = BFIZ ; STK N2509. STK = LEA(b+(i*1)+0); x24,STK N2511. x13 = IND ; STK * N2513. V176(x13); x13 N2515. V176(x13) N2517. CNS_INT 0 N2519. STK = EQ ; x13 N2521. AND ; STK,STK $ N001. V16(x4) * N001. V14(x3)R N2523. JTRUE ; STK Var=Reg end of BB200: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V176=x13 BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} ===== Predecessor for variable locations: BB112 Var=Reg beg of BB201: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V176=x13 N2527. IL_OFFSET INLRT @ 0x626[E-] N2529. IL_OFFSET INLRT @ 0x634[E-] N2531. V16(x4*)R * N2533. V51(x4); x4* N2535. IL_OFFSET INLRT @ 0x634[E-] N2537. V51(x4*) N2539. CNS_INT 1 N2541. x4 = ADD ; x4* N2543. V16(STK); x4 N2545. V176(x13*) * N2547. V123(x13); x13* N2549. IL_OFFSET INL53 @ 0x000[E-] <- INLRT @ ??? N2551. V00(x19) N2553. STK = LEA(b+8) ; x19 N2555. x11 = IND ; STK * N2557. V122(x11); x11 N2559. IL_OFFSET INL53 @ 0x007[E-] <- INLRT @ ??? N2561. V122(x11) N2563. V00(x19) N2565. STK = LEA(b+24); x19 N2567. x14 = IND ; STK N2569. GE ; x11,x14 N2571. JTRUE Var=Reg end of BB201: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V123=x13 V122=x11 BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} ===== Predecessor for variable locations: BB201 Var=Reg beg of BB203: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V123=x13 V122=x11 N2575. IL_OFFSET INL53 @ 0x015[E-] <- INLRT @ ??? N2577. V00(x19) N2579. CNS_INT 16 N2581. x14 = ADD ; x19 * N2583. V124(x14); x14 N2585. V122(x11) N2587. V124(x14) N2589. STK = LEA(b+8) ; x14 N2591. x12 = IND ; STK N2593. BOUNDS_CHECK_Rng -> BB254; x11,x12 N2595. V124(x14*) N2597. x14 = IND ; x14* N2599. V122(x11) N2601. STK = CAST ; x11 N2603. CNS_INT 1 N2605. STK = BFIZ ; STK N2607. STK = LEA(b+(i*1)+0); x14,STK N2609. V123(x13*) N2611. STOREIND ; STK,x13* N2613. IL_OFFSET INL53 @ 0x023[E-] <- INLRT @ ??? N2615. V122(x11*) N2617. CNS_INT 1 N2619. x13 = ADD ; x11* N2621. V00(x19) N2623. STK = LEA(b+8) ; x19 N2625. STOREIND ; STK,x13 Var=Reg end of BB203: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} ===== Predecessor for variable locations: BB201 Var=Reg beg of BB204: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V123=x13 $ N001. V20(x9) $ N001. V14(x3) $ N001. V36(x0) $ N001. V144(x8) N2629. IL_OFFSET INL53 @ 0x02D[E-] <- INLRT @ ??? N2631. V00(x19) N2633. x0 = PUTARG_REG; x19 N2635. V123(x13*) N2637. x1 = PUTARG_REG; x13* N2639. x11 = CNS_INT(h) 0x4000000000435c58 ftn N2641. x11 = PUTARG_REG; x11 N2643. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V14(x3)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB204: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} ===== Predecessor for variable locations: BB139 Var=Reg beg of BB205: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N2647. IL_OFFSET INLRT @ 0x64D[E-] N2649. CNS_INT 0 * N2651. V37(x11) N2653. IL_OFFSET INLRT @ 0x650[E-] N2655. CNS_INT 0 * N2657. V38(x14) N2659. IL_OFFSET INLRT @ 0x653[E-] N2661. V09(x5)R N2663. CNS_INT 0 N2665. JCMP ; x5 Var=Reg end of BB205: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} ===== Predecessor for variable locations: BB205 Var=Reg beg of BB206: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2669. IL_OFFSET INLRT @ 0x65A[E-] N2671. V16(x4)R N2673. V179(x25) N2675. GE ; x4,x25 N2677. JTRUE Var=Reg end of BB206: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} ===== Predecessor for variable locations: BB206 Var=Reg beg of BB207: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2681. IL_OFFSET INLRT @ 0x665[E-] N2683. V34(x24) N2685. V16(x4) N2687. STK = CAST ; x4 N2689. CNS_INT 1 N2691. STK = BFIZ ; STK N2693. STK = LEA(b+(i*1)+0); x24,STK N2695. x12 = IND ; STK * N2697. V176(x12); x12 N2699. V176(x12*) N2701. CNS_INT 48 N2703. EQ ; x12* N2705. JTRUE Var=Reg end of BB207: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} ===== Predecessor for variable locations: BB206 Var=Reg beg of BB208: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2709. IL_OFFSET INLRT @ 0x67A[E-] N2711. V16(x4) N2713. CNS_INT 1 N2715. x12 = ADD ; x4 N2717. V179(x25) N2719. GE ; x12,x25 N2721. JTRUE Var=Reg end of BB208: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} ===== Predecessor for variable locations: BB208 Var=Reg beg of BB209: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2725. IL_OFFSET INLRT @ 0x687[E-] N2727. V34(x24) N2729. V16(x4) N2731. STK = CAST ; x4 N2733. CNS_INT 1 N2735. STK = BFIZ ; STK N2737. STK = LEA(b+(i*1)+0); x24,STK N2739. x12 = IND ; STK * N2741. V176(x12); x12 N2743. V176(x12) N2745. CNS_INT 43 N2747. x15 = NE ; x12 N2749. V34(x24) N2751. V16(x4) N2753. CNS_INT 1 N2755. xip0 = ADD ; x4 N2757. STK = CAST ; xip0 N2759. CNS_INT 1 N2761. STK = BFIZ ; STK N2763. STK = LEA(b+(i*1)+0); x24,STK N2765. xip0 = IND ; STK N2767. CNS_INT 48 N2769. xip0 = NE ; xip0 N2771. x15 = AND ; x15,xip0 N2773. JTRUE ; x15 Var=Reg end of BB209: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V176=x12 V37=x11 BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} ===== Predecessor for variable locations: BB209 Var=Reg beg of BB210: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 N2777. IL_OFFSET INLRT @ 0x694[E-] N2779. IL_OFFSET INLRT @ 0x6A3[E-] N2781. x11 = CNS_INT 1 * N2783. V37(x11); x11 Var=Reg end of BB210: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} ===== Predecessor for variable locations: BB209 Var=Reg beg of BB213: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V176=x12 V37=x11 N2787. IL_OFFSET INLRT @ 0x6B5[E-] N2789. V176(x12*) N2791. CNS_INT 45 N2793. NE ; x12* N2795. JTRUE Var=Reg end of BB213: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} ===== Predecessor for variable locations: BB213 Var=Reg beg of BB214: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2799. IL_OFFSET INLRT @ 0x6C2[E-] N2801. V34(x24) N2803. V16(x4) N2805. CNS_INT 1 N2807. x12 = ADD ; x4 N2809. STK = CAST ; x12 N2811. CNS_INT 1 N2813. STK = BFIZ ; STK N2815. STK = LEA(b+(i*1)+0); x24,STK N2817. x12 = IND ; STK N2819. CNS_INT 48 N2821. EQ ; x12 N2823. JTRUE Var=Reg end of BB214: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB215 [6D1..6DE) -> BB269 (cond), preds={BB208,BB213,BB214} succs={BB216,BB269} ===== Predecessor for variable locations: BB208 Var=Reg beg of BB215: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 N2827. IL_OFFSET INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] N2829. V00(x19) N2831. STK = LEA(b+8) ; x19 N2833. x14 = IND ; STK * N2835. V126(x14); x14 N2837. IL_OFFSET INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] N2839. V126(x14) N2841. V00(x19) N2843. STK = LEA(b+24); x19 N2845. x11 = IND ; STK N2847. GE ; x14,x11 N2849. JTRUE Var=Reg end of BB215: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V126=x14 BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} ===== Predecessor for variable locations: BB215 Var=Reg beg of BB216: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V126=x14 N2853. IL_OFFSET INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] N2855. V00(x19) N2857. CNS_INT 16 N2859. x11 = ADD ; x19 * N2861. V127(x11); x11 N2863. IL_OFFSET INL58 @ ??? <- INLRT @ 0x6D1[E-] N2865. V126(x14) N2867. V127(x11) N2869. STK = LEA(b+8) ; x11 N2871. x12 = IND ; STK N2873. BOUNDS_CHECK_Rng -> BB254; x14,x12 N2875. V127(x11*) N2877. x11 = IND ; x11* N2879. V126(x14) N2881. STK = CAST ; x14 N2883. CNS_INT 1 N2885. STK = BFIZ ; STK N2887. STK = LEA(b+(i*1)+0); x11,STK N2889. V18(x13*) N2891. STOREIND ; STK,x13* N2893. IL_OFFSET INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] N2895. V126(x14*) N2897. CNS_INT 1 N2899. x13 = ADD ; x14* N2901. V00(x19) N2903. STK = LEA(b+8) ; x19 N2905. STOREIND ; STK,x13 $ N001. V16(x4) $ N001. V09(x5) * N001. V14(x3)R Var=Reg end of BB216: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB218 [6DE..6E4), preds={BB207,BB271} succs={BB219} ===== Predecessor for variable locations: BB207 Var=Reg beg of BB218: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2909. IL_OFFSET INLRT @ 0x6DE[E-] N2911. V38(x14*) N2913. CNS_INT 1 N2915. x14 = ADD ; x14* * N2917. V38(x14); x14 Var=Reg end of BB218: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} ===== Predecessor for variable locations: BB218 Var=Reg beg of BB219: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2921. IL_OFFSET INLRT @ 0x6E4[E-] N2923. V16(x4*) N2925. CNS_INT 1 N2927. x4 = ADD ; x4* * N2929. V54(x4); x4 N2931. V54(x4*) * N2933. V16(x12); x4* N2935. V16(x12) N2937. V179(x25) N2939. GE ; x12,x25 N2941. JTRUE Var=Reg end of BB219: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB220 [6F4..701) -> BB271 (cond), preds={BB219} succs={BB270,BB271} ===== Predecessor for variable locations: BB219 Var=Reg beg of BB220: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2945. IL_OFFSET INLRT @ 0x6F4[E-] N2947. V34(x24) S N2949. V16(x12) N2951. STK = CAST ; x12 N2953. CNS_INT 1 N2955. STK = BFIZ ; STK N2957. STK = LEA(b+(i*1)+0); x24,STK N2959. x5 = IND ; STK N2961. CNS_INT 48 N2963. EQ ; x5 N2965. JTRUE Var=Reg end of BB220: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB221 [701..707) -> BB223 (cond), preds={BB219,BB270} succs={BB222,BB223} ===== Predecessor for variable locations: BB219 Var=Reg beg of BB221: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2969. IL_OFFSET INLRT @ 0x701[E-] N2971. V38(x14) N2973. CNS_INT 10 N2975. LE ; x14 N2977. JTRUE Var=Reg end of BB221: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB222 [707..70B), preds={BB221} succs={BB223} ===== Predecessor for variable locations: BB221 Var=Reg beg of BB222: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V37=x11 N2981. IL_OFFSET INLRT @ 0x707[E-] N2983. x14 = CNS_INT 10 * N2985. V38(x14); x14 Var=Reg end of BB222: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} ===== Predecessor for variable locations: BB221 Var=Reg beg of BB223: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N2989. IL_OFFSET INLRT @ 0x70B[E-] N2991. V17(x23) N2993. x5 = IND ; x23 N2995. CNS_INT 0 N2997. JCMP ; x5 Var=Reg end of BB223: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} ===== Predecessor for variable locations: BB223 Var=Reg beg of BB224: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N3001. IL_OFFSET INLRT @ 0x710[E-] N3003. V01(x21) N3005. STK = LEA(b+4) ; x21 N3007. x5 = IND ; STK N3009. V05(x28) N3011. x4 = SUB ; x5,x28 * N3013. V55(x4); x4 $ N001. V16(x12) $ N001. V20(x9) $ N001. V36(x0) $ N001. V144(x8) Var=Reg end of BB224: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 V55=x4 BB225 [71A..71B), preds={BB223} succs={BB226} ===== Predecessor for variable locations: BB223 Var=Reg beg of BB225: V16=x12 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 N3017. IL_OFFSET INLRT @ 0x71A[E-] N3019. CNS_INT 0 * N3021. V55(x4) $ N001. V16(x12) $ N001. V20(x9) $ N001. V36(x0) $ N001. V144(x8) Var=Reg end of BB225: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 V55=x4 BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} ===== Predecessor for variable locations: BB224 Var=Reg beg of BB226: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V38=x14 V01=x21 V15=x26 V17=x23 V37=x11 V55=x4 N3025. IL_OFFSET INLRT @ 0x71D[E-] N3027. V37(x11*) N3029. x5 = PUTARG_REG; x11* N3031. V00(x19) N3033. x0 = PUTARG_REG; x19 N3035. V03(x20) N3037. x1 = PUTARG_REG; x20 N3039. V55(x4*) N3041. x2 = PUTARG_REG; x4* N3043. V18(x13*) N3045. x3 = PUTARG_REG; x13* N3047. V38(x14*) N3049. x4 = PUTARG_REG; x14* N3051. x11 = CNS_INT(h) 0x4000000000540240 ftn N3053. x11 = PUTARG_REG; x11 N3055. CALL r2r_ind; x5,x0,x1,x2,x3,x4,x11 N3057. IL_OFFSET INLRT @ 0x72C[E-] N3059. CNS_INT 0 N3061. V09(STK) * N001. V36(x0)R * N001. V14(x3)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB226: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} ===== Predecessor for variable locations: BB205 Var=Reg beg of BB227: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 N3065. IL_OFFSET INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] N3067. V00(x19) N3069. STK = LEA(b+8) ; x19 N3071. x11 = IND ; STK * N3073. V129(x11); x11 N3075. IL_OFFSET INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] N3077. V129(x11) N3079. V00(x19) N3081. STK = LEA(b+24); x19 N3083. x14 = IND ; STK N3085. GE ; x11,x14 N3087. JTRUE Var=Reg end of BB227: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V129=x11 BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} ===== Predecessor for variable locations: BB227 Var=Reg beg of BB228: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V129=x11 N3091. IL_OFFSET INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] N3093. V00(x19) N3095. CNS_INT 16 N3097. x14 = ADD ; x19 * N3099. V130(x14); x14 N3101. IL_OFFSET INL61 @ ??? <- INLRT @ 0x731[E-] N3103. V129(x11) N3105. V130(x14) N3107. STK = LEA(b+8) ; x14 N3109. x12 = IND ; STK N3111. BOUNDS_CHECK_Rng -> BB254; x11,x12 N3113. V130(x14*) N3115. x14 = IND ; x14* N3117. V129(x11) N3119. STK = CAST ; x11 N3121. CNS_INT 1 N3123. STK = BFIZ ; STK N3125. STK = LEA(b+(i*1)+0); x14,STK N3127. V18(x13*) N3129. STOREIND ; STK,x13* N3131. IL_OFFSET INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] N3133. V129(x11*) N3135. CNS_INT 1 N3137. x13 = ADD ; x11* N3139. V00(x19) N3141. STK = LEA(b+8) ; x19 N3143. STOREIND ; STK,x13 Var=Reg end of BB228: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 BB229 [731..732), preds={BB227} succs={BB230} ===== Predecessor for variable locations: BB227 Var=Reg beg of BB229: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 $ N001. V20(x9) $ N001. V36(x0) $ N001. V144(x8) $ N001. V09(x5) N3147. IL_OFFSET INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] N3149. V00(x19) N3151. x0 = PUTARG_REG; x19 N3153. V18(x13*) N3155. x1 = PUTARG_REG; x13* N3157. x11 = CNS_INT(h) 0x4000000000435c58 ftn N3159. x11 = PUTARG_REG; x11 N3161. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V09(x5)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB229: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} ===== Predecessor for variable locations: BB228 Var=Reg beg of BB230: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 N3165. IL_OFFSET INLRT @ 0x739[E-] N3167. V16(x4)R N3169. V179(x25) N3171. GE ; x4,x25 $ N001. V16(x4) $ N001. V09(x5) * N001. V14(x3)R N3173. JTRUE Var=Reg end of BB230: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} ===== Predecessor for variable locations: BB112 Var=Reg beg of BB231: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3177. IL_OFFSET INLRT @ 0x744[E-] N3179. V34(x24) N3181. V16(x4)R N3183. STK = CAST ; x4 N3185. CNS_INT 1 N3187. STK = BFIZ ; STK N3189. STK = LEA(b+(i*1)+0); x24,STK N3191. x11 = IND ; STK * N3193. V175(x11); x11 N3195. V175(x11) N3197. CNS_INT 43 N3199. EQ ; x11 N3201. JTRUE Var=Reg end of BB231: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V175=x11 BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} ===== Predecessor for variable locations: BB231 Var=Reg beg of BB232: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V175=x11 N3205. IL_OFFSET INLRT @ 0x751[E-] N3207. V175(x11) N3209. CNS_INT 45 N3211. NE ; x11 N3213. JTRUE Var=Reg end of BB232: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V175=x11 BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} ===== Predecessor for variable locations: BB231 Var=Reg beg of BB233: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V175=x11 N3217. IL_OFFSET INLRT @ 0x75E[E-] N3219. V16(x4*) * N3221. V52(x4); x4* N3223. IL_OFFSET INLRT @ 0x75E[E-] N3225. V52(x4*) N3227. CNS_INT 1 N3229. x4 = ADD ; x4* N3231. V16(STK); x4 N3233. V175(x11*) * N3235. V133(x11); x11* N3237. IL_OFFSET INL64 @ 0x000[E-] <- INLRT @ ??? N3239. V00(x19) N3241. STK = LEA(b+8) ; x19 N3243. x13 = IND ; STK * N3245. V132(x13); x13 N3247. IL_OFFSET INL64 @ 0x007[E-] <- INLRT @ ??? N3249. V132(x13) N3251. V00(x19) N3253. STK = LEA(b+24); x19 N3255. x14 = IND ; STK N3257. GE ; x13,x14 N3259. JTRUE Var=Reg end of BB233: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V133=x11 V132=x13 BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ===== Predecessor for variable locations: BB233 Var=Reg beg of BB234: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V133=x11 V132=x13 N3263. IL_OFFSET INL64 @ 0x015[E-] <- INLRT @ ??? N3265. V00(x19) N3267. CNS_INT 16 N3269. x14 = ADD ; x19 * N3271. V134(x14); x14 N3273. V132(x13) N3275. V134(x14) N3277. STK = LEA(b+8) ; x14 N3279. x12 = IND ; STK N3281. BOUNDS_CHECK_Rng -> BB254; x13,x12 N3283. V134(x14*) N3285. x14 = IND ; x14* N3287. V132(x13) N3289. STK = CAST ; x13 N3291. CNS_INT 1 N3293. STK = BFIZ ; STK N3295. STK = LEA(b+(i*1)+0); x14,STK N3297. V133(x11*) N3299. STOREIND ; STK,x11* N3301. IL_OFFSET INL64 @ 0x023[E-] <- INLRT @ ??? N3303. V132(x13*) N3305. CNS_INT 1 N3307. x11 = ADD ; x13* N3309. V00(x19) N3311. STK = LEA(b+8) ; x19 N3313. STOREIND ; STK,x11 * N001. V16(x4)R Var=Reg end of BB234: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} ===== Predecessor for variable locations: BB233 Var=Reg beg of BB235: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V133=x11 $ N001. V20(x9) $ N001. V14(x3) $ N001. V36(x0) $ N001. V144(x8) N3317. IL_OFFSET INL64 @ 0x02D[E-] <- INLRT @ ??? N3319. V00(x19) N3321. x0 = PUTARG_REG; x19 N3323. V133(x11*) N3325. x1 = PUTARG_REG; x11* N3327. x11 = CNS_INT(h) 0x4000000000435c58 ftn N3329. x11 = PUTARG_REG; x11 N3331. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V14(x3)R * N001. V16(x4)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB235: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} ===== Predecessor for variable locations: BB232 Var=Reg beg of BB239: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3335. IL_OFFSET INLRT @ 0x788[E-] N3337. V16(x4) N3339. V179(x25) N3341. GE ; x4,x25 $ N001. V16(x4) N3343. JTRUE Var=Reg end of BB239: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} ===== Predecessor for variable locations: BB112 Var=Reg beg of BB240: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3347. IL_OFFSET INLRT @ 0x793[E-] N3349. V34(x24) N3351. V16(x4)R N3353. STK = CAST ; x4 N3355. CNS_INT 1 N3357. STK = BFIZ ; STK N3359. STK = LEA(b+(i*1)+0); x24,STK N3361. x11 = IND ; STK * N3363. V173(x11); x11 N3365. V173(x11) N3367. CNS_INT 48 N3369. EQ ; x11 N3371. JTRUE Var=Reg end of BB240: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V173=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} ===== Predecessor for variable locations: BB240 Var=Reg beg of BB236: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V173=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3375. IL_OFFSET INLRT @ 0x774[E-] N3377. V16(x4*) * N3379. V53(x4); x4* N3381. IL_OFFSET INLRT @ 0x774[E-] N3383. V53(x4*) N3385. CNS_INT 1 N3387. x4 = ADD ; x4* N3389. V16(STK); x4 N3391. V173(x11*) * N3393. V137(x11); x11* N3395. IL_OFFSET INL66 @ 0x000[E-] <- INLRT @ ??? N3397. V00(x19) N3399. STK = LEA(b+8) ; x19 N3401. x13 = IND ; STK * N3403. V136(x13); x13 N3405. IL_OFFSET INL66 @ 0x007[E-] <- INLRT @ ??? N3407. V136(x13) N3409. V00(x19) N3411. STK = LEA(b+24); x19 N3413. x14 = IND ; STK N3415. GE ; x13,x14 N3417. JTRUE Var=Reg end of BB236: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V137=x11 V14=x3 V136=x13 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} ===== Predecessor for variable locations: BB236 Var=Reg beg of BB237: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V137=x11 V14=x3 V136=x13 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3421. IL_OFFSET INL66 @ 0x015[E-] <- INLRT @ ??? N3423. V00(x19) N3425. CNS_INT 16 N3427. x14 = ADD ; x19 * N3429. V138(x14); x14 N3431. V136(x13) N3433. V138(x14) N3435. STK = LEA(b+8) ; x14 N3437. x12 = IND ; STK N3439. BOUNDS_CHECK_Rng -> BB254; x13,x12 N3441. V138(x14*) N3443. x14 = IND ; x14* N3445. V136(x13) N3447. STK = CAST ; x13 N3449. CNS_INT 1 N3451. STK = BFIZ ; STK N3453. STK = LEA(b+(i*1)+0); x14,STK N3455. V137(x11*) N3457. STOREIND ; STK,x11* N3459. IL_OFFSET INL66 @ 0x023[E-] <- INLRT @ ??? N3461. V136(x13*) N3463. CNS_INT 1 N3465. x11 = ADD ; x13* N3467. V00(x19) N3469. STK = LEA(b+8) ; x19 N3471. STOREIND ; STK,x11 * N001. V16(x4)R Var=Reg end of BB237: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB238 [000..000), preds={BB236} succs={BB239} ===== Predecessor for variable locations: BB236 Var=Reg beg of BB238: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V137=x11 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 $ N001. V20(x9) $ N001. V14(x3) $ N001. V36(x0) $ N001. V144(x8) N3475. IL_OFFSET INL66 @ 0x02D[E-] <- INLRT @ ??? N3477. V00(x19) N3479. x0 = PUTARG_REG; x19 N3481. V137(x11*) N3483. x1 = PUTARG_REG; x11* N3485. x11 = CNS_INT(h) 0x4000000000435c58 ftn N3487. x11 = PUTARG_REG; x11 N3489. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V14(x3)R * N001. V16(x4)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB238: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} ===== Predecessor for variable locations: BB240 Var=Reg beg of BB241: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 $ N001. V16(x4) Var=Reg end of BB241: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB242 [7A2..7AA) -> BB272 (cond), preds={BB140,BB143,BB257(2),BB258(2)} succs={BB243,BB272} ===== Predecessor for variable locations: BB140 Var=Reg beg of BB242: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3495. IL_OFFSET INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] N3497. V00(x19) N3499. STK = LEA(b+8) ; x19 N3501. x11 = IND ; STK * N3503. V140(x11); x11 N3505. IL_OFFSET INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] N3507. V140(x11) N3509. V00(x19) N3511. STK = LEA(b+24); x19 N3513. x14 = IND ; STK N3515. GE ; x11,x14 N3517. JTRUE Var=Reg end of BB242: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V140=x11 BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} ===== Predecessor for variable locations: BB242 Var=Reg beg of BB243: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V140=x11 N3521. IL_OFFSET INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] N3523. V00(x19) N3525. CNS_INT 16 N3527. x14 = ADD ; x19 * N3529. V141(x14); x14 N3531. IL_OFFSET INL69 @ ??? <- INLRT @ 0x7A2[E-] N3533. V140(x11) N3535. V141(x14) N3537. STK = LEA(b+8) ; x14 N3539. x12 = IND ; STK N3541. BOUNDS_CHECK_Rng -> BB254; x11,x12 N3543. V141(x14*) N3545. x14 = IND ; x14* N3547. V140(x11) N3549. STK = CAST ; x11 N3551. CNS_INT 1 N3553. STK = BFIZ ; STK N3555. STK = LEA(b+(i*1)+0); x14,STK N3557. V18(x13*) N3559. STOREIND ; STK,x13* N3561. IL_OFFSET INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] N3563. V140(x11*) N3565. CNS_INT 1 N3567. x13 = ADD ; x11* N3569. V00(x19) N3571. STK = LEA(b+8) ; x19 N3573. STOREIND ; STK,x13 * N001. V14(x3)R Var=Reg end of BB243: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB244 [7A2..7A3) -> BB245 (always), preds={BB269,BB272} succs={BB245} ===== Predecessor for variable locations: BB215 Var=Reg beg of BB244: V00=x19 V179=x25 V18=x13 V04=x27 V34=x24 V05=x28 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 N3577. IL_OFFSET INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] N3579. V00(x19) N3581. x0 = PUTARG_REG; x19 N3583. V18(x13*) N3585. x1 = PUTARG_REG; x13* N3587. x11 = CNS_INT(h) 0x4000000000435c58 ftn N3589. x11 = PUTARG_REG; x11 N3591. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V14(x3)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB244: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} ===== Predecessor for variable locations: BB245 Var=Reg beg of BB248: V00=x19 V03=x20 V01=x21 V15=x26 N3595. IL_OFFSET INLRT @ 0x7D1[E-] N3597. CNS_INT 0 N3599. V35 MEM N3601. IL_OFFSET INLRT @ 0x7D5[E-] N3603. V01(x21) N3605. STK = LEA(b+8) ; x21 N3607. x2 = IND ; STK N3609. CNS_INT 0 N3611. STK = EQ ; x2 N3613. V15(x26*) N3615. CNS_INT 0 N3617. STK = NE ; x26* N3619. AND ; STK,STK N3621. JTRUE ; STK Var=Reg end of BB248: V00=x19 V03=x20 V01=x21 BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} ===== Predecessor for variable locations: BB248 Var=Reg beg of BB249: V00=x19 V03=x20 V01=x21 N3625. IL_OFFSET INLRT @ 0x7DD[E-] N3627. IL_OFFSET INLRT @ 0x7E1[E-] N3629. V01(x21*) N3631. STK = LEA(b+4) ; x21* N3633. x2 = IND ; STK N3635. CNS_INT 0 N3637. x2 = NE ; x2 N3639. V00(x19) N3641. STK = LEA(b+8) ; x19 N3643. x0 = IND ; STK N3645. CNS_INT 0 N3647. x0 = LE ; x0 N3649. x2 = AND ; x2,x0 N3651. JTRUE ; x2 Var=Reg end of BB249: V00=x19 V03=x20 BB251 [7E9..7FF), preds={BB249} succs={BB253} ===== Predecessor for variable locations: BB249 Var=Reg beg of BB251: V00=x19 V03=x20 N3655. IL_OFFSET INLRT @ 0x7E9[E-] N3657. IL_OFFSET INLRT @ 0x7F2[E-] N3659. V03(x20*) N3661. STK = LEA(b+40); x20* N3663. x2 = IND ; STK N3665. x2 = PUTARG_REG; x2 N3667. V00(x19*) N3669. x0 = PUTARG_REG; x19* N3671. x11 = CNS_INT(h) 0x4000000000540210 ftn N3673. x11 = PUTARG_REG; x11 N3675. x1 = CNS_INT 0 N3677. x1 = PUTARG_REG; x1 N3679. CALL r2r_ind; x2,x0,x11,x1 Var=Reg end of BB251: none BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} ===== Predecessor for variable locations: BB248 Var=Reg beg of BB253: none N3683. IL_OFFSET INLRT @ 0x7FF[E-] N3685. RETURN Var=Reg end of BB253: none BB255 [061..083) -> BB31,BB17,BB259,BB30,BB259,BB31 (switch), preds={BB09} succs={BB17,BB30,BB31,BB259} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB255: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V182=x14 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3689. V182(x14*) N3691. x0 = CAST ; x14* N3693. x1 = JMPTABLE N3695. SWITCH_TABLE; x0,x1 Var=Reg end of BB255: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB17 [0CF..0D8) -> BB47 (always), preds={BB255} succs={BB47} ===== Predecessor for variable locations: BB255 Var=Reg beg of BB17: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3699. IL_OFFSET INLRT @ 0x0CF[E-] N3701. V04(x27*) N3703. CNS_INT 1 N3705. x27 = ADD ; x27* * N3707. V04(x27); x27 N001. V16(x10) * N002. x1 = COPY ; x10 Var=Reg end of BB17: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB30 [12C..137) -> BB47 (always), preds={BB255} succs={BB47} ===== Predecessor for variable locations: BB255 Var=Reg beg of BB30: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3711. IL_OFFSET INLRT @ 0x12C[E-] N3713. V13(x8*) N3715. CNS_INT 2 N3717. x8 = ADD ; x8* * N3719. V13(x8); x8 N001. V16(x10) * N002. x1 = COPY ; x10 Var=Reg end of BB30: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB31 [142..150) -> BB47 (cond), preds={BB32,BB255(2)} succs={BB32,BB47} ===== Predecessor for variable locations: BB255 Var=Reg beg of BB31: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3723. IL_OFFSET INLRT @ 0x142[E-] N3725. V16(x10) N3727. V179(x25) N3729. STK = GE ; x10,x25 N3731. V22(x9) N3733. V16(x10) N3735. STK = CAST ; x10 N3737. CNS_INT 1 N3739. STK = BFIZ ; STK N3741. STK = LEA(b+(i*1)+0); x9,STK N3743. x0 = IND ; STK * N3745. V171(x0); x0 N3747. V171(x0) N3749. CNS_INT 0 N3751. STK = EQ ; x0 N3753. AND ; STK,STK N001. V16(x10) * N002. x1 = COPY ; x10 N3755. JTRUE ; STK Var=Reg end of BB31: V16=x1 V00=x19 V179=x25 V18=x13 V171=x0 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB32: V16=x1 V00=x19 V179=x25 V18=x13 V171=x0 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3759. IL_OFFSET INLRT @ 0x150[E-] N3761. IL_OFFSET INLRT @ 0x15E[E-] N3763. V16(x1*) * N3765. V74(x1); x1* N3767. IL_OFFSET INLRT @ 0x15E[E-] N3769. V74(x1*) N3771. CNS_INT 1 N3773. x1 = ADD ; x1* N3775. V16(STK); x1 N3777. V171(x0*) N3779. V18(x13) N3781. NE ; x0*,x13 * N001. V16(x10)R N3783. JTRUE Var=Reg end of BB32: V16=x10 V00=x19 V179=x25 V18=x13 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} ===== Predecessor for variable locations: BB255 Var=Reg beg of BB34: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N001. V16(x10) * N002. x1 = COPY ; x10 Var=Reg end of BB34: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB256 [083..0A1) -> BB23,BB260,BB21,BB260,BB18 (switch), preds={BB10} succs={BB18,BB21,BB23,BB260} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB256: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V183=x12 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3789. V183(x12*) N3791. x13 = CAST ; x12* N3793. x0 = JMPTABLE N3795. SWITCH_TABLE; x13,x0 Var=Reg end of BB256: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB18 [0D8..0E0) -> BB20 (cond), preds={BB256} succs={BB19,BB20} ===== Predecessor for variable locations: BB256 Var=Reg beg of BB18: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3799. IL_OFFSET INLRT @ 0x0D8[E-] N3801. V06(x3)R N3803. x4 = CNS_INT 0x7FFFFFFF N3805. NE ; x3,x4 N3807. JTRUE Var=Reg end of BB18: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V06=x3 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB19 [0E0..0E2), preds={BB18} succs={BB20} ===== Predecessor for variable locations: BB18 Var=Reg beg of BB19: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3811. IL_OFFSET INLRT @ 0x0E0[E-] N3813. V04(x27) * N3815. V06(x3); x27 Var=Reg end of BB19: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V06=x3 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} ===== Predecessor for variable locations: BB18 Var=Reg beg of BB20: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V06=x3 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3819. IL_OFFSET INLRT @ 0x0E2[E-] N3821. V04(x27*) N3823. CNS_INT 1 N3825. x27 = ADD ; x27* * N3827. V04(x27); x27 N3829. IL_OFFSET INLRT @ 0x0E6[E-] N3831. V04(x27) * N3833. V07(x2); x27 $ N001. V06(x3) $ N001. V07(x2) N001. V16(x10) * N002. x1 = COPY ; x10 Var=Reg end of BB20: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB21 [0ED..0F4) -> BB47 (cond), preds={BB256} succs={BB22,BB47} ===== Predecessor for variable locations: BB256 Var=Reg beg of BB21: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3837. IL_OFFSET INLRT @ 0x0ED[E-] N3839. V05(x28) N3841. CNS_INT 0 N3843. GE ; x28 N001. V16(x10) * N002. x1 = COPY ; x10 N3845. JTRUE Var=Reg end of BB21: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB22: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3849. IL_OFFSET INLRT @ 0x0F4[E-] N3851. V04(x27) * N3853. V05(x28); x27 Var=Reg end of BB22: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB23 [0FB..102) -> BB47 (cond), preds={BB256} succs={BB24,BB47} ===== Predecessor for variable locations: BB256 Var=Reg beg of BB23: V16=x10 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3857. IL_OFFSET INLRT @ 0x0FB[E-] N3859. V04(x27) N3861. CNS_INT 0 N3863. STK = LE ; x27 N3865. V05(x28) N3867. CNS_INT 0 N3869. STK = GE ; x28 N3871. AND ; STK,STK N001. V16(x10) * N002. x1 = COPY ; x10 N3873. JTRUE ; STK Var=Reg end of BB23: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB24: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3877. IL_OFFSET INLRT @ 0x102[E-] N3879. IL_OFFSET INLRT @ 0x109[E-] N3881. V10(x6) N3883. CNS_INT 0 N3885. LT ; x6 N3887. JTRUE Var=Reg end of BB24: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} ===== Predecessor for variable locations: BB24 Var=Reg beg of BB26: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3891. IL_OFFSET INLRT @ 0x10E[E-] N3893. V10(x6) N3895. V04(x27) N3897. NE ; x6,x27 N3899. JTRUE Var=Reg end of BB26: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} ===== Predecessor for variable locations: BB26 Var=Reg beg of BB27: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3903. IL_OFFSET INLRT @ 0x113[E-] N3905. V11(x22*) N3907. CNS_INT 1 N3909. x22 = ADD ; x22* * N3911. V11(x22); x22 Var=Reg end of BB27: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB28 [11E..121), preds={BB26} succs={BB29} ===== Predecessor for variable locations: BB26 Var=Reg beg of BB28: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3915. IL_OFFSET INLRT @ 0x11E[E-] N3917. x7 = CNS_INT 1 N3919. V12(STK); x7 * N001. V12(x7)R Var=Reg end of BB28: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} ===== Predecessor for variable locations: BB24 Var=Reg beg of BB29: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V12=x7 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 N3923. IL_OFFSET INLRT @ 0x121[E-] N3925. V04(x27) * N3927. V10(x6); x27 N3929. IL_OFFSET INLRT @ 0x124[E-] N3931. x22 = CNS_INT 1 * N3933. V11(x22); x22 Var=Reg end of BB29: V16=x1 V00=x19 V179=x25 V22=x9 V04=x27 V05=x28 V13=x8 V10=x6 V12=x7 V11=x22 V09=x5 V03=x20 V01=x21 V15=x26 V17=x23 V180=x24 BB257 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194 (switch), preds={BB137} succs={BB145,BB186,BB194,BB242} ===== Predecessor for variable locations: BB137 Var=Reg beg of BB257: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V184=x14 N3937. V184(x14*) N3939. x11 = CAST ; x14* N3941. x14 = JMPTABLE N3943. SWITCH_TABLE; x11,x14 Var=Reg end of BB257: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB145 [4E9..4EE) -> BB150 (cond), preds={BB257,BB258} succs={BB146,BB150} ===== Predecessor for variable locations: BB257 Var=Reg beg of BB145: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3947. IL_OFFSET INLRT @ 0x4E9[E-] N3949. V14(x3)R N3951. CNS_INT 0 N3953. GE ; x3 N3955. JTRUE Var=Reg end of BB145: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} ===== Predecessor for variable locations: BB145 Var=Reg beg of BB146: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3959. IL_OFFSET INLRT @ 0x4EE[E-] N3961. V14(x3*) N3963. CNS_INT 1 N3965. x3 = ADD ; x3* N3967. V14(STK); x3 N3969. IL_OFFSET INLRT @ 0x4F4[E-] N3971. V08(x2)R N3973. V06(x22) N3975. LE ; x2,x22 N3977. JTRUE Var=Reg end of BB146: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} ===== Predecessor for variable locations: BB146 Var=Reg beg of BB147: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3981. IL_OFFSET INLRT @ 0x4F9[E-] N3983. CNS_INT 0 * N3985. V58(x13) Var=Reg end of BB147: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V58=x13 BB148 [4FC..4FE), preds={BB146} succs={BB149} ===== Predecessor for variable locations: BB146 Var=Reg beg of BB148: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N3989. IL_OFFSET INLRT @ 0x4FC[E-] N3991. x13 = CNS_INT 48 * N3993. V58(x13); x13 Var=Reg end of BB148: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V58=x13 BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} ===== Predecessor for variable locations: BB147 Var=Reg beg of BB149: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V58=x13 N3997. V58(x13*) N3999. x13 = CAST ; x13* * N4001. V18(x13); x13 Var=Reg end of BB149: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} ===== Predecessor for variable locations: BB145 Var=Reg beg of BB150: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4005. IL_OFFSET INLRT @ 0x502[E-] N4007. V36(x0) N4009. x13 = IND ; x0 N4011. CNS_INT 0 N4013. JCMP ; x13 Var=Reg end of BB150: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} ===== Predecessor for variable locations: BB150 Var=Reg beg of BB151: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4017. IL_OFFSET INLRT @ 0x507[E-] S N4019. V08(x2)R S N4021. V07(x1)R N4023. GT ; x2,x1 N4025. JTRUE Var=Reg end of BB151: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} ===== Predecessor for variable locations: BB151 Var=Reg beg of BB152: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4029. IL_OFFSET INLRT @ 0x50C[E-] N4031. CNS_INT 0 * N4033. V57(x11) Var=Reg end of BB152: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V57=x11 BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} ===== Predecessor for variable locations: BB151 Var=Reg beg of BB153: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4037. IL_OFFSET INLRT @ 0x50F[E-] N4039. x11 = CNS_INT 48 * N4041. V57(x11); x11 Var=Reg end of BB153: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V57=x11 BB154 [513..51B), preds={BB150} succs={BB155} ===== Predecessor for variable locations: BB150 Var=Reg beg of BB154: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4045. IL_OFFSET INLRT @ 0x513[E-] N4047. V36(x0*) * N4049. V56(x11); x0* N4051. IL_OFFSET INLRT @ 0x513[E-] N4053. V56(x11) N4055. CNS_INT 1 N4057. x0 = ADD ; x11 N4059. V36(STK); x0 N4061. V56(x11*) N4063. x11 = IND ; x11* * N4065. V57(x11); x11 * N001. V36(x0)R Var=Reg end of BB154: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V57=x11 BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} ===== Predecessor for variable locations: BB152 Var=Reg beg of BB155: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V57=x11 N4069. V57(x11*) N4071. x13 = CAST ; x11* * N4073. V18(x13); x13 $ N001. V14(x3) * N001. V08(x2)R Var=Reg end of BB155: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} ===== Predecessor for variable locations: BB149 Var=Reg beg of BB156: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4077. IL_OFFSET INLRT @ 0x51D[E-] N4079. V18(x13) N4081. CNS_INT 0 N4083. JCMP ; x13 Var=Reg end of BB156: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} ===== Predecessor for variable locations: BB156 Var=Reg beg of BB157: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4087. IL_OFFSET INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] N4089. V00(x19) N4091. STK = LEA(b+8) ; x19 N4093. x11 = IND ; STK * N4095. V99(x11); x11 N4097. IL_OFFSET INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] N4099. V99(x11) N4101. V00(x19) N4103. STK = LEA(b+24); x19 N4105. x14 = IND ; STK N4107. GE ; x11,x14 N4109. JTRUE Var=Reg end of BB157: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V99=x11 BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} ===== Predecessor for variable locations: BB157 Var=Reg beg of BB158: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V99=x11 N4113. IL_OFFSET INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] N4115. V00(x19) N4117. CNS_INT 16 N4119. x14 = ADD ; x19 * N4121. V100(x14); x14 N4123. IL_OFFSET INL34 @ ??? <- INLRT @ 0x521[E-] N4125. V99(x11) N4127. V100(x14) N4129. STK = LEA(b+8) ; x14 N4131. x12 = IND ; STK N4133. BOUNDS_CHECK_Rng -> BB254; x11,x12 N4135. V100(x14*) N4137. x14 = IND ; x14* N4139. V99(x11) N4141. STK = CAST ; x11 N4143. CNS_INT 1 N4145. STK = BFIZ ; STK N4147. STK = LEA(b+(i*1)+0); x14,STK N4149. V18(x13*) N4151. STOREIND ; STK,x13* N4153. IL_OFFSET INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] N4155. V99(x11*) N4157. CNS_INT 1 N4159. x13 = ADD ; x11* N4161. V00(x19) N4163. STK = LEA(b+8) ; x19 N4165. STOREIND ; STK,x13 Var=Reg end of BB158: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB159 [521..522), preds={BB157} succs={BB160} ===== Predecessor for variable locations: BB157 Var=Reg beg of BB159: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 $ N001. V20(x9) $ N001. V08(x2) $ N001. V36(x0) $ N001. V144(x8) N4169. IL_OFFSET INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] N4171. V00(x19) N4173. x0 = PUTARG_REG; x19 N4175. V18(x13*) N4177. x1 = PUTARG_REG; x13* N4179. x11 = CNS_INT(h) 0x4000000000435c58 ftn N4181. x11 = PUTARG_REG; x11 N4183. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V08(x2)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB159: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} ===== Predecessor for variable locations: BB158 Var=Reg beg of BB160: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4187. IL_OFFSET INLRT @ 0x529[E-] S N4189. V12(x7)R N4191. CNS_INT 0 N4193. STK = EQ ; x7 N4195. V08(x2) N4197. CNS_INT 1 N4199. STK = LE ; x2 N4201. AND ; STK,STK N4203. JTRUE ; STK Var=Reg end of BB160: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB161 [52D..537) -> BB267 (cond), preds={BB160} succs={BB163,BB267} ===== Predecessor for variable locations: BB160 Var=Reg beg of BB161: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4207. IL_OFFSET INLRT @ 0x52D[E-] N4209. IL_OFFSET INLRT @ 0x532[E-] N4211. V20(x9) S N4213. V144(x8) N4215. BOUNDS_CHECK_Rng -> BB254; x9,x8 S N4217. V143(x6)R N4219. V20(x9) N4221. STK = CAST ; x9 N4223. CNS_INT 2 N4225. STK = BFIZ ; STK N4227. STK = LEA(b+(i*1)+0); x6,STK N4229. x11 = IND ; STK N4231. CNS_INT 1 N4233. x11 = ADD ; x11 S N4235. V08(x2) N4237. STK = NE ; x11,x2 S N4239. V20(x9) N4241. CNS_INT 0 N4243. STK = LT ; x9 N4245. AND ; STK,STK N4247. JTRUE ; STK Var=Reg end of BB161: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} ===== Predecessor for variable locations: BB161 Var=Reg beg of BB163: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 N4251. IL_OFFSET INLRT @ 0x537[E-] N4253. IL_OFFSET INLRT @ 0x547[E-] N4255. V03(x20) N4257. STK = LEA(b+56); x20 N4259. x11 = IND ; STK * N4261. V102(x11); x11 N4263. IL_OFFSET INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] N4265. V102(x11) N4267. CNS_INT null N4269. JCMP ; x11 Var=Reg end of BB163: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} ===== Predecessor for variable locations: BB163 Var=Reg beg of BB165: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 N4273. IL_OFFSET INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] N4275. V00(x19) N4277. STK = LEA(b+8) ; x19 N4279. x13 = IND ; STK * N4281. V103(x13); x13 N4283. IL_OFFSET INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] N4285. V102(x11) N4287. STK = LEA(b+8) ; x11 N4289. x14 = IND ; STK N4291. CNS_INT 1 N4293. STK = NE ; x14 N4295. V103(x13) N4297. V00(x19) N4299. STK = LEA(b+24); x19 N4301. x12 = IND ; STK N4303. STK = GE ; x13,x12 N4305. AND ; STK,STK N4307. JTRUE ; STK Var=Reg end of BB165: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 V103=x13 BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} ===== Predecessor for variable locations: BB165 Var=Reg beg of BB166: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 V103=x13 N4311. IL_OFFSET INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] N4313. IL_OFFSET INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] N4315. V00(x19) N4317. CNS_INT 16 N4319. x14 = ADD ; x19 * N4321. V104(x14); x14 N4323. IL_OFFSET INL37 @ ??? <- INLRT @ 0x547[E-] N4325. V103(x13) N4327. V104(x14) N4329. STK = LEA(b+8) ; x14 N4331. x12 = IND ; STK N4333. BOUNDS_CHECK_Rng -> BB254; x13,x12 N4335. V104(x14*) N4337. x14 = IND ; x14* N4339. V103(x13) N4341. STK = CAST ; x13 N4343. CNS_INT 1 N4345. x12 = BFIZ ; STK N4347. x14 = ADD ; x14,x12 N4349. CNS_INT 0 N4351. V102(x11) N4353. STK = LEA(b+8) ; x11 N4355. x12 = IND ; STK N4357. BOUNDS_CHECK_Rng -> BB254; x12 N4359. V102(x11*) N4361. STK = LEA(b+12); x11* N4363. x11 = IND ; STK N4365. STOREIND ; x14,x11 N4367. IL_OFFSET INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] N4369. V103(x13*) N4371. CNS_INT 1 N4373. x11 = ADD ; x13* N4375. V00(x19) N4377. STK = LEA(b+8) ; x19 N4379. STOREIND ; STK,x11 Var=Reg end of BB166: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB168 [547..548), preds={BB165} succs={BB169} ===== Predecessor for variable locations: BB165 Var=Reg beg of BB168: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V102=x11 V01=x21 V15=x26 V17=x23 $ N001. V36(x0) N4383. IL_OFFSET INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] N4385. V00(x19) N4387. x0 = PUTARG_REG; x19 N4389. V102(x11*) N4391. x1 = PUTARG_REG; x11* N4393. x11 = CNS_INT(h) 0x4000000000431d58 ftn N4395. x11 = PUTARG_REG; x11 N4397. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R Var=Reg end of BB168: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} ===== Predecessor for variable locations: BB163 Var=Reg beg of BB169: V00=x19 V179=x25 V04=x27 V34=x24 V05=x28 V36=x0 V06=x22 V03=x20 V01=x21 V15=x26 V17=x23 N4401. IL_OFFSET INLRT @ 0x553[E-] N4403. V20(x9*)R N4405. CNS_INT -1 N4407. x9 = ADD ; x9* N4409. V20(STK); x9 * N001. V08(x2)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB169: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB169,BB267} succs={BB245} ===== Predecessor for variable locations: BB156 Var=Reg beg of BB170: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V08=x2 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4413. IL_OFFSET INLRT @ 0x559[E-] N4415. V08(x2*) N4417. CNS_INT -1 N4419. x2 = ADD ; x2* N4421. V08(STK); x2 * N001. V14(x3)R Var=Reg end of BB170: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB186 [5A9..5BA) -> BB245 (cond), preds={BB257} succs={BB187,BB245} ===== Predecessor for variable locations: BB257 Var=Reg beg of BB186: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4425. IL_OFFSET INLRT @ 0x5A9[E-] N4427. V03(x20) N4429. STK = LEA(b+128); x20 N4431. x11 = IND ; STK * N4433. V114(x11); x11 N4435. IL_OFFSET INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] N4437. V114(x11) N4439. CNS_INT null * N001. V14(x3)R N4441. JCMP ; x11 Var=Reg end of BB186: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} ===== Predecessor for variable locations: BB112 Var=Reg beg of BB187: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 N4445. IL_OFFSET INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] N4447. V00(x19) N4449. STK = LEA(b+8) ; x19 N4451. x13 = IND ; STK * N4453. V115(x13); x13 N4455. IL_OFFSET INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] N4457. V114(x11) N4459. STK = LEA(b+8) ; x11 N4461. x14 = IND ; STK N4463. CNS_INT 1 N4465. STK = NE ; x14 N4467. V115(x13) N4469. V00(x19) N4471. STK = LEA(b+24); x19 N4473. x12 = IND ; STK N4475. STK = GE ; x13,x12 N4477. AND ; STK,STK N4479. JTRUE ; STK Var=Reg end of BB187: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 V115=x13 BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ===== Predecessor for variable locations: BB187 Var=Reg beg of BB188: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 V115=x13 N4483. IL_OFFSET INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] N4485. IL_OFFSET INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] N4487. V00(x19) N4489. CNS_INT 16 N4491. x14 = ADD ; x19 * N4493. V116(x14); x14 N4495. IL_OFFSET INL46 @ ??? <- INLRT @ 0x5A9[E-] N4497. V115(x13) N4499. V116(x14) N4501. STK = LEA(b+8) ; x14 N4503. x12 = IND ; STK N4505. BOUNDS_CHECK_Rng -> BB254; x13,x12 N4507. V116(x14*) N4509. x14 = IND ; x14* N4511. V115(x13) N4513. STK = CAST ; x13 N4515. CNS_INT 1 N4517. x12 = BFIZ ; STK N4519. x14 = ADD ; x14,x12 N4521. CNS_INT 0 N4523. V114(x11) N4525. STK = LEA(b+8) ; x11 N4527. x12 = IND ; STK N4529. BOUNDS_CHECK_Rng -> BB254; x12 N4531. V114(x11*) N4533. STK = LEA(b+12); x11* N4535. x11 = IND ; STK N4537. STOREIND ; x14,x11 N4539. IL_OFFSET INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] N4541. V115(x13*) N4543. CNS_INT 1 N4545. x11 = ADD ; x13* N4547. V00(x19) N4549. STK = LEA(b+8) ; x19 N4551. STOREIND ; STK,x11 Var=Reg end of BB188: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} ===== Predecessor for variable locations: BB187 Var=Reg beg of BB190: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V114=x11 V01=x21 V15=x26 V17=x23 $ N001. V20(x9) $ N001. V14(x3) $ N001. V36(x0) $ N001. V144(x8) N4555. IL_OFFSET INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] N4557. V00(x19) N4559. x0 = PUTARG_REG; x19 N4561. V114(x11*) N4563. x1 = PUTARG_REG; x11* N4565. x11 = CNS_INT(h) 0x4000000000431d58 ftn N4567. x11 = PUTARG_REG; x11 N4569. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V14(x3)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB190: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB194 [5CE..5D9) -> BB197 (cond), preds={BB192,BB193,BB257(2)} succs={BB195,BB197} ===== Predecessor for variable locations: BB257 Var=Reg beg of BB194: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4573. IL_OFFSET INLRT @ 0x5CE[E-] N4575. V16(x4)R N4577. V179(x25) N4579. GE ; x4,x25 N4581. JTRUE Var=Reg end of BB194: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} ===== Predecessor for variable locations: BB194 Var=Reg beg of BB195: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4585. IL_OFFSET INLRT @ 0x5D9[E-] N4587. V34(x24) N4589. V16(x4) N4591. STK = CAST ; x4 N4593. CNS_INT 1 N4595. STK = BFIZ ; STK N4597. STK = LEA(b+(i*1)+0); x24,STK N4599. x14 = IND ; STK * N4601. V172(x14); x14 N4603. V172(x14) N4605. CNS_INT 0 N4607. JCMP ; x14 Var=Reg end of BB195: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V172=x14 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} ===== Predecessor for variable locations: BB195 Var=Reg beg of BB196: V16=x4 V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V172=x14 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4611. IL_OFFSET INLRT @ 0x5E4[E-] N4613. V172(x14) S N4615. V18(x13) N4617. NE ; x14,x13 N4619. JTRUE Var=Reg end of BB196: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V172=x14 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} ===== Predecessor for variable locations: BB196 Var=Reg beg of BB191: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V172=x14 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4623. IL_OFFSET INLRT @ 0x5BA[E-] N4625. V16(x4*) * N4627. V59(x4); x4* N4629. IL_OFFSET INLRT @ 0x5BA[E-] N4631. V59(x4*) N4633. CNS_INT 1 N4635. x4 = ADD ; x4* N4637. V16(STK); x4 N4639. V172(x14*) * N4641. V119(x14); x14* N4643. IL_OFFSET INL48 @ 0x000[E-] <- INLRT @ ??? N4645. V00(x19) N4647. STK = LEA(b+8) ; x19 N4649. x11 = IND ; STK * N4651. V118(x11); x11 N4653. IL_OFFSET INL48 @ 0x007[E-] <- INLRT @ ??? N4655. V118(x11) N4657. V00(x19) N4659. STK = LEA(b+24); x19 N4661. x12 = IND ; STK N4663. GE ; x11,x12 N4665. JTRUE Var=Reg end of BB191: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V119=x14 V118=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} ===== Predecessor for variable locations: BB191 Var=Reg beg of BB192: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V119=x14 V118=x11 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4669. IL_OFFSET INL48 @ 0x015[E-] <- INLRT @ ??? N4671. V00(x19) N4673. CNS_INT 16 N4675. x12 = ADD ; x19 * N4677. V120(x12); x12 N4679. V118(x11) N4681. V120(x12) N4683. STK = LEA(b+8) ; x12 N4685. x15 = IND ; STK N4687. BOUNDS_CHECK_Rng -> BB254; x11,x15 N4689. V120(x12*) N4691. x12 = IND ; x12* N4693. V118(x11) N4695. STK = CAST ; x11 N4697. CNS_INT 1 N4699. STK = BFIZ ; STK N4701. STK = LEA(b+(i*1)+0); x12,STK N4703. V119(x14*) N4705. STOREIND ; STK,x14* N4707. IL_OFFSET INL48 @ 0x023[E-] <- INLRT @ ??? N4709. V118(x11*) N4711. CNS_INT 1 N4713. x14 = ADD ; x11* N4715. V00(x19) N4717. STK = LEA(b+8) ; x19 N4719. STOREIND ; STK,x14 * N001. V18(x13)R Var=Reg end of BB192: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB193 [000..000), preds={BB191} succs={BB194} ===== Predecessor for variable locations: BB191 Var=Reg beg of BB193: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V119=x14 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 $ N001. V20(x9) $ N001. V36(x0) $ N001. V144(x8) N4723. IL_OFFSET INL48 @ 0x02D[E-] <- INLRT @ ??? N4725. V00(x19) N4727. x0 = PUTARG_REG; x19 N4729. V119(x14*) N4731. x1 = PUTARG_REG; x14* N4733. x11 = CNS_INT(h) 0x4000000000435c58 ftn N4735. x11 = PUTARG_REG; x11 N4737. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V144(x8)R * N001. V20(x9)R * N001. V18(x13)R Var=Reg end of BB193: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB197 [5F1..5FF) -> BB268 (cond), preds={BB194,BB196} succs={BB198,BB268} ===== Predecessor for variable locations: BB194 Var=Reg beg of BB197: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4741. IL_OFFSET INLRT @ 0x5F1[E-] N4743. V16(x4) N4745. V179(x25) N4747. GE ; x4,x25 N4749. JTRUE Var=Reg end of BB197: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} ===== Predecessor for variable locations: BB195 Var=Reg beg of BB198: V16=x4 V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4753. IL_OFFSET INLRT @ 0x5FF[E-] N4755. V34(x24) N4757. V16(x4) N4759. STK = CAST ; x4 N4761. CNS_INT 1 N4763. STK = BFIZ ; STK N4765. STK = LEA(b+(i*1)+0); x24,STK N4767. x14 = IND ; STK * N4769. V172(x14); x14 N4771. V172(x14*) N4773. CNS_INT 0 $ N001. V16(x4) * N001. V14(x3)R N4775. JCMP ; x14* Var=Reg end of BB198: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} ===== Predecessor for variable locations: BB112 Var=Reg beg of BB199: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4779. IL_OFFSET INLRT @ 0x60D[E-] N4781. V16(x4*)R N4783. CNS_INT 1 N4785. x4 = ADD ; x4* N4787. V16(STK); x4 Var=Reg end of BB199: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB258 [49A..4B8) -> BB266,BB242,BB171,BB242,BB145 (switch), preds={BB138} succs={BB145,BB171,BB242,BB266} ===== Predecessor for variable locations: BB138 Var=Reg beg of BB258: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 V185=x12 N4791. V185(x12*) N4793. x11 = CAST ; x12* N4795. x14 = JMPTABLE N4797. SWITCH_TABLE; x11,x14 Var=Reg end of BB258: V00=x19 V179=x25 V18=x13 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB171 [564..571) -> BB245 (cond), preds={BB258} succs={BB172,BB245} ===== Predecessor for variable locations: BB258 Var=Reg beg of BB171: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4801. IL_OFFSET INLRT @ 0x564[E-] S N4803. V08(x2)R N4805. CNS_INT 0 N4807. x11 = NE ; x2 N4809. V21(x10)R N4811. x11 = OR ; x11,x10 N4813. CNS_INT 0 $ N001. V21(x10) * N001. V14(x3)R N4815. JCMP ; x11 Var=Reg end of BB171: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} ===== Predecessor for variable locations: BB112 Var=Reg beg of BB172: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4819. IL_OFFSET INLRT @ 0x571[E-] S N4821. V07(x1)R N4823. CNS_INT 0 N4825. LT ; x1 N4827. JTRUE Var=Reg end of BB172: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} ===== Predecessor for variable locations: BB172 Var=Reg beg of BB173: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4831. IL_OFFSET INLRT @ 0x575[E-] N4833. V05(x28) N4835. V04(x27) N4837. STK = GE ; x28,x27 S N4839. V36(x0) N4841. x11 = IND ; x0 N4843. CNS_INT 0 N4845. STK = EQ ; x11 N4847. AND ; STK,STK * N001. V36(x0)R N4849. JTRUE ; STK Var=Reg end of BB173: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} ===== Predecessor for variable locations: BB172 Var=Reg beg of BB174: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N4853. IL_OFFSET INLRT @ 0x57C[E-] N4855. IL_OFFSET INLRT @ 0x584[E-] N4857. V03(x20) N4859. STK = LEA(b+48); x20 N4861. x11 = IND ; STK * N4863. V106(x11); x11 N4865. IL_OFFSET INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] N4867. V106(x11) N4869. CNS_INT null N4871. JCMP ; x11 Var=Reg end of BB174: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} ===== Predecessor for variable locations: BB174 Var=Reg beg of BB176: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 N4875. IL_OFFSET INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] N4877. V00(x19) N4879. STK = LEA(b+8) ; x19 N4881. x10 = IND ; STK * N4883. V107(x10); x10 N4885. IL_OFFSET INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] N4887. V106(x11) N4889. STK = LEA(b+8) ; x11 N4891. x13 = IND ; STK N4893. CNS_INT 1 N4895. STK = NE ; x13 N4897. V107(x10) N4899. V00(x19) N4901. STK = LEA(b+24); x19 N4903. x14 = IND ; STK N4905. STK = GE ; x10,x14 N4907. AND ; STK,STK N4909. JTRUE ; STK Var=Reg end of BB176: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 V107=x10 BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} ===== Predecessor for variable locations: BB176 Var=Reg beg of BB177: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 V107=x10 N4913. IL_OFFSET INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] N4915. IL_OFFSET INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] N4917. V00(x19) N4919. CNS_INT 16 N4921. x13 = ADD ; x19 * N4923. V108(x13); x13 N4925. IL_OFFSET INL40 @ ??? <- INLRT @ 0x584[E-] N4927. V107(x10) N4929. V108(x13) N4931. STK = LEA(b+8) ; x13 N4933. x14 = IND ; STK N4935. BOUNDS_CHECK_Rng -> BB254; x10,x14 N4937. V108(x13*) N4939. x13 = IND ; x13* N4941. V107(x10) N4943. STK = CAST ; x10 N4945. CNS_INT 1 N4947. x14 = BFIZ ; STK N4949. x13 = ADD ; x13,x14 N4951. CNS_INT 0 N4953. V106(x11) N4955. STK = LEA(b+8) ; x11 N4957. x14 = IND ; STK N4959. BOUNDS_CHECK_Rng -> BB254; x14 N4961. V106(x11*) N4963. STK = LEA(b+12); x11* N4965. x11 = IND ; STK N4967. STOREIND ; x13,x11 N4969. IL_OFFSET INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] N4971. V107(x10*) N4973. CNS_INT 1 N4975. x11 = ADD ; x10* N4977. V00(x19) N4979. STK = LEA(b+8) ; x19 N4981. STOREIND ; STK,x11 Var=Reg end of BB177: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB179 [584..585), preds={BB176} succs={BB180} ===== Predecessor for variable locations: BB176 Var=Reg beg of BB179: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V106=x11 V01=x21 V15=x26 V17=x23 $ N001. V20(x9) $ N001. V14(x3) $ N001. V36(x0) $ N001. V144(x8) N4985. IL_OFFSET INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] N4987. V00(x19) N4989. x0 = PUTARG_REG; x19 N4991. V106(x11*) N4993. x1 = PUTARG_REG; x11* N4995. x11 = CNS_INT(h) 0x4000000000431d58 ftn N4997. x11 = PUTARG_REG; x11 N4999. CALL r2r_ind; x0,x1,x11 * N001. V36(x0)R * N001. V14(x3)R * N001. V144(x8)R * N001. V20(x9)R Var=Reg end of BB179: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} ===== Predecessor for variable locations: BB174 Var=Reg beg of BB180: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 N5003. IL_OFFSET INLRT @ 0x590[E-] N5005. x10 = CNS_INT 1 * N5007. V21(x11); x10 $ N001. V21(x11) Var=Reg end of BB180: V00=x19 V179=x25 V04=x27 V20=x9 V34=x24 V05=x28 V14=x3 V36=x0 V06=x22 V144=x8 V03=x20 V01=x21 V15=x26 V17=x23 BB110 [000..000) (throw), preds={BB91} succs={} ===== Predecessor for variable locations: BB91 Var=Reg beg of BB110: none N5011. IL_OFFSET INL17 @ 0x029[E-] <- INLRT @ ??? N5013. x11 = CNS_INT(h) 0x4000000000424a20 ftn N5015. x11 = PUTARG_REG; x11 N5017. CALL r2r_ind; x11 Var=Reg end of BB110: none BB254 [???..???) (throw), preds={} succs={} ===== Predecessor for variable locations: BB00 Var=Reg beg of BB254: none N5021. x0 = CNS_INT(h) 0x4000000000421828 ftn N5023. x0 = IND ; x0 N5025. CALL help; x0 Var=Reg end of BB254: none *************** Finishing PHASE Linear scan register alloc Trees after Linear scan register alloc ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..061)-> BB10 ( cond ) i bwd LIR BB255 [0364] 1 BB09 8 [061..083)-> BB31,BB17,BB259,BB30,BB259,BB31 (switch) i bwd LIR BB259 [0368] 2 BB255(2) 4 [???..???)-> BB47 (always) internal bwd LIR BB10 [0009] 1 BB09 8 1 [083..083)-> BB11 ( cond ) i bwd LIR BB256 [0365] 1 BB10 8 [083..0A1)-> BB23,BB260,BB21,BB260,BB18 (switch) i bwd LIR BB260 [0369] 2 BB256(2) 4 [???..???)-> BB47 (always) internal bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB255 8 1 [0CF..0D8)-> BB47 (always) i bwd LIR BB18 [0017] 1 BB256 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd LIR BB21 [0020] 1 BB256 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB256 8 1 [0FB..102)-> BB47 ( cond ) i bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd LIR BB30 [0029] 1 BB255 8 1 [12C..137)-> BB47 (always) i bwd LIR BB31 [0031] 3 BB32,BB255(2) 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd LIR BB261 [0370] 1 BB43 4 [???..???) internal bwd LIR BB44 [0044] 3 BB39,BB45,BB261 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd LIR BB47 [0047] 22 BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB259,BB260 64 1 [204..20F)-> BB50 ( cond ) i bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB262 ( cond ) i idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB262 [0371] 1 BB78 0.50 [???..???)-> BB103 (always) internal LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd LIR BB103 [0096] 4 BB85,BB89,BB102,BB262 1 [3C8..3D0)-> BB112 ( cond ) i LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i LIR BB245 [0190] 25 BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB266,BB268 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB263 ( cond ) i Loop Loop0 bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB264 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB264 [0373] 1 BB115 1 [???..???)-> BB135 (always) internal bwd LIR BB263 [0372] 1 BB113 1 [???..???)-> BB136 (always) internal bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB265 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB265 [0374] 1 BB125 4 [???..???)-> BB134 (always) internal bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd LIR BB134 [0114] 3 BB124,BB133,BB265 8 3 [461..46D) i bwd LIR BB135 [0115] 3 BB114,BB134,BB264 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src LIR BB136 [0116] 3 BB117,BB135,BB263 2 3 [472..478)-> BB141 ( cond ) i bwd LIR BB137 [0117] 1 BB136 2 3 [478..478)-> BB138 ( cond ) i bwd LIR BB257 [0366] 1 BB137 2 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194 (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..49A)-> BB139 ( cond ) i bwd LIR BB258 [0367] 1 BB138 2 [49A..4B8)-> BB266,BB242,BB171,BB242,BB145 (switch) i bwd LIR BB266 [0375] 1 BB258 1 [???..???)-> BB245 (always) internal bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB257,BB258 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB267 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB267 [0376] 1 BB161 1 [???..???)-> BB170 (always) internal bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd LIR BB170 [0142] 4 BB156,BB160,BB169,BB267 2 3 [559..564)-> BB245 (always) i bwd LIR BB171 [0143] 1 BB258 2 3 [564..571)-> BB245 ( cond ) i bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd LIR BB186 [0149] 1 BB257 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd LIR BB194 [0151] 4 BB192,BB193,BB257(2) 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB268 ( cond ) i bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB268 [0377] 1 BB197 1 [???..???)-> BB245 (always) internal bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB269 ( cond ) i bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB269 [0378] 1 BB215 1 [???..???)-> BB244 (always) internal bwd LIR BB218 [0172] 2 BB207,BB271 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB271 ( cond ) i bwd bwd-src LIR BB270 [0379] 1 BB220 8 [???..???) internal bwd LIR BB221 [0175] 2 BB219,BB270 2 3 [701..707)-> BB223 ( cond ) i bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB271 [0380] 1 BB220 8 [???..???)-> BB218 (always) internal bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB140,BB143,BB257(2),BB258(2) 2 3 [7A2..7AA)-> BB272 ( cond ) i bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB272 [0381] 1 BB242 1 [???..???)-> BB244 (always) internal bwd LIR BB244 [0355] 2 BB269,BB272 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd LIR BB254 [0363] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} N003 (???,???) [003780] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t0 byref N007 (???,???) [004185] ----------- t4185 = * PUTARG_REG byref REG x0 N009 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn REG x11 $42 /--* t2543 long N011 (???,???) [004186] ----------- t4186 = * PUTARG_REG long REG x11 /--* t4185 byref this in x0 +--* t4186 long r2r cell in x11 N013 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void REG NA $VN.Void N015 (???,???) [003781] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N017 ( 1, 2) [000002] -c--------- t2 = CNS_INT int 0 REG NA $c0 /--* t2 int N019 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 x22 REG x22 N021 (???,???) [003782] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] REG NA N023 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 N025 ( 1, 2) [002547] -c--------- t2547 = CNS_INT long 16 REG NA $200 /--* t2546 byref +--* t2547 long N027 ( 3, 4) [002548] -----O----- t2548 = * ADD byref REG x0 $240 /--* t2548 byref N029 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 x0 REG x0 N031 (???,???) [003783] ----------- IL_OFFSET void INLRT @ 0x009[E-] REG NA N033 ( 1, 2) [001497] -c--------- t1497 = CNS_INT int 0 REG NA $c0 N035 ( 1, 1) [001502] ----------- t1502 = LCL_VAR byref V76 tmp36 u:1 x0 REG x0 $240 /--* t1502 byref N037 ( 3, 4) [002556] -c--------- t2556 = * LEA(b+8) byref REG NA /--* t2556 byref N039 ( 4, 3) [001503] ---XG------ t1503 = * IND int REG x1 /--* t1497 int +--* t1503 int N041 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N043 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 x0 (last use) REG x0 $240 /--* t1501 byref N045 ( 3, 2) [001505] n---GO----- t1505 = * IND byref REG x23 /--* t1505 byref N047 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 x23 REG x23 N049 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 x23 (last use) REG x23 /--* t2552 long N051 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 x23 REG x23 N053 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] x24 REG x24 $246 /--* t2558 byref N055 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 x24 REG x24 N057 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 x24 REG x24 $246 /--* t3710 byref N059 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 x0 REG x0 N061 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] x25 REG x25 $342 /--* t2561 int N063 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 x25 REG x25 N065 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t3690 int N067 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 x1 REG x1 N069 (???,???) [003784] ----------- IL_OFFSET void INLRT @ 0x011[E-] REG NA N071 ( 1, 1) [000011] ----------- t11 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t11 long N073 ( 4, 3) [000012] ---XG------ t12 = * IND ubyte REG x2 N075 ( 1, 2) [000013] -c--------- t13 = CNS_INT int 0 REG NA $c0 /--* t12 ubyte +--* t13 int N077 ( 6, 6) [000014] CEQ---XG--N--- * JCMP void REG NA ------------ BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N081 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 x0 (last use) REG x0 $246 /--* t2565 byref N083 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 x0 REG x0 N085 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 x1 (last use) REG x1 $342 /--* t2568 int N087 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 x1 REG x1 N089 ( 1, 1) [001472] ----------- t1472 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1472 byref N091 ( 3, 4) [002572] -c--------- t2572 = * LEA(b+8) byref REG NA /--* t2572 byref N093 ( 5, 4) [001473] n---GO----- t1473 = * IND bool REG x2 N095 ( 1, 2) [001474] -c--------- t1474 = CNS_INT int 0 REG NA $c0 /--* t1473 bool +--* t1474 int N097 ( 7, 7) [001475] CNE----GO-N--- * JCMP void REG NA ------------ BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} N101 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 x0 (last use) REG x0 $246 /--* t2574 byref N103 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 x0 REG x0 N105 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 x1 (last use) REG x1 $342 /--* t2577 int N107 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 x1 REG x1 N109 ( 1, 2) [001489] -c--------- t1489 = CNS_INT int 0 REG NA $c0 /--* t1489 int N111 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 x2 REG x2 ------------ BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} N115 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 x0 (last use) REG x0 $246 /--* t2581 byref N117 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 x0 REG x0 N119 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 x1 (last use) REG x1 $342 /--* t2584 int N121 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 x1 REG x1 N123 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 REG x2 $c1 /--* t1482 int N125 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 x2 REG x2 ------------ BB05 [025..026), preds={BB01} succs={BB06} N129 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 x0 (last use) REG x0 $246 /--* t2588 byref N131 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 x0 REG x0 N133 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 x1 (last use) REG x1 $342 /--* t2591 int N135 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 x1 REG x1 N137 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 REG x2 $c2 /--* t21 int N139 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 x2 REG x2 ------------ BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} N143 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 x0 (last use) REG x0 $246 /--* t2596 byref N145 (???,???) [004187] ----------- t4187 = * PUTARG_REG byref REG x0 N147 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 x1 (last use) REG x1 $342 /--* t2597 int N149 (???,???) [004188] ----------- t4188 = * PUTARG_REG int REG x1 /--* t4187 byref +--* t4188 int N151 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct REG NA $141 N153 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 x2 (last use) REG x2 $281 /--* t29 int N155 (???,???) [004189] ----------- t4189 = * PUTARG_REG int REG x2 N157 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn REG x11 $43 /--* t2594 long N159 (???,???) [004190] ----------- t4190 = * PUTARG_REG long REG x11 /--* t2595 struct arg1 x0,x1 +--* t4189 int arg2 in x2 +--* t4190 long r2r cell in x11 N161 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int REG x0 $2c1 /--* t30 int N163 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 x26 REG x26 ------------ BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} N167 (???,???) [003785] ----------- IL_OFFSET void INLRT @ 0x02D[E-] REG NA N169 ( 1, 2) [000035] -c--------- t35 = CNS_INT int 0 REG NA $c0 /--* t35 int N171 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 x27 REG x27 N173 (???,???) [003786] ----------- IL_OFFSET void INLRT @ 0x02F[E-] REG NA N175 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 REG x28 $c4 /--* t38 int N177 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 x28 REG x28 N179 (???,???) [003787] ----------- IL_OFFSET void INLRT @ 0x031[E-] REG NA N181 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF REG x3 $c9 /--* t41 int N183 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 NA REG NA N185 (???,???) [003788] ----------- IL_OFFSET void INLRT @ 0x037[E-] REG NA N187 ( 1, 2) [000044] -c--------- t44 = CNS_INT int 0 REG NA $c0 /--* t44 int N189 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 NA REG NA N191 (???,???) [003789] ----------- IL_OFFSET void INLRT @ 0x039[E-] REG NA N193 ( 1, 2) [002598] -c--------- t2598 = CNS_INT int 0 REG NA $c0 /--* t2598 int N195 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 x5 REG x5 N197 (???,???) [003790] ----------- IL_OFFSET void INLRT @ 0x03C[E-] REG NA N199 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 REG x6 $c4 /--* t50 int N201 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 x6 REG x6 N203 (???,???) [003791] ----------- IL_OFFSET void INLRT @ 0x03F[E-] REG NA N205 ( 1, 2) [002599] -c--------- t2599 = CNS_INT int 0 REG NA $c0 /--* t2599 int N207 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 x7 REG x7 N209 (???,???) [003792] ----------- IL_OFFSET void INLRT @ 0x042[E-] REG NA N211 ( 1, 2) [000056] -c--------- t56 = CNS_INT int 0 REG NA $c0 /--* t56 int N213 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 x8 REG x8 N215 (???,???) [003793] ----------- IL_OFFSET void INLRT @ 0x045[E-] REG NA N217 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 x26 REG x26 $283 /--* t59 int N219 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 x1 REG x1 N221 (???,???) [003794] ----------- IL_OFFSET void INLRT @ 0x049[E-] REG NA N223 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 x24 REG x24 $246 /--* t3712 byref N225 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 x9 REG x9 N227 (???,???) [003795] ----------- IL_OFFSET void INLRT @ 0x049[E-] REG NA N229 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 x9 REG x9 $246 /--* t1512 byref N231 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 NA REG NA N233 (???,???) [003796] ----------- IL_OFFSET void INLRT @ 0x051[E-] REG NA N235 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 x9 (last use) REG x9 $246 /--* t69 byref N237 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 x9 REG x9 N239 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 x9 (last use) REG x9 $3c4 /--* t2609 long N241 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 x9 REG x9 ------------ BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} N313 (???,???) [003797] ----------- IL_OFFSET void INLRT @ 0x05B[E-] REG NA N315 ( 1, 1) [001226] ----------- t1226 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N317 ( 1, 2) [001227] -c--------- t1227 = CNS_INT int 69 REG NA $d2 /--* t1226 int +--* t1227 int N319 ( 3, 4) [001228] N------N-U- * GT void REG NA N321 ( 5, 6) [001229] ----------- * JTRUE void REG NA $VN.Void ------------ BB09 [061..061) -> BB10 (cond), preds={BB08} succs={BB255,BB10} N325 (???,???) [003798] ----------- IL_OFFSET void INLRT @ 0x061[E-] REG NA N327 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N329 ( 1, 2) [001362] -c--------- t1362 = CNS_INT int -34 REG NA $d6 /--* t1361 int +--* t1362 int N331 ( 3, 4) [001363] ----------- t1363 = * ADD int REG x14 /--* t1363 int N333 (???,???) [004192] DA--------- * STORE_LCL_VAR int V182 rat0 x14 REG x14 N335 ( 3, 2) [004194] ----------- t4194 = LCL_VAR int V182 rat0 x14 REG x14 N337 ( 1, 2) [004195] -c--------- t4195 = CNS_INT int 5 REG NA /--* t4194 int +--* t4195 int N339 ( 8, 5) [004196] ---------U- * GT void REG NA N341 ( 10, 7) [004197] ----------- * JTRUE void REG NA ------------ BB255 [061..083) -> BB31,BB17,BB259,BB30,BB259,BB31 (switch), preds={BB09} succs={BB17,BB30,BB31,BB259} N3689 (???,???) [004198] ----------- t4198 = LCL_VAR int V182 rat0 x14 (last use) REG x14 /--* t4198 int N3691 (???,???) [004199] ---------U- t4199 = * CAST long <- ulong <- uint REG x0 N3693 (???,???) [004200] ----------- t4200 = JMPTABLE long REG x1 /--* t4199 long +--* t4200 long N3695 (???,???) [004201] ----------- * SWITCH_TABLE void REG NA ------------ BB259 [???..???) -> BB47 (always), preds={BB255(2)} succs={BB47} N001 ( 1, 1) [004305] ----------- t4305 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4305 int N002 ( 2, 2) [004306] ----------- t4306 = * COPY int REG x1 ------------ BB10 [083..083) -> BB11 (cond), preds={BB09} succs={BB256,BB11} N345 (???,???) [003799] ----------- IL_OFFSET void INLRT @ 0x083[E-] REG NA N347 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N349 ( 1, 2) [001366] -c--------- t1366 = CNS_INT int -44 REG NA $d7 /--* t1365 int +--* t1366 int N351 ( 3, 4) [001367] ----------- t1367 = * ADD int REG x12 /--* t1367 int N353 (???,???) [004203] DA--------- * STORE_LCL_VAR int V183 rat1 x12 REG x12 N355 ( 3, 2) [004205] ----------- t4205 = LCL_VAR int V183 rat1 x12 REG x12 N357 ( 1, 2) [004206] -c--------- t4206 = CNS_INT int 4 REG NA /--* t4205 int +--* t4206 int N359 ( 8, 5) [004207] ---------U- * GT void REG NA N361 ( 10, 7) [004208] ----------- * JTRUE void REG NA ------------ BB256 [083..0A1) -> BB23,BB260,BB21,BB260,BB18 (switch), preds={BB10} succs={BB18,BB21,BB23,BB260} N3789 (???,???) [004209] ----------- t4209 = LCL_VAR int V183 rat1 x12 (last use) REG x12 /--* t4209 int N3791 (???,???) [004210] ---------U- t4210 = * CAST long <- ulong <- uint REG x13 N3793 (???,???) [004211] ----------- t4211 = JMPTABLE long REG x0 /--* t4210 long +--* t4211 long N3795 (???,???) [004212] ----------- * SWITCH_TABLE void REG NA ------------ BB260 [???..???) -> BB47 (always), preds={BB256(2)} succs={BB47} N001 ( 1, 1) [004307] ----------- t4307 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4307 int N002 ( 2, 2) [004308] ----------- t4308 = * COPY int REG x1 ------------ BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} N365 (???,???) [003800] ----------- IL_OFFSET void INLRT @ 0x0A1[E-] REG NA N367 ( 1, 1) [001369] ----------- t1369 = LCL_VAR int V18 loc14 u:5 x13 (last use) REG x13 N369 ( 1, 2) [001370] -c--------- t1370 = CNS_INT int 69 REG NA $d2 /--* t1369 int +--* t1370 int N371 ( 3, 4) [001371] J------N--- * EQ void REG NA N373 ( 5, 6) [001372] ----------- * JTRUE void REG NA $VN.Void ------------ BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} N001 ( 1, 1) [004365] ----------- t4365 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4365 int N002 ( 2, 2) [004366] ----------- t4366 = * COPY int REG x1 ------------ BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} N379 (???,???) [003801] ----------- IL_OFFSET void INLRT @ 0x0AF[E-] REG NA N381 ( 1, 1) [001230] ----------- t1230 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N383 ( 1, 2) [001231] -c--------- t1231 = CNS_INT int 92 REG NA $d3 /--* t1230 int +--* t1231 int N385 ( 3, 4) [001232] J------N--- * EQ void REG NA N387 ( 5, 6) [001233] ----------- * JTRUE void REG NA $VN.Void ------------ BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} N391 (???,???) [003802] ----------- IL_OFFSET void INLRT @ 0x0B8[E-] REG NA N393 ( 1, 1) [001257] ----------- t1257 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N395 ( 1, 2) [001258] -c--------- t1258 = CNS_INT int 101 REG NA $d4 /--* t1257 int +--* t1258 int N397 ( 3, 4) [001259] J------N--- * EQ void REG NA N399 ( 5, 6) [001260] ----------- * JTRUE void REG NA $VN.Void ------------ BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} N403 (???,???) [003803] ----------- IL_OFFSET void INLRT @ 0x0C1[E-] REG NA N405 ( 1, 1) [001352] ----------- t1352 = LCL_VAR int V18 loc14 u:5 x13 (last use) REG x13 N407 ( 1, 4) [001353] ----------- t1353 = CNS_INT int 0x2030 REG x1 $d5 /--* t1352 int +--* t1353 int N409 ( 3, 6) [001354] J------N--- * NE void REG NA N001 ( 1, 1) [004309] ----------- t4309 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4309 int N002 ( 2, 2) [004310] ----------- t4310 = * COPY int REG x1 N411 ( 5, 8) [001355] ----------- * JTRUE void REG NA $VN.Void ------------ BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} N415 (???,???) [003804] ----------- IL_OFFSET void INLRT @ 0x137[E-] REG NA N417 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 x8 (last use) REG x8 $289 N419 ( 1, 2) [001357] -c--------- t1357 = CNS_INT int 3 REG NA $c3 /--* t1356 int +--* t1357 int N421 ( 3, 4) [001358] ----------- t1358 = * ADD int REG x8 $376 /--* t1358 int N423 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 x8 REG x8 ------------ BB17 [0CF..0D8) -> BB47 (always), preds={BB255} succs={BB47} N3699 (???,???) [003805] ----------- IL_OFFSET void INLRT @ 0x0CF[E-] REG NA N3701 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 x27 (last use) REG x27 $28a N3703 ( 1, 2) [001431] -c--------- t1431 = CNS_INT int 1 REG NA $c1 /--* t1430 int +--* t1431 int N3705 ( 3, 4) [001432] ----------- t1432 = * ADD int REG x27 $68f /--* t1432 int N3707 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 x27 REG x27 N001 ( 1, 1) [004367] ----------- t4367 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4367 int N002 ( 2, 2) [004368] ----------- t4368 = * COPY int REG x1 ------------ BB18 [0D8..0E0) -> BB20 (cond), preds={BB256} succs={BB19,BB20} N3799 (???,???) [003806] ----------- IL_OFFSET void INLRT @ 0x0D8[E-] REG NA N3801 ( 1, 1) [001373] ----------z t1373 = LCL_VAR int V06 loc2 u:2 x3 REG x3 $284 N3803 ( 1, 4) [001374] ----------- t1374 = CNS_INT int 0x7FFFFFFF REG x4 $c9 /--* t1373 int +--* t1374 int N3805 ( 3, 6) [001375] N------N-U- * NE void REG NA $68e N3807 ( 5, 8) [001376] ----------- * JTRUE void REG NA $VN.Void ------------ BB19 [0E0..0E2), preds={BB18} succs={BB20} N3811 (???,???) [003807] ----------- IL_OFFSET void INLRT @ 0x0E0[E-] REG NA N3813 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1385 int N3815 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 x3 REG x3 ------------ BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} N3819 (???,???) [003808] ----------- IL_OFFSET void INLRT @ 0x0E2[E-] REG NA N3821 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 x27 (last use) REG x27 $28a N3823 ( 1, 2) [001378] -c--------- t1378 = CNS_INT int 1 REG NA $c1 /--* t1377 int +--* t1378 int N3825 ( 3, 4) [001379] ----------- t1379 = * ADD int REG x27 $68f /--* t1379 int N3827 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 x27 REG x27 N3829 (???,???) [003809] ----------- IL_OFFSET void INLRT @ 0x0E6[E-] REG NA N3831 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 x27 REG x27 $68f /--* t1382 int N3833 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 x2 REG x2 N001 ( 1, 1) [004369] ----------Z t4369 = LCL_VAR int V06 loc2 x3 REG x3 N001 ( 1, 1) [004370] ----------Z t4370 = LCL_VAR int V07 loc3 x2 REG x2 N001 ( 1, 1) [004371] ----------- t4371 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4371 int N002 ( 2, 2) [004372] ----------- t4372 = * COPY int REG x1 ------------ BB21 [0ED..0F4) -> BB47 (cond), preds={BB256} succs={BB22,BB47} N3837 (???,???) [003810] ----------- IL_OFFSET void INLRT @ 0x0ED[E-] REG NA N3839 ( 1, 1) [001388] ----------- t1388 = LCL_VAR int V05 loc1 u:2 x28 REG x28 $286 N3841 ( 1, 2) [001389] -c--------- t1389 = CNS_INT int 0 REG NA $c0 /--* t1388 int +--* t1389 int N3843 ( 3, 4) [001390] J------N--- * GE void REG NA $690 N001 ( 1, 1) [004311] ----------- t4311 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4311 int N002 ( 2, 2) [004312] ----------- t4312 = * COPY int REG x1 N3845 ( 5, 6) [001391] ----------- * JTRUE void REG NA $VN.Void ------------ BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} N3849 (???,???) [003811] ----------- IL_OFFSET void INLRT @ 0x0F4[E-] REG NA N3851 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1392 int N3853 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 x28 REG x28 ------------ BB23 [0FB..102) -> BB47 (cond), preds={BB256} succs={BB24,BB47} N3857 (???,???) [003812] ----------- IL_OFFSET void INLRT @ 0x0FB[E-] REG NA N3859 ( 1, 1) [001395] ----------- t1395 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a N3861 ( 1, 2) [001396] -c--------- t1396 = CNS_INT int 0 REG NA $c0 /--* t1395 int +--* t1396 int N3863 ( 6, 4) [001397] -c-----N--- t1397 = * LE int REG NA $691 N3865 ( 1, 1) [001399] ----------- t1399 = LCL_VAR int V05 loc1 u:2 x28 REG x28 $286 N3867 ( 1, 2) [001400] -c--------- t1400 = CNS_INT int 0 REG NA $c0 /--* t1399 int +--* t1400 int N3869 ( 6, 4) [001401] -c-----N--- t1401 = * GE int REG NA $690 /--* t1397 int +--* t1401 int N3871 ( 13, 9) [003726] Jc-----N--- * AND void REG NA N001 ( 1, 1) [004313] ----------- t4313 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4313 int N002 ( 2, 2) [004314] ----------- t4314 = * COPY int REG x1 N3873 ( 15, 11) [001398] ----------- * JTRUE void REG NA $VN.Void ------------ BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} N3877 (???,???) [003813] ----------- IL_OFFSET void INLRT @ 0x102[E-] REG NA N3879 (???,???) [003814] ----------- IL_OFFSET void INLRT @ 0x109[E-] REG NA N3881 ( 1, 1) [001403] ----------- t1403 = LCL_VAR int V10 loc6 u:2 x6 REG x6 $287 N3883 ( 1, 2) [001404] -c--------- t1404 = CNS_INT int 0 REG NA $c0 /--* t1403 int +--* t1404 int N3885 ( 3, 4) [001405] J------N--- * LT void REG NA $692 N3887 ( 5, 6) [001406] ----------- * JTRUE void REG NA $VN.Void ------------ BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} N3891 (???,???) [003815] ----------- IL_OFFSET void INLRT @ 0x10E[E-] REG NA N3893 ( 1, 1) [001413] ----------- t1413 = LCL_VAR int V10 loc6 u:2 x6 REG x6 $287 N3895 ( 1, 1) [001414] ----------- t1414 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1413 int +--* t1414 int N3897 ( 3, 3) [001415] N------N-U- * NE void REG NA $693 N3899 ( 5, 5) [001416] ----------- * JTRUE void REG NA $VN.Void ------------ BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} N3903 (???,???) [003816] ----------- IL_OFFSET void INLRT @ 0x113[E-] REG NA N3905 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 x22 (last use) REG x22 $288 N3907 ( 1, 2) [001421] -c--------- t1421 = CNS_INT int 1 REG NA $c1 /--* t1420 int +--* t1421 int N3909 ( 3, 4) [001422] ----------- t1422 = * ADD int REG x22 $694 /--* t1422 int N3911 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 x22 REG x22 ------------ BB28 [11E..121), preds={BB26} succs={BB29} N3915 (???,???) [003817] ----------- IL_OFFSET void INLRT @ 0x11E[E-] REG NA N3917 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 REG x7 $c1 /--* t2612 int N3919 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 NA REG NA N001 ( 1, 1) [004373] ----------z t4373 = LCL_VAR bool V12 loc8 x7 REG x7 ------------ BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} N3923 (???,???) [003818] ----------- IL_OFFSET void INLRT @ 0x121[E-] REG NA N3925 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1407 int N3927 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 x6 REG x6 N3929 (???,???) [003819] ----------- IL_OFFSET void INLRT @ 0x124[E-] REG NA N3931 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 REG x22 $c1 /--* t1410 int N3933 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 x22 REG x22 ------------ BB30 [12C..137) -> BB47 (always), preds={BB255} succs={BB47} N3711 (???,???) [003820] ----------- IL_OFFSET void INLRT @ 0x12C[E-] REG NA N3713 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 x8 (last use) REG x8 $289 N3715 ( 1, 2) [001426] -c--------- t1426 = CNS_INT int 2 REG NA $c2 /--* t1425 int +--* t1426 int N3717 ( 3, 4) [001427] ----------- t1427 = * ADD int REG x8 $695 /--* t1427 int N3719 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 x8 REG x8 N001 ( 1, 1) [004374] ----------- t4374 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4374 int N002 ( 2, 2) [004375] ----------- t4375 = * COPY int REG x1 ------------ BB31 [142..150) -> BB47 (cond), preds={BB32,BB255(2)} succs={BB32,BB47} N3723 (???,???) [003821] ----------- IL_OFFSET void INLRT @ 0x142[E-] REG NA N3725 ( 1, 1) [001435] ----------- t1435 = LCL_VAR int V16 loc12 u:21 x10 REG x10 $2b1 N3727 ( 1, 1) [003693] ----------- t3693 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1435 int +--* t3693 int N3729 ( 6, 3) [001440] -c-----N--- t1440 = * GE int REG NA $8b7 N3731 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N3733 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 x10 REG x10 $2b1 /--* t1443 int N3735 ( 2, 3) [001444] -c--------- t1444 = * CAST long <- int REG NA $3de N3737 ( 1, 2) [001446] -c--------- t1446 = CNS_INT long 1 REG NA $204 /--* t1444 long +--* t1446 long N3739 ( 4, 6) [001447] -c--------- t1447 = * BFIZ long REG NA /--* t1442 long +--* t1447 long N3741 ( 6, 8) [001448] -c--------- t1448 = * LEA(b+(i*1)+0) long REG NA /--* t1448 long N3743 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort REG x0 /--* t1449 ushort N3745 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 x0 REG x0 N3747 ( 1, 1) [003626] ----------- t3626 = LCL_VAR int V171 cse0 u:1 x0 REG x0 N3749 ( 1, 2) [001450] -c--------- t1450 = CNS_INT int 0 REG NA $c0 /--* t3626 int +--* t1450 int N3751 ( 15, 14) [001451] -c-XG--N--- t1451 = * EQ int REG NA /--* t1440 int +--* t1451 int N3753 ( 22, 18) [003728] Jc-XG--N--- * AND void REG NA N001 ( 1, 1) [004315] ----------- t4315 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4315 int N002 ( 2, 2) [004316] ----------- t4316 = * COPY int REG x1 N3755 ( 24, 20) [001441] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} N3759 (???,???) [003822] ----------- IL_OFFSET void INLRT @ 0x150[E-] REG NA N3761 (???,???) [003823] ----------- IL_OFFSET void INLRT @ 0x15E[E-] REG NA N3763 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 x1 (last use) REG x1 $2b1 /--* t1454 int N3765 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 x1 REG x1 N3767 (???,???) [003824] ----------- IL_OFFSET void INLRT @ 0x15E[E-] REG NA N3769 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 x1 (last use) REG x1 $2b1 N3771 ( 1, 2) [001456] -c--------- t1456 = CNS_INT int 1 REG NA $c1 /--* t1455 int +--* t1456 int N3773 ( 3, 4) [001457] ----------- t1457 = * ADD int REG x1 $8bc /--* t1457 int N3775 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 NA REG NA N3777 ( 1, 1) [003628] ----------- t3628 = LCL_VAR int V171 cse0 u:1 x0 (last use) REG x0 N3779 ( 1, 1) [001469] ----------- t1469 = LCL_VAR int V18 loc14 u:5 x13 REG x13 /--* t3628 int +--* t1469 int N3781 ( 3, 3) [001470] N---G--N-U- * NE void REG NA N001 ( 1, 1) [004317] ----------z t4317 = LCL_VAR int V16 loc12 x10 REG x10 N3783 ( 5, 5) [001471] ----G------ * JTRUE void REG NA $876 ------------ BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} N001 ( 1, 1) [004376] ----------- t4376 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4376 int N002 ( 2, 2) [004377] ----------- t4377 = * COPY int REG x1 ------------ BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} N427 (???,???) [003825] ----------- IL_OFFSET void INLRT @ 0x175[E-] REG NA N429 ( 1, 1) [001234] ----------- t1234 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 N431 ( 1, 1) [003694] ----------- t3694 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1234 int +--* t3694 int N433 ( 6, 3) [001239] -c-----N--- t1239 = * GE int REG NA $36c N435 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N437 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 /--* t1242 int N439 ( 2, 3) [001243] -c--------- t1243 = * CAST long <- int REG NA $3c8 N441 ( 1, 2) [001245] -c--------- t1245 = CNS_INT long 1 REG NA $204 /--* t1243 long +--* t1245 long N443 ( 4, 6) [001246] -c--------- t1246 = * BFIZ long REG NA /--* t1241 long +--* t1246 long N445 ( 6, 8) [001247] -c--------- t1247 = * LEA(b+(i*1)+0) long REG NA /--* t1247 long N447 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort REG x1 /--* t1248 ushort N449 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 x1 REG x1 N451 ( 1, 1) [003646] ----------- t3646 = LCL_VAR int V174 cse3 x1 (last use) REG x1 N453 ( 1, 2) [001249] -c--------- t1249 = CNS_INT int 0 REG NA $c0 /--* t3646 int +--* t1249 int N455 ( 15, 14) [001250] -c-XG--N--- t1250 = * EQ int REG NA /--* t1239 int +--* t1250 int N457 ( 22, 18) [003730] Jc-XG--N--- * AND void REG NA N001 ( 1, 1) [004318] ----------- t4318 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4318 int N002 ( 2, 2) [004319] ----------- t4319 = * COPY int REG x1 N459 ( 24, 20) [001240] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB36 [183..196) -> BB47 (always), preds={BB35} succs={BB47} N463 (???,???) [003826] ----------- IL_OFFSET void INLRT @ 0x183[E-] REG NA N465 (???,???) [003827] ----------- IL_OFFSET void INLRT @ 0x18E[E-] REG NA N467 ( 1, 1) [001252] ----------- t1252 = LCL_VAR int V16 loc12 u:17 x1 (last use) REG x1 $361 N469 ( 1, 2) [001253] -c--------- t1253 = CNS_INT int 1 REG NA $c1 /--* t1252 int +--* t1253 int N471 ( 3, 4) [001254] ----------- t1254 = * ADD int REG x1 $371 /--* t1254 int N473 ( 3, 4) [001256] DA--------- * STORE_LCL_VAR int V16 loc12 d:20 x1 REG x1 ------------ BB38 [196..1A1) -> BB40 (cond), preds={BB11,BB14} succs={BB39,BB40} N477 (???,???) [003828] ----------- IL_OFFSET void INLRT @ 0x196[E-] REG NA N479 ( 1, 1) [001261] ----------- t1261 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 N481 ( 1, 1) [003695] ----------- t3695 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1261 int +--* t3695 int N483 ( 3, 3) [001266] J------N--- * GE void REG NA $36c N485 ( 5, 5) [001267] ----------- * JTRUE void REG NA $VN.Void ------------ BB39 [1A1..1AE) -> BB44 (cond), preds={BB38} succs={BB40,BB44} N489 (???,???) [003829] ----------- IL_OFFSET void INLRT @ 0x1A1[E-] REG NA N491 ( 1, 1) [001341] ----------- t1341 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N493 ( 1, 1) [001342] ----------- t1342 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 /--* t1342 int N495 ( 2, 3) [001343] -c--------- t1343 = * CAST long <- int REG NA $3c8 N497 ( 1, 2) [001345] -c--------- t1345 = CNS_INT long 1 REG NA $204 /--* t1343 long +--* t1345 long N499 ( 4, 6) [001346] -c--------- t1346 = * BFIZ long REG NA /--* t1341 long +--* t1346 long N501 ( 6, 8) [001347] -c--------- t1347 = * LEA(b+(i*1)+0) long REG NA /--* t1347 long N503 ( 9, 10) [001348] ---XG------ t1348 = * IND ushort REG x1 /--* t1348 ushort N505 ( 9, 10) [003649] DA-XG------ * STORE_LCL_VAR int V174 cse3 x1 REG x1 N507 ( 1, 1) [003650] ----------- t3650 = LCL_VAR int V174 cse3 x1 (last use) REG x1 N509 ( 1, 2) [001349] -c--------- t1349 = CNS_INT int 48 REG NA $d8 /--* t3650 int +--* t1349 int N511 ( 12, 14) [001350] J--XG--N--- * EQ void REG NA N513 ( 14, 16) [001351] ---XG------ * JTRUE void REG NA $311 ------------ BB40 [1AE..1BB) -> BB47 (cond), preds={BB38,BB39} succs={BB41,BB47} N517 (???,???) [003830] ----------- IL_OFFSET void INLRT @ 0x1AE[E-] REG NA N519 ( 1, 1) [001268] ----------- t1268 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 N521 ( 1, 2) [001269] -c--------- t1269 = CNS_INT int 1 REG NA $c1 /--* t1268 int +--* t1269 int N523 ( 3, 4) [001270] ----------- t1270 = * ADD int REG x1 $371 N525 ( 1, 1) [003696] ----------- t3696 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1270 int +--* t3696 int N527 ( 5, 6) [001275] J------N--- * GE void REG NA $681 N001 ( 1, 1) [004320] ----------- t4320 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4320 int N002 ( 2, 2) [004321] ----------- t4321 = * COPY int REG x1 N529 ( 7, 8) [001276] ----------- * JTRUE void REG NA $VN.Void ------------ BB41 [1BB..1C8) -> BB43 (cond), preds={BB40} succs={BB42,BB43} N533 (???,???) [003831] ----------- IL_OFFSET void INLRT @ 0x1BB[E-] REG NA N535 ( 1, 1) [001277] ----------- t1277 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N537 ( 1, 1) [001278] ----------- t1278 = LCL_VAR int V16 loc12 u:17 x1 REG x1 $361 /--* t1278 int N539 ( 2, 3) [001279] -c--------- t1279 = * CAST long <- int REG NA $3c8 N541 ( 1, 2) [001281] -c--------- t1281 = CNS_INT long 1 REG NA $204 /--* t1279 long +--* t1281 long N543 ( 4, 6) [001282] -c--------- t1282 = * BFIZ long REG NA /--* t1277 long +--* t1282 long N545 ( 6, 8) [001283] -c--------- t1283 = * LEA(b+(i*1)+0) long REG NA /--* t1283 long N547 ( 9, 10) [001284] ---XG------ t1284 = * IND ushort REG x0 /--* t1284 ushort N549 ( 9, 10) [003653] DA-XG------ * STORE_LCL_VAR int V174 cse3 x0 REG x0 N551 ( 1, 1) [003654] ----------- t3654 = LCL_VAR int V174 cse3 x0 REG x0 N553 ( 1, 2) [001285] -c--------- t1285 = CNS_INT int 43 REG NA $d9 /--* t3654 int +--* t1285 int N555 ( 12, 14) [001286] J--XG--N--- * EQ void REG NA N557 ( 14, 16) [001287] ---XG------ * JTRUE void REG NA $311 ------------ BB42 [1C8..1D5) -> BB47 (cond), preds={BB41} succs={BB43,BB47} N561 (???,???) [003832] ----------- IL_OFFSET void INLRT @ 0x1C8[E-] REG NA N563 ( 1, 1) [003656] ----------- t3656 = LCL_VAR int V174 cse3 x0 (last use) REG x0 N565 ( 1, 2) [001338] -c--------- t1338 = CNS_INT int 45 REG NA $da /--* t3656 int +--* t1338 int N567 ( 3, 4) [001339] N---G--N-U- * NE void REG NA N569 ( 5, 6) [001340] ----G------ * JTRUE void REG NA $311 ------------ BB43 [1D5..1E4) -> BB47 (cond), preds={BB41,BB42} succs={BB261,BB47} N573 (???,???) [003833] ----------- IL_OFFSET void INLRT @ 0x1D5[E-] REG NA N575 ( 1, 1) [001288] ----------- t1288 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N577 ( 1, 1) [001289] ----------- t1289 = LCL_VAR int V16 loc12 u:17 x1 REG x1 $361 N579 ( 1, 2) [001290] -c--------- t1290 = CNS_INT int 1 REG NA $c1 /--* t1289 int +--* t1290 int N581 ( 3, 4) [001291] ----------- t1291 = * ADD int REG x0 $371 /--* t1291 int N583 ( 4, 6) [001292] -c--------- t1292 = * CAST long <- int REG NA $3cb N585 ( 1, 2) [001294] -c--------- t1294 = CNS_INT long 1 REG NA $204 /--* t1292 long +--* t1294 long N587 ( 6, 9) [001295] -c--------- t1295 = * BFIZ long REG NA /--* t1288 long +--* t1295 long N589 ( 8, 11) [001296] -c--------- t1296 = * LEA(b+(i*1)+0) long REG NA /--* t1296 long N591 ( 11, 13) [001297] ---XG------ t1297 = * IND ushort REG x0 N593 ( 1, 2) [001298] -c--------- t1298 = CNS_INT int 48 REG NA $d8 /--* t1297 ushort +--* t1298 int N595 ( 13, 16) [001299] N--XG--N-U- * NE void REG NA N597 ( 15, 18) [001300] ---XG------ * JTRUE void REG NA $313 ------------ BB261 [???..???), preds={BB43} succs={BB44} N001 ( 1, 1) [004322] ----------- t4322 = LCL_VAR int V16 loc12 x1 REG x1 /--* t4322 int N002 ( 2, 2) [004323] ----------- t4323 = * COPY int REG x10 ------------ BB44 [1E4..1F4) -> BB46 (cond), preds={BB39,BB45,BB261} succs={BB45,BB46} N601 (???,???) [003834] ----------- IL_OFFSET void INLRT @ 0x1E4[E-] REG NA N603 ( 1, 1) [001301] ----------- t1301 = LCL_VAR int V16 loc12 u:18 x10 (last use) REG x10 $2b2 N605 ( 1, 2) [001302] -c--------- t1302 = CNS_INT int 1 REG NA $c1 /--* t1301 int +--* t1302 int N607 ( 3, 4) [001303] ----------- t1303 = * ADD int REG x10 $942 /--* t1303 int N609 ( 3, 4) [001305] DA--------- * STORE_LCL_VAR int V73 tmp33 d:1 x10 REG x10 N611 ( 1, 1) [001307] ----------- t1307 = LCL_VAR int V73 tmp33 u:1 x10 (last use) REG x10 $942 /--* t1307 int N613 ( 1, 3) [001309] DA--------- * STORE_LCL_VAR int V16 loc12 d:19 x10 REG x10 N615 ( 1, 1) [001306] ----------- t1306 = LCL_VAR int V16 loc12 u:19 x10 REG x10 $942 N617 ( 1, 1) [003697] ----------- t3697 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1306 int +--* t3697 int N619 ( 3, 3) [001314] J------N--- * GE void REG NA $943 N621 ( 5, 5) [001315] ----------- * JTRUE void REG NA $VN.Void ------------ BB45 [1F4..201) -> BB44 (cond), preds={BB44} succs={BB46,BB44} N625 (???,???) [003835] ----------- IL_OFFSET void INLRT @ 0x1F4[E-] REG NA N627 ( 1, 1) [001319] ----------- t1319 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N629 ( 1, 1) [001320] ----------- t1320 = LCL_VAR int V16 loc12 u:19 x10 REG x10 $942 /--* t1320 int N631 ( 2, 3) [001321] -c--------- t1321 = * CAST long <- int REG NA $3e1 N633 ( 1, 2) [001323] -c--------- t1323 = CNS_INT long 1 REG NA $204 /--* t1321 long +--* t1323 long N635 ( 4, 6) [001324] -c--------- t1324 = * BFIZ long REG NA /--* t1319 long +--* t1324 long N637 ( 6, 8) [001325] -c--------- t1325 = * LEA(b+(i*1)+0) long REG NA /--* t1325 long N639 ( 9, 10) [001326] ---XG------ t1326 = * IND ushort REG x5 N641 ( 1, 2) [001327] -c--------- t1327 = CNS_INT int 48 REG NA $d8 /--* t1326 ushort +--* t1327 int N643 ( 11, 13) [001328] J--XG--N--- * EQ void REG NA N645 ( 13, 15) [001329] ---XG------ * JTRUE void REG NA $878 ------------ BB46 [201..204), preds={BB44,BB45} succs={BB47} N649 (???,???) [003836] ----------- IL_OFFSET void INLRT @ 0x201[E-] REG NA N651 ( 1, 2) [002613] ----------- t2613 = CNS_INT int 1 REG x5 $c1 /--* t2613 int N653 ( 1, 3) [001318] DA--------- * STORE_LCL_VAR int V09 loc5 d:5 x5 REG x5 N001 ( 1, 1) [004378] ----------- t4378 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4378 int N002 ( 2, 2) [004379] ----------- t4379 = * COPY int REG x1 ------------ BB47 [204..20F) -> BB50 (cond), preds={BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB259,BB260} succs={BB48,BB50} N245 (???,???) [003837] ----------- IL_OFFSET void INLRT @ 0x204[E-] REG NA N247 ( 1, 1) [000073] ----------- t73 = LCL_VAR int V16 loc12 u:2 x1 REG x1 $28b N249 ( 1, 1) [003698] ----------- t3698 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t73 int +--* t3698 int N251 ( 3, 3) [000078] J------N--- * GE void REG NA $360 N253 ( 5, 5) [000079] ----------- * JTRUE void REG NA $VN.Void ------------ BB48 [20F..222) -> BB50 (cond), preds={BB47} succs={BB49,BB50} N257 (???,???) [003838] ----------- IL_OFFSET void INLRT @ 0x20F[E-] REG NA N259 ( 1, 1) [001198] ----------- t1198 = LCL_VAR int V16 loc12 u:2 x1 (last use) REG x1 $28b /--* t1198 int N261 ( 1, 3) [001205] DA--------- * STORE_LCL_VAR int V71 tmp31 d:1 x1 REG x1 N263 (???,???) [003839] ----------- IL_OFFSET void INLRT @ 0x20F[E-] REG NA N265 ( 1, 1) [001199] ----------- t1199 = LCL_VAR int V71 tmp31 u:1 x1 REG x1 $28b N267 ( 1, 2) [001200] -c--------- t1200 = CNS_INT int 1 REG NA $c1 /--* t1199 int +--* t1200 int N269 ( 3, 4) [001201] ----------- t1201 = * ADD int REG x0 $361 /--* t1201 int N271 ( 3, 4) [001203] DA--------- * STORE_LCL_VAR int V16 loc12 d:17 x10 REG x10 N273 ( 1, 1) [001197] ----------- t1197 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 N275 ( 1, 1) [001206] ----------- t1206 = LCL_VAR int V71 tmp31 u:1 x1 (last use) REG x1 $28b /--* t1206 int N277 ( 2, 3) [001207] -c--------- t1207 = * CAST long <- int REG NA $3c5 N279 ( 1, 2) [001209] -c--------- t1209 = CNS_INT long 1 REG NA $204 /--* t1207 long +--* t1209 long N281 ( 4, 6) [001210] -c--------- t1210 = * BFIZ long REG NA /--* t1197 long +--* t1210 long N283 ( 6, 8) [001211] -c--------- t1211 = * LEA(b+(i*1)+0) long REG NA /--* t1211 long N285 ( 9, 10) [001212] ---XG------ t1212 = * IND ushort REG x13 /--* t1212 ushort N287 ( 9, 10) [001214] DA-XG------ * STORE_LCL_VAR int V72 tmp32 d:1 x13 REG x13 N289 ( 1, 1) [001216] ----------- t1216 = LCL_VAR int V72 tmp32 u:1 x13 (last use) REG x13 /--* t1216 int N291 ( 1, 3) [001218] DA--------- * STORE_LCL_VAR int V18 loc14 d:5 x13 REG x13 N293 ( 1, 1) [001215] ----------- t1215 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N295 ( 1, 2) [001219] -c--------- t1219 = CNS_INT int 0 REG NA $c0 /--* t1215 int +--* t1219 int N297 ( 3, 4) [001220] CEQ-------N--- * JCMP void REG NA ------------ BB49 [222..22B) -> BB08 (cond), preds={BB48} succs={BB50,BB08} N301 (???,???) [003840] ----------- IL_OFFSET void INLRT @ 0x222[E-] REG NA N303 ( 1, 1) [001222] ----------- t1222 = LCL_VAR int V18 loc14 u:5 x13 REG x13 N305 ( 1, 2) [001223] -c--------- t1223 = CNS_INT int 59 REG NA $d1 /--* t1222 int +--* t1223 int N307 ( 3, 4) [001224] N------N-U- * NE void REG NA N309 ( 5, 6) [001225] ----------- * JTRUE void REG NA $VN.Void ------------ BB50 [22B..233) -> BB52 (cond), preds={BB47,BB48,BB49} succs={BB51,BB52} N657 (???,???) [003841] ----------- IL_OFFSET void INLRT @ 0x22B[E-] REG NA N659 ( 1, 2) [000081] -c--------- t81 = CNS_INT long 0 REG NA $205 /--* t81 long N661 ( 1, 3) [000083] DA--------- * STORE_LCL_VAR byref V23 loc19 NA REG NA N663 (???,???) [003842] ----------- IL_OFFSET void INLRT @ 0x22F[E-] REG NA N665 ( 1, 1) [000084] ----------- t84 = LCL_VAR int V05 loc1 u:2 x28 REG x28 $286 N667 ( 1, 2) [000085] -c--------- t85 = CNS_INT int 0 REG NA $c0 /--* t84 int +--* t85 int N669 ( 3, 4) [000086] J------N--- * GE void REG NA $690 N671 ( 5, 6) [000087] ----------- * JTRUE void REG NA $VN.Void ------------ BB51 [233..235), preds={BB50} succs={BB52} N675 (???,???) [003843] ----------- IL_OFFSET void INLRT @ 0x233[E-] REG NA N677 ( 1, 1) [001194] ----------- t1194 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1194 int N679 ( 1, 3) [001196] DA--------- * STORE_LCL_VAR int V05 loc1 d:4 x28 REG x28 ------------ BB52 [235..23A) -> BB56 (cond), preds={BB50,BB51} succs={BB53,BB56} N683 (???,???) [003844] ----------- IL_OFFSET void INLRT @ 0x235[E-] REG NA N685 ( 1, 1) [000088] ----------- t88 = LCL_VAR int V10 loc6 u:2 x6 REG x6 $287 N687 ( 1, 2) [000089] -c--------- t89 = CNS_INT int 0 REG NA $c0 /--* t88 int +--* t89 int N689 ( 3, 4) [000090] J------N--- * LT void REG NA $692 N691 ( 5, 6) [000091] ----------- * JTRUE void REG NA $VN.Void ------------ BB53 [23A..23F) -> BB55 (cond), preds={BB52} succs={BB54,BB55} N695 (???,???) [003845] ----------- IL_OFFSET void INLRT @ 0x23A[E-] REG NA N697 ( 1, 1) [001180] ----------- t1180 = LCL_VAR int V10 loc6 u:2 x6 (last use) REG x6 $287 N699 ( 1, 1) [001181] ----------- t1181 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t1180 int +--* t1181 int N701 ( 3, 3) [001182] N------N-U- * NE void REG NA $696 N703 ( 5, 5) [001183] ----------- * JTRUE void REG NA $VN.Void ------------ BB54 [23F..24A) -> BB56 (always), preds={BB53} succs={BB56} N707 (???,???) [003846] ----------- IL_OFFSET void INLRT @ 0x23F[E-] REG NA N709 ( 1, 1) [001187] ----------- t1187 = LCL_VAR int V13 loc9 u:2 x8 (last use) REG x8 $289 N711 ( 1, 1) [001188] ----------- t1188 = LCL_VAR int V11 loc7 u:3 x22 REG x22 $288 N713 ( 1, 2) [001189] ----------- t1189 = CNS_INT int 3 REG x1 $c3 /--* t1188 int +--* t1189 int N715 ( 6, 6) [001190] -c--------- t1190 = * MUL int REG NA $697 /--* t1187 int +--* t1190 int N717 ( 8, 8) [001191] ----------- t1191 = * SUB int REG x8 $698 /--* t1191 int N719 ( 8, 8) [001193] DA--------- * STORE_LCL_VAR int V13 loc9 d:4 x8 REG x8 ------------ BB55 [24A..24D), preds={BB53} succs={BB56} N723 (???,???) [003847] ----------- IL_OFFSET void INLRT @ 0x24A[E-] REG NA N725 ( 1, 2) [002615] ----------- t2615 = CNS_INT int 1 REG x7 $c1 /--* t2615 int N727 ( 1, 3) [001186] DA--------- * STORE_LCL_VAR int V12 loc8 d:4 NA REG NA N001 ( 1, 1) [004380] ----------z t4380 = LCL_VAR bool V12 loc8 x7 REG x7 ------------ BB56 [24D..252) -> BB63 (cond), preds={BB52,BB54,BB55} succs={BB57,BB63} N731 (???,???) [003848] ----------- IL_OFFSET void INLRT @ 0x24D[E-] REG NA N733 ( 1, 1) [000092] ----------- t92 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t92 long N735 ( 4, 3) [000093] ---XG------ t93 = * IND ubyte REG x1 N737 ( 1, 2) [000094] -c--------- t94 = CNS_INT int 0 REG NA $c0 /--* t93 ubyte +--* t94 int N739 ( 6, 6) [000095] CEQ---XG--N--- * JCMP void REG NA ------------ BB57 [252..262) -> BB59 (cond), preds={BB56} succs={BB58,BB59} N743 (???,???) [003849] ----------- IL_OFFSET void INLRT @ 0x252[E-] REG NA N745 ( 1, 1) [002618] ----------- t2618 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 N747 ( 1, 2) [002619] -c--------- t2619 = CNS_INT long 4 REG NA $207 /--* t2618 byref +--* t2619 long N749 ( 3, 4) [002620] -----O----- t2620 = * ADD byref REG x1 $24a /--* t2620 byref N751 ( 3, 4) [001129] DA--GO----- * STORE_LCL_VAR byref V69 tmp29 d:1 x1 REG x1 N753 ( 1, 1) [001131] ----------- t1131 = LCL_VAR byref V69 tmp29 u:1 x1 REG x1 $24a /--* t1131 byref N755 ( 3, 2) [001132] n---GO----- t1132 = * IND int REG x0 N757 ( 1, 1) [001133] ----------- t1133 = LCL_VAR int V13 loc9 u:3 x8 (last use) REG x8 $28e /--* t1132 int +--* t1133 int N759 ( 5, 4) [001134] ----GO----- t1134 = * ADD int REG x0 N761 ( 1, 1) [001130] ----------- t1130 = LCL_VAR byref V69 tmp29 u:1 x1 (last use) REG x1 $24a /--* t1130 byref +--* t1134 int N763 (???,???) [003850] -A--GO----- * STOREIND int REG NA N765 (???,???) [003851] ----------- IL_OFFSET void INLRT @ 0x25E[E-] REG NA N767 ( 1, 1) [001137] ----------Z t1137 = LCL_VAR int V09 loc5 u:2 x5 REG x5 $4c1 N769 ( 1, 2) [001138] -c--------- t1138 = CNS_INT int 0 REG NA $c0 /--* t1137 int +--* t1138 int N771 ( 3, 4) [001139] CNE-------N--- * JCMP void REG NA ------------ BB58 [262..26E) -> BB60 (always), preds={BB57} succs={BB60} N775 (???,???) [003852] ----------- IL_OFFSET void INLRT @ 0x262[E-] REG NA N777 ( 1, 1) [001171] ----------- t1171 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1171 byref N779 ( 3, 4) [002623] -c--------- t2623 = * LEA(b+4) byref REG NA /--* t2623 byref N781 ( 4, 3) [001172] n---GO----- t1172 = * IND int REG x1 N783 ( 1, 1) [001173] ----------- t1173 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1172 int +--* t1173 int N785 ( 6, 5) [001174] ----GO----- t1174 = * ADD int REG x1 N787 ( 1, 1) [001175] ----------- t1175 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t1174 int +--* t1175 int N789 ( 8, 7) [001176] ----GO----- t1176 = * SUB int REG x1 /--* t1176 int N791 ( 8, 7) [001178] DA--GO----- * STORE_LCL_VAR int V70 tmp30 d:3 x1 REG x1 N001 ( 1, 1) [004381] ----------Z t4381 = LCL_VAR bool V12 loc8 x7 REG x7 ------------ BB59 [26E..26F), preds={BB57} succs={BB60} N795 (???,???) [003853] ----------- IL_OFFSET void INLRT @ 0x26E[E-] REG NA N797 ( 1, 1) [001141] ----------- t1141 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1141 int N799 ( 1, 3) [001143] DA--------- * STORE_LCL_VAR int V70 tmp30 d:2 x1 REG x1 N001 ( 1, 1) [004382] ----------Z t4382 = LCL_VAR bool V12 loc8 x7 REG x7 ------------ BB60 [26F..27F) -> BB66 (cond), preds={BB58,BB59} succs={BB61,BB66} N803 (???,???) [003854] ----------- IL_OFFSET void INLRT @ 0x271[E-] REG NA N805 ( 1, 1) [001145] ----------- t1145 = LCL_VAR int V70 tmp30 u:1 x1 (last use) REG x1 $291 /--* t1145 int N807 (???,???) [004213] ----------- t4213 = * PUTARG_REG int REG x1 N809 ( 1, 1) [001148] ----------- t1148 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1148 byref N811 (???,???) [004214] ----------- t4214 = * PUTARG_REG byref REG x0 N813 ( 2, 8) [002624] H---------- t2624 = CNS_INT(h) long 0x400000000046acb8 ftn REG x11 $45 /--* t2624 long N815 (???,???) [004215] ----------- t4215 = * PUTARG_REG long REG x11 N817 ( 1, 2) [001150] ----------- t1150 = CNS_INT int 0 REG x2 $c0 /--* t1150 int N819 (???,???) [004216] ----------- t4216 = * PUTARG_REG int REG x2 /--* t4213 int arg2 in x1 +--* t4214 byref arg1 in x0 +--* t4215 long r2r cell in x11 +--* t4216 int arg3 in x2 N821 ( 19, 18) [001151] --CXG------ * CALL r2r_ind void REG NA $VN.Void N823 (???,???) [003855] ----------- IL_OFFSET void INLRT @ 0x27A[E-] REG NA N825 ( 1, 1) [001152] ----------- t1152 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t1152 long N827 ( 4, 3) [001153] ---XG------ t1153 = * IND ubyte REG x0 N829 ( 1, 2) [001154] -c--------- t1154 = CNS_INT int 0 REG NA $c0 /--* t1153 ubyte +--* t1154 int N831 ( 6, 6) [001155] CNE---XG--N--- * JCMP void REG NA ------------ BB61 [27F..28E) -> BB66 (cond), preds={BB60} succs={BB62,BB66} N835 (???,???) [003856] ----------- IL_OFFSET void INLRT @ 0x27F[E-] REG NA N837 ( 1, 1) [003713] ----------- t3713 = LCL_VAR byref V180 cse9 u:1 x24 REG x24 $246 /--* t3713 byref N839 (???,???) [004217] ----------- t4217 = * PUTARG_REG byref REG x0 N841 ( 3, 4) [002628] ----------- t2628 = LCL_FLD long V02 arg2 u:1[+8] x1 REG x1 $3ce /--* t2628 long N843 (???,???) [004218] ----------- t4218 = * PUTARG_REG long REG x1 /--* t4217 byref +--* t4218 long N845 ( 4, 5) [002626] -c--------- t2626 = * FIELD_LIST struct REG NA $142 N847 ( 2, 8) [002625] H---------- t2625 = CNS_INT(h) long 0x40000000005401e8 ftn REG x11 $43 /--* t2625 long N849 (???,???) [004219] ----------- t4219 = * PUTARG_REG long REG x11 N851 ( 1, 2) [001158] ----------- t1158 = CNS_INT int 2 REG x2 $c2 /--* t1158 int N853 (???,???) [004220] ----------- t4220 = * PUTARG_REG int REG x2 /--* t2626 struct arg1 x0,x1 +--* t4219 long r2r cell in x11 +--* t4220 int arg2 in x2 N855 ( 21, 20) [001159] --CXG------ t1159 = * CALL r2r_ind int REG x0 $2c4 /--* t1159 int N857 ( 21, 20) [001163] DA-XG------ * STORE_LCL_VAR int V16 loc12 d:16 x1 REG x1 N859 (???,???) [003857] ----------- IL_OFFSET void INLRT @ 0x288[E-] REG NA N861 ( 1, 1) [001164] ----------- t1164 = LCL_VAR int V16 loc12 u:16 x1 REG x1 $2c4 N863 ( 1, 1) [001165] ----------- t1165 = LCL_VAR int V15 loc11 u:2 x26 REG x26 $283 /--* t1164 int +--* t1165 int N865 ( 3, 3) [001166] J------N--- * EQ void REG NA $6b6 N867 ( 5, 5) [001167] ----------- * JTRUE void REG NA $VN.Void ------------ BB62 [28E..297) -> BB07 (always), preds={BB61} succs={BB07} N871 (???,???) [003858] ----------- IL_OFFSET void INLRT @ 0x28E[E-] REG NA N873 ( 1, 1) [001168] ----------- t1168 = LCL_VAR int V16 loc12 u:16 x1 (last use) REG x1 $2c4 /--* t1168 int N875 ( 1, 3) [001170] DA--------- * STORE_LCL_VAR int V15 loc11 d:3 x26 REG x26 ------------ BB63 [297..2A0) -> BB65 (cond), preds={BB56} succs={BB64,BB65} N879 (???,???) [003859] ----------- IL_OFFSET void INLRT @ 0x297[E-] REG NA N881 ( 1, 1) [000097] ----------- t97 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t97 byref N883 ( 3, 4) [002630] -c--------- t2630 = * LEA(b+10) byref REG NA /--* t2630 byref N885 ( 5, 4) [000098] n---GO----- t98 = * IND ubyte REG x1 N887 ( 1, 2) [000099] -c--------- t99 = CNS_INT int 3 REG NA $c3 /--* t98 ubyte +--* t99 int N889 ( 7, 7) [000100] J---GO-N--- * EQ void REG NA N891 ( 9, 9) [000101] ----GO----- * JTRUE void REG NA $301 ------------ BB64 [2A0..2A7), preds={BB63} succs={BB65} N895 (???,???) [003860] ----------- IL_OFFSET void INLRT @ 0x2A0[E-] REG NA N897 ( 1, 1) [001122] ----------- t1122 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1122 byref N899 ( 3, 4) [002632] -c--------- t2632 = * LEA(b+8) byref REG NA N901 ( 1, 2) [001123] -c--------- t1123 = CNS_INT int 0 REG NA $c0 /--* t2632 byref +--* t1123 int N903 (???,???) [003861] -A--GO----- * STOREIND bool REG NA ------------ BB65 [2A7..2AE), preds={BB63,BB64} succs={BB66} N907 (???,???) [003862] ----------- IL_OFFSET void INLRT @ 0x2A7[E-] REG NA N909 ( 1, 1) [000102] ----------- t102 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t102 byref N911 ( 3, 4) [002634] -c--------- t2634 = * LEA(b+4) byref REG NA N913 ( 1, 2) [000103] -c--------- t103 = CNS_INT int 0 REG NA $c0 /--* t2634 byref +--* t103 int N915 (???,???) [003863] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004383] ----------Z t4383 = LCL_VAR bool V12 loc8 x7 REG x7 N001 ( 1, 1) [004384] ----------Z t4384 = LCL_VAR bool V09 loc5 x5 REG x5 ------------ BB66 [2AE..2C8) -> BB74 (cond), preds={BB60,BB61,BB65} succs={BB73,BB74} N919 (???,???) [003864] ----------- IL_OFFSET void INLRT @ 0x2AE[E-] REG NA N921 (???,???) [003865] ----------- IL_OFFSET void INLRT @ 0x2B2[E-] REG NA N923 ( 1, 1) [000106] ----------- t106 = LCL_VAR int V06 loc2 u:2 x3 (last use) REG x3 $284 N925 ( 1, 1) [000107] ----------- t107 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t106 int +--* t107 int N927 ( 3, 3) [000108] Jc-----N--- t108 = * LT int REG NA $6b7 N929 ( 1, 1) [000110] ----------- t110 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d N931 ( 1, 1) [000111] ----------z t111 = LCL_VAR int V06 loc2 u:2 x3 REG x3 $284 /--* t110 int +--* t111 int N933 ( 3, 3) [000112] ----------- t112 = * SUB int REG x0 $6b8 N935 ( 1, 2) [001118] -c--------- t1118 = CNS_INT int 0 REG NA $c0 /--* t108 int +--* t112 int +--* t1118 int N937 ( 8, 9) [003777] ----------- t3777 = * SELECT int REG x3 /--* t3777 int N939 ( 12, 12) [001120] DA--------- * STORE_LCL_VAR int V44 tmp4 d:3 x3 REG x3 N941 (???,???) [003866] ----------- IL_OFFSET void INLRT @ 0x2B5[E-] REG NA N943 ( 3, 2) [000116] ----------- t116 = LCL_VAR int V44 tmp4 u:1 x3 (last use) REG x3 $292 /--* t116 int N945 ( 3, 3) [000118] DA--------- * STORE_LCL_VAR int V06 loc2 d:3 x22 REG x22 N947 (???,???) [003867] ----------- IL_OFFSET void INLRT @ 0x2B9[E-] REG NA N949 (???,???) [003868] ----------- IL_OFFSET void INLRT @ 0x2BD[E-] REG NA N951 ( 1, 1) [000119] ----------- t119 = LCL_VAR int V07 loc3 u:2 x4 (last use) REG x4 $285 N953 ( 1, 1) [000120] ----------- t120 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t119 int +--* t120 int N955 ( 3, 3) [000121] Jc-----N--- t121 = * GT int REG NA $6b9 N957 ( 1, 1) [000123] ----------- t123 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d N959 ( 1, 1) [000124] ----------z t124 = LCL_VAR int V07 loc3 u:2 x4 REG x4 $285 /--* t123 int +--* t124 int N961 ( 3, 3) [000125] ----------- t125 = * SUB int REG x0 $6ba N963 ( 1, 2) [001114] -c--------- t1114 = CNS_INT int 0 REG NA $c0 /--* t121 int +--* t125 int +--* t1114 int N965 ( 8, 9) [003774] ----------- t3774 = * SELECT int REG x4 /--* t3774 int N967 ( 12, 12) [001116] DA--------- * STORE_LCL_VAR int V45 tmp5 d:3 x4 REG x4 N969 (???,???) [003869] ----------- IL_OFFSET void INLRT @ 0x2C0[E-] REG NA N971 ( 3, 2) [000129] ----------- t129 = LCL_VAR int V45 tmp5 u:1 x4 (last use) REG x4 $293 /--* t129 int N973 ( 3, 3) [000131] DA--------- * STORE_LCL_VAR int V07 loc3 d:3 NA REG NA N975 (???,???) [003870] ----------- IL_OFFSET void INLRT @ 0x2C4[E-] REG NA N977 ( 1, 1) [000132] ----------z t132 = LCL_VAR int V09 loc5 u:2 x5 REG x5 $4c1 N979 ( 1, 2) [000133] -c--------- t133 = CNS_INT int 0 REG NA $c0 /--* t132 int +--* t133 int N981 ( 3, 4) [000134] CEQ-------N--- * JCMP void REG NA ------------ BB73 [2C8..2D0) -> BB78 (always), preds={BB66} succs={BB78} N985 (???,???) [003871] ----------- IL_OFFSET void INLRT @ 0x2C8[E-] REG NA N987 ( 1, 1) [001108] ----------- t1108 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t1108 int N989 ( 1, 3) [001110] DA--------- * STORE_LCL_VAR int V08 loc4 d:8 x2 REG x2 N991 (???,???) [003872] ----------- IL_OFFSET void INLRT @ 0x2CB[E-] REG NA N993 ( 1, 2) [001111] -c--------- t1111 = CNS_INT int 0 REG NA $c0 /--* t1111 int N995 ( 1, 3) [001113] DA--------- * STORE_LCL_VAR int V14 loc10 d:9 x3 REG x3 ------------ BB74 [2D0..2EE), preds={BB66} succs={BB78} N999 (???,???) [003873] ----------- IL_OFFSET void INLRT @ 0x2D0[E-] REG NA N1001 (???,???) [003874] ----------- IL_OFFSET void INLRT @ 0x2D9[E-] REG NA N1003 ( 1, 1) [000136] ----------- t136 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t136 byref N1005 ( 3, 4) [002636] -c--------- t2636 = * LEA(b+4) byref REG NA /--* t2636 byref N1007 ( 4, 3) [000137] n---GO----- t137 = * IND int REG x3 /--* t137 int N1009 ( 8, 6) [003683] DA--GO----- * STORE_LCL_VAR int V178 cse7 d:1 x3 REG x3 N1011 ( 3, 2) [003684] ----------- t3684 = LCL_VAR int V178 cse7 u:1 x3 REG x3 N1013 ( 1, 1) [000138] ----------- t138 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t3684 int +--* t138 int N1015 ( 13, 10) [000139] Jc--GO-N--- t139 = * GT int REG NA N1017 ( 3, 2) [003686] ----------- t3686 = LCL_VAR int V178 cse7 u:1 x3 REG x3 N1019 ( 1, 1) [001104] ----------- t1104 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t139 int +--* t3686 int +--* t1104 int N1021 ( 18, 14) [003771] ----GO----- t3771 = * SELECT int REG x2 /--* t3771 int N1023 ( 22, 17) [001106] DA--GO----- * STORE_LCL_VAR int V46 tmp6 d:3 x2 REG x2 N1025 (???,???) [003875] ----------- IL_OFFSET void INLRT @ 0x2DC[E-] REG NA N1027 ( 3, 2) [000146] ----------- t146 = LCL_VAR int V46 tmp6 u:1 x2 (last use) REG x2 $295 /--* t146 int N1029 ( 3, 3) [000148] DA--------- * STORE_LCL_VAR int V08 loc4 d:7 x2 REG x2 N1031 (???,???) [003876] ----------- IL_OFFSET void INLRT @ 0x2E4[E-] REG NA N1033 ( 3, 2) [003687] ----------- t3687 = LCL_VAR int V178 cse7 u:1 x3 (last use) REG x3 N1035 ( 1, 1) [000151] ----------- t151 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t3687 int +--* t151 int N1037 ( 5, 4) [000152] ----G------ t152 = * SUB int REG x3 /--* t152 int N1039 ( 5, 4) [000154] DA--G------ * STORE_LCL_VAR int V14 loc10 d:8 x3 REG x3 ------------ BB78 [000..30D) -> BB262 (cond), preds={BB73,BB74} succs={BB79,BB262} N1043 (???,???) [003877] ----------- IL_OFFSET void INLRT @ 0x2EE[E-] REG NA N1045 ( 1, 1) [000155] ----------- t155 = LCL_VAR int V15 loc11 u:2 x26 REG x26 $283 /--* t155 int N1047 ( 1, 3) [000157] DA--------- * STORE_LCL_VAR int V16 loc12 d:3 NA REG NA N1049 (???,???) [003878] ----------- IL_OFFSET void INLRT @ 0x2F2[E-] REG NA N1051 (???,???) [003879] ----------- IL_OFFSET void INL09 @ 0x01F[E-] <- INLRT @ ??? REG NA N1053 ( 3, 3) [001550] ----------- t1550 = LCL_VAR_ADDR long V47 tmp7 x6 REG x6 $740 /--* t1550 long N1055 ( 3, 3) [001553] DA--------- * STORE_LCL_VAR byref V151 tmp111 d:1 x6 REG x6 N1057 (???,???) [003880] ----------- IL_OFFSET void INL09 @ 0x026[E-] <- INLRT @ ??? REG NA N1059 (???,???) [003881] ----------- IL_OFFSET void INLRT @ 0x2FF[E-] REG NA N1061 ( 1, 1) [002649] ----------- t2649 = LCL_VAR byref V151 tmp111 u:1 x6 (last use) REG x6 $24b /--* t2649 byref N1063 ( 1, 3) [002650] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:1 NA REG NA N1065 ( 1, 2) [003720] ----------- t3720 = CNS_INT int 4 REG x8 $c8 /--* t3720 int N1067 ( 1, 3) [002653] DA--------- * STORE_LCL_VAR int V144 tmp104 d:1 x8 REG x8 N1069 (???,???) [003882] ----------- IL_OFFSET void INLRT @ 0x303[E-] REG NA N1071 ( 1, 2) [000175] ----------- t175 = CNS_INT int -1 REG x9 $c4 /--* t175 int N1073 ( 1, 3) [000177] DA--------- * STORE_LCL_VAR int V20 loc16 d:1 x9 REG x9 N1075 (???,???) [003883] ----------- IL_OFFSET void INLRT @ 0x306[E-] REG NA N1077 ( 1, 1) [000941] ----------- t941 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t941 ref N1079 ( 3, 4) [002656] -c--------- t2656 = * LEA(b+56) byref REG NA /--* t2656 byref N1081 ( 4, 3) [001570] ---XG------ t1570 = * IND ref REG x0 /--* t1570 ref N1083 (???,???) [004156] -c--------- t4156 = * LEA(b+8) byref REG NA /--* t4156 byref N1085 ( 6, 5) [000944] ---XG------ t944 = * IND int REG x0 N1087 ( 1, 2) [000945] -c--------- t945 = CNS_INT int 0 REG NA $c0 /--* t944 int +--* t945 int N1089 ( 11, 8) [000946] -c-XG--N--- t946 = * LE int REG NA N1091 ( 1, 1) [000178] ----------z t178 = LCL_VAR int V12 loc8 u:3 x7 REG x7 $4c4 N1093 ( 1, 2) [000179] -c--------- t179 = CNS_INT int 0 REG NA $c0 /--* t178 int +--* t179 int N1095 ( 6, 4) [000180] -c-----N--- t180 = * EQ int REG NA $70a /--* t946 int +--* t180 int N1097 ( 18, 13) [003732] Jc-XG--N--- * AND void REG NA N1099 ( 20, 15) [000181] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB79 [30D..336) -> BB82 (cond), preds={BB78} succs={BB81,BB82} N1103 (???,???) [003884] ----------- IL_OFFSET void INLRT @ 0x30D[E-] REG NA N1105 (???,???) [003885] ----------- IL_OFFSET void INLRT @ 0x31E[E-] REG NA N1107 ( 1, 1) [000948] ----------- t948 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t948 ref N1109 ( 3, 4) [002658] -c--------- t2658 = * LEA(b+8) byref REG NA /--* t2658 byref N1111 ( 4, 3) [000949] n---GO----- t949 = * IND ref REG x10 /--* t949 ref N1113 ( 4, 3) [000951] DA--GO----z * STORE_LCL_VAR ref V26 loc22 d:1 x10 REG x10 N1115 (???,???) [003886] ----------- IL_OFFSET void INLRT @ 0x326[E-] REG NA N1117 ( 1, 2) [000952] -c--------- t952 = CNS_INT int 0 REG NA $c0 /--* t952 int N1119 ( 1, 3) [000954] DA--------- * STORE_LCL_VAR int V27 loc23 d:1 NA REG NA N1121 (???,???) [003887] ----------- IL_OFFSET void INLRT @ 0x329[E-] REG NA N1123 ( 1, 2) [000955] -c--------- t955 = CNS_INT int 0 REG NA $c0 /--* t955 int N1125 ( 1, 3) [000957] DA--------- * STORE_LCL_VAR int V28 loc24 d:1 x14 REG x14 N1127 (???,???) [003888] ----------- IL_OFFSET void INLRT @ 0x32C[E-] REG NA N1129 ( 1, 1) [000958] ----------- t958 = LCL_VAR ref V26 loc22 u:1 x10 REG x10 /--* t958 ref N1131 (???,???) [004158] -c--------- t4158 = * LEA(b+8) byref REG NA /--* t4158 byref N1133 ( 3, 3) [000959] ---X------- t959 = * IND int REG x12 /--* t959 int N1135 ( 3, 3) [000961] DA-X------z * STORE_LCL_VAR int V29 loc25 d:1 x12 REG x12 N1137 (???,???) [003889] ----------- IL_OFFSET void INLRT @ 0x332[E-] REG NA N1139 ( 1, 1) [000962] ----------Z t962 = LCL_VAR int V29 loc25 u:1 x12 REG x12 N1141 ( 1, 2) [000963] -c--------- t963 = CNS_INT int 0 REG NA $c0 /--* t962 int +--* t963 int N1143 ( 3, 4) [000964] CEQ-------N--- * JCMP void REG NA ------------ BB81 [336..33D), preds={BB79} succs={BB82} N1147 (???,???) [003890] ----------- IL_OFFSET void INLRT @ 0x336[E-] REG NA N1149 ( 1, 1) [002659] ----------Z t2659 = LCL_VAR ref V26 loc22 u:1 x10 REG x10 /--* t2659 ref N1151 ( 1, 1) [002667] -c--------- t2667 = * LEA(b+16) byref REG NA /--* t2667 byref N1153 ( 4, 3) [002671] n---GO----- t2671 = * IND int REG x14 /--* t2671 int N1155 ( 4, 3) [001103] DA--GO----- * STORE_LCL_VAR int V28 loc24 d:5 x14 REG x14 N001 ( 1, 1) [004385] ----------z t4385 = LCL_VAR ref V26 loc22 x10 REG x10 ------------ BB82 [33D..348) -> BB84 (cond), preds={BB79,BB81} succs={BB83,BB84} N1159 (???,???) [003891] ----------- IL_OFFSET void INLRT @ 0x33D[E-] REG NA N1161 ( 1, 1) [000966] ----------Z t966 = LCL_VAR int V28 loc24 u:2 x14 REG x14 $298 /--* t966 int N1163 ( 1, 3) [000968] DA--------- * STORE_LCL_VAR int V30 loc26 d:1 x15 REG x15 N1165 ( 1, 1) [000969] ----------Z t969 = LCL_VAR int V08 loc4 u:1 x2 REG x2 $297 /--* t969 int N1167 ( 5, 4) [000975] DA--------- * STORE_LCL_VAR int V64 tmp24 d:1 x0 REG x0 N1169 (???,???) [003892] ----------- IL_OFFSET void INLRT @ 0x341[E-] REG NA N1171 ( 1, 1) [000970] ----------- t970 = LCL_VAR int V14 loc10 u:1 x3 REG x3 $296 N1173 ( 1, 2) [000971] -c--------- t971 = CNS_INT int 0 REG NA $c0 /--* t970 int +--* t971 int N1175 ( 3, 4) [000972] J------N--- * LT void REG NA $719 N1177 ( 5, 6) [000973] ----------- * JTRUE void REG NA $VN.Void ------------ BB83 [348..34B) -> BB85 (always), preds={BB82} succs={BB85} N1181 ( 3, 2) [000977] ----------- t977 = LCL_VAR int V64 tmp24 u:1 x0 (last use) REG x0 $297 /--* t977 int N1183 ( 7, 5) [001093] DA--------- * STORE_LCL_VAR int V65 tmp25 d:3 x0 REG x0 N1185 ( 1, 2) [001091] -c--------- t1091 = CNS_INT int 0 REG NA $c0 /--* t1091 int N1187 ( 5, 5) [001096] DA--------- * STORE_LCL_VAR int V66 tmp26 d:3 x11 REG x11 ------------ BB262 [???..???) -> BB103 (always), preds={BB78} succs={BB103} N001 ( 1, 1) [004324] ----------Z t4324 = LCL_VAR int V08 loc4 x2 REG x2 ------------ BB84 [34B..34D), preds={BB82} succs={BB85} N1191 ( 3, 2) [000978] ----------- t978 = LCL_VAR int V64 tmp24 u:1 x0 (last use) REG x0 $297 /--* t978 int N1193 ( 7, 5) [000981] DA--------- * STORE_LCL_VAR int V65 tmp25 d:2 x0 REG x0 N1195 ( 1, 1) [000979] ----------Z t979 = LCL_VAR int V14 loc10 u:1 x3 REG x3 $296 /--* t979 int N1197 ( 5, 4) [000984] DA--------- * STORE_LCL_VAR int V66 tmp26 d:2 x11 REG x11 N001 ( 1, 1) [004386] ----------z t4386 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB85 [34D..35E) -> BB103 (cond), preds={BB83,BB84} succs={BB89,BB103} N1201 ( 3, 2) [000986] ----------- t986 = LCL_VAR int V65 tmp25 u:1 x0 (last use) REG x0 $297 N1203 ( 3, 2) [000987] ----------- t987 = LCL_VAR int V66 tmp26 u:1 x11 (last use) REG x11 $299 /--* t986 int +--* t987 int N1205 ( 7, 5) [000988] ----------- t988 = * ADD int REG x0 $71a /--* t988 int N1207 ( 11, 8) [000990] DA--------- * STORE_LCL_VAR int V31 loc27 d:1 x0 REG x0 N1209 (???,???) [003893] ----------- IL_OFFSET void INLRT @ 0x350[E-] REG NA N1211 (???,???) [003894] ----------- IL_OFFSET void INLRT @ 0x355[E-] REG NA N1213 ( 1, 1) [000991] ----------- t991 = LCL_VAR int V06 loc2 u:3 x22 REG x22 $292 N1215 ( 3, 2) [000992] ----------- t992 = LCL_VAR int V31 loc27 u:1 x0 REG x0 $71a /--* t991 int +--* t992 int N1217 ( 5, 4) [000993] Jc-----N--- t993 = * GT int REG NA $71b N1219 ( 1, 1) [000995] ----------- t995 = LCL_VAR int V06 loc2 u:3 x22 REG x22 $292 N1221 ( 3, 2) [001087] ----------- t1087 = LCL_VAR int V31 loc27 u:1 x0 (last use) REG x0 $71a /--* t993 int +--* t995 int +--* t1087 int N1223 ( 10, 8) [003768] ----------- t3768 = * SELECT int REG xip0 /--* t3768 int N1225 ( 14, 11) [001089] DA--------- * STORE_LCL_VAR int V67 tmp27 d:3 xip0 REG xip0 N1227 (???,???) [003895] ----------- IL_OFFSET void INLRT @ 0x359[E-] REG NA N1229 ( 3, 2) [000999] ----------- t999 = LCL_VAR int V67 tmp27 u:1 xip0 (last use) REG xip0 $29a /--* t999 int N1231 ( 3, 3) [001001] DA--------z * STORE_LCL_VAR int V32 loc28 d:1 xip0 REG xip0 N1233 (???,???) [003896] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] REG NA N1235 ( 1, 1) [003158] ----------Z t3158 = LCL_VAR int V32 loc28 u:1 xip0 REG xip0 $29a N1237 ( 1, 1) [003159] ----------- t3159 = LCL_VAR int V30 loc26 u:1 x15 REG x15 $298 /--* t3158 int +--* t3159 int N1239 ( 3, 3) [003157] J------N--- * LE void REG NA $71c N1241 ( 5, 5) [003156] ----------- * JTRUE void REG NA $VN.Void ------------ BB89 [35E..362) -> BB103 (cond), preds={BB85,BB102} succs={BB90,BB103} N1245 (???,???) [003897] ----------- IL_OFFSET void INLRT @ 0x35E[E-] REG NA N1247 ( 1, 1) [001006] ----------Z t1006 = LCL_VAR int V30 loc26 u:2 x15 REG x15 $29d N1249 ( 1, 2) [001007] -c--------- t1007 = CNS_INT int 0 REG NA $c0 /--* t1006 int +--* t1007 int N1251 ( 3, 4) [001008] CEQ-------N--- * JCMP void REG NA ------------ BB90 [362..373) -> BB100 (cond), preds={BB89} succs={BB91,BB100} N1255 (???,???) [003898] ----------- IL_OFFSET void INLRT @ 0x362[E-] REG NA N1257 ( 1, 1) [001010] ----------- t1010 = LCL_VAR int V20 loc16 u:10 x9 (last use) REG x9 $29b N1259 ( 1, 2) [001011] -c--------- t1011 = CNS_INT int 1 REG NA $c1 /--* t1010 int +--* t1011 int N1261 ( 3, 4) [001012] ----------- t1012 = * ADD int REG x9 $71f /--* t1012 int N1263 ( 3, 4) [001014] DA--------- * STORE_LCL_VAR int V20 loc16 d:11 x9 REG x9 N1265 (???,???) [003899] ----------- IL_OFFSET void INLRT @ 0x368[E-] REG NA N1267 ( 1, 1) [001015] ----------Z t1015 = LCL_VAR int V20 loc16 u:11 x9 REG x9 $71f N1269 ( 1, 1) [001574] ----------- t1574 = LCL_VAR int V144 tmp104 u:3 x8 REG x8 $29c /--* t1015 int +--* t1574 int N1271 ( 3, 3) [001020] J------N--- * LT void REG NA $720 N1273 ( 5, 5) [001021] ----------- * JTRUE void REG NA $VN.Void ------------ BB91 [000..39A) -> BB110 (cond), preds={BB90} succs={BB95,BB110} N001 ( 1, 1) [004387] ----------Z t4387 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004388] ----------Z t4388 = LCL_VAR ref V26 loc22 x10 REG x10 N1277 (???,???) [003900] ----------- IL_OFFSET void INLRT @ 0x373[E-] REG NA N1279 ( 1, 1) [001578] ----------Z t1578 = LCL_VAR int V144 tmp104 u:3 x8 REG x8 $29c N1281 ( 1, 2) [001065] -c--------- t1065 = CNS_INT int 1 REG NA $c1 /--* t1578 int +--* t1065 int N1283 ( 3, 4) [001066] ----------- t1066 = * LSH int REG x0 $721 /--* t1066 int N1285 ( 4, 6) [001067] ----------- t1067 = * CAST long <- int REG x0 $3cf /--* t1067 long N1287 (???,???) [004221] ----------- t4221 = * PUTARG_REG long REG x0 N1289 ( 2, 8) [002672] H---------- t2672 = CNS_INT(h) long 0x4000000000421858 ftn REG x11 $49 /--* t2672 long N1291 (???,???) [004222] ----------- t4222 = * PUTARG_REG long REG x11 /--* t4221 long arg1 in x0 +--* t4222 long r2r cell in x11 N1293 ( 20, 18) [001068] --CXG------ t1068 = * CALL help r2r_ind ref CORINFO_HELP_READYTORUN_NEWARR_1 REG x0 $330 /--* t1068 ref N1295 ( 20, 18) [001070] DA-XG-----z * STORE_LCL_VAR ref V33 loc29 d:1 x3 REG x3 N1297 (???,???) [003901] ----------- IL_OFFSET void INL14 @ 0x000[E-] <- INLRT @ 0x383[E-] REG NA N1299 (???,???) [003902] ----------- IL_OFFSET void INL15 @ 0x038[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] REG NA N1301 ( 1, 1) [002689] ----------- t2689 = LCL_VAR ref V33 loc29 u:1 x3 REG x3 $800 N1303 ( 1, 2) [002690] -c--------- t2690 = CNS_INT long 16 Fseq[] REG NA $200 /--* t2689 ref +--* t2690 long N1305 ( 3, 4) [002691] -----O----- t2691 = * ADD byref REG x0 $253 /--* t2691 byref N1307 ( 3, 4) [001604] DA---O----- * STORE_LCL_VAR byref V159 tmp119 d:2 x0 REG x0 N1309 (???,???) [003903] ----------- IL_OFFSET void INL15 @ 0x044[E-] <- INL14 @ ??? <- INLRT @ 0x383[E-] REG NA N1311 ( 1, 1) [001607] ----------Z t1607 = LCL_VAR ref V33 loc29 u:1 x3 REG x3 $800 /--* t1607 ref N1313 (???,???) [004160] -c--------- t4160 = * LEA(b+8) byref REG NA /--* t4160 byref N1315 ( 3, 3) [001608] ---X------- t1608 = * IND int REG x2 $2cc /--* t1608 int N1317 ( 3, 3) [001610] DA-X------- * STORE_LCL_VAR int V160 tmp120 d:2 x2 REG x2 N1319 ( 1, 1) [002694] ----------- t2694 = LCL_VAR byref V159 tmp119 u:1 x0 (last use) REG x0 $382 /--* t2694 byref N1321 ( 1, 3) [002695] DA--------- * STORE_LCL_VAR byref V161 tmp121 d:1 x0 REG x0 N1323 ( 1, 1) [001620] ----------z t1620 = LCL_VAR int V144 tmp104 u:3 x4 REG x4 $29c N1325 ( 1, 1) [001647] ----------- t1647 = LCL_VAR int V160 tmp120 u:1 x2 (last use) REG x2 $2a0 /--* t1620 int +--* t1647 int N1327 ( 3, 3) [001628] N------N-U- * GT void REG NA $722 N1329 ( 5, 5) [001629] ----------- * JTRUE void REG NA $VN.Void ------------ BB95 [000..392), preds={BB91} succs={BB100} N1333 (???,???) [003904] ----------- IL_OFFSET void INL17 @ 0x00F[E-] <- INLRT @ ??? REG NA N1335 ( 1, 1) [001639] ----------- t1639 = LCL_VAR int V144 tmp104 u:3 x4 (last use) REG x4 $29c /--* t1639 int N1337 ( 2, 3) [001640] ---------U- t1640 = * CAST long <- ulong <- uint REG x2 $3d0 /--* t1640 long N1339 ( 2, 3) [001673] DA--------- * STORE_LCL_VAR long V83 tmp43 d:1 x2 REG x2 N1341 (???,???) [003905] ----------- IL_OFFSET void INL19 @ 0x007[E-] <- INL17 @ 0x00F[E-] <- INLRT @ ??? REG NA N1343 ( 1, 1) [001663] ----------- t1663 = LCL_VAR long V83 tmp43 u:1 x2 (last use) REG x2 $3d0 N1345 ( 1, 2) [001665] -c--------- t1665 = CNS_INT long 2 REG NA $20a /--* t1663 long +--* t1665 long N1347 ( 3, 4) [001666] ----------- t1666 = * LSH long REG x2 $3d1 /--* t1666 long N1349 (???,???) [004223] ----------- t4223 = * PUTARG_REG long REG x2 N1351 ( 1, 1) [001661] ----------- t1661 = LCL_VAR byref V161 tmp121 u:1 x0 (last use) REG x0 $382 /--* t1661 byref N1353 (???,???) [004224] ----------- t4224 = * PUTARG_REG byref REG x0 N1355 ( 1, 1) [001662] ----------z t1662 = LCL_VAR byref V143 tmp103 u:3 x1 (last use) REG x1 $381 /--* t1662 byref N1357 (???,???) [004225] ----------- t4225 = * PUTARG_REG byref REG x1 N1359 ( 2, 8) [002700] H---------- t2700 = CNS_INT(h) long 0x4000000000420490 ftn REG x11 $4b /--* t2700 long N1361 (???,???) [004226] ----------- t4226 = * PUTARG_REG long REG x11 /--* t4223 long arg3 in x2 +--* t4224 byref arg1 in x0 +--* t4225 byref arg2 in x1 +--* t4226 long r2r cell in x11 N1363 ( 21, 20) [001667] --CXG------ * CALL r2r_ind void REG NA $VN.Void N1365 (???,???) [003906] ----------- IL_OFFSET void INL22 @ 0x000[E-] <- INLRT @ 0x391[E-] REG NA N1367 (???,???) [003907] ----------- IL_OFFSET void INL23 @ 0x038[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] REG NA N1369 ( 1, 1) [002718] ----------z t2718 = LCL_VAR ref V33 loc29 u:1 x0 REG x0 $800 N1371 ( 1, 2) [002719] -c--------- t2719 = CNS_INT long 16 Fseq[] REG NA $200 /--* t2718 ref +--* t2719 long N1373 ( 3, 4) [002720] -----O----- t2720 = * ADD byref REG x1 $253 /--* t2720 byref N1375 ( 3, 4) [001716] DA---O----- * STORE_LCL_VAR byref V163 tmp123 d:2 x1 REG x1 N1377 (???,???) [003908] ----------- IL_OFFSET void INL23 @ 0x044[E-] <- INL22 @ ??? <- INLRT @ 0x391[E-] REG NA N1379 ( 1, 1) [001719] ----------- t1719 = LCL_VAR ref V33 loc29 u:1 x0 (last use) REG x0 $800 /--* t1719 ref N1381 (???,???) [004162] -c--------- t4162 = * LEA(b+8) byref REG NA /--* t4162 byref N1383 ( 3, 3) [001720] ---X------- t1720 = * IND int REG x4 $2cc /--* t1720 int N1385 ( 3, 3) [001722] DA-X------- * STORE_LCL_VAR int V164 tmp124 d:2 x4 REG x4 N1387 (???,???) [003909] ----------- IL_OFFSET void INLRT @ 0x391[E-] REG NA N1389 ( 1, 1) [002723] ----------- t2723 = LCL_VAR byref V163 tmp123 u:1 x1 (last use) REG x1 $383 /--* t2723 byref N1391 ( 1, 3) [002724] DA--------- * STORE_LCL_VAR byref V143 tmp103 d:5 x2 REG x2 N1393 ( 1, 1) [002726] ----------- t2726 = LCL_VAR int V164 tmp124 u:1 x4 (last use) REG x4 $2a1 /--* t2726 int N1395 ( 1, 3) [002727] DA--------- * STORE_LCL_VAR int V144 tmp104 d:5 x3 REG x3 N001 ( 1, 1) [004389] ----------Z t4389 = LCL_VAR byref V143 tmp103 x2 REG x2 N001 ( 1, 1) [004390] ----------- t4390 = LCL_VAR int V144 tmp104 x3 REG x3 /--* t4390 int N002 ( 2, 2) [004391] ----------- t4391 = * COPY int REG x8 N001 ( 1, 1) [004392] ----------z t4392 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004393] ----------z t4393 = LCL_VAR ref V26 loc22 x10 REG x10 ------------ BB100 [39A..3AE) -> BB102 (cond), preds={BB90,BB95} succs={BB101,BB102} N1399 (???,???) [003910] ----------- IL_OFFSET void INLRT @ 0x39A[E-] REG NA N1401 ( 1, 1) [001024] ----------z t1024 = LCL_VAR int V20 loc16 u:11 x9 REG x9 $71f N1403 ( 1, 1) [001028] ----------Z t1028 = LCL_VAR int V144 tmp104 u:4 x8 REG x8 $2a2 /--* t1024 int +--* t1028 int N1405 ( 6, 9) [001029] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $334 N1407 ( 1, 1) [001033] ----------z t1033 = LCL_VAR byref V143 tmp103 u:4 x6 REG x6 $384 N1409 ( 1, 1) [001025] ----------Z t1025 = LCL_VAR int V20 loc16 u:11 x9 REG x9 $71f /--* t1025 int N1411 ( 2, 3) [001030] -c-------U- t1030 = * CAST long <- uint REG NA $3d2 N1413 ( 1, 2) [001031] -c--------- t1031 = CNS_INT long 2 REG NA $20a /--* t1030 long +--* t1031 long N1415 ( 4, 6) [001032] -c--------- t1032 = * BFIZ long REG NA /--* t1033 byref +--* t1032 long N1417 ( 6, 8) [001034] -c--------- t1034 = * LEA(b+(i*1)+0) byref REG NA N1419 ( 1, 1) [001036] ----------z t1036 = LCL_VAR int V28 loc24 u:3 x14 REG x14 $29f /--* t1034 byref +--* t1036 int N1421 (???,???) [003911] -A-XGO----- * STOREIND int REG NA N1423 (???,???) [003912] ----------- IL_OFFSET void INLRT @ 0x3A6[E-] REG NA N1425 ( 1, 1) [001039] ----------z t1039 = LCL_VAR int V27 loc23 u:2 x13 REG x13 $29e N1427 ( 1, 1) [001040] ----------z t1040 = LCL_VAR int V29 loc25 u:1 x12 REG x12 N1429 ( 1, 2) [001041] -c--------- t1041 = CNS_INT int -1 REG NA $c4 /--* t1040 int +--* t1041 int N1431 ( 3, 4) [001042] ----------- t1042 = * ADD int REG x0 /--* t1039 int +--* t1042 int N1433 ( 5, 6) [001043] J------N--- * GE void REG NA N1435 ( 7, 8) [001044] ----------- * JTRUE void REG NA $VN.Void ------------ BB101 [3AE..3BB), preds={BB100} succs={BB102} N1439 (???,???) [003913] ----------- IL_OFFSET void INLRT @ 0x3AE[E-] REG NA N1441 ( 1, 1) [001050] ----------- t1050 = LCL_VAR int V27 loc23 u:2 x13 (last use) REG x13 $29e N1443 ( 1, 2) [001051] -c--------- t1051 = CNS_INT int 1 REG NA $c1 /--* t1050 int +--* t1051 int N1445 ( 3, 4) [001052] ----------- t1052 = * ADD int REG x13 $727 /--* t1052 int N1447 ( 3, 4) [001054] DA--------- * STORE_LCL_VAR int V27 loc23 d:4 x13 REG x13 N1449 (???,???) [003914] ----------- IL_OFFSET void INLRT @ 0x3B4[E-] REG NA N1451 ( 1, 1) [001056] ----------- t1056 = LCL_VAR int V27 loc23 u:4 x13 REG x13 $727 N1453 ( 1, 1) [001055] ----------- t1055 = LCL_VAR ref V26 loc22 u:1 x10 REG x10 /--* t1055 ref N1455 (???,???) [004164] -c--------- t4164 = * LEA(b+8) byref REG NA /--* t4164 byref N1457 ( 3, 3) [002732] ---X------- t2732 = * IND int REG x15 /--* t1056 int +--* t2732 int N1459 ( 8, 11) [002733] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N1461 ( 1, 1) [002730] ----------- t2730 = LCL_VAR ref V26 loc22 u:1 x10 REG x10 N1463 ( 1, 2) [002737] -c--------- t2737 = CNS_INT long 16 REG NA $200 /--* t2730 ref +--* t2737 long N1465 ( 3, 4) [002738] ----------- t2738 = * ADD byref REG x0 N1467 ( 1, 1) [002731] ----------- t2731 = LCL_VAR int V27 loc23 u:4 x13 REG x13 $727 /--* t2731 int N1469 ( 2, 3) [002734] -c-------U- t2734 = * CAST long <- uint REG NA $3d4 N1471 ( 1, 2) [002735] -c-----N--- t2735 = CNS_INT long 2 REG NA $20a /--* t2734 long +--* t2735 long N1473 ( 4, 6) [002736] -c--------- t2736 = * BFIZ long REG NA /--* t2738 byref +--* t2736 long N1475 ( 7, 10) [002739] -c--------- t2739 = * LEA(b+(i*1)+0) byref REG NA /--* t2739 byref N1477 ( 10, 12) [002742] n---GO----- t2742 = * IND int REG x15 /--* t2742 int N1479 ( 18, 23) [001060] DA-XGO----- * STORE_LCL_VAR int V30 loc26 d:4 x0 REG x0 N001 ( 1, 1) [004394] ----------Z t4394 = LCL_VAR int V30 loc26 x0 REG x0 ------------ BB102 [3BB..3C8) -> BB89 (cond), preds={BB100,BB101} succs={BB103,BB89} N1483 (???,???) [003915] ----------- IL_OFFSET void INLRT @ 0x3BB[E-] REG NA N1485 ( 1, 1) [001045] ----------- t1045 = LCL_VAR int V28 loc24 u:3 x14 (last use) REG x14 $29f N1487 ( 1, 1) [001046] ----------z t1046 = LCL_VAR int V30 loc26 u:3 x15 REG x15 $2a3 /--* t1045 int +--* t1046 int N1489 ( 3, 3) [001047] ----------- t1047 = * ADD int REG x14 $72b /--* t1047 int N1491 ( 3, 3) [001049] DA--------- * STORE_LCL_VAR int V28 loc24 d:4 x14 REG x14 N1493 (???,???) [003916] ----------- IL_OFFSET void INLRT @ 0x3C2[E-] REG NA N1495 ( 1, 1) [001002] ----------z t1002 = LCL_VAR int V32 loc28 u:1 xip0 REG xip0 $29a N1497 ( 1, 1) [001003] ----------- t1003 = LCL_VAR int V28 loc24 u:4 x14 REG x14 $72b /--* t1002 int +--* t1003 int N1499 ( 3, 3) [001004] J------N--- * GT void REG NA $72c N001 ( 1, 1) [004325] ----------Z t4325 = LCL_VAR int V28 loc24 x14 REG x14 N001 ( 1, 1) [004326] ----------Z t4326 = LCL_VAR int V27 loc23 x13 REG x13 N001 ( 1, 1) [004327] ----------Z t4327 = LCL_VAR int V29 loc25 x12 REG x12 N001 ( 1, 1) [004328] ----------Z t4328 = LCL_VAR int V32 loc28 xip0 REG xip0 N001 ( 1, 1) [004329] ----------z t4329 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004330] ----------z t4330 = LCL_VAR int V20 loc16 x9 REG x9 N1501 ( 5, 5) [001005] ----------- * JTRUE void REG NA $VN.Void ------------ BB103 [3C8..3D0) -> BB112 (cond), preds={BB85,BB89,BB102,BB262} succs={BB104,BB112} N1505 (???,???) [003917] ----------- IL_OFFSET void INLRT @ 0x3C8[E-] REG NA N1507 ( 1, 1) [000182] ----------- t182 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t182 byref N1509 ( 3, 4) [002744] -c--------- t2744 = * LEA(b+8) byref REG NA /--* t2744 byref N1511 ( 5, 4) [000183] n---GO----- t183 = * IND bool REG x0 N1513 ( 1, 2) [000184] -c--------- t184 = CNS_INT int 0 REG NA $c0 /--* t183 bool +--* t184 int N1515 ( 10, 7) [000185] -c--GO-N--- t185 = * EQ int REG NA N1517 ( 1, 1) [000927] ----------z t927 = LCL_VAR int V16 loc12 u:3 x4 REG x4 $283 N1519 ( 1, 2) [000928] -c--------- t928 = CNS_INT int 0 REG NA $c0 /--* t927 int +--* t928 int N1521 ( 6, 4) [000929] -c-----N--- t929 = * NE int REG NA $733 /--* t185 int +--* t929 int N1523 ( 17, 12) [003734] Jc--GO-N--- * AND void REG NA N1525 ( 19, 14) [000186] ----GO----- * JTRUE void REG NA $301 ------------ BB104 [3D0..3DC) -> BB112 (cond), preds={BB103} succs={BB106,BB112} N1529 (???,???) [003918] ----------- IL_OFFSET void INLRT @ 0x3D0[E-] REG NA N1531 (???,???) [003919] ----------- IL_OFFSET void INLRT @ 0x3D4[E-] REG NA N1533 ( 1, 1) [000931] ----------- t931 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t931 byref N1535 ( 3, 4) [002746] -c--------- t2746 = * LEA(b+4) byref REG NA /--* t2746 byref N1537 ( 4, 3) [000932] n---GO----- t932 = * IND int REG x0 N1539 ( 1, 2) [000933] -c--------- t933 = CNS_INT int 0 REG NA $c0 /--* t932 int +--* t933 int N1541 ( 6, 6) [000934] CEQ----GO-N--- * JCMP void REG NA ------------ BB106 [3DC..3E8) -> BB112 (cond), preds={BB104} succs={BB107,BB112} N1545 (???,???) [003920] ----------- IL_OFFSET void INLRT @ 0x3DC[E-] REG NA N1547 ( 1, 1) [000937] ----------- t937 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t937 ref N1549 ( 3, 4) [002748] -c--------- t2748 = * LEA(b+40) byref REG NA /--* t2748 byref N1551 ( 4, 3) [001730] ---XG------ t1730 = * IND ref REG x11 /--* t1730 ref N1553 ( 4, 3) [001783] DA-XG------ * STORE_LCL_VAR ref V86 tmp46 d:1 x11 REG x11 N1555 (???,???) [003921] ----------- IL_OFFSET void INL26 @ 0x000[E-] <- INLRT @ 0x3DC[E-] REG NA N1557 ( 1, 1) [001732] ----------- t1732 = LCL_VAR ref V86 tmp46 u:1 x11 REG x11 N1559 ( 1, 2) [001733] -c--------- t1733 = CNS_INT ref null REG NA $VN.Null /--* t1732 ref +--* t1733 ref N1561 ( 3, 4) [001734] CEQ-------N--- * JCMP void REG NA ------------ BB107 [3DC..3DD) -> BB111 (cond), preds={BB106} succs={BB108,BB111} N1565 (???,???) [003922] ----------- IL_OFFSET void INL26 @ 0x004[E-] <- INLRT @ 0x3DC[E-] REG NA N1567 ( 1, 1) [000936] ----------- t936 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t936 byref N1569 ( 3, 4) [002750] -c--------- t2750 = * LEA(b+8) byref REG NA /--* t2750 byref N1571 ( 4, 3) [001736] ---XG------ t1736 = * IND int REG x0 /--* t1736 int N1573 ( 8, 6) [001738] DA-XG------ * STORE_LCL_VAR int V87 tmp47 d:1 x0 REG x0 N1575 (???,???) [003923] ----------- IL_OFFSET void INL26 @ 0x00B[E-] <- INLRT @ 0x3DC[E-] REG NA N1577 ( 1, 1) [001739] ----------- t1739 = LCL_VAR ref V86 tmp46 u:1 x11 REG x11 /--* t1739 ref N1579 (???,???) [004166] -c--------- t4166 = * LEA(b+8) byref REG NA /--* t4166 byref N1581 ( 3, 3) [001740] ---X------- t1740 = * IND int REG x10 N1583 ( 1, 2) [001741] -c--------- t1741 = CNS_INT int 1 REG NA $c1 /--* t1740 int +--* t1741 int N1585 ( 8, 6) [001742] Nc-X---N-U- t1742 = * NE int REG NA N1587 ( 3, 2) [001747] ----------- t1747 = LCL_VAR int V87 tmp47 u:1 x0 REG x0 N1589 ( 1, 1) [001748] ----------- t1748 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1748 byref N1591 ( 3, 4) [002754] -c--------- t2754 = * LEA(b+24) byref REG NA /--* t2754 byref N1593 ( 4, 3) [001786] n---GO----- t1786 = * IND int REG x13 /--* t1747 int +--* t1786 int N1595 ( 11, 6) [001752] Nc--GO-N-U- t1752 = * GE int REG NA /--* t1742 int +--* t1752 int N1597 ( 20, 13) [003736] Jc-XGO-N--- * AND void REG NA N1599 ( 22, 15) [001743] ---XGO----- * JTRUE void REG NA ------------ BB108 [3DC..3DD), preds={BB107} succs={BB112} N1603 (???,???) [003924] ----------- IL_OFFSET void INL26 @ 0x014[E-] <- INLRT @ 0x3DC[E-] REG NA N1605 (???,???) [003925] ----------- IL_OFFSET void INL26 @ 0x022[E-] <- INLRT @ 0x3DC[E-] REG NA N1607 ( 1, 1) [002758] ----------- t2758 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N1609 ( 1, 2) [002759] -c--------- t2759 = CNS_INT long 16 REG NA $200 /--* t2758 byref +--* t2759 long N1611 ( 3, 4) [002760] -----O----- t2760 = * ADD byref REG x10 $25c /--* t2760 byref N1613 ( 3, 4) [001759] DA--GO----- * STORE_LCL_VAR byref V88 tmp48 d:1 x10 REG x10 N1615 (???,???) [003926] ----------- IL_OFFSET void INL26 @ ??? <- INLRT @ 0x3DC[E-] REG NA N1617 ( 3, 2) [001756] ----------- t1756 = LCL_VAR int V87 tmp47 u:1 x0 REG x0 N1619 ( 1, 1) [001761] ----------- t1761 = LCL_VAR byref V88 tmp48 u:1 x10 REG x10 $25c /--* t1761 byref N1621 ( 3, 4) [002763] -c--------- t2763 = * LEA(b+8) byref REG NA /--* t2763 byref N1623 ( 4, 3) [001762] n---GO----- t1762 = * IND int REG x13 /--* t1756 int +--* t1762 int N1625 ( 11, 12) [001763] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N1627 ( 1, 1) [001760] ----------- t1760 = LCL_VAR byref V88 tmp48 u:1 x10 (last use) REG x10 $25c /--* t1760 byref N1629 ( 3, 2) [001767] n---GO----- t1767 = * IND byref REG x10 N1631 ( 3, 2) [001757] ----------- t1757 = LCL_VAR int V87 tmp47 u:1 x0 REG x0 /--* t1757 int N1633 ( 4, 4) [001764] -c-------U- t1764 = * CAST long <- uint REG NA N1635 ( 1, 2) [001765] -c--------- t1765 = CNS_INT long 1 REG NA $204 /--* t1764 long +--* t1765 long N1637 ( 6, 7) [001766] ----------- t1766 = * BFIZ long REG x13 /--* t1767 byref +--* t1766 long N1639 ( 10, 10) [001768] ----GO-N--- t1768 = * ADD byref REG x10 N1641 ( 1, 1) [002765] ----------- t2765 = LCL_VAR ref V86 tmp46 u:1 x11 (last use) REG x11 /--* t2765 ref N1643 ( 1, 1) [002772] -c--------- t2772 = * LEA(b+12) byref REG NA /--* t2772 byref N1645 ( 5, 4) [002777] n---GO----- t2777 = * IND ushort REG x11 /--* t1768 byref +--* t2777 ushort N1647 (???,???) [003927] -A-XGO----- * STOREIND short REG NA N1649 (???,???) [003928] ----------- IL_OFFSET void INL26 @ 0x036[E-] <- INLRT @ 0x3DC[E-] REG NA N1651 ( 3, 2) [001777] ----------- t1777 = LCL_VAR int V87 tmp47 u:1 x0 (last use) REG x0 N1653 ( 1, 2) [001778] -c--------- t1778 = CNS_INT int 1 REG NA $c1 /--* t1777 int +--* t1778 int N1655 ( 5, 5) [001779] ----------- t1779 = * ADD int REG x0 N1657 ( 1, 1) [001776] ----------- t1776 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1776 byref N1659 ( 3, 4) [002779] -c--------- t2779 = * LEA(b+8) byref REG NA /--* t2779 byref +--* t1779 int N1661 (???,???) [003929] -A--GO----- * STOREIND int REG NA ------------ BB112 [3E8..401), preds={BB103,BB104,BB106,BB108,BB111} succs={BB245} N1683 (???,???) [003930] ----------- IL_OFFSET void INLRT @ 0x3E8[E-] REG NA N1685 ( 1, 2) [002781] -c--------- t2781 = CNS_INT int 0 REG NA $c0 /--* t2781 int N1687 ( 1, 3) [000189] DA--------- * STORE_LCL_VAR int V21 loc17 d:1 NA REG NA N1689 (???,???) [003931] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] REG NA N1691 ( 1, 1) [003714] ----------- t3714 = LCL_VAR byref V180 cse9 u:1 x24 (last use) REG x24 $246 /--* t3714 byref N1693 ( 1, 3) [002784] DA--------- * STORE_LCL_VAR byref V165 tmp125 d:1 x24 REG x24 N1695 (???,???) [003932] ----------- IL_OFFSET void INLRT @ 0x3EB[E-] REG NA N1697 ( 1, 1) [001792] ----------- t1792 = LCL_VAR byref V165 tmp125 u:1 x24 REG x24 $246 /--* t1792 byref N1699 ( 5, 4) [000196] DA--------- * STORE_LCL_VAR byref V35 loc31 NA REG NA N1701 (???,???) [003933] ----------- IL_OFFSET void INLRT @ 0x3F3[E-] REG NA N1703 ( 1, 1) [000197] ----------- t197 = LCL_VAR byref V165 tmp125 u:1 x24 (last use) REG x24 $246 /--* t197 byref N1705 ( 1, 3) [002790] DA--------- * STORE_LCL_VAR long V169 tmp129 d:1 x24 REG x24 N1707 ( 1, 1) [002791] ----------- t2791 = LCL_VAR long V169 tmp129 u:1 x24 (last use) REG x24 $3c4 /--* t2791 long N1709 ( 2, 4) [000200] DA--------- * STORE_LCL_VAR long V34 loc30 d:1 x24 REG x24 N1711 (???,???) [003934] ----------- IL_OFFSET void INLRT @ 0x3F8[E-] REG NA N1713 ( 1, 1) [000201] ----------- t201 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t201 long N1715 ( 1, 3) [000203] DA--------- * STORE_LCL_VAR long V36 loc32 d:1 x0 REG x0 ------------ BB245 [7AA..7B5) -> BB248 (cond), preds={BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB266,BB268} succs={BB246,BB248} N1719 (???,???) [003935] ----------- IL_OFFSET void INLRT @ 0x7AA[E-] REG NA N1721 ( 1, 1) [000204] ----------z t204 = LCL_VAR int V16 loc12 u:4 x4 REG x4 $2ae N1723 ( 1, 1) [003707] ----------- t3707 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t204 int +--* t3707 int N1725 ( 3, 3) [000209] J------N--- * GE void REG NA $897 N1727 ( 5, 5) [000210] ----------- * JTRUE void REG NA $VN.Void ------------ BB246 [7B5..7C8) -> BB248 (cond), preds={BB245} succs={BB247,BB248} N1731 (???,???) [003936] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] REG NA N1733 ( 1, 1) [000243] ----------- t243 = LCL_VAR int V16 loc12 u:4 x4 (last use) REG x4 $2ae /--* t243 int N1735 ( 1, 3) [000250] DA--------- * STORE_LCL_VAR int V49 tmp9 d:1 x11 REG x11 N1737 (???,???) [003937] ----------- IL_OFFSET void INLRT @ 0x7B5[E-] REG NA N1739 ( 1, 1) [000244] ----------- t244 = LCL_VAR int V49 tmp9 u:1 x11 REG x11 $2ae N1741 ( 1, 2) [000245] -c--------- t245 = CNS_INT int 1 REG NA $c1 /--* t244 int +--* t245 int N1743 ( 3, 4) [000246] ----------- t246 = * ADD int REG x4 $898 /--* t246 int N1745 ( 3, 4) [000248] DA--------- * STORE_LCL_VAR int V16 loc12 d:5 NA REG NA N1747 ( 1, 1) [000242] ----------- t242 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N1749 ( 1, 1) [000251] ----------- t251 = LCL_VAR int V49 tmp9 u:1 x11 (last use) REG x11 $2ae /--* t251 int N1751 ( 2, 3) [000252] -c--------- t252 = * CAST long <- int REG NA $3db N1753 ( 1, 2) [000254] -c--------- t254 = CNS_INT long 1 REG NA $204 /--* t252 long +--* t254 long N1755 ( 4, 6) [000255] -c--------- t255 = * BFIZ long REG NA /--* t242 long +--* t255 long N1757 ( 6, 8) [000256] -c--------- t256 = * LEA(b+(i*1)+0) long REG NA /--* t256 long N1759 ( 9, 10) [000257] ---XG------ t257 = * IND ushort REG x13 /--* t257 ushort N1761 ( 9, 10) [000259] DA-XG------ * STORE_LCL_VAR int V50 tmp10 d:1 x13 REG x13 N1763 ( 1, 1) [000261] ----------- t261 = LCL_VAR int V50 tmp10 u:1 x13 (last use) REG x13 /--* t261 int N1765 ( 1, 3) [000263] DA--------- * STORE_LCL_VAR int V18 loc14 d:1 x13 REG x13 N1767 ( 1, 1) [000260] ----------- t260 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1769 ( 1, 2) [000264] -c--------- t264 = CNS_INT int 0 REG NA $c0 /--* t260 int +--* t264 int N1771 ( 3, 4) [000265] CEQ-------N--- * JCMP void REG NA ------------ BB247 [7C8..7D1) -> BB113 (cond), preds={BB246} succs={BB248,BB113} N1775 (???,???) [003938] ----------- IL_OFFSET void INLRT @ 0x7C8[E-] REG NA N1777 ( 1, 1) [000267] ----------- t267 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1779 ( 1, 2) [000268] -c--------- t268 = CNS_INT int 59 REG NA $d1 /--* t267 int +--* t268 int N1781 ( 3, 4) [000269] N------N-U- * NE void REG NA N1783 ( 5, 6) [000270] ----------- * JTRUE void REG NA $VN.Void ------------ BB248 [7D1..7DD) -> BB253 (cond), preds={BB245,BB246,BB247} succs={BB249,BB253} N3595 (???,???) [003939] ----------- IL_OFFSET void INLRT @ 0x7D1[E-] REG NA N3597 ( 1, 2) [000212] -c--------- t212 = CNS_INT long 0 REG NA $205 /--* t212 long N3599 ( 5, 5) [000214] DA--------- * STORE_LCL_VAR byref V35 loc31 NA REG NA N3601 (???,???) [003940] ----------- IL_OFFSET void INLRT @ 0x7D5[E-] REG NA N3603 ( 1, 1) [000215] ----------- t215 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t215 byref N3605 ( 3, 4) [003148] -c--------- t3148 = * LEA(b+8) byref REG NA /--* t3148 byref N3607 ( 5, 4) [000216] n---GO----- t216 = * IND bool REG x2 N3609 ( 1, 2) [000217] -c--------- t217 = CNS_INT int 0 REG NA $c0 /--* t216 bool +--* t217 int N3611 ( 10, 7) [000218] -c--GO-N--- t218 = * EQ int REG NA N3613 ( 1, 1) [000221] ----------- t221 = LCL_VAR int V15 loc11 u:2 x26 (last use) REG x26 $283 N3615 ( 1, 2) [000222] -c--------- t222 = CNS_INT int 0 REG NA $c0 /--* t221 int +--* t222 int N3617 ( 6, 4) [000223] -c-----N--- t223 = * NE int REG NA $733 /--* t218 int +--* t223 int N3619 ( 17, 12) [003764] Jc--GO-N--- * AND void REG NA N3621 ( 19, 14) [000219] ----GO----- * JTRUE void REG NA $301 ------------ BB249 [7DD..7E9) -> BB253 (cond), preds={BB248} succs={BB251,BB253} N3625 (???,???) [003941] ----------- IL_OFFSET void INLRT @ 0x7DD[E-] REG NA N3627 (???,???) [003942] ----------- IL_OFFSET void INLRT @ 0x7E1[E-] REG NA N3629 ( 1, 1) [000225] ----------- t225 = LCL_VAR byref V01 arg1 u:1 x21 (last use) REG x21 $101 /--* t225 byref N3631 ( 3, 4) [003150] -c--------- t3150 = * LEA(b+4) byref REG NA /--* t3150 byref N3633 ( 4, 3) [000226] n---GO----- t226 = * IND int REG x2 N3635 ( 1, 2) [000227] -c--------- t227 = CNS_INT int 0 REG NA $c0 /--* t226 int +--* t227 int N3637 ( 9, 6) [000228] ----GO-N--- t228 = * NE int REG x2 N3639 ( 1, 1) [000230] ----------- t230 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t230 byref N3641 ( 3, 4) [003152] -c--------- t3152 = * LEA(b+8) byref REG NA /--* t3152 byref N3643 ( 4, 3) [002539] ---XG------ t2539 = * IND int REG x0 N3645 ( 1, 2) [000233] -c--------- t233 = CNS_INT int 0 REG NA $c0 /--* t2539 int +--* t233 int N3647 ( 9, 6) [000234] ---XG--N--- t234 = * LE int REG x0 /--* t228 int +--* t234 int N3649 ( 19, 13) [003766] J--XGO-N--- t3766 = * AND int REG x2 /--* t3766 int N3651 ( 21, 15) [000229] ---XGO----- * JTRUE void REG NA $301 ------------ BB251 [7E9..7FF), preds={BB249} succs={BB253} N3655 (???,???) [003943] ----------- IL_OFFSET void INLRT @ 0x7E9[E-] REG NA N3657 (???,???) [003944] ----------- IL_OFFSET void INLRT @ 0x7F2[E-] REG NA N3659 ( 1, 1) [000238] ----------- t238 = LCL_VAR ref V03 arg3 u:1 x20 (last use) REG x20 $180 /--* t238 ref N3661 ( 3, 4) [003155] -c--------- t3155 = * LEA(b+40) byref REG NA /--* t3155 byref N3663 ( 4, 3) [002541] ---XG------ t2541 = * IND ref REG x2 /--* t2541 ref N3665 (???,???) [004227] ---XG------ t4227 = * PUTARG_REG ref REG x2 N3667 ( 1, 1) [000236] ----------- t236 = LCL_VAR byref V00 arg0 u:1 x19 (last use) REG x19 $100 /--* t236 byref N3669 (???,???) [004228] ----------- t4228 = * PUTARG_REG byref REG x0 N3671 ( 2, 8) [003153] H---------- t3153 = CNS_INT(h) long 0x4000000000540210 ftn REG x11 $51 /--* t3153 long N3673 (???,???) [004229] ----------- t4229 = * PUTARG_REG long REG x11 N3675 ( 1, 2) [000237] ----------- t237 = CNS_INT int 0 REG x1 $c0 /--* t237 int N3677 (???,???) [004230] ----------- t4230 = * PUTARG_REG int REG x1 /--* t4227 ref arg3 in x2 +--* t4228 byref this in x0 +--* t4229 long r2r cell in x11 +--* t4230 int arg2 in x1 N3679 ( 22, 20) [000241] --CXG------ * CALL r2r_ind void REG NA $VN.Void ------------ BB253 [7FF..800) (return), preds={BB248,BB249,BB251} succs={} N3683 (???,???) [003945] ----------- IL_OFFSET void INLRT @ 0x7FF[E-] REG NA N3685 ( 0, 0) [000220] ----------- RETURN void REG NA $VN.Void ------------ BB111 [3DC..3DD) -> BB112 (always), preds={BB107} succs={BB112} N001 ( 1, 1) [004395] ----------Z t4395 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004396] ----------Z t4396 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004397] ----------Z t4397 = LCL_VAR int V144 tmp104 x8 REG x8 N1665 (???,???) [003946] ----------- IL_OFFSET void INL26 @ 0x040[E-] <- INLRT @ 0x3DC[E-] REG NA N1667 ( 1, 1) [001744] ----------- t1744 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1744 byref N1669 (???,???) [004231] ----------- t4231 = * PUTARG_REG byref REG x0 N1671 ( 1, 1) [001745] ----------- t1745 = LCL_VAR ref V86 tmp46 u:1 x11 (last use) REG x11 /--* t1745 ref N1673 (???,???) [004232] ----------- t4232 = * PUTARG_REG ref REG x1 N1675 ( 2, 8) [002780] H---------- t2780 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2780 long N1677 (???,???) [004233] ----------- t4233 = * PUTARG_REG long REG x11 /--* t4231 byref this in x0 +--* t4232 ref arg2 in x1 +--* t4233 long r2r cell in x11 N1679 ( 18, 15) [001746] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004398] ----------z t4398 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004399] ----------z t4399 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004400] ----------z t4400 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB113 [401..406) -> BB263 (cond), preds={BB247} succs={BB114,BB263} N1787 (???,???) [003947] ----------- IL_OFFSET void INLRT @ 0x401[E-] REG NA N1789 ( 1, 1) [000271] ----------- t271 = LCL_VAR int V14 loc10 u:2 x3 REG x3 $2ab N1791 ( 1, 2) [000272] -c--------- t272 = CNS_INT int 0 REG NA $c0 /--* t271 int +--* t272 int N1793 ( 3, 4) [000273] J------N--- * LE void REG NA $89f N1795 ( 5, 6) [000274] ----------- * JTRUE void REG NA $VN.Void ------------ BB114 [406..40C) -> BB135 (cond), preds={BB113} succs={BB115,BB135} N1799 (???,???) [003948] ----------- IL_OFFSET void INLRT @ 0x406[E-] REG NA N1801 ( 1, 1) [000821] ----------- t821 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1803 ( 1, 2) [000822] -c--------- t822 = CNS_INT int 35 REG NA $ea /--* t821 int +--* t822 int N1805 ( 6, 4) [000823] -c-----N--- t823 = * EQ int REG NA N1807 ( 1, 1) [000919] ----------- t919 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1809 ( 1, 2) [000920] ----------- t920 = CNS_INT int 46 REG x11 $eb /--* t919 int +--* t920 int N1811 ( 6, 4) [000921] -c-----N--- t921 = * EQ int REG NA /--* t823 int +--* t921 int N1813 ( 13, 9) [003738] Jc-----N--- * AND void REG NA N1815 ( 15, 11) [000824] ----------- * JTRUE void REG NA $VN.Void ------------ BB115 [40C..418) -> BB264 (cond), preds={BB114} succs={BB117,BB264} N1819 (???,???) [003949] ----------- IL_OFFSET void INLRT @ 0x40C[E-] REG NA N1821 (???,???) [003950] ----------- IL_OFFSET void INLRT @ 0x412[E-] REG NA N1823 ( 1, 1) [000923] ----------Z t923 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N1825 ( 1, 2) [000924] -c--------- t924 = CNS_INT int 48 REG NA $d8 /--* t923 int +--* t924 int N1827 ( 3, 4) [000925] J------N--- * EQ void REG NA N1829 ( 5, 6) [000926] ----------- * JTRUE void REG NA $VN.Void ------------ BB117 [418..41A) -> BB136 (always), preds={BB115} succs={BB136} N001 ( 1, 1) [004401] ----------Z t4401 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004402] ----------z t4402 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB264 [???..???) -> BB135 (always), preds={BB115} succs={BB135} N001 ( 1, 1) [004332] ----------z t4332 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB263 [???..???) -> BB136 (always), preds={BB113} succs={BB136} N001 ( 1, 1) [004331] ----------Z t4331 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB118 [41A..420) -> BB120 (cond), preds={BB135} succs={BB119,BB120} N1847 (???,???) [003951] ----------- IL_OFFSET void INLRT @ 0x41A[E-] REG NA N1849 ( 1, 1) [000830] ----------- t830 = LCL_VAR long V36 loc32 u:7 x0 REG x0 $904 /--* t830 long N1851 ( 4, 3) [000831] ---XG------ t831 = * IND ubyte REG x11 /--* t831 ubyte N1853 ( 4, 3) [003678] DA-XG------ * STORE_LCL_VAR int V177 cse6 d:1 x11 REG x11 N1855 ( 1, 1) [003679] ----------- t3679 = LCL_VAR int V177 cse6 u:1 x11 REG x11 N1857 ( 1, 2) [000832] -c--------- t832 = CNS_INT int 0 REG NA $c0 /--* t3679 int +--* t832 int N1859 ( 7, 7) [000833] CNE---XG--N--- * JCMP void REG NA ------------ BB119 [420..424) -> BB121 (always), preds={BB118} succs={BB121} N1863 ( 1, 2) [000912] ----------- t912 = CNS_INT int 48 REG x14 $d8 /--* t912 int N1865 ( 1, 3) [000917] DA--------- * STORE_LCL_VAR int V63 tmp23 d:3 x14 REG x14 ------------ BB120 [424..42C), preds={BB118} succs={BB121} N1869 ( 1, 1) [000840] ----------- t840 = LCL_VAR long V36 loc32 u:7 x0 (last use) REG x0 $904 /--* t840 long N1871 ( 1, 3) [000848] DA--------- * STORE_LCL_VAR long V61 tmp21 d:1 x0 REG x0 N1873 ( 1, 1) [000841] ----------- t841 = LCL_VAR long V61 tmp21 u:1 x0 (last use) REG x0 $904 N1875 ( 1, 2) [000843] -c--------- t843 = CNS_INT long 1 REG NA $204 /--* t841 long +--* t843 long N1877 ( 3, 4) [000844] ----------- t844 = * ADD long REG x0 $adc /--* t844 long N1879 ( 3, 4) [000846] DA--------- * STORE_LCL_VAR long V36 loc32 d:9 NA REG NA N1881 ( 1, 1) [003681] ----------- t3681 = LCL_VAR int V177 cse6 u:1 x11 (last use) REG x11 /--* t3681 int N1883 ( 1, 3) [000855] DA--G------ * STORE_LCL_VAR int V63 tmp23 d:2 x14 REG x14 N001 ( 1, 1) [004403] ----------z t4403 = LCL_VAR long V36 loc32 x0 REG x0 ------------ BB121 [000..435) -> BB123 (cond), preds={BB119,BB120} succs={BB122,BB123} N1887 ( 1, 1) [000858] ----------- t858 = LCL_VAR int V63 tmp23 u:1 x14 (last use) REG x14 $b16 /--* t858 int N1889 ( 2, 3) [001796] ----------- t1796 = * CAST int <- ushort <- int REG x11 $c75 /--* t1796 int N1891 ( 2, 3) [001836] DA--------- * STORE_LCL_VAR int V92 tmp52 d:1 x11 REG x11 N1893 (???,???) [003952] ----------- IL_OFFSET void INL29 @ 0x000[E-] <- INLRT @ ??? REG NA N1895 ( 1, 1) [000857] ----------- t857 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t857 byref N1897 ( 3, 4) [002795] -c--------- t2795 = * LEA(b+8) byref REG NA /--* t2795 byref N1899 ( 4, 3) [001797] ---XG------ t1797 = * IND int REG x14 /--* t1797 int N1901 ( 4, 3) [001799] DA-XG------ * STORE_LCL_VAR int V91 tmp51 d:1 x14 REG x14 N1903 (???,???) [003953] ----------- IL_OFFSET void INL29 @ 0x007[E-] <- INLRT @ ??? REG NA N1905 ( 1, 1) [001800] ----------- t1800 = LCL_VAR int V91 tmp51 u:1 x14 REG x14 N1907 ( 1, 1) [001801] ----------- t1801 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1801 byref N1909 ( 3, 4) [002799] -c--------- t2799 = * LEA(b+24) byref REG NA /--* t2799 byref N1911 ( 4, 3) [001839] n---GO----- t1839 = * IND int REG x12 /--* t1800 int +--* t1839 int N1913 ( 6, 5) [001805] N---GO-N-U- * GE void REG NA N1915 ( 8, 7) [001806] ----GO----- * JTRUE void REG NA $845 ------------ BB122 [000..000) -> BB124 (always), preds={BB121} succs={BB124} N1919 (???,???) [003954] ----------- IL_OFFSET void INL29 @ 0x015[E-] <- INLRT @ ??? REG NA N1921 ( 1, 1) [002803] ----------- t2803 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N1923 ( 1, 2) [002804] -c--------- t2804 = CNS_INT long 16 REG NA $200 /--* t2803 byref +--* t2804 long N1925 ( 3, 4) [002805] -----O----- t2805 = * ADD byref REG x12 $25c /--* t2805 byref N1927 ( 3, 4) [001815] DA--GO----- * STORE_LCL_VAR byref V93 tmp53 d:1 x12 REG x12 N1929 ( 1, 1) [001812] ----------- t1812 = LCL_VAR int V91 tmp51 u:1 x14 REG x14 N1931 ( 1, 1) [001817] ----------- t1817 = LCL_VAR byref V93 tmp53 u:1 x12 REG x12 $25c /--* t1817 byref N1933 ( 3, 4) [002808] -c--------- t2808 = * LEA(b+8) byref REG NA /--* t2808 byref N1935 ( 4, 3) [001818] n---GO----- t1818 = * IND int REG x15 /--* t1812 int +--* t1818 int N1937 ( 9, 11) [001819] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N1939 ( 1, 1) [001816] ----------- t1816 = LCL_VAR byref V93 tmp53 u:1 x12 (last use) REG x12 $25c /--* t1816 byref N1941 ( 3, 2) [001823] n---GO----- t1823 = * IND byref REG x12 N1943 ( 1, 1) [001813] ----------- t1813 = LCL_VAR int V91 tmp51 u:1 x14 REG x14 /--* t1813 int N1945 ( 2, 3) [001820] -c-------U- t1820 = * CAST long <- uint REG NA N1947 ( 1, 2) [001821] -c--------- t1821 = CNS_INT long 1 REG NA $204 /--* t1820 long +--* t1821 long N1949 ( 4, 6) [001822] -c--------- t1822 = * BFIZ long REG NA /--* t1823 byref +--* t1822 long N1951 ( 8, 9) [001824] -c--------- t1824 = * LEA(b+(i*1)+0) byref REG NA N1953 ( 1, 1) [001826] ----------- t1826 = LCL_VAR int V92 tmp52 u:1 x11 (last use) REG x11 $c75 /--* t1824 byref +--* t1826 int N1955 (???,???) [003955] -A-XGO----- * STOREIND short REG NA N1957 (???,???) [003956] ----------- IL_OFFSET void INL29 @ 0x023[E-] <- INLRT @ ??? REG NA N1959 ( 1, 1) [001830] ----------- t1830 = LCL_VAR int V91 tmp51 u:1 x14 (last use) REG x14 N1961 ( 1, 2) [001831] -c--------- t1831 = CNS_INT int 1 REG NA $c1 /--* t1830 int +--* t1831 int N1963 ( 3, 4) [001832] ----------- t1832 = * ADD int REG x11 N1965 ( 1, 1) [001829] ----------- t1829 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1829 byref N1967 ( 3, 4) [002811] -c--------- t2811 = * LEA(b+8) byref REG NA /--* t2811 byref +--* t1832 int N1969 (???,???) [003957] -A--GO----- * STOREIND int REG NA ------------ BB123 [000..000), preds={BB121} succs={BB124} N001 ( 1, 1) [004404] ----------Z t4404 = LCL_VAR ushort V18 loc14 x13 REG x13 N001 ( 1, 1) [004405] ----------Z t4405 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004406] ----------Z t4406 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004407] ----------Z t4407 = LCL_VAR int V144 tmp104 x8 REG x8 N1973 (???,???) [003958] ----------- IL_OFFSET void INL29 @ 0x02D[E-] <- INLRT @ ??? REG NA N1975 ( 1, 1) [001807] ----------- t1807 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1807 byref N1977 (???,???) [004234] ----------- t4234 = * PUTARG_REG byref REG x0 N1979 ( 1, 1) [001808] ----------- t1808 = LCL_VAR int V92 tmp52 u:1 x11 (last use) REG x11 $c75 /--* t1808 int N1981 (???,???) [004235] ----------- t4235 = * PUTARG_REG int REG x1 N1983 ( 2, 8) [002812] H---------- t2812 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t2812 long N1985 (???,???) [004236] ----------- t4236 = * PUTARG_REG long REG x11 /--* t4234 byref this in x0 +--* t4235 int arg2 in x1 +--* t4236 long r2r cell in x11 N1987 ( 18, 15) [001809] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004408] ----------z t4408 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004409] ----------z t4409 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004410] ----------z t4410 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004411] ----------z t4411 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB124 [???..???) -> BB134 (cond), preds={BB122,BB123} succs={BB125,BB134} N1991 (???,???) [003959] ----------- IL_OFFSET void INLRT @ 0x431[E-] REG NA N1993 ( 1, 1) [000860] ----------z t860 = LCL_VAR int V12 loc8 u:3 x7 REG x7 $4c4 N1995 ( 1, 2) [000861] -c--------- t861 = CNS_INT int 0 REG NA $c0 /--* t860 int +--* t861 int N1997 ( 6, 4) [000862] -c-----N--- t862 = * EQ int REG NA $70a N1999 ( 1, 1) [000874] ----------z t874 = LCL_VAR int V08 loc4 u:5 x2 REG x2 $b15 N2001 ( 1, 2) [000875] -c--------- t875 = CNS_INT int 1 REG NA $c1 /--* t874 int +--* t875 int N2003 ( 6, 4) [000876] -c-----N--- t876 = * LE int REG NA $d03 /--* t862 int +--* t876 int N2005 ( 13, 9) [003740] Jc-----N--- * AND void REG NA N2007 ( 15, 11) [000863] ----------- * JTRUE void REG NA $VN.Void ------------ BB125 [435..43F) -> BB265 (cond), preds={BB124} succs={BB127,BB265} N2011 (???,???) [003960] ----------- IL_OFFSET void INLRT @ 0x435[E-] REG NA N2013 (???,???) [003961] ----------- IL_OFFSET void INLRT @ 0x43A[E-] REG NA N2015 ( 1, 1) [000885] ----------- t885 = LCL_VAR int V20 loc16 u:7 x9 REG x9 $b13 N2017 ( 1, 1) [000889] ----------Z t889 = LCL_VAR int V144 tmp104 u:2 x8 REG x8 $2a6 /--* t885 int +--* t889 int N2019 ( 6, 9) [000890] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $c31 N2021 ( 1, 1) [000894] ----------z t894 = LCL_VAR byref V143 tmp103 u:2 x6 REG x6 $385 N2023 ( 1, 1) [000886] ----------- t886 = LCL_VAR int V20 loc16 u:7 x9 REG x9 $b13 /--* t886 int N2025 ( 2, 3) [000891] -c-------U- t891 = * CAST long <- uint REG NA $ae2 N2027 ( 1, 2) [000892] -c--------- t892 = CNS_INT long 2 REG NA $20a /--* t891 long +--* t892 long N2029 ( 4, 6) [000893] -c--------- t893 = * BFIZ long REG NA /--* t894 byref +--* t893 long N2031 ( 6, 8) [000895] -c--------- t895 = * LEA(b+(i*1)+0) byref REG NA /--* t895 byref N2033 ( 8, 9) [002813] ---XGO----- t2813 = * IND int REG x11 N2035 ( 1, 2) [000898] -c--------- t898 = CNS_INT int 1 REG NA $c1 /--* t2813 int +--* t898 int N2037 ( 16, 21) [000899] ---XGO----- t899 = * ADD int REG x11 N2039 ( 1, 1) [000882] ----------Z t882 = LCL_VAR int V08 loc4 u:5 x2 REG x2 $b15 /--* t899 int +--* t882 int N2041 ( 21, 23) [000900] Nc-XGO-N-U- t900 = * NE int REG NA N2043 ( 1, 1) [000878] ----------Z t878 = LCL_VAR int V20 loc16 u:7 x9 REG x9 $b13 N2045 ( 1, 2) [000879] -c--------- t879 = CNS_INT int 0 REG NA $c0 /--* t878 int +--* t879 int N2047 ( 6, 4) [000880] -c-----N--- t880 = * LT int REG NA $d04 /--* t900 int +--* t880 int N2049 ( 28, 28) [003742] Jc-XGO-N--- * AND void REG NA N2051 ( 30, 30) [000881] ---XGO----- * JTRUE void REG NA $VN.Void ------------ BB127 [43F..461) -> BB133 (cond), preds={BB125} succs={BB129,BB133} N2055 (???,???) [003962] ----------- IL_OFFSET void INLRT @ 0x43F[E-] REG NA N2057 (???,???) [003963] ----------- IL_OFFSET void INLRT @ 0x44F[E-] REG NA N2059 ( 1, 1) [000903] ----------- t903 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t903 ref N2061 ( 3, 4) [002815] -c--------- t2815 = * LEA(b+56) byref REG NA /--* t2815 byref N2063 ( 4, 3) [001843] ---XG------ t1843 = * IND ref REG x11 /--* t1843 ref N2065 ( 4, 3) [001896] DA-XG------ * STORE_LCL_VAR ref V95 tmp55 d:1 x11 REG x11 N2067 (???,???) [003964] ----------- IL_OFFSET void INL32 @ 0x000[E-] <- INLRT @ 0x44F[E-] REG NA N2069 ( 1, 1) [001845] ----------- t1845 = LCL_VAR ref V95 tmp55 u:1 x11 REG x11 N2071 ( 1, 2) [001846] -c--------- t1846 = CNS_INT ref null REG NA $VN.Null /--* t1845 ref +--* t1846 ref N2073 ( 3, 4) [001847] CEQ-------N--- * JCMP void REG NA ------------ BB129 [44F..450) -> BB132 (cond), preds={BB127} succs={BB130,BB132} N2077 (???,???) [003965] ----------- IL_OFFSET void INL32 @ 0x004[E-] <- INLRT @ 0x44F[E-] REG NA N2079 ( 1, 1) [000902] ----------- t902 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t902 byref N2081 ( 3, 4) [002817] -c--------- t2817 = * LEA(b+8) byref REG NA /--* t2817 byref N2083 ( 4, 3) [001849] n---GO----- t1849 = * IND int REG x14 /--* t1849 int N2085 ( 4, 3) [001851] DA--GO----- * STORE_LCL_VAR int V96 tmp56 d:1 x14 REG x14 N2087 (???,???) [003966] ----------- IL_OFFSET void INL32 @ 0x00B[E-] <- INLRT @ 0x44F[E-] REG NA N2089 ( 1, 1) [001852] ----------- t1852 = LCL_VAR ref V95 tmp55 u:1 x11 REG x11 /--* t1852 ref N2091 (???,???) [004168] -c--------- t4168 = * LEA(b+8) byref REG NA /--* t4168 byref N2093 ( 3, 3) [001853] ---X------- t1853 = * IND int REG x12 /--* t1853 int N2095 ( 3, 3) [003716] DA-X------- * STORE_LCL_VAR int V181 cse10 d:1 x12 REG x12 N2097 ( 1, 1) [003717] ----------- t3717 = LCL_VAR int V181 cse10 u:1 x12 REG x12 N2099 ( 1, 2) [001854] -c--------- t1854 = CNS_INT int 1 REG NA $c1 /--* t3717 int +--* t1854 int N2101 ( 9, 7) [001855] Nc-X---N-U- t1855 = * NE int REG NA N2103 ( 1, 1) [001860] ----------- t1860 = LCL_VAR int V96 tmp56 u:1 x14 REG x14 N2105 ( 1, 1) [001861] ----------- t1861 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1861 byref N2107 ( 3, 4) [002821] -c--------- t2821 = * LEA(b+24) byref REG NA /--* t2821 byref N2109 ( 4, 3) [001899] n---GO----- t1899 = * IND int REG x15 /--* t1860 int +--* t1899 int N2111 ( 9, 5) [001865] Nc--GO-N-U- t1865 = * GE int REG NA /--* t1855 int +--* t1865 int N2113 ( 19, 13) [003744] Jc-XGO-N--- * AND void REG NA N2115 ( 21, 15) [001856] ---XGO----- * JTRUE void REG NA ------------ BB130 [44F..450) -> BB133 (always), preds={BB129} succs={BB133} N2119 (???,???) [003967] ----------- IL_OFFSET void INL32 @ 0x014[E-] <- INLRT @ 0x44F[E-] REG NA N2121 (???,???) [003968] ----------- IL_OFFSET void INL32 @ 0x022[E-] <- INLRT @ 0x44F[E-] REG NA N2123 ( 1, 1) [002825] ----------- t2825 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N2125 ( 1, 2) [002826] -c--------- t2826 = CNS_INT long 16 REG NA $200 /--* t2825 byref +--* t2826 long N2127 ( 3, 4) [002827] -----O----- t2827 = * ADD byref REG x15 $25c /--* t2827 byref N2129 ( 3, 4) [001872] DA--GO----- * STORE_LCL_VAR byref V97 tmp57 d:1 x15 REG x15 N2131 (???,???) [003969] ----------- IL_OFFSET void INL32 @ ??? <- INLRT @ 0x44F[E-] REG NA N2133 ( 1, 1) [001869] ----------- t1869 = LCL_VAR int V96 tmp56 u:1 x14 REG x14 N2135 ( 1, 1) [001874] ----------- t1874 = LCL_VAR byref V97 tmp57 u:1 x15 REG x15 $25c /--* t1874 byref N2137 ( 3, 4) [002830] -c--------- t2830 = * LEA(b+8) byref REG NA /--* t2830 byref N2139 ( 4, 3) [001875] n---GO----- t1875 = * IND int REG xip0 /--* t1869 int +--* t1875 int N2141 ( 9, 11) [001876] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2143 ( 1, 1) [001873] ----------- t1873 = LCL_VAR byref V97 tmp57 u:1 x15 (last use) REG x15 $25c /--* t1873 byref N2145 ( 3, 2) [001880] n---GO----- t1880 = * IND byref REG x15 N2147 ( 1, 1) [001870] ----------- t1870 = LCL_VAR int V96 tmp56 u:1 x14 REG x14 /--* t1870 int N2149 ( 2, 3) [001877] -c-------U- t1877 = * CAST long <- uint REG NA N2151 ( 1, 2) [001878] -c--------- t1878 = CNS_INT long 1 REG NA $204 /--* t1877 long +--* t1878 long N2153 ( 4, 6) [001879] ----------- t1879 = * BFIZ long REG xip0 /--* t1880 byref +--* t1879 long N2155 ( 8, 9) [001881] ----GO-N--- t1881 = * ADD byref REG x15 N2157 ( 1, 2) [001884] -c--------- t1884 = CNS_INT int 0 REG NA $c0 N2159 ( 1, 1) [003719] ----------- t3719 = LCL_VAR int V181 cse10 u:1 x12 (last use) REG x12 /--* t1884 int +--* t3719 int N2161 ( 6, 10) [002835] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2163 ( 1, 1) [002832] ----------- t2832 = LCL_VAR ref V95 tmp55 u:1 x11 (last use) REG x11 /--* t2832 ref N2165 ( 1, 1) [002839] -c--------- t2839 = * LEA(b+12) byref REG NA /--* t2839 byref N2167 ( 5, 4) [002844] n---GO----- t2844 = * IND ushort REG x11 /--* t1881 byref +--* t2844 ushort N2169 (???,???) [003970] -A-XGO----- * STOREIND short REG NA N2171 (???,???) [003971] ----------- IL_OFFSET void INL32 @ 0x036[E-] <- INLRT @ 0x44F[E-] REG NA N2173 ( 1, 1) [001890] ----------- t1890 = LCL_VAR int V96 tmp56 u:1 x14 (last use) REG x14 N2175 ( 1, 2) [001891] -c--------- t1891 = CNS_INT int 1 REG NA $c1 /--* t1890 int +--* t1891 int N2177 ( 3, 4) [001892] ----------- t1892 = * ADD int REG x11 N2179 ( 1, 1) [001889] ----------- t1889 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1889 byref N2181 ( 3, 4) [002846] -c--------- t2846 = * LEA(b+8) byref REG NA /--* t2846 byref +--* t1892 int N2183 (???,???) [003972] -A--GO----- * STOREIND int REG NA ------------ BB265 [???..???) -> BB134 (always), preds={BB125} succs={BB134} N001 ( 1, 1) [004333] ----------z t4333 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004334] ----------z t4334 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004335] ----------z t4335 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB132 [44F..450), preds={BB129} succs={BB133} N001 ( 1, 1) [004412] ----------Z t4412 = LCL_VAR ushort V18 loc14 x13 REG x13 N001 ( 1, 1) [004413] ----------Z t4413 = LCL_VAR long V36 loc32 x0 REG x0 N2187 (???,???) [003973] ----------- IL_OFFSET void INL32 @ 0x040[E-] <- INLRT @ 0x44F[E-] REG NA N2189 ( 1, 1) [001857] ----------- t1857 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1857 byref N2191 (???,???) [004237] ----------- t4237 = * PUTARG_REG byref REG x0 N2193 ( 1, 1) [001858] ----------- t1858 = LCL_VAR ref V95 tmp55 u:1 x11 (last use) REG x11 /--* t1858 ref N2195 (???,???) [004238] ----------- t4238 = * PUTARG_REG ref REG x1 N2197 ( 2, 8) [002847] H---------- t2847 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2847 long N2199 (???,???) [004239] ----------- t4239 = * PUTARG_REG long REG x11 /--* t4237 byref this in x0 +--* t4238 ref arg2 in x1 +--* t4239 long r2r cell in x11 N2201 ( 18, 15) [001859] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004414] ----------z t4414 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004415] ----------z t4415 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB133 [???..???), preds={BB127,BB130,BB132} succs={BB134} N2205 (???,???) [003974] ----------- IL_OFFSET void INLRT @ 0x45B[E-] REG NA N2207 ( 1, 1) [000907] ----------z t907 = LCL_VAR int V20 loc16 u:7 x9 (last use) REG x9 $b13 N2209 ( 1, 2) [000908] -c--------- t908 = CNS_INT int -1 REG NA $c4 /--* t907 int +--* t908 int N2211 ( 3, 4) [000909] ----------- t909 = * ADD int REG x9 $d27 /--* t909 int N2213 ( 3, 4) [000911] DA--------- * STORE_LCL_VAR int V20 loc16 d:9 NA REG NA N001 ( 1, 1) [004416] ----------z t4416 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004417] ----------z t4417 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004418] ----------z t4418 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB134 [461..46D), preds={BB124,BB133,BB265} succs={BB135} N2217 (???,???) [003975] ----------- IL_OFFSET void INLRT @ 0x461[E-] REG NA N2219 ( 1, 1) [000864] ----------- t864 = LCL_VAR int V08 loc4 u:5 x2 (last use) REG x2 $b15 N2221 ( 1, 2) [000865] -c--------- t865 = CNS_INT int -1 REG NA $c4 /--* t864 int +--* t865 int N2223 ( 3, 4) [000866] ----------- t866 = * ADD int REG x2 $d29 /--* t866 int N2225 ( 3, 4) [000868] DA--------- * STORE_LCL_VAR int V08 loc4 d:6 NA REG NA N2227 (???,???) [003976] ----------- IL_OFFSET void INLRT @ 0x467[E-] REG NA N2229 ( 1, 1) [000869] ----------z t869 = LCL_VAR int V14 loc10 u:6 x3 (last use) REG x3 $b14 N2231 ( 1, 2) [000870] -c--------- t870 = CNS_INT int -1 REG NA $c4 /--* t869 int +--* t870 int N2233 ( 3, 4) [000871] ----------- t871 = * ADD int REG x3 $d2a /--* t871 int N2235 ( 3, 4) [000873] DA--------- * STORE_LCL_VAR int V14 loc10 d:7 NA REG NA N001 ( 1, 1) [004419] ----------z t4419 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB135 [46D..472) -> BB118 (cond), preds={BB114,BB134,BB264} succs={BB136,BB118} N1835 (???,???) [003977] ----------- IL_OFFSET void INLRT @ 0x46D[E-] REG NA N1837 ( 1, 1) [000825] ----------Z t825 = LCL_VAR int V14 loc10 u:6 x3 REG x3 $b14 N1839 ( 1, 2) [000826] -c--------- t826 = CNS_INT int 0 REG NA $c0 /--* t825 int +--* t826 int N1841 ( 3, 4) [000827] J------N--- * GT void REG NA $c6e N1843 ( 5, 6) [000828] ----------- * JTRUE void REG NA $VN.Void ------------ BB136 [472..478) -> BB141 (cond), preds={BB117,BB135,BB263} succs={BB137,BB141} N2239 (???,???) [003978] ----------- IL_OFFSET void INLRT @ 0x472[E-] REG NA N2241 ( 1, 1) [000275] ----------- t275 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2243 ( 1, 2) [000276] -c--------- t276 = CNS_INT int 69 REG NA $d2 /--* t275 int +--* t276 int N2245 ( 3, 4) [000277] N------N-U- * GT void REG NA N2247 ( 5, 6) [000278] ----------- * JTRUE void REG NA $VN.Void ------------ BB137 [478..478) -> BB138 (cond), preds={BB136} succs={BB257,BB138} N2251 (???,???) [003979] ----------- IL_OFFSET void INLRT @ 0x478[E-] REG NA N2253 ( 1, 1) [000593] ----------- t593 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2255 ( 1, 2) [000594] -c--------- t594 = CNS_INT int -34 REG NA $d6 /--* t593 int +--* t594 int N2257 ( 3, 4) [000595] ----------- t595 = * ADD int REG x14 /--* t595 int N2259 (???,???) [004241] DA--------- * STORE_LCL_VAR int V184 rat2 x14 REG x14 N2261 ( 3, 2) [004243] ----------- t4243 = LCL_VAR int V184 rat2 x14 REG x14 N2263 ( 1, 2) [004244] -c--------- t4244 = CNS_INT int 5 REG NA /--* t4243 int +--* t4244 int N2265 ( 8, 5) [004245] ---------U- * GT void REG NA N2267 ( 10, 7) [004246] ----------- * JTRUE void REG NA ------------ BB257 [478..49A) -> BB194,BB145,BB242,BB186,BB242,BB194 (switch), preds={BB137} succs={BB145,BB186,BB194,BB242} N3937 (???,???) [004247] ----------- t4247 = LCL_VAR int V184 rat2 x14 (last use) REG x14 /--* t4247 int N3939 (???,???) [004248] ---------U- t4248 = * CAST long <- ulong <- uint REG x11 N3941 (???,???) [004249] ----------- t4249 = JMPTABLE long REG x14 /--* t4248 long +--* t4249 long N3943 (???,???) [004250] ----------- * SWITCH_TABLE void REG NA ------------ BB138 [49A..49A) -> BB139 (cond), preds={BB137} succs={BB258,BB139} N2271 (???,???) [003980] ----------- IL_OFFSET void INLRT @ 0x49A[E-] REG NA N2273 ( 1, 1) [000597] ----------- t597 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2275 ( 1, 2) [000598] -c--------- t598 = CNS_INT int -44 REG NA $d7 /--* t597 int +--* t598 int N2277 ( 3, 4) [000599] ----------- t599 = * ADD int REG x12 /--* t599 int N2279 (???,???) [004252] DA--------- * STORE_LCL_VAR int V185 rat3 x12 REG x12 N2281 ( 3, 2) [004254] ----------- t4254 = LCL_VAR int V185 rat3 x12 REG x12 N2283 ( 1, 2) [004255] -c--------- t4255 = CNS_INT int 4 REG NA /--* t4254 int +--* t4255 int N2285 ( 8, 5) [004256] ---------U- * GT void REG NA N2287 ( 10, 7) [004257] ----------- * JTRUE void REG NA ------------ BB258 [49A..4B8) -> BB266,BB242,BB171,BB242,BB145 (switch), preds={BB138} succs={BB145,BB171,BB242,BB266} N4791 (???,???) [004258] ----------- t4258 = LCL_VAR int V185 rat3 x12 (last use) REG x12 /--* t4258 int N4793 (???,???) [004259] ---------U- t4259 = * CAST long <- ulong <- uint REG x11 N4795 (???,???) [004260] ----------- t4260 = JMPTABLE long REG x14 /--* t4259 long +--* t4260 long N4797 (???,???) [004261] ----------- * SWITCH_TABLE void REG NA ------------ BB266 [???..???) -> BB245 (always), preds={BB258} succs={BB245} N001 ( 1, 1) [004336] ----------z t4336 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB139 [4B8..4C1) -> BB205 (cond), preds={BB138} succs={BB140,BB205} N2291 (???,???) [003981] ----------- IL_OFFSET void INLRT @ 0x4B8[E-] REG NA N2293 ( 1, 1) [000601] ----------- t601 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2295 ( 1, 2) [000602] -c--------- t602 = CNS_INT int 69 REG NA $d2 /--* t601 int +--* t602 int N2297 ( 3, 4) [000603] J------N--- * EQ void REG NA N2299 ( 5, 6) [000604] ----------- * JTRUE void REG NA $VN.Void ------------ BB140 [4C1..4C6) -> BB242 (always), preds={BB139} succs={BB242} ------------ BB141 [4C6..4CF) -> BB200 (cond), preds={BB136} succs={BB142,BB200} N2305 (???,???) [003982] ----------- IL_OFFSET void INLRT @ 0x4C6[E-] REG NA N2307 ( 1, 1) [000279] ----------- t279 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2309 ( 1, 2) [000280] -c--------- t280 = CNS_INT int 92 REG NA $d3 /--* t279 int +--* t280 int N2311 ( 3, 4) [000281] J------N--- * EQ void REG NA N2313 ( 5, 6) [000282] ----------- * JTRUE void REG NA $VN.Void ------------ BB142 [4CF..4D8) -> BB205 (cond), preds={BB141} succs={BB143,BB205} N2317 (???,???) [003983] ----------- IL_OFFSET void INLRT @ 0x4CF[E-] REG NA N2319 ( 1, 1) [000319] ----------- t319 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2321 ( 1, 2) [000320] -c--------- t320 = CNS_INT int 101 REG NA $d4 /--* t319 int +--* t320 int N2323 ( 3, 4) [000321] J------N--- * EQ void REG NA N2325 ( 5, 6) [000322] ----------- * JTRUE void REG NA $VN.Void ------------ BB143 [4D8..4E4) -> BB242 (cond), preds={BB142} succs={BB144,BB242} N2329 (???,???) [003984] ----------- IL_OFFSET void INLRT @ 0x4D8[E-] REG NA N2331 ( 1, 1) [000581] ----------- t581 = LCL_VAR int V18 loc14 u:1 x13 REG x13 N2333 ( 1, 4) [000582] ----------- t582 = CNS_INT int 0x2030 REG x11 $d5 /--* t581 int +--* t582 int N2335 ( 3, 6) [000583] J------N--- * NE void REG NA N2337 ( 5, 8) [000584] ----------- * JTRUE void REG NA $VN.Void ------------ BB144 [598..5A9) -> BB181 (always), preds={BB143} succs={BB181} N2341 (???,???) [003985] ----------- IL_OFFSET void INLRT @ 0x598[E-] REG NA N2343 ( 1, 1) [000586] ----------- t586 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t586 ref N2345 ( 3, 4) [002849] -c--------- t2849 = * LEA(b+136) byref REG NA /--* t2849 byref N2347 ( 4, 3) [002066] ---XG------ t2066 = * IND ref REG x11 /--* t2066 ref N2349 ( 4, 3) [002119] DA-XG------ * STORE_LCL_VAR ref V110 tmp70 d:1 x11 REG x11 ------------ BB145 [4E9..4EE) -> BB150 (cond), preds={BB257,BB258} succs={BB146,BB150} N3947 (???,???) [003986] ----------- IL_OFFSET void INLRT @ 0x4E9[E-] REG NA N3949 ( 1, 1) [000639] ----------z t639 = LCL_VAR int V14 loc10 u:3 x3 REG x3 $2b4 N3951 ( 1, 2) [000640] -c--------- t640 = CNS_INT int 0 REG NA $c0 /--* t639 int +--* t640 int N3953 ( 3, 4) [000641] J------N--- * GE void REG NA $9ff N3955 ( 5, 6) [000642] ----------- * JTRUE void REG NA $VN.Void ------------ BB146 [4EE..4F9) -> BB148 (cond), preds={BB145} succs={BB147,BB148} N3959 (???,???) [003987] ----------- IL_OFFSET void INLRT @ 0x4EE[E-] REG NA N3961 ( 1, 1) [000731] ----------- t731 = LCL_VAR int V14 loc10 u:3 x3 (last use) REG x3 $2b4 N3963 ( 1, 2) [000732] -c--------- t732 = CNS_INT int 1 REG NA $c1 /--* t731 int +--* t732 int N3965 ( 3, 4) [000733] ----------- t733 = * ADD int REG x3 $a88 /--* t733 int N3967 ( 3, 4) [000735] DA--------- * STORE_LCL_VAR int V14 loc10 d:5 NA REG NA N3969 (???,???) [003988] ----------- IL_OFFSET void INLRT @ 0x4F4[E-] REG NA N3971 ( 1, 1) [000736] ----------z t736 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 N3973 ( 1, 1) [000737] ----------- t737 = LCL_VAR int V06 loc2 u:3 x22 REG x22 $292 /--* t736 int +--* t737 int N3975 ( 3, 3) [000738] J------N--- * LE void REG NA $a89 N3977 ( 5, 5) [000739] ----------- * JTRUE void REG NA $VN.Void ------------ BB147 [4F9..4FC) -> BB149 (always), preds={BB146} succs={BB149} N3981 (???,???) [003989] ----------- IL_OFFSET void INLRT @ 0x4F9[E-] REG NA N3983 ( 1, 2) [000747] -c--------- t747 = CNS_INT int 0 REG NA $c0 /--* t747 int N3985 ( 1, 3) [000749] DA--------- * STORE_LCL_VAR int V58 tmp18 d:3 x13 REG x13 ------------ BB148 [4FC..4FE), preds={BB146} succs={BB149} N3989 (???,???) [003990] ----------- IL_OFFSET void INLRT @ 0x4FC[E-] REG NA N3991 ( 1, 2) [000740] ----------- t740 = CNS_INT int 48 REG x13 $d8 /--* t740 int N3993 ( 1, 3) [000742] DA--------- * STORE_LCL_VAR int V58 tmp18 d:2 x13 REG x13 ------------ BB149 [4FE..502) -> BB156 (always), preds={BB147,BB148} succs={BB156} N3997 ( 1, 1) [000744] ----------- t744 = LCL_VAR int V58 tmp18 u:1 x13 (last use) REG x13 $2bd /--* t744 int N3999 ( 2, 3) [002850] ----------- t2850 = * CAST int <- ushort <- int REG x13 $a8a /--* t2850 int N4001 ( 2, 3) [000746] DA--------- * STORE_LCL_VAR int V18 loc14 d:4 x13 REG x13 ------------ BB150 [502..507) -> BB154 (cond), preds={BB145} succs={BB151,BB154} N4005 (???,???) [003991] ----------- IL_OFFSET void INLRT @ 0x502[E-] REG NA N4007 ( 1, 1) [000643] ----------- t643 = LCL_VAR long V36 loc32 u:3 x0 REG x0 $901 /--* t643 long N4009 ( 4, 3) [000644] ---XG------ t644 = * IND ubyte REG x13 N4011 ( 1, 2) [000645] -c--------- t645 = CNS_INT int 0 REG NA $c0 /--* t644 ubyte +--* t645 int N4013 ( 6, 6) [000646] CNE---XG--N--- * JCMP void REG NA ------------ BB151 [507..50C) -> BB153 (cond), preds={BB150} succs={BB152,BB153} N4017 (???,???) [003992] ----------- IL_OFFSET void INLRT @ 0x507[E-] REG NA N4019 ( 1, 1) [000719] ----------z t719 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 N4021 ( 1, 1) [000720] ----------z t720 = LCL_VAR int V07 loc3 u:3 x1 REG x1 $293 /--* t719 int +--* t720 int N4023 ( 3, 3) [000721] J------N--- * GT void REG NA $a86 N4025 ( 5, 5) [000722] ----------- * JTRUE void REG NA $VN.Void ------------ BB152 [50C..50F) -> BB155 (always), preds={BB151} succs={BB155} N4029 (???,???) [003993] ----------- IL_OFFSET void INLRT @ 0x50C[E-] REG NA N4031 ( 1, 2) [000727] -c--------- t727 = CNS_INT int 0 REG NA $c0 /--* t727 int N4033 ( 1, 3) [000729] DA--------- * STORE_LCL_VAR int V57 tmp17 d:4 x11 REG x11 ------------ BB153 [50F..513) -> BB155 (always), preds={BB151} succs={BB155} N4037 (???,???) [003994] ----------- IL_OFFSET void INLRT @ 0x50F[E-] REG NA N4039 ( 1, 2) [000723] ----------- t723 = CNS_INT int 48 REG x11 $d8 /--* t723 int N4041 ( 1, 3) [000725] DA--------- * STORE_LCL_VAR int V57 tmp17 d:3 x11 REG x11 ------------ BB154 [513..51B), preds={BB150} succs={BB155} N4045 (???,???) [003995] ----------- IL_OFFSET void INLRT @ 0x513[E-] REG NA N4047 ( 1, 1) [000648] ----------- t648 = LCL_VAR long V36 loc32 u:3 x0 (last use) REG x0 $901 /--* t648 long N4049 ( 1, 3) [000656] DA--------- * STORE_LCL_VAR long V56 tmp16 d:1 x11 REG x11 N4051 (???,???) [003996] ----------- IL_OFFSET void INLRT @ 0x513[E-] REG NA N4053 ( 1, 1) [000649] ----------- t649 = LCL_VAR long V56 tmp16 u:1 x11 REG x11 $901 N4055 ( 1, 2) [000651] -c--------- t651 = CNS_INT long 1 REG NA $204 /--* t649 long +--* t651 long N4057 ( 3, 4) [000652] ----------- t652 = * ADD long REG x0 $3fb /--* t652 long N4059 ( 3, 4) [000654] DA--------- * STORE_LCL_VAR long V36 loc32 d:6 NA REG NA N4061 ( 1, 1) [000657] ----------- t657 = LCL_VAR long V56 tmp16 u:1 x11 (last use) REG x11 $901 /--* t657 long N4063 ( 4, 3) [000658] ---XG------ t658 = * IND ubyte REG x11 /--* t658 ubyte N4065 ( 4, 3) [000660] DA-XG------ * STORE_LCL_VAR int V57 tmp17 d:2 x11 REG x11 N001 ( 1, 1) [004420] ----------z t4420 = LCL_VAR long V36 loc32 x0 REG x0 ------------ BB155 [51B..51D), preds={BB152,BB153,BB154} succs={BB156} N4069 ( 1, 1) [000662] ----------- t662 = LCL_VAR int V57 tmp17 u:1 x11 (last use) REG x11 $2bc /--* t662 int N4071 ( 2, 3) [002851] ----------- t2851 = * CAST int <- ushort <- int REG x13 $a87 /--* t2851 int N4073 ( 2, 3) [000664] DA--------- * STORE_LCL_VAR int V18 loc14 d:3 x13 REG x13 N001 ( 1, 1) [004421] ----------Z t4421 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004422] ----------z t4422 = LCL_VAR int V08 loc4 x2 REG x2 ------------ BB156 [51D..521) -> BB170 (cond), preds={BB149,BB155} succs={BB157,BB170} N4077 (???,???) [003997] ----------- IL_OFFSET void INLRT @ 0x51D[E-] REG NA N4079 ( 1, 1) [000665] ----------- t665 = LCL_VAR int V18 loc14 u:2 x13 REG x13 $5c9 N4081 ( 1, 2) [000666] -c--------- t666 = CNS_INT int 0 REG NA $c0 /--* t665 int +--* t666 int N4083 ( 3, 4) [000667] CEQ-------N--- * JCMP void REG NA ------------ BB157 [521..52D) -> BB159 (cond), preds={BB156} succs={BB158,BB159} N4087 (???,???) [003998] ----------- IL_OFFSET void INL34 @ 0x000[E-] <- INLRT @ 0x521[E-] REG NA N4089 ( 1, 1) [000674] ----------- t674 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t674 byref N4091 ( 3, 4) [002853] -c--------- t2853 = * LEA(b+8) byref REG NA /--* t2853 byref N4093 ( 4, 3) [001903] ---XG------ t1903 = * IND int REG x11 /--* t1903 int N4095 ( 4, 3) [001905] DA-XG------ * STORE_LCL_VAR int V99 tmp59 d:1 x11 REG x11 N4097 (???,???) [003999] ----------- IL_OFFSET void INL34 @ 0x007[E-] <- INLRT @ 0x521[E-] REG NA N4099 ( 1, 1) [001906] ----------- t1906 = LCL_VAR int V99 tmp59 u:1 x11 REG x11 N4101 ( 1, 1) [001907] ----------- t1907 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1907 byref N4103 ( 3, 4) [002857] -c--------- t2857 = * LEA(b+24) byref REG NA /--* t2857 byref N4105 ( 4, 3) [001942] n---GO----- t1942 = * IND int REG x14 /--* t1906 int +--* t1942 int N4107 ( 6, 5) [001911] N---GO-N-U- * GE void REG NA N4109 ( 8, 7) [001912] ----GO----- * JTRUE void REG NA $845 ------------ BB158 [521..522) -> BB160 (always), preds={BB157} succs={BB160} N4113 (???,???) [004000] ----------- IL_OFFSET void INL34 @ 0x015[E-] <- INLRT @ 0x521[E-] REG NA N4115 ( 1, 1) [002861] ----------- t2861 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4117 ( 1, 2) [002862] -c--------- t2862 = CNS_INT long 16 REG NA $200 /--* t2861 byref +--* t2862 long N4119 ( 3, 4) [002863] -----O----- t2863 = * ADD byref REG x14 $25c /--* t2863 byref N4121 ( 3, 4) [001920] DA--GO----- * STORE_LCL_VAR byref V100 tmp60 d:1 x14 REG x14 N4123 (???,???) [004001] ----------- IL_OFFSET void INL34 @ ??? <- INLRT @ 0x521[E-] REG NA N4125 ( 1, 1) [001917] ----------- t1917 = LCL_VAR int V99 tmp59 u:1 x11 REG x11 N4127 ( 1, 1) [001922] ----------- t1922 = LCL_VAR byref V100 tmp60 u:1 x14 REG x14 $25c /--* t1922 byref N4129 ( 3, 4) [002866] -c--------- t2866 = * LEA(b+8) byref REG NA /--* t2866 byref N4131 ( 4, 3) [001923] n---GO----- t1923 = * IND int REG x12 /--* t1917 int +--* t1923 int N4133 ( 9, 11) [001924] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4135 ( 1, 1) [001921] ----------- t1921 = LCL_VAR byref V100 tmp60 u:1 x14 (last use) REG x14 $25c /--* t1921 byref N4137 ( 3, 2) [001928] n---GO----- t1928 = * IND byref REG x14 N4139 ( 1, 1) [001918] ----------- t1918 = LCL_VAR int V99 tmp59 u:1 x11 REG x11 /--* t1918 int N4141 ( 2, 3) [001925] -c-------U- t1925 = * CAST long <- uint REG NA N4143 ( 1, 2) [001926] -c--------- t1926 = CNS_INT long 1 REG NA $204 /--* t1925 long +--* t1926 long N4145 ( 4, 6) [001927] -c--------- t1927 = * BFIZ long REG NA /--* t1928 byref +--* t1927 long N4147 ( 8, 9) [001929] -c--------- t1929 = * LEA(b+(i*1)+0) byref REG NA N4149 ( 1, 1) [001931] ----------- t1931 = LCL_VAR int V18 loc14 u:2 x13 (last use) REG x13 $5c9 /--* t1929 byref +--* t1931 int N4151 (???,???) [004002] -A-XGO----- * STOREIND short REG NA N4153 (???,???) [004003] ----------- IL_OFFSET void INL34 @ 0x023[E-] <- INLRT @ 0x521[E-] REG NA N4155 ( 1, 1) [001935] ----------- t1935 = LCL_VAR int V99 tmp59 u:1 x11 (last use) REG x11 N4157 ( 1, 2) [001936] -c--------- t1936 = CNS_INT int 1 REG NA $c1 /--* t1935 int +--* t1936 int N4159 ( 3, 4) [001937] ----------- t1937 = * ADD int REG x13 N4161 ( 1, 1) [001934] ----------- t1934 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1934 byref N4163 ( 3, 4) [002869] -c--------- t2869 = * LEA(b+8) byref REG NA /--* t2869 byref +--* t1937 int N4165 (???,???) [004004] -A--GO----- * STOREIND int REG NA ------------ BB159 [521..522), preds={BB157} succs={BB160} N001 ( 1, 1) [004423] ----------Z t4423 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004424] ----------Z t4424 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004425] ----------Z t4425 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004426] ----------Z t4426 = LCL_VAR int V144 tmp104 x8 REG x8 N4169 (???,???) [004005] ----------- IL_OFFSET void INL34 @ 0x02D[E-] <- INLRT @ 0x521[E-] REG NA N4171 ( 1, 1) [001913] ----------- t1913 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1913 byref N4173 (???,???) [004262] ----------- t4262 = * PUTARG_REG byref REG x0 N4175 ( 1, 1) [000675] ----------- t675 = LCL_VAR int V18 loc14 u:2 x13 (last use) REG x13 $5c9 /--* t675 int N4177 (???,???) [004263] ----------- t4263 = * PUTARG_REG int REG x1 N4179 ( 2, 8) [002870] H---------- t2870 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t2870 long N4181 (???,???) [004264] ----------- t4264 = * PUTARG_REG long REG x11 /--* t4262 byref this in x0 +--* t4263 int arg2 in x1 +--* t4264 long r2r cell in x11 N4183 ( 18, 15) [001914] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004427] ----------z t4427 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004428] ----------z t4428 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004429] ----------z t4429 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004430] ----------z t4430 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB160 [???..???) -> BB170 (cond), preds={BB158,BB159} succs={BB161,BB170} N4187 (???,???) [004006] ----------- IL_OFFSET void INLRT @ 0x529[E-] REG NA N4189 ( 1, 1) [000677] ----------z t677 = LCL_VAR int V12 loc8 u:3 x7 REG x7 $4c4 N4191 ( 1, 2) [000678] -c--------- t678 = CNS_INT int 0 REG NA $c0 /--* t677 int +--* t678 int N4193 ( 6, 4) [000679] -c-----N--- t679 = * EQ int REG NA $70a N4195 ( 1, 1) [000681] ----------- t681 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 N4197 ( 1, 2) [000682] -c--------- t682 = CNS_INT int 1 REG NA $c1 /--* t681 int +--* t682 int N4199 ( 6, 4) [000683] -c-----N--- t683 = * LE int REG NA $a93 /--* t679 int +--* t683 int N4201 ( 13, 9) [003746] Jc-----N--- * AND void REG NA N4203 ( 15, 11) [000680] ----------- * JTRUE void REG NA $VN.Void ------------ BB161 [52D..537) -> BB267 (cond), preds={BB160} succs={BB163,BB267} N4207 (???,???) [004007] ----------- IL_OFFSET void INLRT @ 0x52D[E-] REG NA N4209 (???,???) [004008] ----------- IL_OFFSET void INLRT @ 0x532[E-] REG NA N4211 ( 1, 1) [000692] ----------- t692 = LCL_VAR int V20 loc16 u:4 x9 REG x9 $2b3 N4213 ( 1, 1) [000696] ----------Z t696 = LCL_VAR int V144 tmp104 u:2 x8 REG x8 $2a6 /--* t692 int +--* t696 int N4215 ( 6, 9) [000697] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA $a34 N4217 ( 1, 1) [000701] ----------z t701 = LCL_VAR byref V143 tmp103 u:2 x6 REG x6 $385 N4219 ( 1, 1) [000693] ----------- t693 = LCL_VAR int V20 loc16 u:4 x9 REG x9 $2b3 /--* t693 int N4221 ( 2, 3) [000698] -c-------U- t698 = * CAST long <- uint REG NA $ac0 N4223 ( 1, 2) [000699] -c--------- t699 = CNS_INT long 2 REG NA $20a /--* t698 long +--* t699 long N4225 ( 4, 6) [000700] -c--------- t700 = * BFIZ long REG NA /--* t701 byref +--* t700 long N4227 ( 6, 8) [000702] -c--------- t702 = * LEA(b+(i*1)+0) byref REG NA /--* t702 byref N4229 ( 8, 9) [002871] ---XGO----- t2871 = * IND int REG x11 N4231 ( 1, 2) [000705] -c--------- t705 = CNS_INT int 1 REG NA $c1 /--* t2871 int +--* t705 int N4233 ( 16, 21) [000706] ---XGO----- t706 = * ADD int REG x11 N4235 ( 1, 1) [000689] ----------Z t689 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 /--* t706 int +--* t689 int N4237 ( 21, 23) [000707] Nc-XGO-N-U- t707 = * NE int REG NA N4239 ( 1, 1) [000685] ----------Z t685 = LCL_VAR int V20 loc16 u:4 x9 REG x9 $2b3 N4241 ( 1, 2) [000686] -c--------- t686 = CNS_INT int 0 REG NA $c0 /--* t685 int +--* t686 int N4243 ( 6, 4) [000687] -c-----N--- t687 = * LT int REG NA $a94 /--* t707 int +--* t687 int N4245 ( 28, 28) [003748] Jc-XGO-N--- * AND void REG NA N4247 ( 30, 30) [000688] ---XGO----- * JTRUE void REG NA $VN.Void ------------ BB163 [537..559) -> BB169 (cond), preds={BB161} succs={BB165,BB169} N4251 (???,???) [004009] ----------- IL_OFFSET void INLRT @ 0x537[E-] REG NA N4253 (???,???) [004010] ----------- IL_OFFSET void INLRT @ 0x547[E-] REG NA N4255 ( 1, 1) [000710] ----------- t710 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t710 ref N4257 ( 3, 4) [002873] -c--------- t2873 = * LEA(b+56) byref REG NA /--* t2873 byref N4259 ( 4, 3) [001946] ---XG------ t1946 = * IND ref REG x11 /--* t1946 ref N4261 ( 4, 3) [001999] DA-XG------ * STORE_LCL_VAR ref V102 tmp62 d:1 x11 REG x11 N4263 (???,???) [004011] ----------- IL_OFFSET void INL37 @ 0x000[E-] <- INLRT @ 0x547[E-] REG NA N4265 ( 1, 1) [001948] ----------- t1948 = LCL_VAR ref V102 tmp62 u:1 x11 REG x11 N4267 ( 1, 2) [001949] -c--------- t1949 = CNS_INT ref null REG NA $VN.Null /--* t1948 ref +--* t1949 ref N4269 ( 3, 4) [001950] CEQ-------N--- * JCMP void REG NA ------------ BB165 [547..548) -> BB168 (cond), preds={BB163} succs={BB166,BB168} N4273 (???,???) [004012] ----------- IL_OFFSET void INL37 @ 0x004[E-] <- INLRT @ 0x547[E-] REG NA N4275 ( 1, 1) [000709] ----------- t709 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t709 byref N4277 ( 3, 4) [002875] -c--------- t2875 = * LEA(b+8) byref REG NA /--* t2875 byref N4279 ( 4, 3) [001952] n---GO----- t1952 = * IND int REG x13 /--* t1952 int N4281 ( 4, 3) [001954] DA--GO----- * STORE_LCL_VAR int V103 tmp63 d:1 x13 REG x13 N4283 (???,???) [004013] ----------- IL_OFFSET void INL37 @ 0x00B[E-] <- INLRT @ 0x547[E-] REG NA N4285 ( 1, 1) [001955] ----------- t1955 = LCL_VAR ref V102 tmp62 u:1 x11 REG x11 /--* t1955 ref N4287 (???,???) [004170] -c--------- t4170 = * LEA(b+8) byref REG NA /--* t4170 byref N4289 ( 3, 3) [001956] ---X------- t1956 = * IND int REG x14 N4291 ( 1, 2) [001957] -c--------- t1957 = CNS_INT int 1 REG NA $c1 /--* t1956 int +--* t1957 int N4293 ( 8, 6) [001958] Nc-X---N-U- t1958 = * NE int REG NA N4295 ( 1, 1) [001963] ----------- t1963 = LCL_VAR int V103 tmp63 u:1 x13 REG x13 N4297 ( 1, 1) [001964] ----------- t1964 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1964 byref N4299 ( 3, 4) [002879] -c--------- t2879 = * LEA(b+24) byref REG NA /--* t2879 byref N4301 ( 4, 3) [002002] n---GO----- t2002 = * IND int REG x12 /--* t1963 int +--* t2002 int N4303 ( 9, 5) [001968] Nc--GO-N-U- t1968 = * GE int REG NA /--* t1958 int +--* t1968 int N4305 ( 18, 12) [003750] Jc-XGO-N--- * AND void REG NA N4307 ( 20, 14) [001959] ---XGO----- * JTRUE void REG NA ------------ BB166 [547..548) -> BB169 (always), preds={BB165} succs={BB169} N4311 (???,???) [004014] ----------- IL_OFFSET void INL37 @ 0x014[E-] <- INLRT @ 0x547[E-] REG NA N4313 (???,???) [004015] ----------- IL_OFFSET void INL37 @ 0x022[E-] <- INLRT @ 0x547[E-] REG NA N4315 ( 1, 1) [002883] ----------- t2883 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4317 ( 1, 2) [002884] -c--------- t2884 = CNS_INT long 16 REG NA $200 /--* t2883 byref +--* t2884 long N4319 ( 3, 4) [002885] -----O----- t2885 = * ADD byref REG x14 $25c /--* t2885 byref N4321 ( 3, 4) [001975] DA--GO----- * STORE_LCL_VAR byref V104 tmp64 d:1 x14 REG x14 N4323 (???,???) [004016] ----------- IL_OFFSET void INL37 @ ??? <- INLRT @ 0x547[E-] REG NA N4325 ( 1, 1) [001972] ----------- t1972 = LCL_VAR int V103 tmp63 u:1 x13 REG x13 N4327 ( 1, 1) [001977] ----------- t1977 = LCL_VAR byref V104 tmp64 u:1 x14 REG x14 $25c /--* t1977 byref N4329 ( 3, 4) [002888] -c--------- t2888 = * LEA(b+8) byref REG NA /--* t2888 byref N4331 ( 4, 3) [001978] n---GO----- t1978 = * IND int REG x12 /--* t1972 int +--* t1978 int N4333 ( 9, 11) [001979] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4335 ( 1, 1) [001976] ----------- t1976 = LCL_VAR byref V104 tmp64 u:1 x14 (last use) REG x14 $25c /--* t1976 byref N4337 ( 3, 2) [001983] n---GO----- t1983 = * IND byref REG x14 N4339 ( 1, 1) [001973] ----------- t1973 = LCL_VAR int V103 tmp63 u:1 x13 REG x13 /--* t1973 int N4341 ( 2, 3) [001980] -c-------U- t1980 = * CAST long <- uint REG NA N4343 ( 1, 2) [001981] -c--------- t1981 = CNS_INT long 1 REG NA $204 /--* t1980 long +--* t1981 long N4345 ( 4, 6) [001982] ----------- t1982 = * BFIZ long REG x12 /--* t1983 byref +--* t1982 long N4347 ( 8, 9) [001984] ----GO-N--- t1984 = * ADD byref REG x14 N4349 ( 1, 2) [001987] -c--------- t1987 = CNS_INT int 0 REG NA $c0 N4351 ( 1, 1) [001986] ----------- t1986 = LCL_VAR ref V102 tmp62 u:1 x11 REG x11 /--* t1986 ref N4353 (???,???) [004172] -c--------- t4172 = * LEA(b+8) byref REG NA /--* t4172 byref N4355 ( 3, 3) [002892] ---X------- t2892 = * IND int REG x12 /--* t1987 int +--* t2892 int N4357 ( 8, 12) [002893] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4359 ( 1, 1) [002890] ----------- t2890 = LCL_VAR ref V102 tmp62 u:1 x11 (last use) REG x11 /--* t2890 ref N4361 ( 1, 1) [002897] -c--------- t2897 = * LEA(b+12) byref REG NA /--* t2897 byref N4363 ( 5, 4) [002902] n---GO----- t2902 = * IND ushort REG x11 /--* t1984 byref +--* t2902 ushort N4365 (???,???) [004017] -A-XGO----- * STOREIND short REG NA N4367 (???,???) [004018] ----------- IL_OFFSET void INL37 @ 0x036[E-] <- INLRT @ 0x547[E-] REG NA N4369 ( 1, 1) [001993] ----------- t1993 = LCL_VAR int V103 tmp63 u:1 x13 (last use) REG x13 N4371 ( 1, 2) [001994] -c--------- t1994 = CNS_INT int 1 REG NA $c1 /--* t1993 int +--* t1994 int N4373 ( 3, 4) [001995] ----------- t1995 = * ADD int REG x11 N4375 ( 1, 1) [001992] ----------- t1992 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1992 byref N4377 ( 3, 4) [002904] -c--------- t2904 = * LEA(b+8) byref REG NA /--* t2904 byref +--* t1995 int N4379 (???,???) [004019] -A--GO----- * STOREIND int REG NA ------------ BB267 [???..???) -> BB170 (always), preds={BB161} succs={BB170} N001 ( 1, 1) [004337] ----------z t4337 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004338] ----------z t4338 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004339] ----------z t4339 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB168 [547..548), preds={BB165} succs={BB169} N001 ( 1, 1) [004431] ----------Z t4431 = LCL_VAR long V36 loc32 x0 REG x0 N4383 (???,???) [004020] ----------- IL_OFFSET void INL37 @ 0x040[E-] <- INLRT @ 0x547[E-] REG NA N4385 ( 1, 1) [001960] ----------- t1960 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t1960 byref N4387 (???,???) [004265] ----------- t4265 = * PUTARG_REG byref REG x0 N4389 ( 1, 1) [001961] ----------- t1961 = LCL_VAR ref V102 tmp62 u:1 x11 (last use) REG x11 /--* t1961 ref N4391 (???,???) [004266] ----------- t4266 = * PUTARG_REG ref REG x1 N4393 ( 2, 8) [002905] H---------- t2905 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2905 long N4395 (???,???) [004267] ----------- t4267 = * PUTARG_REG long REG x11 /--* t4265 byref this in x0 +--* t4266 ref arg2 in x1 +--* t4267 long r2r cell in x11 N4397 ( 18, 15) [001962] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004432] ----------z t4432 = LCL_VAR long V36 loc32 x0 REG x0 ------------ BB169 [???..???), preds={BB163,BB166,BB168} succs={BB170} N4401 (???,???) [004021] ----------- IL_OFFSET void INLRT @ 0x553[E-] REG NA N4403 ( 1, 1) [000714] ----------z t714 = LCL_VAR int V20 loc16 u:4 x9 (last use) REG x9 $2b3 N4405 ( 1, 2) [000715] -c--------- t715 = CNS_INT int -1 REG NA $c4 /--* t714 int +--* t715 int N4407 ( 3, 4) [000716] ----------- t716 = * ADD int REG x9 $ab7 /--* t716 int N4409 ( 3, 4) [000718] DA--------- * STORE_LCL_VAR int V20 loc16 d:6 NA REG NA N001 ( 1, 1) [004433] ----------z t4433 = LCL_VAR int V08 loc4 x2 REG x2 N001 ( 1, 1) [004434] ----------z t4434 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004435] ----------z t4435 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB170 [559..564) -> BB245 (always), preds={BB156,BB160,BB169,BB267} succs={BB245} N4413 (???,???) [004022] ----------- IL_OFFSET void INLRT @ 0x559[E-] REG NA N4415 ( 1, 1) [000669] ----------- t669 = LCL_VAR int V08 loc4 u:3 x2 (last use) REG x2 $2b5 N4417 ( 1, 2) [000670] -c--------- t670 = CNS_INT int -1 REG NA $c4 /--* t669 int +--* t670 int N4419 ( 3, 4) [000671] ----------- t671 = * ADD int REG x2 $ab9 /--* t671 int N4421 ( 3, 4) [000673] DA--------- * STORE_LCL_VAR int V08 loc4 d:4 NA REG NA N001 ( 1, 1) [004436] ----------z t4436 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB171 [564..571) -> BB245 (cond), preds={BB258} succs={BB172,BB245} N4801 (???,???) [004023] ----------- IL_OFFSET void INLRT @ 0x564[E-] REG NA N4803 ( 1, 1) [000605] ----------z t605 = LCL_VAR int V08 loc4 u:3 x2 REG x2 $2b5 N4805 ( 1, 2) [000606] -c--------- t606 = CNS_INT int 0 REG NA $c0 /--* t605 int +--* t606 int N4807 ( 6, 4) [000607] ----------- t607 = * NE int REG x11 $aba N4809 ( 1, 1) [000608] ----------z t608 = LCL_VAR int V21 loc17 u:2 x10 REG x10 $4c7 /--* t607 int +--* t608 int N4811 ( 8, 6) [000609] ----------- t609 = * OR int REG x11 $abb N4813 ( 1, 2) [000610] -c--------- t610 = CNS_INT int 0 REG NA $c0 N001 ( 1, 1) [004340] ----------Z t4340 = LCL_VAR bool V21 loc17 x10 REG x10 N001 ( 1, 1) [004341] ----------z t4341 = LCL_VAR int V14 loc10 x3 REG x3 /--* t609 int +--* t610 int N4815 ( 10, 9) [000611] CNE-------N--- * JCMP void REG NA ------------ BB172 [571..575) -> BB174 (cond), preds={BB171} succs={BB173,BB174} N4819 (???,???) [004024] ----------- IL_OFFSET void INLRT @ 0x571[E-] REG NA N4821 ( 1, 1) [000613] ----------z t613 = LCL_VAR int V07 loc3 u:3 x1 REG x1 $293 N4823 ( 1, 2) [000614] -c--------- t614 = CNS_INT int 0 REG NA $c0 /--* t613 int +--* t614 int N4825 ( 3, 4) [000615] J------N--- * LT void REG NA $abd N4827 ( 5, 6) [000616] ----------- * JTRUE void REG NA $VN.Void ------------ BB173 [575..57C) -> BB245 (cond), preds={BB172} succs={BB174,BB245} N4831 (???,???) [004025] ----------- IL_OFFSET void INLRT @ 0x575[E-] REG NA N4833 ( 1, 1) [000625] ----------- t625 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d N4835 ( 1, 1) [000626] ----------- t626 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t625 int +--* t626 int N4837 ( 6, 3) [000627] -c-----N--- t627 = * GE int REG NA $abe N4839 ( 1, 1) [000629] ----------Z t629 = LCL_VAR long V36 loc32 u:3 x0 REG x0 $901 /--* t629 long N4841 ( 4, 3) [000630] ---XG------ t630 = * IND ubyte REG x11 N4843 ( 1, 2) [000631] -c--------- t631 = CNS_INT int 0 REG NA $c0 /--* t630 ubyte +--* t631 int N4845 ( 9, 6) [000632] -c-XG--N--- t632 = * EQ int REG NA /--* t627 int +--* t632 int N4847 ( 16, 10) [003752] Jc-XG--N--- * AND void REG NA N001 ( 1, 1) [004342] ----------z t4342 = LCL_VAR long V36 loc32 x0 REG x0 N4849 ( 18, 12) [000628] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB174 [57C..598) -> BB180 (cond), preds={BB172,BB173} succs={BB176,BB180} N4853 (???,???) [004026] ----------- IL_OFFSET void INLRT @ 0x57C[E-] REG NA N4855 (???,???) [004027] ----------- IL_OFFSET void INLRT @ 0x584[E-] REG NA N4857 ( 1, 1) [000618] ----------- t618 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t618 ref N4859 ( 3, 4) [002907] -c--------- t2907 = * LEA(b+48) byref REG NA /--* t2907 byref N4861 ( 4, 3) [002006] ---XG------ t2006 = * IND ref REG x11 /--* t2006 ref N4863 ( 4, 3) [002059] DA-XG------ * STORE_LCL_VAR ref V106 tmp66 d:1 x11 REG x11 N4865 (???,???) [004028] ----------- IL_OFFSET void INL40 @ 0x000[E-] <- INLRT @ 0x584[E-] REG NA N4867 ( 1, 1) [002008] ----------- t2008 = LCL_VAR ref V106 tmp66 u:1 x11 REG x11 N4869 ( 1, 2) [002009] -c--------- t2009 = CNS_INT ref null REG NA $VN.Null /--* t2008 ref +--* t2009 ref N4871 ( 3, 4) [002010] CEQ-------N--- * JCMP void REG NA ------------ BB176 [584..585) -> BB179 (cond), preds={BB174} succs={BB177,BB179} N4875 (???,???) [004029] ----------- IL_OFFSET void INL40 @ 0x004[E-] <- INLRT @ 0x584[E-] REG NA N4877 ( 1, 1) [000617] ----------- t617 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t617 byref N4879 ( 3, 4) [002909] -c--------- t2909 = * LEA(b+8) byref REG NA /--* t2909 byref N4881 ( 4, 3) [002012] ---XG------ t2012 = * IND int REG x10 /--* t2012 int N4883 ( 4, 3) [002014] DA-XG------ * STORE_LCL_VAR int V107 tmp67 d:1 x10 REG x10 N4885 (???,???) [004030] ----------- IL_OFFSET void INL40 @ 0x00B[E-] <- INLRT @ 0x584[E-] REG NA N4887 ( 1, 1) [002015] ----------- t2015 = LCL_VAR ref V106 tmp66 u:1 x11 REG x11 /--* t2015 ref N4889 (???,???) [004174] -c--------- t4174 = * LEA(b+8) byref REG NA /--* t4174 byref N4891 ( 3, 3) [002016] ---X------- t2016 = * IND int REG x13 N4893 ( 1, 2) [002017] -c--------- t2017 = CNS_INT int 1 REG NA $c1 /--* t2016 int +--* t2017 int N4895 ( 8, 6) [002018] Nc-X---N-U- t2018 = * NE int REG NA N4897 ( 1, 1) [002023] ----------- t2023 = LCL_VAR int V107 tmp67 u:1 x10 REG x10 N4899 ( 1, 1) [002024] ----------- t2024 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2024 byref N4901 ( 3, 4) [002913] -c--------- t2913 = * LEA(b+24) byref REG NA /--* t2913 byref N4903 ( 4, 3) [002062] n---GO----- t2062 = * IND int REG x14 /--* t2023 int +--* t2062 int N4905 ( 9, 5) [002028] Nc--GO-N-U- t2028 = * GE int REG NA /--* t2018 int +--* t2028 int N4907 ( 18, 12) [003754] Jc-XGO-N--- * AND void REG NA N4909 ( 20, 14) [002019] ---XGO----- * JTRUE void REG NA ------------ BB177 [584..585) -> BB180 (always), preds={BB176} succs={BB180} N4913 (???,???) [004031] ----------- IL_OFFSET void INL40 @ 0x014[E-] <- INLRT @ 0x584[E-] REG NA N4915 (???,???) [004032] ----------- IL_OFFSET void INL40 @ 0x022[E-] <- INLRT @ 0x584[E-] REG NA N4917 ( 1, 1) [002917] ----------- t2917 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4919 ( 1, 2) [002918] -c--------- t2918 = CNS_INT long 16 REG NA $200 /--* t2917 byref +--* t2918 long N4921 ( 3, 4) [002919] -----O----- t2919 = * ADD byref REG x13 $25c /--* t2919 byref N4923 ( 3, 4) [002035] DA--GO----- * STORE_LCL_VAR byref V108 tmp68 d:1 x13 REG x13 N4925 (???,???) [004033] ----------- IL_OFFSET void INL40 @ ??? <- INLRT @ 0x584[E-] REG NA N4927 ( 1, 1) [002032] ----------- t2032 = LCL_VAR int V107 tmp67 u:1 x10 REG x10 N4929 ( 1, 1) [002037] ----------- t2037 = LCL_VAR byref V108 tmp68 u:1 x13 REG x13 $25c /--* t2037 byref N4931 ( 3, 4) [002922] -c--------- t2922 = * LEA(b+8) byref REG NA /--* t2922 byref N4933 ( 4, 3) [002038] n---GO----- t2038 = * IND int REG x14 /--* t2032 int +--* t2038 int N4935 ( 9, 11) [002039] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4937 ( 1, 1) [002036] ----------- t2036 = LCL_VAR byref V108 tmp68 u:1 x13 (last use) REG x13 $25c /--* t2036 byref N4939 ( 3, 2) [002043] n---GO----- t2043 = * IND byref REG x13 N4941 ( 1, 1) [002033] ----------- t2033 = LCL_VAR int V107 tmp67 u:1 x10 REG x10 /--* t2033 int N4943 ( 2, 3) [002040] -c-------U- t2040 = * CAST long <- uint REG NA N4945 ( 1, 2) [002041] -c--------- t2041 = CNS_INT long 1 REG NA $204 /--* t2040 long +--* t2041 long N4947 ( 4, 6) [002042] ----------- t2042 = * BFIZ long REG x14 /--* t2043 byref +--* t2042 long N4949 ( 8, 9) [002044] ----GO-N--- t2044 = * ADD byref REG x13 N4951 ( 1, 2) [002047] -c--------- t2047 = CNS_INT int 0 REG NA $c0 N4953 ( 1, 1) [002046] ----------- t2046 = LCL_VAR ref V106 tmp66 u:1 x11 REG x11 /--* t2046 ref N4955 (???,???) [004176] -c--------- t4176 = * LEA(b+8) byref REG NA /--* t4176 byref N4957 ( 3, 3) [002926] ---X------- t2926 = * IND int REG x14 /--* t2047 int +--* t2926 int N4959 ( 8, 12) [002927] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4961 ( 1, 1) [002924] ----------- t2924 = LCL_VAR ref V106 tmp66 u:1 x11 (last use) REG x11 /--* t2924 ref N4963 ( 1, 1) [002931] -c--------- t2931 = * LEA(b+12) byref REG NA /--* t2931 byref N4965 ( 5, 4) [002936] n---GO----- t2936 = * IND ushort REG x11 /--* t2044 byref +--* t2936 ushort N4967 (???,???) [004034] -A-XGO----- * STOREIND short REG NA N4969 (???,???) [004035] ----------- IL_OFFSET void INL40 @ 0x036[E-] <- INLRT @ 0x584[E-] REG NA N4971 ( 1, 1) [002053] ----------- t2053 = LCL_VAR int V107 tmp67 u:1 x10 (last use) REG x10 N4973 ( 1, 2) [002054] -c--------- t2054 = CNS_INT int 1 REG NA $c1 /--* t2053 int +--* t2054 int N4975 ( 3, 4) [002055] ----------- t2055 = * ADD int REG x11 N4977 ( 1, 1) [002052] ----------- t2052 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2052 byref N4979 ( 3, 4) [002938] -c--------- t2938 = * LEA(b+8) byref REG NA /--* t2938 byref +--* t2055 int N4981 (???,???) [004036] -A--GO----- * STOREIND int REG NA ------------ BB179 [584..585), preds={BB176} succs={BB180} N001 ( 1, 1) [004437] ----------Z t4437 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004438] ----------Z t4438 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004439] ----------Z t4439 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004440] ----------Z t4440 = LCL_VAR int V144 tmp104 x8 REG x8 N4985 (???,???) [004037] ----------- IL_OFFSET void INL40 @ 0x040[E-] <- INLRT @ 0x584[E-] REG NA N4987 ( 1, 1) [002020] ----------- t2020 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2020 byref N4989 (???,???) [004268] ----------- t4268 = * PUTARG_REG byref REG x0 N4991 ( 1, 1) [002021] ----------- t2021 = LCL_VAR ref V106 tmp66 u:1 x11 (last use) REG x11 /--* t2021 ref N4993 (???,???) [004269] ----------- t4269 = * PUTARG_REG ref REG x1 N4995 ( 2, 8) [002939] H---------- t2939 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2939 long N4997 (???,???) [004270] ----------- t4270 = * PUTARG_REG long REG x11 /--* t4268 byref this in x0 +--* t4269 ref arg2 in x1 +--* t4270 long r2r cell in x11 N4999 ( 18, 15) [002022] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004441] ----------z t4441 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004442] ----------z t4442 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004443] ----------z t4443 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004444] ----------z t4444 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB180 [???..???) -> BB245 (always), preds={BB174,BB177,BB179} succs={BB245} N5003 (???,???) [004038] ----------- IL_OFFSET void INLRT @ 0x590[E-] REG NA N5005 ( 1, 2) [002940] ----------- t2940 = CNS_INT int 1 REG x10 $c1 /--* t2940 int N5007 ( 1, 3) [000624] DA--------- * STORE_LCL_VAR int V21 loc17 d:3 x11 REG x11 N001 ( 1, 1) [004445] ----------Z t4445 = LCL_VAR bool V21 loc17 x11 REG x11 ------------ BB181 [598..599) -> BB245 (cond), preds={BB144} succs={BB182,BB245} N2353 (???,???) [004039] ----------- IL_OFFSET void INL43 @ 0x000[E-] <- INLRT @ 0x598[E-] REG NA N2355 ( 1, 1) [002068] ----------- t2068 = LCL_VAR ref V110 tmp70 u:1 x11 REG x11 N2357 ( 1, 2) [002069] -c--------- t2069 = CNS_INT ref null REG NA $VN.Null N001 ( 1, 1) [004343] ----------z t4343 = LCL_VAR int V14 loc10 x3 REG x3 /--* t2068 ref +--* t2069 ref N2359 ( 3, 4) [002070] CEQ-------N--- * JCMP void REG NA ------------ BB182 [598..599) -> BB185 (cond), preds={BB181} succs={BB183,BB185} N2363 (???,???) [004040] ----------- IL_OFFSET void INL43 @ 0x004[E-] <- INLRT @ 0x598[E-] REG NA N2365 ( 1, 1) [000585] ----------- t585 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t585 byref N2367 ( 3, 4) [002942] -c--------- t2942 = * LEA(b+8) byref REG NA /--* t2942 byref N2369 ( 4, 3) [002072] ---XG------ t2072 = * IND int REG x13 /--* t2072 int N2371 ( 4, 3) [002074] DA-XG------ * STORE_LCL_VAR int V111 tmp71 d:1 x13 REG x13 N2373 (???,???) [004041] ----------- IL_OFFSET void INL43 @ 0x00B[E-] <- INLRT @ 0x598[E-] REG NA N2375 ( 1, 1) [002075] ----------- t2075 = LCL_VAR ref V110 tmp70 u:1 x11 REG x11 /--* t2075 ref N2377 (???,???) [004178] -c--------- t4178 = * LEA(b+8) byref REG NA /--* t4178 byref N2379 ( 3, 3) [002076] ---X------- t2076 = * IND int REG x14 N2381 ( 1, 2) [002077] -c--------- t2077 = CNS_INT int 1 REG NA $c1 /--* t2076 int +--* t2077 int N2383 ( 8, 6) [002078] Nc-X---N-U- t2078 = * NE int REG NA N2385 ( 1, 1) [002083] ----------- t2083 = LCL_VAR int V111 tmp71 u:1 x13 REG x13 N2387 ( 1, 1) [002084] ----------- t2084 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2084 byref N2389 ( 3, 4) [002946] -c--------- t2946 = * LEA(b+24) byref REG NA /--* t2946 byref N2391 ( 4, 3) [002122] n---GO----- t2122 = * IND int REG x12 /--* t2083 int +--* t2122 int N2393 ( 9, 5) [002088] Nc--GO-N-U- t2088 = * GE int REG NA /--* t2078 int +--* t2088 int N2395 ( 18, 12) [003756] Jc-XGO-N--- * AND void REG NA N2397 ( 20, 14) [002079] ---XGO----- * JTRUE void REG NA ------------ BB183 [598..599) -> BB245 (always), preds={BB182} succs={BB245} N2401 (???,???) [004042] ----------- IL_OFFSET void INL43 @ 0x014[E-] <- INLRT @ 0x598[E-] REG NA N2403 (???,???) [004043] ----------- IL_OFFSET void INL43 @ 0x022[E-] <- INLRT @ 0x598[E-] REG NA N2405 ( 1, 1) [002950] ----------- t2950 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N2407 ( 1, 2) [002951] -c--------- t2951 = CNS_INT long 16 REG NA $200 /--* t2950 byref +--* t2951 long N2409 ( 3, 4) [002952] -----O----- t2952 = * ADD byref REG x14 $25c /--* t2952 byref N2411 ( 3, 4) [002095] DA--GO----- * STORE_LCL_VAR byref V112 tmp72 d:1 x14 REG x14 N2413 (???,???) [004044] ----------- IL_OFFSET void INL43 @ ??? <- INLRT @ 0x598[E-] REG NA N2415 ( 1, 1) [002092] ----------- t2092 = LCL_VAR int V111 tmp71 u:1 x13 REG x13 N2417 ( 1, 1) [002097] ----------- t2097 = LCL_VAR byref V112 tmp72 u:1 x14 REG x14 $25c /--* t2097 byref N2419 ( 3, 4) [002955] -c--------- t2955 = * LEA(b+8) byref REG NA /--* t2955 byref N2421 ( 4, 3) [002098] n---GO----- t2098 = * IND int REG x12 /--* t2092 int +--* t2098 int N2423 ( 9, 11) [002099] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2425 ( 1, 1) [002096] ----------- t2096 = LCL_VAR byref V112 tmp72 u:1 x14 (last use) REG x14 $25c /--* t2096 byref N2427 ( 3, 2) [002103] n---GO----- t2103 = * IND byref REG x14 N2429 ( 1, 1) [002093] ----------- t2093 = LCL_VAR int V111 tmp71 u:1 x13 REG x13 /--* t2093 int N2431 ( 2, 3) [002100] -c-------U- t2100 = * CAST long <- uint REG NA N2433 ( 1, 2) [002101] -c--------- t2101 = CNS_INT long 1 REG NA $204 /--* t2100 long +--* t2101 long N2435 ( 4, 6) [002102] ----------- t2102 = * BFIZ long REG x12 /--* t2103 byref +--* t2102 long N2437 ( 8, 9) [002104] ----GO-N--- t2104 = * ADD byref REG x14 N2439 ( 1, 2) [002107] -c--------- t2107 = CNS_INT int 0 REG NA $c0 N2441 ( 1, 1) [002106] ----------- t2106 = LCL_VAR ref V110 tmp70 u:1 x11 REG x11 /--* t2106 ref N2443 (???,???) [004180] -c--------- t4180 = * LEA(b+8) byref REG NA /--* t4180 byref N2445 ( 3, 3) [002959] ---X------- t2959 = * IND int REG x12 /--* t2107 int +--* t2959 int N2447 ( 8, 12) [002960] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2449 ( 1, 1) [002957] ----------- t2957 = LCL_VAR ref V110 tmp70 u:1 x11 (last use) REG x11 /--* t2957 ref N2451 ( 1, 1) [002964] -c--------- t2964 = * LEA(b+12) byref REG NA /--* t2964 byref N2453 ( 5, 4) [002969] n---GO----- t2969 = * IND ushort REG x11 /--* t2104 byref +--* t2969 ushort N2455 (???,???) [004045] -A-XGO----- * STOREIND short REG NA N2457 (???,???) [004046] ----------- IL_OFFSET void INL43 @ 0x036[E-] <- INLRT @ 0x598[E-] REG NA N2459 ( 1, 1) [002113] ----------- t2113 = LCL_VAR int V111 tmp71 u:1 x13 (last use) REG x13 N2461 ( 1, 2) [002114] -c--------- t2114 = CNS_INT int 1 REG NA $c1 /--* t2113 int +--* t2114 int N2463 ( 3, 4) [002115] ----------- t2115 = * ADD int REG x11 N2465 ( 1, 1) [002112] ----------- t2112 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2112 byref N2467 ( 3, 4) [002971] -c--------- t2971 = * LEA(b+8) byref REG NA /--* t2971 byref +--* t2115 int N2469 (???,???) [004047] -A--GO----- * STOREIND int REG NA ------------ BB185 [598..599) -> BB245 (always), preds={BB182} succs={BB245} N001 ( 1, 1) [004446] ----------Z t4446 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004447] ----------Z t4447 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004448] ----------Z t4448 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004449] ----------Z t4449 = LCL_VAR int V144 tmp104 x8 REG x8 N2473 (???,???) [004048] ----------- IL_OFFSET void INL43 @ 0x040[E-] <- INLRT @ 0x598[E-] REG NA N2475 ( 1, 1) [002080] ----------- t2080 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2080 byref N2477 (???,???) [004271] ----------- t4271 = * PUTARG_REG byref REG x0 N2479 ( 1, 1) [002081] ----------- t2081 = LCL_VAR ref V110 tmp70 u:1 x11 (last use) REG x11 /--* t2081 ref N2481 (???,???) [004272] ----------- t4272 = * PUTARG_REG ref REG x1 N2483 ( 2, 8) [002972] H---------- t2972 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t2972 long N2485 (???,???) [004273] ----------- t4273 = * PUTARG_REG long REG x11 /--* t4271 byref this in x0 +--* t4272 ref arg2 in x1 +--* t4273 long r2r cell in x11 N2487 ( 18, 15) [002082] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004450] ----------z t4450 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004451] ----------z t4451 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004452] ----------z t4452 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004453] ----------z t4453 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB186 [5A9..5BA) -> BB245 (cond), preds={BB257} succs={BB187,BB245} N4425 (???,???) [004049] ----------- IL_OFFSET void INLRT @ 0x5A9[E-] REG NA N4427 ( 1, 1) [000635] ----------- t635 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t635 ref N4429 ( 3, 4) [002974] -c--------- t2974 = * LEA(b+128) byref REG NA /--* t2974 byref N4431 ( 4, 3) [002126] ---XG------ t2126 = * IND ref REG x11 /--* t2126 ref N4433 ( 4, 3) [002179] DA-XG------ * STORE_LCL_VAR ref V114 tmp74 d:1 x11 REG x11 N4435 (???,???) [004050] ----------- IL_OFFSET void INL46 @ 0x000[E-] <- INLRT @ 0x5A9[E-] REG NA N4437 ( 1, 1) [002128] ----------- t2128 = LCL_VAR ref V114 tmp74 u:1 x11 REG x11 N4439 ( 1, 2) [002129] -c--------- t2129 = CNS_INT ref null REG NA $VN.Null N001 ( 1, 1) [004344] ----------z t4344 = LCL_VAR int V14 loc10 x3 REG x3 /--* t2128 ref +--* t2129 ref N4441 ( 3, 4) [002130] CEQ-------N--- * JCMP void REG NA ------------ BB187 [5A9..5AA) -> BB190 (cond), preds={BB186} succs={BB188,BB190} N4445 (???,???) [004051] ----------- IL_OFFSET void INL46 @ 0x004[E-] <- INLRT @ 0x5A9[E-] REG NA N4447 ( 1, 1) [000634] ----------- t634 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t634 byref N4449 ( 3, 4) [002976] -c--------- t2976 = * LEA(b+8) byref REG NA /--* t2976 byref N4451 ( 4, 3) [002132] ---XG------ t2132 = * IND int REG x13 /--* t2132 int N4453 ( 4, 3) [002134] DA-XG------ * STORE_LCL_VAR int V115 tmp75 d:1 x13 REG x13 N4455 (???,???) [004052] ----------- IL_OFFSET void INL46 @ 0x00B[E-] <- INLRT @ 0x5A9[E-] REG NA N4457 ( 1, 1) [002135] ----------- t2135 = LCL_VAR ref V114 tmp74 u:1 x11 REG x11 /--* t2135 ref N4459 (???,???) [004182] -c--------- t4182 = * LEA(b+8) byref REG NA /--* t4182 byref N4461 ( 3, 3) [002136] ---X------- t2136 = * IND int REG x14 N4463 ( 1, 2) [002137] -c--------- t2137 = CNS_INT int 1 REG NA $c1 /--* t2136 int +--* t2137 int N4465 ( 8, 6) [002138] Nc-X---N-U- t2138 = * NE int REG NA N4467 ( 1, 1) [002143] ----------- t2143 = LCL_VAR int V115 tmp75 u:1 x13 REG x13 N4469 ( 1, 1) [002144] ----------- t2144 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2144 byref N4471 ( 3, 4) [002980] -c--------- t2980 = * LEA(b+24) byref REG NA /--* t2980 byref N4473 ( 4, 3) [002182] n---GO----- t2182 = * IND int REG x12 /--* t2143 int +--* t2182 int N4475 ( 9, 5) [002148] Nc--GO-N-U- t2148 = * GE int REG NA /--* t2138 int +--* t2148 int N4477 ( 18, 12) [003758] Jc-XGO-N--- * AND void REG NA N4479 ( 20, 14) [002139] ---XGO----- * JTRUE void REG NA ------------ BB188 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} N4483 (???,???) [004053] ----------- IL_OFFSET void INL46 @ 0x014[E-] <- INLRT @ 0x5A9[E-] REG NA N4485 (???,???) [004054] ----------- IL_OFFSET void INL46 @ 0x022[E-] <- INLRT @ 0x5A9[E-] REG NA N4487 ( 1, 1) [002984] ----------- t2984 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4489 ( 1, 2) [002985] -c--------- t2985 = CNS_INT long 16 REG NA $200 /--* t2984 byref +--* t2985 long N4491 ( 3, 4) [002986] -----O----- t2986 = * ADD byref REG x14 $25c /--* t2986 byref N4493 ( 3, 4) [002155] DA--GO----- * STORE_LCL_VAR byref V116 tmp76 d:1 x14 REG x14 N4495 (???,???) [004055] ----------- IL_OFFSET void INL46 @ ??? <- INLRT @ 0x5A9[E-] REG NA N4497 ( 1, 1) [002152] ----------- t2152 = LCL_VAR int V115 tmp75 u:1 x13 REG x13 N4499 ( 1, 1) [002157] ----------- t2157 = LCL_VAR byref V116 tmp76 u:1 x14 REG x14 $25c /--* t2157 byref N4501 ( 3, 4) [002989] -c--------- t2989 = * LEA(b+8) byref REG NA /--* t2989 byref N4503 ( 4, 3) [002158] n---GO----- t2158 = * IND int REG x12 /--* t2152 int +--* t2158 int N4505 ( 9, 11) [002159] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4507 ( 1, 1) [002156] ----------- t2156 = LCL_VAR byref V116 tmp76 u:1 x14 (last use) REG x14 $25c /--* t2156 byref N4509 ( 3, 2) [002163] n---GO----- t2163 = * IND byref REG x14 N4511 ( 1, 1) [002153] ----------- t2153 = LCL_VAR int V115 tmp75 u:1 x13 REG x13 /--* t2153 int N4513 ( 2, 3) [002160] -c-------U- t2160 = * CAST long <- uint REG NA N4515 ( 1, 2) [002161] -c--------- t2161 = CNS_INT long 1 REG NA $204 /--* t2160 long +--* t2161 long N4517 ( 4, 6) [002162] ----------- t2162 = * BFIZ long REG x12 /--* t2163 byref +--* t2162 long N4519 ( 8, 9) [002164] ----GO-N--- t2164 = * ADD byref REG x14 N4521 ( 1, 2) [002167] -c--------- t2167 = CNS_INT int 0 REG NA $c0 N4523 ( 1, 1) [002166] ----------- t2166 = LCL_VAR ref V114 tmp74 u:1 x11 REG x11 /--* t2166 ref N4525 (???,???) [004184] -c--------- t4184 = * LEA(b+8) byref REG NA /--* t4184 byref N4527 ( 3, 3) [002993] ---X------- t2993 = * IND int REG x12 /--* t2167 int +--* t2993 int N4529 ( 8, 12) [002994] ---X-O----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4531 ( 1, 1) [002991] ----------- t2991 = LCL_VAR ref V114 tmp74 u:1 x11 (last use) REG x11 /--* t2991 ref N4533 ( 1, 1) [002998] -c--------- t2998 = * LEA(b+12) byref REG NA /--* t2998 byref N4535 ( 5, 4) [003003] n---GO----- t3003 = * IND ushort REG x11 /--* t2164 byref +--* t3003 ushort N4537 (???,???) [004056] -A-XGO----- * STOREIND short REG NA N4539 (???,???) [004057] ----------- IL_OFFSET void INL46 @ 0x036[E-] <- INLRT @ 0x5A9[E-] REG NA N4541 ( 1, 1) [002173] ----------- t2173 = LCL_VAR int V115 tmp75 u:1 x13 (last use) REG x13 N4543 ( 1, 2) [002174] -c--------- t2174 = CNS_INT int 1 REG NA $c1 /--* t2173 int +--* t2174 int N4545 ( 3, 4) [002175] ----------- t2175 = * ADD int REG x11 N4547 ( 1, 1) [002172] ----------- t2172 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2172 byref N4549 ( 3, 4) [003005] -c--------- t3005 = * LEA(b+8) byref REG NA /--* t3005 byref +--* t2175 int N4551 (???,???) [004058] -A--GO----- * STOREIND int REG NA ------------ BB190 [5A9..5AA) -> BB245 (always), preds={BB187} succs={BB245} N001 ( 1, 1) [004454] ----------Z t4454 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004455] ----------Z t4455 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004456] ----------Z t4456 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004457] ----------Z t4457 = LCL_VAR int V144 tmp104 x8 REG x8 N4555 (???,???) [004059] ----------- IL_OFFSET void INL46 @ 0x040[E-] <- INLRT @ 0x5A9[E-] REG NA N4557 ( 1, 1) [002140] ----------- t2140 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2140 byref N4559 (???,???) [004274] ----------- t4274 = * PUTARG_REG byref REG x0 N4561 ( 1, 1) [002141] ----------- t2141 = LCL_VAR ref V114 tmp74 u:1 x11 (last use) REG x11 /--* t2141 ref N4563 (???,???) [004275] ----------- t4275 = * PUTARG_REG ref REG x1 N4565 ( 2, 8) [003006] H---------- t3006 = CNS_INT(h) long 0x4000000000431d58 ftn REG x11 $4f /--* t3006 long N4567 (???,???) [004276] ----------- t4276 = * PUTARG_REG long REG x11 /--* t4274 byref this in x0 +--* t4275 ref arg2 in x1 +--* t4276 long r2r cell in x11 N4569 ( 18, 15) [002142] --CXG------ * CALL r2r_ind void System.Text.ValueStringBuilder:AppendSlow(System.String):this REG NA $VN.Void N001 ( 1, 1) [004458] ----------z t4458 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004459] ----------z t4459 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004460] ----------z t4460 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004461] ----------z t4461 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB191 [000..5CE) -> BB193 (cond), preds={BB196} succs={BB192,BB193} N4623 (???,???) [004060] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] REG NA N4625 ( 1, 1) [000805] ----------- t805 = LCL_VAR int V16 loc12 u:13 x4 (last use) REG x4 $b04 /--* t805 int N4627 ( 1, 3) [000812] DA--------- * STORE_LCL_VAR int V59 tmp19 d:1 x4 REG x4 N4629 (???,???) [004061] ----------- IL_OFFSET void INLRT @ 0x5BA[E-] REG NA N4631 ( 1, 1) [000806] ----------- t806 = LCL_VAR int V59 tmp19 u:1 x4 (last use) REG x4 $b04 N4633 ( 1, 2) [000807] -c--------- t807 = CNS_INT int 1 REG NA $c1 /--* t806 int +--* t807 int N4635 ( 3, 4) [000808] ----------- t808 = * ADD int REG x4 $bad /--* t808 int N4637 ( 3, 4) [000810] DA--------- * STORE_LCL_VAR int V16 loc12 d:15 NA REG NA N4639 ( 1, 1) [003629] ----------- t3629 = LCL_VAR int V172 cse1 x14 (last use) REG x14 /--* t3629 int N4641 ( 1, 3) [002225] DA--G------ * STORE_LCL_VAR int V119 tmp79 d:1 x14 REG x14 N4643 (???,???) [004062] ----------- IL_OFFSET void INL48 @ 0x000[E-] <- INLRT @ ??? REG NA N4645 ( 1, 1) [000803] ----------- t803 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t803 byref N4647 ( 3, 4) [003008] -c--------- t3008 = * LEA(b+8) byref REG NA /--* t3008 byref N4649 ( 4, 3) [002186] ---XG------ t2186 = * IND int REG x11 /--* t2186 int N4651 ( 4, 3) [002188] DA-XG------ * STORE_LCL_VAR int V118 tmp78 d:1 x11 REG x11 N4653 (???,???) [004063] ----------- IL_OFFSET void INL48 @ 0x007[E-] <- INLRT @ ??? REG NA N4655 ( 1, 1) [002189] ----------- t2189 = LCL_VAR int V118 tmp78 u:1 x11 REG x11 N4657 ( 1, 1) [002190] ----------- t2190 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2190 byref N4659 ( 3, 4) [003012] -c--------- t3012 = * LEA(b+24) byref REG NA /--* t3012 byref N4661 ( 4, 3) [002228] n---GO----- t2228 = * IND int REG x12 /--* t2189 int +--* t2228 int N4663 ( 6, 5) [002194] N---GO-N-U- * GE void REG NA N4665 ( 8, 7) [002195] ----GO----- * JTRUE void REG NA $845 ------------ BB192 [000..000) -> BB194 (always), preds={BB191} succs={BB194} N4669 (???,???) [004064] ----------- IL_OFFSET void INL48 @ 0x015[E-] <- INLRT @ ??? REG NA N4671 ( 1, 1) [003016] ----------- t3016 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N4673 ( 1, 2) [003017] -c--------- t3017 = CNS_INT long 16 REG NA $200 /--* t3016 byref +--* t3017 long N4675 ( 3, 4) [003018] -----O----- t3018 = * ADD byref REG x12 $25c /--* t3018 byref N4677 ( 3, 4) [002204] DA--GO----- * STORE_LCL_VAR byref V120 tmp80 d:1 x12 REG x12 N4679 ( 1, 1) [002201] ----------- t2201 = LCL_VAR int V118 tmp78 u:1 x11 REG x11 N4681 ( 1, 1) [002206] ----------- t2206 = LCL_VAR byref V120 tmp80 u:1 x12 REG x12 $25c /--* t2206 byref N4683 ( 3, 4) [003021] -c--------- t3021 = * LEA(b+8) byref REG NA /--* t3021 byref N4685 ( 4, 3) [002207] n---GO----- t2207 = * IND int REG x15 /--* t2201 int +--* t2207 int N4687 ( 9, 11) [002208] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N4689 ( 1, 1) [002205] ----------- t2205 = LCL_VAR byref V120 tmp80 u:1 x12 (last use) REG x12 $25c /--* t2205 byref N4691 ( 3, 2) [002212] n---GO----- t2212 = * IND byref REG x12 N4693 ( 1, 1) [002202] ----------- t2202 = LCL_VAR int V118 tmp78 u:1 x11 REG x11 /--* t2202 int N4695 ( 2, 3) [002209] -c-------U- t2209 = * CAST long <- uint REG NA N4697 ( 1, 2) [002210] -c--------- t2210 = CNS_INT long 1 REG NA $204 /--* t2209 long +--* t2210 long N4699 ( 4, 6) [002211] -c--------- t2211 = * BFIZ long REG NA /--* t2212 byref +--* t2211 long N4701 ( 8, 9) [002213] -c--------- t2213 = * LEA(b+(i*1)+0) byref REG NA N4703 ( 1, 1) [002215] ----------- t2215 = LCL_VAR int V119 tmp79 u:1 x14 (last use) REG x14 /--* t2213 byref +--* t2215 int N4705 (???,???) [004065] -A-XGO----- * STOREIND short REG NA N4707 (???,???) [004066] ----------- IL_OFFSET void INL48 @ 0x023[E-] <- INLRT @ ??? REG NA N4709 ( 1, 1) [002219] ----------- t2219 = LCL_VAR int V118 tmp78 u:1 x11 (last use) REG x11 N4711 ( 1, 2) [002220] -c--------- t2220 = CNS_INT int 1 REG NA $c1 /--* t2219 int +--* t2220 int N4713 ( 3, 4) [002221] ----------- t2221 = * ADD int REG x14 N4715 ( 1, 1) [002218] ----------- t2218 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2218 byref N4717 ( 3, 4) [003024] -c--------- t3024 = * LEA(b+8) byref REG NA /--* t3024 byref +--* t2221 int N4719 (???,???) [004067] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004462] ----------z t4462 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB193 [000..000), preds={BB191} succs={BB194} N001 ( 1, 1) [004463] ----------Z t4463 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004464] ----------Z t4464 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004465] ----------Z t4465 = LCL_VAR int V144 tmp104 x8 REG x8 N4723 (???,???) [004068] ----------- IL_OFFSET void INL48 @ 0x02D[E-] <- INLRT @ ??? REG NA N4725 ( 1, 1) [002196] ----------- t2196 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2196 byref N4727 (???,???) [004277] ----------- t4277 = * PUTARG_REG byref REG x0 N4729 ( 1, 1) [002197] ----------- t2197 = LCL_VAR int V119 tmp79 u:1 x14 (last use) REG x14 /--* t2197 int N4731 (???,???) [004278] ----------- t4278 = * PUTARG_REG int REG x1 N4733 ( 2, 8) [003025] H---------- t3025 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3025 long N4735 (???,???) [004279] ----------- t4279 = * PUTARG_REG long REG x11 /--* t4277 byref this in x0 +--* t4278 int arg2 in x1 +--* t4279 long r2r cell in x11 N4737 ( 18, 15) [002198] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004466] ----------z t4466 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004467] ----------z t4467 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004468] ----------z t4468 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004469] ----------z t4469 = LCL_VAR ushort V18 loc14 x13 REG x13 ------------ BB194 [5CE..5D9) -> BB197 (cond), preds={BB192,BB193,BB257(2)} succs={BB195,BB197} N4573 (???,???) [004069] ----------- IL_OFFSET void INLRT @ 0x5CE[E-] REG NA N4575 ( 1, 1) [000751] ----------z t751 = LCL_VAR int V16 loc12 u:13 x4 REG x4 $b04 N4577 ( 1, 1) [003699] ----------- t3699 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t751 int +--* t3699 int N4579 ( 3, 3) [000756] J------N--- * GE void REG NA $ba4 N4581 ( 5, 5) [000757] ----------- * JTRUE void REG NA $VN.Void ------------ BB195 [5D9..5E4) -> BB198 (cond), preds={BB194} succs={BB196,BB198} N4585 (???,???) [004070] ----------- IL_OFFSET void INLRT @ 0x5D9[E-] REG NA N4587 ( 1, 1) [000781] ----------- t781 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N4589 ( 1, 1) [000782] ----------- t782 = LCL_VAR int V16 loc12 u:13 x4 REG x4 $b04 /--* t782 int N4591 ( 2, 3) [000783] -c--------- t783 = * CAST long <- int REG NA $aca N4593 ( 1, 2) [000785] -c--------- t785 = CNS_INT long 1 REG NA $204 /--* t783 long +--* t785 long N4595 ( 4, 6) [000786] -c--------- t786 = * BFIZ long REG NA /--* t781 long +--* t786 long N4597 ( 6, 8) [000787] -c--------- t787 = * LEA(b+(i*1)+0) long REG NA /--* t787 long N4599 ( 9, 10) [000788] ---XG------ t788 = * IND ushort REG x14 /--* t788 ushort N4601 ( 9, 10) [003631] DA-XG------ * STORE_LCL_VAR int V172 cse1 x14 REG x14 N4603 ( 1, 1) [003632] ----------- t3632 = LCL_VAR int V172 cse1 x14 REG x14 N4605 ( 1, 2) [000789] -c--------- t789 = CNS_INT int 0 REG NA $c0 /--* t3632 int +--* t789 int N4607 ( 12, 14) [000790] CEQ---XG--N--- * JCMP void REG NA ------------ BB196 [5E4..5F1) -> BB191 (cond), preds={BB195} succs={BB197,BB191} N4611 (???,???) [004071] ----------- IL_OFFSET void INLRT @ 0x5E4[E-] REG NA N4613 ( 1, 1) [003634] ----------- t3634 = LCL_VAR int V172 cse1 x14 REG x14 N4615 ( 1, 1) [000800] ----------Z t800 = LCL_VAR int V18 loc14 u:1 x13 REG x13 /--* t3634 int +--* t800 int N4617 ( 3, 3) [000801] N---G--N-U- * NE void REG NA N4619 ( 5, 5) [000802] ----G------ * JTRUE void REG NA $bec ------------ BB197 [5F1..5FF) -> BB268 (cond), preds={BB194,BB196} succs={BB198,BB268} N4741 (???,???) [004072] ----------- IL_OFFSET void INLRT @ 0x5F1[E-] REG NA N4743 ( 1, 1) [000758] ----------- t758 = LCL_VAR int V16 loc12 u:13 x4 REG x4 $b04 N4745 ( 1, 1) [003700] ----------- t3700 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t758 int +--* t3700 int N4747 ( 3, 3) [000763] J------N--- * GE void REG NA $ba4 N4749 ( 5, 5) [000764] ----------- * JTRUE void REG NA $VN.Void ------------ BB198 [5FF..60D) -> BB245 (cond), preds={BB195,BB197} succs={BB199,BB245} N4753 (???,???) [004073] ----------- IL_OFFSET void INLRT @ 0x5FF[E-] REG NA N4755 ( 1, 1) [000765] ----------- t765 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N4757 ( 1, 1) [000766] ----------- t766 = LCL_VAR int V16 loc12 u:13 x4 REG x4 $b04 /--* t766 int N4759 ( 2, 3) [000767] -c--------- t767 = * CAST long <- int REG NA $aca N4761 ( 1, 2) [000769] -c--------- t769 = CNS_INT long 1 REG NA $204 /--* t767 long +--* t769 long N4763 ( 4, 6) [000770] -c--------- t770 = * BFIZ long REG NA /--* t765 long +--* t770 long N4765 ( 6, 8) [000771] -c--------- t771 = * LEA(b+(i*1)+0) long REG NA /--* t771 long N4767 ( 9, 10) [000772] ---XG------ t772 = * IND ushort REG x14 /--* t772 ushort N4769 ( 9, 10) [003636] DA-XG------ * STORE_LCL_VAR int V172 cse1 x14 REG x14 N4771 ( 1, 1) [003637] ----------- t3637 = LCL_VAR int V172 cse1 x14 (last use) REG x14 N4773 ( 1, 2) [000773] -c--------- t773 = CNS_INT int 0 REG NA $c0 N001 ( 1, 1) [004347] ----------Z t4347 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004348] ----------z t4348 = LCL_VAR int V14 loc10 x3 REG x3 /--* t3637 int +--* t773 int N4775 ( 12, 14) [000774] CEQ---XG--N--- * JCMP void REG NA ------------ BB199 [60D..618) -> BB245 (always), preds={BB198} succs={BB245} N4779 (???,???) [004074] ----------- IL_OFFSET void INLRT @ 0x60D[E-] REG NA N4781 ( 1, 1) [000776] ----------z t776 = LCL_VAR int V16 loc12 u:13 x4 (last use) REG x4 $b04 N4783 ( 1, 2) [000777] -c--------- t777 = CNS_INT int 1 REG NA $c1 /--* t776 int +--* t777 int N4785 ( 3, 4) [000778] ----------- t778 = * ADD int REG x4 $bad /--* t778 int N4787 ( 3, 4) [000780] DA--------- * STORE_LCL_VAR int V16 loc12 d:14 NA REG NA ------------ BB268 [???..???) -> BB245 (always), preds={BB197} succs={BB245} N001 ( 1, 1) [004345] ----------Z t4345 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004346] ----------z t4346 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB200 [618..626) -> BB245 (cond), preds={BB141} succs={BB201,BB245} N2491 (???,???) [004075] ----------- IL_OFFSET void INLRT @ 0x618[E-] REG NA N2493 ( 1, 1) [000283] ----------- t283 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2495 ( 1, 1) [003701] ----------- t3701 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t283 int +--* t3701 int N2497 ( 6, 3) [000288] -c-----N--- t288 = * GE int REG NA $94d N2499 ( 1, 1) [000290] ----------- t290 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2501 ( 1, 1) [000291] ----------z t291 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 /--* t291 int N2503 ( 2, 3) [000292] -c--------- t292 = * CAST long <- int REG NA $3e5 N2505 ( 1, 2) [000294] -c--------- t294 = CNS_INT long 1 REG NA $204 /--* t292 long +--* t294 long N2507 ( 4, 6) [000295] -c--------- t295 = * BFIZ long REG NA /--* t290 long +--* t295 long N2509 ( 6, 8) [000296] -c--------- t296 = * LEA(b+(i*1)+0) long REG NA /--* t296 long N2511 ( 9, 10) [000297] ---XG------ t297 = * IND ushort REG x13 /--* t297 ushort N2513 ( 9, 10) [003664] DA-XG------ * STORE_LCL_VAR int V176 cse5 x13 REG x13 N2515 ( 1, 1) [003665] ----------- t3665 = LCL_VAR int V176 cse5 x13 REG x13 N2517 ( 1, 2) [000298] -c--------- t298 = CNS_INT int 0 REG NA $c0 /--* t3665 int +--* t298 int N2519 ( 15, 14) [000299] -c-XG--N--- t299 = * EQ int REG NA /--* t288 int +--* t299 int N2521 ( 22, 18) [003760] Jc-XG--N--- * AND void REG NA N001 ( 1, 1) [004349] ----------Z t4349 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004350] ----------z t4350 = LCL_VAR int V14 loc10 x3 REG x3 N2523 ( 24, 20) [000289] ---XG------ * JTRUE void REG NA $VN.Void ------------ BB201 [000..64D) -> BB204 (cond), preds={BB200} succs={BB203,BB204} N2527 (???,???) [004076] ----------- IL_OFFSET void INLRT @ 0x626[E-] REG NA N2529 (???,???) [004077] ----------- IL_OFFSET void INLRT @ 0x634[E-] REG NA N2531 ( 1, 1) [000303] ----------z t303 = LCL_VAR int V16 loc12 u:5 x4 (last use) REG x4 $898 /--* t303 int N2533 ( 1, 3) [000310] DA--------- * STORE_LCL_VAR int V51 tmp11 d:1 x4 REG x4 N2535 (???,???) [004078] ----------- IL_OFFSET void INLRT @ 0x634[E-] REG NA N2537 ( 1, 1) [000304] ----------- t304 = LCL_VAR int V51 tmp11 u:1 x4 (last use) REG x4 $898 N2539 ( 1, 2) [000305] -c--------- t305 = CNS_INT int 1 REG NA $c1 /--* t304 int +--* t305 int N2541 ( 3, 4) [000306] ----------- t306 = * ADD int REG x4 $952 /--* t306 int N2543 ( 3, 4) [000308] DA--------- * STORE_LCL_VAR int V16 loc12 d:12 NA REG NA N2545 ( 1, 1) [003667] ----------- t3667 = LCL_VAR int V176 cse5 x13 (last use) REG x13 /--* t3667 int N2547 ( 1, 3) [002283] DA--G------ * STORE_LCL_VAR int V123 tmp83 d:1 x13 REG x13 N2549 (???,???) [004079] ----------- IL_OFFSET void INL53 @ 0x000[E-] <- INLRT @ ??? REG NA N2551 ( 1, 1) [000301] ----------- t301 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t301 byref N2553 ( 3, 4) [003027] -c--------- t3027 = * LEA(b+8) byref REG NA /--* t3027 byref N2555 ( 4, 3) [002244] ---XG------ t2244 = * IND int REG x11 /--* t2244 int N2557 ( 4, 3) [002246] DA-XG------ * STORE_LCL_VAR int V122 tmp82 d:1 x11 REG x11 N2559 (???,???) [004080] ----------- IL_OFFSET void INL53 @ 0x007[E-] <- INLRT @ ??? REG NA N2561 ( 1, 1) [002247] ----------- t2247 = LCL_VAR int V122 tmp82 u:1 x11 REG x11 N2563 ( 1, 1) [002248] ----------- t2248 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2248 byref N2565 ( 3, 4) [003031] -c--------- t3031 = * LEA(b+24) byref REG NA /--* t3031 byref N2567 ( 4, 3) [002286] n---GO----- t2286 = * IND int REG x14 /--* t2247 int +--* t2286 int N2569 ( 6, 5) [002252] N---GO-N-U- * GE void REG NA N2571 ( 8, 7) [002253] ----GO----- * JTRUE void REG NA $845 ------------ BB203 [000..000) -> BB245 (always), preds={BB201} succs={BB245} N2575 (???,???) [004081] ----------- IL_OFFSET void INL53 @ 0x015[E-] <- INLRT @ ??? REG NA N2577 ( 1, 1) [003035] ----------- t3035 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N2579 ( 1, 2) [003036] -c--------- t3036 = CNS_INT long 16 REG NA $200 /--* t3035 byref +--* t3036 long N2581 ( 3, 4) [003037] -----O----- t3037 = * ADD byref REG x14 $25c /--* t3037 byref N2583 ( 3, 4) [002262] DA--GO----- * STORE_LCL_VAR byref V124 tmp84 d:1 x14 REG x14 N2585 ( 1, 1) [002259] ----------- t2259 = LCL_VAR int V122 tmp82 u:1 x11 REG x11 N2587 ( 1, 1) [002264] ----------- t2264 = LCL_VAR byref V124 tmp84 u:1 x14 REG x14 $25c /--* t2264 byref N2589 ( 3, 4) [003040] -c--------- t3040 = * LEA(b+8) byref REG NA /--* t3040 byref N2591 ( 4, 3) [002265] n---GO----- t2265 = * IND int REG x12 /--* t2259 int +--* t2265 int N2593 ( 9, 11) [002266] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2595 ( 1, 1) [002263] ----------- t2263 = LCL_VAR byref V124 tmp84 u:1 x14 (last use) REG x14 $25c /--* t2263 byref N2597 ( 3, 2) [002270] n---GO----- t2270 = * IND byref REG x14 N2599 ( 1, 1) [002260] ----------- t2260 = LCL_VAR int V122 tmp82 u:1 x11 REG x11 /--* t2260 int N2601 ( 2, 3) [002267] -c-------U- t2267 = * CAST long <- uint REG NA N2603 ( 1, 2) [002268] -c--------- t2268 = CNS_INT long 1 REG NA $204 /--* t2267 long +--* t2268 long N2605 ( 4, 6) [002269] -c--------- t2269 = * BFIZ long REG NA /--* t2270 byref +--* t2269 long N2607 ( 8, 9) [002271] -c--------- t2271 = * LEA(b+(i*1)+0) byref REG NA N2609 ( 1, 1) [002273] ----------- t2273 = LCL_VAR int V123 tmp83 u:1 x13 (last use) REG x13 /--* t2271 byref +--* t2273 int N2611 (???,???) [004082] -A-XGO----- * STOREIND short REG NA N2613 (???,???) [004083] ----------- IL_OFFSET void INL53 @ 0x023[E-] <- INLRT @ ??? REG NA N2615 ( 1, 1) [002277] ----------- t2277 = LCL_VAR int V122 tmp82 u:1 x11 (last use) REG x11 N2617 ( 1, 2) [002278] -c--------- t2278 = CNS_INT int 1 REG NA $c1 /--* t2277 int +--* t2278 int N2619 ( 3, 4) [002279] ----------- t2279 = * ADD int REG x13 N2621 ( 1, 1) [002276] ----------- t2276 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2276 byref N2623 ( 3, 4) [003043] -c--------- t3043 = * LEA(b+8) byref REG NA /--* t3043 byref +--* t2279 int N2625 (???,???) [004084] -A--GO----- * STOREIND int REG NA ------------ BB204 [000..000) -> BB245 (always), preds={BB201} succs={BB245} N001 ( 1, 1) [004470] ----------Z t4470 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004471] ----------Z t4471 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004472] ----------Z t4472 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004473] ----------Z t4473 = LCL_VAR int V144 tmp104 x8 REG x8 N2629 (???,???) [004085] ----------- IL_OFFSET void INL53 @ 0x02D[E-] <- INLRT @ ??? REG NA N2631 ( 1, 1) [002254] ----------- t2254 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2254 byref N2633 (???,???) [004280] ----------- t4280 = * PUTARG_REG byref REG x0 N2635 ( 1, 1) [002255] ----------- t2255 = LCL_VAR int V123 tmp83 u:1 x13 (last use) REG x13 /--* t2255 int N2637 (???,???) [004281] ----------- t4281 = * PUTARG_REG int REG x1 N2639 ( 2, 8) [003044] H---------- t3044 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3044 long N2641 (???,???) [004282] ----------- t4282 = * PUTARG_REG long REG x11 /--* t4280 byref this in x0 +--* t4281 int arg2 in x1 +--* t4282 long r2r cell in x11 N2643 ( 18, 15) [002256] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004474] ----------z t4474 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004475] ----------z t4475 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004476] ----------z t4476 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004477] ----------z t4477 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB205 [64D..65A) -> BB227 (cond), preds={BB139,BB142} succs={BB206,BB227} N2647 (???,???) [004086] ----------- IL_OFFSET void INLRT @ 0x64D[E-] REG NA N2649 ( 1, 2) [003045] -c--------- t3045 = CNS_INT int 0 REG NA $c0 /--* t3045 int N2651 ( 1, 3) [000325] DA--------- * STORE_LCL_VAR int V37 loc33 d:1 x11 REG x11 N2653 (???,???) [004087] ----------- IL_OFFSET void INLRT @ 0x650[E-] REG NA N2655 ( 1, 2) [000326] -c--------- t326 = CNS_INT int 0 REG NA $c0 /--* t326 int N2657 ( 1, 3) [000328] DA--------- * STORE_LCL_VAR int V38 loc34 d:1 x14 REG x14 N2659 (???,???) [004088] ----------- IL_OFFSET void INLRT @ 0x653[E-] REG NA N2661 ( 1, 1) [000329] ----------z t329 = LCL_VAR int V09 loc5 u:3 x5 REG x5 $4c6 N2663 ( 1, 2) [000330] -c--------- t330 = CNS_INT int 0 REG NA $c0 /--* t329 int +--* t330 int N2665 ( 3, 4) [000331] CEQ-------N--- * JCMP void REG NA ------------ BB206 [65A..665) -> BB208 (cond), preds={BB205} succs={BB207,BB208} N2669 (???,???) [004089] ----------- IL_OFFSET void INLRT @ 0x65A[E-] REG NA N2671 ( 1, 1) [000419] ----------z t419 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2673 ( 1, 1) [003702] ----------- t3702 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t419 int +--* t3702 int N2675 ( 3, 3) [000424] J------N--- * GE void REG NA $94d N2677 ( 5, 5) [000425] ----------- * JTRUE void REG NA $VN.Void ------------ BB207 [665..672) -> BB218 (cond), preds={BB206} succs={BB208,BB218} N2681 (???,???) [004090] ----------- IL_OFFSET void INLRT @ 0x665[E-] REG NA N2683 ( 1, 1) [000565] ----------- t565 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2685 ( 1, 1) [000566] ----------- t566 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 /--* t566 int N2687 ( 2, 3) [000567] -c--------- t567 = * CAST long <- int REG NA $3e5 N2689 ( 1, 2) [000569] -c--------- t569 = CNS_INT long 1 REG NA $204 /--* t567 long +--* t569 long N2691 ( 4, 6) [000570] -c--------- t570 = * BFIZ long REG NA /--* t565 long +--* t570 long N2693 ( 6, 8) [000571] -c--------- t571 = * LEA(b+(i*1)+0) long REG NA /--* t571 long N2695 ( 9, 10) [000572] ---XG------ t572 = * IND ushort REG x12 /--* t572 ushort N2697 ( 9, 10) [003669] DA-XG------ * STORE_LCL_VAR int V176 cse5 x12 REG x12 N2699 ( 1, 1) [003670] ----------- t3670 = LCL_VAR int V176 cse5 x12 (last use) REG x12 N2701 ( 1, 2) [000573] -c--------- t573 = CNS_INT int 48 REG NA $d8 /--* t3670 int +--* t573 int N2703 ( 12, 14) [000574] N--XG--N-U- * EQ void REG NA N2705 ( 14, 16) [000575] ---XG------ * JTRUE void REG NA $87a ------------ BB208 [67A..687) -> BB215 (cond), preds={BB206,BB207} succs={BB209,BB215} N2709 (???,???) [004091] ----------- IL_OFFSET void INLRT @ 0x67A[E-] REG NA N2711 ( 1, 1) [000426] ----------- t426 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2713 ( 1, 2) [000427] -c--------- t427 = CNS_INT int 1 REG NA $c1 /--* t426 int +--* t427 int N2715 ( 3, 4) [000428] ----------- t428 = * ADD int REG x12 $952 N2717 ( 1, 1) [003703] ----------- t3703 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t428 int +--* t3703 int N2719 ( 5, 6) [000433] J------N--- * GE void REG NA $9e2 N2721 ( 7, 8) [000434] ----------- * JTRUE void REG NA $VN.Void ------------ BB209 [687..694) -> BB213 (cond), preds={BB208} succs={BB210,BB213} N2725 (???,???) [004092] ----------- IL_OFFSET void INLRT @ 0x687[E-] REG NA N2727 ( 1, 1) [000538] ----------- t538 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2729 ( 1, 1) [000539] ----------- t539 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 /--* t539 int N2731 ( 2, 3) [000540] -c--------- t540 = * CAST long <- int REG NA $3e5 N2733 ( 1, 2) [000542] -c--------- t542 = CNS_INT long 1 REG NA $204 /--* t540 long +--* t542 long N2735 ( 4, 6) [000543] -c--------- t543 = * BFIZ long REG NA /--* t538 long +--* t543 long N2737 ( 6, 8) [000544] -c--------- t544 = * LEA(b+(i*1)+0) long REG NA /--* t544 long N2739 ( 9, 10) [000545] ---XG------ t545 = * IND ushort REG x12 /--* t545 ushort N2741 ( 9, 10) [003673] DA-XG------ * STORE_LCL_VAR int V176 cse5 x12 REG x12 N2743 ( 1, 1) [003674] ----------- t3674 = LCL_VAR int V176 cse5 x12 REG x12 N2745 ( 1, 2) [000546] -c--------- t546 = CNS_INT int 43 REG NA $d9 /--* t3674 int +--* t546 int N2747 ( 15, 14) [000547] N--XG--N-U- t547 = * NE int REG x15 N2749 ( 1, 1) [000549] ----------- t549 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2751 ( 1, 1) [000550] ----------- t550 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2753 ( 1, 2) [000551] -c--------- t551 = CNS_INT int 1 REG NA $c1 /--* t550 int +--* t551 int N2755 ( 3, 4) [000552] ----------- t552 = * ADD int REG xip0 $952 /--* t552 int N2757 ( 4, 6) [000553] -c--------- t553 = * CAST long <- int REG NA $3f4 N2759 ( 1, 2) [000555] -c--------- t555 = CNS_INT long 1 REG NA $204 /--* t553 long +--* t555 long N2761 ( 6, 9) [000556] -c--------- t556 = * BFIZ long REG NA /--* t549 long +--* t556 long N2763 ( 8, 11) [000557] -c--------- t557 = * LEA(b+(i*1)+0) long REG NA /--* t557 long N2765 ( 11, 13) [000558] ---XG------ t558 = * IND ushort REG xip0 N2767 ( 1, 2) [000559] -c--------- t559 = CNS_INT int 48 REG NA $d8 /--* t558 ushort +--* t559 int N2769 ( 16, 16) [000560] N--XG--N-U- t560 = * NE int REG xip0 /--* t547 int +--* t560 int N2771 ( 32, 31) [003762] J--XG--N--- t3762 = * AND int REG x15 /--* t3762 int N2773 ( 34, 33) [000548] ---XG------ * JTRUE void REG NA $87a ------------ BB210 [694..6A8) -> BB219 (always), preds={BB209} succs={BB219} N2777 (???,???) [004093] ----------- IL_OFFSET void INLRT @ 0x694[E-] REG NA N2779 (???,???) [004094] ----------- IL_OFFSET void INLRT @ 0x6A3[E-] REG NA N2781 ( 1, 2) [003046] ----------- t3046 = CNS_INT int 1 REG x11 $c1 /--* t3046 int N2783 ( 1, 3) [000564] DA--------- * STORE_LCL_VAR int V37 loc33 d:4 x11 REG x11 ------------ BB213 [6B5..6C2) -> BB215 (cond), preds={BB209} succs={BB214,BB215} N2787 (???,???) [004095] ----------- IL_OFFSET void INLRT @ 0x6B5[E-] REG NA N2789 ( 1, 1) [003676] ----------- t3676 = LCL_VAR int V176 cse5 x12 (last use) REG x12 N2791 ( 1, 2) [000455] -c--------- t455 = CNS_INT int 45 REG NA $da /--* t3676 int +--* t455 int N2793 ( 3, 4) [000456] N---G--N-U- * NE void REG NA N2795 ( 5, 6) [000457] ----G------ * JTRUE void REG NA $87a ------------ BB214 [6C2..6D1) -> BB219 (cond), preds={BB213} succs={BB215,BB219} N2799 (???,???) [004096] ----------- IL_OFFSET void INLRT @ 0x6C2[E-] REG NA N2801 ( 1, 1) [000458] ----------- t458 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2803 ( 1, 1) [000459] ----------- t459 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N2805 ( 1, 2) [000460] -c--------- t460 = CNS_INT int 1 REG NA $c1 /--* t459 int +--* t460 int N2807 ( 3, 4) [000461] ----------- t461 = * ADD int REG x12 $952 /--* t461 int N2809 ( 4, 6) [000462] -c--------- t462 = * CAST long <- int REG NA $3f4 N2811 ( 1, 2) [000464] -c--------- t464 = CNS_INT long 1 REG NA $204 /--* t462 long +--* t464 long N2813 ( 6, 9) [000465] -c--------- t465 = * BFIZ long REG NA /--* t458 long +--* t465 long N2815 ( 8, 11) [000466] -c--------- t466 = * LEA(b+(i*1)+0) long REG NA /--* t466 long N2817 ( 11, 13) [000467] ---XG------ t467 = * IND ushort REG x12 N2819 ( 1, 2) [000468] -c--------- t468 = CNS_INT int 48 REG NA $d8 /--* t467 ushort +--* t468 int N2821 ( 13, 16) [000469] J--XG--N--- * EQ void REG NA N2823 ( 15, 18) [000470] ---XG------ * JTRUE void REG NA $a11 ------------ BB215 [6D1..6DE) -> BB269 (cond), preds={BB208,BB213,BB214} succs={BB216,BB269} N2827 (???,???) [004097] ----------- IL_OFFSET void INL58 @ 0x000[E-] <- INLRT @ 0x6D1[E-] REG NA N2829 ( 1, 1) [000444] ----------- t444 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t444 byref N2831 ( 3, 4) [003048] -c--------- t3048 = * LEA(b+8) byref REG NA /--* t3048 byref N2833 ( 4, 3) [002302] ---XG------ t2302 = * IND int REG x14 /--* t2302 int N2835 ( 4, 3) [002304] DA-XG------ * STORE_LCL_VAR int V126 tmp86 d:1 x14 REG x14 N2837 (???,???) [004098] ----------- IL_OFFSET void INL58 @ 0x007[E-] <- INLRT @ 0x6D1[E-] REG NA N2839 ( 1, 1) [002305] ----------- t2305 = LCL_VAR int V126 tmp86 u:1 x14 REG x14 N2841 ( 1, 1) [002306] ----------- t2306 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2306 byref N2843 ( 3, 4) [003052] -c--------- t3052 = * LEA(b+24) byref REG NA /--* t3052 byref N2845 ( 4, 3) [002341] n---GO----- t2341 = * IND int REG x11 /--* t2305 int +--* t2341 int N2847 ( 6, 5) [002310] N---GO-N-U- * GE void REG NA N2849 ( 8, 7) [002311] ----GO----- * JTRUE void REG NA $845 ------------ BB216 [6D1..6D2) -> BB245 (always), preds={BB215} succs={BB245} N2853 (???,???) [004099] ----------- IL_OFFSET void INL58 @ 0x015[E-] <- INLRT @ 0x6D1[E-] REG NA N2855 ( 1, 1) [003056] ----------- t3056 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N2857 ( 1, 2) [003057] -c--------- t3057 = CNS_INT long 16 REG NA $200 /--* t3056 byref +--* t3057 long N2859 ( 3, 4) [003058] -----O----- t3058 = * ADD byref REG x11 $25c /--* t3058 byref N2861 ( 3, 4) [002319] DA--GO----- * STORE_LCL_VAR byref V127 tmp87 d:1 x11 REG x11 N2863 (???,???) [004100] ----------- IL_OFFSET void INL58 @ ??? <- INLRT @ 0x6D1[E-] REG NA N2865 ( 1, 1) [002316] ----------- t2316 = LCL_VAR int V126 tmp86 u:1 x14 REG x14 N2867 ( 1, 1) [002321] ----------- t2321 = LCL_VAR byref V127 tmp87 u:1 x11 REG x11 $25c /--* t2321 byref N2869 ( 3, 4) [003061] -c--------- t3061 = * LEA(b+8) byref REG NA /--* t3061 byref N2871 ( 4, 3) [002322] n---GO----- t2322 = * IND int REG x12 /--* t2316 int +--* t2322 int N2873 ( 9, 11) [002323] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N2875 ( 1, 1) [002320] ----------- t2320 = LCL_VAR byref V127 tmp87 u:1 x11 (last use) REG x11 $25c /--* t2320 byref N2877 ( 3, 2) [002327] n---GO----- t2327 = * IND byref REG x11 N2879 ( 1, 1) [002317] ----------- t2317 = LCL_VAR int V126 tmp86 u:1 x14 REG x14 /--* t2317 int N2881 ( 2, 3) [002324] -c-------U- t2324 = * CAST long <- uint REG NA N2883 ( 1, 2) [002325] -c--------- t2325 = CNS_INT long 1 REG NA $204 /--* t2324 long +--* t2325 long N2885 ( 4, 6) [002326] -c--------- t2326 = * BFIZ long REG NA /--* t2327 byref +--* t2326 long N2887 ( 8, 9) [002328] -c--------- t2328 = * LEA(b+(i*1)+0) byref REG NA N2889 ( 1, 1) [002330] ----------- t2330 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t2328 byref +--* t2330 int N2891 (???,???) [004101] -A-XGO----- * STOREIND short REG NA N2893 (???,???) [004102] ----------- IL_OFFSET void INL58 @ 0x023[E-] <- INLRT @ 0x6D1[E-] REG NA N2895 ( 1, 1) [002334] ----------- t2334 = LCL_VAR int V126 tmp86 u:1 x14 (last use) REG x14 N2897 ( 1, 2) [002335] -c--------- t2335 = CNS_INT int 1 REG NA $c1 /--* t2334 int +--* t2335 int N2899 ( 3, 4) [002336] ----------- t2336 = * ADD int REG x13 N2901 ( 1, 1) [002333] ----------- t2333 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2333 byref N2903 ( 3, 4) [003064] -c--------- t3064 = * LEA(b+8) byref REG NA /--* t3064 byref +--* t2336 int N2905 (???,???) [004103] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004478] ----------Z t4478 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004479] ----------Z t4479 = LCL_VAR bool V09 loc5 x5 REG x5 N001 ( 1, 1) [004480] ----------z t4480 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB269 [???..???) -> BB244 (always), preds={BB215} succs={BB244} N001 ( 1, 1) [004351] ----------Z t4351 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004352] ----------Z t4352 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004353] ----------Z t4353 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004354] ----------Z t4354 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004355] ----------Z t4355 = LCL_VAR bool V09 loc5 x5 REG x5 ------------ BB218 [6DE..6E4), preds={BB207,BB271} succs={BB219} N2909 (???,???) [004104] ----------- IL_OFFSET void INLRT @ 0x6DE[E-] REG NA N2911 ( 1, 1) [000533] ----------- t533 = LCL_VAR int V38 loc34 u:5 x14 (last use) REG x14 $b0d N2913 ( 1, 2) [000534] -c--------- t534 = CNS_INT int 1 REG NA $c1 /--* t533 int +--* t534 int N2915 ( 3, 4) [000535] ----------- t535 = * ADD int REG x14 $c59 /--* t535 int N2917 ( 3, 4) [000537] DA--------- * STORE_LCL_VAR int V38 loc34 d:6 x14 REG x14 ------------ BB219 [6E4..6F4) -> BB221 (cond), preds={BB210,BB214,BB218} succs={BB220,BB221} N2921 (???,???) [004105] ----------- IL_OFFSET void INLRT @ 0x6E4[E-] REG NA N2923 ( 1, 1) [000471] ----------- t471 = LCL_VAR int V16 loc12 u:9 x4 (last use) REG x4 $b0e N2925 ( 1, 2) [000472] -c--------- t472 = CNS_INT int 1 REG NA $c1 /--* t471 int +--* t472 int N2927 ( 3, 4) [000473] ----------- t473 = * ADD int REG x4 $c5c /--* t473 int N2929 ( 3, 4) [000475] DA--------- * STORE_LCL_VAR int V54 tmp14 d:1 x4 REG x4 N2931 ( 1, 1) [000477] ----------- t477 = LCL_VAR int V54 tmp14 u:1 x4 (last use) REG x4 $c5c /--* t477 int N2933 ( 1, 3) [000479] DA--------- * STORE_LCL_VAR int V16 loc12 d:10 x12 REG x12 N2935 ( 1, 1) [000476] ----------- t476 = LCL_VAR int V16 loc12 u:10 x12 REG x12 $c5c N2937 ( 1, 1) [003704] ----------- t3704 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t476 int +--* t3704 int N2939 ( 3, 3) [000484] J------N--- * GE void REG NA $c5d N2941 ( 5, 5) [000485] ----------- * JTRUE void REG NA $VN.Void ------------ BB220 [6F4..701) -> BB271 (cond), preds={BB219} succs={BB270,BB271} N2945 (???,???) [004106] ----------- IL_OFFSET void INLRT @ 0x6F4[E-] REG NA N2947 ( 1, 1) [000522] ----------- t522 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N2949 ( 1, 1) [000523] ----------Z t523 = LCL_VAR int V16 loc12 u:10 x12 REG x12 $c5c /--* t523 int N2951 ( 2, 3) [000524] -c--------- t524 = * CAST long <- int REG NA $ad8 N2953 ( 1, 2) [000526] -c--------- t526 = CNS_INT long 1 REG NA $204 /--* t524 long +--* t526 long N2955 ( 4, 6) [000527] -c--------- t527 = * BFIZ long REG NA /--* t522 long +--* t527 long N2957 ( 6, 8) [000528] -c--------- t528 = * LEA(b+(i*1)+0) long REG NA /--* t528 long N2959 ( 9, 10) [000529] ---XG------ t529 = * IND ushort REG x5 N2961 ( 1, 2) [000530] -c--------- t530 = CNS_INT int 48 REG NA $d8 /--* t529 ushort +--* t530 int N2963 ( 11, 13) [000531] J--XG--N--- * EQ void REG NA N2965 ( 13, 15) [000532] ---XG------ * JTRUE void REG NA $c18 ------------ BB270 [???..???), preds={BB220} succs={BB221} N001 ( 1, 1) [004356] ----------z t4356 = LCL_VAR int V16 loc12 x12 REG x12 ------------ BB221 [701..707) -> BB223 (cond), preds={BB219,BB270} succs={BB222,BB223} N2969 (???,???) [004107] ----------- IL_OFFSET void INLRT @ 0x701[E-] REG NA N2971 ( 1, 1) [000486] ----------- t486 = LCL_VAR int V38 loc34 u:2 x14 REG x14 $b0f N2973 ( 1, 2) [000487] -c--------- t487 = CNS_INT int 10 REG NA $e4 /--* t486 int +--* t487 int N2975 ( 3, 4) [000488] J------N--- * LE void REG NA $c62 N2977 ( 5, 6) [000489] ----------- * JTRUE void REG NA $VN.Void ------------ BB222 [707..70B), preds={BB221} succs={BB223} N2981 (???,???) [004108] ----------- IL_OFFSET void INLRT @ 0x707[E-] REG NA N2983 ( 1, 2) [000519] ----------- t519 = CNS_INT int 10 REG x14 $e4 /--* t519 int N2985 ( 1, 3) [000521] DA--------- * STORE_LCL_VAR int V38 loc34 d:4 x14 REG x14 ------------ BB223 [70B..710) -> BB225 (cond), preds={BB221,BB222} succs={BB224,BB225} N2989 (???,???) [004109] ----------- IL_OFFSET void INLRT @ 0x70B[E-] REG NA N2991 ( 1, 1) [000490] ----------- t490 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t490 long N2993 ( 4, 3) [000491] ---XG------ t491 = * IND ubyte REG x5 N2995 ( 1, 2) [000492] -c--------- t492 = CNS_INT int 0 REG NA $c0 /--* t491 ubyte +--* t492 int N2997 ( 6, 6) [000493] CEQ---XG--N--- * JCMP void REG NA ------------ BB224 [710..71A) -> BB226 (always), preds={BB223} succs={BB226} N3001 (???,???) [004110] ----------- IL_OFFSET void INLRT @ 0x710[E-] REG NA N3003 ( 1, 1) [000512] ----------- t512 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t512 byref N3005 ( 3, 4) [003067] -c--------- t3067 = * LEA(b+4) byref REG NA /--* t3067 byref N3007 ( 4, 3) [000513] n---GO----- t513 = * IND int REG x5 N3009 ( 1, 1) [000514] ----------- t514 = LCL_VAR int V05 loc1 u:3 x28 REG x28 $28d /--* t513 int +--* t514 int N3011 ( 6, 5) [000515] ----GO----- t515 = * SUB int REG x4 /--* t515 int N3013 ( 6, 5) [000517] DA--GO----- * STORE_LCL_VAR int V55 tmp15 d:3 x4 REG x4 N001 ( 1, 1) [004481] ----------Z t4481 = LCL_VAR int V16 loc12 x12 REG x12 N001 ( 1, 1) [004482] ----------Z t4482 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004483] ----------Z t4483 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004484] ----------Z t4484 = LCL_VAR int V144 tmp104 x8 REG x8 ------------ BB271 [???..???) -> BB218 (always), preds={BB220} succs={BB218} N001 ( 1, 1) [004357] ----------z t4357 = LCL_VAR int V16 loc12 x4 REG x4 ------------ BB225 [71A..71B), preds={BB223} succs={BB226} N3017 (???,???) [004111] ----------- IL_OFFSET void INLRT @ 0x71A[E-] REG NA N3019 ( 1, 2) [000495] -c--------- t495 = CNS_INT int 0 REG NA $c0 /--* t495 int N3021 ( 1, 3) [000497] DA--------- * STORE_LCL_VAR int V55 tmp15 d:2 x4 REG x4 N001 ( 1, 1) [004485] ----------Z t4485 = LCL_VAR int V16 loc12 x12 REG x12 N001 ( 1, 1) [004486] ----------Z t4486 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004487] ----------Z t4487 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004488] ----------Z t4488 = LCL_VAR int V144 tmp104 x8 REG x8 ------------ BB226 [71B..731) -> BB245 (always), preds={BB224,BB225} succs={BB245} N3025 (???,???) [004112] ----------- IL_OFFSET void INLRT @ 0x71D[E-] REG NA N3027 ( 1, 1) [000507] ----------- t507 = LCL_VAR int V37 loc33 u:2 x11 (last use) REG x11 $4ca /--* t507 int N3029 (???,???) [004283] ----------- t4283 = * PUTARG_REG int REG x5 N3031 ( 1, 1) [000502] ----------- t502 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t502 byref N3033 (???,???) [004284] ----------- t4284 = * PUTARG_REG byref REG x0 N3035 ( 1, 1) [000503] ----------- t503 = LCL_VAR ref V03 arg3 u:1 x20 REG x20 $180 /--* t503 ref N3037 (???,???) [004285] ----------- t4285 = * PUTARG_REG ref REG x1 N3039 ( 1, 1) [000499] ----------- t499 = LCL_VAR int V55 tmp15 u:1 x4 (last use) REG x4 $b12 /--* t499 int N3041 (???,???) [004286] ----------- t4286 = * PUTARG_REG int REG x2 N3043 ( 1, 1) [000505] ----------- t505 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t505 int N3045 (???,???) [004287] ----------- t4287 = * PUTARG_REG int REG x3 N3047 ( 1, 1) [000506] ----------- t506 = LCL_VAR int V38 loc34 u:3 x14 (last use) REG x14 $b10 /--* t506 int N3049 (???,???) [004288] ----------- t4288 = * PUTARG_REG int REG x4 N3051 ( 2, 8) [003068] H---------- t3068 = CNS_INT(h) long 0x4000000000540240 ftn REG x11 $5e /--* t3068 long N3053 (???,???) [004289] ----------- t4289 = * PUTARG_REG long REG x11 /--* t4283 int arg6 in x5 +--* t4284 byref arg1 in x0 +--* t4285 ref arg2 in x1 +--* t4286 int arg3 in x2 +--* t4287 int arg4 in x3 +--* t4288 int arg5 in x4 +--* t4289 long r2r cell in x11 N3055 ( 22, 23) [000508] --CXG------ * CALL r2r_ind void System.Number:FormatExponent(byref,System.Globalization.NumberFormatInfo,int,ushort,int,bool) REG NA $VN.Void N3057 (???,???) [004113] ----------- IL_OFFSET void INLRT @ 0x72C[E-] REG NA N3059 ( 1, 2) [003069] -c--------- t3069 = CNS_INT int 0 REG NA $c0 /--* t3069 int N3061 ( 1, 3) [000511] DA--------- * STORE_LCL_VAR int V09 loc5 d:4 NA REG NA N001 ( 1, 1) [004489] ----------z t4489 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004490] ----------z t4490 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004491] ----------z t4491 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004492] ----------z t4492 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB227 [731..744) -> BB229 (cond), preds={BB205} succs={BB228,BB229} N3065 (???,???) [004114] ----------- IL_OFFSET void INL61 @ 0x000[E-] <- INLRT @ 0x731[E-] REG NA N3067 ( 1, 1) [000333] ----------- t333 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t333 byref N3069 ( 3, 4) [003071] -c--------- t3071 = * LEA(b+8) byref REG NA /--* t3071 byref N3071 ( 4, 3) [002349] ---XG------ t2349 = * IND int REG x11 /--* t2349 int N3073 ( 4, 3) [002351] DA-XG------ * STORE_LCL_VAR int V129 tmp89 d:1 x11 REG x11 N3075 (???,???) [004115] ----------- IL_OFFSET void INL61 @ 0x007[E-] <- INLRT @ 0x731[E-] REG NA N3077 ( 1, 1) [002352] ----------- t2352 = LCL_VAR int V129 tmp89 u:1 x11 REG x11 N3079 ( 1, 1) [002353] ----------- t2353 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2353 byref N3081 ( 3, 4) [003075] -c--------- t3075 = * LEA(b+24) byref REG NA /--* t3075 byref N3083 ( 4, 3) [002388] n---GO----- t2388 = * IND int REG x14 /--* t2352 int +--* t2388 int N3085 ( 6, 5) [002357] N---GO-N-U- * GE void REG NA N3087 ( 8, 7) [002358] ----GO----- * JTRUE void REG NA $845 ------------ BB228 [731..732) -> BB230 (always), preds={BB227} succs={BB230} N3091 (???,???) [004116] ----------- IL_OFFSET void INL61 @ 0x015[E-] <- INLRT @ 0x731[E-] REG NA N3093 ( 1, 1) [003079] ----------- t3079 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N3095 ( 1, 2) [003080] -c--------- t3080 = CNS_INT long 16 REG NA $200 /--* t3079 byref +--* t3080 long N3097 ( 3, 4) [003081] -----O----- t3081 = * ADD byref REG x14 $25c /--* t3081 byref N3099 ( 3, 4) [002366] DA--GO----- * STORE_LCL_VAR byref V130 tmp90 d:1 x14 REG x14 N3101 (???,???) [004117] ----------- IL_OFFSET void INL61 @ ??? <- INLRT @ 0x731[E-] REG NA N3103 ( 1, 1) [002363] ----------- t2363 = LCL_VAR int V129 tmp89 u:1 x11 REG x11 N3105 ( 1, 1) [002368] ----------- t2368 = LCL_VAR byref V130 tmp90 u:1 x14 REG x14 $25c /--* t2368 byref N3107 ( 3, 4) [003084] -c--------- t3084 = * LEA(b+8) byref REG NA /--* t3084 byref N3109 ( 4, 3) [002369] n---GO----- t2369 = * IND int REG x12 /--* t2363 int +--* t2369 int N3111 ( 9, 11) [002370] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N3113 ( 1, 1) [002367] ----------- t2367 = LCL_VAR byref V130 tmp90 u:1 x14 (last use) REG x14 $25c /--* t2367 byref N3115 ( 3, 2) [002374] n---GO----- t2374 = * IND byref REG x14 N3117 ( 1, 1) [002364] ----------- t2364 = LCL_VAR int V129 tmp89 u:1 x11 REG x11 /--* t2364 int N3119 ( 2, 3) [002371] -c-------U- t2371 = * CAST long <- uint REG NA N3121 ( 1, 2) [002372] -c--------- t2372 = CNS_INT long 1 REG NA $204 /--* t2371 long +--* t2372 long N3123 ( 4, 6) [002373] -c--------- t2373 = * BFIZ long REG NA /--* t2374 byref +--* t2373 long N3125 ( 8, 9) [002375] -c--------- t2375 = * LEA(b+(i*1)+0) byref REG NA N3127 ( 1, 1) [002377] ----------- t2377 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t2375 byref +--* t2377 int N3129 (???,???) [004118] -A-XGO----- * STOREIND short REG NA N3131 (???,???) [004119] ----------- IL_OFFSET void INL61 @ 0x023[E-] <- INLRT @ 0x731[E-] REG NA N3133 ( 1, 1) [002381] ----------- t2381 = LCL_VAR int V129 tmp89 u:1 x11 (last use) REG x11 N3135 ( 1, 2) [002382] -c--------- t2382 = CNS_INT int 1 REG NA $c1 /--* t2381 int +--* t2382 int N3137 ( 3, 4) [002383] ----------- t2383 = * ADD int REG x13 N3139 ( 1, 1) [002380] ----------- t2380 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2380 byref N3141 ( 3, 4) [003087] -c--------- t3087 = * LEA(b+8) byref REG NA /--* t3087 byref +--* t2383 int N3143 (???,???) [004120] -A--GO----- * STOREIND int REG NA ------------ BB229 [731..732), preds={BB227} succs={BB230} N001 ( 1, 1) [004493] ----------Z t4493 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004494] ----------Z t4494 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004495] ----------Z t4495 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004496] ----------Z t4496 = LCL_VAR bool V09 loc5 x5 REG x5 N3147 (???,???) [004121] ----------- IL_OFFSET void INL61 @ 0x02D[E-] <- INLRT @ 0x731[E-] REG NA N3149 ( 1, 1) [002359] ----------- t2359 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2359 byref N3151 (???,???) [004290] ----------- t4290 = * PUTARG_REG byref REG x0 N3153 ( 1, 1) [000334] ----------- t334 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t334 int N3155 (???,???) [004291] ----------- t4291 = * PUTARG_REG int REG x1 N3157 ( 2, 8) [003088] H---------- t3088 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3088 long N3159 (???,???) [004292] ----------- t4292 = * PUTARG_REG long REG x11 /--* t4290 byref this in x0 +--* t4291 int arg2 in x1 +--* t4292 long r2r cell in x11 N3161 ( 18, 15) [002360] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004497] ----------z t4497 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004498] ----------z t4498 = LCL_VAR bool V09 loc5 x5 REG x5 N001 ( 1, 1) [004499] ----------z t4499 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004500] ----------z t4500 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB230 [???..???) -> BB245 (cond), preds={BB228,BB229} succs={BB231,BB245} N3165 (???,???) [004122] ----------- IL_OFFSET void INLRT @ 0x739[E-] REG NA N3167 ( 1, 1) [000336] ----------z t336 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 N3169 ( 1, 1) [003705] ----------- t3705 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t336 int +--* t3705 int N3171 ( 3, 3) [000341] J------N--- * GE void REG NA $94d N001 ( 1, 1) [004358] ----------Z t4358 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004359] ----------Z t4359 = LCL_VAR bool V09 loc5 x5 REG x5 N001 ( 1, 1) [004360] ----------z t4360 = LCL_VAR int V14 loc10 x3 REG x3 N3173 ( 5, 5) [000342] ----------- * JTRUE void REG NA $VN.Void ------------ BB231 [744..751) -> BB233 (cond), preds={BB230} succs={BB232,BB233} N3177 (???,???) [004123] ----------- IL_OFFSET void INLRT @ 0x744[E-] REG NA N3179 ( 1, 1) [000343] ----------- t343 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N3181 ( 1, 1) [000344] ----------z t344 = LCL_VAR int V16 loc12 u:5 x4 REG x4 $898 /--* t344 int N3183 ( 2, 3) [000345] -c--------- t345 = * CAST long <- int REG NA $3e5 N3185 ( 1, 2) [000347] -c--------- t347 = CNS_INT long 1 REG NA $204 /--* t345 long +--* t347 long N3187 ( 4, 6) [000348] -c--------- t348 = * BFIZ long REG NA /--* t343 long +--* t348 long N3189 ( 6, 8) [000349] -c--------- t349 = * LEA(b+(i*1)+0) long REG NA /--* t349 long N3191 ( 9, 10) [000350] ---XG------ t350 = * IND ushort REG x11 /--* t350 ushort N3193 ( 9, 10) [003658] DA-XG------ * STORE_LCL_VAR int V175 cse4 d:1 x11 REG x11 N3195 ( 1, 1) [003659] ----------- t3659 = LCL_VAR int V175 cse4 u:1 x11 REG x11 N3197 ( 1, 2) [000351] -c--------- t351 = CNS_INT int 43 REG NA $d9 /--* t3659 int +--* t351 int N3199 ( 12, 14) [000352] J--XG--N--- * EQ void REG NA N3201 ( 14, 16) [000353] ---XG------ * JTRUE void REG NA $87a ------------ BB232 [751..75E) -> BB239 (cond), preds={BB231} succs={BB233,BB239} N3205 (???,???) [004124] ----------- IL_OFFSET void INLRT @ 0x751[E-] REG NA N3207 ( 1, 1) [003661] ----------- t3661 = LCL_VAR int V175 cse4 u:1 x11 REG x11 N3209 ( 1, 2) [000416] -c--------- t416 = CNS_INT int 45 REG NA $da /--* t3661 int +--* t416 int N3211 ( 3, 4) [000417] N---G--N-U- * NE void REG NA N3213 ( 5, 6) [000418] ----G------ * JTRUE void REG NA $87a ------------ BB233 [000..774) -> BB235 (cond), preds={BB231,BB232} succs={BB234,BB235} N3217 (???,???) [004125] ----------- IL_OFFSET void INLRT @ 0x75E[E-] REG NA N3219 ( 1, 1) [000356] ----------- t356 = LCL_VAR int V16 loc12 u:5 x4 (last use) REG x4 $898 /--* t356 int N3221 ( 1, 3) [000363] DA--------- * STORE_LCL_VAR int V52 tmp12 d:1 x4 REG x4 N3223 (???,???) [004126] ----------- IL_OFFSET void INLRT @ 0x75E[E-] REG NA N3225 ( 1, 1) [000357] ----------- t357 = LCL_VAR int V52 tmp12 u:1 x4 (last use) REG x4 $898 N3227 ( 1, 2) [000358] -c--------- t358 = CNS_INT int 1 REG NA $c1 /--* t357 int +--* t358 int N3229 ( 3, 4) [000359] ----------- t359 = * ADD int REG x4 $952 /--* t359 int N3231 ( 3, 4) [000361] DA--------- * STORE_LCL_VAR int V16 loc12 d:8 NA REG NA N3233 ( 1, 1) [003662] ----------- t3662 = LCL_VAR int V175 cse4 u:1 x11 (last use) REG x11 /--* t3662 int N3235 ( 1, 3) [002435] DA--G------ * STORE_LCL_VAR int V133 tmp93 d:1 x11 REG x11 N3237 (???,???) [004127] ----------- IL_OFFSET void INL64 @ 0x000[E-] <- INLRT @ ??? REG NA N3239 ( 1, 1) [000354] ----------- t354 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t354 byref N3241 ( 3, 4) [003090] -c--------- t3090 = * LEA(b+8) byref REG NA /--* t3090 byref N3243 ( 4, 3) [002396] n---GO----- t2396 = * IND int REG x13 /--* t2396 int N3245 ( 4, 3) [002398] DA--GO----- * STORE_LCL_VAR int V132 tmp92 d:1 x13 REG x13 N3247 (???,???) [004128] ----------- IL_OFFSET void INL64 @ 0x007[E-] <- INLRT @ ??? REG NA N3249 ( 1, 1) [002399] ----------- t2399 = LCL_VAR int V132 tmp92 u:1 x13 REG x13 N3251 ( 1, 1) [002400] ----------- t2400 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2400 byref N3253 ( 3, 4) [003094] -c--------- t3094 = * LEA(b+24) byref REG NA /--* t3094 byref N3255 ( 4, 3) [002438] n---GO----- t2438 = * IND int REG x14 /--* t2399 int +--* t2438 int N3257 ( 6, 5) [002404] N---GO-N-U- * GE void REG NA N3259 ( 8, 7) [002405] ----GO----- * JTRUE void REG NA $845 ------------ BB234 [000..000) -> BB239 (always), preds={BB233} succs={BB239} N3263 (???,???) [004129] ----------- IL_OFFSET void INL64 @ 0x015[E-] <- INLRT @ ??? REG NA N3265 ( 1, 1) [003098] ----------- t3098 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N3267 ( 1, 2) [003099] -c--------- t3099 = CNS_INT long 16 REG NA $200 /--* t3098 byref +--* t3099 long N3269 ( 3, 4) [003100] -----O----- t3100 = * ADD byref REG x14 $25c /--* t3100 byref N3271 ( 3, 4) [002414] DA--GO----- * STORE_LCL_VAR byref V134 tmp94 d:1 x14 REG x14 N3273 ( 1, 1) [002411] ----------- t2411 = LCL_VAR int V132 tmp92 u:1 x13 REG x13 N3275 ( 1, 1) [002416] ----------- t2416 = LCL_VAR byref V134 tmp94 u:1 x14 REG x14 $25c /--* t2416 byref N3277 ( 3, 4) [003103] -c--------- t3103 = * LEA(b+8) byref REG NA /--* t3103 byref N3279 ( 4, 3) [002417] n---GO----- t2417 = * IND int REG x12 /--* t2411 int +--* t2417 int N3281 ( 9, 11) [002418] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N3283 ( 1, 1) [002415] ----------- t2415 = LCL_VAR byref V134 tmp94 u:1 x14 (last use) REG x14 $25c /--* t2415 byref N3285 ( 3, 2) [002422] n---GO----- t2422 = * IND byref REG x14 N3287 ( 1, 1) [002412] ----------- t2412 = LCL_VAR int V132 tmp92 u:1 x13 REG x13 /--* t2412 int N3289 ( 2, 3) [002419] -c-------U- t2419 = * CAST long <- uint REG NA N3291 ( 1, 2) [002420] -c--------- t2420 = CNS_INT long 1 REG NA $204 /--* t2419 long +--* t2420 long N3293 ( 4, 6) [002421] -c--------- t2421 = * BFIZ long REG NA /--* t2422 byref +--* t2421 long N3295 ( 8, 9) [002423] -c--------- t2423 = * LEA(b+(i*1)+0) byref REG NA N3297 ( 1, 1) [002425] ----------- t2425 = LCL_VAR int V133 tmp93 u:1 x11 (last use) REG x11 /--* t2423 byref +--* t2425 int N3299 (???,???) [004130] -A-XGO----- * STOREIND short REG NA N3301 (???,???) [004131] ----------- IL_OFFSET void INL64 @ 0x023[E-] <- INLRT @ ??? REG NA N3303 ( 1, 1) [002429] ----------- t2429 = LCL_VAR int V132 tmp92 u:1 x13 (last use) REG x13 N3305 ( 1, 2) [002430] -c--------- t2430 = CNS_INT int 1 REG NA $c1 /--* t2429 int +--* t2430 int N3307 ( 3, 4) [002431] ----------- t2431 = * ADD int REG x11 N3309 ( 1, 1) [002428] ----------- t2428 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2428 byref N3311 ( 3, 4) [003106] -c--------- t3106 = * LEA(b+8) byref REG NA /--* t3106 byref +--* t2431 int N3313 (???,???) [004132] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004501] ----------z t4501 = LCL_VAR int V16 loc12 x4 REG x4 ------------ BB235 [000..000) -> BB239 (always), preds={BB233} succs={BB239} N001 ( 1, 1) [004502] ----------Z t4502 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004503] ----------Z t4503 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004504] ----------Z t4504 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004505] ----------Z t4505 = LCL_VAR int V144 tmp104 x8 REG x8 N3317 (???,???) [004133] ----------- IL_OFFSET void INL64 @ 0x02D[E-] <- INLRT @ ??? REG NA N3319 ( 1, 1) [002406] ----------- t2406 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2406 byref N3321 (???,???) [004293] ----------- t4293 = * PUTARG_REG byref REG x0 N3323 ( 1, 1) [002407] ----------- t2407 = LCL_VAR int V133 tmp93 u:1 x11 (last use) REG x11 /--* t2407 int N3325 (???,???) [004294] ----------- t4294 = * PUTARG_REG int REG x1 N3327 ( 2, 8) [003107] H---------- t3107 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3107 long N3329 (???,???) [004295] ----------- t4295 = * PUTARG_REG long REG x11 /--* t4293 byref this in x0 +--* t4294 int arg2 in x1 +--* t4295 long r2r cell in x11 N3331 ( 18, 15) [002408] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004506] ----------z t4506 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004507] ----------z t4507 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004508] ----------z t4508 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004509] ----------z t4509 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004510] ----------z t4510 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB236 [000..788) -> BB238 (cond), preds={BB240} succs={BB237,BB238} N3375 (???,???) [004134] ----------- IL_OFFSET void INLRT @ 0x774[E-] REG NA N3377 ( 1, 1) [000392] ----------- t392 = LCL_VAR int V16 loc12 u:6 x4 (last use) REG x4 $b08 /--* t392 int N3379 ( 1, 3) [000399] DA--------- * STORE_LCL_VAR int V53 tmp13 d:1 x4 REG x4 N3381 (???,???) [004135] ----------- IL_OFFSET void INLRT @ 0x774[E-] REG NA N3383 ( 1, 1) [000393] ----------- t393 = LCL_VAR int V53 tmp13 u:1 x4 (last use) REG x4 $b08 N3385 ( 1, 2) [000394] -c--------- t394 = CNS_INT int 1 REG NA $c1 /--* t393 int +--* t394 int N3387 ( 3, 4) [000395] ----------- t395 = * ADD int REG x4 $c47 /--* t395 int N3389 ( 3, 4) [000397] DA--------- * STORE_LCL_VAR int V16 loc12 d:7 NA REG NA N3391 ( 1, 1) [003639] ----------- t3639 = LCL_VAR int V173 cse2 u:1 x11 (last use) REG x11 /--* t3639 int N3393 ( 1, 3) [002481] DA--G------ * STORE_LCL_VAR int V137 tmp97 d:1 x11 REG x11 N3395 (???,???) [004136] ----------- IL_OFFSET void INL66 @ 0x000[E-] <- INLRT @ ??? REG NA N3397 ( 1, 1) [000390] ----------- t390 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t390 byref N3399 ( 3, 4) [003109] -c--------- t3109 = * LEA(b+8) byref REG NA /--* t3109 byref N3401 ( 4, 3) [002442] n---GO----- t2442 = * IND int REG x13 /--* t2442 int N3403 ( 4, 3) [002444] DA--GO----- * STORE_LCL_VAR int V136 tmp96 d:1 x13 REG x13 N3405 (???,???) [004137] ----------- IL_OFFSET void INL66 @ 0x007[E-] <- INLRT @ ??? REG NA N3407 ( 1, 1) [002445] ----------- t2445 = LCL_VAR int V136 tmp96 u:1 x13 REG x13 N3409 ( 1, 1) [002446] ----------- t2446 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2446 byref N3411 ( 3, 4) [003113] -c--------- t3113 = * LEA(b+24) byref REG NA /--* t3113 byref N3413 ( 4, 3) [002484] n---GO----- t2484 = * IND int REG x14 /--* t2445 int +--* t2484 int N3415 ( 6, 5) [002450] N---GO-N-U- * GE void REG NA N3417 ( 8, 7) [002451] ----GO----- * JTRUE void REG NA $845 ------------ BB237 [000..000) -> BB239 (always), preds={BB236} succs={BB239} N3421 (???,???) [004138] ----------- IL_OFFSET void INL66 @ 0x015[E-] <- INLRT @ ??? REG NA N3423 ( 1, 1) [003117] ----------- t3117 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N3425 ( 1, 2) [003118] -c--------- t3118 = CNS_INT long 16 REG NA $200 /--* t3117 byref +--* t3118 long N3427 ( 3, 4) [003119] -----O----- t3119 = * ADD byref REG x14 $25c /--* t3119 byref N3429 ( 3, 4) [002460] DA--GO----- * STORE_LCL_VAR byref V138 tmp98 d:1 x14 REG x14 N3431 ( 1, 1) [002457] ----------- t2457 = LCL_VAR int V136 tmp96 u:1 x13 REG x13 N3433 ( 1, 1) [002462] ----------- t2462 = LCL_VAR byref V138 tmp98 u:1 x14 REG x14 $25c /--* t2462 byref N3435 ( 3, 4) [003122] -c--------- t3122 = * LEA(b+8) byref REG NA /--* t3122 byref N3437 ( 4, 3) [002463] n---GO----- t2463 = * IND int REG x12 /--* t2457 int +--* t2463 int N3439 ( 9, 11) [002464] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N3441 ( 1, 1) [002461] ----------- t2461 = LCL_VAR byref V138 tmp98 u:1 x14 (last use) REG x14 $25c /--* t2461 byref N3443 ( 3, 2) [002468] n---GO----- t2468 = * IND byref REG x14 N3445 ( 1, 1) [002458] ----------- t2458 = LCL_VAR int V136 tmp96 u:1 x13 REG x13 /--* t2458 int N3447 ( 2, 3) [002465] -c-------U- t2465 = * CAST long <- uint REG NA N3449 ( 1, 2) [002466] -c--------- t2466 = CNS_INT long 1 REG NA $204 /--* t2465 long +--* t2466 long N3451 ( 4, 6) [002467] -c--------- t2467 = * BFIZ long REG NA /--* t2468 byref +--* t2467 long N3453 ( 8, 9) [002469] -c--------- t2469 = * LEA(b+(i*1)+0) byref REG NA N3455 ( 1, 1) [002471] ----------- t2471 = LCL_VAR int V137 tmp97 u:1 x11 (last use) REG x11 /--* t2469 byref +--* t2471 int N3457 (???,???) [004139] -A-XGO----- * STOREIND short REG NA N3459 (???,???) [004140] ----------- IL_OFFSET void INL66 @ 0x023[E-] <- INLRT @ ??? REG NA N3461 ( 1, 1) [002475] ----------- t2475 = LCL_VAR int V136 tmp96 u:1 x13 (last use) REG x13 N3463 ( 1, 2) [002476] -c--------- t2476 = CNS_INT int 1 REG NA $c1 /--* t2475 int +--* t2476 int N3465 ( 3, 4) [002477] ----------- t2477 = * ADD int REG x11 N3467 ( 1, 1) [002474] ----------- t2474 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2474 byref N3469 ( 3, 4) [003125] -c--------- t3125 = * LEA(b+8) byref REG NA /--* t3125 byref +--* t2477 int N3471 (???,???) [004141] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004511] ----------z t4511 = LCL_VAR int V16 loc12 x4 REG x4 ------------ BB238 [000..000), preds={BB236} succs={BB239} N001 ( 1, 1) [004512] ----------Z t4512 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004513] ----------Z t4513 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004514] ----------Z t4514 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004515] ----------Z t4515 = LCL_VAR int V144 tmp104 x8 REG x8 N3475 (???,???) [004142] ----------- IL_OFFSET void INL66 @ 0x02D[E-] <- INLRT @ ??? REG NA N3477 ( 1, 1) [002452] ----------- t2452 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2452 byref N3479 (???,???) [004296] ----------- t4296 = * PUTARG_REG byref REG x0 N3481 ( 1, 1) [002453] ----------- t2453 = LCL_VAR int V137 tmp97 u:1 x11 (last use) REG x11 /--* t2453 int N3483 (???,???) [004297] ----------- t4297 = * PUTARG_REG int REG x1 N3485 ( 2, 8) [003126] H---------- t3126 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3126 long N3487 (???,???) [004298] ----------- t4298 = * PUTARG_REG long REG x11 /--* t4296 byref this in x0 +--* t4297 int arg2 in x1 +--* t4298 long r2r cell in x11 N3489 ( 18, 15) [002454] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004516] ----------z t4516 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004517] ----------z t4517 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004518] ----------z t4518 = LCL_VAR int V16 loc12 x4 REG x4 N001 ( 1, 1) [004519] ----------z t4519 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004520] ----------z t4520 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB239 [788..793) -> BB245 (cond), preds={BB232,BB234,BB235,BB237,BB238} succs={BB240,BB245} N3335 (???,???) [004143] ----------- IL_OFFSET void INLRT @ 0x788[E-] REG NA N3337 ( 1, 1) [000372] ----------- t372 = LCL_VAR int V16 loc12 u:6 x4 REG x4 $b08 N3339 ( 1, 1) [003706] ----------- t3706 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t372 int +--* t3706 int N3341 ( 3, 3) [000377] J------N--- * GE void REG NA $c42 N001 ( 1, 1) [004361] ----------Z t4361 = LCL_VAR int V16 loc12 x4 REG x4 N3343 ( 5, 5) [000378] ----------- * JTRUE void REG NA $VN.Void ------------ BB240 [793..7A0) -> BB236 (cond), preds={BB239} succs={BB241,BB236} N3347 (???,???) [004144] ----------- IL_OFFSET void INLRT @ 0x793[E-] REG NA N3349 ( 1, 1) [000379] ----------- t379 = LCL_VAR long V34 loc30 u:1 x24 REG x24 $3c4 N3351 ( 1, 1) [000380] ----------z t380 = LCL_VAR int V16 loc12 u:6 x4 REG x4 $b08 /--* t380 int N3353 ( 2, 3) [000381] -c--------- t381 = * CAST long <- int REG NA $ad1 N3355 ( 1, 2) [000383] -c--------- t383 = CNS_INT long 1 REG NA $204 /--* t381 long +--* t383 long N3357 ( 4, 6) [000384] -c--------- t384 = * BFIZ long REG NA /--* t379 long +--* t384 long N3359 ( 6, 8) [000385] -c--------- t385 = * LEA(b+(i*1)+0) long REG NA /--* t385 long N3361 ( 9, 10) [000386] ---XG------ t386 = * IND ushort REG x11 /--* t386 ushort N3363 ( 9, 10) [003641] DA-XG------ * STORE_LCL_VAR int V173 cse2 d:1 x11 REG x11 N3365 ( 1, 1) [003642] ----------- t3642 = LCL_VAR int V173 cse2 u:1 x11 REG x11 N3367 ( 1, 2) [000387] -c--------- t387 = CNS_INT int 48 REG NA $d8 /--* t3642 int +--* t387 int N3369 ( 12, 14) [000388] J--XG--N--- * EQ void REG NA N3371 ( 14, 16) [000389] ---XG------ * JTRUE void REG NA $c02 ------------ BB241 [7A0..7A2) -> BB245 (always), preds={BB240} succs={BB245} N001 ( 1, 1) [004521] ----------Z t4521 = LCL_VAR int V16 loc12 x4 REG x4 ------------ BB242 [7A2..7AA) -> BB272 (cond), preds={BB140,BB143,BB257(2),BB258(2)} succs={BB243,BB272} N3495 (???,???) [004145] ----------- IL_OFFSET void INL69 @ 0x000[E-] <- INLRT @ 0x7A2[E-] REG NA N3497 ( 1, 1) [000590] ----------- t590 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t590 byref N3499 ( 3, 4) [003128] -c--------- t3128 = * LEA(b+8) byref REG NA /--* t3128 byref N3501 ( 4, 3) [002492] ---XG------ t2492 = * IND int REG x11 /--* t2492 int N3503 ( 4, 3) [002494] DA-XG------ * STORE_LCL_VAR int V140 tmp100 d:1 x11 REG x11 N3505 (???,???) [004146] ----------- IL_OFFSET void INL69 @ 0x007[E-] <- INLRT @ 0x7A2[E-] REG NA N3507 ( 1, 1) [002495] ----------- t2495 = LCL_VAR int V140 tmp100 u:1 x11 REG x11 N3509 ( 1, 1) [002496] ----------- t2496 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2496 byref N3511 ( 3, 4) [003132] -c--------- t3132 = * LEA(b+24) byref REG NA /--* t3132 byref N3513 ( 4, 3) [002531] n---GO----- t2531 = * IND int REG x14 /--* t2495 int +--* t2531 int N3515 ( 6, 5) [002500] N---GO-N-U- * GE void REG NA N3517 ( 8, 7) [002501] ----GO----- * JTRUE void REG NA $845 ------------ BB243 [7A2..7A3) -> BB245 (always), preds={BB242} succs={BB245} N3521 (???,???) [004147] ----------- IL_OFFSET void INL69 @ 0x015[E-] <- INLRT @ 0x7A2[E-] REG NA N3523 ( 1, 1) [003136] ----------- t3136 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 N3525 ( 1, 2) [003137] -c--------- t3137 = CNS_INT long 16 REG NA $200 /--* t3136 byref +--* t3137 long N3527 ( 3, 4) [003138] -----O----- t3138 = * ADD byref REG x14 $25c /--* t3138 byref N3529 ( 3, 4) [002509] DA--GO----- * STORE_LCL_VAR byref V141 tmp101 d:1 x14 REG x14 N3531 (???,???) [004148] ----------- IL_OFFSET void INL69 @ ??? <- INLRT @ 0x7A2[E-] REG NA N3533 ( 1, 1) [002506] ----------- t2506 = LCL_VAR int V140 tmp100 u:1 x11 REG x11 N3535 ( 1, 1) [002511] ----------- t2511 = LCL_VAR byref V141 tmp101 u:1 x14 REG x14 $25c /--* t2511 byref N3537 ( 3, 4) [003141] -c--------- t3141 = * LEA(b+8) byref REG NA /--* t3141 byref N3539 ( 4, 3) [002512] n---GO----- t2512 = * IND int REG x12 /--* t2506 int +--* t2512 int N3541 ( 9, 11) [002513] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA N3543 ( 1, 1) [002510] ----------- t2510 = LCL_VAR byref V141 tmp101 u:1 x14 (last use) REG x14 $25c /--* t2510 byref N3545 ( 3, 2) [002517] n---GO----- t2517 = * IND byref REG x14 N3547 ( 1, 1) [002507] ----------- t2507 = LCL_VAR int V140 tmp100 u:1 x11 REG x11 /--* t2507 int N3549 ( 2, 3) [002514] -c-------U- t2514 = * CAST long <- uint REG NA N3551 ( 1, 2) [002515] -c--------- t2515 = CNS_INT long 1 REG NA $204 /--* t2514 long +--* t2515 long N3553 ( 4, 6) [002516] -c--------- t2516 = * BFIZ long REG NA /--* t2517 byref +--* t2516 long N3555 ( 8, 9) [002518] -c--------- t2518 = * LEA(b+(i*1)+0) byref REG NA N3557 ( 1, 1) [002520] ----------- t2520 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t2518 byref +--* t2520 int N3559 (???,???) [004149] -A-XGO----- * STOREIND short REG NA N3561 (???,???) [004150] ----------- IL_OFFSET void INL69 @ 0x023[E-] <- INLRT @ 0x7A2[E-] REG NA N3563 ( 1, 1) [002524] ----------- t2524 = LCL_VAR int V140 tmp100 u:1 x11 (last use) REG x11 N3565 ( 1, 2) [002525] -c--------- t2525 = CNS_INT int 1 REG NA $c1 /--* t2524 int +--* t2525 int N3567 ( 3, 4) [002526] ----------- t2526 = * ADD int REG x13 N3569 ( 1, 1) [002523] ----------- t2523 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2523 byref N3571 ( 3, 4) [003144] -c--------- t3144 = * LEA(b+8) byref REG NA /--* t3144 byref +--* t2526 int N3573 (???,???) [004151] -A--GO----- * STOREIND int REG NA N001 ( 1, 1) [004522] ----------z t4522 = LCL_VAR int V14 loc10 x3 REG x3 ------------ BB272 [???..???) -> BB244 (always), preds={BB242} succs={BB244} N001 ( 1, 1) [004362] ----------Z t4362 = LCL_VAR int V20 loc16 x9 REG x9 N001 ( 1, 1) [004363] ----------Z t4363 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004364] ----------Z t4364 = LCL_VAR int V144 tmp104 x8 REG x8 ------------ BB244 [7A2..7A3) -> BB245 (always), preds={BB269,BB272} succs={BB245} N3577 (???,???) [004152] ----------- IL_OFFSET void INL69 @ 0x02D[E-] <- INLRT @ 0x7A2[E-] REG NA N3579 ( 1, 1) [002502] ----------- t2502 = LCL_VAR byref V00 arg0 u:1 x19 REG x19 $100 /--* t2502 byref N3581 (???,???) [004299] ----------- t4299 = * PUTARG_REG byref REG x0 N3583 ( 1, 1) [000591] ----------- t591 = LCL_VAR int V18 loc14 u:1 x13 (last use) REG x13 /--* t591 int N3585 (???,???) [004300] ----------- t4300 = * PUTARG_REG int REG x1 N3587 ( 2, 8) [003145] H---------- t3145 = CNS_INT(h) long 0x4000000000435c58 ftn REG x11 $53 /--* t3145 long N3589 (???,???) [004301] ----------- t4301 = * PUTARG_REG long REG x11 /--* t4299 byref this in x0 +--* t4300 int arg2 in x1 +--* t4301 long r2r cell in x11 N3591 ( 18, 15) [002503] --CXG------ * CALL r2r_ind void REG NA $VN.Void N001 ( 1, 1) [004523] ----------z t4523 = LCL_VAR long V36 loc32 x0 REG x0 N001 ( 1, 1) [004524] ----------z t4524 = LCL_VAR int V14 loc10 x3 REG x3 N001 ( 1, 1) [004525] ----------z t4525 = LCL_VAR int V144 tmp104 x8 REG x8 N001 ( 1, 1) [004526] ----------z t4526 = LCL_VAR int V20 loc16 x9 REG x9 ------------ BB110 [000..000) (throw), preds={BB91} succs={} N5011 (???,???) [004153] ----------- IL_OFFSET void INL17 @ 0x029[E-] <- INLRT @ ??? REG NA N5013 ( 2, 8) [002701] H---------- t2701 = CNS_INT(h) long 0x4000000000424a20 ftn REG x11 $4a /--* t2701 long N5015 (???,???) [004302] ----------- t4302 = * PUTARG_REG long REG x11 /--* t4302 long r2r cell in x11 N5017 ( 16, 11) [001630] --CXG------ * CALL r2r_ind void System.ThrowHelper:ThrowArgumentException_DestinationTooShort() REG NA $VN.Void ------------ BB254 [???..???) (throw), preds={} succs={} N5021 ( 2, 8) [004303] H---------- t4303 = CNS_INT(h) long 0x4000000000421828 ftn REG x0 /--* t4303 long N5023 ( 5, 10) [004304] ----------- t4304 = * IND long REG x0 /--* t4304 long control expr N5025 ( 14, 2) [004154] --CXG------ * CALL help void CORINFO_HELP_RNGCHKFAIL REG NA ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Place 'align' instructions *************** Finishing PHASE Place 'align' instructions [no changes] *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..061)-> BB10 ( cond ) i bwd LIR BB255 [0364] 1 BB09 8 [061..083)-> BB31,BB17,BB259,BB30,BB259,BB31 (switch) i bwd LIR BB259 [0368] 2 BB255(2) 4 [???..???)-> BB47 (always) internal bwd LIR BB10 [0009] 1 BB09 8 1 [083..083)-> BB11 ( cond ) i bwd LIR BB256 [0365] 1 BB10 8 [083..0A1)-> BB23,BB260,BB21,BB260,BB18 (switch) i bwd LIR BB260 [0369] 2 BB256(2) 4 [???..???)-> BB47 (always) internal bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB255 8 1 [0CF..0D8)-> BB47 (always) i bwd LIR BB18 [0017] 1 BB256 8 1 [0D8..0E0)-> BB20 ( cond ) i bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i bwd LIR BB21 [0020] 1 BB256 8 1 [0ED..0F4)-> BB47 ( cond ) i bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB256 8 1 [0FB..102)-> BB47 ( cond ) i bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i bwd LIR BB30 [0029] 1 BB255 8 1 [12C..137)-> BB47 (always) i bwd LIR BB31 [0031] 3 BB32,BB255(2) 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i bwd LIR BB261 [0370] 1 BB43 4 [???..???) internal bwd LIR BB44 [0044] 3 BB39,BB45,BB261 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i bwd LIR BB47 [0047] 22 BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB259,BB260 64 1 [204..20F)-> BB50 ( cond ) i bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB262 ( cond ) i idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB262 [0371] 1 BB78 0.50 [???..???)-> BB103 (always) internal LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i bwd LIR BB103 [0096] 4 BB85,BB89,BB102,BB262 1 [3C8..3D0)-> BB112 ( cond ) i LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i LIR BB245 [0190] 25 BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB266,BB268 8 3 [7AA..7B5)-> BB248 ( cond ) i bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB263 ( cond ) i Loop Loop0 bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB264 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB264 [0373] 1 BB115 1 [???..???)-> BB135 (always) internal bwd LIR BB263 [0372] 1 BB113 1 [???..???)-> BB136 (always) internal bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB265 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB265 [0374] 1 BB125 4 [???..???)-> BB134 (always) internal bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal bwd LIR BB134 [0114] 3 BB124,BB133,BB265 8 3 [461..46D) i bwd LIR BB135 [0115] 3 BB114,BB134,BB264 16 3 [46D..472)-> BB118 ( cond ) i bwd bwd-src LIR BB136 [0116] 3 BB117,BB135,BB263 2 3 [472..478)-> BB141 ( cond ) i bwd LIR BB137 [0117] 1 BB136 2 3 [478..478)-> BB138 ( cond ) i bwd LIR BB257 [0366] 1 BB137 2 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194 (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..49A)-> BB139 ( cond ) i bwd LIR BB258 [0367] 1 BB138 2 [49A..4B8)-> BB266,BB242,BB171,BB242,BB145 (switch) i bwd LIR BB266 [0375] 1 BB258 1 [???..???)-> BB245 (always) internal bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB257,BB258 2 3 [4E9..4EE)-> BB150 ( cond ) i bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB267 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB267 [0376] 1 BB161 1 [???..???)-> BB170 (always) internal bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal bwd LIR BB170 [0142] 4 BB156,BB160,BB169,BB267 2 3 [559..564)-> BB245 (always) i bwd LIR BB171 [0143] 1 BB258 2 3 [564..571)-> BB245 ( cond ) i bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i hascall gcsafe bwd LIR BB186 [0149] 1 BB257 2 3 [5A9..5BA)-> BB245 ( cond ) i bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal hascall gcsafe bwd LIR BB194 [0151] 4 BB192,BB193,BB257(2) 16 3 [5CE..5D9)-> BB197 ( cond ) i bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB268 ( cond ) i bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB268 [0377] 1 BB197 1 [???..???)-> BB245 (always) internal bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB269 ( cond ) i bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB269 [0378] 1 BB215 1 [???..???)-> BB244 (always) internal bwd LIR BB218 [0172] 2 BB207,BB271 8 3 [6DE..6E4) i Loop Loop0 bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB271 ( cond ) i bwd bwd-src LIR BB270 [0379] 1 BB220 8 [???..???) internal bwd LIR BB221 [0175] 2 BB219,BB270 2 3 [701..707)-> BB223 ( cond ) i bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB271 [0380] 1 BB220 8 [???..???)-> BB218 (always) internal bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB140,BB143,BB257(2),BB258(2) 2 3 [7A2..7AA)-> BB272 ( cond ) i bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB272 [0381] 1 BB242 1 [???..???)-> BB244 (always) internal bwd LIR BB244 [0355] 2 BB269,BB272 2 3 [7A2..7A3)-> BB245 (always) i hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare hascall gcsafe bwd LIR BB254 [0363] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(x19) V03(x20) V01(x21) must init V23 because it has a GC ref must init V35 because it has a GC ref Modified regs: [x0-xip1 x19-x28 lr] Callee-saved registers pushed: 12 [x19-x28 fp lr] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Setting genSaveFpLrWithAllCalleeSavedRegisters to false Assign V170 GsCookie, size=8, stkOffs=-0x58 Assign V47 tmp7, size=16, stkOffs=-0x68 Assign V02 arg2, size=16, stkOffs=-0x78 Assign V06 loc2, size=4, stkOffs=-0x7c Assign V07 loc3, size=4, stkOffs=-0x80 Assign V08 loc4, size=4, stkOffs=-0x84 Assign V09 loc5, size=4, stkOffs=-0x88 Assign V12 loc8, size=4, stkOffs=-0x8c Assign V14 loc10, size=4, stkOffs=-0x90 Assign V16 loc12, size=4, stkOffs=-0x94 Assign V18 loc14, size=4, stkOffs=-0x98 Assign V20 loc16, size=4, stkOffs=-0x9c Assign V21 loc17, size=4, stkOffs=-0xa0 Assign V23 loc19, size=8, stkOffs=-0xa8 Assign V27 loc23, size=4, stkOffs=-0xac Assign V28 loc24, size=4, stkOffs=-0xb0 Assign V29 loc25, size=4, stkOffs=-0xb4 Assign V30 loc26, size=4, stkOffs=-0xb8 Assign V32 loc28, size=4, stkOffs=-0xbc Pad V35 loc31, size=8, stkOffs=-0xc0, pad=4 Assign V35 loc31, size=8, stkOffs=-0xc8 Assign V36 loc32, size=8, stkOffs=-0xd0 Assign V144 tmp104, size=4, stkOffs=-0xd4 Pad V26 loc22, size=8, stkOffs=-0xd8, pad=4 Assign V26 loc22, size=8, stkOffs=-0xe0 Assign V33 loc29, size=8, stkOffs=-0xe8 Assign V143 tmp103, size=8, stkOffs=-0xf0 --- delta bump 256 for FP frame --- virtual stack offset to actual stack offset delta is 256 -- V02 was -120, now 136 -- V06 was -124, now 132 -- V07 was -128, now 128 -- V08 was -132, now 124 -- V09 was -136, now 120 -- V12 was -140, now 116 -- V14 was -144, now 112 -- V16 was -148, now 108 -- V18 was -152, now 104 -- V20 was -156, now 100 -- V21 was -160, now 96 -- V23 was -168, now 88 -- V26 was -224, now 32 -- V27 was -172, now 84 -- V28 was -176, now 80 -- V29 was -180, now 76 -- V30 was -184, now 72 -- V32 was -188, now 68 -- V33 was -232, now 24 -- V35 was -200, now 56 -- V36 was -208, now 48 -- V40 was 0, now 256 -- V47 was -104, now 152 -- V143 was -240, now 16 -- V144 was -212, now 44 -- V170 was -88, now 168 ; Final local variable assignments ; ; V00 arg0 [V00,T01] ( 79,265.50) byref -> x19 single-def ; V01 arg1 [V01,T58] ( 17, 21.50) byref -> x21 single-def ; V02 arg2 [V02,T86] ( 5, 8 ) struct (16) [fp+88H] do-not-enreg[SFA] multireg-arg ld-addr-op single-def ptr ; V03 arg3 [V03,T46] ( 12, 22.50) ref -> x20 class-hnd single-def ; V04 loc0 [V04,T08] ( 15, 96 ) int -> x27 ; V05 loc1 [V05,T16] ( 18, 56 ) int -> x28 ; V06 loc2 [V06,T41] ( 9, 30 ) int -> [fp+84H] ptr ; V07 loc3 [V07,T59] ( 7, 23 ) int -> [fp+80H] ptr ; V08 loc4 [V08,T28] ( 14, 47.50) int -> [fp+7CH] ptr ; V09 loc5 [V09,T45] ( 6, 25 ) bool -> [fp+78H] ; V10 loc6 [V10,T30] ( 6, 42 ) int -> x6 ; V11 loc7 [V11,T44] ( 5, 27 ) int -> x22 ; V12 loc8 [V12,T42] ( 6, 29 ) bool -> [fp+74H] ; V13 loc9 [V13,T18] ( 8, 48 ) int -> x8 ; V14 loc10 [V14,T29] ( 11, 42 ) int -> [fp+70H] ptr ; V15 loc11 [V15,T61] ( 6, 19 ) int -> x26 ; V16 loc12 [V16,T00] ( 59,914 ) int -> [fp+6CH] ptr ; V17 loc13 [V17,T63] ( 6, 17 ) long -> x23 ; V18 loc14 [V18,T05] ( 36,238 ) ushort -> [fp+68H] ptr ;* V19 loc15 [V19 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op ; V20 loc16 [V20,T11] ( 16, 71 ) int -> [fp+64H] ptr ; V21 loc17 [V21,T110] ( 3, 5 ) bool -> [fp+60H] ; V22 loc18 [V22,T07] ( 8,184 ) long -> x9 ; V23 loc19 [V23 ] ( 2, 16 ) byref -> [fp+58H] must-init pinned ptr ;* V24 loc20 [V24 ] ( 0, 0 ) int -> zero-ref ;* V25 loc21 [V25 ] ( 0, 0 ) struct (16) zero-ref ; V26 loc22 [V26,T108] ( 5, 5.50) ref -> [fp+20H] class-hnd spill-single-def ptr ; V27 loc23 [V27,T68] ( 6, 12.50) int -> [fp+54H] ptr ; V28 loc24 [V28,T62] ( 7, 17.50) int -> [fp+50H] ptr ; V29 loc25 [V29,T111] ( 3, 5 ) int -> [fp+4CH] spill-single-def ptr ; V30 loc26 [V30,T84] ( 5, 11 ) int -> [fp+48H] ptr ; V31 loc27 [V31,T133] ( 3, 1.50) int -> x0 ; V32 loc28 [V32,T112] ( 3, 5 ) int -> [fp+44H] spill-single-def ptr ; V33 loc29 [V33,T85] ( 5, 10 ) ref -> [fp+18H] class-hnd exact spill-single-def ptr ; V34 loc30 [V34,T12] ( 12, 67 ) long -> x24 ; V35 loc31 [V35 ] ( 2, 2 ) byref -> [fp+38H] must-init pinned ptr ; V36 loc32 [V36,T36] ( 8, 33 ) long -> [fp+30H] ptr ; V37 loc33 [V37,T105] ( 3, 6 ) bool -> x11 ; V38 loc34 [V38,T51] ( 6, 24 ) int -> x14 ;* V39 loc35 [V39 ] ( 0, 0 ) int -> zero-ref ;# V40 OutArgs [V40 ] ( 1, 1 ) lclBlk ( 0) [sp+00H] "OutgoingArgSpace" ;* V41 tmp1 [V41 ] ( 0, 0 ) struct (16) zero-ref ;* V42 tmp2 [V42 ] ( 0, 0 ) struct (16) zero-ref multireg-arg ; V43 tmp3 [V43,T124] ( 4, 2.50) int -> x2 ; V44 tmp4 [V44,T130] ( 2, 2 ) int -> x3 ; V45 tmp5 [V45,T131] ( 2, 2 ) int -> x4 ; V46 tmp6 [V46,T138] ( 2, 1 ) int -> x2 ; V47 tmp7 [V47 ] ( 1, 1 ) blk (16) [fp+98H] do-not-enreg[X] addr-exposed ld-addr-op unsafe-buffer "stackallocLocal" ;* V48 tmp8 [V48 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ; V49 tmp9 [V49,T54] ( 3, 24 ) int -> x11 "impSpillLclRefs" ; V50 tmp10 [V50,T66] ( 2, 16 ) int -> x13 "dup spill" ; V51 tmp11 [V51,T100] ( 2, 8 ) int -> x4 "impSpillLclRefs" ; V52 tmp12 [V52,T101] ( 2, 8 ) int -> x4 "impSpillLclRefs" ; V53 tmp13 [V53,T37] ( 2, 32 ) int -> x4 "impSpillLclRefs" ; V54 tmp14 [V54,T13] ( 2, 64 ) int -> x4 "dup spill" ; V55 tmp15 [V55,T106] ( 3, 6 ) int -> x4 ; V56 tmp16 [V56,T79] ( 3, 12 ) long -> x11 "impSpillLclRefs" ; V57 tmp17 [V57,T97] ( 4, 8 ) int -> x11 ; V58 tmp18 [V58,T107] ( 3, 6 ) int -> x13 ; V59 tmp19 [V59,T38] ( 2, 32 ) int -> x4 "impSpillLclRefs" ;* V60 tmp20 [V60,T103] ( 0, 0 ) byref -> zero-ref ptr ; V61 tmp21 [V61,T39] ( 2, 32 ) long -> x0 "impSpillLclRefs" ;* V62 tmp22 [V62,T65] ( 0, 0 ) byref -> zero-ref ptr ; V63 tmp23 [V63,T55] ( 3, 24 ) int -> x14 ; V64 tmp24 [V64,T134] ( 3, 1.50) int -> x0 ; V65 tmp25 [V65,T135] ( 3, 1.50) int -> x0 ; V66 tmp26 [V66,T136] ( 3, 1.50) int -> x11 ; V67 tmp27 [V67,T139] ( 2, 1 ) int -> xip0 ;* V68 tmp28 [V68 ] ( 0, 0 ) struct (16) zero-ref "struct address for call/obj" ; V69 tmp29 [V69,T52] ( 3, 24 ) byref -> x1 "dup spill" ; V70 tmp30 [V70,T99] ( 3, 8 ) int -> x1 ; V71 tmp31 [V71,T09] ( 3, 96 ) int -> x1 "impSpillLclRefs" ; V72 tmp32 [V72,T14] ( 2, 64 ) int -> x13 "dup spill" ; V73 tmp33 [V73,T03] ( 2,256 ) int -> x10 "dup spill" ; V74 tmp34 [V74,T04] ( 2,256 ) int -> x1 "impSpillLclRefs" ;* V75 tmp35 [V75 ] ( 0, 0 ) struct (16) zero-ref ; V76 tmp36 [V76,T104] ( 3, 6 ) byref -> x0 single-def "Span.get_Item ptrToSpan" ;* V77 tmp37 [V77 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg" ;* V78 tmp38 [V78 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ;* V79 tmp39 [V79 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg" ;* V80 tmp40 [V80 ] ( 0, 0 ) int -> zero-ref "impAppendStmt" ;* V81 tmp41 [V81 ] ( 0, 0 ) byref -> zero-ref ptr "Inlining Arg" ;* V82 tmp42 [V82 ] ( 0, 0 ) byref -> zero-ref ptr "Inlining Arg" ; V83 tmp43 [V83,T102] ( 2, 8 ) long -> x2 "Inlining Arg" ;* V84 tmp44 [V84 ] ( 0, 0 ) long -> zero-ref "Inlining Arg" ;* V85 tmp45 [V85 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "NewObj constructor temp" ; V86 tmp46 [V86,T109] ( 5, 5 ) ref -> x11 class-hnd single-def "Inlining Arg" ; V87 tmp47 [V87,T122] ( 5, 2.50) int -> x0 "Inline stloc first use temp" ; V88 tmp48 [V88,T120] ( 3, 3 ) byref -> x10 single-def "Span.get_Item ptrToSpan" ;* V89 tmp49 [V89 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ;* V90 tmp50 [V90 ] ( 0, 0 ) struct (16) zero-ref ld-addr-op "Inlining Arg" ; V91 tmp51 [V91,T31] ( 5, 40 ) int -> x14 "Inline stloc first use temp" ; V92 tmp52 [V92,T23] ( 3, 48 ) ushort -> x11 "Inlining Arg" ; V93 tmp53 [V93,T19] ( 3, 48 ) byref -> x12 "Span.get_Item ptrToSpan" ;* V94 tmp54 [V94 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V95 tmp55 [V95,T10] ( 5, 80 ) ref -> x11 class-hnd "Inlining Arg" ; V96 tmp56 [V96,T32] ( 5, 40 ) int -> x14 "Inline stloc first use temp" ; V97 tmp57 [V97,T20] ( 3, 48 ) byref -> x15 "Span.get_Item ptrToSpan" ;* V98 tmp58 [V98 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V99 tmp59 [V99,T87] ( 5, 10 ) int -> x11 "Inline stloc first use temp" ; V100 tmp60 [V100,T69] ( 3, 12 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V101 tmp61 [V101 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V102 tmp62 [V102,T47] ( 6, 24 ) ref -> x11 class-hnd "Inlining Arg" ; V103 tmp63 [V103,T88] ( 5, 10 ) int -> x13 "Inline stloc first use temp" ; V104 tmp64 [V104,T70] ( 3, 12 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V105 tmp65 [V105 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V106 tmp66 [V106,T48] ( 6, 24 ) ref -> x11 class-hnd "Inlining Arg" ; V107 tmp67 [V107,T89] ( 5, 10 ) int -> x10 "Inline stloc first use temp" ; V108 tmp68 [V108,T71] ( 3, 12 ) byref -> x13 "Span.get_Item ptrToSpan" ;* V109 tmp69 [V109 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V110 tmp70 [V110,T49] ( 6, 24 ) ref -> x11 class-hnd "Inlining Arg" ; V111 tmp71 [V111,T90] ( 5, 10 ) int -> x13 "Inline stloc first use temp" ; V112 tmp72 [V112,T72] ( 3, 12 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V113 tmp73 [V113 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V114 tmp74 [V114,T50] ( 6, 24 ) ref -> x11 class-hnd "Inlining Arg" ; V115 tmp75 [V115,T91] ( 5, 10 ) int -> x13 "Inline stloc first use temp" ; V116 tmp76 [V116,T73] ( 3, 12 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V117 tmp77 [V117 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V118 tmp78 [V118,T33] ( 5, 40 ) int -> x11 "Inline stloc first use temp" ; V119 tmp79 [V119,T24] ( 3, 48 ) ushort -> x14 "Inlining Arg" ; V120 tmp80 [V120,T21] ( 3, 48 ) byref -> x12 "Span.get_Item ptrToSpan" ;* V121 tmp81 [V121 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V122 tmp82 [V122,T92] ( 5, 10 ) int -> x11 "Inline stloc first use temp" ; V123 tmp83 [V123,T80] ( 3, 12 ) ushort -> x13 "Inlining Arg" ; V124 tmp84 [V124,T74] ( 3, 12 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V125 tmp85 [V125 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V126 tmp86 [V126,T93] ( 5, 10 ) int -> x14 "Inline stloc first use temp" ; V127 tmp87 [V127,T75] ( 3, 12 ) byref -> x11 "Span.get_Item ptrToSpan" ;* V128 tmp88 [V128 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V129 tmp89 [V129,T94] ( 5, 10 ) int -> x11 "Inline stloc first use temp" ; V130 tmp90 [V130,T76] ( 3, 12 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V131 tmp91 [V131 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V132 tmp92 [V132,T95] ( 5, 10 ) int -> x13 "Inline stloc first use temp" ; V133 tmp93 [V133,T81] ( 3, 12 ) ushort -> x11 "Inlining Arg" ; V134 tmp94 [V134,T77] ( 3, 12 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V135 tmp95 [V135 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V136 tmp96 [V136,T34] ( 5, 40 ) int -> x13 "Inline stloc first use temp" ; V137 tmp97 [V137,T25] ( 3, 48 ) ushort -> x11 "Inlining Arg" ; V138 tmp98 [V138,T22] ( 3, 48 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V139 tmp99 [V139 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V140 tmp100 [V140,T96] ( 5, 10 ) int -> x11 "Inline stloc first use temp" ; V141 tmp101 [V141,T78] ( 3, 12 ) byref -> x14 "Span.get_Item ptrToSpan" ;* V142 tmp102 [V142 ] ( 0, 0 ) byref -> zero-ref "Inlining Arg" ; V143 tmp103 [V143,T60] ( 6, 19 ) byref -> [fp+10H] ptr V19._reference(offs=0x00) P-INDEP "field V19._reference (fldOffset=0x0)" ; V144 tmp104 [V144,T43] ( 9, 27 ) int -> [fp+2CH] ptr V19._length(offs=0x08) P-INDEP "field V19._length (fldOffset=0x8)" ;* V145 tmp105 [V145 ] ( 0, 0 ) byref -> zero-ref V25._reference(offs=0x00) P-INDEP "field V25._reference (fldOffset=0x0)" ;* V146 tmp106 [V146 ] ( 0, 0 ) int -> zero-ref V25._length(offs=0x08) P-INDEP "field V25._length (fldOffset=0x8)" ; V147 tmp107 [V147,T127] ( 3, 2 ) byref -> x0 single-def V41._reference(offs=0x00) P-INDEP "field V41._reference (fldOffset=0x0)" ; V148 tmp108 [V148,T128] ( 3, 2 ) int -> x1 V41._length(offs=0x08) P-INDEP "field V41._length (fldOffset=0x8)" ; V149 tmp109 [V149,T123] ( 4, 2.50) byref -> x0 V42._reference(offs=0x00) P-INDEP "field V42._reference (fldOffset=0x0)" ; V150 tmp110 [V150,T125] ( 4, 2.50) int -> x1 V42._length(offs=0x08) P-INDEP "field V42._length (fldOffset=0x8)" ; V151 tmp111 [V151,T129] ( 2, 2 ) byref -> x6 V48._reference(offs=0x00) P-INDEP "field V48._reference (fldOffset=0x0)" ;* V152 tmp112 [V152,T140] ( 0, 0 ) int -> zero-ref ptr V48._length(offs=0x08) P-INDEP "field V48._length (fldOffset=0x8)" ;* V153 tmp113 [V153 ] ( 0, 0 ) byref -> zero-ref V68._reference(offs=0x00) P-INDEP "field V68._reference (fldOffset=0x0)" ;* V154 tmp114 [V154 ] ( 0, 0 ) int -> zero-ref V68._length(offs=0x08) P-INDEP "field V68._length (fldOffset=0x8)" ; V155 tmp115 [V155,T132] ( 3, 1.50) byref -> x0 single-def V75._reference(offs=0x00) P-INDEP "field V75._reference (fldOffset=0x0)" ; V156 tmp116 [V156,T137] ( 3, 1.50) int -> x1 V75._length(offs=0x08) P-INDEP "field V75._length (fldOffset=0x8)" ; V157 tmp117 [V157,T53] ( 3, 24 ) byref -> x9 V77._reference(offs=0x00) P-INDEP "field V77._reference (fldOffset=0x0)" ;* V158 tmp118 [V158 ] ( 0, 0 ) int -> zero-ref ptr V77._length(offs=0x08) P-INDEP "field V77._length (fldOffset=0x8)" ; V159 tmp119 [V159,T113] ( 2, 4 ) byref -> x0 V78._reference(offs=0x00) P-INDEP "field V78._reference (fldOffset=0x0)" ; V160 tmp120 [V160,T116] ( 2, 4 ) int -> x2 V78._length(offs=0x08) P-INDEP "field V78._length (fldOffset=0x8)" ; V161 tmp121 [V161,T114] ( 2, 4 ) byref -> x0 V79._reference(offs=0x00) P-INDEP "field V79._reference (fldOffset=0x0)" ;* V162 tmp122 [V162 ] ( 0, 0 ) int -> zero-ref ptr V79._length(offs=0x08) P-INDEP "field V79._length (fldOffset=0x8)" ; V163 tmp123 [V163,T115] ( 2, 4 ) byref -> x1 V85._reference(offs=0x00) P-INDEP "field V85._reference (fldOffset=0x0)" ; V164 tmp124 [V164,T117] ( 2, 4 ) int -> x4 V85._length(offs=0x08) P-INDEP "field V85._length (fldOffset=0x8)" ; V165 tmp125 [V165,T121] ( 3, 3 ) byref -> x24 single-def V90._reference(offs=0x00) P-INDEP "field V90._reference (fldOffset=0x0)" ;* V166 tmp126 [V166 ] ( 0, 0 ) int -> zero-ref ptr V90._length(offs=0x08) P-INDEP "field V90._length (fldOffset=0x8)" ; V167 tmp127 [V167,T118] ( 2, 4 ) long -> x23 "Cast away GC" ; V168 tmp128 [V168,T40] ( 2, 32 ) long -> x9 "Cast away GC" ; V169 tmp129 [V169,T119] ( 2, 4 ) long -> x24 "Cast away GC" ; V170 GsCookie [V170 ] ( 1, 1 ) long -> [fp+A8H] do-not-enreg[X] addr-exposed "GSSecurityCookie" ; V171 cse0 [V171,T06] ( 3,192 ) int -> x0 "CSE - aggressive" ; V172 cse1 [V172,T15] ( 6, 60 ) int -> x14 "CSE - aggressive" ; V173 cse2 [V173,T35] ( 3, 40 ) int -> x11 "CSE - moderate" ; V174 cse3 [V174,T17] ( 7, 56 ) int -> registers "CSE - aggressive" ; V175 cse4 [V175,T98] ( 4, 8 ) int -> x11 "CSE - conservative" ; V176 cse5 [V176,T64] ( 8, 16 ) int -> registers "CSE - moderate" ; V177 cse6 [V177,T56] ( 3, 24 ) int -> x11 "CSE - moderate" ; V178 cse7 [V178,T126] ( 4, 2 ) int -> x3 "CSE - conservative" ; V179 cse8 [V179,T02] ( 17,284 ) int -> x25 "CSE - aggressive" ; V180 cse9 [V180,T67] ( 5, 15 ) byref -> x24 "CSE - moderate" ; V181 cse10 [V181,T57] ( 3, 24 ) int -> x12 "CSE - moderate" ; V182 rat0 [V182,T26] ( 3, 48 ) int -> x14 "ReplaceWithLclVar is creating a new local variable" ; V183 rat1 [V183,T27] ( 3, 48 ) int -> x12 "ReplaceWithLclVar is creating a new local variable" ; V184 rat2 [V184,T82] ( 3, 12 ) int -> x14 "ReplaceWithLclVar is creating a new local variable" ; V185 rat3 [V185,T83] ( 3, 12 ) int -> x12 "ReplaceWithLclVar is creating a new local variable" ; ; Lcl frame size = 160 Mark labels for codegen BB01 : first block BB01 : function has switch; mark first block BB05 : branch target BB04 : branch target BB06 : branch target BB06 : branch target BB47 : branch target BB13 : branch target BB10 : branch target BB31 : branch target BB17 : branch target BB259 : branch target BB30 : branch target BB259 : branch target BB31 : branch target BB47 : branch target BB11 : branch target BB23 : branch target BB260 : branch target BB21 : branch target BB260 : branch target BB18 : branch target BB47 : branch target BB38 : branch target BB47 : branch target BB35 : branch target BB38 : branch target BB47 : branch target BB47 : branch target BB47 : branch target BB20 : branch target BB47 : branch target BB47 : branch target BB47 : branch target BB47 : branch target BB29 : branch target BB28 : branch target BB47 : branch target BB47 : branch target BB47 : branch target BB47 : branch target BB31 : branch target BB47 : branch target BB47 : branch target BB47 : branch target BB40 : branch target BB44 : branch target BB47 : branch target BB43 : branch target BB47 : branch target BB47 : branch target BB46 : branch target BB44 : branch target BB50 : branch target BB50 : branch target BB08 : branch target BB52 : branch target BB56 : branch target BB55 : branch target BB56 : branch target BB63 : branch target BB59 : branch target BB60 : branch target BB66 : branch target BB66 : branch target BB07 : branch target BB65 : branch target BB74 : branch target BB78 : branch target BB262 : branch target BB82 : branch target BB84 : branch target BB85 : branch target BB103 : branch target BB103 : branch target BB103 : branch target BB100 : branch target BB110 : branch target BB102 : branch target BB89 : branch target BB112 : branch target BB112 : branch target BB112 : branch target BB111 : branch target BB248 : branch target BB248 : branch target BB113 : branch target BB253 : branch target BB253 : branch target BB112 : branch target BB263 : branch target BB135 : branch target BB264 : branch target BB136 : branch target BB135 : branch target BB136 : branch target BB120 : branch target BB121 : branch target BB123 : branch target BB124 : branch target BB134 : branch target BB265 : branch target BB133 : branch target BB132 : branch target BB133 : branch target BB134 : branch target BB118 : branch target BB141 : branch target BB138 : branch target BB194 : branch target BB145 : branch target BB242 : branch target BB186 : branch target BB242 : branch target BB194 : branch target BB139 : branch target BB266 : branch target BB242 : branch target BB171 : branch target BB242 : branch target BB145 : branch target BB245 : branch target BB205 : branch target BB242 : branch target BB200 : branch target BB205 : branch target BB242 : branch target BB181 : branch target BB150 : branch target BB148 : branch target BB149 : branch target BB156 : branch target BB154 : branch target BB153 : branch target BB155 : branch target BB155 : branch target BB170 : branch target BB159 : branch target BB160 : branch target BB170 : branch target BB267 : branch target BB169 : branch target BB168 : branch target BB169 : branch target BB170 : branch target BB245 : branch target BB245 : branch target BB174 : branch target BB245 : branch target BB180 : branch target BB179 : branch target BB180 : branch target BB245 : branch target BB245 : branch target BB185 : branch target BB245 : branch target BB245 : branch target BB245 : branch target BB190 : branch target BB245 : branch target BB245 : branch target BB193 : branch target BB194 : branch target BB197 : branch target BB198 : branch target BB191 : branch target BB268 : branch target BB245 : branch target BB245 : branch target BB245 : branch target BB245 : branch target BB204 : branch target BB245 : branch target BB245 : branch target BB227 : branch target BB208 : branch target BB218 : branch target BB215 : branch target BB213 : branch target BB219 : branch target BB215 : branch target BB219 : branch target BB269 : branch target BB245 : branch target BB244 : branch target BB221 : branch target BB271 : branch target BB223 : branch target BB225 : branch target BB226 : branch target BB218 : branch target BB245 : branch target BB229 : branch target BB230 : branch target BB245 : branch target BB233 : branch target BB239 : branch target BB235 : branch target BB239 : branch target BB239 : branch target BB238 : branch target BB239 : branch target BB245 : branch target BB236 : branch target BB245 : branch target BB272 : branch target BB245 : branch target BB244 : branch target BB245 : branch target BB254 : throw helper block *************** After genMarkLabelsForCodegen() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..017)-> BB05 ( cond ) i label hascall gcsafe nullcheck LIR BB02 [0001] 1 BB01 0.50 [017..01F)-> BB04 ( cond ) i gcsafe LIR BB03 [0002] 1 BB02 0.50 [01F..022)-> BB06 (always) i gcsafe LIR BB04 [0003] 1 BB02 0.50 [022..025)-> BB06 (always) i label gcsafe LIR BB05 [0004] 1 BB01 0.50 [025..026) i label gcsafe LIR BB06 [0005] 3 BB03,BB04,BB05 1 [026..02D) i label hascall gcsafe LIR BB07 [0006] 2 BB06,BB62 8 0 [02D..05B)-> BB47 (always) i Loop Loop1 label gcsafe bwd bwd-target LoopPH LIR BB08 [0007] 1 BB49 8 1 [05B..061)-> BB13 ( cond ) i Loop Loop0 label bwd bwd-target LIR BB09 [0008] 1 BB08 8 1 [061..061)-> BB10 ( cond ) i bwd LIR BB255 [0364] 1 BB09 8 [061..083)-> BB31,BB17,BB259,BB30,BB259,BB31 (switch) i bwd LIR BB259 [0368] 2 BB255(2) 4 [???..???)-> BB47 (always) internal label bwd LIR BB10 [0009] 1 BB09 8 1 [083..083)-> BB11 ( cond ) i label bwd LIR BB256 [0365] 1 BB10 8 [083..0A1)-> BB23,BB260,BB21,BB260,BB18 (switch) i bwd LIR BB260 [0369] 2 BB256(2) 4 [???..???)-> BB47 (always) internal label bwd LIR BB11 [0010] 1 BB10 8 1 [0A1..0AA)-> BB38 ( cond ) i label bwd LIR BB12 [0011] 1 BB11 8 1 [0AA..0AF)-> BB47 (always) i bwd LIR BB13 [0012] 1 BB08 8 1 [0AF..0B8)-> BB35 ( cond ) i label bwd LIR BB14 [0013] 1 BB13 8 1 [0B8..0C1)-> BB38 ( cond ) i bwd LIR BB15 [0014] 1 BB14 8 1 [0C1..0CA)-> BB47 ( cond ) i bwd LIR BB16 [0030] 1 BB15 8 1 [137..142)-> BB47 (always) i bwd LIR BB17 [0016] 1 BB255 8 1 [0CF..0D8)-> BB47 (always) i label bwd LIR BB18 [0017] 1 BB256 8 1 [0D8..0E0)-> BB20 ( cond ) i label bwd LIR BB19 [0018] 1 BB18 8 1 [0E0..0E2) i bwd LIR BB20 [0019] 2 BB18,BB19 8 1 [0E2..0ED)-> BB47 (always) i label bwd LIR BB21 [0020] 1 BB256 8 1 [0ED..0F4)-> BB47 ( cond ) i label bwd LIR BB22 [0021] 1 BB21 8 1 [0F4..0FB)-> BB47 (always) i bwd LIR BB23 [0022] 1 BB256 8 1 [0FB..102)-> BB47 ( cond ) i label bwd LIR BB24 [0023] 1 BB23 8 1 [102..10E)-> BB29 ( cond ) i bwd LIR BB26 [0025] 1 BB24 8 1 [10E..113)-> BB28 ( cond ) i bwd LIR BB27 [0026] 1 BB26 8 1 [113..11E)-> BB47 (always) i bwd LIR BB28 [0027] 1 BB26 8 1 [11E..121) i label bwd LIR BB29 [0028] 2 BB24,BB28 8 1 [121..12C)-> BB47 (always) i label bwd LIR BB30 [0029] 1 BB255 8 1 [12C..137)-> BB47 (always) i label bwd LIR BB31 [0031] 3 BB32,BB255(2) 64 1 [142..150)-> BB47 ( cond ) i Loop Loop0 label bwd bwd-target LIR BB32 [0032] 1 BB31 64 1 [150..170)-> BB31 ( cond ) i bwd LIR BB34 [0034] 1 BB32 8 1 [170..175)-> BB47 (always) i bwd LIR BB35 [0035] 1 BB13 8 1 [175..183)-> BB47 ( cond ) i label bwd LIR BB36 [0036] 1 BB35 8 1 [183..196)-> BB47 (always) i bwd LIR BB38 [0038] 2 BB11,BB14 8 1 [196..1A1)-> BB40 ( cond ) i label bwd LIR BB39 [0039] 1 BB38 8 1 [1A1..1AE)-> BB44 ( cond ) i bwd LIR BB40 [0040] 2 BB38,BB39 8 1 [1AE..1BB)-> BB47 ( cond ) i label bwd LIR BB41 [0041] 1 BB40 8 1 [1BB..1C8)-> BB43 ( cond ) i bwd LIR BB42 [0042] 1 BB41 8 1 [1C8..1D5)-> BB47 ( cond ) i bwd LIR BB43 [0043] 2 BB41,BB42 8 1 [1D5..1E4)-> BB47 ( cond ) i label bwd LIR BB261 [0370] 1 BB43 4 [???..???) internal bwd LIR BB44 [0044] 3 BB39,BB45,BB261 64 1 [1E4..1F4)-> BB46 ( cond ) i Loop Loop0 label bwd bwd-target LIR BB45 [0045] 1 BB44 64 1 [1F4..201)-> BB44 ( cond ) i bwd bwd-src LIR BB46 [0046] 2 BB44,BB45 8 1 [201..204) i label bwd LIR BB47 [0047] 22 BB07,BB12,BB15,BB16,BB17,BB20,BB21,BB22,BB23,BB27,BB29,BB30,BB31,BB34,BB35,BB36,BB40,BB42,BB43,BB46,BB259,BB260 64 1 [204..20F)-> BB50 ( cond ) i label bwd LIR BB48 [0048] 1 BB47 16 1 [20F..222)-> BB50 ( cond ) i bwd LIR BB49 [0049] 1 BB48 16 1 [222..22B)-> BB08 ( cond ) i bwd bwd-src LIR BB50 [0050] 3 BB47,BB48,BB49 8 0 [22B..233)-> BB52 ( cond ) i label bwd LIR BB51 [0051] 1 BB50 2 0 [233..235) i bwd LIR BB52 [0052] 2 BB50,BB51 8 0 [235..23A)-> BB56 ( cond ) i label bwd LIR BB53 [0053] 1 BB52 2 0 [23A..23F)-> BB55 ( cond ) i bwd LIR BB54 [0054] 1 BB53 2 0 [23F..24A)-> BB56 (always) i bwd LIR BB55 [0055] 1 BB53 2 0 [24A..24D) i label bwd LIR BB56 [0056] 3 BB52,BB54,BB55 8 0 [24D..252)-> BB63 ( cond ) i label bwd LIR BB57 [0057] 1 BB56 4 0 [252..262)-> BB59 ( cond ) i nullcheck bwd LIR BB58 [0058] 1 BB57 2 0 [262..26E)-> BB60 (always) i bwd LIR BB59 [0059] 1 BB57 2 0 [26E..26F) i label bwd LIR BB60 [0060] 2 BB58,BB59 4 0 [26F..27F)-> BB66 ( cond ) i label hascall gcsafe bwd LIR BB61 [0061] 1 BB60 4 0 [27F..28E)-> BB66 ( cond ) i hascall gcsafe bwd LIR BB62 [0062] 1 BB61 4 0 [28E..297)-> BB07 (always) i gcsafe bwd bwd-src LIR BB63 [0063] 1 BB56 0.50 [297..2A0)-> BB65 ( cond ) i label LIR BB64 [0064] 1 BB63 0.50 [2A0..2A7) i LIR BB65 [0065] 2 BB63,BB64 0.50 [2A7..2AE) i label LIR BB66 [0066] 3 BB60,BB61,BB65 1 [2AE..2C8)-> BB74 ( cond ) i label LIR BB73 [0073] 1 BB66 0.50 [2C8..2D0)-> BB78 (always) i LIR BB74 [0074] 1 BB66 0.50 [2D0..2EE) i label LIR BB78 [0078] 2 BB73,BB74 1 [000..30D)-> BB262 ( cond ) i label idxlen LIR BB79 [0079] 1 BB78 0.50 [30D..336)-> BB82 ( cond ) i idxlen LIR BB81 [0081] 1 BB79 0.50 [336..33D) i idxlen LIR BB82 [0082] 2 BB79,BB81 0.50 [33D..348)-> BB84 ( cond ) i label LIR BB83 [0083] 1 BB82 0.50 [348..34B)-> BB85 (always) i LIR BB262 [0371] 1 BB78 0.50 [???..???)-> BB103 (always) internal label LIR BB84 [0084] 1 BB82 0.50 [34B..34D) i label LIR BB85 [0085] 2 BB83,BB84 0.50 [34D..35E)-> BB103 ( cond ) i label LIR BB89 [0089] 2 BB85,BB102 4 2 [35E..362)-> BB103 ( cond ) i Loop Loop0 label bwd bwd-target LIR BB90 [0090] 1 BB89 4 2 [362..373)-> BB100 ( cond ) i bwd LIR BB91 [0091] 1 BB90 2 2 [000..39A)-> BB110 ( cond ) i hascall idxlen nullcheck bwd LIR BB95 [0227] 1 BB91 2 2 [000..392) i hascall gcsafe idxlen nullcheck bwd LIR BB100 [0092] 2 BB90,BB95 4 2 [39A..3AE)-> BB102 ( cond ) i label bwd LIR BB101 [0093] 1 BB100 2 2 [3AE..3BB) i idxlen bwd LIR BB102 [0094] 2 BB100,BB101 4 2 [3BB..3C8)-> BB89 ( cond ) i label bwd LIR BB103 [0096] 4 BB85,BB89,BB102,BB262 1 [3C8..3D0)-> BB112 ( cond ) i label LIR BB104 [0097] 1 BB103 0.50 [3D0..3DC)-> BB112 ( cond ) i LIR BB106 [0099] 1 BB104 0.50 [3DC..3E8)-> BB112 ( cond ) i LIR BB107 [0252] 1 BB106 0.50 [3DC..3DD)-> BB111 ( cond ) i idxlen LIR BB108 [0253] 1 BB107 0.50 [3DC..3DD) i idxlen nullcheck LIR BB112 [0256] 5 BB103,BB104,BB106,BB108,BB111 1 [3E8..401) i label LIR BB245 [0190] 25 BB112,BB170,BB171,BB173,BB180,BB181,BB183,BB185,BB186,BB188,BB190,BB198,BB199,BB200,BB203,BB204,BB216,BB226,BB230,BB239,BB241,BB243,BB244,BB266,BB268 8 3 [7AA..7B5)-> BB248 ( cond ) i label bwd LIR BB246 [0191] 1 BB245 4 3 [7B5..7C8)-> BB248 ( cond ) i bwd LIR BB247 [0192] 1 BB246 4 3 [7C8..7D1)-> BB113 ( cond ) i bwd bwd-src LIR BB248 [0193] 3 BB245,BB246,BB247 1 [7D1..7DD)-> BB253 ( cond ) i label LIR BB249 [0194] 1 BB248 0.50 [7DD..7E9)-> BB253 ( cond ) i LIR BB251 [0196] 1 BB249 0.50 [7E9..7FF) i gcsafe LIR BB253 [0198] 3 BB248,BB249,BB251 1 [7FF..800) (return) i label LIR BB111 [0255] 1 BB107 0.50 [3DC..3DD)-> BB112 (always) i label hascall gcsafe LIR BB113 [0101] 1 BB247 2 3 [401..406)-> BB263 ( cond ) i Loop Loop0 label bwd bwd-target LIR BB114 [0102] 1 BB113 2 3 [406..40C)-> BB135 ( cond ) i bwd LIR BB115 [0103] 1 BB114 2 3 [40C..418)-> BB264 ( cond ) i bwd LIR BB117 [0105] 1 BB115 2 3 [418..41A)-> BB136 (always) i bwd LIR BB264 [0373] 1 BB115 1 [???..???)-> BB135 (always) internal label bwd LIR BB263 [0372] 1 BB113 1 [???..???)-> BB136 (always) internal label bwd LIR BB118 [0106] 1 BB135 8 3 [41A..420)-> BB120 ( cond ) i Loop Loop0 label bwd bwd-target LIR BB119 [0107] 1 BB118 8 3 [420..424)-> BB121 (always) i bwd LIR BB120 [0108] 1 BB118 8 3 [424..42C) i label bwd LIR BB121 [0109] 2 BB119,BB120 8 3 [000..435)-> BB123 ( cond ) i label bwd LIR BB122 [0260] 1 BB121 8 3 [000..000)-> BB124 (always) i internal nullcheck bwd LIR BB123 [0261] 1 BB121 8 3 [000..000) i internal label hascall gcsafe bwd LIR BB124 [0262] 2 BB122,BB123 8 3 [???..???)-> BB134 ( cond ) internal label bwd LIR BB125 [0110] 1 BB124 8 3 [435..43F)-> BB265 ( cond ) i bwd LIR BB127 [0112] 1 BB125 8 3 [43F..461)-> BB133 ( cond ) i bwd LIR BB129 [0267] 1 BB127 8 3 [44F..450)-> BB132 ( cond ) i idxlen bwd LIR BB130 [0268] 1 BB129 8 3 [44F..450)-> BB133 (always) i idxlen nullcheck bwd LIR BB265 [0374] 1 BB125 4 [???..???)-> BB134 (always) internal label bwd LIR BB132 [0270] 1 BB129 8 3 [44F..450) i label hascall gcsafe bwd LIR BB133 [0271] 3 BB127,BB130,BB132 8 3 [???..???) internal label bwd LIR BB134 [0114] 3 BB124,BB133,BB265 8 3 [461..46D) i label bwd LIR BB135 [0115] 3 BB114,BB134,BB264 16 3 [46D..472)-> BB118 ( cond ) i label bwd bwd-src LIR BB136 [0116] 3 BB117,BB135,BB263 2 3 [472..478)-> BB141 ( cond ) i label bwd LIR BB137 [0117] 1 BB136 2 3 [478..478)-> BB138 ( cond ) i bwd LIR BB257 [0366] 1 BB137 2 [478..49A)-> BB194,BB145,BB242,BB186,BB242,BB194 (switch) i bwd LIR BB138 [0118] 1 BB137 2 3 [49A..49A)-> BB139 ( cond ) i label bwd LIR BB258 [0367] 1 BB138 2 [49A..4B8)-> BB266,BB242,BB171,BB242,BB145 (switch) i bwd LIR BB266 [0375] 1 BB258 1 [???..???)-> BB245 (always) internal label bwd LIR BB139 [0119] 1 BB138 2 3 [4B8..4C1)-> BB205 ( cond ) i label bwd LIR BB140 [0120] 1 BB139 2 3 [4C1..4C6)-> BB242 (always) i bwd LIR BB141 [0121] 1 BB136 2 3 [4C6..4CF)-> BB200 ( cond ) i label bwd LIR BB142 [0122] 1 BB141 2 3 [4CF..4D8)-> BB205 ( cond ) i bwd LIR BB143 [0123] 1 BB142 2 3 [4D8..4E4)-> BB242 ( cond ) i bwd LIR BB144 [0148] 1 BB143 2 3 [598..5A9)-> BB181 (always) i bwd LIR BB145 [0125] 2 BB257,BB258 2 3 [4E9..4EE)-> BB150 ( cond ) i label bwd LIR BB146 [0126] 1 BB145 2 3 [4EE..4F9)-> BB148 ( cond ) i bwd LIR BB147 [0127] 1 BB146 2 3 [4F9..4FC)-> BB149 (always) i bwd LIR BB148 [0128] 1 BB146 2 3 [4FC..4FE) i label bwd LIR BB149 [0129] 2 BB147,BB148 2 3 [4FE..502)-> BB156 (always) i label bwd LIR BB150 [0130] 1 BB145 2 3 [502..507)-> BB154 ( cond ) i label bwd LIR BB151 [0131] 1 BB150 2 3 [507..50C)-> BB153 ( cond ) i bwd LIR BB152 [0132] 1 BB151 2 3 [50C..50F)-> BB155 (always) i bwd LIR BB153 [0133] 1 BB151 2 3 [50F..513)-> BB155 (always) i label bwd LIR BB154 [0134] 1 BB150 2 3 [513..51B) i label bwd LIR BB155 [0135] 3 BB152,BB153,BB154 2 3 [51B..51D) i label bwd LIR BB156 [0136] 2 BB149,BB155 2 3 [51D..521)-> BB170 ( cond ) i label bwd LIR BB157 [0137] 1 BB156 2 3 [521..52D)-> BB159 ( cond ) i bwd LIR BB158 [0274] 1 BB157 2 3 [521..522)-> BB160 (always) i nullcheck bwd LIR BB159 [0275] 1 BB157 2 3 [521..522) i label hascall gcsafe bwd LIR BB160 [0276] 2 BB158,BB159 2 3 [???..???)-> BB170 ( cond ) internal label bwd LIR BB161 [0138] 1 BB160 2 3 [52D..537)-> BB267 ( cond ) i bwd LIR BB163 [0140] 1 BB161 2 3 [537..559)-> BB169 ( cond ) i bwd LIR BB165 [0281] 1 BB163 2 3 [547..548)-> BB168 ( cond ) i idxlen bwd LIR BB166 [0282] 1 BB165 2 3 [547..548)-> BB169 (always) i idxlen nullcheck bwd LIR BB267 [0376] 1 BB161 1 [???..???)-> BB170 (always) internal label bwd LIR BB168 [0284] 1 BB165 2 3 [547..548) i label hascall gcsafe bwd LIR BB169 [0285] 3 BB163,BB166,BB168 2 3 [???..???) internal label bwd LIR BB170 [0142] 4 BB156,BB160,BB169,BB267 2 3 [559..564)-> BB245 (always) i label bwd LIR BB171 [0143] 1 BB258 2 3 [564..571)-> BB245 ( cond ) i label bwd LIR BB172 [0144] 1 BB171 2 3 [571..575)-> BB174 ( cond ) i bwd LIR BB173 [0145] 1 BB172 2 3 [575..57C)-> BB245 ( cond ) i bwd LIR BB174 [0146] 2 BB172,BB173 2 3 [57C..598)-> BB180 ( cond ) i label bwd LIR BB176 [0290] 1 BB174 2 3 [584..585)-> BB179 ( cond ) i idxlen bwd LIR BB177 [0291] 1 BB176 2 3 [584..585)-> BB180 (always) i idxlen nullcheck bwd LIR BB179 [0293] 1 BB176 2 3 [584..585) i label hascall gcsafe bwd LIR BB180 [0294] 3 BB174,BB177,BB179 2 3 [???..???)-> BB245 (always) internal label bwd LIR BB181 [0297] 1 BB144 2 3 [598..599)-> BB245 ( cond ) i label bwd LIR BB182 [0299] 1 BB181 2 3 [598..599)-> BB185 ( cond ) i idxlen bwd LIR BB183 [0300] 1 BB182 2 3 [598..599)-> BB245 (always) i idxlen nullcheck bwd LIR BB185 [0302] 1 BB182 2 3 [598..599)-> BB245 (always) i label hascall gcsafe bwd LIR BB186 [0149] 1 BB257 2 3 [5A9..5BA)-> BB245 ( cond ) i label bwd LIR BB187 [0308] 1 BB186 2 3 [5A9..5AA)-> BB190 ( cond ) i idxlen bwd LIR BB188 [0309] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i idxlen nullcheck bwd LIR BB190 [0311] 1 BB187 2 3 [5A9..5AA)-> BB245 (always) i label hascall gcsafe bwd LIR BB191 [0150] 1 BB196 8 3 [000..5CE)-> BB193 ( cond ) i Loop Loop0 label bwd bwd-target LIR BB192 [0315] 1 BB191 8 3 [000..000)-> BB194 (always) i internal nullcheck bwd LIR BB193 [0316] 1 BB191 8 3 [000..000) i internal label hascall gcsafe bwd LIR BB194 [0151] 4 BB192,BB193,BB257(2) 16 3 [5CE..5D9)-> BB197 ( cond ) i label bwd LIR BB195 [0152] 1 BB194 16 3 [5D9..5E4)-> BB198 ( cond ) i bwd LIR BB196 [0153] 1 BB195 16 3 [5E4..5F1)-> BB191 ( cond ) i bwd bwd-src LIR BB197 [0154] 2 BB194,BB196 2 3 [5F1..5FF)-> BB268 ( cond ) i label bwd LIR BB198 [0155] 2 BB195,BB197 2 3 [5FF..60D)-> BB245 ( cond ) i label bwd LIR BB199 [0156] 1 BB198 2 3 [60D..618)-> BB245 (always) i bwd LIR BB268 [0377] 1 BB197 1 [???..???)-> BB245 (always) internal label bwd LIR BB200 [0157] 1 BB141 2 3 [618..626)-> BB245 ( cond ) i label bwd LIR BB201 [0158] 1 BB200 2 3 [000..64D)-> BB204 ( cond ) i bwd LIR BB203 [0323] 1 BB201 2 3 [000..000)-> BB245 (always) i internal nullcheck bwd LIR BB204 [0324] 1 BB201 2 3 [000..000)-> BB245 (always) i internal label hascall gcsafe bwd LIR BB205 [0160] 2 BB139,BB142 2 3 [64D..65A)-> BB227 ( cond ) i label bwd LIR BB206 [0161] 1 BB205 2 3 [65A..665)-> BB208 ( cond ) i bwd LIR BB207 [0162] 1 BB206 2 3 [665..672)-> BB218 ( cond ) i bwd LIR BB208 [0164] 2 BB206,BB207 2 3 [67A..687)-> BB215 ( cond ) i label bwd LIR BB209 [0165] 1 BB208 2 3 [687..694)-> BB213 ( cond ) i bwd LIR BB210 [0166] 1 BB209 2 3 [694..6A8)-> BB219 (always) i bwd LIR BB213 [0169] 1 BB209 2 3 [6B5..6C2)-> BB215 ( cond ) i label bwd LIR BB214 [0170] 1 BB213 2 3 [6C2..6D1)-> BB219 ( cond ) i bwd LIR BB215 [0171] 3 BB208,BB213,BB214 2 3 [6D1..6DE)-> BB269 ( cond ) i label bwd LIR BB216 [0331] 1 BB215 2 3 [6D1..6D2)-> BB245 (always) i nullcheck bwd LIR BB269 [0378] 1 BB215 1 [???..???)-> BB244 (always) internal label bwd LIR BB218 [0172] 2 BB207,BB271 8 3 [6DE..6E4) i Loop Loop0 label bwd bwd-target LIR BB219 [0173] 3 BB210,BB214,BB218 16 3 [6E4..6F4)-> BB221 ( cond ) i label bwd LIR BB220 [0174] 1 BB219 16 3 [6F4..701)-> BB271 ( cond ) i bwd bwd-src LIR BB270 [0379] 1 BB220 8 [???..???) internal bwd LIR BB221 [0175] 2 BB219,BB270 2 3 [701..707)-> BB223 ( cond ) i label bwd LIR BB222 [0176] 1 BB221 2 3 [707..70B) i bwd LIR BB223 [0177] 2 BB221,BB222 2 3 [70B..710)-> BB225 ( cond ) i label bwd LIR BB224 [0178] 1 BB223 2 3 [710..71A)-> BB226 (always) i bwd LIR BB271 [0380] 1 BB220 8 [???..???)-> BB218 (always) internal label bwd LIR BB225 [0179] 1 BB223 2 3 [71A..71B) i label bwd LIR BB226 [0180] 2 BB224,BB225 2 3 [71B..731)-> BB245 (always) i label hascall gcsafe bwd LIR BB227 [0181] 1 BB205 2 3 [731..744)-> BB229 ( cond ) i label bwd LIR BB228 [0337] 1 BB227 2 3 [731..732)-> BB230 (always) i nullcheck bwd LIR BB229 [0338] 1 BB227 2 3 [731..732) i label hascall gcsafe bwd LIR BB230 [0339] 2 BB228,BB229 2 3 [???..???)-> BB245 ( cond ) i internal label bwd LIR BB231 [0182] 1 BB230 2 3 [744..751)-> BB233 ( cond ) i bwd LIR BB232 [0183] 1 BB231 2 3 [751..75E)-> BB239 ( cond ) i bwd LIR BB233 [0184] 2 BB231,BB232 2 3 [000..774)-> BB235 ( cond ) i label bwd LIR BB234 [0343] 1 BB233 2 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB235 [0344] 1 BB233 2 3 [000..000)-> BB239 (always) i internal label hascall gcsafe bwd LIR BB236 [0185] 1 BB240 8 3 [000..788)-> BB238 ( cond ) i Loop Loop0 label bwd bwd-target LIR BB237 [0348] 1 BB236 8 3 [000..000)-> BB239 (always) i internal nullcheck bwd LIR BB238 [0349] 1 BB236 8 3 [000..000) i internal label hascall gcsafe bwd LIR BB239 [0350] 5 BB232,BB234,BB235,BB237,BB238 16 3 [788..793)-> BB245 ( cond ) i label bwd LIR BB240 [0187] 1 BB239 16 3 [793..7A0)-> BB236 ( cond ) i bwd bwd-src LIR BB241 [0188] 1 BB240 2 3 [7A0..7A2)-> BB245 (always) i bwd LIR BB242 [0189] 6 BB140,BB143,BB257(2),BB258(2) 2 3 [7A2..7AA)-> BB272 ( cond ) i label bwd LIR BB243 [0354] 1 BB242 2 3 [7A2..7A3)-> BB245 (always) i nullcheck bwd LIR BB272 [0381] 1 BB242 1 [???..???)-> BB244 (always) internal label bwd LIR BB244 [0355] 2 BB269,BB272 2 3 [7A2..7A3)-> BB245 (always) i label hascall gcsafe bwd LIR BB110 [0228] 1 BB91 0 [000..000) (throw ) i internal rare label hascall gcsafe bwd LIR BB254 [0363] 0 0 [???..???) (throw ) keep i internal rare label LIR ----------------------------------------------------------------------------------------------------------------------------------------- Setting stack level from -572662307 to 0 =============== Generating BB01 [000..017) -> BB05 (cond), preds={} succs={BB02,BB05} flags=0x00000002.20090420: i label hascall gcsafe nullcheck LIR BB01 IN (4)={V00 V03 V01 V02 } + ByrefExposed + GcHeap OUT(10)={V00 V179 V11 V03 V01 V17 V180 V02 V147 V148} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V00(x19) V03(x20) V01(x21) Change life 000000000000000000000000000000000000000000000000 {} -> 000000000000000000000000004000000400400000000002 {V00 V01 V02 V03} V00 in reg x19 is becoming live [------] Live regs: 0000 {} => 80000 {x19} New debug range: first V03 in reg x20 is becoming live [------] Live regs: 80000 {x19} => 180000 {x19 x20} New debug range: first V01 in reg x21 is becoming live [------] Live regs: 180000 {x19 x20} => 380000 {x19 x20 x21} New debug range: first New debug range: first Live regs: (unchanged) 380000 {x19 x20 x21} GC regs: (unchanged) 100000 {x20} Byref regs: (unchanged) 280000 {x19 x21} L_M30548_BB01: Mapped BB01 to G_M30548_IG02 Label: IG02, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=280000 {x19 x21} Scope info: begin block BB01, IL range [000..017) Added IP mapping: 0x0000 STACK_EMPTY (G_M30548_IG02,ins#0,ofs#0) label Generating: N003 (???,???) [003780] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA Generating: N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t0 byref Generating: N007 (???,???) [004185] ----------- t4185 = * PUTARG_REG byref REG x0 IN0001: mov x0, x21 Byref regs: 280000 {x19 x21} => 280001 {x0 x19 x21} Generating: N009 ( 2, 8) [002543] H---------- t2543 = CNS_INT(h) long 0x400000000046ac80 ftn REG x11 $42 IN0002: adrp x11, [HIGH RELOC #0x400000000046ac80] // function address IN0003: add x11, x11, [LOW RELOC #0x400000000046ac80] /--* t2543 long Generating: N011 (???,???) [004186] ----------- t4186 = * PUTARG_REG long REG x11 /--* t4185 byref this in x0 +--* t4186 long r2r cell in x11 Generating: N013 ( 17, 13) [000001] --CXG------ * CALL r2r_ind void REG NA $VN.Void Byref regs: 280001 {x0 x19 x21} => 280000 {x19 x21} IN0004: ldr x1, [x11] Call: GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=280000 {x19 x21} [05] Rec call GC vars = 000000000000000000000000000000000000000000000000 IN0005: blr x1 Added IP mapping: 0x0006 STACK_EMPTY (G_M30548_IG02,ins#5,ofs#20) Generating: N015 (???,???) [003781] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA Generating: N017 ( 1, 2) [000002] -c--------- t2 = CNS_INT int 0 REG NA $c0 /--* t2 int Generating: N019 ( 1, 3) [000004] DA--------- * STORE_LCL_VAR int V11 loc7 d:1 x22 REG x22 IN0006: mov w22, wzr V11 in reg x22 is becoming live [000004] Live regs: 380000 {x19 x20 x21} => 780000 {x19 x20 x21 x22} Live vars: {V00 V01 V02 V03} => {V00 V01 V02 V03 V11} New debug range: first Added IP mapping: 0x0009 STACK_EMPTY (G_M30548_IG02,ins#6,ofs#24) Generating: N021 (???,???) [003782] ----------- IL_OFFSET void INL01 @ 0x000[E-] <- INLRT @ 0x009[E-] REG NA Generating: N023 ( 1, 1) [002546] ----------- t2546 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 Generating: N025 ( 1, 2) [002547] -c--------- t2547 = CNS_INT long 16 REG NA $200 /--* t2546 byref +--* t2547 long Generating: N027 ( 3, 4) [002548] -----O----- t2548 = * ADD byref REG x0 $240 IN0007: add x0, x21, #16 Byref regs: 280000 {x19 x21} => 280001 {x0 x19 x21} /--* t2548 byref Generating: N029 ( 3, 4) [001500] DA--GO----- * STORE_LCL_VAR byref V76 tmp36 d:1 x0 REG x0 Byref regs: 280001 {x0 x19 x21} => 280000 {x19 x21} V76 in reg x0 is becoming live [001500] Live regs: 780000 {x19 x20 x21 x22} => 780001 {x0 x19 x20 x21 x22} Live vars: {V00 V01 V02 V03 V11} => {V00 V01 V02 V03 V11 V76} Byref regs: 280000 {x19 x21} => 280001 {x0 x19 x21} genIPmappingAdd: ignoring duplicate IL offset 0x9 Generating: N031 (???,???) [003783] ----------- IL_OFFSET void INLRT @ 0x009[E-] REG NA Generating: N033 ( 1, 2) [001497] -c--------- t1497 = CNS_INT int 0 REG NA $c0 Generating: N035 ( 1, 1) [001502] ----------- t1502 = LCL_VAR byref V76 tmp36 u:1 x0 REG x0 $240 /--* t1502 byref Generating: N037 ( 3, 4) [002556] -c--------- t2556 = * LEA(b+8) byref REG NA /--* t2556 byref Generating: N039 ( 4, 3) [001503] ---XG------ t1503 = * IND int REG x1 IN0008: ldr w1, [x0, #0x08] /--* t1497 int +--* t1503 int Generating: N041 ( 9, 12) [001504] ---XGO----- * BOUNDS_CHECK_Rng -> BB254 void REG NA IN0009: cmp w1, #0 IN000a: bls (LARGEJMP)L_M30548_BB254 Generating: N043 ( 1, 1) [001501] ----------- t1501 = LCL_VAR byref V76 tmp36 u:1 x0 (last use) REG x0 $240 /--* t1501 byref Generating: N045 ( 3, 2) [001505] n---GO----- t1505 = * IND byref REG x23 V76 in reg x0 is becoming dead [001501] Live regs: 780001 {x0 x19 x20 x21 x22} => 780000 {x19 x20 x21 x22} Live vars: {V00 V01 V02 V03 V11 V76} => {V00 V01 V02 V03 V11} Byref regs: 280001 {x0 x19 x21} => 280000 {x19 x21} IN000b: ldr x23, [x0] Byref regs: 280000 {x19 x21} => A80000 {x19 x21 x23} /--* t1505 byref Generating: N047 ( 12, 14) [002551] DA-XGO----- * STORE_LCL_VAR long V167 tmp127 d:1 x23 REG x23 Byref regs: A80000 {x19 x21 x23} => 280000 {x19 x21} V167 in reg x23 is becoming live [002551] Live regs: 780000 {x19 x20 x21 x22} => F80000 {x19 x20 x21 x22 x23} Live vars: {V00 V01 V02 V03 V11} => {V00 V01 V02 V03 V11 V167} Generating: N049 ( 1, 1) [002552] ----------- t2552 = LCL_VAR long V167 tmp127 u:1 x23 (last use) REG x23 /--* t2552 long Generating: N051 ( 13, 15) [000009] DA-XGO----- * STORE_LCL_VAR long V17 loc13 d:1 x23 REG x23 V167 in reg x23 is becoming dead [002552] Live regs: F80000 {x19 x20 x21 x22 x23} => 780000 {x19 x20 x21 x22} Live vars: {V00 V01 V02 V03 V11 V167} => {V00 V01 V02 V03 V11} V17 in reg x23 is becoming live [000009] Live regs: 780000 {x19 x20 x21 x22} => F80000 {x19 x20 x21 x22 x23} Live vars: {V00 V01 V02 V03 V11} => {V00 V01 V02 V03 V11 V17} New debug range: first Generating: N053 ( 3, 4) [002558] ----------- t2558 = LCL_FLD byref V02 arg2 u:1[+0] x24 REG x24 $246 IN000c: ldr x24, [fp, #0x88] Byref regs: 280000 {x19 x21} => 1280000 {x19 x21 x24} /--* t2558 byref Generating: N055 ( 3, 4) [003709] DA--------- * STORE_LCL_VAR byref V180 cse9 d:1 x24 REG x24 Byref regs: 1280000 {x19 x21 x24} => 280000 {x19 x21} V180 in reg x24 is becoming live [003709] Live regs: F80000 {x19 x20 x21 x22 x23} => 1F80000 {x19 x20 x21 x22 x23 x24} Live vars: {V00 V01 V02 V03 V11 V17} => {V00 V01 V02 V03 V11 V17 V180} Byref regs: 280000 {x19 x21} => 1280000 {x19 x21 x24} Generating: N057 ( 1, 1) [003710] ----------- t3710 = LCL_VAR byref V180 cse9 u:1 x24 REG x24 $246 /--* t3710 byref Generating: N059 ( 8, 8) [002559] DA--------- * STORE_LCL_VAR byref V147 tmp107 d:1 x0 REG x0 IN000d: mov x0, x24 V147 in reg x0 is becoming live [002559] Live regs: 1F80000 {x19 x20 x21 x22 x23 x24} => 1F80001 {x0 x19 x20 x21 x22 x23 x24} Live vars: {V00 V01 V02 V03 V11 V17 V180} => {V00 V01 V02 V03 V11 V17 V147 V180} Byref regs: 1280000 {x19 x21 x24} => 1280001 {x0 x19 x21 x24} Generating: N061 ( 3, 4) [002561] ----------- t2561 = LCL_FLD int V02 arg2 u:1[+8] x25 REG x25 $342 IN000e: ldr w25, [fp, #0x90] /--* t2561 int Generating: N063 ( 3, 4) [003689] DA--------- * STORE_LCL_VAR int V179 cse8 d:1 x25 REG x25 V179 in reg x25 is becoming live [003689] Live regs: 1F80001 {x0 x19 x20 x21 x22 x23 x24} => 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V147 V180} => {V00 V01 V02 V03 V11 V17 V147 V179 V180} Generating: N065 ( 1, 1) [003690] ----------- t3690 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t3690 int Generating: N067 ( 8, 8) [002562] DA--------- * STORE_LCL_VAR int V148 tmp108 d:1 x1 REG x1 IN000f: mov w1, w25 V148 in reg x1 is becoming live [002562] Live regs: 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V147 V179 V180} => {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} Added IP mapping: 0x0011 STACK_EMPTY (G_M30548_IG02,ins#15,ofs#64) Generating: N069 (???,???) [003784] ----------- IL_OFFSET void INLRT @ 0x011[E-] REG NA Generating: N071 ( 1, 1) [000011] ----------- t11 = LCL_VAR long V17 loc13 u:1 x23 REG x23 /--* t11 long Generating: N073 ( 4, 3) [000012] ---XG------ t12 = * IND ubyte REG x2 IN0010: ldrb w2, [x23] Generating: N075 ( 1, 2) [000013] -c--------- t13 = CNS_INT int 0 REG NA $c0 /--* t12 ubyte +--* t13 int Generating: N077 ( 6, 6) [000014] CEQ---XG--N--- * JCMP void REG NA IN0011: cbz (LARGEJMP)L_M30548_BB05 Variable Live Range History Dump for BB01 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] =============== Generating BB02 [017..01F) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.20080020: i gcsafe LIR BB02 IN (10)={V00 V179 V11 V03 V01 V17 V180 V02 V147 V148 } + ByrefExposed + GcHeap OUT(10)={V00 V179 V11 V03 V01 V17 V180 V02 V155 V156} + ByrefExposed + GcHeap Recording Var Locations at start of BB02 V00(x19) V179(x25) V11(x22) V03(x20) V01(x21) V17(x23) V180(x24) V147(x0) V148(x1) Liveness not changing: 000000000000000180000000004000088400500000000006 {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} Live regs: 0000 {} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280001 {x0 x19 x21 x24} L_M30548_BB02: Adding label due to BB weight difference: BBJ_COND BB01 with weight 100 different from BB02 with weight 50 G_M30548_IG02: ; offs=000000H, funclet=00, bbWeight=1 , byref Mapped BB02 to G_M30548_IG03 Label: IG03, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280001 {x0 x19 x21 x24} Scope info: begin block BB02, IL range [017..01F) Generating: N081 ( 3, 2) [002565] ----------- t2565 = LCL_VAR byref V147 tmp107 u:1 x0 (last use) REG x0 $246 /--* t2565 byref Generating: N083 ( 7, 5) [002566] DA--------- * STORE_LCL_VAR byref V155 tmp115 d:1 x0 REG x0 V147 in reg x0 is becoming dead [002565] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80002 {x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} => {V00 V01 V02 V03 V11 V17 V148 V179 V180} Byref regs: 1280001 {x0 x19 x21 x24} => 1280000 {x19 x21 x24} V155 in reg x0 is becoming live [002566] Live regs: 3F80002 {x1 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V148 V179 V180} => {V00 V01 V02 V03 V11 V17 V148 V155 V179 V180} Byref regs: 1280000 {x19 x21 x24} => 1280001 {x0 x19 x21 x24} Generating: N085 ( 3, 2) [002568] ----------- t2568 = LCL_VAR int V148 tmp108 u:1 x1 (last use) REG x1 $342 /--* t2568 int Generating: N087 ( 7, 5) [002569] DA--------- * STORE_LCL_VAR int V156 tmp116 d:1 x1 REG x1 V148 in reg x1 is becoming dead [002568] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V148 V155 V179 V180} => {V00 V01 V02 V03 V11 V17 V155 V179 V180} V156 in reg x1 is becoming live [002569] Live regs: 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V155 V179 V180} => {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} Generating: N089 ( 1, 1) [001472] ----------- t1472 = LCL_VAR byref V01 arg1 u:1 x21 REG x21 $101 /--* t1472 byref Generating: N091 ( 3, 4) [002572] -c--------- t2572 = * LEA(b+8) byref REG NA /--* t2572 byref Generating: N093 ( 5, 4) [001473] n---GO----- t1473 = * IND bool REG x2 IN0012: ldrb w2, [x21, #0x08] Generating: N095 ( 1, 2) [001474] -c--------- t1474 = CNS_INT int 0 REG NA $c0 /--* t1473 bool +--* t1474 int Generating: N097 ( 7, 7) [001475] CNE----GO-N--- * JCMP void REG NA IN0013: cbnz (LARGEJMP)L_M30548_BB04 Variable Live Range History Dump for BB02 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] =============== Generating BB03 [01F..022) -> BB06 (always), preds={BB02} succs={BB06} flags=0x00000000.20080020: i gcsafe LIR BB03 IN (10)={V00 V179 V11 V03 V01 V17 V180 V02 V155 V156} + ByrefExposed + GcHeap OUT(11)={V00 V179 V11 V03 V01 V17 V180 V02 V149 V43 V150 } + ByrefExposed + GcHeap Recording Var Locations at start of BB03 V00(x19) V179(x25) V11(x22) V03(x20) V01(x21) V17(x23) V180(x24) V155(x0) V156(x1) Liveness not changing: 000000000000021000000000004000088400500000000006 {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} Live regs: 0000 {} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280001 {x0 x19 x21 x24} L_M30548_BB03: Scope info: begin block BB03, IL range [01F..022) Generating: N101 ( 3, 2) [002574] ----------- t2574 = LCL_VAR byref V155 tmp115 u:1 x0 (last use) REG x0 $246 /--* t2574 byref Generating: N103 ( 7, 5) [002575] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:4 x0 REG x0 V155 in reg x0 is becoming dead [002574] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80002 {x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} => {V00 V01 V02 V03 V11 V17 V156 V179 V180} Byref regs: 1280001 {x0 x19 x21 x24} => 1280000 {x19 x21 x24} V149 in reg x0 is becoming live [002575] Live regs: 3F80002 {x1 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V156 V179 V180} => {V00 V01 V02 V03 V11 V17 V149 V156 V179 V180} Byref regs: 1280000 {x19 x21 x24} => 1280001 {x0 x19 x21 x24} Generating: N105 ( 3, 2) [002577] ----------- t2577 = LCL_VAR int V156 tmp116 u:1 x1 (last use) REG x1 $342 /--* t2577 int Generating: N107 ( 7, 5) [002578] DA--------- * STORE_LCL_VAR int V150 tmp110 d:4 x1 REG x1 V156 in reg x1 is becoming dead [002577] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V149 V156 V179 V180} => {V00 V01 V02 V03 V11 V17 V149 V179 V180} V150 in reg x1 is becoming live [002578] Live regs: 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V149 V179 V180} => {V00 V01 V02 V03 V11 V17 V149 V150 V179 V180} Generating: N109 ( 1, 2) [001489] -c--------- t1489 = CNS_INT int 0 REG NA $c0 /--* t1489 int Generating: N111 ( 5, 5) [001494] DA--------- * STORE_LCL_VAR int V43 tmp3 d:4 x2 REG x2 IN0014: mov w2, wzr V43 in reg x2 is becoming live [001494] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80007 {x0 x1 x2 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V149 V150 V179 V180} => {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} IN0015: b L_M30548_BB06 Variable Live Range History Dump for BB03 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] =============== Generating BB04 [022..025) -> BB06 (always), preds={BB02} succs={BB06} flags=0x00000000.20090020: i label gcsafe LIR BB04 IN (10)={V00 V179 V11 V03 V01 V17 V180 V02 V155 V156} + ByrefExposed + GcHeap OUT(11)={V00 V179 V11 V03 V01 V17 V180 V02 V149 V43 V150 } + ByrefExposed + GcHeap Recording Var Locations at start of BB04 V00(x19) V179(x25) V11(x22) V03(x20) V01(x21) V17(x23) V180(x24) V155(x0) V156(x1) Change life 000000000000000038000000004000088400500000000006 {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} -> 000000000000021000000000004000088400500000000006 {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} V149 in reg x0 is becoming dead [------] Live regs: (unchanged) 0000 {} V43 in reg x2 is becoming dead [------] Live regs: (unchanged) 0000 {} V150 in reg x1 is becoming dead [------] Live regs: (unchanged) 0000 {} V155 in reg x0 is becoming live [------] Live regs: 0000 {} => 0001 {x0} V156 in reg x1 is becoming live [------] Live regs: 0001 {x0} => 0003 {x0 x1} Live regs: 0003 {x0 x1} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} GC regs: 0000 {} => 100000 {x20} Byref regs: 0001 {x0} => 1280001 {x0 x19 x21 x24} L_M30548_BB04: G_M30548_IG03: ; offs=00004CH, funclet=00, bbWeight=0.50, byref Mapped BB04 to G_M30548_IG04 Label: IG04, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280001 {x0 x19 x21 x24} Scope info: begin block BB04, IL range [022..025) Generating: N115 ( 3, 2) [002581] ----------- t2581 = LCL_VAR byref V155 tmp115 u:1 x0 (last use) REG x0 $246 /--* t2581 byref Generating: N117 ( 7, 5) [002582] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:3 x0 REG x0 V155 in reg x0 is becoming dead [002581] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80002 {x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V155 V156 V179 V180} => {V00 V01 V02 V03 V11 V17 V156 V179 V180} Byref regs: 1280001 {x0 x19 x21 x24} => 1280000 {x19 x21 x24} V149 in reg x0 is becoming live [002582] Live regs: 3F80002 {x1 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V156 V179 V180} => {V00 V01 V02 V03 V11 V17 V149 V156 V179 V180} Byref regs: 1280000 {x19 x21 x24} => 1280001 {x0 x19 x21 x24} Generating: N119 ( 3, 2) [002584] ----------- t2584 = LCL_VAR int V156 tmp116 u:1 x1 (last use) REG x1 $342 /--* t2584 int Generating: N121 ( 7, 5) [002585] DA--------- * STORE_LCL_VAR int V150 tmp110 d:3 x1 REG x1 V156 in reg x1 is becoming dead [002584] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V149 V156 V179 V180} => {V00 V01 V02 V03 V11 V17 V149 V179 V180} V150 in reg x1 is becoming live [002585] Live regs: 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V149 V179 V180} => {V00 V01 V02 V03 V11 V17 V149 V150 V179 V180} Generating: N123 ( 1, 2) [001482] ----------- t1482 = CNS_INT int 1 REG x2 $c1 IN0016: mov w2, #1 /--* t1482 int Generating: N125 ( 5, 5) [001487] DA--------- * STORE_LCL_VAR int V43 tmp3 d:3 x2 REG x2 V43 in reg x2 is becoming live [001487] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80007 {x0 x1 x2 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V149 V150 V179 V180} => {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} IN0017: b L_M30548_BB06 Variable Live Range History Dump for BB04 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] =============== Generating BB05 [025..026), preds={BB01} succs={BB06} flags=0x00000000.20090020: i label gcsafe LIR BB05 IN (10)={V00 V179 V11 V03 V01 V17 V180 V02 V147 V148} + ByrefExposed + GcHeap OUT(11)={V00 V179 V11 V03 V01 V17 V180 V02 V149 V43 V150 } + ByrefExposed + GcHeap Recording Var Locations at start of BB05 V00(x19) V179(x25) V11(x22) V03(x20) V01(x21) V17(x23) V180(x24) V147(x0) V148(x1) Change life 000000000000000038000000004000088400500000000006 {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} -> 000000000000000180000000004000088400500000000006 {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} V149 in reg x0 is becoming dead [------] Live regs: (unchanged) 0000 {} V43 in reg x2 is becoming dead [------] Live regs: (unchanged) 0000 {} V150 in reg x1 is becoming dead [------] Live regs: (unchanged) 0000 {} V147 in reg x0 is becoming live [------] Live regs: 0000 {} => 0001 {x0} V148 in reg x1 is becoming live [------] Live regs: 0001 {x0} => 0003 {x0 x1} Live regs: 0003 {x0 x1} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} GC regs: 0000 {} => 100000 {x20} Byref regs: 0001 {x0} => 1280001 {x0 x19 x21 x24} L_M30548_BB05: G_M30548_IG04: ; offs=000060H, funclet=00, bbWeight=0.50, byref Mapped BB05 to G_M30548_IG05 Label: IG05, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280001 {x0 x19 x21 x24} Scope info: begin block BB05, IL range [025..026) Generating: N129 ( 3, 2) [002588] ----------- t2588 = LCL_VAR byref V147 tmp107 u:1 x0 (last use) REG x0 $246 /--* t2588 byref Generating: N131 ( 7, 5) [002589] DA--------- * STORE_LCL_VAR byref V149 tmp109 d:2 x0 REG x0 V147 in reg x0 is becoming dead [002588] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80002 {x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V147 V148 V179 V180} => {V00 V01 V02 V03 V11 V17 V148 V179 V180} Byref regs: 1280001 {x0 x19 x21 x24} => 1280000 {x19 x21 x24} V149 in reg x0 is becoming live [002589] Live regs: 3F80002 {x1 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V148 V179 V180} => {V00 V01 V02 V03 V11 V17 V148 V149 V179 V180} Byref regs: 1280000 {x19 x21 x24} => 1280001 {x0 x19 x21 x24} Generating: N133 ( 3, 2) [002591] ----------- t2591 = LCL_VAR int V148 tmp108 u:1 x1 (last use) REG x1 $342 /--* t2591 int Generating: N135 ( 7, 5) [002592] DA--------- * STORE_LCL_VAR int V150 tmp110 d:2 x1 REG x1 V148 in reg x1 is becoming dead [002591] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V148 V149 V179 V180} => {V00 V01 V02 V03 V11 V17 V149 V179 V180} V150 in reg x1 is becoming live [002592] Live regs: 3F80001 {x0 x19 x20 x21 x22 x23 x24 x25} => 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V149 V179 V180} => {V00 V01 V02 V03 V11 V17 V149 V150 V179 V180} Generating: N137 ( 1, 2) [000021] ----------- t21 = CNS_INT int 2 REG x2 $c2 IN0018: mov w2, #2 /--* t21 int Generating: N139 ( 5, 5) [000026] DA--------- * STORE_LCL_VAR int V43 tmp3 d:2 x2 REG x2 V43 in reg x2 is becoming live [000026] Live regs: 3F80003 {x0 x1 x19 x20 x21 x22 x23 x24 x25} => 3F80007 {x0 x1 x2 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V149 V150 V179 V180} => {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} Variable Live Range History Dump for BB05 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] =============== Generating BB06 [026..02D), preds={BB03,BB04,BB05} succs={BB07} flags=0x00000002.20090020: i label hascall gcsafe LIR BB06 IN (11)={V00 V179 V11 V03 V01 V17 V180 V02 V149 V43 V150} + ByrefExposed + GcHeap OUT(9)={V00 V179 V11 V03 V01 V15 V17 V180 V02 } + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V00(x19) V179(x25) V11(x22) V03(x20) V01(x21) V17(x23) V180(x24) V149(x0) V43(x2) V150(x1) Liveness not changing: 000000000000000038000000004000088400500000000006 {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} Live regs: 0000 {} => 3F80007 {x0 x1 x2 x19 x20 x21 x22 x23 x24 x25} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280001 {x0 x19 x21 x24} L_M30548_BB06: G_M30548_IG05: ; offs=000068H, funclet=00, bbWeight=0.50, byref Mapped BB06 to G_M30548_IG06 Label: IG06, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280001 {x0 x19 x21 x24} Scope info: begin block BB06, IL range [026..02D) Generating: N143 ( 3, 2) [002596] ----------- t2596 = LCL_VAR byref V149 tmp109 u:1 x0 (last use) REG x0 $246 /--* t2596 byref Generating: N145 (???,???) [004187] ----------- t4187 = * PUTARG_REG byref REG x0 V149 in reg x0 is becoming dead [002596] Live regs: 3F80007 {x0 x1 x2 x19 x20 x21 x22 x23 x24 x25} => 3F80006 {x1 x2 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V43 V149 V150 V179 V180} => {V00 V01 V02 V03 V11 V17 V43 V150 V179 V180} Byref regs: 1280001 {x0 x19 x21 x24} => 1280000 {x19 x21 x24} Byref regs: 1280000 {x19 x21 x24} => 1280001 {x0 x19 x21 x24} Generating: N147 ( 3, 2) [002597] ----------- t2597 = LCL_VAR int V150 tmp110 u:1 x1 (last use) REG x1 $342 /--* t2597 int Generating: N149 (???,???) [004188] ----------- t4188 = * PUTARG_REG int REG x1 V150 in reg x1 is becoming dead [002597] Live regs: 3F80006 {x1 x2 x19 x20 x21 x22 x23 x24 x25} => 3F80004 {x2 x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V43 V150 V179 V180} => {V00 V01 V02 V03 V11 V17 V43 V179 V180} /--* t4187 byref +--* t4188 int Generating: N151 ( 6, 4) [002595] -c--------- t2595 = * FIELD_LIST struct REG NA $141 Generating: N153 ( 3, 2) [000029] ----------- t29 = LCL_VAR int V43 tmp3 u:1 x2 (last use) REG x2 $281 /--* t29 int Generating: N155 (???,???) [004189] ----------- t4189 = * PUTARG_REG int REG x2 V43 in reg x2 is becoming dead [000029] Live regs: 3F80004 {x2 x19 x20 x21 x22 x23 x24 x25} => 3F80000 {x19 x20 x21 x22 x23 x24 x25} Live vars: {V00 V01 V02 V03 V11 V17 V43 V179 V180} => {V00 V01 V02 V03 V11 V17 V179 V180} Generating: N157 ( 2, 8) [002594] H---------- t2594 = CNS_INT(h) long 0x40000000005401e8 ftn REG x11 $43 IN0019: adrp x11, [HIGH RELOC #0x40000000005401e8] // function address IN001a: add x11, x11, [LOW RELOC #0x40000000005401e8] /--* t2594 long Generating: N159 (???,???) [004190] ----------- t4190 = * PUTARG_REG long REG x11 /--* t2595 struct arg1 x0,x1 +--* t4189 int arg2 in x2 +--* t4190 long r2r cell in x11 Generating: N161 ( 25, 19) [000030] --CXG------ t30 = * CALL r2r_ind int REG x0 $2c1 Byref regs: 1280001 {x0 x19 x21 x24} => 1280000 {x19 x21 x24} IN001b: ldr x3, [x11] Call: GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} [28] Rec call GC vars = 000000000000000000000000000000000000000000000000 IN001c: blr x3 /--* t30 int Generating: N163 ( 25, 19) [000034] DA-XG------ * STORE_LCL_VAR int V15 loc11 d:1 x26 REG x26 IN001d: mov w26, w0 V15 in reg x26 is becoming live [000034] Live regs: 3F80000 {x19 x20 x21 x22 x23 x24 x25} => 7F80000 {x19 x20 x21 x22 x23 x24 x25 x26} Live vars: {V00 V01 V02 V03 V11 V17 V179 V180} => {V00 V01 V02 V03 V11 V15 V17 V179 V180} New debug range: first Variable Live Range History Dump for BB06 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] =============== Generating BB07 [02D..05B) -> BB47 (always), preds={BB06,BB62} succs={BB47} flags=0x00000008.2509a020: i Loop Loop1 label gcsafe bwd bwd-target LoopPH LIR BB07 IN (9)={ V00 V179 V11 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB07 V00(x19) V179(x25) V11(x22) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008A400500000000006 {V00 V01 V02 V03 V11 V15 V17 V179 V180} Live regs: 0000 {} => 7F80000 {x19 x20 x21 x22 x23 x24 x25 x26} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB07: G_M30548_IG06: ; offs=00006CH, funclet=00, bbWeight=1 , byref Mapped BB07 to G_M30548_IG07 Label: IG07, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB07, IL range [02D..05B) Added IP mapping: 0x002D STACK_EMPTY (G_M30548_IG07,ins#0,ofs#0) label Generating: N167 (???,???) [003785] ----------- IL_OFFSET void INLRT @ 0x02D[E-] REG NA Generating: N169 ( 1, 2) [000035] -c--------- t35 = CNS_INT int 0 REG NA $c0 /--* t35 int Generating: N171 ( 1, 3) [000037] DA--------- * STORE_LCL_VAR int V04 loc0 d:1 x27 REG x27 IN001e: mov w27, wzr V04 in reg x27 is becoming live [000037] Live regs: 7F80000 {x19 x20 x21 x22 x23 x24 x25 x26} => FF80000 {x19 x20 x21 x22 x23 x24 x25 x26 x27} Live vars: {V00 V01 V02 V03 V11 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V11 V15 V17 V179 V180} New debug range: first Added IP mapping: 0x002F STACK_EMPTY (G_M30548_IG07,ins#1,ofs#4) Generating: N173 (???,???) [003786] ----------- IL_OFFSET void INLRT @ 0x02F[E-] REG NA Generating: N175 ( 1, 2) [000038] ----------- t38 = CNS_INT int -1 REG x28 $c4 IN001f: movn w28, #0 /--* t38 int Generating: N177 ( 1, 3) [000040] DA--------- * STORE_LCL_VAR int V05 loc1 d:1 x28 REG x28 V05 in reg x28 is becoming live [000040] Live regs: FF80000 {x19 x20 x21 x22 x23 x24 x25 x26 x27} => 1FF80000 {x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V11 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V11 V15 V17 V179 V180} New debug range: first Added IP mapping: 0x0031 STACK_EMPTY (G_M30548_IG07,ins#2,ofs#8) Generating: N179 (???,???) [003787] ----------- IL_OFFSET void INLRT @ 0x031[E-] REG NA Generating: N181 ( 1, 4) [000041] ----------- t41 = CNS_INT int 0x7FFFFFFF REG x3 $c9 IN0020: movn w3, #0x8000 LSL #16 /--* t41 int Generating: N183 ( 1, 4) [000043] DA--------- * STORE_LCL_VAR int V06 loc2 d:1 NA REG NA IN0021: str w3, [fp, #0x84] // [V06 loc2] Live vars: {V00 V01 V02 V03 V04 V05 V11 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V11 V15 V17 V179 V180} New debug range: first Added IP mapping: 0x0037 STACK_EMPTY (G_M30548_IG07,ins#4,ofs#16) Generating: N185 (???,???) [003788] ----------- IL_OFFSET void INLRT @ 0x037[E-] REG NA Generating: N187 ( 1, 2) [000044] -c--------- t44 = CNS_INT int 0 REG NA $c0 /--* t44 int Generating: N189 ( 1, 3) [000046] DA--------- * STORE_LCL_VAR int V07 loc3 d:1 NA REG NA IN0022: str wzr, [fp, #0x80] // [V07 loc3] Live vars: {V00 V01 V02 V03 V04 V05 V06 V11 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V11 V15 V17 V179 V180} New debug range: first Added IP mapping: 0x0039 STACK_EMPTY (G_M30548_IG07,ins#5,ofs#20) Generating: N191 (???,???) [003789] ----------- IL_OFFSET void INLRT @ 0x039[E-] REG NA Generating: N193 ( 1, 2) [002598] -c--------- t2598 = CNS_INT int 0 REG NA $c0 /--* t2598 int Generating: N195 ( 1, 3) [000049] DA--------- * STORE_LCL_VAR int V09 loc5 d:1 x5 REG x5 IN0023: mov w5, wzr V09 in reg x5 is becoming live [000049] Live regs: 1FF80000 {x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF80020 {x5 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V11 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V15 V17 V179 V180} New debug range: first Added IP mapping: 0x003C STACK_EMPTY (G_M30548_IG07,ins#6,ofs#24) Generating: N197 (???,???) [003790] ----------- IL_OFFSET void INLRT @ 0x03C[E-] REG NA Generating: N199 ( 1, 2) [000050] ----------- t50 = CNS_INT int -1 REG x6 $c4 IN0024: movn w6, #0 /--* t50 int Generating: N201 ( 1, 3) [000052] DA--------- * STORE_LCL_VAR int V10 loc6 d:1 x6 REG x6 V10 in reg x6 is becoming live [000052] Live regs: 1FF80020 {x5 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF80060 {x5 x6 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V11 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V15 V17 V179 V180} New debug range: first Added IP mapping: 0x003F STACK_EMPTY (G_M30548_IG07,ins#7,ofs#28) Generating: N203 (???,???) [003791] ----------- IL_OFFSET void INLRT @ 0x03F[E-] REG NA Generating: N205 ( 1, 2) [002599] -c--------- t2599 = CNS_INT int 0 REG NA $c0 /--* t2599 int Generating: N207 ( 1, 3) [000055] DA--------- * STORE_LCL_VAR int V12 loc8 d:1 x7 REG x7 IN0025: mov w7, wzr V12 in reg x7 is becoming live [000055] Live regs: 1FF80060 {x5 x6 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF800E0 {x5 x6 x7 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V17 V179 V180} New debug range: first Added IP mapping: 0x0042 STACK_EMPTY (G_M30548_IG07,ins#8,ofs#32) Generating: N209 (???,???) [003792] ----------- IL_OFFSET void INLRT @ 0x042[E-] REG NA Generating: N211 ( 1, 2) [000056] -c--------- t56 = CNS_INT int 0 REG NA $c0 /--* t56 int Generating: N213 ( 1, 3) [000058] DA--------- * STORE_LCL_VAR int V13 loc9 d:1 x8 REG x8 IN0026: mov w8, wzr V13 in reg x8 is becoming live [000058] Live regs: 1FF800E0 {x5 x6 x7 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF801E0 {x5 x6 x7 x8 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} New debug range: first Added IP mapping: 0x0045 STACK_EMPTY (G_M30548_IG07,ins#9,ofs#36) Generating: N215 (???,???) [003793] ----------- IL_OFFSET void INLRT @ 0x045[E-] REG NA Generating: N217 ( 1, 1) [000059] ----------- t59 = LCL_VAR int V15 loc11 u:2 x26 REG x26 $283 /--* t59 int Generating: N219 ( 1, 3) [000061] DA--------- * STORE_LCL_VAR int V16 loc12 d:1 x1 REG x1 IN0027: mov w1, w26 V16 in reg x1 is becoming live [000061] Live regs: 1FF801E0 {x5 x6 x7 x8 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF801E2 {x1 x5 x6 x7 x8 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V179 V180} New debug range: first Added IP mapping: 0x0049 STACK_EMPTY (G_M30548_IG07,ins#10,ofs#40) Generating: N221 (???,???) [003794] ----------- IL_OFFSET void INLRT @ 0x049[E-] REG NA Generating: N223 ( 1, 1) [003712] ----------- t3712 = LCL_VAR byref V180 cse9 u:1 x24 REG x24 $246 /--* t3712 byref Generating: N225 ( 1, 3) [002602] DA--------- * STORE_LCL_VAR byref V157 tmp117 d:1 x9 REG x9 IN0028: mov x9, x24 V157 in reg x9 is becoming live [002602] Live regs: 1FF801E2 {x1 x5 x6 x7 x8 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V157 V179 V180} Byref regs: 1280000 {x19 x21 x24} => 1280200 {x9 x19 x21 x24} genIPmappingAdd: ignoring duplicate IL offset 0x49 Generating: N227 (???,???) [003795] ----------- IL_OFFSET void INLRT @ 0x049[E-] REG NA Generating: N229 ( 1, 1) [001512] ----------- t1512 = LCL_VAR byref V157 tmp117 u:1 x9 REG x9 $246 /--* t1512 byref Generating: N231 ( 1, 3) [000068] DA--------- * STORE_LCL_VAR byref V23 loc19 NA REG NA IN0029: str x9, [fp, #0x58] // [V23 loc19] Added IP mapping: 0x0051 STACK_EMPTY (G_M30548_IG07,ins#12,ofs#48) Generating: N233 (???,???) [003796] ----------- IL_OFFSET void INLRT @ 0x051[E-] REG NA Generating: N235 ( 1, 1) [000069] ----------- t69 = LCL_VAR byref V157 tmp117 u:1 x9 (last use) REG x9 $246 /--* t69 byref Generating: N237 ( 1, 3) [002608] DA--------- * STORE_LCL_VAR long V168 tmp128 d:1 x9 REG x9 V157 in reg x9 is becoming dead [000069] Live regs: 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF801E2 {x1 x5 x6 x7 x8 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V157 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V179 V180} Byref regs: 1280200 {x9 x19 x21 x24} => 1280000 {x19 x21 x24} V168 in reg x9 is becoming live [002608] Live regs: 1FF801E2 {x1 x5 x6 x7 x8 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V168 V179 V180} Generating: N239 ( 1, 1) [002609] ----------- t2609 = LCL_VAR long V168 tmp128 u:1 x9 (last use) REG x9 $3c4 /--* t2609 long Generating: N241 ( 2, 4) [000072] DA--------- * STORE_LCL_VAR long V22 loc18 d:1 x9 REG x9 V168 in reg x9 is becoming dead [002609] Live regs: 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF801E2 {x1 x5 x6 x7 x8 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V168 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V179 V180} V22 in reg x9 is becoming live [000072] Live regs: 1FF801E2 {x1 x5 x6 x7 x8 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} New debug range: first IN002a: b L_M30548_BB47 Variable Live Range History Dump for BB07 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG07,ins#10,ofs#40), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB08 [05B..061) -> BB13 (cond), preds={BB49} succs={BB09,BB13} flags=0x00000008.21016020: i Loop Loop0 label bwd bwd-target LIR BB08 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB08 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} V18 in reg x13 is becoming live [------] Live regs: 0000 {} => 2000 {x13} New debug range: first Live regs: 2000 {x13} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB08: G_M30548_IG07: ; offs=000080H, funclet=00, bbWeight=8 , byref Mapped BB08 to G_M30548_IG08 Label: IG08, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB08, IL range [05B..061) Added IP mapping: 0x005B STACK_EMPTY (G_M30548_IG08,ins#0,ofs#0) label Generating: N313 (???,???) [003797] ----------- IL_OFFSET void INLRT @ 0x05B[E-] REG NA Generating: N315 ( 1, 1) [001226] ----------- t1226 = LCL_VAR int V18 loc14 u:5 x13 REG x13 Generating: N317 ( 1, 2) [001227] -c--------- t1227 = CNS_INT int 69 REG NA $d2 /--* t1226 int +--* t1227 int Generating: N319 ( 3, 4) [001228] N------N-U- * GT void REG NA IN002b: cmp w13, #69 Generating: N321 ( 5, 6) [001229] ----------- * JTRUE void REG NA $VN.Void IN002c: bhi (LARGEJMP)L_M30548_BB13 Variable Live Range History Dump for BB08 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG07,ins#10,ofs#40), (G_M30548_IG07,ins#13,ofs#52)]; x10 [(G_M30548_IG07,ins#13,ofs#52), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG07,ins#13,ofs#52), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB09 [061..061) -> BB10 (cond), preds={BB08} succs={BB255,BB10} flags=0x00000000.21000020: i bwd LIR BB09 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V18 V22 V04 V05 V13 V182 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB09 V16(x10) V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Live regs: 0000 {} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB09: Scope info: begin block BB09, IL range [061..061) Added IP mapping: 0x0061 STACK_EMPTY (G_M30548_IG08,ins#2,ofs#12) label Generating: N325 (???,???) [003798] ----------- IL_OFFSET void INLRT @ 0x061[E-] REG NA Generating: N327 ( 1, 1) [001361] ----------- t1361 = LCL_VAR int V18 loc14 u:5 x13 REG x13 Generating: N329 ( 1, 2) [001362] -c--------- t1362 = CNS_INT int -34 REG NA $d6 /--* t1361 int +--* t1362 int Generating: N331 ( 3, 4) [001363] ----------- t1363 = * ADD int REG x14 IN002d: sub w14, w13, #34 /--* t1363 int Generating: N333 (???,???) [004192] DA--------- * STORE_LCL_VAR int V182 rat0 x14 REG x14 V182 in reg x14 is becoming live [004192] Live regs: 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF867E0 {x5 x6 x7 x8 x9 x10 x13 x14 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V182} Generating: N335 ( 3, 2) [004194] ----------- t4194 = LCL_VAR int V182 rat0 x14 REG x14 Generating: N337 ( 1, 2) [004195] -c--------- t4195 = CNS_INT int 5 REG NA /--* t4194 int +--* t4195 int Generating: N339 ( 8, 5) [004196] ---------U- * GT void REG NA IN002e: cmp w14, #5 Generating: N341 ( 10, 7) [004197] ----------- * JTRUE void REG NA IN002f: bhi (LARGEJMP)L_M30548_BB10 Variable Live Range History Dump for BB09 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG07,ins#13,ofs#52), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG07,ins#13,ofs#52), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB255 [061..083) -> BB31,BB17,BB259,BB30,BB259,BB31 (switch), preds={BB09} succs={BB17,BB30,BB31,BB259} flags=0x00000000.21000020: i bwd LIR BB255 IN (21)={V16 V00 V179 V18 V22 V04 V05 V13 V182 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB255 V16(x10) V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V182(x14) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC007600440501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V182} Live regs: 0000 {} => 1FF867E0 {x5 x6 x7 x8 x9 x10 x13 x14 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB255: Scope info: begin block BB255, IL range [061..083) Generating: N3689 (???,???) [004198] ----------- t4198 = LCL_VAR int V182 rat0 x14 (last use) REG x14 /--* t4198 int Generating: N3691 (???,???) [004199] ---------U- t4199 = * CAST long <- ulong <- uint REG x0 V182 in reg x14 is becoming dead [004198] Live regs: 1FF867E0 {x5 x6 x7 x8 x9 x10 x13 x14 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V182} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} IN0030: mov w0, w14 Generating: N3693 (???,???) [004200] ----------- t4200 = JMPTABLE long REG x1 J_M30548_DS00 LABEL DWORD DD L_M30548_BB31 DD L_M30548_BB17 DD L_M30548_BB259 DD L_M30548_BB30 DD L_M30548_BB259 DD L_M30548_BB31 IN0031: adr x1, (LARGEADR)[@RWD00] /--* t4199 long +--* t4200 long Generating: N3695 (???,???) [004201] ----------- * SWITCH_TABLE void REG NA IN0032: ldr w1, [x1, x0, LSL #2] IN0033: adr x11, (LARGEADR)[L_M30548_BB01] IN0034: add x1, x1, x11 IN0035: br x1 Variable Live Range History Dump for BB255 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG07,ins#13,ofs#52), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG07,ins#13,ofs#52), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB259 [???..???) -> BB47 (always), preds={BB255(2)} succs={BB47} flags=0x00000000.21010040: internal label bwd LIR BB259 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} Recording Var Locations at start of BB259 V16(x10) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} -> 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} V18 in reg x13 is becoming dead [------] Live regs: (unchanged) 0000 {} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB259: G_M30548_IG08: ; offs=0000B4H, funclet=00, bbWeight=8 , byref Mapped BB259 to G_M30548_IG09 Label: IG09, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB259, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M30548_IG09,ins#0,ofs#0) label Generating: N001 ( 1, 1) [004305] ----------- t4305 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4305 int Generating: N002 ( 2, 2) [004306] ----------- t4306 = * COPY int REG x1 IN0036: mov w1, w10 V16 in reg x10 is becoming dead [004305] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004306] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Scope info: ignoring block end IN0037: b L_M30548_BB47 Variable Live Range History Dump for BB259 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG07,ins#13,ofs#52), (G_M30548_IG09,ins#1,ofs#4)]; x1 [(G_M30548_IG09,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG07,ins#13,ofs#52), (G_M30548_IG08,ins#11,ofs#60)] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB10 [083..083) -> BB11 (cond), preds={BB09} succs={BB256,BB11} flags=0x00000000.21010020: i label bwd LIR BB10 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V18 V22 V04 V05 V13 V183 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB10 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} V18 in reg x13 is becoming live [------] Live regs: 0000 {} => 2000 {x13} New debug range: new var or location Live regs: 2000 {x13} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB10: G_M30548_IG09: ; offs=0000F0H, funclet=00, bbWeight=4 , byref Mapped BB10 to G_M30548_IG10 Label: IG10, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB10, IL range [083..083) Added IP mapping: 0x0083 STACK_EMPTY (G_M30548_IG10,ins#0,ofs#0) label Generating: N345 (???,???) [003799] ----------- IL_OFFSET void INLRT @ 0x083[E-] REG NA Generating: N347 ( 1, 1) [001365] ----------- t1365 = LCL_VAR int V18 loc14 u:5 x13 REG x13 Generating: N349 ( 1, 2) [001366] -c--------- t1366 = CNS_INT int -44 REG NA $d7 /--* t1365 int +--* t1366 int Generating: N351 ( 3, 4) [001367] ----------- t1367 = * ADD int REG x12 IN0038: sub w12, w13, #44 /--* t1367 int Generating: N353 (???,???) [004203] DA--------- * STORE_LCL_VAR int V183 rat1 x12 REG x12 V183 in reg x12 is becoming live [004203] Live regs: 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF837E0 {x5 x6 x7 x8 x9 x10 x12 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V183} Generating: N355 ( 3, 2) [004205] ----------- t4205 = LCL_VAR int V183 rat1 x12 REG x12 Generating: N357 ( 1, 2) [004206] -c--------- t4206 = CNS_INT int 4 REG NA /--* t4205 int +--* t4206 int Generating: N359 ( 8, 5) [004207] ---------U- * GT void REG NA IN0039: cmp w12, #4 Generating: N361 ( 10, 7) [004208] ----------- * JTRUE void REG NA IN003a: bhi (LARGEJMP)L_M30548_BB11 Variable Live Range History Dump for BB10 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG09,ins#1,ofs#4), (G_M30548_IG09,ins#2,ofs#8)]; x10 [(G_M30548_IG09,ins#2,ofs#8), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG09,ins#2,ofs#8), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB256 [083..0A1) -> BB23,BB260,BB21,BB260,BB18 (switch), preds={BB10} succs={BB18,BB21,BB23,BB260} flags=0x00000000.21000020: i bwd LIR BB256 IN (20)={V16 V00 V179 V22 V04 V05 V13 V183 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB256 V16(x10) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V183(x12) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC007600480501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180 V183} -> 00000000000000000000000000400008AC00760048050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180 V183} V18 in reg x13 is becoming dead [------] Live regs: (unchanged) 0000 {} Live regs: 0000 {} => 1FF817E0 {x5 x6 x7 x8 x9 x10 x12 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB256: Scope info: begin block BB256, IL range [083..0A1) Generating: N3789 (???,???) [004209] ----------- t4209 = LCL_VAR int V183 rat1 x12 (last use) REG x12 /--* t4209 int Generating: N3791 (???,???) [004210] ---------U- t4210 = * CAST long <- ulong <- uint REG x13 V183 in reg x12 is becoming dead [004209] Live regs: 1FF817E0 {x5 x6 x7 x8 x9 x10 x12 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180 V183} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} IN003b: mov w13, w12 Generating: N3793 (???,???) [004211] ----------- t4211 = JMPTABLE long REG x0 J_M30548_DS24 LABEL DWORD DD L_M30548_BB23 DD L_M30548_BB260 DD L_M30548_BB21 DD L_M30548_BB260 DD L_M30548_BB18 IN003c: adr x0, (LARGEADR)[@RWD24] /--* t4210 long +--* t4211 long Generating: N3795 (???,???) [004212] ----------- * SWITCH_TABLE void REG NA IN003d: ldr w0, [x0, x13, LSL #2] IN003e: adr x1, (LARGEADR)[L_M30548_BB01] IN003f: add x0, x0, x1 IN0040: br x0 Variable Live Range History Dump for BB256 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG09,ins#2,ofs#8), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG09,ins#2,ofs#8), (G_M30548_IG10,ins#3,ofs#16)] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB260 [???..???) -> BB47 (always), preds={BB256(2)} succs={BB47} flags=0x00000000.21010040: internal label bwd LIR BB260 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} Recording Var Locations at start of BB260 V16(x10) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB260: G_M30548_IG10: ; offs=0000F8H, funclet=00, bbWeight=8 , byref Mapped BB260 to G_M30548_IG11 Label: IG11, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB260, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP (G_M30548_IG11,ins#0,ofs#0) label Generating: N001 ( 1, 1) [004307] ----------- t4307 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4307 int Generating: N002 ( 2, 2) [004308] ----------- t4308 = * COPY int REG x1 IN0041: mov w1, w10 V16 in reg x10 is becoming dead [004307] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004308] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Scope info: ignoring block end IN0042: b L_M30548_BB47 Variable Live Range History Dump for BB260 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG09,ins#2,ofs#8), (G_M30548_IG11,ins#1,ofs#4)]; x1 [(G_M30548_IG11,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB11 [0A1..0AA) -> BB38 (cond), preds={BB10} succs={BB12,BB38} flags=0x00000000.21010020: i label bwd LIR BB11 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB11 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} V18 in reg x13 is becoming live [------] Live regs: 0000 {} => 2000 {x13} New debug range: new var or location Live regs: 2000 {x13} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB11: G_M30548_IG11: ; offs=000128H, funclet=00, bbWeight=4 , byref Mapped BB11 to G_M30548_IG12 Label: IG12, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB11, IL range [0A1..0AA) Added IP mapping: 0x00A1 STACK_EMPTY (G_M30548_IG12,ins#0,ofs#0) label Generating: N365 (???,???) [003800] ----------- IL_OFFSET void INLRT @ 0x0A1[E-] REG NA Generating: N367 ( 1, 1) [001369] ----------- t1369 = LCL_VAR int V18 loc14 u:5 x13 (last use) REG x13 Generating: N369 ( 1, 2) [001370] -c--------- t1370 = CNS_INT int 69 REG NA $d2 /--* t1369 int +--* t1370 int Generating: N371 ( 3, 4) [001371] J------N--- * EQ void REG NA V18 in reg x13 is becoming dead [001369] Live regs: 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} IN0043: cmp w13, #69 Generating: N373 ( 5, 6) [001372] ----------- * JTRUE void REG NA $VN.Void IN0044: beq (LARGEJMP)L_M30548_BB38 Variable Live Range History Dump for BB11 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG11,ins#1,ofs#4), (G_M30548_IG11,ins#2,ofs#8)]; x10 [(G_M30548_IG11,ins#2,ofs#8), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG11,ins#2,ofs#8), (G_M30548_IG12,ins#0,ofs#0)] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB12 [0AA..0AF) -> BB47 (always), preds={BB11} succs={BB47} flags=0x00000000.21000020: i bwd LIR BB12 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB12 V16(x10) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB12: Scope info: begin block BB12, IL range [0AA..0AF) Generating: N001 ( 1, 1) [004365] ----------- t4365 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4365 int Generating: N002 ( 2, 2) [004366] ----------- t4366 = * COPY int REG x1 IN0045: mov w1, w10 V16 in reg x10 is becoming dead [004365] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004366] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} IN0046: b L_M30548_BB47 Variable Live Range History Dump for BB12 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG11,ins#2,ofs#8), (G_M30548_IG12,ins#3,ofs#16)]; x1 [(G_M30548_IG12,ins#3,ofs#16), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB13 [0AF..0B8) -> BB35 (cond), preds={BB08} succs={BB14,BB35} flags=0x00000000.21010020: i label bwd LIR BB13 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB13 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} V18 in reg x13 is becoming live [------] Live regs: 0000 {} => 2000 {x13} New debug range: new var or location Live regs: 2000 {x13} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB13: G_M30548_IG12: ; offs=000130H, funclet=00, bbWeight=8 , byref Mapped BB13 to G_M30548_IG13 Label: IG13, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB13, IL range [0AF..0B8) Added IP mapping: 0x00AF STACK_EMPTY (G_M30548_IG13,ins#0,ofs#0) label Generating: N379 (???,???) [003801] ----------- IL_OFFSET void INLRT @ 0x0AF[E-] REG NA Generating: N381 ( 1, 1) [001230] ----------- t1230 = LCL_VAR int V18 loc14 u:5 x13 REG x13 Generating: N383 ( 1, 2) [001231] -c--------- t1231 = CNS_INT int 92 REG NA $d3 /--* t1230 int +--* t1231 int Generating: N385 ( 3, 4) [001232] J------N--- * EQ void REG NA IN0047: cmp w13, #92 Generating: N387 ( 5, 6) [001233] ----------- * JTRUE void REG NA $VN.Void IN0048: beq (LARGEJMP)L_M30548_BB35 Variable Live Range History Dump for BB13 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG12,ins#3,ofs#16), (G_M30548_IG12,ins#4,ofs#20)]; x10 [(G_M30548_IG12,ins#4,ofs#20), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG12,ins#4,ofs#20), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB14 [0B8..0C1) -> BB38 (cond), preds={BB13} succs={BB15,BB38} flags=0x00000000.21000020: i bwd LIR BB14 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB14 V16(x10) V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Live regs: 0000 {} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB14: Scope info: begin block BB14, IL range [0B8..0C1) Added IP mapping: 0x00B8 STACK_EMPTY (G_M30548_IG13,ins#2,ofs#12) label Generating: N391 (???,???) [003802] ----------- IL_OFFSET void INLRT @ 0x0B8[E-] REG NA Generating: N393 ( 1, 1) [001257] ----------- t1257 = LCL_VAR int V18 loc14 u:5 x13 REG x13 Generating: N395 ( 1, 2) [001258] -c--------- t1258 = CNS_INT int 101 REG NA $d4 /--* t1257 int +--* t1258 int Generating: N397 ( 3, 4) [001259] J------N--- * EQ void REG NA IN0049: cmp w13, #101 Generating: N399 ( 5, 6) [001260] ----------- * JTRUE void REG NA $VN.Void IN004a: beq (LARGEJMP)L_M30548_BB38 Variable Live Range History Dump for BB14 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG12,ins#4,ofs#20), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG12,ins#4,ofs#20), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB15 [0C1..0CA) -> BB47 (cond), preds={BB14} succs={BB16,BB47} flags=0x00000000.21000020: i bwd LIR BB15 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB15 V16(x10) V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} Live regs: 0000 {} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB15: Scope info: begin block BB15, IL range [0C1..0CA) Added IP mapping: 0x00C1 STACK_EMPTY (G_M30548_IG13,ins#4,ofs#24) label Generating: N403 (???,???) [003803] ----------- IL_OFFSET void INLRT @ 0x0C1[E-] REG NA Generating: N405 ( 1, 1) [001352] ----------- t1352 = LCL_VAR int V18 loc14 u:5 x13 (last use) REG x13 Generating: N407 ( 1, 4) [001353] ----------- t1353 = CNS_INT int 0x2030 REG x1 $d5 IN004b: mov w1, #0x2030 /--* t1352 int +--* t1353 int Generating: N409 ( 3, 6) [001354] J------N--- * NE void REG NA V18 in reg x13 is becoming dead [001352] Live regs: 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} IN004c: cmp w13, w1 Generating: N001 ( 1, 1) [004309] ----------- t4309 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4309 int Generating: N002 ( 2, 2) [004310] ----------- t4310 = * COPY int REG x1 IN004d: mov w1, w10 V16 in reg x10 is becoming dead [004309] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004310] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Generating: N411 ( 5, 8) [001355] ----------- * JTRUE void REG NA $VN.Void IN004e: bne (LARGEJMP)L_M30548_BB47 Variable Live Range History Dump for BB15 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG12,ins#4,ofs#20), (G_M30548_IG13,ins#7,ofs#36)]; x1 [(G_M30548_IG13,ins#7,ofs#36), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG12,ins#4,ofs#20), (G_M30548_IG13,ins#5,ofs#28)] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB16 [137..142) -> BB47 (always), preds={BB15} succs={BB47} flags=0x00000000.21000020: i bwd LIR BB16 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB16 V16(x1) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB16: Scope info: begin block BB16, IL range [137..142) Added IP mapping: 0x0137 STACK_EMPTY (G_M30548_IG13,ins#8,ofs#44) label Generating: N415 (???,???) [003804] ----------- IL_OFFSET void INLRT @ 0x137[E-] REG NA Generating: N417 ( 1, 1) [001356] ----------- t1356 = LCL_VAR int V13 loc9 u:2 x8 (last use) REG x8 $289 Generating: N419 ( 1, 2) [001357] -c--------- t1357 = CNS_INT int 3 REG NA $c3 /--* t1356 int +--* t1357 int Generating: N421 ( 3, 4) [001358] ----------- t1358 = * ADD int REG x8 $376 V13 in reg x8 is becoming dead [001356] Live regs: 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF802E2 {x1 x5 x6 x7 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V16 V17 V22 V179 V180} IN004f: add w8, w8, #3 /--* t1358 int Generating: N423 ( 3, 4) [001360] DA--------- * STORE_LCL_VAR int V13 loc9 d:5 x8 REG x8 V13 in reg x8 is becoming live [001360] Live regs: 1FF802E2 {x1 x5 x6 x7 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Extending debug range... IN0050: b L_M30548_BB47 Variable Live Range History Dump for BB16 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG13,ins#7,ofs#36), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB17 [0CF..0D8) -> BB47 (always), preds={BB255} succs={BB47} flags=0x00000000.21010020: i label bwd LIR BB17 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB17 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB17: G_M30548_IG13: ; offs=000144H, funclet=00, bbWeight=8 , byref Mapped BB17 to G_M30548_IG14 Label: IG14, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB17, IL range [0CF..0D8) Added IP mapping: 0x00CF STACK_EMPTY (G_M30548_IG14,ins#0,ofs#0) label Generating: N3699 (???,???) [003805] ----------- IL_OFFSET void INLRT @ 0x0CF[E-] REG NA Generating: N3701 ( 1, 1) [001430] ----------- t1430 = LCL_VAR int V04 loc0 u:2 x27 (last use) REG x27 $28a Generating: N3703 ( 1, 2) [001431] -c--------- t1431 = CNS_INT int 1 REG NA $c1 /--* t1430 int +--* t1431 int Generating: N3705 ( 3, 4) [001432] ----------- t1432 = * ADD int REG x27 $68f V04 in reg x27 is becoming dead [001430] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 17F807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} IN0051: add w27, w27, #1 /--* t1432 int Generating: N3707 ( 3, 4) [001434] DA--------- * STORE_LCL_VAR int V04 loc0 d:3 x27 REG x27 V04 in reg x27 is becoming live [001434] Live regs: 17F807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x28} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Extending debug range... Generating: N001 ( 1, 1) [004367] ----------- t4367 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4367 int Generating: N002 ( 2, 2) [004368] ----------- t4368 = * COPY int REG x1 IN0052: mov w1, w10 V16 in reg x10 is becoming dead [004367] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004368] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} IN0053: b L_M30548_BB47 Variable Live Range History Dump for BB17 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG13,ins#7,ofs#36), (G_M30548_IG13,ins#10,ofs#52)]; x10 [(G_M30548_IG13,ins#10,ofs#52), (G_M30548_IG14,ins#2,ofs#8)]; x1 [(G_M30548_IG14,ins#2,ofs#8), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB18 [0D8..0E0) -> BB20 (cond), preds={BB256} succs={BB19,BB20} flags=0x00000000.21010020: i label bwd LIR BB18 IN (18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB18 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008A400760040050187 {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB18: G_M30548_IG14: ; offs=000178H, funclet=00, bbWeight=8 , byref Mapped BB18 to G_M30548_IG15 Label: IG15, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB18, IL range [0D8..0E0) Added IP mapping: 0x00D8 STACK_EMPTY (G_M30548_IG15,ins#0,ofs#0) label Generating: N3799 (???,???) [003806] ----------- IL_OFFSET void INLRT @ 0x0D8[E-] REG NA Generating: N3801 ( 1, 1) [001373] ----------z t1373 = LCL_VAR int V06 loc2 u:2 x3 REG x3 $284 Generating: N3803 ( 1, 4) [001374] ----------- t1374 = CNS_INT int 0x7FFFFFFF REG x4 $c9 IN0054: movn w4, #0x8000 LSL #16 /--* t1373 int +--* t1374 int Generating: N3805 ( 3, 6) [001375] N------N-U- * NE void REG NA $68e IN0055: ldr w3, [fp, #0x84] // [V06 loc2] New debug range: not adjacent V06 in reg x3 is becoming live [001373] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E8 {x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} IN0056: cmp w3, w4 Generating: N3807 ( 5, 8) [001376] ----------- * JTRUE void REG NA $VN.Void IN0057: bne (LARGEJMP)L_M30548_BB20 Variable Live Range History Dump for BB18 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG07,ins#4,ofs#16), (G_M30548_IG15,ins#2,ofs#8)]; x3 [(G_M30548_IG15,ins#2,ofs#8), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG07,ins#5,ofs#20), (G_M30548_IG14,ins#3,ofs#12)] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG14,ins#2,ofs#8), (G_M30548_IG14,ins#3,ofs#12)]; x10 [(G_M30548_IG14,ins#3,ofs#12), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB19 [0E0..0E2), preds={BB18} succs={BB20} flags=0x00000000.21000020: i bwd LIR BB19 IN (17)={V16 V00 V179 V22 V04 V05 V13 V10 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB19 V16(x10) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008A400760040050187 {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008A400740040050187 {V00 V01 V02 V03 V04 V05 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} V06 in reg x3 is becoming dead [------] Live regs: (unchanged) 0000 {} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB19: Scope info: begin block BB19, IL range [0E0..0E2) Added IP mapping: 0x00E0 STACK_EMPTY (G_M30548_IG15,ins#4,ofs#20) label Generating: N3811 (???,???) [003807] ----------- IL_OFFSET void INLRT @ 0x0E0[E-] REG NA Generating: N3813 ( 1, 1) [001385] ----------- t1385 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1385 int Generating: N3815 ( 1, 3) [001387] DA--------- * STORE_LCL_VAR int V06 loc2 d:5 x3 REG x3 IN0058: mov w3, w27 V06 in reg x3 is becoming live [001387] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E8 {x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Extending debug range... Variable Live Range History Dump for BB19 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: x3 [(G_M30548_IG15,ins#2,ofs#8), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG14,ins#3,ofs#12), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB20 [0E2..0ED) -> BB47 (always), preds={BB18,BB19} succs={BB47} flags=0x00000000.21010020: i label bwd LIR BB20 IN (18)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB20 V16(x10) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V06(x3) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008A400760040050187 {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E8 {x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB20: G_M30548_IG15: ; offs=000184H, funclet=00, bbWeight=8 , byref Mapped BB20 to G_M30548_IG16 Label: IG16, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB20, IL range [0E2..0ED) Added IP mapping: 0x00E2 STACK_EMPTY (G_M30548_IG16,ins#0,ofs#0) label Generating: N3819 (???,???) [003808] ----------- IL_OFFSET void INLRT @ 0x0E2[E-] REG NA Generating: N3821 ( 1, 1) [001377] ----------- t1377 = LCL_VAR int V04 loc0 u:2 x27 (last use) REG x27 $28a Generating: N3823 ( 1, 2) [001378] -c--------- t1378 = CNS_INT int 1 REG NA $c1 /--* t1377 int +--* t1378 int Generating: N3825 ( 3, 4) [001379] ----------- t1379 = * ADD int REG x27 $68f V04 in reg x27 is becoming dead [001377] Live regs: 1FF807E8 {x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 17F807E8 {x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} IN0059: add w27, w27, #1 /--* t1379 int Generating: N3827 ( 3, 4) [001381] DA--------- * STORE_LCL_VAR int V04 loc0 d:4 x27 REG x27 V04 in reg x27 is becoming live [001381] Live regs: 17F807E8 {x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x28} => 1FF807E8 {x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Extending debug range... Added IP mapping: 0x00E6 STACK_EMPTY (G_M30548_IG16,ins#1,ofs#4) Generating: N3829 (???,???) [003809] ----------- IL_OFFSET void INLRT @ 0x0E6[E-] REG NA Generating: N3831 ( 1, 1) [001382] ----------- t1382 = LCL_VAR int V04 loc0 u:4 x27 REG x27 $68f /--* t1382 int Generating: N3833 ( 1, 3) [001384] DA--------- * STORE_LCL_VAR int V07 loc3 d:4 x2 REG x2 IN005a: mov w2, w27 V07 in reg x2 is becoming live [001384] Live regs: 1FF807E8 {x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807EC {x2 x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} New debug range: not adjacent Generating: N001 ( 1, 1) [004369] ----------Z t4369 = LCL_VAR int V06 loc2 x3 REG x3 IN005b: str w3, [fp, #0x84] // [V06 loc2] V06 in reg x3 is becoming dead [004369] Live regs: 1FF807EC {x2 x3 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E4 {x2 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent Generating: N001 ( 1, 1) [004370] ----------Z t4370 = LCL_VAR int V07 loc3 x2 REG x2 IN005c: str w2, [fp, #0x80] // [V07 loc3] V07 in reg x2 is becoming dead [004370] Live regs: 1FF807E4 {x2 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent Generating: N001 ( 1, 1) [004371] ----------- t4371 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4371 int Generating: N002 ( 2, 2) [004372] ----------- t4372 = * COPY int REG x1 IN005d: mov w1, w10 V16 in reg x10 is becoming dead [004371] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004372] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} IN005e: b L_M30548_BB47 Variable Live Range History Dump for BB20 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: x3 [(G_M30548_IG15,ins#2,ofs#8), (G_M30548_IG16,ins#3,ofs#12)]; fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: x2 [(G_M30548_IG16,ins#2,ofs#8), (G_M30548_IG16,ins#4,ofs#16)]; fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG14,ins#3,ofs#12), (G_M30548_IG16,ins#5,ofs#20)]; x1 [(G_M30548_IG16,ins#5,ofs#20), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB21 [0ED..0F4) -> BB47 (cond), preds={BB256} succs={BB22,BB47} flags=0x00000000.21010020: i label bwd LIR BB21 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB21 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB21: G_M30548_IG16: ; offs=00019CH, funclet=00, bbWeight=8 , byref Mapped BB21 to G_M30548_IG17 Label: IG17, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB21, IL range [0ED..0F4) Added IP mapping: 0x00ED STACK_EMPTY (G_M30548_IG17,ins#0,ofs#0) label Generating: N3837 (???,???) [003810] ----------- IL_OFFSET void INLRT @ 0x0ED[E-] REG NA Generating: N3839 ( 1, 1) [001388] ----------- t1388 = LCL_VAR int V05 loc1 u:2 x28 REG x28 $286 Generating: N3841 ( 1, 2) [001389] -c--------- t1389 = CNS_INT int 0 REG NA $c0 /--* t1388 int +--* t1389 int Generating: N3843 ( 3, 4) [001390] J------N--- * GE void REG NA $690 IN005f: cmp w28, #0 Generating: N001 ( 1, 1) [004311] ----------- t4311 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4311 int Generating: N002 ( 2, 2) [004312] ----------- t4312 = * COPY int REG x1 IN0060: mov w1, w10 V16 in reg x10 is becoming dead [004311] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004312] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Generating: N3845 ( 5, 6) [001391] ----------- * JTRUE void REG NA $VN.Void IN0061: bge (LARGEJMP)L_M30548_BB47 Variable Live Range History Dump for BB21 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG16,ins#5,ofs#20), (G_M30548_IG16,ins#6,ofs#24)]; x10 [(G_M30548_IG16,ins#6,ofs#24), (G_M30548_IG17,ins#2,ofs#8)]; x1 [(G_M30548_IG17,ins#2,ofs#8), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB22 [0F4..0FB) -> BB47 (always), preds={BB21} succs={BB47} flags=0x00000000.21000020: i bwd LIR BB22 IN (18)={V16 V00 V179 V22 V04 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB22 V16(x1) V00(x19) V179(x25) V22(x9) V04(x27) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008AC00760040040187 {V00 V01 V02 V03 V04 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} V05 in reg x28 is becoming dead [------] Live regs: (unchanged) 0000 {} Live regs: 0000 {} => FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB22: Scope info: begin block BB22, IL range [0F4..0FB) Added IP mapping: 0x00F4 STACK_EMPTY (G_M30548_IG17,ins#3,ofs#16) label Generating: N3849 (???,???) [003811] ----------- IL_OFFSET void INLRT @ 0x0F4[E-] REG NA Generating: N3851 ( 1, 1) [001392] ----------- t1392 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1392 int Generating: N3853 ( 1, 3) [001394] DA--------- * STORE_LCL_VAR int V05 loc1 d:5 x28 REG x28 IN0062: mov w28, w27 V05 in reg x28 is becoming live [001394] Live regs: FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Extending debug range... IN0063: b L_M30548_BB47 Variable Live Range History Dump for BB22 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG17,ins#2,ofs#8), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB23 [0FB..102) -> BB47 (cond), preds={BB256} succs={BB24,BB47} flags=0x00000000.21010020: i label bwd LIR BB23 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB23 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB23: G_M30548_IG17: ; offs=0001B4H, funclet=00, bbWeight=8 , byref Mapped BB23 to G_M30548_IG18 Label: IG18, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB23, IL range [0FB..102) Added IP mapping: 0x00FB STACK_EMPTY (G_M30548_IG18,ins#0,ofs#0) label Generating: N3857 (???,???) [003812] ----------- IL_OFFSET void INLRT @ 0x0FB[E-] REG NA Generating: N3859 ( 1, 1) [001395] ----------- t1395 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a Generating: N3861 ( 1, 2) [001396] -c--------- t1396 = CNS_INT int 0 REG NA $c0 /--* t1395 int +--* t1396 int Generating: N3863 ( 6, 4) [001397] -c-----N--- t1397 = * LE int REG NA $691 Generating: N3865 ( 1, 1) [001399] ----------- t1399 = LCL_VAR int V05 loc1 u:2 x28 REG x28 $286 Generating: N3867 ( 1, 2) [001400] -c--------- t1400 = CNS_INT int 0 REG NA $c0 /--* t1399 int +--* t1400 int Generating: N3869 ( 6, 4) [001401] -c-----N--- t1401 = * GE int REG NA $690 /--* t1397 int +--* t1401 int Generating: N3871 ( 13, 9) [003726] Jc-----N--- * AND void REG NA Generating: N001 ( 1, 1) [004313] ----------- t4313 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4313 int Generating: N002 ( 2, 2) [004314] ----------- t4314 = * COPY int REG x1 IN0064: mov w1, w10 V16 in reg x10 is becoming dead [004313] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004314] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Generating: N3873 ( 15, 11) [001398] ----------- * JTRUE void REG NA $VN.Void Generating compare chain: IN0065: cmp w27, #0 IN0066: ccmp w28, #0, nc, le IN0067: bge (LARGEJMP)L_M30548_BB47 Variable Live Range History Dump for BB23 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG17,ins#2,ofs#8), (G_M30548_IG17,ins#5,ofs#24)]; x10 [(G_M30548_IG17,ins#5,ofs#24), (G_M30548_IG18,ins#1,ofs#4)]; x1 [(G_M30548_IG18,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB24 [102..10E) -> BB29 (cond), preds={BB23} succs={BB26,BB29} flags=0x00000000.21000020: i bwd LIR BB24 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB24 V16(x1) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB24: Scope info: begin block BB24, IL range [102..10E) Added IP mapping: 0x0102 STACK_EMPTY (G_M30548_IG18,ins#4,ofs#20) label Generating: N3877 (???,???) [003813] ----------- IL_OFFSET void INLRT @ 0x102[E-] REG NA Added IP mapping: 0x0109 STACK_EMPTY (G_M30548_IG18,ins#4,ofs#20) Generating: N3879 (???,???) [003814] ----------- IL_OFFSET void INLRT @ 0x109[E-] REG NA Generating: N3881 ( 1, 1) [001403] ----------- t1403 = LCL_VAR int V10 loc6 u:2 x6 REG x6 $287 Generating: N3883 ( 1, 2) [001404] -c--------- t1404 = CNS_INT int 0 REG NA $c0 /--* t1403 int +--* t1404 int Generating: N3885 ( 3, 4) [001405] J------N--- * LT void REG NA $692 IN0068: cmp w6, #0 Generating: N3887 ( 5, 6) [001406] ----------- * JTRUE void REG NA $VN.Void IN0069: blt (LARGEJMP)L_M30548_BB29 Variable Live Range History Dump for BB24 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG18,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB26 [10E..113) -> BB28 (cond), preds={BB24} succs={BB27,BB28} flags=0x00000000.21000020: i bwd LIR BB26 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB26 V16(x1) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB26: Scope info: begin block BB26, IL range [10E..113) Added IP mapping: 0x010E STACK_EMPTY (G_M30548_IG18,ins#6,ofs#32) label Generating: N3891 (???,???) [003815] ----------- IL_OFFSET void INLRT @ 0x10E[E-] REG NA Generating: N3893 ( 1, 1) [001413] ----------- t1413 = LCL_VAR int V10 loc6 u:2 x6 REG x6 $287 Generating: N3895 ( 1, 1) [001414] ----------- t1414 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1413 int +--* t1414 int Generating: N3897 ( 3, 3) [001415] N------N-U- * NE void REG NA $693 IN006a: cmp w6, w27 Generating: N3899 ( 5, 5) [001416] ----------- * JTRUE void REG NA $VN.Void IN006b: bne (LARGEJMP)L_M30548_BB28 Variable Live Range History Dump for BB26 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG18,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB27 [113..11E) -> BB47 (always), preds={BB26} succs={BB47} flags=0x00000000.21000020: i bwd LIR BB27 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB27 V16(x1) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB27: Scope info: begin block BB27, IL range [113..11E) Added IP mapping: 0x0113 STACK_EMPTY (G_M30548_IG18,ins#8,ofs#44) label Generating: N3903 (???,???) [003816] ----------- IL_OFFSET void INLRT @ 0x113[E-] REG NA Generating: N3905 ( 1, 1) [001420] ----------- t1420 = LCL_VAR int V11 loc7 u:3 x22 (last use) REG x22 $288 Generating: N3907 ( 1, 2) [001421] -c--------- t1421 = CNS_INT int 1 REG NA $c1 /--* t1420 int +--* t1421 int Generating: N3909 ( 3, 4) [001422] ----------- t1422 = * ADD int REG x22 $694 V11 in reg x22 is becoming dead [001420] Live regs: 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FB803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V12 V13 V15 V16 V17 V22 V179 V180} IN006c: add w22, w22, #1 /--* t1422 int Generating: N3911 ( 3, 4) [001424] DA--------- * STORE_LCL_VAR int V11 loc7 d:5 x22 REG x22 V11 in reg x22 is becoming live [001424] Live regs: 1FB803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Extending debug range... IN006d: b L_M30548_BB47 Variable Live Range History Dump for BB27 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), ...] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), ...] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG18,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB28 [11E..121), preds={BB26} succs={BB29} flags=0x00000000.21010020: i label bwd LIR BB28 IN (16)={V16 V00 V179 V22 V04 V05 V13 V06 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(17)={V16 V00 V179 V22 V04 V05 V13 V06 V12 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB28 V16(x1) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008AC00620000050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V13 V15 V16 V17 V22 V179 V180} V10 in reg x6 is becoming dead [------] Live regs: (unchanged) 0000 {} V12 in reg x7 is becoming dead [------] Live regs: (unchanged) 0000 {} V11 in reg x22 is becoming dead [------] Live regs: (unchanged) 0000 {} Live regs: 0000 {} => 1FB80322 {x1 x5 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB28: G_M30548_IG18: ; offs=0001CCH, funclet=00, bbWeight=8 , byref Mapped BB28 to G_M30548_IG19 Label: IG19, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB28, IL range [11E..121) Added IP mapping: 0x011E STACK_EMPTY (G_M30548_IG19,ins#0,ofs#0) label Generating: N3915 (???,???) [003817] ----------- IL_OFFSET void INLRT @ 0x11E[E-] REG NA Generating: N3917 ( 1, 2) [002612] ----------- t2612 = CNS_INT int 1 REG x7 $c1 IN006e: mov w7, #1 /--* t2612 int Generating: N3919 ( 1, 3) [001419] DA--------- * STORE_LCL_VAR int V12 loc8 d:6 NA REG NA IN006f: str w7, [fp, #0x74] // [V12 loc8] Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22 V179 V180} New debug range: new var or location Generating: N001 ( 1, 1) [004373] ----------z t4373 = LCL_VAR bool V12 loc8 x7 REG x7 IN0070: ldr w7, [fp, #0x74] // [V12 loc8] New debug range: new var or location V12 in reg x7 is becoming live [004373] Live regs: 1FB80322 {x1 x5 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} => 1FB803A2 {x1 x5 x7 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} Variable Live Range History Dump for BB28 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG07,ins#7,ofs#28), (G_M30548_IG18,ins#10,ofs#52)] V11 loc7: x22 [(G_M30548_IG02,ins#6,ofs#24), (G_M30548_IG18,ins#10,ofs#52)] V12 loc8: x7 [(G_M30548_IG07,ins#8,ofs#32), (G_M30548_IG18,ins#10,ofs#52)]; x7 [(G_M30548_IG19,ins#2,ofs#8), (G_M30548_IG19,ins#3,ofs#12)]; x7 [(G_M30548_IG19,ins#3,ofs#12), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG18,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB29 [121..12C) -> BB47 (always), preds={BB24,BB28} succs={BB47} flags=0x00000000.21010020: i label bwd LIR BB29 IN (17)={V16 V00 V179 V22 V04 V05 V13 V06 V12 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB29 V16(x1) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V12(x7) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00660000050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FB803A2 {x1 x5 x7 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB29: G_M30548_IG19: ; offs=000200H, funclet=00, bbWeight=8 , byref Mapped BB29 to G_M30548_IG20 Label: IG20, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB29, IL range [121..12C) Added IP mapping: 0x0121 STACK_EMPTY (G_M30548_IG20,ins#0,ofs#0) label Generating: N3923 (???,???) [003818] ----------- IL_OFFSET void INLRT @ 0x121[E-] REG NA Generating: N3925 ( 1, 1) [001407] ----------- t1407 = LCL_VAR int V04 loc0 u:2 x27 REG x27 $28a /--* t1407 int Generating: N3927 ( 1, 3) [001409] DA--------- * STORE_LCL_VAR int V10 loc6 d:3 x6 REG x6 IN0071: mov w6, w27 V10 in reg x6 is becoming live [001409] Live regs: 1FB803A2 {x1 x5 x7 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} => 1FB803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V12 V13 V15 V16 V17 V22 V179 V180} New debug range: new var or location Added IP mapping: 0x0124 STACK_EMPTY (G_M30548_IG20,ins#1,ofs#4) Generating: N3929 (???,???) [003819] ----------- IL_OFFSET void INLRT @ 0x124[E-] REG NA Generating: N3931 ( 1, 2) [001410] ----------- t1410 = CNS_INT int 1 REG x22 $c1 IN0072: mov w22, #1 /--* t1410 int Generating: N3933 ( 1, 3) [001412] DA--------- * STORE_LCL_VAR int V11 loc7 d:4 x22 REG x22 V11 in reg x22 is becoming live [001412] Live regs: 1FB803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} New debug range: new var or location IN0073: b L_M30548_BB47 Variable Live Range History Dump for BB29 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG20,ins#1,ofs#4), ...] V11 loc7: x22 [(G_M30548_IG20,ins#2,ofs#8), ...] V12 loc8: x7 [(G_M30548_IG19,ins#3,ofs#12), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG18,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB30 [12C..137) -> BB47 (always), preds={BB255} succs={BB47} flags=0x00000000.21010020: i label bwd LIR BB30 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB30 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB30: G_M30548_IG20: ; offs=00020CH, funclet=00, bbWeight=8 , byref Mapped BB30 to G_M30548_IG21 Label: IG21, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB30, IL range [12C..137) Added IP mapping: 0x012C STACK_EMPTY (G_M30548_IG21,ins#0,ofs#0) label Generating: N3711 (???,???) [003820] ----------- IL_OFFSET void INLRT @ 0x12C[E-] REG NA Generating: N3713 ( 1, 1) [001425] ----------- t1425 = LCL_VAR int V13 loc9 u:2 x8 (last use) REG x8 $289 Generating: N3715 ( 1, 2) [001426] -c--------- t1426 = CNS_INT int 2 REG NA $c2 /--* t1425 int +--* t1426 int Generating: N3717 ( 3, 4) [001427] ----------- t1427 = * ADD int REG x8 $695 V13 in reg x8 is becoming dead [001425] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF806E0 {x5 x6 x7 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V16 V17 V22 V179 V180} IN0074: add w8, w8, #2 /--* t1427 int Generating: N3719 ( 3, 4) [001429] DA--------- * STORE_LCL_VAR int V13 loc9 d:6 x8 REG x8 V13 in reg x8 is becoming live [001429] Live regs: 1FF806E0 {x5 x6 x7 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Extending debug range... Generating: N001 ( 1, 1) [004374] ----------- t4374 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4374 int Generating: N002 ( 2, 2) [004375] ----------- t4375 = * COPY int REG x1 IN0075: mov w1, w10 V16 in reg x10 is becoming dead [004374] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004375] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} IN0076: b L_M30548_BB47 Variable Live Range History Dump for BB30 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG20,ins#1,ofs#4), ...] V11 loc7: x22 [(G_M30548_IG20,ins#2,ofs#8), ...] V12 loc8: x7 [(G_M30548_IG19,ins#3,ofs#12), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG18,ins#1,ofs#4), (G_M30548_IG20,ins#3,ofs#12)]; x10 [(G_M30548_IG20,ins#3,ofs#12), (G_M30548_IG21,ins#2,ofs#8)]; x1 [(G_M30548_IG21,ins#2,ofs#8), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB31 [142..150) -> BB47 (cond), preds={BB32,BB255(2)} succs={BB32,BB47} flags=0x00000008.21016020: i Loop Loop0 label bwd bwd-target LIR BB31 IN (20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(21)={V16 V00 V179 V18 V171 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB31 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V18(x13) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} -> 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} V18 in reg x13 is becoming live [------] Live regs: 0000 {} => 2000 {x13} New debug range: new var or location Live regs: 2000 {x13} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB31: G_M30548_IG21: ; offs=000218H, funclet=00, bbWeight=8 , byref Mapped BB31 to G_M30548_IG22 Label: IG22, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB31, IL range [142..150) Added IP mapping: 0x0142 STACK_EMPTY (G_M30548_IG22,ins#0,ofs#0) label Generating: N3723 (???,???) [003821] ----------- IL_OFFSET void INLRT @ 0x142[E-] REG NA Generating: N3725 ( 1, 1) [001435] ----------- t1435 = LCL_VAR int V16 loc12 u:21 x10 REG x10 $2b1 Generating: N3727 ( 1, 1) [003693] ----------- t3693 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1435 int +--* t3693 int Generating: N3729 ( 6, 3) [001440] -c-----N--- t1440 = * GE int REG NA $8b7 Generating: N3731 ( 1, 1) [001442] ----------- t1442 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 Generating: N3733 ( 1, 1) [001443] ----------- t1443 = LCL_VAR int V16 loc12 u:21 x10 REG x10 $2b1 /--* t1443 int Generating: N3735 ( 2, 3) [001444] -c--------- t1444 = * CAST long <- int REG NA $3de Generating: N3737 ( 1, 2) [001446] -c--------- t1446 = CNS_INT long 1 REG NA $204 /--* t1444 long +--* t1446 long Generating: N3739 ( 4, 6) [001447] -c--------- t1447 = * BFIZ long REG NA /--* t1442 long +--* t1447 long Generating: N3741 ( 6, 8) [001448] -c--------- t1448 = * LEA(b+(i*1)+0) long REG NA /--* t1448 long Generating: N3743 ( 9, 10) [001449] ---XG------ t1449 = * IND ushort REG x0 IN0077: ldrh w0, [x9, w10, SXTW #2] /--* t1449 ushort Generating: N3745 ( 9, 10) [003625] DA-XG------ * STORE_LCL_VAR int V171 cse0 d:1 x0 REG x0 V171 in reg x0 is becoming live [003625] Live regs: 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF827E1 {x0 x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} Generating: N3747 ( 1, 1) [003626] ----------- t3626 = LCL_VAR int V171 cse0 u:1 x0 REG x0 Generating: N3749 ( 1, 2) [001450] -c--------- t1450 = CNS_INT int 0 REG NA $c0 /--* t3626 int +--* t1450 int Generating: N3751 ( 15, 14) [001451] -c-XG--N--- t1451 = * EQ int REG NA /--* t1440 int +--* t1451 int Generating: N3753 ( 22, 18) [003728] Jc-XG--N--- * AND void REG NA Generating: N001 ( 1, 1) [004315] ----------- t4315 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4315 int Generating: N002 ( 2, 2) [004316] ----------- t4316 = * COPY int REG x1 IN0078: mov w1, w10 V16 in reg x10 is becoming dead [004315] Live regs: 1FF827E1 {x0 x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF823E1 {x0 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004316] Live regs: 1FF823E1 {x0 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF823E3 {x0 x1 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Generating: N3755 ( 24, 20) [001441] ---XG------ * JTRUE void REG NA $VN.Void IN0079: mov w10, w1 Generating compare chain: IN007a: cmp w10, w25 IN007b: ccmp w0, #0, 0, ge IN007c: beq (LARGEJMP)L_M30548_BB47 Variable Live Range History Dump for BB31 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG20,ins#1,ofs#4), ...] V11 loc7: x22 [(G_M30548_IG20,ins#2,ofs#8), ...] V12 loc8: x7 [(G_M30548_IG19,ins#3,ofs#12), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG21,ins#2,ofs#8), (G_M30548_IG21,ins#3,ofs#12)]; x10 [(G_M30548_IG21,ins#3,ofs#12), (G_M30548_IG22,ins#2,ofs#8)]; x1 [(G_M30548_IG22,ins#2,ofs#8), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG21,ins#3,ofs#12), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB32 [150..170) -> BB31 (cond), preds={BB31} succs={BB34,BB31} flags=0x00000000.21000020: i bwd LIR BB32 IN (21)={V16 V00 V179 V18 V171 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(20)={V16 V00 V179 V18 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB32 V16(x1) V00(x19) V179(x25) V18(x13) V171(x0) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC007600400501E7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} Live regs: 0000 {} => 1FF823E3 {x0 x1 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB32: Scope info: begin block BB32, IL range [150..170) Added IP mapping: 0x0150 STACK_EMPTY (G_M30548_IG22,ins#6,ofs#28) label Generating: N3759 (???,???) [003822] ----------- IL_OFFSET void INLRT @ 0x150[E-] REG NA Added IP mapping: 0x015E STACK_EMPTY (G_M30548_IG22,ins#6,ofs#28) Generating: N3761 (???,???) [003823] ----------- IL_OFFSET void INLRT @ 0x15E[E-] REG NA Generating: N3763 ( 1, 1) [001454] ----------- t1454 = LCL_VAR int V16 loc12 u:21 x1 (last use) REG x1 $2b1 /--* t1454 int Generating: N3765 ( 1, 3) [001461] DA--------- * STORE_LCL_VAR int V74 tmp34 d:1 x1 REG x1 V16 in reg x1 is becoming dead [001454] Live regs: 1FF823E3 {x0 x1 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF823E1 {x0 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V18 V22 V171 V179 V180} V74 in reg x1 is becoming live [001461] Live regs: 1FF823E1 {x0 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF823E3 {x0 x1 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V18 V22 V171 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V18 V22 V74 V171 V179 V180} genIPmappingAdd: ignoring duplicate IL offset 0x15e Generating: N3767 (???,???) [003824] ----------- IL_OFFSET void INLRT @ 0x15E[E-] REG NA Generating: N3769 ( 1, 1) [001455] ----------- t1455 = LCL_VAR int V74 tmp34 u:1 x1 (last use) REG x1 $2b1 Generating: N3771 ( 1, 2) [001456] -c--------- t1456 = CNS_INT int 1 REG NA $c1 /--* t1455 int +--* t1456 int Generating: N3773 ( 3, 4) [001457] ----------- t1457 = * ADD int REG x1 $8bc V74 in reg x1 is becoming dead [001455] Live regs: 1FF823E3 {x0 x1 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF823E1 {x0 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V18 V22 V74 V171 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V18 V22 V171 V179 V180} IN007d: add w1, w1, #1 /--* t1457 int Generating: N3775 ( 3, 4) [001459] DA--------- * STORE_LCL_VAR int V16 loc12 d:22 NA REG NA IN007e: str w1, [fp, #0x6C] // [V16 loc12] Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V17 V18 V22 V171 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} New debug range: new var or location Generating: N3777 ( 1, 1) [003628] ----------- t3628 = LCL_VAR int V171 cse0 u:1 x0 (last use) REG x0 Generating: N3779 ( 1, 1) [001469] ----------- t1469 = LCL_VAR int V18 loc14 u:5 x13 REG x13 /--* t3628 int +--* t1469 int Generating: N3781 ( 3, 3) [001470] N---G--N-U- * NE void REG NA V171 in reg x0 is becoming dead [003628] Live regs: 1FF823E1 {x0 x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF823E0 {x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V171 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} IN007f: cmp w0, w13 Generating: N001 ( 1, 1) [004317] ----------z t4317 = LCL_VAR int V16 loc12 x10 REG x10 IN0080: ldr w10, [fp, #0x6C] // [V16 loc12] New debug range: not adjacent V16 in reg x10 is becoming live [004317] Live regs: 1FF823E0 {x5 x6 x7 x8 x9 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF827E0 {x5 x6 x7 x8 x9 x10 x13 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Generating: N3783 ( 5, 5) [001471] ----G------ * JTRUE void REG NA $876 IN0081: bne (LARGEJMP)L_M30548_BB31 Variable Live Range History Dump for BB32 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG20,ins#1,ofs#4), ...] V11 loc7: x22 [(G_M30548_IG20,ins#2,ofs#8), ...] V12 loc8: x7 [(G_M30548_IG19,ins#3,ofs#12), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x1 [(G_M30548_IG22,ins#2,ofs#8), (G_M30548_IG22,ins#6,ofs#28)]; x1 [(G_M30548_IG22,ins#8,ofs#36), (G_M30548_IG22,ins#10,ofs#44)]; x10 [(G_M30548_IG22,ins#10,ofs#44), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG21,ins#3,ofs#12), ...] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB34 [170..175) -> BB47 (always), preds={BB32} succs={BB47} flags=0x00000000.21000020: i bwd LIR BB34 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB34 V16(x10) V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Change life 00000000000000000000000000400008AC007600400501A7 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V18 V22 V179 V180} -> 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} V18 in reg x13 is becoming dead [------] Live regs: (unchanged) 0000 {} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB34: Adding label due to BB weight difference: BBJ_COND BB32 with weight 6400 different from BB34 with weight 800 G_M30548_IG22: ; offs=000224H, funclet=00, bbWeight=64 , byref Mapped BB34 to G_M30548_IG23 Label: IG23, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB34, IL range [170..175) Generating: N001 ( 1, 1) [004376] ----------- t4376 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4376 int Generating: N002 ( 2, 2) [004377] ----------- t4377 = * COPY int REG x1 IN0082: mov w1, w10 V16 in reg x10 is becoming dead [004376] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004377] Live regs: 1FF803E0 {x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} IN0083: b L_M30548_BB47 Variable Live Range History Dump for BB34 V00 arg0: x19 [(G_M30548_IG02,ins#0,ofs#0), ...] V01 arg1: x21 [(G_M30548_IG02,ins#0,ofs#0), ...] V02 arg2: fp[136] (1 slot) [(G_M30548_IG02,ins#0,ofs#0), ...] V03 arg3: x20 [(G_M30548_IG02,ins#0,ofs#0), ...] V04 loc0: x27 [(G_M30548_IG07,ins#1,ofs#4), ...] V05 loc1: x28 [(G_M30548_IG07,ins#2,ofs#8), ...] V06 loc2: fp[132] (1 slot) [(G_M30548_IG16,ins#3,ofs#12), ...] V07 loc3: fp[128] (1 slot) [(G_M30548_IG16,ins#4,ofs#16), ...] V09 loc5: x5 [(G_M30548_IG07,ins#6,ofs#24), ...] V10 loc6: x6 [(G_M30548_IG20,ins#1,ofs#4), ...] V11 loc7: x22 [(G_M30548_IG20,ins#2,ofs#8), ...] V12 loc8: x7 [(G_M30548_IG19,ins#3,ofs#12), ...] V13 loc9: x8 [(G_M30548_IG07,ins#9,ofs#36), ...] V15 loc11: x26 [(G_M30548_IG06,ins#5,ofs#20), ...] V16 loc12: x10 [(G_M30548_IG22,ins#10,ofs#44), (G_M30548_IG23,ins#1,ofs#4)]; x1 [(G_M30548_IG23,ins#1,ofs#4), ...] V17 loc13: x23 [(G_M30548_IG02,ins#11,ofs#48), ...] V18 loc14: x13 [(G_M30548_IG21,ins#3,ofs#12), (G_M30548_IG22,ins#11,ofs#52)] V22 loc18: x9 [(G_M30548_IG07,ins#12,ofs#48), ...] =============== Generating BB35 [175..183) -> BB47 (cond), preds={BB13} succs={BB36,BB47} flags=0x00000000.21010020: i label bwd LIR BB35 IN (19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap OUT(19)={V16 V00 V179 V22 V04 V05 V13 V10 V06 V12 V11 V09 V03 V01 V07 V15 V17 V180 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB35 V16(x1->x10)New debug range: not adjacent V00(x19) V179(x25) V22(x9) V04(x27) V05(x28) V13(x8) V10(x6) V12(x7) V11(x22) V09(x5) V03(x20) V01(x21) V15(x26) V17(x23) V180(x24) Liveness not changing: 00000000000000000000000000400008AC00760040050187 {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} Live regs: 0000 {} => 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} GC regs: 0000 {} => 100000 {x20} Byref regs: 0000 {} => 1280000 {x19 x21 x24} L_M30548_BB35: G_M30548_IG23: ; offs=000258H, funclet=00, bbWeight=8 , byref Mapped BB35 to G_M30548_IG24 Label: IG24, GCvars=000000000000000000000000000000000000000000000000 {}, gcrefRegs=100000 {x20}, byrefRegs=1280000 {x19 x21 x24} Scope info: begin block BB35, IL range [175..183) Added IP mapping: 0x0175 STACK_EMPTY (G_M30548_IG24,ins#0,ofs#0) label Generating: N427 (???,???) [003825] ----------- IL_OFFSET void INLRT @ 0x175[E-] REG NA Generating: N429 ( 1, 1) [001234] ----------- t1234 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 Generating: N431 ( 1, 1) [003694] ----------- t3694 = LCL_VAR int V179 cse8 u:1 x25 REG x25 $342 /--* t1234 int +--* t3694 int Generating: N433 ( 6, 3) [001239] -c-----N--- t1239 = * GE int REG NA $36c Generating: N435 ( 1, 1) [001241] ----------- t1241 = LCL_VAR long V22 loc18 u:1 x9 REG x9 $3c4 Generating: N437 ( 1, 1) [001242] ----------- t1242 = LCL_VAR int V16 loc12 u:17 x10 REG x10 $361 /--* t1242 int Generating: N439 ( 2, 3) [001243] -c--------- t1243 = * CAST long <- int REG NA $3c8 Generating: N441 ( 1, 2) [001245] -c--------- t1245 = CNS_INT long 1 REG NA $204 /--* t1243 long +--* t1245 long Generating: N443 ( 4, 6) [001246] -c--------- t1246 = * BFIZ long REG NA /--* t1241 long +--* t1246 long Generating: N445 ( 6, 8) [001247] -c--------- t1247 = * LEA(b+(i*1)+0) long REG NA /--* t1247 long Generating: N447 ( 9, 10) [001248] ---XG------ t1248 = * IND ushort REG x1 IN0084: ldrh w1, [x9, w10, SXTW #2] /--* t1248 ushort Generating: N449 ( 9, 10) [003645] DA-XG------ * STORE_LCL_VAR int V174 cse3 x1 REG x1 V174 in reg x1 is becoming live [003645] Live regs: 1FF807E0 {x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF807E2 {x1 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V179 V180} => {V00 V01 V02 V03 V04 V05 V06 V07 V09 V10 V11 V12 V13 V15 V16 V17 V22 V174 V179 V180} Generating: N451 ( 1, 1) [003646] ----------- t3646 = LCL_VAR int V174 cse3 x1 (last use) REG x1 Generating: N453 ( 1, 2) [001249] -c--------- t1249 = CNS_INT int 0 REG NA $c0 /--* t3646 int +--* t1249 int Generating: N455 ( 15, 14) [001250] -c-XG--N--- t1250 = * EQ int REG NA /--* t1239 int +--* t1250 int Generating: N457 ( 22, 18) [003730] Jc-XG--N--- * AND void REG NA Generating: N001 ( 1, 1) [004318] ----------- t4318 = LCL_VAR int V16 loc12 x10 REG x10 /--* t4318 int Generating: N002 ( 2, 2) [004319] ----------- t4319 = * COPY int REG x1 IN0085: mov w1, w10 V16 in reg x10 is becoming dead [004318] Live regs: 1FF807E2 {x1 x5 x6 x7 x8 x9 x10 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} => 1FF803E2 {x1 x5 x6 x7 x8 x9 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28} New debug range: not adjacent V16 in reg x1 is becoming live [004319] ISSUE: #1 /home/alahay01/dotnet/runtime_andchains/src/coreclr/jit/codegencommon.cpp (550) - Assertion failed 'varDsc->IsAlwaysAliveInMemory() || ((regSet.GetMaskVars() & regMask) == 0)' in 'System.Number:NumberToStringFormat(byref,byref,System.ReadOnlySpan`1[ushort],System.Globalization.NumberFormatInfo)' during 'Generate code' (IL size 2048; hash 0x1ee688ab; FullOpts) Loaded 1 Jitted 1 FailedCompile 1 Excluded 0 Missing 0 Total time: 872.663877ms